1 /* Definitions of target machine for GNU compiler. 2 Vitesse IQ2000 processors 3 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009 4 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 3, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 /* Driver configuration. */ 23 24 #undef SWITCH_TAKES_ARG 25 #define SWITCH_TAKES_ARG(CHAR) \ 26 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') 27 28 /* The svr4.h LIB_SPEC with -leval and --*group tacked on */ 29 #undef LIB_SPEC 30 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" 31 32 #undef STARTFILE_SPEC 33 #undef ENDFILE_SPEC 34 35 36 /* Run-time target specifications. */ 37 38 #define TARGET_CPU_CPP_BUILTINS() \ 39 do \ 40 { \ 41 builtin_define ("__iq2000__"); \ 42 builtin_assert ("cpu=iq2000"); \ 43 builtin_assert ("machine=iq2000"); \ 44 } \ 45 while (0) 46 47 /* Macros used in the machine description to test the flags. */ 48 49 #define TARGET_STATS 0 50 51 #define TARGET_DEBUG_MODE 0 52 #define TARGET_DEBUG_A_MODE 0 53 #define TARGET_DEBUG_B_MODE 0 54 #define TARGET_DEBUG_C_MODE 0 55 #define TARGET_DEBUG_D_MODE 0 56 57 #ifndef IQ2000_ISA_DEFAULT 58 #define IQ2000_ISA_DEFAULT 1 59 #endif 60 61 #define IQ2000_VERSION "[1.0]" 62 63 #ifndef MACHINE_TYPE 64 #define MACHINE_TYPE "IQ2000" 65 #endif 66 67 #ifndef TARGET_VERSION_INTERNAL 68 #define TARGET_VERSION_INTERNAL(STREAM) \ 69 fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE) 70 #endif 71 72 #ifndef TARGET_VERSION 73 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr) 74 #endif 75 76 #define OVERRIDE_OPTIONS override_options () 77 78 #define CAN_DEBUG_WITHOUT_FP 79 80 /* Storage Layout. */ 81 82 #define BITS_BIG_ENDIAN 0 83 #define BYTES_BIG_ENDIAN 1 84 #define WORDS_BIG_ENDIAN 1 85 #define LIBGCC2_WORDS_BIG_ENDIAN 1 86 #define BITS_PER_WORD 32 87 #define MAX_BITS_PER_WORD 64 88 #define UNITS_PER_WORD 4 89 #define MIN_UNITS_PER_WORD 4 90 #define POINTER_SIZE 32 91 92 /* Define this macro if it is advisable to hold scalars in registers 93 in a wider mode than that declared by the program. In such cases, 94 the value is constrained to be within the bounds of the declared 95 type, but kept valid in the wider mode. The signedness of the 96 extension may differ from that of the type. 97 98 We promote any value smaller than SImode up to SImode. */ 99 100 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 101 if (GET_MODE_CLASS (MODE) == MODE_INT \ 102 && GET_MODE_SIZE (MODE) < 4) \ 103 (MODE) = SImode; 104 105 #define PARM_BOUNDARY 32 106 107 #define STACK_BOUNDARY 64 108 109 #define FUNCTION_BOUNDARY 32 110 111 #define BIGGEST_ALIGNMENT 64 112 113 #undef DATA_ALIGNMENT 114 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 115 ((((ALIGN) < BITS_PER_WORD) \ 116 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 117 || TREE_CODE (TYPE) == UNION_TYPE \ 118 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 119 120 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 121 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 122 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 123 124 #define EMPTY_FIELD_BOUNDARY 32 125 126 #define STRUCTURE_SIZE_BOUNDARY 8 127 128 #define STRICT_ALIGNMENT 1 129 130 #define PCC_BITFIELD_TYPE_MATTERS 1 131 132 133 /* Layout of Source Language Data Types. */ 134 135 #define INT_TYPE_SIZE 32 136 #define SHORT_TYPE_SIZE 16 137 #define LONG_TYPE_SIZE 32 138 #define LONG_LONG_TYPE_SIZE 64 139 #define CHAR_TYPE_SIZE BITS_PER_UNIT 140 #define FLOAT_TYPE_SIZE 32 141 #define DOUBLE_TYPE_SIZE 64 142 #define LONG_DOUBLE_TYPE_SIZE 64 143 #define DEFAULT_SIGNED_CHAR 1 144 145 146 /* Register Basics. */ 147 148 /* On the IQ2000, we have 32 integer registers. */ 149 #define FIRST_PSEUDO_REGISTER 33 150 151 #define FIXED_REGISTERS \ 152 { \ 153 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1 \ 155 } 156 157 #define CALL_USED_REGISTERS \ 158 { \ 159 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 160 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1 \ 161 } 162 163 164 /* Order of allocation of registers. */ 165 166 #define REG_ALLOC_ORDER \ 167 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 168 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 \ 169 } 170 171 172 /* How Values Fit in Registers. */ 173 174 #define HARD_REGNO_NREGS(REGNO, MODE) \ 175 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 176 177 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 178 ((REGNO_REG_CLASS (REGNO) == GR_REGS) \ 179 ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4 \ 180 : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4) 181 182 #define MODES_TIEABLE_P(MODE1, MODE2) \ 183 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ 184 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 185 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ 186 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 187 188 #define AVOID_CCMODE_COPIES 189 190 191 /* Register Classes. */ 192 193 enum reg_class 194 { 195 NO_REGS, /* No registers in set. */ 196 GR_REGS, /* Integer registers. */ 197 ALL_REGS, /* All registers. */ 198 LIM_REG_CLASSES /* Max value + 1. */ 199 }; 200 201 #define GENERAL_REGS GR_REGS 202 203 #define N_REG_CLASSES (int) LIM_REG_CLASSES 204 205 #define IRA_COVER_CLASSES \ 206 { \ 207 GR_REGS, LIM_REG_CLASSES \ 208 } 209 210 #define REG_CLASS_NAMES \ 211 { \ 212 "NO_REGS", \ 213 "GR_REGS", \ 214 "ALL_REGS" \ 215 } 216 217 #define REG_CLASS_CONTENTS \ 218 { \ 219 { 0x00000000, 0x00000000 }, /* No registers, */ \ 220 { 0xffffffff, 0x00000000 }, /* Integer registers. */ \ 221 { 0xffffffff, 0x00000001 } /* All registers. */ \ 222 } 223 224 #define REGNO_REG_CLASS(REGNO) \ 225 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS) 226 227 #define BASE_REG_CLASS (GR_REGS) 228 229 #define INDEX_REG_CLASS NO_REGS 230 231 #define REG_CLASS_FROM_LETTER(C) \ 232 ((C) == 'd' ? GR_REGS : \ 233 (C) == 'b' ? ALL_REGS : \ 234 (C) == 'y' ? GR_REGS : \ 235 NO_REGS) 236 237 #define REGNO_OK_FOR_INDEX_P(regno) 0 238 239 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 240 ((CLASS) != ALL_REGS \ 241 ? (CLASS) \ 242 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 243 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \ 244 ? (GR_REGS) \ 245 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ 246 || GET_MODE (X) == VOIDmode) \ 247 ? (GR_REGS) \ 248 : (CLASS)))) 249 250 #define SMALL_REGISTER_CLASSES 0 251 252 #define CLASS_MAX_NREGS(CLASS, MODE) \ 253 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 254 255 /* For IQ2000: 256 257 `I' is used for the range of constants an arithmetic insn can 258 actually contain (16-bits signed integers). 259 260 `J' is used for the range which is just zero (i.e., $r0). 261 262 `K' is used for the range of constants a logical insn can actually 263 contain (16-bit zero-extended integers). 264 265 `L' is used for the range of constants that be loaded with lui 266 (i.e., the bottom 16 bits are zero). 267 268 `M' is used for the range of constants that take two words to load 269 (i.e., not matched by `I', `K', and `L'). 270 271 `N' is used for constants 0xffffnnnn or 0xnnnnffff 272 273 `O' is a 5-bit zero-extended integer. */ 274 275 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 276 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \ 277 : (C) == 'J' ? ((VALUE) == 0) \ 278 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \ 279 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \ 280 && (((VALUE) & ~2147483647) == 0 \ 281 || ((VALUE) & ~2147483647) == ~2147483647)) \ 282 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \ 283 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \ 284 && (((VALUE) & 0x0000ffff) != 0 \ 285 || (((VALUE) & ~2147483647) != 0 \ 286 && ((VALUE) & ~2147483647) != ~2147483647))) \ 287 : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff) \ 288 || (((VALUE) & 0xffff0000) == 0xffff0000)) \ 289 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40) \ 290 : 0) 291 292 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 293 ((C) == 'G' \ 294 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) 295 296 /* `R' is for memory references which take 1 word for the instruction. */ 297 298 #define EXTRA_CONSTRAINT(OP,CODE) \ 299 (((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \ 300 : FALSE) 301 302 303 /* Basic Stack Layout. */ 304 305 #define STACK_GROWS_DOWNWARD 306 307 #define FRAME_GROWS_DOWNWARD 0 308 309 #define STARTING_FRAME_OFFSET \ 310 (crtl->outgoing_args_size) 311 312 /* Use the default value zero. */ 313 /* #define STACK_POINTER_OFFSET 0 */ 314 315 #define FIRST_PARM_OFFSET(FNDECL) 0 316 317 /* The return address for the current frame is in r31 if this is a leaf 318 function. Otherwise, it is on the stack. It is at a variable offset 319 from sp/fp/ap, so we define a fake hard register rap which is a 320 pointer to the return address on the stack. This always gets eliminated 321 during reload to be either the frame pointer or the stack pointer plus 322 an offset. */ 323 324 #define RETURN_ADDR_RTX(count, frame) \ 325 (((count) == 0) \ 326 ? (leaf_function_p () \ 327 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \ 328 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \ 329 RETURN_ADDRESS_POINTER_REGNUM))) \ 330 : (rtx) 0) 331 332 /* Before the prologue, RA lives in r31. */ 333 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31) 334 335 336 /* Register That Address the Stack Frame. */ 337 338 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) 339 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1) 340 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 27) 341 #define ARG_POINTER_REGNUM GP_REG_FIRST 342 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM 343 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2) 344 345 346 /* Eliminating the Frame Pointer and the Arg Pointer. */ 347 348 #define ELIMINABLE_REGS \ 349 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 350 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 351 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 352 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 353 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \ 354 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 355 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 356 357 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 358 (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO)) 359 360 /* Passing Function Arguments on the Stack. */ 361 362 /* #define PUSH_ROUNDING(BYTES) 0 */ 363 364 #define ACCUMULATE_OUTGOING_ARGS 1 365 366 #define REG_PARM_STACK_SPACE(FNDECL) 0 367 368 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 369 370 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 371 372 373 /* Function Arguments in Registers. */ 374 375 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 376 function_arg (& CUM, MODE, TYPE, NAMED) 377 378 #define MAX_ARGS_IN_REGISTERS 8 379 380 typedef struct iq2000_args 381 { 382 int gp_reg_found; /* Whether a gp register was found yet. */ 383 unsigned int arg_number; /* Argument number. */ 384 unsigned int arg_words; /* # total words the arguments take. */ 385 unsigned int fp_arg_words; /* # words for FP args (IQ2000_EABI only). */ 386 int last_arg_fp; /* Nonzero if last arg was FP (EABI only). */ 387 int fp_code; /* Mode of FP arguments. */ 388 unsigned int num_adjusts; /* Number of adjustments made. */ 389 /* Adjustments made to args pass in regs. */ 390 struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2]; 391 } CUMULATIVE_ARGS; 392 393 /* Initialize a variable CUM of type CUMULATIVE_ARGS 394 for a call to a function whose data type is FNTYPE. 395 For a library call, FNTYPE is 0. */ 396 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 397 init_cumulative_args (& CUM, FNTYPE, LIBNAME) \ 398 399 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 400 function_arg_advance (& CUM, MODE, TYPE, NAMED) 401 402 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 403 (! BYTES_BIG_ENDIAN \ 404 ? upward \ 405 : (((MODE) == BLKmode \ 406 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ 407 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\ 408 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \ 409 && (GET_MODE_CLASS (MODE) == MODE_INT))) \ 410 ? downward : upward)) 411 412 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 413 (((TYPE) != 0) \ 414 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \ 415 ? PARM_BOUNDARY \ 416 : TYPE_ALIGN(TYPE)) \ 417 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \ 418 ? PARM_BOUNDARY \ 419 : GET_MODE_ALIGNMENT(MODE))) 420 421 #define FUNCTION_ARG_REGNO_P(N) \ 422 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST)) 423 424 425 /* On the IQ2000, R2 and R3 are the only register thus used. */ 426 427 #define FUNCTION_VALUE_REGNO_P(N) iq2000_function_value_regno_p (N) 428 429 430 /* How Large Values are Returned. */ 431 432 #define DEFAULT_PCC_STRUCT_RETURN 0 433 434 /* Function Entry and Exit. */ 435 436 #define EXIT_IGNORE_STACK 1 437 438 439 /* Generating Code for Profiling. */ 440 441 #define FUNCTION_PROFILER(FILE, LABELNO) \ 442 { \ 443 fprintf (FILE, "\t.set\tnoreorder\n"); \ 444 fprintf (FILE, "\t.set\tnoat\n"); \ 445 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \ 446 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \ 447 fprintf (FILE, "\tjal\t_mcount\n"); \ 448 fprintf (FILE, \ 449 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \ 450 "subu", \ 451 reg_names[STACK_POINTER_REGNUM], \ 452 reg_names[STACK_POINTER_REGNUM], \ 453 Pmode == DImode ? 16 : 8); \ 454 fprintf (FILE, "\t.set\treorder\n"); \ 455 fprintf (FILE, "\t.set\tat\n"); \ 456 } 457 458 459 /* Trampolines for Nested Functions. */ 460 461 #define TRAMPOLINE_CODE_SIZE (8*4) 462 #define TRAMPOLINE_SIZE (TRAMPOLINE_CODE_SIZE + 2*GET_MODE_SIZE (Pmode)) 463 #define TRAMPOLINE_ALIGNMENT GET_MODE_ALIGNMENT (Pmode) 464 465 466 /* Addressing Modes. */ 467 468 #define CONSTANT_ADDRESS_P(X) \ 469 ( (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 470 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 471 || (GET_CODE (X) == CONST))) 472 473 #define MAX_REGS_PER_ADDRESS 1 474 475 #define REG_OK_FOR_INDEX_P(X) 0 476 477 #define LEGITIMATE_CONSTANT_P(X) (1) 478 479 480 /* Describing Relative Costs of Operations. */ 481 482 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2 483 484 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ 485 (TO_P ? 2 : 16) 486 487 #define BRANCH_COST(speed_p, predictable_p) 2 488 489 #define SLOW_BYTE_ACCESS 1 490 491 #define NO_FUNCTION_CSE 1 492 493 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \ 494 if (REG_NOTE_KIND (LINK) != 0) \ 495 (COST) = 0; /* Anti or output dependence. */ 496 497 498 /* Dividing the output into sections. */ 499 500 #define TEXT_SECTION_ASM_OP "\t.text" /* Instructions. */ 501 502 #define DATA_SECTION_ASM_OP "\t.data" /* Large data. */ 503 504 505 /* The Overall Framework of an Assembler File. */ 506 507 #define ASM_COMMENT_START " #" 508 509 #define ASM_APP_ON "#APP\n" 510 511 #define ASM_APP_OFF "#NO_APP\n" 512 513 514 /* Output and Generation of Labels. */ 515 516 #undef ASM_GENERATE_INTERNAL_LABEL 517 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 518 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM)) 519 520 #define GLOBAL_ASM_OP "\t.globl\t" 521 522 523 /* Output of Assembler Instructions. */ 524 525 #define REGISTER_NAMES \ 526 { \ 527 "%0", "%1", "%2", "%3", "%4", "%5", "%6", "%7", \ 528 "%8", "%9", "%10", "%11", "%12", "%13", "%14", "%15", \ 529 "%16", "%17", "%18", "%19", "%20", "%21", "%22", "%23", \ 530 "%24", "%25", "%26", "%27", "%28", "%29", "%30", "%31", "%rap" \ 531 }; 532 533 #define ADDITIONAL_REGISTER_NAMES \ 534 { \ 535 { "%0", 0 + GP_REG_FIRST }, \ 536 { "%1", 1 + GP_REG_FIRST }, \ 537 { "%2", 2 + GP_REG_FIRST }, \ 538 { "%3", 3 + GP_REG_FIRST }, \ 539 { "%4", 4 + GP_REG_FIRST }, \ 540 { "%5", 5 + GP_REG_FIRST }, \ 541 { "%6", 6 + GP_REG_FIRST }, \ 542 { "%7", 7 + GP_REG_FIRST }, \ 543 { "%8", 8 + GP_REG_FIRST }, \ 544 { "%9", 9 + GP_REG_FIRST }, \ 545 { "%10", 10 + GP_REG_FIRST }, \ 546 { "%11", 11 + GP_REG_FIRST }, \ 547 { "%12", 12 + GP_REG_FIRST }, \ 548 { "%13", 13 + GP_REG_FIRST }, \ 549 { "%14", 14 + GP_REG_FIRST }, \ 550 { "%15", 15 + GP_REG_FIRST }, \ 551 { "%16", 16 + GP_REG_FIRST }, \ 552 { "%17", 17 + GP_REG_FIRST }, \ 553 { "%18", 18 + GP_REG_FIRST }, \ 554 { "%19", 19 + GP_REG_FIRST }, \ 555 { "%20", 20 + GP_REG_FIRST }, \ 556 { "%21", 21 + GP_REG_FIRST }, \ 557 { "%22", 22 + GP_REG_FIRST }, \ 558 { "%23", 23 + GP_REG_FIRST }, \ 559 { "%24", 24 + GP_REG_FIRST }, \ 560 { "%25", 25 + GP_REG_FIRST }, \ 561 { "%26", 26 + GP_REG_FIRST }, \ 562 { "%27", 27 + GP_REG_FIRST }, \ 563 { "%28", 28 + GP_REG_FIRST }, \ 564 { "%29", 29 + GP_REG_FIRST }, \ 565 { "%30", 27 + GP_REG_FIRST }, \ 566 { "%31", 31 + GP_REG_FIRST }, \ 567 { "%rap", 32 + GP_REG_FIRST }, \ 568 } 569 570 /* Check if the current insn needs a nop in front of it 571 because of load delays, and also update the delay slot statistics. */ 572 573 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 574 final_prescan_insn (INSN, OPVEC, NOPERANDS) 575 576 /* See iq2000.c for the IQ2000 specific codes. */ 577 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 578 579 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) iq2000_print_operand_punct[CODE] 580 581 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 582 583 #define DBR_OUTPUT_SEQEND(STREAM) \ 584 do \ 585 { \ 586 fputs ("\n", STREAM); \ 587 } \ 588 while (0) 589 590 #define LOCAL_LABEL_PREFIX "$" 591 592 #define USER_LABEL_PREFIX "" 593 594 595 /* Output of dispatch tables. */ 596 597 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 598 do \ 599 { \ 600 fprintf (STREAM, "\t%s\t%sL%d\n", \ 601 Pmode == DImode ? ".dword" : ".word", \ 602 LOCAL_LABEL_PREFIX, VALUE); \ 603 } \ 604 while (0) 605 606 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 607 fprintf (STREAM, "\t%s\t%sL%d\n", \ 608 Pmode == DImode ? ".dword" : ".word", \ 609 LOCAL_LABEL_PREFIX, \ 610 VALUE) 611 612 613 /* Assembler Commands for Alignment. */ 614 615 #undef ASM_OUTPUT_SKIP 616 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ 617 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", \ 618 (unsigned HOST_WIDE_INT)(SIZE)) 619 620 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 621 if ((LOG) != 0) \ 622 fprintf (STREAM, "\t.balign %d\n", 1<<(LOG)) 623 624 625 /* Macros Affecting all Debug Formats. */ 626 627 #define DEBUGGER_AUTO_OFFSET(X) \ 628 iq2000_debugger_offset (X, (HOST_WIDE_INT) 0) 629 630 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ 631 iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET) 632 633 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 634 635 #define DWARF2_DEBUGGING_INFO 1 636 637 638 /* Miscellaneous Parameters. */ 639 640 #define CASE_VECTOR_MODE SImode 641 642 #define WORD_REGISTER_OPERATIONS 643 644 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 645 646 #define MOVE_MAX 4 647 648 #define MAX_MOVE_MAX 8 649 650 #define SHIFT_COUNT_TRUNCATED 1 651 652 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 653 654 #define STORE_FLAG_VALUE 1 655 656 #define Pmode SImode 657 658 #define FUNCTION_MODE SImode 659 660 /* Standard GCC variables that we reference. */ 661 662 extern char call_used_regs[]; 663 664 /* IQ2000 external variables defined in iq2000.c. */ 665 666 /* Comparison type. */ 667 enum cmp_type 668 { 669 CMP_SI, /* Compare four byte integers. */ 670 CMP_DI, /* Compare eight byte integers. */ 671 CMP_SF, /* Compare single precision floats. */ 672 CMP_DF, /* Compare double precision floats. */ 673 CMP_MAX /* Max comparison type. */ 674 }; 675 676 /* Types of delay slot. */ 677 enum delay_type 678 { 679 DELAY_NONE, /* No delay slot. */ 680 DELAY_LOAD, /* Load from memory delay. */ 681 DELAY_FCMP /* Delay after doing c.<xx>.{d,s}. */ 682 }; 683 684 /* Which processor to schedule for. */ 685 686 enum processor_type 687 { 688 PROCESSOR_DEFAULT, 689 PROCESSOR_IQ2000, 690 PROCESSOR_IQ10 691 }; 692 693 /* Recast the cpu class to be the cpu attribute. */ 694 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune) 695 696 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16) /* 0xffff0000 */ 697 #define BITMASK_LOWER16 ((unsigned long) 0xffff) /* 0x0000ffff */ 698 699 700 #define GENERATE_BRANCHLIKELY (ISA_HAS_BRANCHLIKELY) 701 702 /* Macros to decide whether certain features are available or not, 703 depending on the instruction set architecture level. */ 704 705 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY 706 707 /* ISA has branch likely instructions. */ 708 #define ISA_HAS_BRANCHLIKELY (iq2000_isa == 1) 709 710 711 #undef ASM_SPEC 712 713 714 /* The mapping from gcc register number to DWARF 2 CFA column number. */ 715 #define DWARF_FRAME_REGNUM(REG) (REG) 716 717 /* The DWARF 2 CFA column which tracks the return address. */ 718 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31) 719 720 /* Describe how we implement __builtin_eh_return. */ 721 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 722 723 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the 724 location used to store the amount to adjust the stack. This is 725 usually a register that is available from end of the function's body 726 to the end of the epilogue. Thus, this cannot be a register used as a 727 temporary by the epilogue. 728 729 This must be an integer register. */ 730 #define EH_RETURN_STACKADJ_REGNO 3 731 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) 732 733 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the 734 location used to store the address the processor should jump to 735 catch exception. This is usually a registers that is available from 736 end of the function's body to the end of the epilogue. Thus, this 737 cannot be a register used as a temporary by the epilogue. 738 739 This must be an address register. */ 740 #define EH_RETURN_HANDLER_REGNO 26 741 #define EH_RETURN_HANDLER_RTX \ 742 gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) 743 744 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ 745 #define DWARF_CIE_DATA_ALIGNMENT 4 746 747 /* For IQ2000, width of a floating point register. */ 748 #define UNITS_PER_FPREG 4 749 750 /* Force right-alignment for small varargs in 32 bit little_endian mode */ 751 752 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN 753 754 /* Internal macros to classify a register number as to whether it's a 755 general purpose register, a floating point register, a 756 multiply/divide register, or a status register. */ 757 758 #define GP_REG_FIRST 0 759 #define GP_REG_LAST 31 760 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 761 762 #define RAP_REG_NUM 32 763 #define AT_REGNUM (GP_REG_FIRST + 1) 764 765 #define GP_REG_P(REGNO) \ 766 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 767 768 /* IQ2000 registers used in prologue/epilogue code when the stack frame 769 is larger than 32K bytes. These registers must come from the 770 scratch register set, and not used for passing and returning 771 arguments and any other information used in the calling sequence. */ 772 773 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12) 774 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13) 775 776 /* This macro is used later on in the file. */ 777 #define GR_REG_CLASS_P(CLASS) \ 778 ((CLASS) == GR_REGS) 779 780 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) 781 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000) 782 783 /* Certain machines have the property that some registers cannot be 784 copied to some other registers without using memory. Define this 785 macro on those machines to be a C expression that is nonzero if 786 objects of mode MODE in registers of CLASS1 can only be copied to 787 registers of class CLASS2 by storing a register of CLASS1 into 788 memory and loading that memory location into a register of CLASS2. 789 790 Do not define this macro if its value would always be zero. */ 791 792 /* Return the maximum number of consecutive registers 793 needed to represent mode MODE in a register of class CLASS. */ 794 795 #define CLASS_UNITS(mode, size) \ 796 ((GET_MODE_SIZE (mode) + (size) - 1) / (size)) 797 798 /* If defined, gives a class of registers that cannot be used as the 799 operand of a SUBREG that changes the mode of the object illegally. */ 800 801 #define CLASS_CANNOT_CHANGE_MODE 0 802 803 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ 804 805 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ 806 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) 807 808 /* Make sure 4 words are always allocated on the stack. */ 809 810 #ifndef STACK_ARGS_ADJUST 811 #define STACK_ARGS_ADJUST(SIZE) \ 812 { \ 813 if (SIZE.constant < 4 * UNITS_PER_WORD) \ 814 SIZE.constant = 4 * UNITS_PER_WORD; \ 815 } 816 #endif 817 818 819 /* Symbolic macros for the registers used to return integer and floating 820 point values. */ 821 822 #define GP_RETURN (GP_REG_FIRST + 2) 823 824 /* Symbolic macros for the first/last argument registers. */ 825 826 #define GP_ARG_FIRST (GP_REG_FIRST + 4) 827 #define GP_ARG_LAST (GP_REG_FIRST + 11) 828 829 #define MAX_ARGS_IN_REGISTERS 8 830 831 832 /* Tell prologue and epilogue if register REGNO should be saved / restored. */ 833 834 #define MUST_SAVE_REGISTER(regno) \ 835 ((df_regs_ever_live_p (regno) && !call_used_regs[regno]) \ 836 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ 837 || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31))) 838 839 /* ALIGN FRAMES on double word boundaries */ 840 #ifndef IQ2000_STACK_ALIGN 841 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7) 842 #endif 843 844 845 /* These assume that REGNO is a hard or pseudo reg number. 846 They give nonzero only if REGNO is a hard reg of the suitable class 847 or a pseudo reg currently allocated to a suitable hard reg. 848 These definitions are NOT overridden anywhere. */ 849 850 #define BASE_REG_P(regno, mode) \ 851 (GP_REG_P (regno)) 852 853 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \ 854 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \ 855 (mode)) 856 857 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \ 858 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode)))) 859 860 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \ 861 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode)) 862 863 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 864 and check its validity for a certain class. 865 We have two alternate definitions for each of them. 866 The usual definition accepts all pseudo regs; the other rejects them all. 867 The symbol REG_OK_STRICT causes the latter definition to be used. 868 869 Most source files want to accept pseudo regs in the hope that 870 they will get allocated to the class that the insn wants them to be in. 871 Some source files that are used after register allocation 872 need to be strict. */ 873 874 #ifndef REG_OK_STRICT 875 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 876 iq2000_reg_mode_ok_for_base_p (X, MODE, 0) 877 #else 878 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 879 iq2000_reg_mode_ok_for_base_p (X, MODE, 1) 880 #endif 881 882 #if 1 883 #define GO_PRINTF(x) fprintf (stderr, (x)) 884 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y)) 885 #define GO_DEBUG_RTX(x) debug_rtx (x) 886 887 #else 888 #define GO_PRINTF(x) 889 #define GO_PRINTF2(x,y) 890 #define GO_DEBUG_RTX(x) 891 #endif 892 893 /* If defined, modifies the length assigned to instruction INSN as a 894 function of the context in which it is used. LENGTH is an lvalue 895 that contains the initially computed length of the insn and should 896 be updated with the correct length of the insn. */ 897 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 898 ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH))) 899 900 901 902 903 /* How to tell the debugger about changes of source files. */ 904 905 #ifndef SET_FILE_NUMBER 906 #define SET_FILE_NUMBER() ++ num_source_filenames 907 #endif 908 909 /* This is how to output a note the debugger telling it the line number 910 to which the following sequence of instructions corresponds. */ 911 912 #ifndef LABEL_AFTER_LOC 913 #define LABEL_AFTER_LOC(STREAM) 914 #endif 915 916 917 /* Default to -G 8 */ 918 #ifndef IQ2000_DEFAULT_GVALUE 919 #define IQ2000_DEFAULT_GVALUE 8 920 #endif 921 922 #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small data. */ 923 924 925 /* List of all IQ2000 punctuation characters used by print_operand. */ 926 extern char iq2000_print_operand_punct[256]; 927 928 /* The target cpu for optimization and scheduling. */ 929 extern enum processor_type iq2000_tune; 930 931 /* Which instruction set architecture to use. */ 932 extern int iq2000_isa; 933 934 enum iq2000_builtins 935 { 936 IQ2000_BUILTIN_ADO16, 937 IQ2000_BUILTIN_CFC0, 938 IQ2000_BUILTIN_CFC1, 939 IQ2000_BUILTIN_CFC2, 940 IQ2000_BUILTIN_CFC3, 941 IQ2000_BUILTIN_CHKHDR, 942 IQ2000_BUILTIN_CTC0, 943 IQ2000_BUILTIN_CTC1, 944 IQ2000_BUILTIN_CTC2, 945 IQ2000_BUILTIN_CTC3, 946 IQ2000_BUILTIN_LU, 947 IQ2000_BUILTIN_LUC32L, 948 IQ2000_BUILTIN_LUC64, 949 IQ2000_BUILTIN_LUC64L, 950 IQ2000_BUILTIN_LUK, 951 IQ2000_BUILTIN_LULCK, 952 IQ2000_BUILTIN_LUM32, 953 IQ2000_BUILTIN_LUM32L, 954 IQ2000_BUILTIN_LUM64, 955 IQ2000_BUILTIN_LUM64L, 956 IQ2000_BUILTIN_LUR, 957 IQ2000_BUILTIN_LURL, 958 IQ2000_BUILTIN_MFC0, 959 IQ2000_BUILTIN_MFC1, 960 IQ2000_BUILTIN_MFC2, 961 IQ2000_BUILTIN_MFC3, 962 IQ2000_BUILTIN_MRGB, 963 IQ2000_BUILTIN_MTC0, 964 IQ2000_BUILTIN_MTC1, 965 IQ2000_BUILTIN_MTC2, 966 IQ2000_BUILTIN_MTC3, 967 IQ2000_BUILTIN_PKRL, 968 IQ2000_BUILTIN_RAM, 969 IQ2000_BUILTIN_RB, 970 IQ2000_BUILTIN_RX, 971 IQ2000_BUILTIN_SRRD, 972 IQ2000_BUILTIN_SRRDL, 973 IQ2000_BUILTIN_SRULC, 974 IQ2000_BUILTIN_SRULCK, 975 IQ2000_BUILTIN_SRWR, 976 IQ2000_BUILTIN_SRWRU, 977 IQ2000_BUILTIN_TRAPQF, 978 IQ2000_BUILTIN_TRAPQFL, 979 IQ2000_BUILTIN_TRAPQN, 980 IQ2000_BUILTIN_TRAPQNE, 981 IQ2000_BUILTIN_TRAPRE, 982 IQ2000_BUILTIN_TRAPREL, 983 IQ2000_BUILTIN_WB, 984 IQ2000_BUILTIN_WBR, 985 IQ2000_BUILTIN_WBU, 986 IQ2000_BUILTIN_WX, 987 IQ2000_BUILTIN_SYSCALL 988 }; 989