1 /* Definitions of target machine GNU compiler. IA-64 version. 2 Copyright (C) 1999-2015 Free Software Foundation, Inc. 3 Contributed by James E. Wilson <wilson@cygnus.com> and 4 David Mosberger <davidm@hpl.hp.com>. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 /* ??? Look at ABI group documents for list of preprocessor macros and 23 other features required for ABI compliance. */ 24 25 /* ??? Functions containing a non-local goto target save many registers. Why? 26 See for instance execute/920428-2.c. */ 27 28 29 /* Run-time target specifications */ 30 31 /* Target CPU builtins. */ 32 #define TARGET_CPU_CPP_BUILTINS() \ 33 do { \ 34 builtin_assert("cpu=ia64"); \ 35 builtin_assert("machine=ia64"); \ 36 builtin_define("__ia64"); \ 37 builtin_define("__ia64__"); \ 38 builtin_define("__itanium__"); \ 39 if (TARGET_BIG_ENDIAN) \ 40 builtin_define("__BIG_ENDIAN__"); \ 41 } while (0) 42 43 #ifndef SUBTARGET_EXTRA_SPECS 44 #define SUBTARGET_EXTRA_SPECS 45 #endif 46 47 #define EXTRA_SPECS \ 48 { "asm_extra", ASM_EXTRA_SPEC }, \ 49 SUBTARGET_EXTRA_SPECS 50 51 #define CC1_SPEC "%(cc1_cpu) " 52 53 #define ASM_EXTRA_SPEC "" 54 55 /* Variables which are this size or smaller are put in the sdata/sbss 56 sections. */ 57 extern unsigned int ia64_section_threshold; 58 59 /* If the assembler supports thread-local storage, assume that the 60 system does as well. If a particular target system has an 61 assembler that supports TLS -- but the rest of the system does not 62 support TLS -- that system should explicit define TARGET_HAVE_TLS 63 to false in its own configuration file. */ 64 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS) 65 #define TARGET_HAVE_TLS true 66 #endif 67 68 #define TARGET_TLS14 (ia64_tls_size == 14) 69 #define TARGET_TLS22 (ia64_tls_size == 22) 70 #define TARGET_TLS64 (ia64_tls_size == 64) 71 72 #define TARGET_HPUX 0 73 #define TARGET_HPUX_LD 0 74 75 #define TARGET_ABI_OPEN_VMS 0 76 77 #ifndef TARGET_ILP32 78 #define TARGET_ILP32 0 79 #endif 80 81 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS 82 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0 83 #endif 84 85 /* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and 86 TARGET_INLINE_SQRT. */ 87 88 enum ia64_inline_type 89 { 90 INL_NO = 0, 91 INL_MIN_LAT = 1, 92 INL_MAX_THR = 2 93 }; 94 95 /* Default target_flags if no switches are specified */ 96 97 #ifndef TARGET_DEFAULT 98 #define TARGET_DEFAULT (MASK_DWARF2_ASM) 99 #endif 100 101 #ifndef TARGET_CPU_DEFAULT 102 #define TARGET_CPU_DEFAULT 0 103 #endif 104 105 /* Driver configuration */ 106 107 /* A C string constant that tells the GCC driver program options to pass to 108 `cc1'. It can also specify how to translate options you give to GCC into 109 options for GCC to pass to the `cc1'. */ 110 111 #undef CC1_SPEC 112 #define CC1_SPEC "%{G*}" 113 114 /* A C string constant that tells the GCC driver program options to pass to 115 `cc1plus'. It can also specify how to translate options you give to GCC 116 into options for GCC to pass to the `cc1plus'. */ 117 118 /* #define CC1PLUS_SPEC "" */ 119 120 /* Storage Layout */ 121 122 /* Define this macro to have the value 1 if the most significant bit in a byte 123 has the lowest number; otherwise define it to have the value zero. */ 124 125 #define BITS_BIG_ENDIAN 0 126 127 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 128 129 /* Define this macro to have the value 1 if, in a multiword object, the most 130 significant word has the lowest number. */ 131 132 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 133 134 #define UNITS_PER_WORD 8 135 136 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 137 138 /* A C expression whose value is zero if pointers that need to be extended 139 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if 140 they are zero-extended and negative one if there is a ptr_extend operation. 141 142 You need not define this macro if the `POINTER_SIZE' is equal to the width 143 of `Pmode'. */ 144 /* Need this for 32-bit pointers, see hpux.h for setting it. */ 145 /* #define POINTERS_EXTEND_UNSIGNED */ 146 147 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and 148 which has the specified mode and signedness is to be stored in a register. 149 This macro is only called when TYPE is a scalar type. */ 150 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 151 do \ 152 { \ 153 if (GET_MODE_CLASS (MODE) == MODE_INT \ 154 && GET_MODE_SIZE (MODE) < 4) \ 155 (MODE) = SImode; \ 156 } \ 157 while (0) 158 159 #define PARM_BOUNDARY 64 160 161 /* Define this macro if you wish to preserve a certain alignment for the stack 162 pointer. The definition is a C expression for the desired alignment 163 (measured in bits). */ 164 165 #define STACK_BOUNDARY 128 166 167 /* Align frames on double word boundaries */ 168 #ifndef IA64_STACK_ALIGN 169 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15) 170 #endif 171 172 #define FUNCTION_BOUNDARY 128 173 174 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word 175 128-bit integers all require 128-bit alignment. */ 176 #define BIGGEST_ALIGNMENT 128 177 178 /* If defined, a C expression to compute the alignment for a static variable. 179 TYPE is the data type, and ALIGN is the alignment that the object 180 would ordinarily have. The value of this macro is used instead of that 181 alignment to align the object. */ 182 183 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 184 (TREE_CODE (TYPE) == ARRAY_TYPE \ 185 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 186 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 187 188 /* If defined, a C expression to compute the alignment given to a constant that 189 is being placed in memory. CONSTANT is the constant and ALIGN is the 190 alignment that the object would ordinarily have. The value of this macro is 191 used instead of that alignment to align the object. */ 192 193 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 194 (TREE_CODE (EXP) == STRING_CST \ 195 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 196 197 #define STRICT_ALIGNMENT 1 198 199 /* Define this if you wish to imitate the way many other C compilers handle 200 alignment of bitfields and the structures that contain them. 201 The behavior is that the type written for a bit-field (`int', `short', or 202 other integer type) imposes an alignment for the entire structure, as if the 203 structure really did contain an ordinary field of that type. In addition, 204 the bit-field is placed within the structure so that it would fit within such 205 a field, not crossing a boundary for it. */ 206 #define PCC_BITFIELD_TYPE_MATTERS 1 207 208 /* An integer expression for the size in bits of the largest integer machine 209 mode that should actually be used. */ 210 211 /* Allow pairs of registers to be used, which is the intent of the default. */ 212 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 213 214 /* By default, the C++ compiler will use function addresses in the 215 vtable entries. Setting this nonzero tells the compiler to use 216 function descriptors instead. The value of this macro says how 217 many words wide the descriptor is (normally 2). It is assumed 218 that the address of a function descriptor may be treated as a 219 pointer to a function. 220 221 For reasons known only to HP, the vtable entries (as opposed to 222 normal function descriptors) are 16 bytes wide in 32-bit mode as 223 well, even though the 3rd and 4th words are unused. */ 224 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2) 225 226 /* Due to silliness in the HPUX linker, vtable entries must be 227 8-byte aligned even in 32-bit mode. Rather than create multiple 228 ABIs, force this restriction on everyone else too. */ 229 #define TARGET_VTABLE_ENTRY_ALIGN 64 230 231 /* Due to the above, we need extra padding for the data entries below 0 232 to retain the alignment of the descriptors. */ 233 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1) 234 235 /* Layout of Source Language Data Types */ 236 237 #define INT_TYPE_SIZE 32 238 239 #define SHORT_TYPE_SIZE 16 240 241 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 242 243 #define LONG_LONG_TYPE_SIZE 64 244 245 #define FLOAT_TYPE_SIZE 32 246 247 #define DOUBLE_TYPE_SIZE 64 248 249 /* long double is XFmode normally, and TFmode for HPUX. It should be 250 TFmode for VMS as well but we only support up to DFmode now. */ 251 #define LONG_DOUBLE_TYPE_SIZE \ 252 (TARGET_HPUX ? 128 \ 253 : TARGET_ABI_OPEN_VMS ? 64 \ 254 : 80) 255 256 257 #define DEFAULT_SIGNED_CHAR 1 258 259 /* A C expression for a string describing the name of the data type to use for 260 size values. The typedef name `size_t' is defined using the contents of the 261 string. */ 262 /* ??? Needs to be defined for P64 code. */ 263 /* #define SIZE_TYPE */ 264 265 /* A C expression for a string describing the name of the data type to use for 266 the result of subtracting two pointers. The typedef name `ptrdiff_t' is 267 defined using the contents of the string. See `SIZE_TYPE' above for more 268 information. */ 269 /* ??? Needs to be defined for P64 code. */ 270 /* #define PTRDIFF_TYPE */ 271 272 /* A C expression for a string describing the name of the data type to use for 273 wide characters. The typedef name `wchar_t' is defined using the contents 274 of the string. See `SIZE_TYPE' above for more information. */ 275 /* #define WCHAR_TYPE */ 276 277 /* A C expression for the size in bits of the data type for wide characters. 278 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */ 279 /* #define WCHAR_TYPE_SIZE */ 280 281 282 /* Register Basics */ 283 284 /* Number of hardware registers known to the compiler. 285 We have 128 general registers, 128 floating point registers, 286 64 predicate registers, 8 branch registers, one frame pointer, 287 and several "application" registers. */ 288 289 #define FIRST_PSEUDO_REGISTER 334 290 291 /* Ranges for the various kinds of registers. */ 292 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3) 293 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127) 294 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255) 295 #define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159) 296 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319) 297 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327) 298 #define GENERAL_REGNO_P(REGNO) \ 299 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM) 300 301 #define GR_REG(REGNO) ((REGNO) + 0) 302 #define FR_REG(REGNO) ((REGNO) + 128) 303 #define PR_REG(REGNO) ((REGNO) + 256) 304 #define BR_REG(REGNO) ((REGNO) + 320) 305 #define OUT_REG(REGNO) ((REGNO) + 120) 306 #define IN_REG(REGNO) ((REGNO) + 112) 307 #define LOC_REG(REGNO) ((REGNO) + 32) 308 309 #define AR_CCV_REGNUM 329 310 #define AR_UNAT_REGNUM 330 311 #define AR_PFS_REGNUM 331 312 #define AR_LC_REGNUM 332 313 #define AR_EC_REGNUM 333 314 315 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7)) 316 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79)) 317 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7)) 318 319 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \ 320 || (REGNO) == AR_UNAT_REGNUM) 321 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \ 322 && (REGNO) < FIRST_PSEUDO_REGISTER) 323 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \ 324 && (REGNO) < FIRST_PSEUDO_REGISTER) 325 326 327 /* ??? Don't really need two sets of macros. I like this one better because 328 it is less typing. */ 329 #define R_GR(REGNO) GR_REG (REGNO) 330 #define R_FR(REGNO) FR_REG (REGNO) 331 #define R_PR(REGNO) PR_REG (REGNO) 332 #define R_BR(REGNO) BR_REG (REGNO) 333 334 /* An initializer that says which registers are used for fixed purposes all 335 throughout the compiled code and are therefore not available for general 336 allocation. 337 338 r0: constant 0 339 r1: global pointer (gp) 340 r12: stack pointer (sp) 341 r13: thread pointer (tp) 342 f0: constant 0.0 343 f1: constant 1.0 344 p0: constant true 345 fp: eliminable frame pointer */ 346 347 /* The last 16 stacked regs are reserved for the 8 input and 8 output 348 registers. */ 349 350 #define FIXED_REGISTERS \ 351 { /* General registers. */ \ 352 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ 353 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 354 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 355 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 356 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 357 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 358 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 359 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 360 /* Floating-point registers. */ \ 361 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 363 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 364 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 365 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 366 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 367 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 368 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 369 /* Predicate registers. */ \ 370 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 371 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 372 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 373 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 374 /* Branch registers. */ \ 375 0, 0, 0, 0, 0, 0, 0, 0, \ 376 /*FP CCV UNAT PFS LC EC */ \ 377 1, 1, 1, 1, 1, 1 \ 378 } 379 380 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered 381 (in general) by function calls as well as for fixed registers. This 382 macro therefore identifies the registers that are not available for 383 general allocation of values that must live across function calls. */ 384 385 #define CALL_USED_REGISTERS \ 386 { /* General registers. */ \ 387 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 388 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 389 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 390 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 391 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 392 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 393 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 394 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 395 /* Floating-point registers. */ \ 396 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 397 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 398 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 399 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 400 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 401 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 402 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 403 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 404 /* Predicate registers. */ \ 405 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 406 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 407 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 409 /* Branch registers. */ \ 410 1, 0, 0, 0, 0, 0, 1, 1, \ 411 /*FP CCV UNAT PFS LC EC */ \ 412 1, 1, 1, 1, 1, 1 \ 413 } 414 415 /* Like `CALL_USED_REGISTERS' but used to overcome a historical 416 problem which makes CALL_USED_REGISTERS *always* include 417 all the FIXED_REGISTERS. Until this problem has been 418 resolved this macro can be used to overcome this situation. 419 In particular, block_propagate() requires this list 420 be accurate, or we can remove registers which should be live. 421 This macro is used in regs_invalidated_by_call. */ 422 423 #define CALL_REALLY_USED_REGISTERS \ 424 { /* General registers. */ \ 425 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, \ 426 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 427 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 428 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 429 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 430 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 431 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 432 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 433 /* Floating-point registers. */ \ 434 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 436 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 437 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 438 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 439 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 440 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 441 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 442 /* Predicate registers. */ \ 443 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 444 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 446 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 447 /* Branch registers. */ \ 448 1, 0, 0, 0, 0, 0, 1, 1, \ 449 /*FP CCV UNAT PFS LC EC */ \ 450 0, 1, 0, 1, 0, 0 \ 451 } 452 453 454 /* Define this macro if the target machine has register windows. This C 455 expression returns the register number as seen by the called function 456 corresponding to the register number OUT as seen by the calling function. 457 Return OUT if register number OUT is not an outbound register. */ 458 459 #define INCOMING_REGNO(OUT) \ 460 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT)) 461 462 /* Define this macro if the target machine has register windows. This C 463 expression returns the register number as seen by the calling function 464 corresponding to the register number IN as seen by the called function. 465 Return IN if register number IN is not an inbound register. */ 466 467 #define OUTGOING_REGNO(IN) \ 468 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN)) 469 470 /* Define this macro if the target machine has register windows. This 471 C expression returns true if the register is call-saved but is in the 472 register window. */ 473 474 #define LOCAL_REGNO(REGNO) \ 475 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO)) 476 477 /* We define CCImode in ia64-modes.def so we need a selector. */ 478 479 #define SELECT_CC_MODE(OP,X,Y) CCmode 480 481 /* Order of allocation of registers */ 482 483 /* If defined, an initializer for a vector of integers, containing the numbers 484 of hard registers in the order in which GCC should prefer to use them 485 (from most preferred to least). 486 487 If this macro is not defined, registers are used lowest numbered first (all 488 else being equal). 489 490 One use of this macro is on machines where the highest numbered registers 491 must always be saved and the save-multiple-registers instruction supports 492 only sequences of consecutive registers. On such machines, define 493 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered 494 allocatable register first. */ 495 496 /* ??? Should the GR return value registers come before or after the rest 497 of the caller-save GRs? */ 498 499 #define REG_ALLOC_ORDER \ 500 { \ 501 /* Caller-saved general registers. */ \ 502 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \ 503 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \ 504 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \ 505 R_GR (30), R_GR (31), \ 506 /* Output registers. */ \ 507 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \ 508 R_GR (126), R_GR (127), \ 509 /* Caller-saved general registers, also used for return values. */ \ 510 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \ 511 /* addl caller-saved general registers. */ \ 512 R_GR (2), R_GR (3), \ 513 /* Caller-saved FP registers. */ \ 514 R_FR (6), R_FR (7), \ 515 /* Caller-saved FP registers, used for parameters and return values. */ \ 516 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \ 517 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \ 518 /* Rotating caller-saved FP registers. */ \ 519 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \ 520 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \ 521 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \ 522 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \ 523 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \ 524 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \ 525 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \ 526 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \ 527 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \ 528 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \ 529 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \ 530 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \ 531 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \ 532 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \ 533 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \ 534 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \ 535 R_FR (126), R_FR (127), \ 536 /* Caller-saved predicate registers. */ \ 537 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \ 538 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \ 539 /* Rotating caller-saved predicate registers. */ \ 540 R_PR (16), R_PR (17), \ 541 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \ 542 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \ 543 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \ 544 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \ 545 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \ 546 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \ 547 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \ 548 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \ 549 /* Caller-saved branch registers. */ \ 550 R_BR (6), R_BR (7), \ 551 \ 552 /* Stacked callee-saved general registers. */ \ 553 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \ 554 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \ 555 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \ 556 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \ 557 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \ 558 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \ 559 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \ 560 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \ 561 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \ 562 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \ 563 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \ 564 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \ 565 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \ 566 R_GR (108), \ 567 /* Input registers. */ \ 568 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \ 569 R_GR (118), R_GR (119), \ 570 /* Callee-saved general registers. */ \ 571 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \ 572 /* Callee-saved FP registers. */ \ 573 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \ 574 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \ 575 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \ 576 R_FR (30), R_FR (31), \ 577 /* Callee-saved predicate registers. */ \ 578 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \ 579 /* Callee-saved branch registers. */ \ 580 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \ 581 \ 582 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \ 583 R_GR (109), R_GR (110), R_GR (111), \ 584 \ 585 /* Special general registers. */ \ 586 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \ 587 /* Special FP registers. */ \ 588 R_FR (0), R_FR (1), \ 589 /* Special predicate registers. */ \ 590 R_PR (0), \ 591 /* Special branch registers. */ \ 592 R_BR (0), \ 593 /* Other fixed registers. */ \ 594 FRAME_POINTER_REGNUM, \ 595 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \ 596 AR_EC_REGNUM \ 597 } 598 599 /* How Values Fit in Registers */ 600 601 /* A C expression for the number of consecutive hard registers, starting at 602 register number REGNO, required to hold a value of mode MODE. */ 603 604 /* ??? We say that BImode PR values require two registers. This allows us to 605 easily store the normal and inverted values. We use CCImode to indicate 606 a single predicate register. */ 607 608 #define HARD_REGNO_NREGS(REGNO, MODE) \ 609 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \ 610 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \ 611 : (PR_REGNO_P (REGNO) || GR_REGNO_P (REGNO)) && (MODE) == CCImode ? 1\ 612 : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \ 613 : FR_REGNO_P (REGNO) && (MODE) == RFmode ? 1 \ 614 : FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \ 615 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 616 617 /* A C expression that is nonzero if it is permissible to store a value of mode 618 MODE in hard register number REGNO (or in several registers starting with 619 that one). */ 620 621 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 622 (FR_REGNO_P (REGNO) ? \ 623 GET_MODE_CLASS (MODE) != MODE_CC && \ 624 (MODE) != BImode && \ 625 (MODE) != TFmode \ 626 : PR_REGNO_P (REGNO) ? \ 627 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \ 628 : GR_REGNO_P (REGNO) ? \ 629 (MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \ 630 : AR_REGNO_P (REGNO) ? (MODE) == DImode \ 631 : BR_REGNO_P (REGNO) ? (MODE) == DImode \ 632 : 0) 633 634 /* A C expression that is nonzero if it is desirable to choose register 635 allocation so as to avoid move instructions between a value of mode MODE1 636 and a value of mode MODE2. 637 638 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are 639 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be 640 zero. */ 641 /* Don't tie integer and FP modes, as that causes us to get integer registers 642 allocated for FP instructions. XFmode only supported in FP registers so 643 we can't tie it with any other modes. */ 644 #define MODES_TIEABLE_P(MODE1, MODE2) \ 645 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 646 && ((((MODE1) == XFmode) || ((MODE1) == XCmode) || ((MODE1) == RFmode)) \ 647 == (((MODE2) == XFmode) || ((MODE2) == XCmode) || ((MODE2) == RFmode))) \ 648 && (((MODE1) == BImode) == ((MODE2) == BImode))) 649 650 /* Specify the modes required to caller save a given hard regno. 651 We need to ensure floating pt regs are not saved as DImode. */ 652 653 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 654 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode \ 655 : choose_hard_reg_mode ((REGNO), (NREGS), false)) 656 657 /* Handling Leaf Functions */ 658 659 /* A C initializer for a vector, indexed by hard register number, which 660 contains 1 for a register that is allowable in a candidate for leaf function 661 treatment. */ 662 /* ??? This might be useful. */ 663 /* #define LEAF_REGISTERS */ 664 665 /* A C expression whose value is the register number to which REGNO should be 666 renumbered, when a function is treated as a leaf function. */ 667 /* ??? This might be useful. */ 668 /* #define LEAF_REG_REMAP(REGNO) */ 669 670 671 /* Register Classes */ 672 673 /* An enumeral type that must be defined with all the register class names as 674 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last 675 register class, followed by one more enumeral value, `LIM_REG_CLASSES', 676 which is not a register class but rather tells how many classes there 677 are. */ 678 /* ??? When compiling without optimization, it is possible for the only use of 679 a pseudo to be a parameter load from the stack with a REG_EQUIV note. 680 Regclass handles this case specially and does not assign any costs to the 681 pseudo. The pseudo then ends up using the last class before ALL_REGS. 682 Thus we must not let either PR_REGS or BR_REGS be the last class. The 683 testcase for this is gcc.c-torture/execute/va-arg-7.c. */ 684 enum reg_class 685 { 686 NO_REGS, 687 PR_REGS, 688 BR_REGS, 689 AR_M_REGS, 690 AR_I_REGS, 691 ADDL_REGS, 692 GR_REGS, 693 FP_REGS, 694 FR_REGS, 695 GR_AND_BR_REGS, 696 GR_AND_FR_REGS, 697 ALL_REGS, 698 LIM_REG_CLASSES 699 }; 700 701 #define GENERAL_REGS GR_REGS 702 703 /* The number of distinct register classes. */ 704 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 705 706 /* An initializer containing the names of the register classes as C string 707 constants. These names are used in writing some of the debugging dumps. */ 708 #define REG_CLASS_NAMES \ 709 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \ 710 "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \ 711 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" } 712 713 /* An initializer containing the contents of the register classes, as integers 714 which are bit masks. The Nth integer specifies the contents of class N. 715 The way the integer MASK is interpreted is that register R is in the class 716 if `MASK & (1 << R)' is 1. */ 717 #define REG_CLASS_CONTENTS \ 718 { \ 719 /* NO_REGS. */ \ 720 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 721 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 722 0x00000000, 0x00000000, 0x0000 }, \ 723 /* PR_REGS. */ \ 724 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 725 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 726 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \ 727 /* BR_REGS. */ \ 728 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 729 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 730 0x00000000, 0x00000000, 0x00FF }, \ 731 /* AR_M_REGS. */ \ 732 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 733 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 734 0x00000000, 0x00000000, 0x0600 }, \ 735 /* AR_I_REGS. */ \ 736 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 737 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 738 0x00000000, 0x00000000, 0x3800 }, \ 739 /* ADDL_REGS. */ \ 740 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \ 741 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 742 0x00000000, 0x00000000, 0x0000 }, \ 743 /* GR_REGS. */ \ 744 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 745 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 746 0x00000000, 0x00000000, 0x0100 }, \ 747 /* FP_REGS. */ \ 748 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 749 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, \ 750 0x00000000, 0x00000000, 0x0000 }, \ 751 /* FR_REGS. */ \ 752 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 753 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 754 0x00000000, 0x00000000, 0x0000 }, \ 755 /* GR_AND_BR_REGS. */ \ 756 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 757 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 758 0x00000000, 0x00000000, 0x01FF }, \ 759 /* GR_AND_FR_REGS. */ \ 760 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 761 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 762 0x00000000, 0x00000000, 0x0100 }, \ 763 /* ALL_REGS. */ \ 764 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 765 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 766 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \ 767 } 768 769 /* A C expression whose value is a register class containing hard register 770 REGNO. In general there is more than one such class; choose a class which 771 is "minimal", meaning that no smaller class also contains the register. */ 772 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which 773 may call here with private (invalid) register numbers, such as 774 REG_VOLATILE. */ 775 #define REGNO_REG_CLASS(REGNO) \ 776 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \ 777 : GENERAL_REGNO_P (REGNO) ? GR_REGS \ 778 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \ 779 && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \ 780 : PR_REGNO_P (REGNO) ? PR_REGS \ 781 : BR_REGNO_P (REGNO) ? BR_REGS \ 782 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \ 783 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \ 784 : NO_REGS) 785 786 /* A macro whose definition is the name of the class to which a valid base 787 register must belong. A base register is one used in an address which is 788 the register value plus a displacement. */ 789 #define BASE_REG_CLASS GENERAL_REGS 790 791 /* A macro whose definition is the name of the class to which a valid index 792 register must belong. An index register is one used in an address where its 793 value is either multiplied by a scale factor or added to another register 794 (as well as added to a displacement). This is needed for POST_MODIFY. */ 795 #define INDEX_REG_CLASS GENERAL_REGS 796 797 /* A C expression which is nonzero if register number NUM is suitable for use 798 as a base register in operand addresses. It may be either a suitable hard 799 register or a pseudo register that has been allocated such a hard reg. */ 800 #define REGNO_OK_FOR_BASE_P(REGNO) \ 801 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO])) 802 803 /* A C expression which is nonzero if register number NUM is suitable for use 804 as an index register in operand addresses. It may be either a suitable hard 805 register or a pseudo register that has been allocated such a hard reg. 806 This is needed for POST_MODIFY. */ 807 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) 808 809 /* You should define this macro to indicate to the reload phase that it may 810 need to allocate at least one register for a reload in addition to the 811 register to contain the data. Specifically, if copying X to a register 812 CLASS in MODE requires an intermediate register, you should define this 813 to return the largest register class all of whose registers can be used 814 as intermediate registers or scratch registers. */ 815 816 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 817 ia64_secondary_reload_class (CLASS, MODE, X) 818 819 /* Certain machines have the property that some registers cannot be copied to 820 some other registers without using memory. Define this macro on those 821 machines to be a C expression that is nonzero if objects of mode M in 822 registers of CLASS1 can only be copied to registers of class CLASS2 by 823 storing a register of CLASS1 into memory and loading that memory location 824 into a register of CLASS2. */ 825 826 #if 0 827 /* ??? May need this, but since we've disallowed XFmode in GR_REGS, 828 I'm not quite sure how it could be invoked. The normal problems 829 with unions should be solved with the addressof fiddling done by 830 movxf and friends. */ 831 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 832 (((MODE) == XFmode || (MODE) == XCmode) \ 833 && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \ 834 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS))) 835 #endif 836 837 /* A C expression for the maximum number of consecutive registers of 838 class CLASS needed to hold a value of mode MODE. 839 This is closely related to the macro `HARD_REGNO_NREGS'. */ 840 841 #define CLASS_MAX_NREGS(CLASS, MODE) \ 842 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \ 843 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \ 844 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \ 845 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \ 846 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 847 848 /* In BR regs, we can't change the DImode at all. 849 In FP regs, we can't change FP values to integer values and vice versa, 850 but we can change e.g. DImode to SImode, and V2SFmode into DImode. */ 851 852 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 853 (reg_classes_intersect_p (CLASS, BR_REGS) \ 854 ? (FROM) != (TO) \ 855 : (SCALAR_FLOAT_MODE_P (FROM) != SCALAR_FLOAT_MODE_P (TO) \ 856 ? reg_classes_intersect_p (CLASS, FR_REGS) \ 857 : 0)) 858 859 /* Basic Stack Layout */ 860 861 /* Define this macro if pushing a word onto the stack moves the stack pointer 862 to a smaller address. */ 863 #define STACK_GROWS_DOWNWARD 1 864 865 /* Define this macro to nonzero if the addresses of local variable slots 866 are at negative offsets from the frame pointer. */ 867 #define FRAME_GROWS_DOWNWARD 0 868 869 /* Offset from the frame pointer to the first local variable slot to 870 be allocated. */ 871 #define STARTING_FRAME_OFFSET 0 872 873 /* Offset from the stack pointer register to the first location at which 874 outgoing arguments are placed. If not specified, the default value of zero 875 is used. This is the proper value for most machines. */ 876 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */ 877 #define STACK_POINTER_OFFSET 16 878 879 /* Offset from the argument pointer register to the first argument's address. 880 On some machines it may depend on the data type of the function. */ 881 #define FIRST_PARM_OFFSET(FUNDECL) 0 882 883 /* A C expression whose value is RTL representing the value of the return 884 address for the frame COUNT steps up from the current frame, after the 885 prologue. */ 886 887 /* ??? Frames other than zero would likely require interpreting the frame 888 unwind info, so we don't try to support them. We would also need to define 889 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */ 890 891 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 892 ia64_return_addr_rtx (COUNT, FRAME) 893 894 /* A C expression whose value is RTL representing the location of the incoming 895 return address at the beginning of any function, before the prologue. This 896 RTL is either a `REG', indicating that the return value is saved in `REG', 897 or a `MEM' representing a location in the stack. This enables DWARF2 898 unwind info for C++ EH. */ 899 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0)) 900 901 /* A C expression whose value is an integer giving the offset, in bytes, from 902 the value of the stack pointer register to the top of the stack frame at the 903 beginning of any function, before the prologue. The top of the frame is 904 defined to be the value of the stack pointer in the previous frame, just 905 before the call instruction. */ 906 /* The CFA is past the red zone, not at the entry-point stack 907 pointer. */ 908 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET 909 910 /* We shorten debug info by using CFA-16 as DW_AT_frame_base. */ 911 #define CFA_FRAME_BASE_OFFSET(FUNDECL) (-INCOMING_FRAME_SP_OFFSET) 912 913 914 /* Register That Address the Stack Frame. */ 915 916 /* The register number of the stack pointer register, which must also be a 917 fixed register according to `FIXED_REGISTERS'. On most machines, the 918 hardware determines which register this is. */ 919 920 #define STACK_POINTER_REGNUM 12 921 922 /* The register number of the frame pointer register, which is used to access 923 automatic variables in the stack frame. On some machines, the hardware 924 determines which register this is. On other machines, you can choose any 925 register you wish for this purpose. */ 926 927 #define FRAME_POINTER_REGNUM 328 928 929 /* Base register for access to local variables of the function. */ 930 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79) 931 932 /* The register number of the arg pointer register, which is used to access the 933 function's argument list. */ 934 /* r0 won't otherwise be used, so put the always eliminated argument pointer 935 in it. */ 936 #define ARG_POINTER_REGNUM R_GR(0) 937 938 /* Due to the way varargs and argument spilling happens, the argument 939 pointer is not 16-byte aligned like the stack pointer. */ 940 #define INIT_EXPANDERS \ 941 do { \ 942 ia64_init_expanders (); \ 943 if (crtl->emit.regno_pointer_align) \ 944 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \ 945 } while (0) 946 947 /* Register numbers used for passing a function's static chain pointer. */ 948 /* ??? The ABI sez the static chain should be passed as a normal parameter. */ 949 #define STATIC_CHAIN_REGNUM 15 950 951 /* Eliminating the Frame Pointer and the Arg Pointer */ 952 953 /* If defined, this macro specifies a table of register pairs used to eliminate 954 unneeded registers that point into the stack frame. */ 955 956 #define ELIMINABLE_REGS \ 957 { \ 958 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 959 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 960 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 961 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 962 } 963 964 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It 965 specifies the initial difference between the specified pair of 966 registers. This macro must be defined if `ELIMINABLE_REGS' is 967 defined. */ 968 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 969 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO))) 970 971 /* Passing Function Arguments on the Stack */ 972 973 /* If defined, the maximum amount of space required for outgoing arguments will 974 be computed and placed into the variable 975 `crtl->outgoing_args_size'. */ 976 977 #define ACCUMULATE_OUTGOING_ARGS 1 978 979 980 /* Function Arguments in Registers */ 981 982 #define MAX_ARGUMENT_SLOTS 8 983 #define MAX_INT_RETURN_SLOTS 4 984 #define GR_ARG_FIRST IN_REG (0) 985 #define GR_RET_FIRST GR_REG (8) 986 #define GR_RET_LAST GR_REG (11) 987 #define FR_ARG_FIRST FR_REG (8) 988 #define FR_RET_FIRST FR_REG (8) 989 #define FR_RET_LAST FR_REG (15) 990 #define AR_ARG_FIRST OUT_REG (0) 991 992 /* A C type for declaring a variable that is used as the first argument of 993 `FUNCTION_ARG' and other related values. For some target machines, the type 994 `int' suffices and can hold the number of bytes of argument so far. */ 995 996 enum ivms_arg_type {I64, FF, FD, FG, FS, FT}; 997 /* VMS floating point formats VAX F, VAX D, VAX G, IEEE S, IEEE T. */ 998 999 typedef struct ia64_args 1000 { 1001 int words; /* # words of arguments so far */ 1002 int int_regs; /* # GR registers used so far */ 1003 int fp_regs; /* # FR registers used so far */ 1004 int prototype; /* whether function prototyped */ 1005 enum ivms_arg_type atypes[8]; /* which VMS float type or if not float */ 1006 } CUMULATIVE_ARGS; 1007 1008 /* A C statement (sans semicolon) for initializing the variable CUM for the 1009 state at the beginning of the argument list. */ 1010 1011 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1012 do { \ 1013 (CUM).words = 0; \ 1014 (CUM).int_regs = 0; \ 1015 (CUM).fp_regs = 0; \ 1016 (CUM).prototype = ((FNTYPE) && prototype_p (FNTYPE)) || (LIBNAME); \ 1017 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \ 1018 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \ 1019 (CUM).atypes[6] = (CUM).atypes[7] = I64; \ 1020 } while (0) 1021 1022 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the 1023 arguments for the function being compiled. If this macro is undefined, 1024 `INIT_CUMULATIVE_ARGS' is used instead. */ 1025 1026 /* We set prototype to true so that we never try to return a PARALLEL from 1027 function_arg. */ 1028 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1029 do { \ 1030 (CUM).words = 0; \ 1031 (CUM).int_regs = 0; \ 1032 (CUM).fp_regs = 0; \ 1033 (CUM).prototype = 1; \ 1034 (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64; \ 1035 (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64; \ 1036 (CUM).atypes[6] = (CUM).atypes[7] = I64; \ 1037 } while (0) 1038 1039 /* A C expression that is nonzero if REGNO is the number of a hard register in 1040 which function arguments are sometimes passed. This does *not* include 1041 implicit arguments such as the static chain and the structure-value address. 1042 On many machines, no registers can be used for this purpose since all 1043 function arguments are pushed on the stack. */ 1044 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1045 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \ 1046 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS))) 1047 1048 1049 /* How Large Values are Returned */ 1050 1051 #define DEFAULT_PCC_STRUCT_RETURN 0 1052 1053 1054 /* Caller-Saves Register Allocation */ 1055 1056 /* A C expression to determine whether it is worthwhile to consider placing a 1057 pseudo-register in a call-clobbered hard register and saving and restoring 1058 it around each function call. The expression should be 1 when this is worth 1059 doing, and 0 otherwise. 1060 1061 If you don't define this macro, a default is used which is good on most 1062 machines: `4 * CALLS < REFS'. */ 1063 /* ??? Investigate. */ 1064 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */ 1065 1066 1067 /* Function Entry and Exit */ 1068 1069 /* Define this macro as a C expression that is nonzero if the return 1070 instruction or the function epilogue ignores the value of the stack pointer; 1071 in other words, if it is safe to delete an instruction to adjust the stack 1072 pointer before a return from the function. */ 1073 1074 #define EXIT_IGNORE_STACK 1 1075 1076 /* Define this macro as a C expression that is nonzero for registers 1077 used by the epilogue or the `return' pattern. */ 1078 1079 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO) 1080 1081 /* Nonzero for registers used by the exception handling mechanism. */ 1082 1083 #define EH_USES(REGNO) ia64_eh_uses (REGNO) 1084 1085 /* Output part N of a function descriptor for DECL. For ia64, both 1086 words are emitted with a single relocation, so ignore N > 0. */ 1087 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \ 1088 do { \ 1089 if ((PART) == 0) \ 1090 { \ 1091 if (TARGET_ILP32) \ 1092 fputs ("\tdata8.ua @iplt(", FILE); \ 1093 else \ 1094 fputs ("\tdata16.ua @iplt(", FILE); \ 1095 mark_decl_referenced (DECL); \ 1096 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \ 1097 fputs (")\n", FILE); \ 1098 if (TARGET_ILP32) \ 1099 fputs ("\tdata8.ua 0\n", FILE); \ 1100 } \ 1101 } while (0) 1102 1103 /* Generating Code for Profiling. */ 1104 1105 /* A C statement or compound statement to output to FILE some assembler code to 1106 call the profiling subroutine `mcount'. */ 1107 1108 #undef FUNCTION_PROFILER 1109 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1110 ia64_output_function_profiler(FILE, LABELNO) 1111 1112 /* Neither hpux nor linux use profile counters. */ 1113 #define NO_PROFILE_COUNTERS 1 1114 1115 /* Trampolines for Nested Functions. */ 1116 1117 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of 1118 the function containing a non-local goto target. */ 1119 1120 #define STACK_SAVEAREA_MODE(LEVEL) \ 1121 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode) 1122 1123 /* A C expression for the size in bytes of the trampoline, as an integer. */ 1124 1125 #define TRAMPOLINE_SIZE 32 1126 1127 /* Alignment required for trampolines, in bits. */ 1128 1129 #define TRAMPOLINE_ALIGNMENT 64 1130 1131 /* Addressing Modes */ 1132 1133 /* Define this macro if the machine supports post-increment addressing. */ 1134 1135 #define HAVE_POST_INCREMENT 1 1136 #define HAVE_POST_DECREMENT 1 1137 #define HAVE_POST_MODIFY_DISP 1 1138 #define HAVE_POST_MODIFY_REG 1 1139 1140 /* A C expression that is 1 if the RTX X is a constant which is a valid 1141 address. */ 1142 1143 #define CONSTANT_ADDRESS_P(X) 0 1144 1145 /* The max number of registers that can appear in a valid memory address. */ 1146 1147 #define MAX_REGS_PER_ADDRESS 2 1148 1149 1150 /* Condition Code Status */ 1151 1152 /* One some machines not all possible comparisons are defined, but you can 1153 convert an invalid comparison into a valid one. */ 1154 /* ??? Investigate. See the alpha definition. */ 1155 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */ 1156 1157 1158 /* Describing Relative Costs of Operations */ 1159 1160 /* A C expression for the cost of a branch instruction. A value of 1 is the 1161 default; other values are interpreted relative to that. Used by the 1162 if-conversion code as max instruction count. */ 1163 /* ??? This requires investigation. The primary effect might be how 1164 many additional insn groups we run into, vs how good the dynamic 1165 branch predictor is. */ 1166 1167 #define BRANCH_COST(speed_p, predictable_p) 6 1168 1169 /* Define this macro as a C expression which is nonzero if accessing less than 1170 a word of memory (i.e. a `char' or a `short') is no faster than accessing a 1171 word of memory. */ 1172 1173 #define SLOW_BYTE_ACCESS 1 1174 1175 /* Define this macro if it is as good or better to call a constant function 1176 address than to call an address kept in a register. 1177 1178 Indirect function calls are more expensive that direct function calls, so 1179 don't cse function addresses. */ 1180 1181 #define NO_FUNCTION_CSE 1182 1183 1184 /* Dividing the output into sections. */ 1185 1186 /* A C expression whose value is a string containing the assembler operation 1187 that should precede instructions and read-only data. */ 1188 1189 #define TEXT_SECTION_ASM_OP "\t.text" 1190 1191 /* A C expression whose value is a string containing the assembler operation to 1192 identify the following data as writable initialized data. */ 1193 1194 #define DATA_SECTION_ASM_OP "\t.data" 1195 1196 /* If defined, a C expression whose value is a string containing the assembler 1197 operation to identify the following data as uninitialized global data. */ 1198 1199 #define BSS_SECTION_ASM_OP "\t.bss" 1200 1201 #define IA64_DEFAULT_GVALUE 8 1202 1203 /* Position Independent Code. */ 1204 1205 /* The register number of the register used to address a table of static data 1206 addresses in memory. */ 1207 1208 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of 1209 gen_rtx_REG (DImode, 1). */ 1210 1211 /* ??? Should we set flag_pic? Probably need to define 1212 LEGITIMIZE_PIC_OPERAND_P to make that work. */ 1213 1214 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1) 1215 1216 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is 1217 clobbered by calls. */ 1218 1219 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1 1220 1221 1222 /* The Overall Framework of an Assembler File. */ 1223 1224 /* A C string constant describing how to begin a comment in the target 1225 assembler language. The compiler assumes that the comment will end at the 1226 end of the line. */ 1227 1228 #define ASM_COMMENT_START "//" 1229 1230 /* A C string constant for text to be output before each `asm' statement or 1231 group of consecutive ones. */ 1232 1233 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n") 1234 1235 /* A C string constant for text to be output after each `asm' statement or 1236 group of consecutive ones. */ 1237 1238 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n") 1239 1240 /* Output and Generation of Labels. */ 1241 1242 /* A C statement (sans semicolon) to output to the stdio stream STREAM the 1243 assembler definition of a label named NAME. */ 1244 1245 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of 1246 why ia64_asm_output_label exists. */ 1247 1248 extern int ia64_asm_output_label; 1249 #define ASM_OUTPUT_LABEL(STREAM, NAME) \ 1250 do { \ 1251 ia64_asm_output_label = 1; \ 1252 assemble_name (STREAM, NAME); \ 1253 fputs (":\n", STREAM); \ 1254 ia64_asm_output_label = 0; \ 1255 } while (0) 1256 1257 /* Globalizing directive for a label. */ 1258 #define GLOBAL_ASM_OP "\t.global " 1259 1260 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text 1261 necessary for declaring the name of an external symbol named NAME which is 1262 referenced in this compilation but not defined. */ 1263 1264 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ 1265 ia64_asm_output_external (FILE, DECL, NAME) 1266 1267 /* A C statement to store into the string STRING a label whose name is made 1268 from the string PREFIX and the number NUM. */ 1269 1270 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ 1271 do { \ 1272 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \ 1273 } while (0) 1274 1275 /* ??? Not sure if using a ? in the name for Intel as is safe. */ 1276 1277 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu") 1278 1279 /* A C statement to output to the stdio stream STREAM assembler code which 1280 defines (equates) the symbol NAME to have the value VALUE. */ 1281 1282 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ 1283 do { \ 1284 assemble_name (STREAM, NAME); \ 1285 fputs (" = ", STREAM); \ 1286 if (ISDIGIT (*VALUE)) \ 1287 ia64_asm_output_label = 1; \ 1288 assemble_name (STREAM, VALUE); \ 1289 fputc ('\n', STREAM); \ 1290 ia64_asm_output_label = 0; \ 1291 } while (0) 1292 1293 1294 /* Macros Controlling Initialization Routines. */ 1295 1296 /* This is handled by sysv4.h. */ 1297 1298 1299 /* Output of Assembler Instructions. */ 1300 1301 /* A C initializer containing the assembler's names for the machine registers, 1302 each one as a C string constant. */ 1303 1304 #define REGISTER_NAMES \ 1305 { \ 1306 /* General registers. */ \ 1307 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ 1308 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ 1309 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ 1310 "r30", "r31", \ 1311 /* Local registers. */ \ 1312 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \ 1313 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \ 1314 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \ 1315 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \ 1316 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \ 1317 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \ 1318 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \ 1319 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \ 1320 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \ 1321 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \ 1322 /* Input registers. */ \ 1323 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \ 1324 /* Output registers. */ \ 1325 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \ 1326 /* Floating-point registers. */ \ 1327 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \ 1328 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \ 1329 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \ 1330 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \ 1331 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \ 1332 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \ 1333 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \ 1334 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \ 1335 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \ 1336 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \ 1337 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\ 1338 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\ 1339 "f120","f121","f122","f123","f124","f125","f126","f127", \ 1340 /* Predicate registers. */ \ 1341 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \ 1342 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \ 1343 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \ 1344 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \ 1345 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \ 1346 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \ 1347 "p60", "p61", "p62", "p63", \ 1348 /* Branch registers. */ \ 1349 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \ 1350 /* Frame pointer. Application registers. */ \ 1351 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \ 1352 } 1353 1354 /* If defined, a C initializer for an array of structures containing a name and 1355 a register number. This macro defines additional names for hard registers, 1356 thus allowing the `asm' option in declarations to refer to registers using 1357 alternate names. */ 1358 1359 #define ADDITIONAL_REGISTER_NAMES \ 1360 { \ 1361 { "gp", R_GR (1) }, \ 1362 { "sp", R_GR (12) }, \ 1363 { "in0", IN_REG (0) }, \ 1364 { "in1", IN_REG (1) }, \ 1365 { "in2", IN_REG (2) }, \ 1366 { "in3", IN_REG (3) }, \ 1367 { "in4", IN_REG (4) }, \ 1368 { "in5", IN_REG (5) }, \ 1369 { "in6", IN_REG (6) }, \ 1370 { "in7", IN_REG (7) }, \ 1371 { "out0", OUT_REG (0) }, \ 1372 { "out1", OUT_REG (1) }, \ 1373 { "out2", OUT_REG (2) }, \ 1374 { "out3", OUT_REG (3) }, \ 1375 { "out4", OUT_REG (4) }, \ 1376 { "out5", OUT_REG (5) }, \ 1377 { "out6", OUT_REG (6) }, \ 1378 { "out7", OUT_REG (7) }, \ 1379 { "loc0", LOC_REG (0) }, \ 1380 { "loc1", LOC_REG (1) }, \ 1381 { "loc2", LOC_REG (2) }, \ 1382 { "loc3", LOC_REG (3) }, \ 1383 { "loc4", LOC_REG (4) }, \ 1384 { "loc5", LOC_REG (5) }, \ 1385 { "loc6", LOC_REG (6) }, \ 1386 { "loc7", LOC_REG (7) }, \ 1387 { "loc8", LOC_REG (8) }, \ 1388 { "loc9", LOC_REG (9) }, \ 1389 { "loc10", LOC_REG (10) }, \ 1390 { "loc11", LOC_REG (11) }, \ 1391 { "loc12", LOC_REG (12) }, \ 1392 { "loc13", LOC_REG (13) }, \ 1393 { "loc14", LOC_REG (14) }, \ 1394 { "loc15", LOC_REG (15) }, \ 1395 { "loc16", LOC_REG (16) }, \ 1396 { "loc17", LOC_REG (17) }, \ 1397 { "loc18", LOC_REG (18) }, \ 1398 { "loc19", LOC_REG (19) }, \ 1399 { "loc20", LOC_REG (20) }, \ 1400 { "loc21", LOC_REG (21) }, \ 1401 { "loc22", LOC_REG (22) }, \ 1402 { "loc23", LOC_REG (23) }, \ 1403 { "loc24", LOC_REG (24) }, \ 1404 { "loc25", LOC_REG (25) }, \ 1405 { "loc26", LOC_REG (26) }, \ 1406 { "loc27", LOC_REG (27) }, \ 1407 { "loc28", LOC_REG (28) }, \ 1408 { "loc29", LOC_REG (29) }, \ 1409 { "loc30", LOC_REG (30) }, \ 1410 { "loc31", LOC_REG (31) }, \ 1411 { "loc32", LOC_REG (32) }, \ 1412 { "loc33", LOC_REG (33) }, \ 1413 { "loc34", LOC_REG (34) }, \ 1414 { "loc35", LOC_REG (35) }, \ 1415 { "loc36", LOC_REG (36) }, \ 1416 { "loc37", LOC_REG (37) }, \ 1417 { "loc38", LOC_REG (38) }, \ 1418 { "loc39", LOC_REG (39) }, \ 1419 { "loc40", LOC_REG (40) }, \ 1420 { "loc41", LOC_REG (41) }, \ 1421 { "loc42", LOC_REG (42) }, \ 1422 { "loc43", LOC_REG (43) }, \ 1423 { "loc44", LOC_REG (44) }, \ 1424 { "loc45", LOC_REG (45) }, \ 1425 { "loc46", LOC_REG (46) }, \ 1426 { "loc47", LOC_REG (47) }, \ 1427 { "loc48", LOC_REG (48) }, \ 1428 { "loc49", LOC_REG (49) }, \ 1429 { "loc50", LOC_REG (50) }, \ 1430 { "loc51", LOC_REG (51) }, \ 1431 { "loc52", LOC_REG (52) }, \ 1432 { "loc53", LOC_REG (53) }, \ 1433 { "loc54", LOC_REG (54) }, \ 1434 { "loc55", LOC_REG (55) }, \ 1435 { "loc56", LOC_REG (56) }, \ 1436 { "loc57", LOC_REG (57) }, \ 1437 { "loc58", LOC_REG (58) }, \ 1438 { "loc59", LOC_REG (59) }, \ 1439 { "loc60", LOC_REG (60) }, \ 1440 { "loc61", LOC_REG (61) }, \ 1441 { "loc62", LOC_REG (62) }, \ 1442 { "loc63", LOC_REG (63) }, \ 1443 { "loc64", LOC_REG (64) }, \ 1444 { "loc65", LOC_REG (65) }, \ 1445 { "loc66", LOC_REG (66) }, \ 1446 { "loc67", LOC_REG (67) }, \ 1447 { "loc68", LOC_REG (68) }, \ 1448 { "loc69", LOC_REG (69) }, \ 1449 { "loc70", LOC_REG (70) }, \ 1450 { "loc71", LOC_REG (71) }, \ 1451 { "loc72", LOC_REG (72) }, \ 1452 { "loc73", LOC_REG (73) }, \ 1453 { "loc74", LOC_REG (74) }, \ 1454 { "loc75", LOC_REG (75) }, \ 1455 { "loc76", LOC_REG (76) }, \ 1456 { "loc77", LOC_REG (77) }, \ 1457 { "loc78", LOC_REG (78) }, \ 1458 { "loc79", LOC_REG (79) }, \ 1459 } 1460 1461 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and 1462 `%I' options of `asm_fprintf' (see `final.c'). */ 1463 1464 #define REGISTER_PREFIX "" 1465 #define LOCAL_LABEL_PREFIX "." 1466 #define USER_LABEL_PREFIX "" 1467 #define IMMEDIATE_PREFIX "" 1468 1469 1470 /* Output of dispatch tables. */ 1471 1472 /* This macro should be provided on machines where the addresses in a dispatch 1473 table are relative to the table's own address. */ 1474 1475 /* ??? Depends on the pointer size. */ 1476 1477 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 1478 do { \ 1479 if (CASE_VECTOR_MODE == SImode) \ 1480 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \ 1481 else \ 1482 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \ 1483 } while (0) 1484 1485 /* Jump tables only need 4 or 8 byte alignment. */ 1486 1487 #define ADDR_VEC_ALIGN(ADDR_VEC) (CASE_VECTOR_MODE == SImode ? 2 : 3) 1488 1489 1490 /* Assembler Commands for Exception Regions. */ 1491 1492 /* Select a format to encode pointers in exception handling data. CODE 1493 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1494 true if the symbol may be affected by dynamic relocations. */ 1495 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1496 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \ 1497 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \ 1498 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8)) 1499 1500 /* Handle special EH pointer encodings. Absolute, pc-relative, and 1501 indirect are handled automatically. */ 1502 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ 1503 do { \ 1504 const char *reltag = NULL; \ 1505 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \ 1506 reltag = "@segrel("; \ 1507 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \ 1508 reltag = "@gprel("; \ 1509 if (reltag) \ 1510 { \ 1511 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1512 fputs (reltag, FILE); \ 1513 assemble_name (FILE, XSTR (ADDR, 0)); \ 1514 fputc (')', FILE); \ 1515 goto DONE; \ 1516 } \ 1517 } while (0) 1518 1519 1520 /* Assembler Commands for Alignment. */ 1521 1522 /* ??? Investigate. */ 1523 1524 /* The alignment (log base 2) to put in front of LABEL, which follows 1525 a BARRIER. */ 1526 1527 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */ 1528 1529 /* The desired alignment for the location counter at the beginning 1530 of a loop. */ 1531 1532 /* #define LOOP_ALIGN(LABEL) */ 1533 1534 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text 1535 section because it fails put zeros in the bytes that are skipped. */ 1536 1537 #define ASM_NO_SKIP_IN_TEXT 1 1538 1539 /* A C statement to output to the stdio stream STREAM an assembler command to 1540 advance the location counter to a multiple of 2 to the POWER bytes. */ 1541 1542 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 1543 fprintf (STREAM, "\t.align %d\n", 1<<(POWER)) 1544 1545 1546 /* Macros Affecting all Debug Formats. */ 1547 1548 /* This is handled in sysv4.h. */ 1549 1550 1551 /* Specific Options for DBX Output. */ 1552 1553 /* This is handled by dbxelf.h. */ 1554 1555 1556 /* Open ended Hooks for DBX Output. */ 1557 1558 /* Likewise. */ 1559 1560 1561 /* File names in DBX format. */ 1562 1563 /* Likewise. */ 1564 1565 1566 /* Macros for SDB and Dwarf Output. */ 1567 1568 /* Define this macro if GCC should produce dwarf version 2 format debugging 1569 output in response to the `-g' option. */ 1570 1571 #define DWARF2_DEBUGGING_INFO 1 1572 1573 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM) 1574 1575 /* Use tags for debug info labels, so that they don't break instruction 1576 bundles. This also avoids getting spurious DV warnings from the 1577 assembler. This is similar to (*targetm.asm_out.internal_label), except that we 1578 add brackets around the label. */ 1579 1580 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ 1581 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM) 1582 1583 /* Use section-relative relocations for debugging offsets. Unlike other 1584 targets that fake this by putting the section VMA at 0, IA-64 has 1585 proper relocations for them. */ 1586 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, SECTION) \ 1587 do { \ 1588 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1589 fputs ("@secrel(", FILE); \ 1590 assemble_name (FILE, LABEL); \ 1591 fputc (')', FILE); \ 1592 } while (0) 1593 1594 /* Emit a PC-relative relocation. */ 1595 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1596 do { \ 1597 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1598 fputs ("@pcrel(", FILE); \ 1599 assemble_name (FILE, LABEL); \ 1600 fputc (')', FILE); \ 1601 } while (0) 1602 1603 /* Register Renaming Parameters. */ 1604 1605 /* A C expression that is nonzero if hard register number REGNO2 can be 1606 considered for use as a rename register for REGNO1 */ 1607 1608 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ 1609 ia64_hard_regno_rename_ok((REGNO1), (REGNO2)) 1610 1611 1612 /* Miscellaneous Parameters. */ 1613 1614 /* Flag to mark data that is in the small address area (addressable 1615 via "addl", that is, within a 2MByte offset of 0. */ 1616 #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 1617 #define SYMBOL_REF_SMALL_ADDR_P(X) \ 1618 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0) 1619 1620 /* An alias for a machine mode name. This is the machine mode that elements of 1621 a jump-table should have. */ 1622 1623 #define CASE_VECTOR_MODE ptr_mode 1624 1625 /* Define as C expression which evaluates to nonzero if the tablejump 1626 instruction expects the table to contain offsets from the address of the 1627 table. */ 1628 1629 #define CASE_VECTOR_PC_RELATIVE 1 1630 1631 /* Define this macro if operations between registers with integral mode smaller 1632 than a word are always performed on the entire register. */ 1633 1634 #define WORD_REGISTER_OPERATIONS 1635 1636 /* Define this macro to be a C expression indicating when insns that read 1637 memory in MODE, an integral mode narrower than a word, set the bits outside 1638 of MODE to be either the sign-extension or the zero-extension of the data 1639 read. */ 1640 1641 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1642 1643 /* The maximum number of bytes that a single instruction can move quickly from 1644 memory to memory. */ 1645 #define MOVE_MAX 8 1646 1647 /* A C expression which is nonzero if on this machine it is safe to "convert" 1648 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller 1649 than INPREC) by merely operating on it as if it had only OUTPREC bits. */ 1650 1651 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1652 1653 /* A C expression describing the value returned by a comparison operator with 1654 an integral mode and stored by a store-flag instruction (`sCOND') when the 1655 condition is true. */ 1656 1657 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */ 1658 1659 /* An alias for the machine mode for pointers. */ 1660 1661 /* ??? This would change if we had ILP32 support. */ 1662 1663 #define Pmode DImode 1664 1665 /* An alias for the machine mode used for memory references to functions being 1666 called, in `call' RTL expressions. */ 1667 1668 #define FUNCTION_MODE Pmode 1669 1670 /* A C expression for the maximum number of instructions to execute via 1671 conditional execution instructions instead of a branch. A value of 1672 BRANCH_COST+1 is the default if the machine does not use 1673 cc0, and 1 if it does use cc0. */ 1674 /* ??? Investigate. */ 1675 #define MAX_CONDITIONAL_EXECUTE 12 1676 1677 extern int ia64_final_schedule; 1678 1679 #define TARGET_UNWIND_TABLES_DEFAULT true 1680 1681 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM) 1682 1683 /* This function contains machine specific function data. */ 1684 struct GTY(()) machine_function 1685 { 1686 /* The new stack pointer when unwinding from EH. */ 1687 rtx ia64_eh_epilogue_sp; 1688 1689 /* The new bsp value when unwinding from EH. */ 1690 rtx ia64_eh_epilogue_bsp; 1691 1692 /* The GP value save register. */ 1693 rtx ia64_gp_save; 1694 1695 /* The number of varargs registers to save. */ 1696 int n_varargs; 1697 1698 /* The number of the next unwind state to copy. */ 1699 int state_num; 1700 }; 1701 1702 #define DONT_USE_BUILTIN_SETJMP 1703 1704 /* Output any profiling code before the prologue. */ 1705 1706 #undef PROFILE_BEFORE_PROLOGUE 1707 #define PROFILE_BEFORE_PROLOGUE 1 1708 1709 /* Initialize library function table. */ 1710 #undef TARGET_INIT_LIBFUNCS 1711 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs 1712 1713 1714 /* Switch on code for querying unit reservations. */ 1715 #define CPU_UNITS_QUERY 1 1716 1717 /* End of ia64.h */ 1718