1;; Copyright (C) 2012-2019 Free Software Foundation, Inc. 2;; 3;; This file is part of GCC. 4;; 5;; GCC is free software; you can redistribute it and/or modify 6;; it under the terms of the GNU General Public License as published by 7;; the Free Software Foundation; either version 3, or (at your option) 8;; any later version. 9;; 10;; GCC is distributed in the hope that it will be useful, 11;; but WITHOUT ANY WARRANTY; without even the implied warranty of 12;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13;; GNU General Public License for more details. 14;; 15;; You should have received a copy of the GNU General Public License 16;; along with GCC; see the file COPYING3. If not see 17;; <http://www.gnu.org/licenses/>. 18;; 19 20(define_attr "znver1_decode" "direct,vector,double" 21 (const_string "direct")) 22 23;; AMD znver1 and znver2 Scheduling 24;; Modeling automatons for zen decoders, integer execution pipes, 25;; AGU pipes and floating point execution units. 26(define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu") 27 28;; Decoders unit has 4 decoders and all of them can decode fast path 29;; and vector type instructions. 30(define_cpu_unit "znver1-decode0" "znver1") 31(define_cpu_unit "znver1-decode1" "znver1") 32(define_cpu_unit "znver1-decode2" "znver1") 33(define_cpu_unit "znver1-decode3" "znver1") 34 35;; Currently blocking all decoders for vector path instructions as 36;; they are dispatched separetely as microcode sequence. 37;; Fix me: Need to revisit this. 38(define_reservation "znver1-vector" "znver1-decode0+znver1-decode1+znver1-decode2+znver1-decode3") 39 40;; Direct instructions can be issued to any of the four decoders. 41(define_reservation "znver1-direct" "znver1-decode0|znver1-decode1|znver1-decode2|znver1-decode3") 42 43;; Fix me: Need to revisit this later to simulate fast path double behavior. 44(define_reservation "znver1-double" "znver1-direct") 45 46 47;; Integer unit 4 ALU pipes. 48(define_cpu_unit "znver1-ieu0" "znver1_ieu") 49(define_cpu_unit "znver1-ieu1" "znver1_ieu") 50(define_cpu_unit "znver1-ieu2" "znver1_ieu") 51(define_cpu_unit "znver1-ieu3" "znver1_ieu") 52(define_reservation "znver1-ieu" "znver1-ieu0|znver1-ieu1|znver1-ieu2|znver1-ieu3") 53 54;; 2 AGU pipes in znver1 and 3 AGU pipes in znver2 55;; According to CPU diagram last AGU unit is used only for stores. 56(define_cpu_unit "znver1-agu0" "znver1_agu") 57(define_cpu_unit "znver1-agu1" "znver1_agu") 58(define_cpu_unit "znver2-agu2" "znver1_agu") 59(define_reservation "znver1-agu-reserve" "znver1-agu0|znver1-agu1") 60(define_reservation "znver2-store-agu-reserve" "znver1-agu0|znver1-agu1|znver2-agu2") 61 62;; Load is 4 cycles. We do not model reservation of load unit. 63;;(define_reservation "znver1-load" "znver1-agu-reserve, nothing, nothing, nothing") 64(define_reservation "znver1-load" "znver1-agu-reserve") 65;; Store operations differs between znver1 and znver2 because extra AGU 66;; was added. 67(define_reservation "znver1-store" "znver1-agu-reserve") 68(define_reservation "znver2-store" "znver2-store-agu-reserve") 69 70;; vectorpath (microcoded) instructions are single issue instructions. 71;; So, they occupy all the integer units. 72(define_reservation "znver1-ivector" "znver1-ieu0+znver1-ieu1 73 +znver1-ieu2+znver1-ieu3 74 +znver1-agu0+znver1-agu1") 75 76(define_reservation "znver2-ivector" "znver1-ieu0+znver1-ieu1 77 +znver1-ieu2+znver1-ieu3 78 +znver1-agu0+znver1-agu1+znver2-agu2") 79;; Floating point unit 4 FP pipes. 80(define_cpu_unit "znver1-fp0" "znver1_fp") 81(define_cpu_unit "znver1-fp1" "znver1_fp") 82(define_cpu_unit "znver1-fp2" "znver1_fp") 83(define_cpu_unit "znver1-fp3" "znver1_fp") 84 85(define_reservation "znver1-fpu" "znver1-fp0|znver1-fp1|znver1-fp2|znver1-fp3") 86 87(define_reservation "znver1-fvector" "znver1-fp0+znver1-fp1 88 +znver1-fp2+znver1-fp3 89 +znver1-agu0+znver1-agu1") 90(define_reservation "znver2-fvector" "znver1-fp0+znver1-fp1 91 +znver1-fp2+znver1-fp3 92 +znver1-agu0+znver1-agu1+znver2-agu2") 93 94;; Call instruction 95(define_insn_reservation "znver1_call" 1 96 (and (eq_attr "cpu" "znver1") 97 (eq_attr "type" "call,callv")) 98 "znver1-double,znver1-store,znver1-ieu0|znver1-ieu3") 99 100(define_insn_reservation "znver2_call" 1 101 (and (eq_attr "cpu" "znver2") 102 (eq_attr "type" "call,callv")) 103 "znver1-double,znver2-store,znver1-ieu0|znver1-ieu3") 104 105;; General instructions 106(define_insn_reservation "znver1_push" 1 107 (and (eq_attr "cpu" "znver1") 108 (and (eq_attr "type" "push") 109 (eq_attr "memory" "store"))) 110 "znver1-direct,znver1-store") 111(define_insn_reservation "znver2_push" 1 112 (and (eq_attr "cpu" "znver2") 113 (and (eq_attr "type" "push") 114 (eq_attr "memory" "store"))) 115 "znver1-direct,znver1-store") 116 117(define_insn_reservation "znver1_push_load" 4 118 (and (eq_attr "cpu" "znver1") 119 (and (eq_attr "type" "push") 120 (eq_attr "memory" "both"))) 121 "znver1-direct,znver1-load,znver1-store") 122(define_insn_reservation "znver2_push_load" 4 123 (and (eq_attr "cpu" "znver2") 124 (and (eq_attr "type" "push") 125 (eq_attr "memory" "both"))) 126 "znver1-direct,znver1-load,znver2-store") 127 128(define_insn_reservation "znver1_pop" 4 129 (and (eq_attr "cpu" "znver1,znver2") 130 (and (eq_attr "type" "pop") 131 (eq_attr "memory" "load"))) 132 "znver1-direct,znver1-load") 133 134(define_insn_reservation "znver1_pop_mem" 4 135 (and (eq_attr "cpu" "znver1") 136 (and (eq_attr "type" "pop") 137 (eq_attr "memory" "both"))) 138 "znver1-direct,znver1-load,znver1-store") 139(define_insn_reservation "znver2_pop_mem" 4 140 (and (eq_attr "cpu" "znver2") 141 (and (eq_attr "type" "pop") 142 (eq_attr "memory" "both"))) 143 "znver1-direct,znver1-load,znver2-store") 144 145;; Leave 146(define_insn_reservation "znver1_leave" 1 147 (and (eq_attr "cpu" "znver1") 148 (eq_attr "type" "leave")) 149 "znver1-double,znver1-ieu, znver1-store") 150(define_insn_reservation "znver2_leave" 1 151 (and (eq_attr "cpu" "znver2") 152 (eq_attr "type" "leave")) 153 "znver1-double,znver1-ieu, znver2-store") 154 155;; Integer Instructions or General instructions 156;; Multiplications 157;; Reg operands 158(define_insn_reservation "znver1_imul" 3 159 (and (eq_attr "cpu" "znver1,znver2") 160 (and (eq_attr "type" "imul") 161 (eq_attr "memory" "none"))) 162 "znver1-direct,znver1-ieu1") 163 164(define_insn_reservation "znver1_imul_mem" 7 165 (and (eq_attr "cpu" "znver1,znver2") 166 (and (eq_attr "type" "imul") 167 (eq_attr "memory" "!none"))) 168 "znver1-direct,znver1-load, znver1-ieu1") 169 170;; Divisions 171;; Reg operands 172(define_insn_reservation "znver1_idiv_DI" 41 173 (and (eq_attr "cpu" "znver1,znver2") 174 (and (eq_attr "type" "idiv") 175 (and (eq_attr "mode" "DI") 176 (eq_attr "memory" "none")))) 177 "znver1-double,znver1-ieu2*41") 178 179(define_insn_reservation "znver1_idiv_SI" 25 180 (and (eq_attr "cpu" "znver1,znver2") 181 (and (eq_attr "type" "idiv") 182 (and (eq_attr "mode" "SI") 183 (eq_attr "memory" "none")))) 184 "znver1-double,znver1-ieu2*25") 185 186(define_insn_reservation "znver1_idiv_HI" 17 187 (and (eq_attr "cpu" "znver1,znver2") 188 (and (eq_attr "type" "idiv") 189 (and (eq_attr "mode" "HI") 190 (eq_attr "memory" "none")))) 191 "znver1-double,znver1-ieu2*17") 192 193(define_insn_reservation "znver1_idiv_QI" 12 194 (and (eq_attr "cpu" "znver1,znver2") 195 (and (eq_attr "type" "idiv") 196 (and (eq_attr "mode" "QI") 197 (eq_attr "memory" "none")))) 198 "znver1-direct,znver1-ieu2*12") 199 200;; Mem operands 201(define_insn_reservation "znver1_idiv_mem_DI" 45 202 (and (eq_attr "cpu" "znver1,znver2") 203 (and (eq_attr "type" "idiv") 204 (and (eq_attr "mode" "DI") 205 (eq_attr "memory" "none")))) 206 "znver1-double,znver1-load,znver1-ieu2*41") 207 208(define_insn_reservation "znver1_idiv_mem_SI" 29 209 (and (eq_attr "cpu" "znver1,znver2") 210 (and (eq_attr "type" "idiv") 211 (and (eq_attr "mode" "SI") 212 (eq_attr "memory" "none")))) 213 "znver1-double,znver1-load,znver1-ieu2*25") 214 215(define_insn_reservation "znver1_idiv_mem_HI" 21 216 (and (eq_attr "cpu" "znver1,znver2") 217 (and (eq_attr "type" "idiv") 218 (and (eq_attr "mode" "HI") 219 (eq_attr "memory" "none")))) 220 "znver1-double,znver1-load,znver1-ieu2*17") 221 222(define_insn_reservation "znver1_idiv_mem_QI" 16 223 (and (eq_attr "cpu" "znver1,znver2") 224 (and (eq_attr "type" "idiv") 225 (and (eq_attr "mode" "QI") 226 (eq_attr "memory" "none")))) 227 "znver1-direct,znver1-load,znver1-ieu2*12") 228 229;; STR ISHIFT which are micro coded. 230;; Fix me: Latency need to be rechecked. 231(define_insn_reservation "znver1_str_ishift" 6 232 (and (eq_attr "cpu" "znver1") 233 (and (eq_attr "type" "str,ishift") 234 (eq_attr "memory" "both,store"))) 235 "znver1-vector,znver1-ivector") 236 237(define_insn_reservation "znver2_str_ishift" 3 238 (and (eq_attr "cpu" "znver2") 239 (and (eq_attr "type" "ishift") 240 (eq_attr "memory" "both,store"))) 241 "znver1-vector,znver1-ivector") 242(define_insn_reservation "znver2_str_istr" 19 243 (and (eq_attr "cpu" "znver2") 244 (and (eq_attr "type" "str") 245 (eq_attr "memory" "both,store"))) 246 "znver1-vector,znver1-ivector") 247;; MOV - integer moves 248(define_insn_reservation "znver1_load_imov_double" 2 249 (and (eq_attr "cpu" "znver1") 250 (and (eq_attr "znver1_decode" "double") 251 (and (eq_attr "type" "imovx") 252 (eq_attr "memory" "none")))) 253 "znver1-double,znver1-ieu|znver1-ieu") 254 255(define_insn_reservation "znver2_load_imov_double" 1 256 (and (eq_attr "cpu" "znver2") 257 (and (eq_attr "znver1_decode" "double") 258 (and (eq_attr "type" "imovx") 259 (eq_attr "memory" "none")))) 260 "znver1-double,znver1-ieu|znver1-ieu") 261 262(define_insn_reservation "znver1_load_imov_direct" 1 263 (and (eq_attr "cpu" "znver1,znver2") 264 (and (eq_attr "type" "imov,imovx") 265 (eq_attr "memory" "none"))) 266 "znver1-direct,znver1-ieu") 267 268(define_insn_reservation "znver1_load_imov_double_store" 2 269 (and (eq_attr "cpu" "znver1") 270 (and (eq_attr "znver1_decode" "double") 271 (and (eq_attr "type" "imovx") 272 (eq_attr "memory" "store")))) 273 "znver1-double,znver1-ieu|znver1-ieu,znver1-store") 274 275(define_insn_reservation "znver2_load_imov_double_store" 1 276 (and (eq_attr "cpu" "znver2") 277 (and (eq_attr "znver1_decode" "double") 278 (and (eq_attr "type" "imovx") 279 (eq_attr "memory" "store")))) 280 "znver1-double,znver1-ieu|znver1-ieu,znver2-store") 281 282(define_insn_reservation "znver1_load_imov_direct_store" 1 283 (and (eq_attr "cpu" "znver1") 284 (and (eq_attr "type" "imov,imovx") 285 (eq_attr "memory" "store"))) 286 "znver1-direct,znver1-ieu,znver1-store") 287 288(define_insn_reservation "znver2_load_imov_direct_store" 1 289 (and (eq_attr "cpu" "znver2") 290 (and (eq_attr "type" "imov,imovx") 291 (eq_attr "memory" "store"))) 292 "znver1-direct,znver1-ieu,znver2-store") 293 294(define_insn_reservation "znver1_load_imov_double_load" 5 295 (and (eq_attr "cpu" "znver1,znver2") 296 (and (eq_attr "znver1_decode" "double") 297 (and (eq_attr "type" "imovx") 298 (eq_attr "memory" "load")))) 299 "znver1-double,znver1-load,znver1-ieu|znver1-ieu") 300 301(define_insn_reservation "znver2_load_imov_double_load" 4 302 (and (eq_attr "cpu" "znver1,znver2") 303 (and (eq_attr "znver1_decode" "double") 304 (and (eq_attr "type" "imovx") 305 (eq_attr "memory" "load")))) 306 "znver1-double,znver1-load,znver1-ieu|znver1-ieu") 307 308(define_insn_reservation "znver1_load_imov_direct_load" 4 309 (and (eq_attr "cpu" "znver1,znver2") 310 (and (eq_attr "type" "imov,imovx") 311 (eq_attr "memory" "load"))) 312 "znver1-direct,znver1-load") 313 314;; INTEGER/GENERAL instructions 315;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST 316(define_insn_reservation "znver1_insn" 1 317 (and (eq_attr "cpu" "znver1,znver2") 318 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov") 319 (eq_attr "memory" "none,unknown"))) 320 "znver1-direct,znver1-ieu") 321 322(define_insn_reservation "znver1_insn_load" 5 323 (and (eq_attr "cpu" "znver1,znver2") 324 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov") 325 (eq_attr "memory" "load"))) 326 "znver1-direct,znver1-load,znver1-ieu") 327 328(define_insn_reservation "znver1_insn_store" 1 329 (and (eq_attr "cpu" "znver1") 330 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec") 331 (eq_attr "memory" "store"))) 332 "znver1-direct,znver1-ieu,znver1-store") 333 334(define_insn_reservation "znver2_insn_store" 1 335 (and (eq_attr "cpu" "znver2") 336 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec") 337 (eq_attr "memory" "store"))) 338 "znver1-direct,znver1-ieu,znver2-store") 339 340(define_insn_reservation "znver1_insn_both" 5 341 (and (eq_attr "cpu" "znver1") 342 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec") 343 (eq_attr "memory" "both"))) 344 "znver1-direct,znver1-load,znver1-ieu,znver1-store") 345 346(define_insn_reservation "znver2_insn_both" 5 347 (and (eq_attr "cpu" "znver2") 348 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec") 349 (eq_attr "memory" "both"))) 350 "znver1-direct,znver1-load,znver1-ieu,znver2-store") 351 352;; Fix me: Other vector type insns keeping latency 6 as of now. 353(define_insn_reservation "znver1_ieu_vector" 6 354 (and (eq_attr "cpu" "znver1") 355 (eq_attr "type" "other,str,multi")) 356 "znver1-vector,znver1-ivector") 357 358(define_insn_reservation "znver2_ieu_vector" 5 359 (and (eq_attr "cpu" "znver2") 360 (eq_attr "type" "other,str,multi")) 361 "znver1-vector,znver2-ivector") 362 363;; ALU1 register operands. 364(define_insn_reservation "znver1_alu1_vector" 3 365 (and (eq_attr "cpu" "znver1") 366 (and (eq_attr "znver1_decode" "vector") 367 (and (eq_attr "type" "alu1") 368 (eq_attr "memory" "none,unknown")))) 369 "znver1-vector,znver1-ivector") 370 371(define_insn_reservation "znver2_alu1_vector" 3 372 (and (eq_attr "cpu" "znver2") 373 (and (eq_attr "znver1_decode" "vector") 374 (and (eq_attr "type" "alu1") 375 (eq_attr "memory" "none,unknown")))) 376 "znver1-vector,znver2-ivector") 377 378(define_insn_reservation "znver1_alu1_double" 2 379 (and (eq_attr "cpu" "znver1,znver2") 380 (and (eq_attr "znver1_decode" "double") 381 (and (eq_attr "type" "alu1") 382 (eq_attr "memory" "none,unknown")))) 383 "znver1-double,znver1-ieu") 384 385(define_insn_reservation "znver1_alu1_direct" 1 386 (and (eq_attr "cpu" "znver1,znver2") 387 (and (eq_attr "znver1_decode" "direct") 388 (and (eq_attr "type" "alu1") 389 (eq_attr "memory" "none,unknown")))) 390 "znver1-direct,znver1-ieu") 391 392;; Branches : Fix me need to model conditional branches. 393(define_insn_reservation "znver1_branch" 1 394 (and (eq_attr "cpu" "znver1,znver2") 395 (and (eq_attr "type" "ibr") 396 (eq_attr "memory" "none"))) 397 "znver1-direct") 398 399;; Indirect branches check latencies. 400(define_insn_reservation "znver1_indirect_branch_mem" 6 401 (and (eq_attr "cpu" "znver1") 402 (and (eq_attr "type" "ibr") 403 (eq_attr "memory" "load"))) 404 "znver1-vector,znver1-ivector") 405 406(define_insn_reservation "znver2_indirect_branch_mem" 6 407 (and (eq_attr "cpu" "znver2") 408 (and (eq_attr "type" "ibr") 409 (eq_attr "memory" "load"))) 410 "znver1-vector,znver2-ivector") 411 412;; LEA executes in ALU units with 1 cycle latency. 413(define_insn_reservation "znver1_lea" 1 414 (and (eq_attr "cpu" "znver1,znver2") 415 (eq_attr "type" "lea")) 416 "znver1-direct,znver1-ieu") 417 418;; Other integer instrucions 419(define_insn_reservation "znver1_idirect" 1 420 (and (eq_attr "cpu" "znver1,znver2") 421 (and (eq_attr "unit" "integer,unknown") 422 (eq_attr "memory" "none,unknown"))) 423 "znver1-direct,znver1-ieu") 424 425;; Floating point 426(define_insn_reservation "znver1_fp_cmov" 6 427 (and (eq_attr "cpu" "znver1,znver2") 428 (eq_attr "type" "fcmov")) 429 "znver1-vector,znver1-fvector") 430 431(define_insn_reservation "znver1_fp_mov_direct_load" 8 432 (and (eq_attr "cpu" "znver1,znver2") 433 (and (eq_attr "znver1_decode" "direct") 434 (and (eq_attr "type" "fmov") 435 (eq_attr "memory" "load")))) 436 "znver1-direct,znver1-load,znver1-fp3|znver1-fp1") 437 438(define_insn_reservation "znver1_fp_mov_direct_store" 5 439 (and (eq_attr "cpu" "znver1") 440 (and (eq_attr "znver1_decode" "direct") 441 (and (eq_attr "type" "fmov") 442 (eq_attr "memory" "store")))) 443 "znver1-direct,znver1-fp2|znver1-fp3,znver1-store") 444(define_insn_reservation "znver2_fp_mov_direct_store" 5 445 (and (eq_attr "cpu" "znver2") 446 (and (eq_attr "znver1_decode" "direct") 447 (and (eq_attr "type" "fmov") 448 (eq_attr "memory" "store")))) 449 "znver1-direct,znver1-fp2|znver1-fp3,znver2-store") 450 451(define_insn_reservation "znver1_fp_mov_double" 4 452 (and (eq_attr "cpu" "znver1,znver2") 453 (and (eq_attr "znver1_decode" "double") 454 (and (eq_attr "type" "fmov") 455 (eq_attr "memory" "none")))) 456 "znver1-double,znver1-fp3") 457 458(define_insn_reservation "znver1_fp_mov_double_load" 12 459 (and (eq_attr "cpu" "znver1") 460 (and (eq_attr "znver1_decode" "double") 461 (and (eq_attr "type" "fmov") 462 (eq_attr "memory" "load")))) 463 "znver1-double,znver1-load,znver1-fp3") 464 465(define_insn_reservation "znver2_fp_mov_double_load" 12 466 (and (eq_attr "cpu" "znver2") 467 (and (eq_attr "znver1_decode" "double") 468 (and (eq_attr "type" "fmov") 469 (eq_attr "memory" "load")))) 470 "znver1-double,znver1-load,znver1-fp3") 471 472(define_insn_reservation "znver1_fp_mov_direct" 1 473 (and (eq_attr "cpu" "znver1,znver2") 474 (eq_attr "type" "fmov")) 475 "znver1-direct,znver1-fp3") 476 477;; TODO: AGU? 478(define_insn_reservation "znver1_fp_spc_direct" 5 479 (and (eq_attr "cpu" "znver1,znver2") 480 (and (eq_attr "type" "fpspc") 481 (eq_attr "memory" "store"))) 482 "znver1-direct,znver1-fp3,znver1-fp2") 483 484(define_insn_reservation "znver1_fp_insn_vector" 6 485 (and (eq_attr "cpu" "znver1") 486 (and (eq_attr "znver1_decode" "vector") 487 (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov"))) 488 "znver1-vector,znver1-fvector") 489(define_insn_reservation "znver2_fp_insn_vector" 6 490 (and (eq_attr "cpu" "znver2") 491 (and (eq_attr "znver1_decode" "vector") 492 (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov"))) 493 "znver1-vector,znver2-fvector") 494 495;; FABS 496(define_insn_reservation "znver1_fp_fsgn" 1 497 (and (eq_attr "cpu" "znver1,znver2") 498 (eq_attr "type" "fsgn")) 499 "znver1-direct,znver1-fp3") 500 501(define_insn_reservation "znver1_fp_fcmp" 2 502 (and (eq_attr "cpu" "znver1,znver2") 503 (and (eq_attr "memory" "none") 504 (and (eq_attr "znver1_decode" "double") 505 (eq_attr "type" "fcmp")))) 506 "znver1-double,znver1-fp0,znver1-fp2") 507 508(define_insn_reservation "znver1_fp_fcmp_load" 9 509 (and (eq_attr "cpu" "znver1,znver2") 510 (and (eq_attr "memory" "none") 511 (and (eq_attr "znver1_decode" "double") 512 (eq_attr "type" "fcmp")))) 513 "znver1-double,znver1-load, znver1-fp0,znver1-fp2") 514 515;;FADD FSUB FMUL 516(define_insn_reservation "znver1_fp_op_mul" 5 517 (and (eq_attr "cpu" "znver1,znver2") 518 (and (eq_attr "type" "fop,fmul") 519 (eq_attr "memory" "none"))) 520 "znver1-direct,znver1-fp0*5") 521 522(define_insn_reservation "znver1_fp_op_mul_load" 12 523 (and (eq_attr "cpu" "znver1,znver2") 524 (and (eq_attr "type" "fop,fmul") 525 (eq_attr "memory" "load"))) 526 "znver1-direct,znver1-load,znver1-fp0*5") 527 528(define_insn_reservation "znver1_fp_op_imul_load" 16 529 (and (eq_attr "cpu" "znver1,znver2") 530 (and (eq_attr "type" "fop,fmul") 531 (and (eq_attr "fp_int_src" "true") 532 (eq_attr "memory" "load")))) 533 "znver1-double,znver1-load,znver1-fp3,znver1-fp0") 534 535(define_insn_reservation "znver1_fp_op_div" 15 536 (and (eq_attr "cpu" "znver1,znver2") 537 (and (eq_attr "type" "fdiv") 538 (eq_attr "memory" "none"))) 539 "znver1-direct,znver1-fp3*15") 540 541(define_insn_reservation "znver1_fp_op_div_load" 22 542 (and (eq_attr "cpu" "znver1,znver2") 543 (and (eq_attr "type" "fdiv") 544 (eq_attr "memory" "load"))) 545 "znver1-direct,znver1-load,znver1-fp3*15") 546 547(define_insn_reservation "znver1_fp_op_idiv_load" 27 548 (and (eq_attr "cpu" "znver1") 549 (and (eq_attr "type" "fdiv") 550 (and (eq_attr "fp_int_src" "true") 551 (eq_attr "memory" "load")))) 552 "znver1-double,znver1-load,znver1-fp3*19") 553 554(define_insn_reservation "znver2_fp_op_idiv_load" 26 555 (and (eq_attr "cpu" "znver2") 556 (and (eq_attr "type" "fdiv") 557 (and (eq_attr "fp_int_src" "true") 558 (eq_attr "memory" "load")))) 559 "znver1-double,znver1-load,znver1-fp3*19") 560 561;; MMX, SSE, SSEn.n, AVX, AVX2 instructions 562(define_insn_reservation "znver1_fp_insn" 1 563 (and (eq_attr "cpu" "znver1,znver2") 564 (eq_attr "type" "mmx")) 565 "znver1-direct,znver1-fpu") 566 567(define_insn_reservation "znver1_mmx_add" 1 568 (and (eq_attr "cpu" "znver1,znver2") 569 (and (eq_attr "type" "mmxadd") 570 (eq_attr "memory" "none"))) 571 "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3") 572 573(define_insn_reservation "znver1_mmx_add_load" 8 574 (and (eq_attr "cpu" "znver1,znver2") 575 (and (eq_attr "type" "mmxadd") 576 (eq_attr "memory" "load"))) 577 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3") 578 579(define_insn_reservation "znver1_mmx_cmp" 1 580 (and (eq_attr "cpu" "znver1,znver2") 581 (and (eq_attr "type" "mmxcmp") 582 (eq_attr "memory" "none"))) 583 "znver1-direct,znver1-fp0|znver1-fp3") 584 585(define_insn_reservation "znver1_mmx_cmp_load" 8 586 (and (eq_attr "cpu" "znver1,znver2") 587 (and (eq_attr "type" "mmxcmp") 588 (eq_attr "memory" "load"))) 589 "znver1-direct,znver1-load,znver1-fp0|znver1-fp3") 590 591(define_insn_reservation "znver1_mmx_cvt_pck_shuf" 1 592 (and (eq_attr "cpu" "znver1,znver2") 593 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1") 594 (eq_attr "memory" "none"))) 595 "znver1-direct,znver1-fp1|znver1-fp2") 596 597(define_insn_reservation "znver1_mmx_cvt_pck_shuf_load" 8 598 (and (eq_attr "cpu" "znver1,znver2") 599 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1") 600 (eq_attr "memory" "load"))) 601 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") 602 603(define_insn_reservation "znver1_mmx_shift_move" 1 604 (and (eq_attr "cpu" "znver1,znver2") 605 (and (eq_attr "type" "mmxshft,mmxmov") 606 (eq_attr "memory" "none"))) 607 "znver1-direct,znver1-fp2") 608 609(define_insn_reservation "znver1_mmx_shift_move_load" 8 610 (and (eq_attr "cpu" "znver1,znver2") 611 (and (eq_attr "type" "mmxshft,mmxmov") 612 (eq_attr "memory" "load"))) 613 "znver1-direct,znver1-load,znver1-fp2") 614 615(define_insn_reservation "znver1_mmx_move_store" 1 616 (and (eq_attr "cpu" "znver1") 617 (and (eq_attr "type" "mmxshft,mmxmov") 618 (eq_attr "memory" "store,both"))) 619 "znver1-direct,znver1-fp2,znver1-store") 620(define_insn_reservation "znver2_mmx_move_store" 1 621 (and (eq_attr "cpu" "znver1") 622 (and (eq_attr "type" "mmxshft,mmxmov") 623 (eq_attr "memory" "store,both"))) 624 "znver1-direct,znver1-fp2,znver2-store") 625 626(define_insn_reservation "znver1_mmx_mul" 3 627 (and (eq_attr "cpu" "znver1,znver2") 628 (and (eq_attr "type" "mmxmul") 629 (eq_attr "memory" "none"))) 630 "znver1-direct,znver1-fp0*3") 631 632(define_insn_reservation "znver1_mmx_load" 10 633 (and (eq_attr "cpu" "znver1,znver2") 634 (and (eq_attr "type" "mmxmul") 635 (eq_attr "memory" "load"))) 636 "znver1-direct,znver1-load,znver1-fp0*3") 637 638;; TODO 639(define_insn_reservation "znver1_avx256_log" 1 640 (and (eq_attr "cpu" "znver1") 641 (and (eq_attr "mode" "V8SF,V4DF,OI") 642 (and (eq_attr "type" "sselog") 643 (eq_attr "memory" "none")))) 644 "znver1-double,znver1-fpu") 645 646(define_insn_reservation "znver1_avx256_log_load" 8 647 (and (eq_attr "cpu" "znver1") 648 (and (eq_attr "mode" "V8SF,V4DF,OI") 649 (and (eq_attr "type" "sselog") 650 (eq_attr "memory" "load")))) 651 "znver1-double,znver1-load,znver1-fpu") 652 653(define_insn_reservation "znver1_sse_log" 1 654 (and (eq_attr "cpu" "znver1,znver2") 655 (and (eq_attr "type" "sselog") 656 (eq_attr "memory" "none"))) 657 "znver1-direct,znver1-fpu") 658 659(define_insn_reservation "znver1_sse_log_load" 8 660 (and (eq_attr "cpu" "znver1,znver2") 661 (and (eq_attr "type" "sselog") 662 (eq_attr "memory" "load"))) 663 "znver1-direct,znver1-load,znver1-fpu") 664 665(define_insn_reservation "znver1_avx256_log1" 1 666 (and (eq_attr "cpu" "znver1") 667 (and (eq_attr "mode" "V8SF,V4DF,OI") 668 (and (eq_attr "type" "sselog1") 669 (eq_attr "memory" "none")))) 670 "znver1-double,znver1-fp1|znver1-fp2") 671 672(define_insn_reservation "znver1_avx256_log1_load" 8 673 (and (eq_attr "cpu" "znver1") 674 (and (eq_attr "mode" "V8SF,V4DF,OI") 675 (and (eq_attr "type" "sselog1") 676 (eq_attr "memory" "!none")))) 677 "znver1-double,znver1-load,znver1-fp1|znver1-fp2") 678 679(define_insn_reservation "znver1_sse_log1" 1 680 (and (eq_attr "cpu" "znver1,znver2") 681 (and (eq_attr "type" "sselog1") 682 (eq_attr "memory" "none"))) 683 "znver1-direct,znver1-fp1|znver1-fp2") 684 685(define_insn_reservation "znver1_sse_log1_load" 8 686 (and (eq_attr "cpu" "znver1,znver2") 687 (and (eq_attr "type" "sselog1") 688 (eq_attr "memory" "!none"))) 689 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") 690 691(define_insn_reservation "znver1_sse_comi" 1 692 (and (eq_attr "cpu" "znver1") 693 (and (eq_attr "mode" "SF,DF,V4SF,V2DF") 694 (and (eq_attr "prefix" "!vex") 695 (and (eq_attr "prefix_extra" "0") 696 (and (eq_attr "type" "ssecomi") 697 (eq_attr "memory" "none")))))) 698 "znver1-direct,znver1-fp0|znver1-fp1") 699 700(define_insn_reservation "znver1_sse_comi_load" 8 701 (and (ior (and (eq_attr "cpu" "znver1") 702 (eq_attr "mode" "SF,DF,V4SF,V2DF")) 703 (eq_attr "cpu" "znver2")) 704 (and (eq_attr "prefix_extra" "0") 705 (and (eq_attr "type" "ssecomi") 706 (eq_attr "memory" "load")))) 707 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") 708 709(define_insn_reservation "znver1_sse_comi_double" 2 710 (and (ior (and (eq_attr "cpu" "znver1") 711 (eq_attr "mode" "V4SF,V2DF,TI")) 712 (eq_attr "cpu" "znver2")) 713 (and (eq_attr "prefix" "vex") 714 (and (eq_attr "prefix_extra" "0") 715 (and (eq_attr "type" "ssecomi") 716 (eq_attr "memory" "none"))))) 717 "znver1-double,znver1-fp0|znver1-fp1") 718 719(define_insn_reservation "znver1_sse_comi_double_load" 10 720 (and (ior (and (eq_attr "cpu" "znver1") 721 (eq_attr "mode" "V4SF,V2DF,TI")) 722 (eq_attr "cpu" "znver2")) 723 (and (eq_attr "prefix" "vex") 724 (and (eq_attr "prefix_extra" "0") 725 (and (eq_attr "type" "ssecomi") 726 (eq_attr "memory" "load"))))) 727 "znver1-double,znver1-load,znver1-fp0|znver1-fp1") 728 729(define_insn_reservation "znver1_sse_test" 1 730 (and (ior (and (eq_attr "cpu" "znver1") 731 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) 732 (eq_attr "cpu" "znver2")) 733 (and (eq_attr "prefix_extra" "1") 734 (and (eq_attr "type" "ssecomi") 735 (eq_attr "memory" "none")))) 736 "znver1-direct,znver1-fp1|znver1-fp2") 737 738(define_insn_reservation "znver1_sse_test_load" 8 739 (and (ior (and (eq_attr "cpu" "znver1") 740 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) 741 (eq_attr "cpu" "znver2")) 742 (and (eq_attr "prefix_extra" "1") 743 (and (eq_attr "type" "ssecomi") 744 (eq_attr "memory" "load")))) 745 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") 746 747;; SSE moves 748;; Fix me: Need to revist this again some of the moves may be restricted 749;; to some fpu pipes. 750(define_insn_reservation "znver1_sse_mov" 2 751 (and (eq_attr "cpu" "znver1") 752 (and (eq_attr "mode" "SI") 753 (and (eq_attr "isa" "avx") 754 (and (eq_attr "type" "ssemov") 755 (eq_attr "memory" "none"))))) 756 "znver1-direct,znver1-ieu0") 757 758(define_insn_reservation "znver2_sse_mov" 1 759 (and (eq_attr "cpu" "znver2") 760 (and (eq_attr "mode" "SI") 761 (and (eq_attr "isa" "avx") 762 (and (eq_attr "type" "ssemov") 763 (eq_attr "memory" "none"))))) 764 "znver1-direct,znver1-ieu0") 765 766(define_insn_reservation "znver1_avx_mov" 2 767 (and (eq_attr "cpu" "znver1") 768 (and (eq_attr "mode" "TI") 769 (and (eq_attr "isa" "avx") 770 (and (eq_attr "type" "ssemov") 771 (and (match_operand:SI 1 "register_operand") 772 (eq_attr "memory" "none")))))) 773 "znver1-direct,znver1-ieu2") 774 775(define_insn_reservation "znver2_avx_mov" 1 776 (and (eq_attr "cpu" "znver2") 777 (and (eq_attr "mode" "TI") 778 (and (eq_attr "isa" "avx") 779 (and (eq_attr "type" "ssemov") 780 (and (match_operand:SI 1 "register_operand") 781 (eq_attr "memory" "none")))))) 782 "znver1-direct,znver1-ieu2") 783 784(define_insn_reservation "znver1_sseavx_mov" 1 785 (and (ior (and (eq_attr "cpu" "znver1") 786 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) 787 (eq_attr "cpu" "znver2")) 788 (and (eq_attr "type" "ssemov") 789 (eq_attr "memory" "none"))) 790 "znver1-direct,znver1-fpu") 791 792(define_insn_reservation "znver1_sseavx_mov_store" 1 793 (and (eq_attr "cpu" "znver1") 794 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") 795 (and (eq_attr "type" "ssemov") 796 (eq_attr "memory" "store")))) 797 "znver1-direct,znver1-fpu,znver1-store") 798(define_insn_reservation "znver2_sseavx_mov_store" 1 799 (and (eq_attr "cpu" "znver2") 800 (and (eq_attr "type" "ssemov") 801 (eq_attr "memory" "store"))) 802 "znver1-direct,znver1-fpu,znver2-store") 803 804(define_insn_reservation "znver1_sseavx_mov_load" 8 805 (and (ior (and (eq_attr "cpu" "znver1") 806 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) 807 (eq_attr "cpu" "znver2")) 808 (and (eq_attr "type" "ssemov") 809 (eq_attr "memory" "load"))) 810 "znver1-direct,znver1-load,znver1-fpu") 811 812(define_insn_reservation "znver1_avx256_mov" 1 813 (and (eq_attr "cpu" "znver1") 814 (and (eq_attr "mode" "V8SF,V4DF,OI") 815 (and (eq_attr "type" "ssemov") 816 (eq_attr "memory" "none")))) 817 "znver1-double,znver1-fpu") 818 819(define_insn_reservation "znver1_avx256_mov_store" 1 820 (and (eq_attr "cpu" "znver1") 821 (and (eq_attr "mode" "V8SF,V4DF,OI") 822 (and (eq_attr "type" "ssemov") 823 (eq_attr "memory" "store")))) 824 "znver1-double,znver1-fpu,znver1-store") 825 826(define_insn_reservation "znver1_avx256_mov_load" 8 827 (and (eq_attr "cpu" "znver1") 828 (and (eq_attr "mode" "V8SF,V4DF,OI") 829 (and (eq_attr "type" "ssemov") 830 (eq_attr "memory" "load")))) 831 "znver1-double,znver1-load,znver1-fpu") 832 833;; SSE add 834(define_insn_reservation "znver1_sseavx_add" 3 835 (and (ior (and (eq_attr "cpu" "znver1") 836 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) 837 (eq_attr "cpu" "znver2")) 838 (and (eq_attr "type" "sseadd") 839 (eq_attr "memory" "none"))) 840 "znver1-direct,znver1-fp2|znver1-fp3") 841 842(define_insn_reservation "znver1_sseavx_add_load" 10 843 (and (ior (and (eq_attr "cpu" "znver1") 844 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")) 845 (eq_attr "cpu" "znver2")) 846 (and (eq_attr "type" "sseadd") 847 (eq_attr "memory" "load"))) 848 "znver1-direct,znver1-load,znver1-fp2|znver1-fp3") 849 850(define_insn_reservation "znver1_avx256_add" 3 851 (and (eq_attr "cpu" "znver1") 852 (and (eq_attr "mode" "V8SF,V4DF,OI") 853 (and (eq_attr "type" "sseadd") 854 (eq_attr "memory" "none")))) 855 "znver1-double,znver1-fp2|znver1-fp3") 856 857(define_insn_reservation "znver1_avx256_add_load" 10 858 (and (eq_attr "cpu" "znver1") 859 (and (eq_attr "mode" "V8SF,V4DF,OI") 860 (and (eq_attr "type" "sseadd") 861 (eq_attr "memory" "load")))) 862 "znver1-double,znver1-load,znver1-fp2|znver1-fp3") 863 864(define_insn_reservation "znver1_sseavx_fma" 5 865 (and (ior (and (eq_attr "cpu" "znver1") 866 (eq_attr "mode" "SF,DF,V4SF,V2DF")) 867 (eq_attr "cpu" "znver2")) 868 (and (eq_attr "type" "ssemuladd") 869 (eq_attr "memory" "none"))) 870 "znver1-direct,znver1-fp0|znver1-fp1") 871 872(define_insn_reservation "znver1_sseavx_fma_load" 12 873 (and (ior (and (eq_attr "cpu" "znver1") 874 (eq_attr "mode" "SF,DF,V4SF,V2DF")) 875 (eq_attr "cpu" "znver2")) 876 (and (eq_attr "type" "ssemuladd") 877 (eq_attr "memory" "load"))) 878 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") 879 880(define_insn_reservation "znver1_avx256_fma" 5 881 (and (eq_attr "cpu" "znver1") 882 (and (eq_attr "mode" "V8SF,V4DF") 883 (and (eq_attr "type" "ssemuladd") 884 (eq_attr "memory" "none")))) 885 "znver1-double,znver1-fp0|znver1-fp1") 886 887(define_insn_reservation "znver1_avx256_fma_load" 12 888 (and (eq_attr "cpu" "znver1") 889 (and (eq_attr "mode" "V8SF,V4DF") 890 (and (eq_attr "type" "ssemuladd") 891 (eq_attr "memory" "load")))) 892 "znver1-double,znver1-load,znver1-fp0|znver1-fp1") 893 894(define_insn_reservation "znver1_sseavx_iadd" 1 895 (and (ior (and (eq_attr "cpu" "znver1") 896 (eq_attr "mode" "DI,TI")) 897 (eq_attr "cpu" "znver2")) 898 (and (eq_attr "type" "sseiadd") 899 (eq_attr "memory" "none"))) 900 "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3") 901 902(define_insn_reservation "znver1_sseavx_iadd_load" 8 903 (and (ior (and (eq_attr "cpu" "znver1") 904 (eq_attr "mode" "DI,TI")) 905 (eq_attr "cpu" "znver2")) 906 (and (eq_attr "type" "sseiadd") 907 (eq_attr "memory" "load"))) 908 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3") 909 910(define_insn_reservation "znver1_avx256_iadd" 1 911 (and (eq_attr "cpu" "znver1") 912 (and (eq_attr "mode" "OI") 913 (and (eq_attr "type" "sseiadd") 914 (eq_attr "memory" "none")))) 915 "znver1-double,znver1-fp0|znver1-fp1|znver1-fp3") 916 917(define_insn_reservation "znver1_avx256_iadd_load" 8 918 (and (eq_attr "cpu" "znver1") 919 (and (eq_attr "mode" "OI") 920 (and (eq_attr "type" "sseiadd") 921 (eq_attr "memory" "load")))) 922 "znver1-double,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3") 923 924;; SSE conversions. 925(define_insn_reservation "znver1_ssecvtsf_si_load" 12 926 (and (eq_attr "cpu" "znver1,znver2") 927 (and (eq_attr "mode" "SI") 928 (and (eq_attr "type" "sseicvt") 929 (and (match_operand:SF 1 "memory_operand") 930 (eq_attr "memory" "load"))))) 931 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0") 932 933(define_insn_reservation "znver1_ssecvtdf_si" 5 934 (and (eq_attr "cpu" "znver1") 935 (and (eq_attr "mode" "SI") 936 (and (match_operand:DF 1 "register_operand") 937 (and (eq_attr "type" "sseicvt") 938 (eq_attr "memory" "none"))))) 939 "znver1-double,znver1-fp3,znver1-ieu0") 940(define_insn_reservation "znver2_ssecvtdf_si" 4 941 (and (eq_attr "cpu" "znver2") 942 (and (eq_attr "mode" "SI") 943 (and (match_operand:DF 1 "register_operand") 944 (and (eq_attr "type" "sseicvt") 945 (eq_attr "memory" "none"))))) 946 "znver1-double,znver1-fp3,znver1-ieu0") 947 948(define_insn_reservation "znver1_ssecvtdf_si_load" 12 949 (and (eq_attr "cpu" "znver1") 950 (and (eq_attr "mode" "SI") 951 (and (eq_attr "type" "sseicvt") 952 (and (match_operand:DF 1 "memory_operand") 953 (eq_attr "memory" "load"))))) 954 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0") 955 956(define_insn_reservation "znver2_ssecvtdf_si_load" 11 957 (and (eq_attr "cpu" "znver2") 958 (and (eq_attr "mode" "SI") 959 (and (eq_attr "type" "sseicvt") 960 (and (match_operand:DF 1 "memory_operand") 961 (eq_attr "memory" "load"))))) 962 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0") 963 964;; All other used ssecvt fp3 pipes 965;; Check: Need to revisit this again. 966;; Some SSE converts may use different pipe combinations. 967(define_insn_reservation "znver1_ssecvt" 4 968 (and (eq_attr "cpu" "znver1") 969 (and (eq_attr "type" "ssecvt") 970 (eq_attr "memory" "none"))) 971 "znver1-direct,znver1-fp3") 972 973(define_insn_reservation "znver2_ssecvt" 3 974 (and (eq_attr "cpu" "znver2") 975 (and (eq_attr "type" "ssecvt") 976 (eq_attr "memory" "none"))) 977 "znver1-direct,znver1-fp3") 978 979(define_insn_reservation "znver1_ssecvt_load" 11 980 (and (eq_attr "cpu" "znver1") 981 (and (eq_attr "type" "ssecvt") 982 (eq_attr "memory" "load"))) 983 "znver1-direct,znver1-load,znver1-fp3") 984 985(define_insn_reservation "znver2_ssecvt_load" 11 986 (and (eq_attr "cpu" "znver2") 987 (and (eq_attr "type" "ssecvt") 988 (eq_attr "memory" "load"))) 989 "znver1-direct,znver1-load,znver1-fp3") 990 991;; SSE div 992(define_insn_reservation "znver1_ssediv_ss_ps" 10 993 (and (ior (and (eq_attr "cpu" "znver1") 994 (eq_attr "mode" "V4SF,SF")) 995 (and (eq_attr "cpu" "znver2") 996 (eq_attr "mode" "V8SF,V4SF,SF"))) 997 (and (eq_attr "type" "ssediv") 998 (eq_attr "memory" "none"))) 999 "znver1-direct,znver1-fp3*10") 1000 1001(define_insn_reservation "znver1_ssediv_ss_ps_load" 17 1002 (and (ior (and (eq_attr "cpu" "znver1") 1003 (eq_attr "mode" "V4SF,SF")) 1004 (and (eq_attr "cpu" "znver2") 1005 (eq_attr "mode" "V8SF,V4SF,SF"))) 1006 (and (eq_attr "type" "ssediv") 1007 (eq_attr "memory" "load"))) 1008 "znver1-direct,znver1-load,znver1-fp3*10") 1009 1010(define_insn_reservation "znver1_ssediv_sd_pd" 13 1011 (and (ior (and (eq_attr "cpu" "znver1") 1012 (eq_attr "mode" "V2DF,DF")) 1013 (and (eq_attr "cpu" "znver2") 1014 (eq_attr "mode" "V4DF,V2DF,DF"))) 1015 (and (eq_attr "type" "ssediv") 1016 (eq_attr "memory" "none"))) 1017 "znver1-direct,znver1-fp3*13") 1018 1019(define_insn_reservation "znver1_ssediv_sd_pd_load" 20 1020 (and (ior (and (eq_attr "cpu" "znver1") 1021 (eq_attr "mode" "V2DF,DF")) 1022 (and (eq_attr "cpu" "znver2") 1023 (eq_attr "mode" "V4DF,V2DF,DF"))) 1024 (and (eq_attr "type" "ssediv") 1025 (eq_attr "memory" "load"))) 1026 "znver1-direct,znver1-load,znver1-fp3*13") 1027 1028(define_insn_reservation "znver1_ssediv_avx256_ps" 12 1029 (and (eq_attr "cpu" "znver1") 1030 (and (eq_attr "mode" "V8SF") 1031 (and (eq_attr "memory" "none") 1032 (eq_attr "type" "ssediv")))) 1033 "znver1-double,znver1-fp3*12") 1034 1035(define_insn_reservation "znver1_ssediv_avx256_ps_load" 19 1036 (and (eq_attr "cpu" "znver1") 1037 (and (eq_attr "mode" "V8SF") 1038 (and (eq_attr "type" "ssediv") 1039 (eq_attr "memory" "load")))) 1040 "znver1-double,znver1-load,znver1-fp3*12") 1041 1042(define_insn_reservation "znver1_ssediv_avx256_pd" 15 1043 (and (eq_attr "cpu" "znver1") 1044 (and (eq_attr "mode" "V4DF") 1045 (and (eq_attr "type" "ssediv") 1046 (eq_attr "memory" "none")))) 1047 "znver1-double,znver1-fp3*15") 1048 1049(define_insn_reservation "znver1_ssediv_avx256_pd_load" 22 1050 (and (eq_attr "cpu" "znver1") 1051 (and (eq_attr "mode" "V4DF") 1052 (and (eq_attr "type" "ssediv") 1053 (eq_attr "memory" "load")))) 1054 "znver1-double,znver1-load,znver1-fp3*15") 1055;; SSE MUL 1056(define_insn_reservation "znver1_ssemul_ss_ps" 3 1057 (and (ior (and (eq_attr "cpu" "znver1") 1058 (eq_attr "mode" "V4SF,SF")) 1059 (and (eq_attr "cpu" "znver2") 1060 (eq_attr "mode" "V8SF,V4SF,SF,V4DF,V2DF,DF"))) 1061 (and (eq_attr "type" "ssemul") 1062 (eq_attr "memory" "none"))) 1063 "znver1-direct,(znver1-fp0|znver1-fp1)*3") 1064 1065(define_insn_reservation "znver1_ssemul_ss_ps_load" 10 1066 (and (ior (and (eq_attr "cpu" "znver1") 1067 (eq_attr "mode" "V4SF,SF")) 1068 (and (eq_attr "cpu" "znver2") 1069 (eq_attr "mode" "V8SF,V4SF,SF"))) 1070 (and (eq_attr "type" "ssemul") 1071 (eq_attr "memory" "load"))) 1072 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3") 1073 1074(define_insn_reservation "znver1_ssemul_avx256_ps" 3 1075 (and (eq_attr "cpu" "znver1") 1076 (and (eq_attr "mode" "V8SF") 1077 (and (eq_attr "type" "ssemul") 1078 (eq_attr "memory" "none")))) 1079 "znver1-double,(znver1-fp0|znver1-fp1)*3") 1080 1081(define_insn_reservation "znver1_ssemul_avx256_ps_load" 10 1082 (and (eq_attr "cpu" "znver1") 1083 (and (eq_attr "mode" "V8SF") 1084 (and (eq_attr "type" "ssemul") 1085 (eq_attr "memory" "load")))) 1086 "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*3") 1087 1088(define_insn_reservation "znver1_ssemul_sd_pd" 4 1089 (and (eq_attr "cpu" "znver1") 1090 (and (eq_attr "mode" "V2DF,DF") 1091 (and (eq_attr "type" "ssemul") 1092 (eq_attr "memory" "none")))) 1093 "znver1-direct,(znver1-fp0|znver1-fp1)*4") 1094 1095(define_insn_reservation "znver1_ssemul_sd_pd_load" 11 1096 (and (eq_attr "cpu" "znver1") 1097 (and (eq_attr "mode" "V2DF,DF") 1098 (and (eq_attr "type" "ssemul") 1099 (eq_attr "memory" "load")))) 1100 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*4") 1101 1102(define_insn_reservation "znver2_ssemul_sd_pd" 3 1103 (and (eq_attr "cpu" "znver2") 1104 (and (eq_attr "type" "ssemul") 1105 (eq_attr "memory" "none"))) 1106 "znver1-direct,(znver1-fp0|znver1-fp1)*3") 1107 1108(define_insn_reservation "znver2_ssemul_sd_pd_load" 10 1109 (and (eq_attr "cpu" "znver2") 1110 (and (eq_attr "type" "ssemul") 1111 (eq_attr "memory" "load"))) 1112 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3") 1113 1114(define_insn_reservation "znver1_ssemul_avx256_pd" 5 1115 (and (eq_attr "cpu" "znver1") 1116 (and (eq_attr "mode" "V4DF") 1117 (and (eq_attr "type" "ssemul") 1118 (eq_attr "memory" "none")))) 1119 "znver1-double,(znver1-fp0|znver1-fp1)*4") 1120 1121(define_insn_reservation "znver1_ssemul_avx256_pd_load" 12 1122 (and (eq_attr "cpu" "znver1") 1123 (and (eq_attr "mode" "V4DF") 1124 (and (eq_attr "type" "ssemul") 1125 (eq_attr "memory" "load")))) 1126 "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*4") 1127 1128;;SSE imul 1129(define_insn_reservation "znver1_sseimul" 3 1130 (and (ior (and (eq_attr "cpu" "znver1") 1131 (eq_attr "mode" "TI")) 1132 (and (eq_attr "cpu" "znver2") 1133 (eq_attr "mode" "TI,OI"))) 1134 (and (eq_attr "type" "sseimul") 1135 (eq_attr "memory" "none"))) 1136 "znver1-direct,znver1-fp0*3") 1137 1138(define_insn_reservation "znver1_sseimul_avx256" 4 1139 (and (eq_attr "cpu" "znver1,znver2") 1140 (and (eq_attr "mode" "OI") 1141 (and (eq_attr "type" "sseimul") 1142 (eq_attr "memory" "none")))) 1143 "znver1-double,znver1-fp0*4") 1144 1145(define_insn_reservation "znver1_sseimul_load" 10 1146 (and (ior (and (eq_attr "cpu" "znver1") 1147 (eq_attr "mode" "TI")) 1148 (and (eq_attr "cpu" "znver2") 1149 (eq_attr "mode" "TI,OI"))) 1150 (and (eq_attr "type" "sseimul") 1151 (eq_attr "memory" "load"))) 1152 "znver1-direct,znver1-load,znver1-fp0*3") 1153 1154(define_insn_reservation "znver1_sseimul_avx256_load" 11 1155 (and (eq_attr "cpu" "znver1,znver2") 1156 (and (eq_attr "mode" "OI") 1157 (and (eq_attr "type" "sseimul") 1158 (eq_attr "memory" "load")))) 1159 "znver1-double,znver1-load,znver1-fp0*4") 1160 1161(define_insn_reservation "znver1_sseimul_di" 3 1162 (and (eq_attr "cpu" "znver1,znver2") 1163 (and (eq_attr "mode" "DI") 1164 (and (eq_attr "memory" "none") 1165 (eq_attr "type" "sseimul")))) 1166 "znver1-direct,znver1-fp0*3") 1167 1168(define_insn_reservation "znver1_sseimul_load_di" 10 1169 (and (eq_attr "cpu" "znver1,znver2") 1170 (and (eq_attr "mode" "DI") 1171 (and (eq_attr "type" "sseimul") 1172 (eq_attr "memory" "load")))) 1173 "znver1-direct,znver1-load,znver1-fp0*3") 1174 1175;; SSE compares 1176(define_insn_reservation "znver1_sse_cmp" 1 1177 (and (ior (and (eq_attr "cpu" "znver1") 1178 (eq_attr "mode" "SF,DF,V4SF,V2DF")) 1179 (and (eq_attr "cpu" "znver2") 1180 (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF"))) 1181 (and (eq_attr "type" "ssecmp") 1182 (eq_attr "memory" "none"))) 1183 "znver1-direct,znver1-fp0|znver1-fp1") 1184 1185(define_insn_reservation "znver1_sse_cmp_load" 8 1186 (and (ior (and (eq_attr "cpu" "znver1") 1187 (eq_attr "mode" "SF,DF,V4SF,V2DF")) 1188 (and (eq_attr "cpu" "znver2") 1189 (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF"))) 1190 (and (eq_attr "type" "ssecmp") 1191 (eq_attr "memory" "load"))) 1192 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") 1193 1194(define_insn_reservation "znver1_sse_cmp_avx256" 1 1195 (and (eq_attr "cpu" "znver1") 1196 (and (eq_attr "mode" "V8SF,V4DF") 1197 (and (eq_attr "type" "ssecmp") 1198 (eq_attr "memory" "none")))) 1199 "znver1-double,znver1-fp0|znver1-fp1") 1200 1201(define_insn_reservation "znver1_sse_cmp_avx256_load" 8 1202 (and (eq_attr "cpu" "znver1") 1203 (and (eq_attr "mode" "V8SF,V4DF") 1204 (and (eq_attr "type" "ssecmp") 1205 (eq_attr "memory" "load")))) 1206 "znver1-double,znver1-load,znver1-fp0|znver1-fp1") 1207 1208(define_insn_reservation "znver1_sse_icmp" 1 1209 (and (ior (and (eq_attr "cpu" "znver1") 1210 (eq_attr "mode" "QI,HI,SI,DI,TI")) 1211 (and (eq_attr "cpu" "znver2") 1212 (eq_attr "mode" "QI,HI,SI,DI,TI,OI"))) 1213 (and (eq_attr "type" "ssecmp") 1214 (eq_attr "memory" "none"))) 1215 "znver1-direct,znver1-fp0|znver1-fp3") 1216 1217(define_insn_reservation "znver1_sse_icmp_load" 8 1218 (and (ior (and (eq_attr "cpu" "znver1") 1219 (eq_attr "mode" "QI,HI,SI,DI,TI")) 1220 (and (eq_attr "cpu" "znver2") 1221 (eq_attr "mode" "QI,HI,SI,DI,TI,OI"))) 1222 (and (eq_attr "type" "ssecmp") 1223 (eq_attr "memory" "load"))) 1224 "znver1-direct,znver1-load,znver1-fp0|znver1-fp3") 1225 1226(define_insn_reservation "znver1_sse_icmp_avx256" 1 1227 (and (eq_attr "cpu" "znver1") 1228 (and (eq_attr "mode" "OI") 1229 (and (eq_attr "type" "ssecmp") 1230 (eq_attr "memory" "none")))) 1231 "znver1-double,znver1-fp0|znver1-fp3") 1232 1233(define_insn_reservation "znver1_sse_icmp_avx256_load" 8 1234 (and (eq_attr "cpu" "znver1") 1235 (and (eq_attr "mode" "OI") 1236 (and (eq_attr "type" "ssecmp") 1237 (eq_attr "memory" "load")))) 1238 "znver1-double,znver1-load,znver1-fp0|znver1-fp3") 1239