1 /* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 4 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 Under Section 7 of GPL version 3, you are granted additional 19 permissions described in the GCC Runtime Library Exception, version 20 3.1, as published by the Free Software Foundation. 21 22 You should have received a copy of the GNU General Public License and 23 a copy of the GCC Runtime Library Exception along with this program; 24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 25 <http://www.gnu.org/licenses/>. */ 26 27 /* The purpose of this file is to define the characteristics of the i386, 28 independent of assembler syntax or operating system. 29 30 Three other files build on this one to describe a specific assembler syntax: 31 bsd386.h, att386.h, and sun386.h. 32 33 The actual tm.h file for a particular system should include 34 this file, and then the file for the appropriate assembler syntax. 35 36 Many macros that specify assembler syntax are omitted entirely from 37 this file because they really belong in the files for particular 38 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 39 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 40 that start with ASM_ or end in ASM_OP. */ 41 42 /* Redefines for option macros. */ 43 44 #define TARGET_64BIT OPTION_ISA_64BIT 45 #define TARGET_MMX OPTION_ISA_MMX 46 #define TARGET_3DNOW OPTION_ISA_3DNOW 47 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A 48 #define TARGET_SSE OPTION_ISA_SSE 49 #define TARGET_SSE2 OPTION_ISA_SSE2 50 #define TARGET_SSE3 OPTION_ISA_SSE3 51 #define TARGET_SSSE3 OPTION_ISA_SSSE3 52 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1 53 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2 54 #define TARGET_AVX OPTION_ISA_AVX 55 #define TARGET_FMA OPTION_ISA_FMA 56 #define TARGET_SSE4A OPTION_ISA_SSE4A 57 #define TARGET_FMA4 OPTION_ISA_FMA4 58 #define TARGET_XOP OPTION_ISA_XOP 59 #define TARGET_LWP OPTION_ISA_LWP 60 #define TARGET_ROUND OPTION_ISA_ROUND 61 #define TARGET_ABM OPTION_ISA_ABM 62 #define TARGET_POPCNT OPTION_ISA_POPCNT 63 #define TARGET_SAHF OPTION_ISA_SAHF 64 #define TARGET_MOVBE OPTION_ISA_MOVBE 65 #define TARGET_CRC32 OPTION_ISA_CRC32 66 #define TARGET_AES OPTION_ISA_AES 67 #define TARGET_PCLMUL OPTION_ISA_PCLMUL 68 #define TARGET_CMPXCHG16B OPTION_ISA_CX16 69 70 71 /* SSE4.1 defines round instructions */ 72 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 73 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) 74 75 #include "config/vxworks-dummy.h" 76 77 /* Algorithm to expand string function with. */ 78 enum stringop_alg 79 { 80 no_stringop, 81 libcall, 82 rep_prefix_1_byte, 83 rep_prefix_4_byte, 84 rep_prefix_8_byte, 85 loop_1_byte, 86 loop, 87 unrolled_loop 88 }; 89 90 #define NAX_STRINGOP_ALGS 4 91 92 /* Specify what algorithm to use for stringops on known size. 93 When size is unknown, the UNKNOWN_SIZE alg is used. When size is 94 known at compile time or estimated via feedback, the SIZE array 95 is walked in order until MAX is greater then the estimate (or -1 96 means infinity). Corresponding ALG is used then. 97 For example initializer: 98 {{256, loop}, {-1, rep_prefix_4_byte}} 99 will use loop for blocks smaller or equal to 256 bytes, rep prefix will 100 be used otherwise. */ 101 struct stringop_algs 102 { 103 const enum stringop_alg unknown_size; 104 const struct stringop_strategy { 105 const int max; 106 const enum stringop_alg alg; 107 } size [NAX_STRINGOP_ALGS]; 108 }; 109 110 /* Define the specific costs for a given cpu */ 111 112 struct processor_costs { 113 const int add; /* cost of an add instruction */ 114 const int lea; /* cost of a lea instruction */ 115 const int shift_var; /* variable shift costs */ 116 const int shift_const; /* constant shift costs */ 117 const int mult_init[5]; /* cost of starting a multiply 118 in QImode, HImode, SImode, DImode, TImode*/ 119 const int mult_bit; /* cost of multiply per each bit set */ 120 const int divide[5]; /* cost of a divide/mod 121 in QImode, HImode, SImode, DImode, TImode*/ 122 int movsx; /* The cost of movsx operation. */ 123 int movzx; /* The cost of movzx operation. */ 124 const int large_insn; /* insns larger than this cost more */ 125 const int move_ratio; /* The threshold of number of scalar 126 memory-to-memory move insns. */ 127 const int movzbl_load; /* cost of loading using movzbl */ 128 const int int_load[3]; /* cost of loading integer registers 129 in QImode, HImode and SImode relative 130 to reg-reg move (2). */ 131 const int int_store[3]; /* cost of storing integer register 132 in QImode, HImode and SImode */ 133 const int fp_move; /* cost of reg,reg fld/fst */ 134 const int fp_load[3]; /* cost of loading FP register 135 in SFmode, DFmode and XFmode */ 136 const int fp_store[3]; /* cost of storing FP register 137 in SFmode, DFmode and XFmode */ 138 const int mmx_move; /* cost of moving MMX register. */ 139 const int mmx_load[2]; /* cost of loading MMX register 140 in SImode and DImode */ 141 const int mmx_store[2]; /* cost of storing MMX register 142 in SImode and DImode */ 143 const int sse_move; /* cost of moving SSE register. */ 144 const int sse_load[3]; /* cost of loading SSE register 145 in SImode, DImode and TImode*/ 146 const int sse_store[3]; /* cost of storing SSE register 147 in SImode, DImode and TImode*/ 148 const int mmxsse_to_integer; /* cost of moving mmxsse register to 149 integer and vice versa. */ 150 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 151 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 152 const int prefetch_block; /* bytes moved to cache for prefetch. */ 153 const int simultaneous_prefetches; /* number of parallel prefetch 154 operations. */ 155 const int branch_cost; /* Default value for BRANCH_COST. */ 156 const int fadd; /* cost of FADD and FSUB instructions. */ 157 const int fmul; /* cost of FMUL instruction. */ 158 const int fdiv; /* cost of FDIV instruction. */ 159 const int fabs; /* cost of FABS instruction. */ 160 const int fchs; /* cost of FCHS instruction. */ 161 const int fsqrt; /* cost of FSQRT instruction. */ 162 /* Specify what algorithm 163 to use for stringops on unknown size. */ 164 struct stringop_algs memcpy[2], memset[2]; 165 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding 166 load and store. */ 167 const int scalar_load_cost; /* Cost of scalar load. */ 168 const int scalar_store_cost; /* Cost of scalar store. */ 169 const int vec_stmt_cost; /* Cost of any vector operation, excluding 170 load, store, vector-to-scalar and 171 scalar-to-vector operation. */ 172 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ 173 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ 174 const int vec_align_load_cost; /* Cost of aligned vector load. */ 175 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ 176 const int vec_store_cost; /* Cost of vector store. */ 177 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 178 cost model. */ 179 const int cond_not_taken_branch_cost;/* Cost of not taken branch for 180 vectorizer cost model. */ 181 }; 182 183 extern const struct processor_costs *ix86_cost; 184 extern const struct processor_costs ix86_size_cost; 185 186 #define ix86_cur_cost() \ 187 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 188 189 /* Macros used in the machine description to test the flags. */ 190 191 /* configure can arrange to make this 2, to force a 486. */ 192 193 #ifndef TARGET_CPU_DEFAULT 194 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic 195 #endif 196 197 #ifndef TARGET_FPMATH_DEFAULT 198 #define TARGET_FPMATH_DEFAULT \ 199 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 200 #endif 201 202 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 203 204 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 205 compile-time constant. */ 206 #ifdef IN_LIBGCC2 207 #undef TARGET_64BIT 208 #ifdef __x86_64__ 209 #define TARGET_64BIT 1 210 #else 211 #define TARGET_64BIT 0 212 #endif 213 #else 214 #ifndef TARGET_BI_ARCH 215 #undef TARGET_64BIT 216 #if TARGET_64BIT_DEFAULT 217 #define TARGET_64BIT 1 218 #else 219 #define TARGET_64BIT 0 220 #endif 221 #endif 222 #endif 223 224 #define HAS_LONG_COND_BRANCH 1 225 #define HAS_LONG_UNCOND_BRANCH 1 226 227 #define TARGET_386 (ix86_tune == PROCESSOR_I386) 228 #define TARGET_486 (ix86_tune == PROCESSOR_I486) 229 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 230 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 231 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 232 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) 233 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 234 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 235 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) 236 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 237 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 238 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 239 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) 240 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) 241 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) 242 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 243 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) 244 245 /* Feature tests against the various tunings. */ 246 enum ix86_tune_indices { 247 X86_TUNE_USE_LEAVE, 248 X86_TUNE_PUSH_MEMORY, 249 X86_TUNE_ZERO_EXTEND_WITH_AND, 250 X86_TUNE_UNROLL_STRLEN, 251 X86_TUNE_DEEP_BRANCH_PREDICTION, 252 X86_TUNE_BRANCH_PREDICTION_HINTS, 253 X86_TUNE_DOUBLE_WITH_ADD, 254 X86_TUNE_USE_SAHF, 255 X86_TUNE_MOVX, 256 X86_TUNE_PARTIAL_REG_STALL, 257 X86_TUNE_PARTIAL_FLAG_REG_STALL, 258 X86_TUNE_USE_HIMODE_FIOP, 259 X86_TUNE_USE_SIMODE_FIOP, 260 X86_TUNE_USE_MOV0, 261 X86_TUNE_USE_CLTD, 262 X86_TUNE_USE_XCHGB, 263 X86_TUNE_SPLIT_LONG_MOVES, 264 X86_TUNE_READ_MODIFY_WRITE, 265 X86_TUNE_READ_MODIFY, 266 X86_TUNE_PROMOTE_QIMODE, 267 X86_TUNE_FAST_PREFIX, 268 X86_TUNE_SINGLE_STRINGOP, 269 X86_TUNE_QIMODE_MATH, 270 X86_TUNE_HIMODE_MATH, 271 X86_TUNE_PROMOTE_QI_REGS, 272 X86_TUNE_PROMOTE_HI_REGS, 273 X86_TUNE_ADD_ESP_4, 274 X86_TUNE_ADD_ESP_8, 275 X86_TUNE_SUB_ESP_4, 276 X86_TUNE_SUB_ESP_8, 277 X86_TUNE_INTEGER_DFMODE_MOVES, 278 X86_TUNE_PARTIAL_REG_DEPENDENCY, 279 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, 280 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL, 281 X86_TUNE_SSE_SPLIT_REGS, 282 X86_TUNE_SSE_TYPELESS_STORES, 283 X86_TUNE_SSE_LOAD0_BY_PXOR, 284 X86_TUNE_MEMORY_MISMATCH_STALL, 285 X86_TUNE_PROLOGUE_USING_MOVE, 286 X86_TUNE_EPILOGUE_USING_MOVE, 287 X86_TUNE_SHIFT1, 288 X86_TUNE_USE_FFREEP, 289 X86_TUNE_INTER_UNIT_MOVES, 290 X86_TUNE_INTER_UNIT_CONVERSIONS, 291 X86_TUNE_FOUR_JUMP_LIMIT, 292 X86_TUNE_SCHEDULE, 293 X86_TUNE_USE_BT, 294 X86_TUNE_USE_INCDEC, 295 X86_TUNE_PAD_RETURNS, 296 X86_TUNE_EXT_80387_CONSTANTS, 297 X86_TUNE_SHORTEN_X87_SSE, 298 X86_TUNE_AVOID_VECTOR_DECODE, 299 X86_TUNE_PROMOTE_HIMODE_IMUL, 300 X86_TUNE_SLOW_IMUL_IMM32_MEM, 301 X86_TUNE_SLOW_IMUL_IMM8, 302 X86_TUNE_MOVE_M1_VIA_OR, 303 X86_TUNE_NOT_UNPAIRABLE, 304 X86_TUNE_NOT_VECTORMODE, 305 X86_TUNE_USE_VECTOR_FP_CONVERTS, 306 X86_TUNE_USE_VECTOR_CONVERTS, 307 X86_TUNE_FUSE_CMP_AND_BRANCH, 308 X86_TUNE_OPT_AGU, 309 310 X86_TUNE_LAST 311 }; 312 313 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; 314 315 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 316 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 317 #define TARGET_ZERO_EXTEND_WITH_AND \ 318 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 319 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 320 #define TARGET_DEEP_BRANCH_PREDICTION \ 321 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION] 322 #define TARGET_BRANCH_PREDICTION_HINTS \ 323 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 324 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 325 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 326 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 327 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 328 #define TARGET_PARTIAL_FLAG_REG_STALL \ 329 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 330 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 331 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 332 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 333 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 334 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 335 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 336 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 337 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 338 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 339 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 340 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 341 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 342 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 343 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 344 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 345 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4] 346 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8] 347 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4] 348 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8] 349 #define TARGET_INTEGER_DFMODE_MOVES \ 350 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 351 #define TARGET_PARTIAL_REG_DEPENDENCY \ 352 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 353 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 354 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 355 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \ 356 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL] 357 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 358 #define TARGET_SSE_TYPELESS_STORES \ 359 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 360 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 361 #define TARGET_MEMORY_MISMATCH_STALL \ 362 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 363 #define TARGET_PROLOGUE_USING_MOVE \ 364 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 365 #define TARGET_EPILOGUE_USING_MOVE \ 366 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 367 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 368 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 369 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] 370 #define TARGET_INTER_UNIT_CONVERSIONS\ 371 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 372 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 373 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 374 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 375 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 376 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 377 #define TARGET_EXT_80387_CONSTANTS \ 378 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 379 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE] 380 #define TARGET_AVOID_VECTOR_DECODE \ 381 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 382 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 383 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 384 #define TARGET_SLOW_IMUL_IMM32_MEM \ 385 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 386 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 387 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 388 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 389 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 390 #define TARGET_USE_VECTOR_FP_CONVERTS \ 391 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 392 #define TARGET_USE_VECTOR_CONVERTS \ 393 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 394 #define TARGET_FUSE_CMP_AND_BRANCH \ 395 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] 396 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 397 398 /* Feature tests against the various architecture variations. */ 399 enum ix86_arch_indices { 400 X86_ARCH_CMOV, 401 X86_ARCH_CMPXCHG, 402 X86_ARCH_CMPXCHG8B, 403 X86_ARCH_XADD, 404 X86_ARCH_BSWAP, 405 406 X86_ARCH_LAST 407 }; 408 409 extern unsigned char ix86_arch_features[X86_ARCH_LAST]; 410 411 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 412 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 413 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 414 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 415 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 416 417 /* For sane SSE instruction set generation we need fcomi instruction. 418 It is safe to enable all CMOVE instructions. */ 419 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE) 420 421 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 422 423 extern int x86_prefetch_sse; 424 425 #define TARGET_PREFETCH_SSE x86_prefetch_sse 426 427 #define ASSEMBLER_DIALECT (ix86_asm_dialect) 428 429 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 430 #define TARGET_MIX_SSE_I387 \ 431 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 432 433 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 434 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 435 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 436 #define TARGET_SUN_TLS 0 437 438 extern int ix86_isa_flags; 439 440 #ifndef TARGET_64BIT_DEFAULT 441 #define TARGET_64BIT_DEFAULT 0 442 #endif 443 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 444 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 445 #endif 446 447 /* Fence to use after loop using storent. */ 448 449 extern tree x86_mfence; 450 #define FENCE_FOLLOWING_MOVNT x86_mfence 451 452 /* Once GDB has been enhanced to deal with functions without frame 453 pointers, we can change this to allow for elimination of 454 the frame pointer in leaf functions. */ 455 #define TARGET_DEFAULT 0 456 457 /* Extra bits to force. */ 458 #define TARGET_SUBTARGET_DEFAULT 0 459 #define TARGET_SUBTARGET_ISA_DEFAULT 0 460 461 /* Extra bits to force on w/ 32-bit mode. */ 462 #define TARGET_SUBTARGET32_DEFAULT 0 463 #define TARGET_SUBTARGET32_ISA_DEFAULT 0 464 465 /* Extra bits to force on w/ 64-bit mode. */ 466 #define TARGET_SUBTARGET64_DEFAULT 0 467 #define TARGET_SUBTARGET64_ISA_DEFAULT 0 468 469 /* This is not really a target flag, but is done this way so that 470 it's analogous to similar code for Mach-O on PowerPC. darwin.h 471 redefines this to 1. */ 472 #define TARGET_MACHO 0 473 474 /* Likewise, for the Windows 64-bit ABI. */ 475 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 476 477 /* Available call abi. */ 478 enum calling_abi 479 { 480 SYSV_ABI = 0, 481 MS_ABI = 1 482 }; 483 484 /* The abi used by target. */ 485 extern enum calling_abi ix86_abi; 486 487 /* The default abi used by target. */ 488 #define DEFAULT_ABI SYSV_ABI 489 490 /* Subtargets may reset this to 1 in order to enable 96-bit long double 491 with the rounding mode forced to 53 bits. */ 492 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 493 494 /* Sometimes certain combinations of command options do not make 495 sense on a particular target machine. You can define a macro 496 `OVERRIDE_OPTIONS' to take account of this. This macro, if 497 defined, is executed once just after all the command options have 498 been parsed. 499 500 Don't use this macro to turn on various extra optimizations for 501 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 502 503 #define OVERRIDE_OPTIONS override_options (true) 504 505 /* Define this to change the optimizations performed by default. */ 506 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 507 optimization_options ((LEVEL), (SIZE)) 508 509 /* -march=native handling only makes sense with compiler running on 510 an x86 or x86_64 chip. If changing this condition, also change 511 the condition in driver-i386.c. */ 512 #if defined(__i386__) || defined(__x86_64__) 513 /* In driver-i386.c. */ 514 extern const char *host_detect_local_cpu (int argc, const char **argv); 515 #define EXTRA_SPEC_FUNCTIONS \ 516 { "local_cpu_detect", host_detect_local_cpu }, 517 #define HAVE_LOCAL_CPU_DETECT 518 #endif 519 520 #if TARGET_64BIT_DEFAULT 521 #define OPT_ARCH64 "!m32" 522 #define OPT_ARCH32 "m32" 523 #else 524 #define OPT_ARCH64 "m64" 525 #define OPT_ARCH32 "!m64" 526 #endif 527 528 /* Support for configure-time defaults of some command line options. 529 The order here is important so that -march doesn't squash the 530 tune or cpu values. */ 531 #define OPTION_DEFAULT_SPECS \ 532 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 533 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 534 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 535 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 536 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 537 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 538 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 539 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 540 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 541 542 /* Specs for the compiler proper */ 543 544 #ifndef CC1_CPU_SPEC 545 #define CC1_CPU_SPEC_1 "\ 546 %{mcpu=*:-mtune=%* \ 547 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \ 548 %<mcpu=* \ 549 %{mintel-syntax:-masm=intel \ 550 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 551 %{msse5:-mavx \ 552 %n'-msse5' was removed.\n} \ 553 %{mno-intel-syntax:-masm=att \ 554 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 555 556 #ifndef HAVE_LOCAL_CPU_DETECT 557 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 558 #else 559 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 560 "%{march=native:%<march=native %:local_cpu_detect(arch) \ 561 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ 562 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 563 #endif 564 #endif 565 566 /* Target CPU builtins. */ 567 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 568 569 /* Target Pragmas. */ 570 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 571 572 enum target_cpu_default 573 { 574 TARGET_CPU_DEFAULT_generic = 0, 575 576 TARGET_CPU_DEFAULT_i386, 577 TARGET_CPU_DEFAULT_i486, 578 TARGET_CPU_DEFAULT_pentium, 579 TARGET_CPU_DEFAULT_pentium_mmx, 580 TARGET_CPU_DEFAULT_pentiumpro, 581 TARGET_CPU_DEFAULT_pentium2, 582 TARGET_CPU_DEFAULT_pentium3, 583 TARGET_CPU_DEFAULT_pentium4, 584 TARGET_CPU_DEFAULT_pentium_m, 585 TARGET_CPU_DEFAULT_prescott, 586 TARGET_CPU_DEFAULT_nocona, 587 TARGET_CPU_DEFAULT_core2, 588 TARGET_CPU_DEFAULT_atom, 589 590 TARGET_CPU_DEFAULT_geode, 591 TARGET_CPU_DEFAULT_k6, 592 TARGET_CPU_DEFAULT_k6_2, 593 TARGET_CPU_DEFAULT_k6_3, 594 TARGET_CPU_DEFAULT_athlon, 595 TARGET_CPU_DEFAULT_athlon_sse, 596 TARGET_CPU_DEFAULT_k8, 597 TARGET_CPU_DEFAULT_amdfam10, 598 599 TARGET_CPU_DEFAULT_max 600 }; 601 602 #ifndef CC1_SPEC 603 #define CC1_SPEC "%(cc1_cpu) " 604 #endif 605 606 /* This macro defines names of additional specifications to put in the 607 specs that can be used in various specifications like CC1_SPEC. Its 608 definition is an initializer with a subgrouping for each command option. 609 610 Each subgrouping contains a string constant, that defines the 611 specification name, and a string constant that used by the GCC driver 612 program. 613 614 Do not define this macro if it does not need to do anything. */ 615 616 #ifndef SUBTARGET_EXTRA_SPECS 617 #define SUBTARGET_EXTRA_SPECS 618 #endif 619 620 #define EXTRA_SPECS \ 621 { "cc1_cpu", CC1_CPU_SPEC }, \ 622 SUBTARGET_EXTRA_SPECS 623 624 625 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the 626 FPU, assume that the fpcw is set to extended precision; when using 627 only SSE, rounding is correct; when using both SSE and the FPU, 628 the rounding precision is indeterminate, since either may be chosen 629 apparently at random. */ 630 #define TARGET_FLT_EVAL_METHOD \ 631 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 632 633 /* Whether to allow x87 floating-point arithmetic on MODE (one of 634 SFmode, DFmode and XFmode) in the current excess precision 635 configuration. */ 636 #define X87_ENABLE_ARITH(MODE) \ 637 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) 638 639 /* Likewise, whether to allow direct conversions from integer mode 640 IMODE (HImode, SImode or DImode) to MODE. */ 641 #define X87_ENABLE_FLOAT(MODE, IMODE) \ 642 (flag_excess_precision == EXCESS_PRECISION_FAST \ 643 || (MODE) == XFmode \ 644 || ((MODE) == DFmode && (IMODE) == SImode) \ 645 || (IMODE) == HImode) 646 647 /* target machine storage layout */ 648 649 #define SHORT_TYPE_SIZE 16 650 #define INT_TYPE_SIZE 32 651 #define FLOAT_TYPE_SIZE 32 652 #define LONG_TYPE_SIZE BITS_PER_WORD 653 #define DOUBLE_TYPE_SIZE 64 654 #define LONG_LONG_TYPE_SIZE 64 655 #define LONG_DOUBLE_TYPE_SIZE 80 656 657 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE 658 659 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 660 #define MAX_BITS_PER_WORD 64 661 #else 662 #define MAX_BITS_PER_WORD 32 663 #endif 664 665 /* Define this if most significant byte of a word is the lowest numbered. */ 666 /* That is true on the 80386. */ 667 668 #define BITS_BIG_ENDIAN 0 669 670 /* Define this if most significant byte of a word is the lowest numbered. */ 671 /* That is not true on the 80386. */ 672 #define BYTES_BIG_ENDIAN 0 673 674 /* Define this if most significant word of a multiword number is the lowest 675 numbered. */ 676 /* Not true for 80386 */ 677 #define WORDS_BIG_ENDIAN 0 678 679 /* Width of a word, in units (bytes). */ 680 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 681 #ifdef IN_LIBGCC2 682 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 683 #else 684 #define MIN_UNITS_PER_WORD 4 685 #endif 686 687 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 688 #define PARM_BOUNDARY BITS_PER_WORD 689 690 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 691 #define STACK_BOUNDARY \ 692 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) 693 694 /* Stack boundary of the main function guaranteed by OS. */ 695 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 696 697 /* Minimum stack boundary. */ 698 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 699 700 /* Boundary (in *bits*) on which the stack pointer prefers to be 701 aligned; the compiler cannot rely on having this alignment. */ 702 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 703 704 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 705 both 32bit and 64bit, to support codes that need 128 bit stack 706 alignment for SSE instructions, but can't realign the stack. */ 707 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 708 709 /* 1 if -mstackrealign should be turned on by default. It will 710 generate an alternate prologue and epilogue that realigns the 711 runtime stack if nessary. This supports mixing codes that keep a 712 4-byte aligned stack, as specified by i386 psABI, with codes that 713 need a 16-byte aligned stack, as required by SSE instructions. */ 714 #define STACK_REALIGN_DEFAULT 0 715 716 /* Boundary (in *bits*) on which the incoming stack is aligned. */ 717 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 718 719 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 720 mandatory for the 64-bit ABI, and may or may not be true for other 721 operating systems. */ 722 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 723 724 /* Minimum allocation boundary for the code of a function. */ 725 #define FUNCTION_BOUNDARY 8 726 727 /* C++ stores the virtual bit in the lowest bit of function pointers. */ 728 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 729 730 /* Alignment of field after `int : 0' in a structure. */ 731 732 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 733 734 /* Minimum size in bits of the largest boundary to which any 735 and all fundamental data types supported by the hardware 736 might need to be aligned. No data type wants to be aligned 737 rounder than this. 738 739 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 740 and Pentium Pro XFmode values at 128 bit boundaries. */ 741 742 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256: 128) 743 744 /* Maximum stack alignment. */ 745 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 746 747 /* Alignment value for attribute ((aligned)). It is a constant since 748 it is the part of the ABI. We shouldn't change it with -mavx. */ 749 #define ATTRIBUTE_ALIGNED_VALUE 128 750 751 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ 752 #define ALIGN_MODE_128(MODE) \ 753 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 754 755 /* The published ABIs say that doubles should be aligned on word 756 boundaries, so lower the alignment for structure fields unless 757 -malign-double is set. */ 758 759 /* ??? Blah -- this macro is used directly by libobjc. Since it 760 supports no vector modes, cut out the complexity and fall back 761 on BIGGEST_FIELD_ALIGNMENT. */ 762 #ifdef IN_TARGET_LIBS 763 #ifdef __x86_64__ 764 #define BIGGEST_FIELD_ALIGNMENT 128 765 #else 766 #define BIGGEST_FIELD_ALIGNMENT 32 767 #endif 768 #else 769 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 770 x86_field_alignment (FIELD, COMPUTED) 771 #endif 772 773 /* If defined, a C expression to compute the alignment given to a 774 constant that is being placed in memory. EXP is the constant 775 and ALIGN is the alignment that the object would ordinarily have. 776 The value of this macro is used instead of that alignment to align 777 the object. 778 779 If this macro is not defined, then ALIGN is used. 780 781 The typical use of this macro is to increase alignment for string 782 constants to be word aligned so that `strcpy' calls that copy 783 constants can be done inline. */ 784 785 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 786 787 /* If defined, a C expression to compute the alignment for a static 788 variable. TYPE is the data type, and ALIGN is the alignment that 789 the object would ordinarily have. The value of this macro is used 790 instead of that alignment to align the object. 791 792 If this macro is not defined, then ALIGN is used. 793 794 One use of this macro is to increase alignment of medium-size 795 data to make it all fit in fewer cache lines. Another is to 796 cause character arrays to be word-aligned so that `strcpy' calls 797 that copy constants to character arrays can be done inline. */ 798 799 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 800 801 /* If defined, a C expression to compute the alignment for a local 802 variable. TYPE is the data type, and ALIGN is the alignment that 803 the object would ordinarily have. The value of this macro is used 804 instead of that alignment to align the object. 805 806 If this macro is not defined, then ALIGN is used. 807 808 One use of this macro is to increase alignment of medium-size 809 data to make it all fit in fewer cache lines. */ 810 811 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 812 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 813 814 /* If defined, a C expression to compute the alignment for stack slot. 815 TYPE is the data type, MODE is the widest mode available, and ALIGN 816 is the alignment that the slot would ordinarily have. The value of 817 this macro is used instead of that alignment to align the slot. 818 819 If this macro is not defined, then ALIGN is used when TYPE is NULL, 820 Otherwise, LOCAL_ALIGNMENT will be used. 821 822 One use of this macro is to set alignment of stack slot to the 823 maximum alignment of all possible modes which the slot may have. */ 824 825 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 826 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 827 828 /* If defined, a C expression to compute the alignment for a local 829 variable DECL. 830 831 If this macro is not defined, then 832 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 833 834 One use of this macro is to increase alignment of medium-size 835 data to make it all fit in fewer cache lines. */ 836 837 #define LOCAL_DECL_ALIGNMENT(DECL) \ 838 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 839 840 /* If defined, a C expression to compute the minimum required alignment 841 for dynamic stack realignment purposes for EXP (a TYPE or DECL), 842 MODE, assuming normal alignment ALIGN. 843 844 If this macro is not defined, then (ALIGN) will be used. */ 845 846 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 847 ix86_minimum_alignment (EXP, MODE, ALIGN) 848 849 850 /* If defined, a C expression that gives the alignment boundary, in 851 bits, of an argument with the specified mode and type. If it is 852 not defined, `PARM_BOUNDARY' is used for all arguments. */ 853 854 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 855 ix86_function_arg_boundary ((MODE), (TYPE)) 856 857 /* Set this nonzero if move instructions will actually fail to work 858 when given unaligned data. */ 859 #define STRICT_ALIGNMENT 0 860 861 /* If bit field type is int, don't let it cross an int, 862 and give entire struct the alignment of an int. */ 863 /* Required on the 386 since it doesn't have bit-field insns. */ 864 #define PCC_BITFIELD_TYPE_MATTERS 1 865 866 /* Standard register usage. */ 867 868 /* This processor has special stack-like registers. See reg-stack.c 869 for details. */ 870 871 #define STACK_REGS 872 873 #define IS_STACK_MODE(MODE) \ 874 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ 875 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ 876 || (MODE) == XFmode) 877 878 /* Cover class containing the stack registers. */ 879 #define STACK_REG_COVER_CLASS FLOAT_REGS 880 881 /* Number of actual hardware registers. 882 The hardware registers are assigned numbers for the compiler 883 from 0 to just below FIRST_PSEUDO_REGISTER. 884 All registers that the compiler knows about must be given numbers, 885 even those that are not normally considered general registers. 886 887 In the 80386 we give the 8 general purpose registers the numbers 0-7. 888 We number the floating point registers 8-15. 889 Note that registers 0-7 can be accessed as a short or int, 890 while only 0-3 may be used with byte `mov' instructions. 891 892 Reg 16 does not correspond to any hardware register, but instead 893 appears in the RTL as an argument pointer prior to reload, and is 894 eliminated during reloading in favor of either the stack or frame 895 pointer. */ 896 897 #define FIRST_PSEUDO_REGISTER 53 898 899 /* Number of hardware registers that go into the DWARF-2 unwind info. 900 If not defined, equals FIRST_PSEUDO_REGISTER. */ 901 902 #define DWARF_FRAME_REGISTERS 17 903 904 /* 1 for registers that have pervasive standard uses 905 and are not available for the register allocator. 906 On the 80386, the stack pointer is such, as is the arg pointer. 907 908 The value is zero if the register is not fixed on either 32 or 909 64 bit targets, one if the register if fixed on both 32 and 64 910 bit targets, two if it is only fixed on 32bit targets and three 911 if its only fixed on 64bit targets. 912 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 913 */ 914 #define FIXED_REGISTERS \ 915 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 916 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 917 /*arg,flags,fpsr,fpcr,frame*/ \ 918 1, 1, 1, 1, 1, \ 919 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 920 0, 0, 0, 0, 0, 0, 0, 0, \ 921 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 922 0, 0, 0, 0, 0, 0, 0, 0, \ 923 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 924 2, 2, 2, 2, 2, 2, 2, 2, \ 925 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 926 2, 2, 2, 2, 2, 2, 2, 2 } 927 928 929 /* 1 for registers not available across function calls. 930 These must include the FIXED_REGISTERS and also any 931 registers that can be used without being saved. 932 The latter must include the registers where values are returned 933 and the register where structure-value addresses are passed. 934 Aside from that, you can include as many other registers as you like. 935 936 The value is zero if the register is not call used on either 32 or 937 64 bit targets, one if the register if call used on both 32 and 64 938 bit targets, two if it is only call used on 32bit targets and three 939 if its only call used on 64bit targets. 940 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 941 */ 942 #define CALL_USED_REGISTERS \ 943 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 944 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 945 /*arg,flags,fpsr,fpcr,frame*/ \ 946 1, 1, 1, 1, 1, \ 947 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 948 1, 1, 1, 1, 1, 1, 1, 1, \ 949 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 950 1, 1, 1, 1, 1, 1, 1, 1, \ 951 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 952 1, 1, 1, 1, 2, 2, 2, 2, \ 953 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 954 1, 1, 1, 1, 1, 1, 1, 1 } 955 956 /* Order in which to allocate registers. Each register must be 957 listed once, even those in FIXED_REGISTERS. List frame pointer 958 late and fixed registers last. Note that, in general, we prefer 959 registers listed in CALL_USED_REGISTERS, keeping the others 960 available for storage of persistent values. 961 962 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 963 so this is just empty initializer for array. */ 964 965 #define REG_ALLOC_ORDER \ 966 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 967 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 968 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 969 48, 49, 50, 51, 52 } 970 971 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 972 to be rearranged based on a particular function. When using sse math, 973 we want to allocate SSE before x87 registers and vice versa. */ 974 975 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 976 977 978 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 979 980 /* Macro to conditionally modify fixed_regs/call_used_regs. */ 981 #define CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage () 982 983 /* Return number of consecutive hard regs needed starting at reg REGNO 984 to hold something of mode MODE. 985 This is ordinarily the length in words of a value of mode MODE 986 but can be less for certain modes in special long registers. 987 988 Actually there are no two word move instructions for consecutive 989 registers. And only registers 0-3 may have mov byte instructions 990 applied to them. 991 */ 992 993 #define HARD_REGNO_NREGS(REGNO, MODE) \ 994 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 995 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 996 : ((MODE) == XFmode \ 997 ? (TARGET_64BIT ? 2 : 3) \ 998 : (MODE) == XCmode \ 999 ? (TARGET_64BIT ? 4 : 6) \ 1000 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1001 1002 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 1003 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 1004 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1005 ? 0 \ 1006 : ((MODE) == XFmode || (MODE) == XCmode)) \ 1007 : 0) 1008 1009 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 1010 1011 #define VALID_AVX256_REG_MODE(MODE) \ 1012 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1013 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) 1014 1015 #define VALID_SSE2_REG_MODE(MODE) \ 1016 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1017 || (MODE) == V2DImode || (MODE) == DFmode) 1018 1019 #define VALID_SSE_REG_MODE(MODE) \ 1020 ((MODE) == V1TImode || (MODE) == TImode \ 1021 || (MODE) == V4SFmode || (MODE) == V4SImode \ 1022 || (MODE) == SFmode || (MODE) == TFmode) 1023 1024 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1025 ((MODE) == V2SFmode || (MODE) == SFmode) 1026 1027 #define VALID_MMX_REG_MODE(MODE) \ 1028 ((MODE == V1DImode) || (MODE) == DImode \ 1029 || (MODE) == V2SImode || (MODE) == SImode \ 1030 || (MODE) == V4HImode || (MODE) == V8QImode) 1031 1032 /* ??? No autovectorization into MMX or 3DNOW until we can reliably 1033 place emms and femms instructions. 1034 FIXME: AVX has 32byte floating point vector operations and 16byte 1035 integer vector operations. But vectorizer doesn't support 1036 different sizes for integer and floating point vectors. We limit 1037 vector size to 16byte. */ 1038 #define UNITS_PER_SIMD_WORD(MODE) \ 1039 (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16) \ 1040 : (TARGET_SSE ? 16 : UNITS_PER_WORD)) 1041 1042 #define VALID_DFP_MODE_P(MODE) \ 1043 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1044 1045 #define VALID_FP_MODE_P(MODE) \ 1046 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1047 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1048 1049 #define VALID_INT_MODE_P(MODE) \ 1050 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1051 || (MODE) == DImode \ 1052 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1053 || (MODE) == CDImode \ 1054 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1055 || (MODE) == TFmode || (MODE) == TCmode))) 1056 1057 /* Return true for modes passed in SSE registers. */ 1058 #define SSE_REG_MODE_P(MODE) \ 1059 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 1060 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1061 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1062 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1063 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) 1064 1065 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1066 1067 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1068 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1069 1070 /* Value is 1 if it is a good idea to tie two pseudo registers 1071 when one has mode MODE1 and one has mode MODE2. 1072 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1073 for any hard reg, then this must be 0 for correct output. */ 1074 1075 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 1076 1077 /* It is possible to write patterns to move flags; but until someone 1078 does it, */ 1079 #define AVOID_CCMODE_COPIES 1080 1081 /* Specify the modes required to caller save a given hard regno. 1082 We do this on i386 to prevent flags from being saved at all. 1083 1084 Kill any attempts to combine saving of modes. */ 1085 1086 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1087 (CC_REGNO_P (REGNO) ? VOIDmode \ 1088 : MMX_REGNO_P (REGNO) ? V8QImode \ 1089 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1090 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ 1091 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1092 : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \ 1093 : (MODE)) 1094 1095 /* Specify the registers used for certain standard purposes. 1096 The values of these macros are register numbers. */ 1097 1098 /* on the 386 the pc register is %eip, and is not usable as a general 1099 register. The ordinary mov instructions won't work */ 1100 /* #define PC_REGNUM */ 1101 1102 /* Register to use for pushing function arguments. */ 1103 #define STACK_POINTER_REGNUM 7 1104 1105 /* Base register for access to local variables of the function. */ 1106 #define HARD_FRAME_POINTER_REGNUM 6 1107 1108 /* Base register for access to local variables of the function. */ 1109 #define FRAME_POINTER_REGNUM 20 1110 1111 /* First floating point reg */ 1112 #define FIRST_FLOAT_REG 8 1113 1114 /* First & last stack-like regs */ 1115 #define FIRST_STACK_REG FIRST_FLOAT_REG 1116 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1117 1118 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1119 #define LAST_SSE_REG (FIRST_SSE_REG + 7) 1120 1121 #define FIRST_MMX_REG (LAST_SSE_REG + 1) 1122 #define LAST_MMX_REG (FIRST_MMX_REG + 7) 1123 1124 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1125 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1126 1127 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1128 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1129 1130 /* Override this in other tm.h files to cope with various OS lossage 1131 requiring a frame pointer. */ 1132 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1133 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1134 #endif 1135 1136 /* Make sure we can access arbitrary call frames. */ 1137 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1138 1139 /* Base register for access to arguments of the function. */ 1140 #define ARG_POINTER_REGNUM 16 1141 1142 /* Register to hold the addressing base for position independent 1143 code access to data items. We don't use PIC pointer for 64bit 1144 mode. Define the regnum to dummy value to prevent gcc from 1145 pessimizing code dealing with EBX. 1146 1147 To avoid clobbering a call-saved register unnecessarily, we renumber 1148 the pic register when possible. The change is visible after the 1149 prologue has been emitted. */ 1150 1151 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG 1152 1153 #define PIC_OFFSET_TABLE_REGNUM \ 1154 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 1155 || !flag_pic ? INVALID_REGNUM \ 1156 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1157 : REAL_PIC_OFFSET_TABLE_REGNUM) 1158 1159 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1160 1161 /* This is overridden by <cygwin.h>. */ 1162 #define MS_AGGREGATE_RETURN 0 1163 1164 /* This is overridden by <netware.h>. */ 1165 #define KEEP_AGGREGATE_RETURN_POINTER 0 1166 1167 /* Define the classes of registers for register constraints in the 1168 machine description. Also define ranges of constants. 1169 1170 One of the classes must always be named ALL_REGS and include all hard regs. 1171 If there is more than one class, another class must be named NO_REGS 1172 and contain no registers. 1173 1174 The name GENERAL_REGS must be the name of a class (or an alias for 1175 another name such as ALL_REGS). This is the class of registers 1176 that is allowed by "g" or "r" in a register constraint. 1177 Also, registers outside this class are allocated only when 1178 instructions express preferences for them. 1179 1180 The classes must be numbered in nondecreasing order; that is, 1181 a larger-numbered class must never be contained completely 1182 in a smaller-numbered class. 1183 1184 For any two classes, it is very desirable that there be another 1185 class that represents their union. 1186 1187 It might seem that class BREG is unnecessary, since no useful 386 1188 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1189 and the "b" register constraint is useful in asms for syscalls. 1190 1191 The flags, fpsr and fpcr registers are in no class. */ 1192 1193 enum reg_class 1194 { 1195 NO_REGS, 1196 AREG, DREG, CREG, BREG, SIREG, DIREG, 1197 AD_REGS, /* %eax/%edx for DImode */ 1198 CLOBBERED_REGS, /* call-clobbered integers */ 1199 Q_REGS, /* %eax %ebx %ecx %edx */ 1200 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1201 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1202 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1203 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1204 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1205 FLOAT_REGS, 1206 SSE_FIRST_REG, 1207 SSE_REGS, 1208 MMX_REGS, 1209 FP_TOP_SSE_REGS, 1210 FP_SECOND_SSE_REGS, 1211 FLOAT_SSE_REGS, 1212 FLOAT_INT_REGS, 1213 INT_SSE_REGS, 1214 FLOAT_INT_SSE_REGS, 1215 ALL_REGS, LIM_REG_CLASSES 1216 }; 1217 1218 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1219 1220 #define INTEGER_CLASS_P(CLASS) \ 1221 reg_class_subset_p ((CLASS), GENERAL_REGS) 1222 #define FLOAT_CLASS_P(CLASS) \ 1223 reg_class_subset_p ((CLASS), FLOAT_REGS) 1224 #define SSE_CLASS_P(CLASS) \ 1225 reg_class_subset_p ((CLASS), SSE_REGS) 1226 #define MMX_CLASS_P(CLASS) \ 1227 ((CLASS) == MMX_REGS) 1228 #define MAYBE_INTEGER_CLASS_P(CLASS) \ 1229 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1230 #define MAYBE_FLOAT_CLASS_P(CLASS) \ 1231 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1232 #define MAYBE_SSE_CLASS_P(CLASS) \ 1233 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1234 #define MAYBE_MMX_CLASS_P(CLASS) \ 1235 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1236 1237 #define Q_CLASS_P(CLASS) \ 1238 reg_class_subset_p ((CLASS), Q_REGS) 1239 1240 /* Give names of register classes as strings for dump file. */ 1241 1242 #define REG_CLASS_NAMES \ 1243 { "NO_REGS", \ 1244 "AREG", "DREG", "CREG", "BREG", \ 1245 "SIREG", "DIREG", \ 1246 "AD_REGS", \ 1247 "CLOBBERED_REGS", \ 1248 "Q_REGS", "NON_Q_REGS", \ 1249 "INDEX_REGS", \ 1250 "LEGACY_REGS", \ 1251 "GENERAL_REGS", \ 1252 "FP_TOP_REG", "FP_SECOND_REG", \ 1253 "FLOAT_REGS", \ 1254 "SSE_FIRST_REG", \ 1255 "SSE_REGS", \ 1256 "MMX_REGS", \ 1257 "FP_TOP_SSE_REGS", \ 1258 "FP_SECOND_SSE_REGS", \ 1259 "FLOAT_SSE_REGS", \ 1260 "FLOAT_INT_REGS", \ 1261 "INT_SSE_REGS", \ 1262 "FLOAT_INT_SSE_REGS", \ 1263 "ALL_REGS" } 1264 1265 /* Define which registers fit in which classes. This is an initializer 1266 for a vector of HARD_REG_SET of length N_REG_CLASSES. 1267 1268 Note that the default setting of CLOBBERED_REGS is for 32-bit; this 1269 is adjusted by CONDITIONAL_REGISTER_USAGE for the 64-bit ABI in effect. */ 1270 1271 #define REG_CLASS_CONTENTS \ 1272 { { 0x00, 0x0 }, \ 1273 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1274 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1275 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1276 { 0x03, 0x0 }, /* AD_REGS */ \ 1277 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \ 1278 { 0x0f, 0x0 }, /* Q_REGS */ \ 1279 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1280 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1281 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1282 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1283 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1284 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1285 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ 1286 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1287 { 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1288 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1289 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1290 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1291 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1292 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1293 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1294 { 0xffffffff,0x1fffff } \ 1295 } 1296 1297 /* The same information, inverted: 1298 Return the class number of the smallest class containing 1299 reg number REGNO. This could be a conditional expression 1300 or could index an array. */ 1301 1302 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1303 1304 /* When defined, the compiler allows registers explicitly used in the 1305 rtl to be used as spill registers but prevents the compiler from 1306 extending the lifetime of these registers. */ 1307 1308 #define SMALL_REGISTER_CLASSES 1 1309 1310 #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG) 1311 1312 #define GENERAL_REGNO_P(N) \ 1313 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) 1314 1315 #define GENERAL_REG_P(X) \ 1316 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1317 1318 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1319 1320 #define REX_INT_REGNO_P(N) \ 1321 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 1322 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1323 1324 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1325 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1326 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1327 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1328 1329 #define X87_FLOAT_MODE_P(MODE) \ 1330 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 1331 1332 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1333 #define SSE_REGNO_P(N) \ 1334 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 1335 || REX_SSE_REGNO_P (N)) 1336 1337 #define REX_SSE_REGNO_P(N) \ 1338 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 1339 1340 #define SSE_REGNO(N) \ 1341 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1342 1343 #define SSE_FLOAT_MODE_P(MODE) \ 1344 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1345 1346 #define SSE_VEC_FLOAT_MODE_P(MODE) \ 1347 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode)) 1348 1349 #define AVX_FLOAT_MODE_P(MODE) \ 1350 (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode)) 1351 1352 #define AVX128_VEC_FLOAT_MODE_P(MODE) \ 1353 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode)) 1354 1355 #define AVX256_VEC_FLOAT_MODE_P(MODE) \ 1356 (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode)) 1357 1358 #define AVX_VEC_FLOAT_MODE_P(MODE) \ 1359 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1360 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1361 1362 #define FMA4_VEC_FLOAT_MODE_P(MODE) \ 1363 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1364 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1365 1366 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1367 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1368 1369 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP))) 1370 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1371 1372 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1373 1374 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1375 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1376 1377 /* The class value for index registers, and the one for base regs. */ 1378 1379 #define INDEX_REG_CLASS INDEX_REGS 1380 #define BASE_REG_CLASS GENERAL_REGS 1381 1382 /* Place additional restrictions on the register class to use when it 1383 is necessary to be able to hold a value of mode MODE in a reload 1384 register for which class CLASS would ordinarily be used. */ 1385 1386 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1387 ((MODE) == QImode && !TARGET_64BIT \ 1388 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1389 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1390 ? Q_REGS : (CLASS)) 1391 1392 /* Given an rtx X being reloaded into a reg required to be 1393 in class CLASS, return the class of reg to actually use. 1394 In general this is just CLASS; but on some machines 1395 in some cases it is preferable to use a more restrictive class. 1396 On the 80386 series, we prevent floating constants from being 1397 reloaded into floating registers (since no move-insn can do that) 1398 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1399 1400 /* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1401 QImode must go into class Q_REGS. 1402 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1403 movdf to do mem-to-mem moves through integer regs. */ 1404 1405 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1406 ix86_preferred_reload_class ((X), (CLASS)) 1407 1408 /* Discourage putting floating-point values in SSE registers unless 1409 SSE math is being used, and likewise for the 387 registers. */ 1410 1411 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ 1412 ix86_preferred_output_reload_class ((X), (CLASS)) 1413 1414 /* If we are copying between general and FP registers, we need a memory 1415 location. The same is true for SSE and MMX registers. */ 1416 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1417 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1418 1419 /* Get_secondary_mem widens integral modes to BITS_PER_WORD. 1420 There is no need to emit full 64 bit move on 64 bit targets 1421 for integral modes that can be moved using 32 bit move. */ 1422 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1423 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ 1424 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1425 : MODE) 1426 1427 /* Return the maximum number of consecutive registers 1428 needed to represent mode MODE in a register of class CLASS. */ 1429 /* On the 80386, this is the size of MODE in words, 1430 except in the FP regs, where a single reg is always enough. */ 1431 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1432 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1433 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1434 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ 1435 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1436 1437 /* A C expression whose value is nonzero if pseudos that have been 1438 assigned to registers of class CLASS would likely be spilled 1439 because registers of CLASS are needed for spill registers. 1440 1441 The default value of this macro returns 1 if CLASS has exactly one 1442 register and zero otherwise. On most machines, this default 1443 should be used. Only define this macro to some other expression 1444 if pseudo allocated by `local-alloc.c' end up in memory because 1445 their hard registers were needed for spill registers. If this 1446 macro returns nonzero for those classes, those pseudos will only 1447 be allocated by `global.c', which knows how to reallocate the 1448 pseudo to another register. If there would not be another 1449 register available for reallocation, you should not change the 1450 definition of this macro since the only effect of such a 1451 definition would be to slow down register allocation. */ 1452 1453 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 1454 (((CLASS) == AREG) \ 1455 || ((CLASS) == DREG) \ 1456 || ((CLASS) == CREG) \ 1457 || ((CLASS) == BREG) \ 1458 || ((CLASS) == AD_REGS) \ 1459 || ((CLASS) == SIREG) \ 1460 || ((CLASS) == DIREG) \ 1461 || ((CLASS) == SSE_FIRST_REG) \ 1462 || ((CLASS) == FP_TOP_REG) \ 1463 || ((CLASS) == FP_SECOND_REG)) 1464 1465 /* Return a class of registers that cannot change FROM mode to TO mode. */ 1466 1467 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1468 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1469 1470 /* Stack layout; function entry, exit and calling. */ 1471 1472 /* Define this if pushing a word on the stack 1473 makes the stack pointer a smaller address. */ 1474 #define STACK_GROWS_DOWNWARD 1475 1476 /* Define this to nonzero if the nominal address of the stack frame 1477 is at the high-address end of the local variables; 1478 that is, each additional local variable allocated 1479 goes at a more negative offset in the frame. */ 1480 #define FRAME_GROWS_DOWNWARD 1 1481 1482 /* Offset within stack frame to start allocating local variables at. 1483 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1484 first local allocated. Otherwise, it is the offset to the BEGINNING 1485 of the first local allocated. */ 1486 #define STARTING_FRAME_OFFSET 0 1487 1488 /* If we generate an insn to push BYTES bytes, 1489 this says how many the stack pointer really advances by. 1490 On 386, we have pushw instruction that decrements by exactly 2 no 1491 matter what the position was, there is no pushb. 1492 But as CIE data alignment factor on this arch is -4, we need to make 1493 sure all stack pointer adjustments are in multiple of 4. 1494 1495 For 64bit ABI we round up to 8 bytes. 1496 */ 1497 1498 #define PUSH_ROUNDING(BYTES) \ 1499 (TARGET_64BIT \ 1500 ? (((BYTES) + 7) & (-8)) \ 1501 : (((BYTES) + 3) & (-4))) 1502 1503 /* If defined, the maximum amount of space required for outgoing arguments will 1504 be computed and placed into the variable 1505 `crtl->outgoing_args_size'. No space will be pushed onto the 1506 stack for each call; instead, the function prologue should increase the stack 1507 frame size by this amount. 1508 1509 MS ABI seem to require 16 byte alignment everywhere except for function 1510 prologue and apilogue. This is not possible without 1511 ACCUMULATE_OUTGOING_ARGS. */ 1512 1513 #define ACCUMULATE_OUTGOING_ARGS \ 1514 (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI) 1515 1516 /* If defined, a C expression whose value is nonzero when we want to use PUSH 1517 instructions to pass outgoing arguments. */ 1518 1519 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1520 1521 /* We want the stack and args grow in opposite directions, even if 1522 PUSH_ARGS is 0. */ 1523 #define PUSH_ARGS_REVERSED 1 1524 1525 /* Offset of first parameter from the argument pointer register value. */ 1526 #define FIRST_PARM_OFFSET(FNDECL) 0 1527 1528 /* Define this macro if functions should assume that stack space has been 1529 allocated for arguments even when their values are passed in registers. 1530 1531 The value of this macro is the size, in bytes, of the area reserved for 1532 arguments passed in registers for the function represented by FNDECL. 1533 1534 This space can be allocated by the caller, or be a part of the 1535 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1536 which. */ 1537 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 1538 1539 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 1540 (ix86_function_type_abi (FNTYPE) == MS_ABI) 1541 1542 /* Value is the number of bytes of arguments automatically 1543 popped when returning from a subroutine call. 1544 FUNDECL is the declaration node of the function (as a tree), 1545 FUNTYPE is the data type of the function (as a tree), 1546 or for a library call it is an identifier node for the subroutine name. 1547 SIZE is the number of bytes of arguments passed on the stack. 1548 1549 On the 80386, the RTD insn may be used to pop them if the number 1550 of args is fixed, but if the number is variable then the caller 1551 must pop them all. RTD can't be used for library calls now 1552 because the library is compiled with the Unix compiler. 1553 Use of RTD is a selectable option, since it is incompatible with 1554 standard Unix calling sequences. If the option is not selected, 1555 the caller must always pop the args. 1556 1557 The attribute stdcall is equivalent to RTD on a per module basis. */ 1558 1559 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1560 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1561 1562 #define FUNCTION_VALUE_REGNO_P(N) ix86_function_value_regno_p (N) 1563 1564 /* Define how to find the value returned by a library function 1565 assuming the value has mode MODE. */ 1566 1567 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 1568 1569 /* Define the size of the result block used for communication between 1570 untyped_call and untyped_return. The block contains a DImode value 1571 followed by the block used by fnsave and frstor. */ 1572 1573 #define APPLY_RESULT_SIZE (8+108) 1574 1575 /* 1 if N is a possible register number for function argument passing. */ 1576 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1577 1578 /* Define a data type for recording info about an argument list 1579 during the scan of that argument list. This data type should 1580 hold all necessary information about the function itself 1581 and about the args processed so far, enough to enable macros 1582 such as FUNCTION_ARG to determine where the next arg should go. */ 1583 1584 typedef struct ix86_args { 1585 int words; /* # words passed so far */ 1586 int nregs; /* # registers available for passing */ 1587 int regno; /* next available register number */ 1588 int fastcall; /* fastcall calling convention is used */ 1589 int sse_words; /* # sse words passed so far */ 1590 int sse_nregs; /* # sse registers available for passing */ 1591 int warn_avx; /* True when we want to warn about AVX ABI. */ 1592 int warn_sse; /* True when we want to warn about SSE ABI. */ 1593 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1594 int sse_regno; /* next available sse register number */ 1595 int mmx_words; /* # mmx words passed so far */ 1596 int mmx_nregs; /* # mmx registers available for passing */ 1597 int mmx_regno; /* next available mmx register number */ 1598 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1599 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should 1600 be passed in SSE registers. Otherwise 0. */ 1601 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1602 MS_ABI for ms abi. */ 1603 } CUMULATIVE_ARGS; 1604 1605 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1606 for a call to a function whose data type is FNTYPE. 1607 For a library call, FNTYPE is 0. */ 1608 1609 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1610 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1611 1612 /* Update the data in CUM to advance over an argument 1613 of mode MODE and data type TYPE. 1614 (TYPE is null for libcalls where that information may not be available.) */ 1615 1616 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1617 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1618 1619 /* Define where to put the arguments to a function. 1620 Value is zero to push the argument on the stack, 1621 or a hard register in which to store the argument. 1622 1623 MODE is the argument's machine mode. 1624 TYPE is the data type of the argument (as a tree). 1625 This is null for libcalls where that information may 1626 not be available. 1627 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1628 the preceding args and about the function being called. 1629 NAMED is nonzero if this argument is a named parameter 1630 (otherwise it is an extra parameter matching an ellipsis). */ 1631 1632 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1633 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1634 1635 /* Output assembler code to FILE to increment profiler label # LABELNO 1636 for profiling a function entry. */ 1637 1638 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1639 1640 #define MCOUNT_NAME "_mcount" 1641 1642 #define PROFILE_COUNT_REGISTER "edx" 1643 1644 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1645 the stack pointer does not matter. The value is tested only in 1646 functions that have frame pointers. 1647 No definition is equivalent to always zero. */ 1648 /* Note on the 386 it might be more efficient not to define this since 1649 we have to restore it ourselves from the frame pointer, in order to 1650 use pop */ 1651 1652 #define EXIT_IGNORE_STACK 1 1653 1654 /* Output assembler code for a block containing the constant parts 1655 of a trampoline, leaving space for the variable parts. */ 1656 1657 /* On the 386, the trampoline contains two instructions: 1658 mov #STATIC,ecx 1659 jmp FUNCTION 1660 The trampoline is generated entirely at runtime. The operand of JMP 1661 is the address of FUNCTION relative to the instruction following the 1662 JMP (which is 5 bytes long). */ 1663 1664 /* Length in units of the trampoline for entering a nested function. */ 1665 1666 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) 1667 1668 /* Definitions for register eliminations. 1669 1670 This is an array of structures. Each structure initializes one pair 1671 of eliminable registers. The "from" register number is given first, 1672 followed by "to". Eliminations of the same "from" register are listed 1673 in order of preference. 1674 1675 There are two registers that can always be eliminated on the i386. 1676 The frame pointer and the arg pointer can be replaced by either the 1677 hard frame pointer or to the stack pointer, depending upon the 1678 circumstances. The hard frame pointer is not used before reload and 1679 so it is not eligible for elimination. */ 1680 1681 #define ELIMINABLE_REGS \ 1682 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1683 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1684 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1685 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1686 1687 /* Define the offset between two registers, one to be eliminated, and the other 1688 its replacement, at the start of a routine. */ 1689 1690 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1691 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1692 1693 /* Addressing modes, and classification of registers for them. */ 1694 1695 /* Macros to check register numbers against specific register classes. */ 1696 1697 /* These assume that REGNO is a hard or pseudo reg number. 1698 They give nonzero only if REGNO is a hard reg of the suitable class 1699 or a pseudo reg currently allocated to a suitable hard reg. 1700 Since they use reg_renumber, they are safe only once reg_renumber 1701 has been allocated, which happens in local-alloc.c. */ 1702 1703 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1704 ((REGNO) < STACK_POINTER_REGNUM \ 1705 || REX_INT_REGNO_P (REGNO) \ 1706 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 1707 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1708 1709 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1710 (GENERAL_REGNO_P (REGNO) \ 1711 || (REGNO) == ARG_POINTER_REGNUM \ 1712 || (REGNO) == FRAME_POINTER_REGNUM \ 1713 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1714 1715 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1716 and check its validity for a certain class. 1717 We have two alternate definitions for each of them. 1718 The usual definition accepts all pseudo regs; the other rejects 1719 them unless they have been allocated suitable hard regs. 1720 The symbol REG_OK_STRICT causes the latter definition to be used. 1721 1722 Most source files want to accept pseudo regs in the hope that 1723 they will get allocated to the class that the insn wants them to be in. 1724 Source files for reload pass need to be strict. 1725 After reload, it makes no difference, since pseudo regs have 1726 been eliminated by then. */ 1727 1728 1729 /* Non strict versions, pseudos are ok. */ 1730 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1731 (REGNO (X) < STACK_POINTER_REGNUM \ 1732 || REX_INT_REGNO_P (REGNO (X)) \ 1733 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1734 1735 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1736 (GENERAL_REGNO_P (REGNO (X)) \ 1737 || REGNO (X) == ARG_POINTER_REGNUM \ 1738 || REGNO (X) == FRAME_POINTER_REGNUM \ 1739 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1740 1741 /* Strict versions, hard registers only */ 1742 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1743 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1744 1745 #ifndef REG_OK_STRICT 1746 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1747 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1748 1749 #else 1750 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1751 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1752 #endif 1753 1754 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1755 that is a valid memory address for an instruction. 1756 The MODE argument is the machine mode for the MEM expression 1757 that wants to use this address. 1758 1759 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 1760 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1761 1762 See legitimize_pic_address in i386.c for details as to what 1763 constitutes a legitimate address when -fpic is used. */ 1764 1765 #define MAX_REGS_PER_ADDRESS 2 1766 1767 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1768 1769 /* Nonzero if the constant value X is a legitimate general operand. 1770 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1771 1772 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1773 1774 /* Try a machine-dependent way of reloading an illegitimate address 1775 operand. If we find one, push the reload and jump to WIN. This 1776 macro is used in only one place: `find_reloads_address' in reload.c. */ 1777 1778 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \ 1779 do { \ 1780 if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1781 (int)(TYPE), (INDL))) \ 1782 goto WIN; \ 1783 } while (0) 1784 1785 /* If defined, a C expression to determine the base term of address X. 1786 This macro is used in only one place: `find_base_term' in alias.c. 1787 1788 It is always safe for this macro to not be defined. It exists so 1789 that alias analysis can understand machine-dependent addresses. 1790 1791 The typical use of this macro is to handle addresses containing 1792 a label_ref or symbol_ref within an UNSPEC. */ 1793 1794 #define FIND_BASE_TERM(X) ix86_find_base_term (X) 1795 1796 /* Nonzero if the constant value X is a legitimate general operand 1797 when generating PIC code. It is given that flag_pic is on and 1798 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1799 1800 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1801 1802 #define SYMBOLIC_CONST(X) \ 1803 (GET_CODE (X) == SYMBOL_REF \ 1804 || GET_CODE (X) == LABEL_REF \ 1805 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1806 1807 /* Max number of args passed in registers. If this is more than 3, we will 1808 have problems with ebx (register #4), since it is a caller save register and 1809 is also used as the pic register in ELF. So for now, don't allow more than 1810 3 registers to be passed in registers. */ 1811 1812 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 1813 #define X86_64_REGPARM_MAX 6 1814 #define X86_64_MS_REGPARM_MAX 4 1815 1816 #define X86_32_REGPARM_MAX 3 1817 1818 #define REGPARM_MAX \ 1819 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_REGPARM_MAX \ 1820 : X86_64_REGPARM_MAX) \ 1821 : X86_32_REGPARM_MAX) 1822 1823 #define X86_64_SSE_REGPARM_MAX 8 1824 #define X86_64_MS_SSE_REGPARM_MAX 4 1825 1826 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 1827 1828 #define SSE_REGPARM_MAX \ 1829 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_SSE_REGPARM_MAX \ 1830 : X86_64_SSE_REGPARM_MAX) \ 1831 : X86_32_SSE_REGPARM_MAX) 1832 1833 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1834 1835 1836 /* Specify the machine mode that this machine uses 1837 for the index in the tablejump instruction. */ 1838 #define CASE_VECTOR_MODE \ 1839 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 1840 1841 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1842 #define DEFAULT_SIGNED_CHAR 1 1843 1844 /* Max number of bytes we can move from memory to memory 1845 in one reasonably fast instruction. */ 1846 #define MOVE_MAX 16 1847 1848 /* MOVE_MAX_PIECES is the number of bytes at a time which we can 1849 move efficiently, as opposed to MOVE_MAX which is the maximum 1850 number of bytes we can move with a single instruction. */ 1851 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 1852 1853 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1854 move-instruction pairs, we will do a movmem or libcall instead. 1855 Increasing the value will always make code faster, but eventually 1856 incurs high cost in increased code size. 1857 1858 If you don't define this, a reasonable default is used. */ 1859 1860 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 1861 1862 /* If a clear memory operation would take CLEAR_RATIO or more simple 1863 move-instruction sequences, we will do a clrmem or libcall instead. */ 1864 1865 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) 1866 1867 /* Define if shifts truncate the shift count 1868 which implies one can omit a sign-extension or zero-extension 1869 of a shift count. */ 1870 /* On i386, shifts do truncate the count. But bit opcodes don't. */ 1871 1872 /* #define SHIFT_COUNT_TRUNCATED */ 1873 1874 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1875 is done just by pretending it is already truncated. */ 1876 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1877 1878 /* A macro to update M and UNSIGNEDP when an object whose type is 1879 TYPE and which has the specified mode and signedness is to be 1880 stored in a register. This macro is only called when TYPE is a 1881 scalar type. 1882 1883 On i386 it is sometimes useful to promote HImode and QImode 1884 quantities to SImode. The choice depends on target type. */ 1885 1886 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1887 do { \ 1888 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1889 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1890 (MODE) = SImode; \ 1891 } while (0) 1892 1893 /* Specify the machine mode that pointers have. 1894 After generation of rtl, the compiler makes no further distinction 1895 between pointers and any other objects of this machine mode. */ 1896 #define Pmode (TARGET_64BIT ? DImode : SImode) 1897 1898 /* A function address in a call instruction 1899 is a byte address (for indexing purposes) 1900 so give the MEM rtx a byte's mode. */ 1901 #define FUNCTION_MODE QImode 1902 1903 /* A C expression for the cost of moving data from a register in class FROM to 1904 one in class TO. The classes are expressed using the enumeration values 1905 such as `GENERAL_REGS'. A value of 2 is the default; other values are 1906 interpreted relative to that. 1907 1908 It is not required that the cost always equal 2 when FROM is the same as TO; 1909 on some machines it is expensive to move between registers if they are not 1910 general registers. */ 1911 1912 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1913 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1914 1915 /* A C expression for the cost of moving data of mode M between a 1916 register and memory. A value of 2 is the default; this cost is 1917 relative to those in `REGISTER_MOVE_COST'. 1918 1919 If moving between registers and memory is more expensive than 1920 between two registers, you should define this macro to express the 1921 relative cost. */ 1922 1923 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1924 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 1925 1926 /* A C expression for the cost of a branch instruction. A value of 1 1927 is the default; other values are interpreted relative to that. */ 1928 1929 #define BRANCH_COST(speed_p, predictable_p) \ 1930 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 1931 1932 /* Define this macro as a C expression which is nonzero if accessing 1933 less than a word of memory (i.e. a `char' or a `short') is no 1934 faster than accessing a word of memory, i.e., if such access 1935 require more than one instruction or if there is no difference in 1936 cost between byte and (aligned) word loads. 1937 1938 When this macro is not defined, the compiler will access a field by 1939 finding the smallest containing object; when it is defined, a 1940 fullword load will be used if alignment permits. Unless bytes 1941 accesses are faster than word accesses, using word accesses is 1942 preferable since it may eliminate subsequent memory access if 1943 subsequent accesses occur to other fields in the same word of the 1944 structure, but to different bytes. */ 1945 1946 #define SLOW_BYTE_ACCESS 0 1947 1948 /* Nonzero if access to memory by shorts is slow and undesirable. */ 1949 #define SLOW_SHORT_ACCESS 0 1950 1951 /* Define this macro to be the value 1 if unaligned accesses have a 1952 cost many times greater than aligned accesses, for example if they 1953 are emulated in a trap handler. 1954 1955 When this macro is nonzero, the compiler will act as if 1956 `STRICT_ALIGNMENT' were nonzero when generating code for block 1957 moves. This can cause significantly more instructions to be 1958 produced. Therefore, do not set this macro nonzero if unaligned 1959 accesses only add a cycle or two to the time for a memory access. 1960 1961 If the value of this macro is always zero, it need not be defined. */ 1962 1963 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1964 1965 /* Define this macro if it is as good or better to call a constant 1966 function address than to call an address kept in a register. 1967 1968 Desirable on the 386 because a CALL with a constant address is 1969 faster than one with a register address. */ 1970 1971 #define NO_FUNCTION_CSE 1972 1973 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1974 return the mode to be used for the comparison. 1975 1976 For floating-point equality comparisons, CCFPEQmode should be used. 1977 VOIDmode should be used in all other cases. 1978 1979 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1980 possible, to allow for more combinations. */ 1981 1982 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1983 1984 /* Return nonzero if MODE implies a floating point inequality can be 1985 reversed. */ 1986 1987 #define REVERSIBLE_CC_MODE(MODE) 1 1988 1989 /* A C expression whose value is reversed condition code of the CODE for 1990 comparison done in CC_MODE mode. */ 1991 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 1992 1993 1994 /* Control the assembler format that we output, to the extent 1995 this does not vary between assemblers. */ 1996 1997 /* How to refer to registers in assembler output. 1998 This sequence is indexed by compiler's hard-register-number (see above). */ 1999 2000 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 2001 For non floating point regs, the following are the HImode names. 2002 2003 For float regs, the stack top is sometimes referred to as "%st(0)" 2004 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ 2005 2006 #define HI_REGISTER_NAMES \ 2007 {"ax","dx","cx","bx","si","di","bp","sp", \ 2008 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 2009 "argp", "flags", "fpsr", "fpcr", "frame", \ 2010 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2011 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 2012 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2013 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 2014 2015 #define REGISTER_NAMES HI_REGISTER_NAMES 2016 2017 /* Table of additional register names to use in user input. */ 2018 2019 #define ADDITIONAL_REGISTER_NAMES \ 2020 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2021 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2022 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2023 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2024 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2025 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 2026 2027 /* Note we are omitting these since currently I don't know how 2028 to get gcc to use these, since they want the same but different 2029 number as al, and ax. 2030 */ 2031 2032 #define QI_REGISTER_NAMES \ 2033 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2034 2035 /* These parallel the array above, and can be used to access bits 8:15 2036 of regs 0 through 3. */ 2037 2038 #define QI_HIGH_REGISTER_NAMES \ 2039 {"ah", "dh", "ch", "bh", } 2040 2041 /* How to renumber registers for dbx and gdb. */ 2042 2043 #define DBX_REGISTER_NUMBER(N) \ 2044 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2045 2046 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2047 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2048 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2049 2050 /* Before the prologue, RA is at 0(%esp). */ 2051 #define INCOMING_RETURN_ADDR_RTX \ 2052 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2053 2054 /* After the prologue, RA is at -4(AP) in the current frame. */ 2055 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2056 ((COUNT) == 0 \ 2057 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2058 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2059 2060 /* PC is dbx register 8; let's use that column for RA. */ 2061 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2062 2063 /* Before the prologue, the top of the frame is at 4(%esp). */ 2064 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2065 2066 /* Describe how we implement __builtin_eh_return. */ 2067 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2068 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2069 2070 2071 /* Select a format to encode pointers in exception handling data. CODE 2072 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2073 true if the symbol may be affected by dynamic relocations. 2074 2075 ??? All x86 object file formats are capable of representing this. 2076 After all, the relocation needed is the same as for the call insn. 2077 Whether or not a particular assembler allows us to enter such, I 2078 guess we'll have to see. */ 2079 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2080 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 2081 2082 /* This is how to output an insn to push a register on the stack. 2083 It need not be very fast code. */ 2084 2085 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2086 do { \ 2087 if (TARGET_64BIT) \ 2088 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2089 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2090 else \ 2091 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2092 } while (0) 2093 2094 /* This is how to output an insn to pop a register from the stack. 2095 It need not be very fast code. */ 2096 2097 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2098 do { \ 2099 if (TARGET_64BIT) \ 2100 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2101 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2102 else \ 2103 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2104 } while (0) 2105 2106 /* This is how to output an element of a case-vector that is absolute. */ 2107 2108 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2109 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2110 2111 /* This is how to output an element of a case-vector that is relative. */ 2112 2113 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2114 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2115 2116 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is 2117 true. */ 2118 2119 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 2120 { \ 2121 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 2122 { \ 2123 if (TARGET_AVX) \ 2124 (PTR) += 1; \ 2125 else \ 2126 (PTR) += 2; \ 2127 } \ 2128 } 2129 2130 /* A C statement or statements which output an assembler instruction 2131 opcode to the stdio stream STREAM. The macro-operand PTR is a 2132 variable of type `char *' which points to the opcode name in 2133 its "internal" form--the form that is written in the machine 2134 description. */ 2135 2136 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2137 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 2138 2139 /* A C statement to output to the stdio stream FILE an assembler 2140 command to pad the location counter to a multiple of 1<<LOG 2141 bytes if it is within MAX_SKIP bytes. */ 2142 2143 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2144 #undef ASM_OUTPUT_MAX_SKIP_PAD 2145 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2146 if ((LOG) != 0) \ 2147 { \ 2148 if ((MAX_SKIP) == 0) \ 2149 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2150 else \ 2151 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2152 } 2153 #endif 2154 2155 /* Under some conditions we need jump tables in the text section, 2156 because the assembler cannot handle label differences between 2157 sections. This is the case for x86_64 on Mach-O for example. */ 2158 2159 #define JUMP_TABLES_IN_TEXT_SECTION \ 2160 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2161 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2162 2163 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2164 and switch back. For x86 we do this only to save a few bytes that 2165 would otherwise be unused in the text section. */ 2166 #define CRT_MKSTR2(VAL) #VAL 2167 #define CRT_MKSTR(x) CRT_MKSTR2(x) 2168 2169 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2170 asm (SECTION_OP "\n\t" \ 2171 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 2172 TEXT_SECTION_ASM_OP); 2173 2174 /* Print operand X (an rtx) in assembler syntax to file FILE. 2175 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2176 Effect of various CODE letters is described in i386.c near 2177 print_operand function. */ 2178 2179 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2180 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';') 2181 2182 #define PRINT_OPERAND(FILE, X, CODE) \ 2183 print_operand ((FILE), (X), (CODE)) 2184 2185 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2186 print_operand_address ((FILE), (ADDR)) 2187 2188 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2189 do { \ 2190 if (! output_addr_const_extra (FILE, (X))) \ 2191 goto FAIL; \ 2192 } while (0); 2193 2194 /* Which processor to schedule for. The cpu attribute defines a list that 2195 mirrors this list, so changes to i386.md must be made at the same time. */ 2196 2197 enum processor_type 2198 { 2199 PROCESSOR_I386 = 0, /* 80386 */ 2200 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2201 PROCESSOR_PENTIUM, 2202 PROCESSOR_PENTIUMPRO, 2203 PROCESSOR_GEODE, 2204 PROCESSOR_K6, 2205 PROCESSOR_ATHLON, 2206 PROCESSOR_PENTIUM4, 2207 PROCESSOR_K8, 2208 PROCESSOR_NOCONA, 2209 PROCESSOR_CORE2, 2210 PROCESSOR_GENERIC32, 2211 PROCESSOR_GENERIC64, 2212 PROCESSOR_AMDFAM10, 2213 PROCESSOR_ATOM, 2214 PROCESSOR_max 2215 }; 2216 2217 extern enum processor_type ix86_tune; 2218 extern enum processor_type ix86_arch; 2219 2220 enum fpmath_unit 2221 { 2222 FPMATH_387 = 1, 2223 FPMATH_SSE = 2 2224 }; 2225 2226 extern enum fpmath_unit ix86_fpmath; 2227 2228 enum tls_dialect 2229 { 2230 TLS_DIALECT_GNU, 2231 TLS_DIALECT_GNU2, 2232 TLS_DIALECT_SUN 2233 }; 2234 2235 extern enum tls_dialect ix86_tls_dialect; 2236 2237 enum cmodel { 2238 CM_32, /* The traditional 32-bit ABI. */ 2239 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 2240 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 2241 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 2242 CM_LARGE, /* No assumptions. */ 2243 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ 2244 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */ 2245 CM_LARGE_PIC /* No assumptions. */ 2246 }; 2247 2248 extern enum cmodel ix86_cmodel; 2249 2250 /* Size of the RED_ZONE area. */ 2251 #define RED_ZONE_SIZE 128 2252 /* Reserved area of the red zone for temporaries. */ 2253 #define RED_ZONE_RESERVE 8 2254 2255 enum asm_dialect { 2256 ASM_ATT, 2257 ASM_INTEL 2258 }; 2259 2260 extern enum asm_dialect ix86_asm_dialect; 2261 extern unsigned int ix86_preferred_stack_boundary; 2262 extern unsigned int ix86_incoming_stack_boundary; 2263 extern int ix86_branch_cost, ix86_section_threshold; 2264 2265 /* Smallest class containing REGNO. */ 2266 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2267 2268 extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 2269 extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 2270 2271 enum ix86_fpcmp_strategy { 2272 IX86_FPCMP_SAHF, 2273 IX86_FPCMP_COMI, 2274 IX86_FPCMP_ARITH 2275 }; 2276 2277 /* To properly truncate FP values into integers, we need to set i387 control 2278 word. We can't emit proper mode switching code before reload, as spills 2279 generated by reload may truncate values incorrectly, but we still can avoid 2280 redundant computation of new control word by the mode switching pass. 2281 The fldcw instructions are still emitted redundantly, but this is probably 2282 not going to be noticeable problem, as most CPUs do have fast path for 2283 the sequence. 2284 2285 The machinery is to emit simple truncation instructions and split them 2286 before reload to instructions having USEs of two memory locations that 2287 are filled by this code to old and new control word. 2288 2289 Post-reload pass may be later used to eliminate the redundant fildcw if 2290 needed. */ 2291 2292 enum ix86_entity 2293 { 2294 I387_TRUNC = 0, 2295 I387_FLOOR, 2296 I387_CEIL, 2297 I387_MASK_PM, 2298 MAX_386_ENTITIES 2299 }; 2300 2301 enum ix86_stack_slot 2302 { 2303 SLOT_VIRTUAL = 0, 2304 SLOT_TEMP, 2305 SLOT_CW_STORED, 2306 SLOT_CW_TRUNC, 2307 SLOT_CW_FLOOR, 2308 SLOT_CW_CEIL, 2309 SLOT_CW_MASK_PM, 2310 MAX_386_STACK_LOCALS 2311 }; 2312 2313 /* Define this macro if the port needs extra instructions inserted 2314 for mode switching in an optimizing compilation. */ 2315 2316 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2317 ix86_optimize_mode_switching[(ENTITY)] 2318 2319 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2320 initializer for an array of integers. Each initializer element N 2321 refers to an entity that needs mode switching, and specifies the 2322 number of different modes that might need to be set for this 2323 entity. The position of the initializer in the initializer - 2324 starting counting at zero - determines the integer that is used to 2325 refer to the mode-switched entity in question. */ 2326 2327 #define NUM_MODES_FOR_MODE_SWITCHING \ 2328 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2329 2330 /* ENTITY is an integer specifying a mode-switched entity. If 2331 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2332 return an integer value not larger than the corresponding element 2333 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2334 must be switched into prior to the execution of INSN. */ 2335 2336 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2337 2338 /* This macro specifies the order in which modes for ENTITY are 2339 processed. 0 is the highest priority. */ 2340 2341 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2342 2343 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2344 is the set of hard registers live at the point where the insn(s) 2345 are to be inserted. */ 2346 2347 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2348 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ 2349 ? emit_i387_cw_initialization (MODE), 0 \ 2350 : 0) 2351 2352 2353 /* Avoid renaming of stack registers, as doing so in combination with 2354 scheduling just increases amount of live registers at time and in 2355 the turn amount of fxch instructions needed. 2356 2357 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2358 2359 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2360 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG)) 2361 2362 2363 #define FASTCALL_PREFIX '@' 2364 2365 /* Machine specific CFA tracking during prologue/epilogue generation. */ 2366 2367 #ifndef USED_FOR_TARGET 2368 struct GTY(()) machine_cfa_state 2369 { 2370 rtx reg; 2371 HOST_WIDE_INT offset; 2372 }; 2373 2374 struct GTY(()) machine_function { 2375 struct stack_local_entry *stack_locals; 2376 const char *some_ld_name; 2377 int varargs_gpr_size; 2378 int varargs_fpr_size; 2379 int optimize_mode_switching[MAX_386_ENTITIES]; 2380 2381 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE 2382 has been computed for. */ 2383 int use_fast_prologue_epilogue_nregs; 2384 2385 /* The CFA state at the end of the prologue. */ 2386 struct machine_cfa_state cfa; 2387 2388 /* This value is used for amd64 targets and specifies the current abi 2389 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 2390 enum calling_abi call_abi; 2391 2392 /* Nonzero if the function accesses a previous frame. */ 2393 BOOL_BITFIELD accesses_prev_frame : 1; 2394 2395 /* Nonzero if the function requires a CLD in the prologue. */ 2396 BOOL_BITFIELD needs_cld : 1; 2397 2398 /* Set by ix86_compute_frame_layout and used by prologue/epilogue 2399 expander to determine the style used. */ 2400 BOOL_BITFIELD use_fast_prologue_epilogue : 1; 2401 2402 /* If true, the current function needs the default PIC register, not 2403 an alternate register (on x86) and must not use the red zone (on 2404 x86_64), even if it's a leaf function. We don't want the 2405 function to be regarded as non-leaf because TLS calls need not 2406 affect register allocation. This flag is set when a TLS call 2407 instruction is expanded within a function, and never reset, even 2408 if all such instructions are optimized away. Use the 2409 ix86_current_function_calls_tls_descriptor macro for a better 2410 approximation. */ 2411 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 2412 2413 /* If true, the current function has a STATIC_CHAIN is placed on the 2414 stack below the return address. */ 2415 BOOL_BITFIELD static_chain_on_stack : 1; 2416 }; 2417 #endif 2418 2419 #define ix86_stack_locals (cfun->machine->stack_locals) 2420 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 2421 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 2422 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2423 #define ix86_current_function_needs_cld (cfun->machine->needs_cld) 2424 #define ix86_tls_descriptor_calls_expanded_in_cfun \ 2425 (cfun->machine->tls_descriptor_call_expanded_p) 2426 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2427 calls are optimized away, we try to detect cases in which it was 2428 optimized away. Since such instructions (use (reg REG_SP)), we can 2429 verify whether there's any such instruction live by testing that 2430 REG_SP is live. */ 2431 #define ix86_current_function_calls_tls_descriptor \ 2432 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 2433 #define ix86_cfa_state (&cfun->machine->cfa) 2434 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 2435 2436 /* Control behavior of x86_file_start. */ 2437 #define X86_FILE_START_VERSION_DIRECTIVE false 2438 #define X86_FILE_START_FLTUSED false 2439 2440 /* Flag to mark data that is in the large address area. */ 2441 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2442 #define SYMBOL_REF_FAR_ADDR_P(X) \ 2443 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2444 2445 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 2446 have defined always, to avoid ifdefing. */ 2447 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 2448 #define SYMBOL_REF_DLLIMPORT_P(X) \ 2449 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 2450 2451 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 2452 #define SYMBOL_REF_DLLEXPORT_P(X) \ 2453 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 2454 2455 /* Model costs for vectorizer. */ 2456 2457 /* Cost of conditional branch. */ 2458 #undef TARG_COND_BRANCH_COST 2459 #define TARG_COND_BRANCH_COST ix86_cost->branch_cost 2460 2461 /* Enum through the target specific extra va_list types. 2462 Please, do not iterate the base va_list type name. */ 2463 #define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \ 2464 (TARGET_64BIT ? ix86_enum_va_list (IDX, PNAME, PTYPE) : 0) 2465 2466 /* Cost of any scalar operation, excluding load and store. */ 2467 #undef TARG_SCALAR_STMT_COST 2468 #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost 2469 2470 /* Cost of scalar load. */ 2471 #undef TARG_SCALAR_LOAD_COST 2472 #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost 2473 2474 /* Cost of scalar store. */ 2475 #undef TARG_SCALAR_STORE_COST 2476 #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost 2477 2478 /* Cost of any vector operation, excluding load, store or vector to scalar 2479 operation. */ 2480 #undef TARG_VEC_STMT_COST 2481 #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost 2482 2483 /* Cost of vector to scalar operation. */ 2484 #undef TARG_VEC_TO_SCALAR_COST 2485 #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost 2486 2487 /* Cost of scalar to vector operation. */ 2488 #undef TARG_SCALAR_TO_VEC_COST 2489 #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost 2490 2491 /* Cost of aligned vector load. */ 2492 #undef TARG_VEC_LOAD_COST 2493 #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost 2494 2495 /* Cost of misaligned vector load. */ 2496 #undef TARG_VEC_UNALIGNED_LOAD_COST 2497 #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost 2498 2499 /* Cost of vector store. */ 2500 #undef TARG_VEC_STORE_COST 2501 #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost 2502 2503 /* Cost of conditional taken branch for vectorizer cost model. */ 2504 #undef TARG_COND_TAKEN_BRANCH_COST 2505 #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost 2506 2507 /* Cost of conditional not taken branch for vectorizer cost model. */ 2508 #undef TARG_COND_NOT_TAKEN_BRANCH_COST 2509 #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost 2510 2511 /* 2512 Local variables: 2513 version-control: t 2514 End: 2515 */ 2516