1 /* Subroutines for the gcc driver. 2 Copyright (C) 2006-2013 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "tm.h" 24 25 const char *host_detect_local_cpu (int argc, const char **argv); 26 27 #ifdef __GNUC__ 28 #include "cpuid.h" 29 30 struct cache_desc 31 { 32 unsigned sizekb; 33 unsigned assoc; 34 unsigned line; 35 }; 36 37 /* Returns command line parameters that describe size and 38 cache line size of the processor caches. */ 39 40 static char * 41 describe_cache (struct cache_desc level1, struct cache_desc level2) 42 { 43 char size[100], line[100], size2[100]; 44 45 /* At the moment, gcc does not use the information 46 about the associativity of the cache. */ 47 48 snprintf (size, sizeof (size), 49 "--param l1-cache-size=%u ", level1.sizekb); 50 snprintf (line, sizeof (line), 51 "--param l1-cache-line-size=%u ", level1.line); 52 53 snprintf (size2, sizeof (size2), 54 "--param l2-cache-size=%u ", level2.sizekb); 55 56 return concat (size, line, size2, NULL); 57 } 58 59 /* Detect L2 cache parameters using CPUID extended function 0x80000006. */ 60 61 static void 62 detect_l2_cache (struct cache_desc *level2) 63 { 64 unsigned eax, ebx, ecx, edx; 65 unsigned assoc; 66 67 __cpuid (0x80000006, eax, ebx, ecx, edx); 68 69 level2->sizekb = (ecx >> 16) & 0xffff; 70 level2->line = ecx & 0xff; 71 72 assoc = (ecx >> 12) & 0xf; 73 if (assoc == 6) 74 assoc = 8; 75 else if (assoc == 8) 76 assoc = 16; 77 else if (assoc >= 0xa && assoc <= 0xc) 78 assoc = 32 + (assoc - 0xa) * 16; 79 else if (assoc >= 0xd && assoc <= 0xe) 80 assoc = 96 + (assoc - 0xd) * 32; 81 82 level2->assoc = assoc; 83 } 84 85 /* Returns the description of caches for an AMD processor. */ 86 87 static const char * 88 detect_caches_amd (unsigned max_ext_level) 89 { 90 unsigned eax, ebx, ecx, edx; 91 92 struct cache_desc level1, level2 = {0, 0, 0}; 93 94 if (max_ext_level < 0x80000005) 95 return ""; 96 97 __cpuid (0x80000005, eax, ebx, ecx, edx); 98 99 level1.sizekb = (ecx >> 24) & 0xff; 100 level1.assoc = (ecx >> 16) & 0xff; 101 level1.line = ecx & 0xff; 102 103 if (max_ext_level >= 0x80000006) 104 detect_l2_cache (&level2); 105 106 return describe_cache (level1, level2); 107 } 108 109 /* Decodes the size, the associativity and the cache line size of 110 L1/L2 caches of an Intel processor. Values are based on 111 "Intel Processor Identification and the CPUID Instruction" 112 [Application Note 485], revision -032, December 2007. */ 113 114 static void 115 decode_caches_intel (unsigned reg, bool xeon_mp, 116 struct cache_desc *level1, struct cache_desc *level2) 117 { 118 int i; 119 120 for (i = 24; i >= 0; i -= 8) 121 switch ((reg >> i) & 0xff) 122 { 123 case 0x0a: 124 level1->sizekb = 8; level1->assoc = 2; level1->line = 32; 125 break; 126 case 0x0c: 127 level1->sizekb = 16; level1->assoc = 4; level1->line = 32; 128 break; 129 case 0x0d: 130 level1->sizekb = 16; level1->assoc = 4; level1->line = 64; 131 break; 132 case 0x0e: 133 level1->sizekb = 24; level1->assoc = 6; level1->line = 64; 134 break; 135 case 0x21: 136 level2->sizekb = 256; level2->assoc = 8; level2->line = 64; 137 break; 138 case 0x24: 139 level2->sizekb = 1024; level2->assoc = 16; level2->line = 64; 140 break; 141 case 0x2c: 142 level1->sizekb = 32; level1->assoc = 8; level1->line = 64; 143 break; 144 case 0x39: 145 level2->sizekb = 128; level2->assoc = 4; level2->line = 64; 146 break; 147 case 0x3a: 148 level2->sizekb = 192; level2->assoc = 6; level2->line = 64; 149 break; 150 case 0x3b: 151 level2->sizekb = 128; level2->assoc = 2; level2->line = 64; 152 break; 153 case 0x3c: 154 level2->sizekb = 256; level2->assoc = 4; level2->line = 64; 155 break; 156 case 0x3d: 157 level2->sizekb = 384; level2->assoc = 6; level2->line = 64; 158 break; 159 case 0x3e: 160 level2->sizekb = 512; level2->assoc = 4; level2->line = 64; 161 break; 162 case 0x41: 163 level2->sizekb = 128; level2->assoc = 4; level2->line = 32; 164 break; 165 case 0x42: 166 level2->sizekb = 256; level2->assoc = 4; level2->line = 32; 167 break; 168 case 0x43: 169 level2->sizekb = 512; level2->assoc = 4; level2->line = 32; 170 break; 171 case 0x44: 172 level2->sizekb = 1024; level2->assoc = 4; level2->line = 32; 173 break; 174 case 0x45: 175 level2->sizekb = 2048; level2->assoc = 4; level2->line = 32; 176 break; 177 case 0x48: 178 level2->sizekb = 3072; level2->assoc = 12; level2->line = 64; 179 break; 180 case 0x49: 181 if (xeon_mp) 182 break; 183 level2->sizekb = 4096; level2->assoc = 16; level2->line = 64; 184 break; 185 case 0x4e: 186 level2->sizekb = 6144; level2->assoc = 24; level2->line = 64; 187 break; 188 case 0x60: 189 level1->sizekb = 16; level1->assoc = 8; level1->line = 64; 190 break; 191 case 0x66: 192 level1->sizekb = 8; level1->assoc = 4; level1->line = 64; 193 break; 194 case 0x67: 195 level1->sizekb = 16; level1->assoc = 4; level1->line = 64; 196 break; 197 case 0x68: 198 level1->sizekb = 32; level1->assoc = 4; level1->line = 64; 199 break; 200 case 0x78: 201 level2->sizekb = 1024; level2->assoc = 4; level2->line = 64; 202 break; 203 case 0x79: 204 level2->sizekb = 128; level2->assoc = 8; level2->line = 64; 205 break; 206 case 0x7a: 207 level2->sizekb = 256; level2->assoc = 8; level2->line = 64; 208 break; 209 case 0x7b: 210 level2->sizekb = 512; level2->assoc = 8; level2->line = 64; 211 break; 212 case 0x7c: 213 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; 214 break; 215 case 0x7d: 216 level2->sizekb = 2048; level2->assoc = 8; level2->line = 64; 217 break; 218 case 0x7f: 219 level2->sizekb = 512; level2->assoc = 2; level2->line = 64; 220 break; 221 case 0x80: 222 level2->sizekb = 512; level2->assoc = 8; level2->line = 64; 223 break; 224 case 0x82: 225 level2->sizekb = 256; level2->assoc = 8; level2->line = 32; 226 break; 227 case 0x83: 228 level2->sizekb = 512; level2->assoc = 8; level2->line = 32; 229 break; 230 case 0x84: 231 level2->sizekb = 1024; level2->assoc = 8; level2->line = 32; 232 break; 233 case 0x85: 234 level2->sizekb = 2048; level2->assoc = 8; level2->line = 32; 235 break; 236 case 0x86: 237 level2->sizekb = 512; level2->assoc = 4; level2->line = 64; 238 break; 239 case 0x87: 240 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; 241 242 default: 243 break; 244 } 245 } 246 247 /* Detect cache parameters using CPUID function 2. */ 248 249 static void 250 detect_caches_cpuid2 (bool xeon_mp, 251 struct cache_desc *level1, struct cache_desc *level2) 252 { 253 unsigned regs[4]; 254 int nreps, i; 255 256 __cpuid (2, regs[0], regs[1], regs[2], regs[3]); 257 258 nreps = regs[0] & 0x0f; 259 regs[0] &= ~0x0f; 260 261 while (--nreps >= 0) 262 { 263 for (i = 0; i < 4; i++) 264 if (regs[i] && !((regs[i] >> 31) & 1)) 265 decode_caches_intel (regs[i], xeon_mp, level1, level2); 266 267 if (nreps) 268 __cpuid (2, regs[0], regs[1], regs[2], regs[3]); 269 } 270 } 271 272 /* Detect cache parameters using CPUID function 4. This 273 method doesn't require hardcoded tables. */ 274 275 enum cache_type 276 { 277 CACHE_END = 0, 278 CACHE_DATA = 1, 279 CACHE_INST = 2, 280 CACHE_UNIFIED = 3 281 }; 282 283 static void 284 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2, 285 struct cache_desc *level3) 286 { 287 struct cache_desc *cache; 288 289 unsigned eax, ebx, ecx, edx; 290 int count; 291 292 for (count = 0;; count++) 293 { 294 __cpuid_count(4, count, eax, ebx, ecx, edx); 295 switch (eax & 0x1f) 296 { 297 case CACHE_END: 298 return; 299 case CACHE_DATA: 300 case CACHE_UNIFIED: 301 { 302 switch ((eax >> 5) & 0x07) 303 { 304 case 1: 305 cache = level1; 306 break; 307 case 2: 308 cache = level2; 309 break; 310 case 3: 311 cache = level3; 312 break; 313 default: 314 cache = NULL; 315 } 316 317 if (cache) 318 { 319 unsigned sets = ecx + 1; 320 unsigned part = ((ebx >> 12) & 0x03ff) + 1; 321 322 cache->assoc = ((ebx >> 22) & 0x03ff) + 1; 323 cache->line = (ebx & 0x0fff) + 1; 324 325 cache->sizekb = (cache->assoc * part 326 * cache->line * sets) / 1024; 327 } 328 } 329 default: 330 break; 331 } 332 } 333 } 334 335 /* Returns the description of caches for an Intel processor. */ 336 337 static const char * 338 detect_caches_intel (bool xeon_mp, unsigned max_level, 339 unsigned max_ext_level, unsigned *l2sizekb) 340 { 341 struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0}; 342 343 if (max_level >= 4) 344 detect_caches_cpuid4 (&level1, &level2, &level3); 345 else if (max_level >= 2) 346 detect_caches_cpuid2 (xeon_mp, &level1, &level2); 347 else 348 return ""; 349 350 if (level1.sizekb == 0) 351 return ""; 352 353 /* Let the L3 replace the L2. This assumes inclusive caches 354 and single threaded program for now. */ 355 if (level3.sizekb) 356 level2 = level3; 357 358 /* Intel CPUs are equipped with AMD style L2 cache info. Try this 359 method if other methods fail to provide L2 cache parameters. */ 360 if (level2.sizekb == 0 && max_ext_level >= 0x80000006) 361 detect_l2_cache (&level2); 362 363 *l2sizekb = level2.sizekb; 364 365 return describe_cache (level1, level2); 366 } 367 368 /* This will be called by the spec parser in gcc.c when it sees 369 a %:local_cpu_detect(args) construct. Currently it will be called 370 with either "arch" or "tune" as argument depending on if -march=native 371 or -mtune=native is to be substituted. 372 373 It returns a string containing new command line parameters to be 374 put at the place of the above two options, depending on what CPU 375 this is executed. E.g. "-march=k8" on an AMD64 machine 376 for -march=native. 377 378 ARGC and ARGV are set depending on the actual arguments given 379 in the spec. */ 380 381 const char *host_detect_local_cpu (int argc, const char **argv) 382 { 383 enum processor_type processor = PROCESSOR_I386; 384 const char *cpu = "i386"; 385 386 const char *cache = ""; 387 const char *options = ""; 388 389 unsigned int eax, ebx, ecx, edx; 390 391 unsigned int max_level, ext_level; 392 393 unsigned int vendor; 394 unsigned int model, family; 395 396 unsigned int has_sse3, has_ssse3, has_cmpxchg16b; 397 unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2; 398 399 /* Extended features */ 400 unsigned int has_lahf_lm = 0, has_sse4a = 0; 401 unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0; 402 unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0; 403 unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0; 404 unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0; 405 unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0; 406 unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0; 407 unsigned int has_hle = 0, has_rtm = 0; 408 unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0; 409 unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0; 410 unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0; 411 412 bool arch; 413 414 unsigned int l2sizekb = 0; 415 416 if (argc < 1) 417 return NULL; 418 419 arch = !strcmp (argv[0], "arch"); 420 421 if (!arch && strcmp (argv[0], "tune")) 422 return NULL; 423 424 max_level = __get_cpuid_max (0, &vendor); 425 if (max_level < 1) 426 goto done; 427 428 __cpuid (1, eax, ebx, ecx, edx); 429 430 model = (eax >> 4) & 0x0f; 431 family = (eax >> 8) & 0x0f; 432 if (vendor == signature_INTEL_ebx) 433 { 434 unsigned int extended_model, extended_family; 435 436 extended_model = (eax >> 12) & 0xf0; 437 extended_family = (eax >> 20) & 0xff; 438 if (family == 0x0f) 439 { 440 family += extended_family; 441 model += extended_model; 442 } 443 else if (family == 0x06) 444 model += extended_model; 445 } 446 447 has_sse3 = ecx & bit_SSE3; 448 has_ssse3 = ecx & bit_SSSE3; 449 has_sse4_1 = ecx & bit_SSE4_1; 450 has_sse4_2 = ecx & bit_SSE4_2; 451 has_avx = ecx & bit_AVX; 452 has_osxsave = ecx & bit_OSXSAVE; 453 has_cmpxchg16b = ecx & bit_CMPXCHG16B; 454 has_movbe = ecx & bit_MOVBE; 455 has_popcnt = ecx & bit_POPCNT; 456 has_aes = ecx & bit_AES; 457 has_pclmul = ecx & bit_PCLMUL; 458 has_fma = ecx & bit_FMA; 459 has_f16c = ecx & bit_F16C; 460 has_rdrnd = ecx & bit_RDRND; 461 has_xsave = ecx & bit_XSAVE; 462 463 has_cmpxchg8b = edx & bit_CMPXCHG8B; 464 has_cmov = edx & bit_CMOV; 465 has_mmx = edx & bit_MMX; 466 has_fxsr = edx & bit_FXSAVE; 467 has_sse = edx & bit_SSE; 468 has_sse2 = edx & bit_SSE2; 469 470 if (max_level >= 7) 471 { 472 __cpuid_count (7, 0, eax, ebx, ecx, edx); 473 474 has_bmi = ebx & bit_BMI; 475 has_hle = ebx & bit_HLE; 476 has_rtm = ebx & bit_RTM; 477 has_avx2 = ebx & bit_AVX2; 478 has_bmi2 = ebx & bit_BMI2; 479 has_fsgsbase = ebx & bit_FSGSBASE; 480 has_rdseed = ebx & bit_RDSEED; 481 has_adx = ebx & bit_ADX; 482 } 483 484 if (max_level >= 13) 485 { 486 __cpuid_count (13, 1, eax, ebx, ecx, edx); 487 488 has_xsaveopt = eax & bit_XSAVEOPT; 489 } 490 491 /* Check cpuid level of extended features. */ 492 __cpuid (0x80000000, ext_level, ebx, ecx, edx); 493 494 if (ext_level > 0x80000000) 495 { 496 __cpuid (0x80000001, eax, ebx, ecx, edx); 497 498 has_lahf_lm = ecx & bit_LAHF_LM; 499 has_sse4a = ecx & bit_SSE4a; 500 has_abm = ecx & bit_ABM; 501 has_lwp = ecx & bit_LWP; 502 has_fma4 = ecx & bit_FMA4; 503 has_xop = ecx & bit_XOP; 504 has_tbm = ecx & bit_TBM; 505 has_lzcnt = ecx & bit_LZCNT; 506 has_prfchw = ecx & bit_PRFCHW; 507 508 has_longmode = edx & bit_LM; 509 has_3dnowp = edx & bit_3DNOWP; 510 has_3dnow = edx & bit_3DNOW; 511 } 512 513 /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ 514 #define XCR_XFEATURE_ENABLED_MASK 0x0 515 #define XSTATE_FP 0x1 516 #define XSTATE_SSE 0x2 517 #define XSTATE_YMM 0x4 518 if (has_osxsave) 519 asm (".byte 0x0f; .byte 0x01; .byte 0xd0" 520 : "=a" (eax), "=d" (edx) 521 : "c" (XCR_XFEATURE_ENABLED_MASK)); 522 523 /* Check if SSE and YMM states are supported. */ 524 if (!has_osxsave 525 || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) 526 { 527 has_avx = 0; 528 has_avx2 = 0; 529 has_fma = 0; 530 has_fma4 = 0; 531 has_f16c = 0; 532 has_xop = 0; 533 has_xsave = 0; 534 has_xsaveopt = 0; 535 } 536 537 if (!arch) 538 { 539 if (vendor == signature_AMD_ebx 540 || vendor == signature_CENTAUR_ebx 541 || vendor == signature_CYRIX_ebx 542 || vendor == signature_NSC_ebx) 543 cache = detect_caches_amd (ext_level); 544 else if (vendor == signature_INTEL_ebx) 545 { 546 bool xeon_mp = (family == 15 && model == 6); 547 cache = detect_caches_intel (xeon_mp, max_level, 548 ext_level, &l2sizekb); 549 } 550 } 551 552 if (vendor == signature_AMD_ebx) 553 { 554 unsigned int name; 555 556 /* Detect geode processor by its processor signature. */ 557 if (ext_level > 0x80000001) 558 __cpuid (0x80000002, name, ebx, ecx, edx); 559 else 560 name = 0; 561 562 if (name == signature_NSC_ebx) 563 processor = PROCESSOR_GEODE; 564 else if (has_movbe) 565 processor = PROCESSOR_BTVER2; 566 else if (has_xsaveopt) 567 processor = PROCESSOR_BDVER3; 568 else if (has_bmi) 569 processor = PROCESSOR_BDVER2; 570 else if (has_xop) 571 processor = PROCESSOR_BDVER1; 572 else if (has_sse4a && has_ssse3) 573 processor = PROCESSOR_BTVER1; 574 else if (has_sse4a) 575 processor = PROCESSOR_AMDFAM10; 576 else if (has_sse2 || has_longmode) 577 processor = PROCESSOR_K8; 578 else if (has_3dnowp && family == 6) 579 processor = PROCESSOR_ATHLON; 580 else if (has_mmx) 581 processor = PROCESSOR_K6; 582 else 583 processor = PROCESSOR_PENTIUM; 584 } 585 else if (vendor == signature_CENTAUR_ebx) 586 { 587 if (arch) 588 { 589 switch (family) 590 { 591 case 6: 592 if (model > 9) 593 /* Use the default detection procedure. */ 594 processor = PROCESSOR_GENERIC32; 595 else if (model == 9) 596 cpu = "c3-2"; 597 else if (model >= 6) 598 cpu = "c3"; 599 else 600 processor = PROCESSOR_GENERIC32; 601 break; 602 case 5: 603 if (has_3dnow) 604 cpu = "winchip2"; 605 else if (has_mmx) 606 cpu = "winchip2-c6"; 607 else 608 processor = PROCESSOR_GENERIC32; 609 break; 610 default: 611 /* We have no idea. */ 612 processor = PROCESSOR_GENERIC32; 613 } 614 } 615 } 616 else 617 { 618 switch (family) 619 { 620 case 4: 621 processor = PROCESSOR_I486; 622 break; 623 case 5: 624 processor = PROCESSOR_PENTIUM; 625 break; 626 case 6: 627 processor = PROCESSOR_PENTIUMPRO; 628 break; 629 case 15: 630 processor = PROCESSOR_PENTIUM4; 631 break; 632 default: 633 /* We have no idea. */ 634 processor = PROCESSOR_GENERIC32; 635 } 636 } 637 638 switch (processor) 639 { 640 case PROCESSOR_I386: 641 /* Default. */ 642 break; 643 case PROCESSOR_I486: 644 cpu = "i486"; 645 break; 646 case PROCESSOR_PENTIUM: 647 if (arch && has_mmx) 648 cpu = "pentium-mmx"; 649 else 650 cpu = "pentium"; 651 break; 652 case PROCESSOR_PENTIUMPRO: 653 switch (model) 654 { 655 case 0x1c: 656 case 0x26: 657 /* Atom. */ 658 cpu = "atom"; 659 break; 660 case 0x0f: 661 /* Merom. */ 662 case 0x17: 663 case 0x1d: 664 /* Penryn. */ 665 cpu = "core2"; 666 break; 667 case 0x1a: 668 case 0x1e: 669 case 0x1f: 670 case 0x2e: 671 /* Nehalem. */ 672 case 0x25: 673 case 0x2c: 674 case 0x2f: 675 /* Westmere. */ 676 cpu = "corei7"; 677 break; 678 case 0x2a: 679 case 0x2d: 680 /* Sandy Bridge. */ 681 cpu = "corei7-avx"; 682 break; 683 case 0x3a: 684 case 0x3e: 685 /* Ivy Bridge. */ 686 cpu = "core-avx-i"; 687 break; 688 case 0x3c: 689 case 0x45: 690 case 0x46: 691 /* Haswell. */ 692 cpu = "core-avx2"; 693 break; 694 default: 695 if (arch) 696 { 697 /* This is unknown family 0x6 CPU. */ 698 if (has_avx2) 699 /* Assume Haswell. */ 700 cpu = "core-avx2"; 701 else if (has_avx) 702 /* Assume Sandy Bridge. */ 703 cpu = "corei7-avx"; 704 else if (has_sse4_2) 705 /* Assume Core i7. */ 706 cpu = "corei7"; 707 else if (has_ssse3) 708 { 709 if (has_movbe) 710 /* Assume Atom. */ 711 cpu = "atom"; 712 else 713 /* Assume Core 2. */ 714 cpu = "core2"; 715 } 716 else if (has_longmode) 717 /* Perhaps some emulator? Assume x86-64, otherwise gcc 718 -march=native would be unusable for 64-bit compilations, 719 as all the CPUs below are 32-bit only. */ 720 cpu = "x86-64"; 721 else if (has_sse3) 722 /* It is Core Duo. */ 723 cpu = "pentium-m"; 724 else if (has_sse2) 725 /* It is Pentium M. */ 726 cpu = "pentium-m"; 727 else if (has_sse) 728 /* It is Pentium III. */ 729 cpu = "pentium3"; 730 else if (has_mmx) 731 /* It is Pentium II. */ 732 cpu = "pentium2"; 733 else 734 /* Default to Pentium Pro. */ 735 cpu = "pentiumpro"; 736 } 737 else 738 /* For -mtune, we default to -mtune=generic. */ 739 cpu = "generic"; 740 break; 741 } 742 break; 743 case PROCESSOR_PENTIUM4: 744 if (has_sse3) 745 { 746 if (has_longmode) 747 cpu = "nocona"; 748 else 749 cpu = "prescott"; 750 } 751 else 752 cpu = "pentium4"; 753 break; 754 case PROCESSOR_GEODE: 755 cpu = "geode"; 756 break; 757 case PROCESSOR_K6: 758 if (arch && has_3dnow) 759 cpu = "k6-3"; 760 else 761 cpu = "k6"; 762 break; 763 case PROCESSOR_ATHLON: 764 if (arch && has_sse) 765 cpu = "athlon-4"; 766 else 767 cpu = "athlon"; 768 break; 769 case PROCESSOR_K8: 770 if (arch && has_sse3) 771 cpu = "k8-sse3"; 772 else 773 cpu = "k8"; 774 break; 775 case PROCESSOR_AMDFAM10: 776 cpu = "amdfam10"; 777 break; 778 case PROCESSOR_BDVER1: 779 cpu = "bdver1"; 780 break; 781 case PROCESSOR_BDVER2: 782 cpu = "bdver2"; 783 break; 784 case PROCESSOR_BDVER3: 785 cpu = "bdver3"; 786 break; 787 case PROCESSOR_BTVER1: 788 cpu = "btver1"; 789 break; 790 case PROCESSOR_BTVER2: 791 cpu = "btver2"; 792 break; 793 794 default: 795 /* Use something reasonable. */ 796 if (arch) 797 { 798 if (has_ssse3) 799 cpu = "core2"; 800 else if (has_sse3) 801 { 802 if (has_longmode) 803 cpu = "nocona"; 804 else 805 cpu = "prescott"; 806 } 807 else if (has_sse2) 808 cpu = "pentium4"; 809 else if (has_cmov) 810 cpu = "pentiumpro"; 811 else if (has_mmx) 812 cpu = "pentium-mmx"; 813 else if (has_cmpxchg8b) 814 cpu = "pentium"; 815 } 816 else 817 cpu = "generic"; 818 } 819 820 if (arch) 821 { 822 const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16"; 823 const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf"; 824 const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe"; 825 const char *ase = has_aes ? " -maes" : " -mno-aes"; 826 const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul"; 827 const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt"; 828 const char *abm = has_abm ? " -mabm" : " -mno-abm"; 829 const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp"; 830 const char *fma = has_fma ? " -mfma" : " -mno-fma"; 831 const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4"; 832 const char *xop = has_xop ? " -mxop" : " -mno-xop"; 833 const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi"; 834 const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2"; 835 const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm"; 836 const char *avx = has_avx ? " -mavx" : " -mno-avx"; 837 const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2"; 838 const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2"; 839 const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1"; 840 const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt"; 841 const char *hle = has_hle ? " -mhle" : " -mno-hle"; 842 const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm"; 843 const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd"; 844 const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c"; 845 const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase"; 846 const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed"; 847 const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw"; 848 const char *adx = has_adx ? " -madx" : " -mno-adx"; 849 const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr"; 850 const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave"; 851 const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt"; 852 853 options = concat (options, cx16, sahf, movbe, ase, pclmul, 854 popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2, 855 tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm, 856 hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx, 857 fxsr, xsave, xsaveopt, NULL); 858 } 859 860 done: 861 return concat (cache, "-m", argv[0], "=", cpu, options, NULL); 862 } 863 #else 864 865 /* If we aren't compiling with GCC then the driver will just ignore 866 -march and -mtune "native" target and will leave to the newly 867 built compiler to generate code for its default target. */ 868 869 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED, 870 const char **argv ATTRIBUTE_UNUSED) 871 { 872 return NULL; 873 } 874 #endif /* __GNUC__ */ 875