1 /* 2 * Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc. 3 * 4 * This file is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 3, or (at your option) any 7 * later version. 8 * 9 * This file is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * General Public License for more details. 13 * 14 * Under Section 7 of GPL version 3, you are granted additional 15 * permissions described in the GCC Runtime Library Exception, version 16 * 3.1, as published by the Free Software Foundation. 17 * 18 * You should have received a copy of the GNU General Public License and 19 * a copy of the GCC Runtime Library Exception along with this program; 20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 21 * <http://www.gnu.org/licenses/>. 22 */ 23 24 /* %ecx */ 25 #define bit_SSE3 (1 << 0) 26 #define bit_PCLMUL (1 << 1) 27 #define bit_SSSE3 (1 << 9) 28 #define bit_FMA (1 << 12) 29 #define bit_CMPXCHG16B (1 << 13) 30 #define bit_SSE4_1 (1 << 19) 31 #define bit_SSE4_2 (1 << 20) 32 #define bit_MOVBE (1 << 22) 33 #define bit_POPCNT (1 << 23) 34 #define bit_AES (1 << 25) 35 #define bit_XSAVE (1 << 26) 36 #define bit_OSXSAVE (1 << 27) 37 #define bit_AVX (1 << 28) 38 39 /* %edx */ 40 #define bit_CMPXCHG8B (1 << 8) 41 #define bit_CMOV (1 << 15) 42 #define bit_MMX (1 << 23) 43 #define bit_FXSAVE (1 << 24) 44 #define bit_SSE (1 << 25) 45 #define bit_SSE2 (1 << 26) 46 47 /* Extended Features */ 48 /* %ecx */ 49 #define bit_LAHF_LM (1 << 0) 50 #define bit_ABM (1 << 5) 51 #define bit_SSE4a (1 << 6) 52 #define bit_XOP (1 << 11) 53 #define bit_LWP (1 << 15) 54 #define bit_FMA4 (1 << 16) 55 56 /* %edx */ 57 #define bit_LM (1 << 29) 58 #define bit_3DNOWP (1 << 30) 59 #define bit_3DNOW (1 << 31) 60 61 62 #if defined(__i386__) && defined(__PIC__) 63 /* %ebx may be the PIC register. */ 64 #if __GNUC__ >= 3 65 #define __cpuid(level, a, b, c, d) \ 66 __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ 67 "cpuid\n\t" \ 68 "xchg{l}\t{%%}ebx, %1\n\t" \ 69 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 70 : "0" (level)) 71 72 #define __cpuid_count(level, count, a, b, c, d) \ 73 __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ 74 "cpuid\n\t" \ 75 "xchg{l}\t{%%}ebx, %1\n\t" \ 76 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 77 : "0" (level), "2" (count)) 78 #else 79 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax 80 nor alternatives in i386 code. */ 81 #define __cpuid(level, a, b, c, d) \ 82 __asm__ ("xchgl\t%%ebx, %1\n\t" \ 83 "cpuid\n\t" \ 84 "xchgl\t%%ebx, %1\n\t" \ 85 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 86 : "0" (level)) 87 88 #define __cpuid_count(level, count, a, b, c, d) \ 89 __asm__ ("xchgl\t%%ebx, %1\n\t" \ 90 "cpuid\n\t" \ 91 "xchgl\t%%ebx, %1\n\t" \ 92 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 93 : "0" (level), "2" (count)) 94 #endif 95 #else 96 #define __cpuid(level, a, b, c, d) \ 97 __asm__ ("cpuid\n\t" \ 98 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 99 : "0" (level)) 100 101 #define __cpuid_count(level, count, a, b, c, d) \ 102 __asm__ ("cpuid\n\t" \ 103 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 104 : "0" (level), "2" (count)) 105 #endif 106 107 /* Return highest supported input value for cpuid instruction. ext can 108 be either 0x0 or 0x8000000 to return highest supported value for 109 basic or extended cpuid information. Function returns 0 if cpuid 110 is not supported or whatever cpuid returns in eax register. If sig 111 pointer is non-null, then first four bytes of the signature 112 (as found in ebx register) are returned in location pointed by sig. */ 113 114 static __inline unsigned int 115 __get_cpuid_max (unsigned int __ext, unsigned int *__sig) 116 { 117 unsigned int __eax, __ebx, __ecx, __edx; 118 119 #ifndef __x86_64__ 120 /* See if we can use cpuid. On AMD64 we always can. */ 121 #if __GNUC__ >= 3 122 __asm__ ("pushf{l|d}\n\t" 123 "pushf{l|d}\n\t" 124 "pop{l}\t%0\n\t" 125 "mov{l}\t{%0, %1|%1, %0}\n\t" 126 "xor{l}\t{%2, %0|%0, %2}\n\t" 127 "push{l}\t%0\n\t" 128 "popf{l|d}\n\t" 129 "pushf{l|d}\n\t" 130 "pop{l}\t%0\n\t" 131 "popf{l|d}\n\t" 132 : "=&r" (__eax), "=&r" (__ebx) 133 : "i" (0x00200000)); 134 #else 135 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax 136 nor alternatives in i386 code. */ 137 __asm__ ("pushfl\n\t" 138 "pushfl\n\t" 139 "popl\t%0\n\t" 140 "movl\t%0, %1\n\t" 141 "xorl\t%2, %0\n\t" 142 "pushl\t%0\n\t" 143 "popfl\n\t" 144 "pushfl\n\t" 145 "popl\t%0\n\t" 146 "popfl\n\t" 147 : "=&r" (__eax), "=&r" (__ebx) 148 : "i" (0x00200000)); 149 #endif 150 151 if (!((__eax ^ __ebx) & 0x00200000)) 152 return 0; 153 #endif 154 155 /* Host supports cpuid. Return highest supported cpuid input value. */ 156 __cpuid (__ext, __eax, __ebx, __ecx, __edx); 157 158 if (__sig) 159 *__sig = __ebx; 160 161 return __eax; 162 } 163 164 /* Return cpuid data for requested cpuid level, as found in returned 165 eax, ebx, ecx and edx registers. The function checks if cpuid is 166 supported and returns 1 for valid cpuid information or 0 for 167 unsupported cpuid level. All pointers are required to be non-null. */ 168 169 static __inline int 170 __get_cpuid (unsigned int __level, 171 unsigned int *__eax, unsigned int *__ebx, 172 unsigned int *__ecx, unsigned int *__edx) 173 { 174 unsigned int __ext = __level & 0x80000000; 175 176 if (__get_cpuid_max (__ext, 0) < __level) 177 return 0; 178 179 __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx); 180 return 1; 181 } 182