1;; GCC machine description for Renesas H8/300 2;; Copyright (C) 1992-2013 Free Software Foundation, Inc. 3 4;; Contributed by Steve Chamberlain (sac@cygnus.com), 5;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). 6 7;; This file is part of GCC. 8 9;; GCC is free software; you can redistribute it and/or modify 10;; it under the terms of the GNU General Public License as published by 11;; the Free Software Foundation; either version 3, or (at your option) 12;; any later version. 13 14;; GCC is distributed in the hope that it will be useful, 15;; but WITHOUT ANY WARRANTY; without even the implied warranty of 16;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17;; GNU General Public License for more details. 18 19;; You should have received a copy of the GNU General Public License 20;; along with GCC; see the file COPYING3. If not see 21;; <http://www.gnu.org/licenses/>. 22 23;; We compute exact length on each instruction for most of the time. 24;; In some case, most notably bit operations that may involve memory 25;; operands, the lengths in this file are "worst case". 26 27;; On the H8/300H and H8S, adds/subs operate on the 32bit "er" 28;; registers. Right now GCC doesn't expose the "e" half to the 29;; compiler, so using add/subs for addhi and subhi is safe. Long 30;; term, we want to expose the "e" half to the compiler (gives us 8 31;; more 16bit registers). At that point addhi and subhi can't use 32;; adds/subs. 33 34;; There's currently no way to have an insv/extzv expander for the H8/300H 35;; because word_mode is different for the H8/300 and H8/300H. 36 37;; Shifts/rotates by small constants should be handled by special 38;; patterns so we get the length and cc status correct. 39 40;; Bitfield operations no longer accept memory operands. We need 41;; to add variants which operate on memory back to the MD. 42 43;; ??? Implement remaining bit ops available on the h8300 44 45;; ---------------------------------------------------------------------- 46;; CONSTANTS 47;; ---------------------------------------------------------------------- 48 49(define_constants 50 [(UNSPEC_INCDEC 0) 51 (UNSPEC_MONITOR 1)]) 52 53(define_constants 54 [(UNSPEC_MOVMD 100) 55 (UNSPEC_STPCPY 101)]) 56 57(define_constants 58 [(R0_REG 0) 59 (SC_REG 3) 60 (COUNTER_REG 4) 61 (SOURCE_REG 5) 62 (DESTINATION_REG 6) 63 (HFP_REG 6) 64 (SP_REG 7) 65 (MAC_REG 8) 66 (AP_REG 9) 67 (RAP_REG 10) 68 (FP_REG 11)]) 69 70;; ---------------------------------------------------------------------- 71;; ATTRIBUTES 72;; ---------------------------------------------------------------------- 73 74(define_attr "cpu" "h8300,h8300h" 75 (const (symbol_ref "cpu_type"))) 76 77(define_attr "type" "branch,arith,bitbranch,call" 78 (const_string "arith")) 79 80(define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch" 81 (const_string "none")) 82 83;; The size of instructions in bytes. 84 85(define_attr "length" "" 86 (cond [(eq_attr "type" "branch") 87 ;; In a forward delayed branch, (pc) represents the end of the 88 ;; delay sequence, not the end of the branch itself. 89 (if_then_else (and (ge (minus (match_dup 0) (pc)) 90 (const_int -126)) 91 (le (plus (minus (match_dup 0) (pc)) 92 (symbol_ref "DELAY_SLOT_LENGTH (insn)")) 93 (const_int 125))) 94 (const_int 2) 95 (if_then_else (and (eq_attr "cpu" "h8300h") 96 (and (ge (minus (pc) (match_dup 0)) 97 (const_int -32000)) 98 (le (minus (pc) (match_dup 0)) 99 (const_int 32000)))) 100 (const_int 4) 101 (const_int 6))) 102 (eq_attr "type" "bitbranch") 103 (if_then_else (and (ge (minus (match_dup 0) (pc)) 104 (const_int -126)) 105 (le (minus (match_dup 0) (pc)) 106 (const_int 126))) 107 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)") 108 (const_int 2)) 109 (if_then_else (and (eq_attr "cpu" "h8300h") 110 (and (ge (minus (pc) (match_dup 0)) 111 (const_int -32000)) 112 (le (minus (pc) (match_dup 0)) 113 (const_int 32000)))) 114 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)") 115 (const_int 4)) 116 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)") 117 (const_int 6)))) 118 (eq_attr "length_table" "!none") 119 (symbol_ref "h8300_insn_length_from_table (insn, operands)")] 120 (const_int 200))) 121 122;; Condition code settings. 123;; 124;; none - insn does not affect cc 125;; none_0hit - insn does not affect cc but it does modify operand 0 126;; This attribute is used to keep track of when operand 0 changes. 127;; See the description of NOTICE_UPDATE_CC for more info. 128;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown. 129;; set_zn - insn sets z,n to usable values; v,c are unknown. 130;; compare - compare instruction 131;; clobber - value of cc is unknown 132 133(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber" 134 (const_string "clobber")) 135 136;; Type of delay slot. NONE means the instruction has no delay slot. 137;; JUMP means it is an unconditional jump that (if short enough) 138;; could be implemented using bra/s. 139 140(define_attr "delay_slot" "none,jump" 141 (const_string "none")) 142 143;; "yes" if the instruction can be put into a delay slot. It's not 144;; entirely clear that jsr is not valid in delay slots, but it 145;; definitely doesn't have the effect of causing the called function 146;; to return to the target of the delayed branch. 147 148(define_attr "can_delay" "no,yes" 149 (cond [(eq_attr "type" "branch,bitbranch,call") 150 (const_string "no") 151 (geu (symbol_ref "get_attr_length (insn)") (const_int 2)) 152 (const_string "no")] 153 (const_string "yes"))) 154 155;; Only allow jumps to have a delay slot if we think they might 156;; be short enough. This is just an optimization: we don't know 157;; for certain whether they will be or not. 158 159(define_delay (and (eq_attr "delay_slot" "jump") 160 (eq (symbol_ref "get_attr_length (insn)") (const_int 2))) 161 [(eq_attr "can_delay" "yes") 162 (nil) 163 (nil)]) 164 165;; Provide the maximum length of an assembly instruction in an asm 166;; statement. The maximum length of 14 bytes is achieved on H8SX. 167 168(define_asm_attributes 169 [(set (attr "length") 170 (cond [(match_test "TARGET_H8300") (const_int 4) 171 (match_test "TARGET_H8300H") (const_int 10) 172 (match_test "TARGET_H8300S") (const_int 10)] 173 (const_int 14)))]) 174 175(include "predicates.md") 176(include "constraints.md") 177 178;; ---------------------------------------------------------------------- 179;; MACRO DEFINITIONS 180;; ---------------------------------------------------------------------- 181 182;; This mode iterator allows :P to be used for patterns that operate on 183;; pointer-sized quantities. Exactly one of the two alternatives will match. 184 185(define_mode_iterator P [(HI "Pmode == HImode") (SI "Pmode == SImode")]) 186 187 188;; ---------------------------------------------------------------------- 189;; MOVE INSTRUCTIONS 190;; ---------------------------------------------------------------------- 191 192;; movqi 193 194(define_insn "*movqi_h8300" 195 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m") 196 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))] 197 "TARGET_H8300 198 && h8300_move_ok (operands[0], operands[1])" 199 "@ 200 sub.b %X0,%X0 201 mov.b %R1,%X0 202 mov.b %X1,%R0 203 mov.b %R1,%X0 204 mov.b %R1,%X0 205 mov.b %X1,%R0" 206 [(set_attr "length" "2,2,2,2,4,4") 207 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")]) 208 209(define_insn "*movqi_h8300hs" 210 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m") 211 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))] 212 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX 213 && h8300_move_ok (operands[0], operands[1])" 214 "@ 215 sub.b %X0,%X0 216 mov.b %R1,%X0 217 mov.b %X1,%R0 218 mov.b %R1,%X0 219 mov.b %R1,%X0 220 mov.b %X1,%R0" 221 [(set (attr "length") 222 (symbol_ref "compute_mov_length (operands)")) 223 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")]) 224 225(define_insn "*movqi_h8sx" 226 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ") 227 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))] 228 "TARGET_H8300SX" 229 "@ 230 mov.b %X1:4,%X0 231 mov.b %X1,%X0" 232 [(set_attr "length_table" "mov_imm4,movb") 233 (set_attr "cc" "set_znv")]) 234 235(define_expand "movqi" 236 [(set (match_operand:QI 0 "general_operand_dst" "") 237 (match_operand:QI 1 "general_operand_src" ""))] 238 "" 239 { 240 /* One of the ops has to be in a register. */ 241 if (!TARGET_H8300SX && !h8300_move_ok (operands[0], operands[1])) 242 operands[1] = copy_to_mode_reg (QImode, operands[1]); 243 }) 244 245(define_insn "movstrictqi" 246 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r")) 247 (match_operand:QI 1 "general_operand_src" "I,rmi>"))] 248 "" 249 "@ 250 sub.b %X0,%X0 251 mov.b %X1,%X0" 252 [(set_attr "length" "2,*") 253 (set_attr "length_table" "*,movb") 254 (set_attr "cc" "set_zn,set_znv")]) 255 256;; movhi 257 258(define_insn "*movhi_h8300" 259 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m") 260 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))] 261 "TARGET_H8300 262 && h8300_move_ok (operands[0], operands[1])" 263 "@ 264 sub.w %T0,%T0 265 mov.w %T1,%T0 266 mov.w %T1,%T0 267 mov.w %T1,%T0 268 mov.w %T1,%T0 269 mov.w %T1,%T0" 270 [(set (attr "length") 271 (symbol_ref "compute_mov_length (operands)")) 272 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")]) 273 274(define_insn "*movhi_h8300hs" 275 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m") 276 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))] 277 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX 278 && h8300_move_ok (operands[0], operands[1])" 279 "@ 280 sub.w %T0,%T0 281 mov.w %T1,%T0 282 mov.w %T1,%T0 283 mov.w %T1,%T0 284 mov.w %T1,%T0 285 mov.w %T1,%T0" 286 [(set (attr "length") 287 (symbol_ref "compute_mov_length (operands)")) 288 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")]) 289 290(define_insn "*movhi_h8sx" 291 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ") 292 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))] 293 "TARGET_H8300SX" 294 "@ 295 sub.w %T0,%T0 296 mov.w %T1:3,%T0 297 mov.w %T1:4,%T0 298 mov.w %T1,%T0 299 mov.w %T1,%T0" 300 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw") 301 (set_attr "length" "2,2,*,*,*") 302 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")]) 303 304(define_expand "movhi" 305 [(set (match_operand:HI 0 "general_operand_dst" "") 306 (match_operand:HI 1 "general_operand_src" ""))] 307 "" 308 { 309 /* One of the ops has to be in a register. */ 310 if (!h8300_move_ok (operands[0], operands[1])) 311 operands[1] = copy_to_mode_reg (HImode, operand1); 312 }) 313 314(define_insn "movstricthi" 315 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r")) 316 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))] 317 "" 318 "@ 319 sub.w %T0,%T0 320 mov.w %T1,%T0 321 mov.w %T1,%T0" 322 [(set_attr "length" "2,2,*") 323 (set_attr "length_table" "*,*,movw") 324 (set_attr "cc" "set_zn,set_znv,set_znv")]) 325 326;; movsi 327 328(define_expand "movsi" 329 [(set (match_operand:SI 0 "general_operand_dst" "") 330 (match_operand:SI 1 "general_operand_src" ""))] 331 "" 332 { 333 if (TARGET_H8300) 334 { 335 if (h8300_expand_movsi (operands)) 336 DONE; 337 } 338 else if (!TARGET_H8300SX) 339 { 340 /* One of the ops has to be in a register. */ 341 if (!h8300_move_ok (operands[0], operands[1])) 342 operands[1] = copy_to_mode_reg (SImode, operand1); 343 } 344 }) 345 346(define_insn "*movsi_h8300" 347 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r") 348 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))] 349 "TARGET_H8300 350 && h8300_move_ok (operands[0], operands[1])" 351{ 352 unsigned int rn = -1; 353 switch (which_alternative) 354 { 355 case 0: 356 return "sub.w %e0,%e0\;sub.w %f0,%f0"; 357 case 1: 358 if (REGNO (operands[0]) < REGNO (operands[1])) 359 return "mov.w %e1,%e0\;mov.w %f1,%f0"; 360 else 361 return "mov.w %f1,%f0\;mov.w %e1,%e0"; 362 case 2: 363 /* Make sure we don't trample the register we index with. */ 364 if (GET_CODE (operands[1]) == MEM) 365 { 366 rtx inside = XEXP (operands[1], 0); 367 if (REG_P (inside)) 368 { 369 rn = REGNO (inside); 370 } 371 else if (GET_CODE (inside) == PLUS) 372 { 373 rtx lhs = XEXP (inside, 0); 374 rtx rhs = XEXP (inside, 1); 375 if (REG_P (lhs)) rn = REGNO (lhs); 376 if (REG_P (rhs)) rn = REGNO (rhs); 377 } 378 } 379 if (rn == REGNO (operands[0])) 380 { 381 /* Move the second word first. */ 382 return "mov.w %f1,%f0\;mov.w %e1,%e0"; 383 } 384 else 385 { 386 if (GET_CODE (operands[1]) == CONST_INT) 387 { 388 /* If either half is zero, use sub.w to clear that 389 half. */ 390 if ((INTVAL (operands[1]) & 0xffff) == 0) 391 return "mov.w %e1,%e0\;sub.w %f0,%f0"; 392 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0) 393 return "sub.w %e0,%e0\;mov.w %f1,%f0"; 394 /* If the upper half and the lower half are the same, 395 copy one half to the other. */ 396 if ((INTVAL (operands[1]) & 0xffff) 397 == ((INTVAL (operands[1]) >> 16) & 0xffff)) 398 return "mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0"; 399 } 400 return "mov.w %e1,%e0\;mov.w %f1,%f0"; 401 } 402 case 3: 403 return "mov.w %e1,%e0\;mov.w %f1,%f0"; 404 case 4: 405 return "mov.w %f1,%T0\;mov.w %e1,%T0"; 406 case 5: 407 return "mov.w %T1,%e0\;mov.w %T1,%f0"; 408 default: 409 gcc_unreachable (); 410 } 411} 412 [(set (attr "length") 413 (symbol_ref "compute_mov_length (operands)"))]) 414 415(define_insn "*movsi_h8300hs" 416 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r") 417 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))] 418 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX 419 && h8300_move_ok (operands[0], operands[1])" 420{ 421 switch (which_alternative) 422 { 423 case 0: 424 return "sub.l %S0,%S0"; 425 case 7: 426 return "clrmac"; 427 case 8: 428 return "clrmac\;ldmac %1,macl"; 429 case 9: 430 return "stmac macl,%0"; 431 default: 432 if (GET_CODE (operands[1]) == CONST_INT) 433 { 434 int val = INTVAL (operands[1]); 435 436 /* Look for constants which can be made by adding an 8-bit 437 number to zero in one of the two low bytes. */ 438 if (val == (val & 0xff)) 439 { 440 operands[1] = GEN_INT ((char) val & 0xff); 441 return "sub.l\\t%S0,%S0\;add.b\\t%1,%w0"; 442 } 443 444 if (val == (val & 0xff00)) 445 { 446 operands[1] = GEN_INT ((char) (val >> 8) & 0xff); 447 return "sub.l\\t%S0,%S0\;add.b\\t%1,%x0"; 448 } 449 450 /* Look for constants that can be obtained by subs, inc, and 451 dec to 0. */ 452 switch (val & 0xffffffff) 453 { 454 case 0xffffffff: 455 return "sub.l\\t%S0,%S0\;subs\\t#1,%S0"; 456 case 0xfffffffe: 457 return "sub.l\\t%S0,%S0\;subs\\t#2,%S0"; 458 case 0xfffffffc: 459 return "sub.l\\t%S0,%S0\;subs\\t#4,%S0"; 460 461 case 0x0000ffff: 462 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%f0"; 463 case 0x0000fffe: 464 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%f0"; 465 466 case 0xffff0000: 467 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%e0"; 468 case 0xfffe0000: 469 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%e0"; 470 471 case 0x00010000: 472 return "sub.l\\t%S0,%S0\;inc.w\\t#1,%e0"; 473 case 0x00020000: 474 return "sub.l\\t%S0,%S0\;inc.w\\t#2,%e0"; 475 } 476 } 477 } 478 return "mov.l %S1,%S0"; 479} 480 [(set (attr "length") 481 (symbol_ref "compute_mov_length (operands)")) 482 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")]) 483 484(define_insn "*movsi_h8sx" 485 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r") 486 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))] 487 "TARGET_H8300SX" 488 "@ 489 sub.l %S0,%S0 490 mov.l %S1:3,%S0 491 mov.l %S1,%S0 492 mov.l %S1,%S0 493 clrmac 494 clrmac\;ldmac %1,macl 495 stmac macl,%0" 496 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*") 497 (set_attr "length" "2,2,*,*,2,6,4") 498 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")]) 499 500(define_insn "*movsf_h8sx" 501 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ") 502 (match_operand:SF 1 "general_operand_src" "G,rQi"))] 503 "TARGET_H8300SX" 504 "@ 505 sub.l %S0,%S0 506 mov.l %S1,%S0" 507 [(set_attr "length" "2,*") 508 (set_attr "length_table" "*,movl") 509 (set_attr "cc" "set_zn,set_znv")]) 510 511;; Implement block moves using movmd. Defining movmemsi allows the full 512;; range of constant lengths (up to 0x40000 bytes when using movmd.l). 513;; See h8sx_emit_movmd for details. 514 515(define_expand "movmemsi" 516 [(use (match_operand:BLK 0 "memory_operand" "")) 517 (use (match_operand:BLK 1 "memory_operand" "")) 518 (use (match_operand:SI 2 "" "")) 519 (use (match_operand:SI 3 "const_int_operand" ""))] 520 "TARGET_H8300SX" 521 { 522 if (h8sx_emit_movmd (operands[0], operands[1], operands[2], INTVAL (operands[3]))) 523 DONE; 524 else 525 FAIL; 526 }) 527 528;; Expander for generating movmd insns. Operand 0 is the destination 529;; memory region, operand 1 is the source, operand 2 is the counter 530;; register and operand 3 is the chunk size (1, 2 or 4). 531 532(define_expand "movmd" 533 [(parallel 534 [(set (match_operand:BLK 0 "memory_operand" "") 535 (match_operand:BLK 1 "memory_operand" "")) 536 (unspec [(match_operand:HI 2 "register_operand" "") 537 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD) 538 (clobber (match_dup 4)) 539 (clobber (match_dup 5)) 540 (set (match_dup 2) 541 (const_int 0))])] 542 "TARGET_H8300SX" 543 { 544 operands[4] = copy_rtx (XEXP (operands[0], 0)); 545 operands[5] = copy_rtx (XEXP (operands[1], 0)); 546 }) 547 548;; This is a difficult instruction to reload since operand 0 must be the 549;; frame pointer. See h8300_reg_class_from_letter for an explanation. 550 551(define_insn "movmd_internal_normal" 552 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r")) 553 (mem:BLK (match_operand:HI 4 "register_operand" "1,1"))) 554 (unspec [(match_operand:HI 5 "register_operand" "2,2") 555 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD) 556 (clobber (match_operand:HI 0 "register_operand" "=d,??D")) 557 (clobber (match_operand:HI 1 "register_operand" "=f,f")) 558 (set (match_operand:HI 2 "register_operand" "=c,c") 559 (const_int 0))] 560 "TARGET_H8300SX && TARGET_NORMAL_MODE" 561 "@ 562 movmd%m6 563 #" 564 [(set_attr "length" "2,14") 565 (set_attr "can_delay" "no") 566 (set_attr "cc" "none,clobber")]) 567 568(define_insn "movmd_internal" 569 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r")) 570 (mem:BLK (match_operand:SI 4 "register_operand" "1,1"))) 571 (unspec [(match_operand:HI 5 "register_operand" "2,2") 572 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD) 573 (clobber (match_operand:SI 0 "register_operand" "=d,??D")) 574 (clobber (match_operand:SI 1 "register_operand" "=f,f")) 575 (set (match_operand:HI 2 "register_operand" "=c,c") 576 (const_int 0))] 577 "TARGET_H8300SX && !TARGET_NORMAL_MODE" 578 "@ 579 movmd%m6 580 #" 581 [(set_attr "length" "2,14") 582 (set_attr "can_delay" "no") 583 (set_attr "cc" "none,clobber")]) 584 585;; Split the above instruction if the destination register isn't er6. 586;; We need a sequence like: 587;; 588;; mov.l er6,@-er7 589;; mov.l <dest>,er6 590;; movmd.sz 591;; mov.l er6,<dest> 592;; mov.l @er7+,er6 593;; 594;; where <dest> is the current destination register (operand 4). 595;; The fourth instruction will be deleted if <dest> dies here. 596 597(define_split 598 [(set (match_operand:BLK 0 "memory_operand" "") 599 (match_operand:BLK 1 "memory_operand" "")) 600 (unspec [(match_operand:HI 2 "register_operand" "") 601 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD) 602 (clobber (match_operand:HI 4 "register_operand" "")) 603 (clobber (match_operand:HI 5 "register_operand" "")) 604 (set (match_dup 2) 605 (const_int 0))] 606 "TARGET_H8300SX && TARGET_NORMAL_MODE && reload_completed 607 && REGNO (operands[4]) != DESTINATION_REG" 608 [(const_int 0)] 609 { 610 rtx dest; 611 612 h8300_swap_into_er6 (XEXP (operands[0], 0)); 613 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx); 614 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3])); 615 h8300_swap_out_of_er6 (operands[4]); 616 DONE; 617 }) 618 619(define_split 620 [(set (match_operand:BLK 0 "memory_operand" "") 621 (match_operand:BLK 1 "memory_operand" "")) 622 (unspec [(match_operand:HI 2 "register_operand" "") 623 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD) 624 (clobber (match_operand:SI 4 "register_operand" "")) 625 (clobber (match_operand:SI 5 "register_operand" "")) 626 (set (match_dup 2) 627 (const_int 0))] 628 "TARGET_H8300SX && !TARGET_NORMAL_MODE && reload_completed 629 && REGNO (operands[4]) != DESTINATION_REG" 630 [(const_int 0)] 631 { 632 rtx dest; 633 634 h8300_swap_into_er6 (XEXP (operands[0], 0)); 635 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx); 636 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3])); 637 h8300_swap_out_of_er6 (operands[4]); 638 DONE; 639 }) 640 641;; Expand a call to stpcpy() using movsd. Operand 0 should point to 642;; the final character, but movsd leaves it pointing to the character 643;; after that. 644 645(define_expand "movstr" 646 [(use (match_operand 0 "register_operand" "")) 647 (use (match_operand:BLK 1 "memory_operand" "")) 648 (use (match_operand:BLK 2 "memory_operand" ""))] 649 "TARGET_H8300SX" 650 { 651 operands[1] = replace_equiv_address 652 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); 653 operands[2] = replace_equiv_address 654 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0))); 655 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode))); 656 emit_insn (gen_add3_insn (operands[0], XEXP (operands[1], 0), constm1_rtx)); 657 DONE; 658 }) 659 660;; Expander for generating a movsd instruction. Operand 0 is the 661;; destination string, operand 1 is the source string and operand 2 662;; is a scratch register. 663 664(define_expand "movsd" 665 [(parallel 666 [(set (match_operand:BLK 0 "memory_operand" "") 667 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] 668 UNSPEC_STPCPY)) 669 (clobber (match_dup 3)) 670 (clobber (match_dup 4)) 671 (clobber (match_operand 2 "register_operand" ""))])] 672 "TARGET_H8300SX" 673 { 674 operands[3] = copy_rtx (XEXP (operands[0], 0)); 675 operands[4] = copy_rtx (XEXP (operands[1], 0)); 676 }) 677 678;; See comments above memcpy_internal(). 679 680(define_insn "stpcpy_internal_normal" 681 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r")) 682 (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))] 683 UNSPEC_STPCPY)) 684 (clobber (match_operand:HI 0 "register_operand" "=d,??D")) 685 (clobber (match_operand:HI 1 "register_operand" "=f,f")) 686 (clobber (match_operand:HI 2 "register_operand" "=c,c"))] 687 "TARGET_H8300SX && TARGET_NORMAL_MODE" 688 "@ 689 \n1:\tmovsd\t2f\;bra\t1b\n2: 690 #" 691 [(set_attr "length" "6,18") 692 (set_attr "cc" "none,clobber")]) 693 694(define_insn "stpcpy_internal" 695 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r")) 696 (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))] 697 UNSPEC_STPCPY)) 698 (clobber (match_operand:SI 0 "register_operand" "=d,??D")) 699 (clobber (match_operand:SI 1 "register_operand" "=f,f")) 700 (clobber (match_operand:SI 2 "register_operand" "=c,c"))] 701 "TARGET_H8300SX && !TARGET_NORMAL_MODE" 702 "@ 703 \n1:\tmovsd\t2f\;bra\t1b\n2: 704 #" 705 [(set_attr "length" "6,18") 706 (set_attr "cc" "none,clobber")]) 707 708;; Split the above instruction if the destination isn't er6. This works 709;; in the same way as the movmd splitter. 710 711(define_split 712 [(set (match_operand:BLK 0 "memory_operand" "") 713 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY)) 714 (clobber (match_operand:HI 2 "register_operand" "")) 715 (clobber (match_operand:HI 3 "register_operand" "")) 716 (clobber (match_operand:HI 4 "register_operand" ""))] 717 "TARGET_H8300SX && TARGET_NORMAL_MODE && reload_completed 718 && REGNO (operands[2]) != DESTINATION_REG" 719 [(const_int 0)] 720 { 721 rtx dest; 722 723 h8300_swap_into_er6 (XEXP (operands[0], 0)); 724 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx); 725 emit_insn (gen_movsd (dest, operands[1], operands[4])); 726 h8300_swap_out_of_er6 (operands[2]); 727 DONE; 728 }) 729 730(define_split 731 [(set (match_operand:BLK 0 "memory_operand" "") 732 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY)) 733 (clobber (match_operand:SI 2 "register_operand" "")) 734 (clobber (match_operand:SI 3 "register_operand" "")) 735 (clobber (match_operand:SI 4 "register_operand" ""))] 736 "TARGET_H8300SX && !TARGET_NORMAL_MODE && reload_completed 737 && REGNO (operands[2]) != DESTINATION_REG" 738 [(const_int 0)] 739 { 740 rtx dest; 741 742 h8300_swap_into_er6 (XEXP (operands[0], 0)); 743 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx); 744 emit_insn (gen_movsd (dest, operands[1], operands[4])); 745 h8300_swap_out_of_er6 (operands[2]); 746 DONE; 747 }) 748 749(include "mova.md") 750 751(define_expand "movsf" 752 [(set (match_operand:SF 0 "general_operand_dst" "") 753 (match_operand:SF 1 "general_operand_src" ""))] 754 "" 755 { 756 if (TARGET_H8300) 757 { 758 if (h8300_expand_movsi (operands)) 759 DONE; 760 } 761 else if (!TARGET_H8300SX) 762 { 763 /* One of the ops has to be in a register. */ 764 if (!register_operand (operand1, SFmode) 765 && !register_operand (operand0, SFmode)) 766 { 767 operands[1] = copy_to_mode_reg (SFmode, operand1); 768 } 769 } 770 }) 771 772(define_insn "*movsf_h8300" 773 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r") 774 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))] 775 "TARGET_H8300 776 && (register_operand (operands[0], SFmode) 777 || register_operand (operands[1], SFmode))" 778{ 779 /* Copy of the movsi stuff. */ 780 unsigned int rn = -1; 781 switch (which_alternative) 782 { 783 case 0: 784 return "sub.w %e0,%e0\;sub.w %f0,%f0"; 785 case 1: 786 if (REGNO (operands[0]) < REGNO (operands[1])) 787 return "mov.w %e1,%e0\;mov.w %f1,%f0"; 788 else 789 return "mov.w %f1,%f0\;mov.w %e1,%e0"; 790 case 2: 791 /* Make sure we don't trample the register we index with. */ 792 if (GET_CODE (operands[1]) == MEM) 793 { 794 rtx inside = XEXP (operands[1], 0); 795 if (REG_P (inside)) 796 { 797 rn = REGNO (inside); 798 } 799 else if (GET_CODE (inside) == PLUS) 800 { 801 rtx lhs = XEXP (inside, 0); 802 rtx rhs = XEXP (inside, 1); 803 if (REG_P (lhs)) rn = REGNO (lhs); 804 if (REG_P (rhs)) rn = REGNO (rhs); 805 } 806 } 807 if (rn == REGNO (operands[0])) 808 /* Move the second word first. */ 809 return "mov.w %f1,%f0\;mov.w %e1,%e0"; 810 else 811 /* Move the first word first. */ 812 return "mov.w %e1,%e0\;mov.w %f1,%f0"; 813 814 case 3: 815 return "mov.w %e1,%e0\;mov.w %f1,%f0"; 816 case 4: 817 return "mov.w %f1,%T0\;mov.w %e1,%T0"; 818 case 5: 819 return "mov.w %T1,%e0\;mov.w %T1,%f0"; 820 default: 821 gcc_unreachable (); 822 } 823} 824 [(set (attr "length") 825 (symbol_ref "compute_mov_length (operands)"))]) 826 827(define_insn "*movsf_h8300hs" 828 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r") 829 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))] 830 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX 831 && (register_operand (operands[0], SFmode) 832 || register_operand (operands[1], SFmode))" 833 "@ 834 sub.l %S0,%S0 835 mov.l %S1,%S0 836 mov.l %S1,%S0 837 mov.l %S1,%S0 838 mov.l %S1,%S0 839 mov.l %S1,%S0" 840 [(set (attr "length") 841 (symbol_ref "compute_mov_length (operands)")) 842 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")]) 843 844;; ---------------------------------------------------------------------- 845;; PUSH INSTRUCTIONS 846;; ---------------------------------------------------------------------- 847 848(define_insn "*pushqi1_h8300" 849 [(set (mem:QI 850 (pre_modify:HI 851 (reg:HI SP_REG) 852 (plus:HI (reg:HI SP_REG) (const_int -2)))) 853 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))] 854 "TARGET_H8300" 855 "mov.w\\t%T0,@-r7" 856 [(set_attr "length" "2")]) 857 858(define_insn "*pushqi1_h8300hs_<mode>" 859 [(set (mem:QI 860 (pre_modify:P 861 (reg:P SP_REG) 862 (plus:P (reg:P SP_REG) (const_int -4)))) 863 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))] 864 "TARGET_H8300H || TARGET_H8300S" 865 "mov.l\\t%S0,@-er7" 866 [(set_attr "length" "4")]) 867 868(define_insn "*pushhi1_h8300hs_<mode>" 869 [(set (mem:HI 870 (pre_modify:P 871 (reg:P SP_REG) 872 (plus:P (reg:P SP_REG) (const_int -4)))) 873 (match_operand:HI 0 "register_no_sp_elim_operand" "r"))] 874 "TARGET_H8300H || TARGET_H8300S" 875 "mov.l\\t%S0,@-er7" 876 [(set_attr "length" "4")]) 877 878;; ---------------------------------------------------------------------- 879;; TEST INSTRUCTIONS 880;; ---------------------------------------------------------------------- 881 882(define_insn "" 883 [(set (cc0) 884 (compare (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U") 885 (const_int 1) 886 (match_operand 1 "const_int_operand" "n,n")) 887 (const_int 0)))] 888 "TARGET_H8300" 889 "btst %Z1,%Y0" 890 [(set_attr "length" "2,4") 891 (set_attr "cc" "set_zn,set_zn")]) 892 893(define_insn "" 894 [(set (cc0) 895 (compare (zero_extract:HI (match_operand:HI 0 "register_operand" "r") 896 (const_int 1) 897 (match_operand 1 "const_int_operand" "n")) 898 (const_int 0)))] 899 "TARGET_H8300" 900 "btst %Z1,%Y0" 901 [(set_attr "length" "2") 902 (set_attr "cc" "set_zn")]) 903 904(define_insn_and_split "*tst_extzv_1_n" 905 [(set (cc0) 906 (compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>") 907 (const_int 1) 908 (match_operand 1 "const_int_operand" "n,n,n")) 909 (const_int 0))) 910 (clobber (match_scratch:QI 2 "=X,X,&r"))] 911 "TARGET_H8300H || TARGET_H8300S" 912 "@ 913 btst\\t%Z1,%Y0 914 btst\\t%Z1,%Y0 915 #" 916 "&& reload_completed 917 && !satisfies_constraint_U (operands[0])" 918 [(set (match_dup 2) 919 (match_dup 0)) 920 (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2) 921 (const_int 1) 922 (match_dup 1)) 923 (const_int 0))) 924 (clobber (scratch:QI))])] 925 "" 926 [(set_attr "length" "2,8,10") 927 (set_attr "cc" "set_zn,set_zn,set_zn")]) 928 929(define_insn "" 930 [(set (cc0) 931 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 932 (const_int 1) 933 (match_operand 1 "const_int_operand" "n")) 934 (const_int 0)))] 935 "(TARGET_H8300H || TARGET_H8300S) 936 && INTVAL (operands[1]) <= 15" 937 "btst %Z1,%Y0" 938 [(set_attr "length" "2") 939 (set_attr "cc" "set_zn")]) 940 941(define_insn_and_split "*tstsi_upper_bit" 942 [(set (cc0) 943 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 944 (const_int 1) 945 (match_operand 1 "const_int_operand" "n")) 946 (const_int 0))) 947 (clobber (match_scratch:SI 2 "=&r"))] 948 "(TARGET_H8300H || TARGET_H8300S) 949 && INTVAL (operands[1]) >= 16" 950 "#" 951 "&& reload_completed" 952 [(set (match_dup 2) 953 (ior:SI (and:SI (match_dup 2) 954 (const_int -65536)) 955 (lshiftrt:SI (match_dup 0) 956 (const_int 16)))) 957 (set (cc0) 958 (compare (zero_extract:SI (match_dup 2) 959 (const_int 1) 960 (match_dup 3)) 961 (const_int 0)))] 962 { 963 operands[3] = GEN_INT (INTVAL (operands[1]) - 16); 964 }) 965 966(define_insn "*tstsi_variable_bit" 967 [(set (cc0) 968 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 969 (const_int 1) 970 (and:SI (match_operand:SI 1 "register_operand" "r") 971 (const_int 7))) 972 (const_int 0)))] 973 "TARGET_H8300H || TARGET_H8300S" 974 "btst %w1,%w0" 975 [(set_attr "length" "2") 976 (set_attr "cc" "set_zn")]) 977 978(define_insn_and_split "*tstsi_variable_bit_qi" 979 [(set (cc0) 980 (compare (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")) 981 (const_int 1) 982 (and:SI (match_operand:SI 1 "register_operand" "r,r,r") 983 (const_int 7))) 984 (const_int 0))) 985 (clobber (match_scratch:QI 2 "=X,X,&r"))] 986 "TARGET_H8300H || TARGET_H8300S" 987 "@ 988 btst\\t%w1,%X0 989 btst\\t%w1,%X0 990 #" 991 "&& reload_completed 992 && !satisfies_constraint_U (operands[0])" 993 [(set (match_dup 2) 994 (match_dup 0)) 995 (parallel [(set (cc0) 996 (compare (zero_extract:SI (zero_extend:SI (match_dup 2)) 997 (const_int 1) 998 (and:SI (match_dup 1) 999 (const_int 7))) 1000 (const_int 0))) 1001 (clobber (scratch:QI))])] 1002 "" 1003 [(set_attr "length" "2,8,10") 1004 (set_attr "cc" "set_zn,set_zn,set_zn")]) 1005 1006(define_insn "*tstqi" 1007 [(set (cc0) 1008 (compare (match_operand:QI 0 "register_operand" "r") 1009 (const_int 0)))] 1010 "" 1011 "mov.b %X0,%X0" 1012 [(set_attr "length" "2") 1013 (set_attr "cc" "set_znv")]) 1014 1015(define_insn "*tsthi" 1016 [(set (cc0) 1017 (compare (match_operand:HI 0 "register_operand" "r") 1018 (const_int 0)))] 1019 "" 1020 "mov.w %T0,%T0" 1021 [(set_attr "length" "2") 1022 (set_attr "cc" "set_znv")]) 1023 1024(define_insn "*tsthi_upper" 1025 [(set (cc0) 1026 (compare (and:HI (match_operand:HI 0 "register_operand" "r") 1027 (const_int -256)) 1028 (const_int 0)))] 1029 "" 1030 "mov.b %t0,%t0" 1031 [(set_attr "length" "2") 1032 (set_attr "cc" "set_znv")]) 1033 1034(define_insn "*tstsi" 1035 [(set (cc0) 1036 (compare (match_operand:SI 0 "register_operand" "r") 1037 (const_int 0)))] 1038 "TARGET_H8300H || TARGET_H8300S" 1039 "mov.l %S0,%S0" 1040 [(set_attr "length" "2") 1041 (set_attr "cc" "set_znv")]) 1042 1043(define_insn "*tstsi_upper" 1044 [(set (cc0) 1045 (compare (and:SI (match_operand:SI 0 "register_operand" "r") 1046 (const_int -65536)) 1047 (const_int 0)))] 1048 "" 1049 "mov.w %e0,%e0" 1050 [(set_attr "length" "2") 1051 (set_attr "cc" "set_znv")]) 1052 1053(define_insn "*cmpqi" 1054 [(set (cc0) 1055 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ") 1056 (match_operand:QI 1 "h8300_src_operand" "rQi")))] 1057 "" 1058 "cmp.b %X1,%X0" 1059 [(set_attr "length_table" "addb") 1060 (set_attr "cc" "compare")]) 1061 1062(define_insn "*cmphi_h8300_znvc" 1063 [(set (cc0) 1064 (compare (match_operand:HI 0 "register_operand" "r") 1065 (match_operand:HI 1 "register_operand" "r")))] 1066 "TARGET_H8300" 1067 "cmp.w %T1,%T0" 1068 [(set_attr "length" "2") 1069 (set_attr "cc" "compare")]) 1070 1071(define_insn "*cmphi_h8300hs_znvc" 1072 [(set (cc0) 1073 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ") 1074 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))] 1075 "TARGET_H8300H || TARGET_H8300S" 1076{ 1077 switch (which_alternative) 1078 { 1079 case 0: 1080 if (!TARGET_H8300SX) 1081 return "cmp.w %T1,%T0"; 1082 else 1083 return "cmp.w %T1:3,%T0"; 1084 case 1: 1085 return "cmp.w %T1,%T0"; 1086 default: 1087 gcc_unreachable (); 1088 } 1089} 1090 [(set_attr "length_table" "short_immediate,addw") 1091 (set_attr "cc" "compare,compare")]) 1092 1093(define_insn "cmpsi" 1094 [(set (cc0) 1095 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ") 1096 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))] 1097 "TARGET_H8300H || TARGET_H8300S" 1098{ 1099 switch (which_alternative) 1100 { 1101 case 0: 1102 if (!TARGET_H8300SX) 1103 return "cmp.l %S1,%S0"; 1104 else 1105 return "cmp.l %S1:3,%S0"; 1106 case 1: 1107 return "cmp.l %S1,%S0"; 1108 default: 1109 gcc_unreachable (); 1110 } 1111} 1112 [(set_attr "length" "2,*") 1113 (set_attr "length_table" "*,addl") 1114 (set_attr "cc" "compare,compare")]) 1115 1116;; ---------------------------------------------------------------------- 1117;; ADD INSTRUCTIONS 1118;; ---------------------------------------------------------------------- 1119 1120(define_expand "addqi3" 1121 [(set (match_operand:QI 0 "register_operand" "") 1122 (plus:QI (match_operand:QI 1 "register_operand" "") 1123 (match_operand:QI 2 "h8300_src_operand" "")))] 1124 "" 1125 "") 1126 1127(define_insn "*addqi3" 1128 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ") 1129 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0") 1130 (match_operand:QI 2 "h8300_src_operand" "rQi")))] 1131 "h8300_operands_match_p (operands)" 1132 "add.b %X2,%X0" 1133 [(set_attr "length_table" "addb") 1134 (set_attr "cc" "set_zn")]) 1135 1136(define_expand "addhi3" 1137 [(set (match_operand:HI 0 "register_operand" "") 1138 (plus:HI (match_operand:HI 1 "register_operand" "") 1139 (match_operand:HI 2 "h8300_src_operand" "")))] 1140 "" 1141 "") 1142 1143(define_insn "*addhi3_h8300" 1144 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") 1145 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0") 1146 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))] 1147 "TARGET_H8300" 1148 "@ 1149 adds %2,%T0 1150 subs %G2,%T0 1151 add.b %t2,%t0 1152 add.b %s2,%s0\;addx %t2,%t0 1153 add.w %T2,%T0" 1154 [(set_attr "length" "2,2,2,4,2") 1155 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")]) 1156 1157;; This splitter is very important to make the stack adjustment 1158;; interrupt-safe. The combination of add.b and addx is unsafe! 1159;; 1160;; We apply this split after the peephole2 pass so that we won't end 1161;; up creating too many adds/subs when a scratch register is 1162;; available, which is actually a common case because stack unrolling 1163;; tends to happen immediately after a function call. 1164 1165(define_split 1166 [(set (match_operand:HI 0 "stack_pointer_operand" "") 1167 (plus:HI (match_dup 0) 1168 (match_operand 1 "const_int_gt_2_operand" "")))] 1169 "TARGET_H8300 && epilogue_completed" 1170 [(const_int 0)] 1171 { 1172 split_adds_subs (HImode, operands); 1173 DONE; 1174 }) 1175 1176(define_peephole2 1177 [(match_scratch:HI 2 "r") 1178 (set (match_operand:HI 0 "stack_pointer_operand" "") 1179 (plus:HI (match_dup 0) 1180 (match_operand:HI 1 "const_int_ge_8_operand" "")))] 1181 "TARGET_H8300" 1182 [(set (match_dup 2) 1183 (match_dup 1)) 1184 (set (match_dup 0) 1185 (plus:HI (match_dup 0) 1186 (match_dup 2)))] 1187 "") 1188 1189(define_insn "*addhi3_h8300hs" 1190 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") 1191 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0") 1192 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))] 1193 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX" 1194 "@ 1195 adds %2,%S0 1196 subs %G2,%S0 1197 add.b %t2,%t0 1198 add.w %T2,%T0 1199 add.w %T2,%T0" 1200 [(set_attr "length" "2,2,2,4,2") 1201 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")]) 1202 1203(define_insn "*addhi3_incdec" 1204 [(set (match_operand:HI 0 "register_operand" "=r,r") 1205 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0") 1206 (match_operand:HI 2 "incdec_operand" "M,O")] 1207 UNSPEC_INCDEC))] 1208 "TARGET_H8300H || TARGET_H8300S" 1209 "@ 1210 inc.w %2,%T0 1211 dec.w %G2,%T0" 1212 [(set_attr "length" "2,2") 1213 (set_attr "cc" "set_zn,set_zn")]) 1214 1215(define_insn "*addhi3_h8sx" 1216 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ") 1217 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0") 1218 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))] 1219 "TARGET_H8300SX && h8300_operands_match_p (operands)" 1220 "@ 1221 add.w %T2:3,%T0 1222 sub.w %G2:3,%T0 1223 add.b %t2,%t0 1224 add.w %T2,%T0" 1225 [(set_attr "length_table" "short_immediate,short_immediate,*,addw") 1226 (set_attr "length" "*,*,2,*") 1227 (set_attr "cc" "set_zn")]) 1228 1229(define_split 1230 [(set (match_operand:HI 0 "register_operand" "") 1231 (plus:HI (match_dup 0) 1232 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))] 1233 "" 1234 [(const_int 0)] 1235 { 1236 split_adds_subs (HImode, operands); 1237 DONE; 1238 }) 1239 1240(define_expand "addsi3" 1241 [(set (match_operand:SI 0 "register_operand" "") 1242 (plus:SI (match_operand:SI 1 "register_operand" "") 1243 (match_operand:SI 2 "h8300_src_operand" "")))] 1244 "" 1245 "") 1246 1247(define_insn "*addsi_h8300" 1248 [(set (match_operand:SI 0 "register_operand" "=r,r") 1249 (plus:SI (match_operand:SI 1 "register_operand" "%0,0") 1250 (match_operand:SI 2 "h8300_src_operand" "n,r")))] 1251 "TARGET_H8300" 1252{ 1253 return output_plussi (operands); 1254} 1255 [(set (attr "length") 1256 (symbol_ref "compute_plussi_length (operands)")) 1257 (set (attr "cc") 1258 (symbol_ref "compute_plussi_cc (operands)"))]) 1259 1260(define_insn "*addsi_h8300hs" 1261 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ") 1262 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0") 1263 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))] 1264 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" 1265{ 1266 return output_plussi (operands); 1267} 1268 [(set (attr "length") 1269 (symbol_ref "compute_plussi_length (operands)")) 1270 (set (attr "cc") 1271 (symbol_ref "compute_plussi_cc (operands)"))]) 1272 1273(define_insn "*addsi3_incdec" 1274 [(set (match_operand:SI 0 "register_operand" "=r,r") 1275 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0") 1276 (match_operand:SI 2 "incdec_operand" "M,O")] 1277 UNSPEC_INCDEC))] 1278 "TARGET_H8300H || TARGET_H8300S" 1279 "@ 1280 inc.l %2,%S0 1281 dec.l %G2,%S0" 1282 [(set_attr "length" "2,2") 1283 (set_attr "cc" "set_zn,set_zn")]) 1284 1285(define_split 1286 [(set (match_operand:SI 0 "register_operand" "") 1287 (plus:SI (match_dup 0) 1288 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))] 1289 "TARGET_H8300H || TARGET_H8300S" 1290 [(const_int 0)] 1291 { 1292 split_adds_subs (SImode, operands); 1293 DONE; 1294 }) 1295 1296;; ---------------------------------------------------------------------- 1297;; SUBTRACT INSTRUCTIONS 1298;; ---------------------------------------------------------------------- 1299 1300(define_expand "subqi3" 1301 [(set (match_operand:QI 0 "register_operand" "") 1302 (minus:QI (match_operand:QI 1 "register_operand" "") 1303 (match_operand:QI 2 "h8300_src_operand" "")))] 1304 "" 1305 "") 1306 1307(define_insn "*subqi3" 1308 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ") 1309 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0") 1310 (match_operand:QI 2 "h8300_dst_operand" "rQ")))] 1311 "h8300_operands_match_p (operands)" 1312 "sub.b %X2,%X0" 1313 [(set_attr "length_table" "addb") 1314 (set_attr "cc" "set_zn")]) 1315 1316(define_expand "subhi3" 1317 [(set (match_operand:HI 0 "register_operand" "") 1318 (minus:HI (match_operand:HI 1 "register_operand" "") 1319 (match_operand:HI 2 "h8300_src_operand" "")))] 1320 "" 1321 "") 1322 1323(define_insn "*subhi3_h8300" 1324 [(set (match_operand:HI 0 "register_operand" "=r,r") 1325 (minus:HI (match_operand:HI 1 "register_operand" "0,0") 1326 (match_operand:HI 2 "h8300_src_operand" "r,n")))] 1327 "TARGET_H8300" 1328 "@ 1329 sub.w %T2,%T0 1330 add.b %E2,%s0\;addx %F2,%t0" 1331 [(set_attr "length" "2,4") 1332 (set_attr "cc" "set_zn,clobber")]) 1333 1334(define_insn "*subhi3_h8300hs" 1335 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ") 1336 (minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0") 1337 (match_operand:HI 2 "h8300_src_operand" "rQ,i")))] 1338 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" 1339 "@ 1340 sub.w %T2,%T0 1341 sub.w %T2,%T0" 1342 [(set_attr "length_table" "addw") 1343 (set_attr "cc" "set_zn")]) 1344 1345(define_expand "subsi3" 1346 [(set (match_operand:SI 0 "register_operand" "") 1347 (minus:SI (match_operand:SI 1 "register_operand" "") 1348 (match_operand:SI 2 "h8300_src_operand" "")))] 1349 "" 1350 { 1351 if (TARGET_H8300) 1352 operands[2] = force_reg (SImode, operands[2]); 1353 }) 1354 1355(define_insn "*subsi3_h8300" 1356 [(set (match_operand:SI 0 "register_operand" "=r") 1357 (minus:SI (match_operand:SI 1 "register_operand" "0") 1358 (match_operand:SI 2 "register_operand" "r")))] 1359 "TARGET_H8300" 1360 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0" 1361 [(set_attr "length" "6")]) 1362 1363(define_insn "*subsi3_h8300hs" 1364 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ") 1365 (minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0") 1366 (match_operand:SI 2 "h8300_src_operand" "rQ,i")))] 1367 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" 1368 "@ 1369 sub.l %S2,%S0 1370 sub.l %S2,%S0" 1371 [(set_attr "length_table" "addl") 1372 (set_attr "cc" "set_zn")]) 1373 1374;; ---------------------------------------------------------------------- 1375;; MULTIPLY INSTRUCTIONS 1376;; ---------------------------------------------------------------------- 1377 1378;; Note that the H8/300 can only handle umulqihi3. 1379 1380(define_expand "mulqihi3" 1381 [(set (match_operand:HI 0 "register_operand" "") 1382 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "")) 1383 ;; intentionally-mismatched modes 1384 (match_operand:QI 2 "reg_or_nibble_operand" "")))] 1385 "TARGET_H8300H || TARGET_H8300S" 1386 { 1387 if (GET_MODE (operands[2]) != VOIDmode) 1388 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); 1389 }) 1390 1391(define_insn "*mulqihi3_const" 1392 [(set (match_operand:HI 0 "register_operand" "=r") 1393 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0")) 1394 (match_operand:QI 2 "nibble_operand" "IP4>X")))] 1395 "TARGET_H8300SX" 1396 "mulxs.b %X2,%T0" 1397 [(set_attr "length" "4") 1398 (set_attr "cc" "set_zn")]) 1399 1400(define_insn "*mulqihi3" 1401 [(set (match_operand:HI 0 "register_operand" "=r") 1402 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0")) 1403 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))] 1404 "TARGET_H8300H || TARGET_H8300S" 1405 "mulxs.b %X2,%T0" 1406 [(set_attr "length" "4") 1407 (set_attr "cc" "set_zn")]) 1408 1409(define_expand "mulhisi3" 1410 [(set (match_operand:SI 0 "register_operand" "") 1411 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "")) 1412 ;; intentionally-mismatched modes 1413 (match_operand:HI 2 "reg_or_nibble_operand" "")))] 1414 "TARGET_H8300H || TARGET_H8300S" 1415 { 1416 if (GET_MODE (operands[2]) != VOIDmode) 1417 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); 1418 }) 1419 1420(define_insn "*mulhisi3_const" 1421 [(set (match_operand:SI 0 "register_operand" "=r") 1422 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0")) 1423 (match_operand:SI 2 "nibble_operand" "IP4>X")))] 1424 "TARGET_H8300SX" 1425 "mulxs.w %T2,%S0" 1426 [(set_attr "length" "4") 1427 (set_attr "cc" "set_zn")]) 1428 1429(define_insn "*mulhisi3" 1430 [(set (match_operand:SI 0 "register_operand" "=r") 1431 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0")) 1432 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))] 1433 "TARGET_H8300H || TARGET_H8300S" 1434 "mulxs.w %T2,%S0" 1435 [(set_attr "length" "4") 1436 (set_attr "cc" "set_zn")]) 1437 1438(define_expand "umulqihi3" 1439 [(set (match_operand:HI 0 "register_operand" "") 1440 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "")) 1441 ;; intentionally-mismatched modes 1442 (match_operand:QI 2 "reg_or_nibble_operand" "")))] 1443 "TARGET_H8300H || TARGET_H8300S" 1444 { 1445 if (GET_MODE (operands[2]) != VOIDmode) 1446 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); 1447 }) 1448 1449(define_insn "*umulqihi3_const" 1450 [(set (match_operand:HI 0 "register_operand" "=r") 1451 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0")) 1452 (match_operand:QI 2 "nibble_operand" "IP4>X")))] 1453 "TARGET_H8300SX" 1454 "mulxu.b %X2,%T0" 1455 [(set_attr "length" "4") 1456 (set_attr "cc" "set_zn")]) 1457 1458(define_insn "*umulqihi3" 1459 [(set (match_operand:HI 0 "register_operand" "=r") 1460 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0")) 1461 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))] 1462 "" 1463 "mulxu.b %X2,%T0" 1464 [(set_attr "length" "2") 1465 (set_attr "cc" "none_0hit")]) 1466 1467(define_expand "umulhisi3" 1468 [(set (match_operand:SI 0 "register_operand" "") 1469 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "")) 1470 ;; intentionally-mismatched modes 1471 (match_operand:HI 2 "reg_or_nibble_operand" "")))] 1472 "TARGET_H8300H || TARGET_H8300S" 1473 { 1474 if (GET_MODE (operands[2]) != VOIDmode) 1475 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); 1476 }) 1477 1478(define_insn "*umulhisi3_const" 1479 [(set (match_operand:SI 0 "register_operand" "=r") 1480 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0")) 1481 (match_operand:SI 2 "nibble_operand" "IP4>X")))] 1482 "TARGET_H8300SX" 1483 "mulxu.w %T2,%S0" 1484 [(set_attr "length" "4") 1485 (set_attr "cc" "set_zn")]) 1486 1487(define_insn "*umulhisi3" 1488 [(set (match_operand:SI 0 "register_operand" "=r") 1489 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0")) 1490 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))] 1491 "TARGET_H8300H || TARGET_H8300S" 1492 "mulxu.w %T2,%S0" 1493 [(set_attr "length" "2") 1494 (set_attr "cc" "none_0hit")]) 1495 1496;; We could have used mulu.[wl] here, but mulu.[lw] is only available 1497;; on a H8SX with a multiplier, whereas muls.w seems to be available 1498;; on all H8SX variants. 1499 1500(define_insn "mulhi3" 1501 [(set (match_operand:HI 0 "register_operand" "=r") 1502 (mult:HI (match_operand:HI 1 "register_operand" "%0") 1503 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))] 1504 "TARGET_H8300SX" 1505 "muls.w\\t%T2,%T0" 1506 [(set_attr "length" "2") 1507 (set_attr "cc" "set_zn")]) 1508 1509(define_insn "mulsi3" 1510 [(set (match_operand:SI 0 "register_operand" "=r") 1511 (mult:SI (match_operand:SI 1 "register_operand" "%0") 1512 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))] 1513 "TARGET_H8300SX" 1514 "muls.l\\t%S2,%S0" 1515 [(set_attr "length" "2") 1516 (set_attr "cc" "set_zn")]) 1517 1518(define_insn "smulsi3_highpart" 1519 [(set (match_operand:SI 0 "register_operand" "=r") 1520 (truncate:SI 1521 (lshiftrt:DI 1522 (mult:DI 1523 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) 1524 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X"))) 1525 (const_int 32))))] 1526 "TARGET_H8300SXMUL" 1527 "muls/u.l\\t%S2,%S0" 1528 [(set_attr "length" "2") 1529 (set_attr "cc" "set_zn")]) 1530 1531(define_insn "umulsi3_highpart" 1532 [(set (match_operand:SI 0 "register_operand" "=r") 1533 (truncate:SI 1534 (ashiftrt:DI 1535 (mult:DI 1536 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) 1537 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X"))) 1538 (const_int 32))))] 1539 "TARGET_H8300SX" 1540 "mulu/u.l\\t%S2,%S0" 1541 [(set_attr "length" "2") 1542 (set_attr "cc" "none_0hit")]) 1543 1544;; This is a "bridge" instruction. Combine can't cram enough insns 1545;; together to crate a MAC instruction directly, but it can create 1546;; this instruction, which then allows combine to create the real 1547;; MAC insn. 1548;; 1549;; Unfortunately, if combine doesn't create a MAC instruction, this 1550;; insn must generate reasonably correct code. Egad. 1551 1552(define_insn "" 1553 [(set (match_operand:SI 0 "register_operand" "=a") 1554 (mult:SI 1555 (sign_extend:SI 1556 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r")))) 1557 (sign_extend:SI 1558 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))] 1559 "TARGET_MAC" 1560 "clrmac\;mac @%2+,@%1+" 1561 [(set_attr "length" "6") 1562 (set_attr "cc" "none_0hit")]) 1563 1564(define_insn "" 1565 [(set (match_operand:SI 0 "register_operand" "=a") 1566 (plus:SI (mult:SI 1567 (sign_extend:SI (mem:HI 1568 (post_inc:SI (match_operand:SI 1 "register_operand" "r")))) 1569 (sign_extend:SI (mem:HI 1570 (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))) 1571 (match_operand:SI 3 "register_operand" "0")))] 1572 "TARGET_MAC" 1573 "mac @%2+,@%1+" 1574 [(set_attr "length" "4") 1575 (set_attr "cc" "none_0hit")]) 1576 1577;; ---------------------------------------------------------------------- 1578;; DIVIDE/MOD INSTRUCTIONS 1579;; ---------------------------------------------------------------------- 1580 1581(define_insn "udivhi3" 1582 [(set (match_operand:HI 0 "register_operand" "=r") 1583 (udiv:HI (match_operand:HI 1 "register_operand" "0") 1584 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))] 1585 "TARGET_H8300SX" 1586 "divu.w\\t%T2,%T0" 1587 [(set_attr "length" "2")]) 1588 1589(define_insn "divhi3" 1590 [(set (match_operand:HI 0 "register_operand" "=r") 1591 (div:HI (match_operand:HI 1 "register_operand" "0") 1592 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))] 1593 "TARGET_H8300SX" 1594 "divs.w\\t%T2,%T0" 1595 [(set_attr "length" "2")]) 1596 1597(define_insn "udivsi3" 1598 [(set (match_operand:SI 0 "register_operand" "=r") 1599 (udiv:SI (match_operand:SI 1 "register_operand" "0") 1600 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))] 1601 "TARGET_H8300SX" 1602 "divu.l\\t%S2,%S0" 1603 [(set_attr "length" "2")]) 1604 1605(define_insn "divsi3" 1606 [(set (match_operand:SI 0 "register_operand" "=r") 1607 (div:SI (match_operand:SI 1 "register_operand" "0") 1608 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))] 1609 "TARGET_H8300SX" 1610 "divs.l\\t%S2,%S0" 1611 [(set_attr "length" "2")]) 1612 1613(define_insn "udivmodqi4" 1614 [(set (match_operand:QI 0 "register_operand" "=r") 1615 (truncate:QI 1616 (udiv:HI 1617 (match_operand:HI 1 "register_operand" "0") 1618 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))) 1619 (set (match_operand:QI 3 "register_operand" "=r") 1620 (truncate:QI 1621 (umod:HI 1622 (match_dup 1) 1623 (zero_extend:HI (match_dup 2)))))] 1624 "" 1625{ 1626 if (find_reg_note (insn, REG_UNUSED, operands[3])) 1627 return "divxu.b\\t%X2,%T0"; 1628 else 1629 return "divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3"; 1630} 1631 [(set_attr "length" "4")]) 1632 1633(define_insn "divmodqi4" 1634 [(set (match_operand:QI 0 "register_operand" "=r") 1635 (truncate:QI 1636 (div:HI 1637 (match_operand:HI 1 "register_operand" "0") 1638 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))) 1639 (set (match_operand:QI 3 "register_operand" "=r") 1640 (truncate:QI 1641 (mod:HI 1642 (match_dup 1) 1643 (sign_extend:HI (match_dup 2)))))] 1644 "TARGET_H8300H || TARGET_H8300S" 1645{ 1646 if (find_reg_note (insn, REG_UNUSED, operands[3])) 1647 return "divxs.b\\t%X2,%T0"; 1648 else 1649 return "divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3"; 1650} 1651 [(set_attr "length" "6")]) 1652 1653(define_insn "udivmodhi4" 1654 [(set (match_operand:HI 0 "register_operand" "=r") 1655 (truncate:HI 1656 (udiv:SI 1657 (match_operand:SI 1 "register_operand" "0") 1658 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))) 1659 (set (match_operand:HI 3 "register_operand" "=r") 1660 (truncate:HI 1661 (umod:SI 1662 (match_dup 1) 1663 (zero_extend:SI (match_dup 2)))))] 1664 "TARGET_H8300H || TARGET_H8300S" 1665{ 1666 if (find_reg_note (insn, REG_UNUSED, operands[3])) 1667 return "divxu.w\\t%T2,%S0"; 1668 else 1669 return "divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3"; 1670} 1671 [(set_attr "length" "4")]) 1672 1673(define_insn "divmodhi4" 1674 [(set (match_operand:HI 0 "register_operand" "=r") 1675 (truncate:HI 1676 (div:SI 1677 (match_operand:SI 1 "register_operand" "0") 1678 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))) 1679 (set (match_operand:HI 3 "register_operand" "=r") 1680 (truncate:HI 1681 (mod:SI 1682 (match_dup 1) 1683 (sign_extend:SI (match_dup 2)))))] 1684 "TARGET_H8300H || TARGET_H8300S" 1685{ 1686 if (find_reg_note (insn, REG_UNUSED, operands[3])) 1687 return "divxs.w\\t%T2,%S0"; 1688 else 1689 return "divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3"; 1690} 1691 [(set_attr "length" "6")]) 1692 1693;; ---------------------------------------------------------------------- 1694;; AND INSTRUCTIONS 1695;; ---------------------------------------------------------------------- 1696 1697(define_insn "bclrqi_msx" 1698 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU") 1699 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0") 1700 (match_operand:QI 2 "single_zero_operand" "Y0")))] 1701 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])" 1702 "bclr\\t%W2,%0" 1703 [(set_attr "length" "8")]) 1704 1705(define_split 1706 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U") 1707 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") 1708 (match_operand:HI 2 "single_zero_operand" "Y0")))] 1709 "TARGET_H8300SX" 1710 [(set (match_dup 0) 1711 (and:QI (match_dup 1) 1712 (match_dup 2)))] 1713 { 1714 if (abs (INTVAL (operands[2])) > 0xFF) 1715 { 1716 operands[0] = adjust_address (operands[0], QImode, 0); 1717 operands[1] = adjust_address (operands[1], QImode, 0); 1718 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); 1719 } 1720 else 1721 { 1722 operands[0] = adjust_address (operands[0], QImode, 1); 1723 operands[1] = adjust_address (operands[1], QImode, 1); 1724 } 1725 }) 1726 1727(define_insn "bclrhi_msx" 1728 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m") 1729 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") 1730 (match_operand:HI 2 "single_zero_operand" "Y0")))] 1731 "TARGET_H8300SX" 1732 "bclr\\t%W2,%0" 1733 [(set_attr "length" "8")]) 1734 1735(define_insn "*andqi3_2" 1736 [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r") 1737 (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU") 1738 (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))] 1739 "TARGET_H8300SX" 1740 "@ 1741 bclr\\t %W2,%R0 1742 and %X2,%X0 1743 bfld %2,%1,%R0" 1744 [(set_attr "length" "8,*,8") 1745 (set_attr "length_table" "*,logicb,*") 1746 (set_attr "cc" "none_0hit,set_znv,none_0hit")]) 1747 1748(define_insn "andqi3_1" 1749 [(set (match_operand:QI 0 "bit_operand" "=U,r") 1750 (and:QI (match_operand:QI 1 "bit_operand" "%0,0") 1751 (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))] 1752 "register_operand (operands[0], QImode) 1753 || single_zero_operand (operands[2], QImode)" 1754 "@ 1755 bclr %W2,%R0 1756 and %X2,%X0" 1757 [(set_attr "length" "2,8") 1758 (set_attr "cc" "none_0hit,set_znv")]) 1759 1760(define_expand "andqi3" 1761 [(set (match_operand:QI 0 "register_operand" "") 1762 (and:QI (match_operand:QI 1 "register_operand" "") 1763 (match_operand:QI 2 "h8300_src_operand" "")))] 1764 "" 1765 "") 1766 1767(define_expand "andhi3" 1768 [(set (match_operand:HI 0 "register_operand" "") 1769 (and:HI (match_operand:HI 1 "register_operand" "") 1770 (match_operand:HI 2 "h8300_src_operand" "")))] 1771 "" 1772 "") 1773 1774(define_insn "*andorqi3" 1775 [(set (match_operand:QI 0 "register_operand" "=r") 1776 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r") 1777 (match_operand:QI 3 "single_one_operand" "n")) 1778 (match_operand:QI 1 "register_operand" "0")))] 1779 "" 1780 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0" 1781 [(set_attr "length" "6")]) 1782 1783(define_insn "*andorhi3" 1784 [(set (match_operand:HI 0 "register_operand" "=r") 1785 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r") 1786 (match_operand:HI 3 "single_one_operand" "n")) 1787 (match_operand:HI 1 "register_operand" "0")))] 1788 "" 1789{ 1790 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff); 1791 if (INTVAL (operands[3]) > 128) 1792 { 1793 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8); 1794 return "bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0"; 1795 } 1796 return "bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0"; 1797} 1798 [(set_attr "length" "6")]) 1799 1800(define_insn "*andorsi3" 1801 [(set (match_operand:SI 0 "register_operand" "=r") 1802 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r") 1803 (match_operand:SI 3 "single_one_operand" "n")) 1804 (match_operand:SI 1 "register_operand" "0")))] 1805 "(INTVAL (operands[3]) & 0xffff) != 0" 1806{ 1807 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff); 1808 if (INTVAL (operands[3]) > 128) 1809 { 1810 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8); 1811 return "bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0"; 1812 } 1813 return "bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0"; 1814} 1815 [(set_attr "length" "6")]) 1816 1817(define_insn "*andorsi3_shift_8" 1818 [(set (match_operand:SI 0 "register_operand" "=r") 1819 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") 1820 (const_int 8)) 1821 (const_int 65280)) 1822 (match_operand:SI 1 "register_operand" "0")))] 1823 "" 1824 "or.b\\t%w2,%x0" 1825 [(set_attr "length" "2")]) 1826 1827(define_expand "andsi3" 1828 [(set (match_operand:SI 0 "register_operand" "") 1829 (and:SI (match_operand:SI 1 "register_operand" "") 1830 (match_operand:SI 2 "h8300_src_operand" "")))] 1831 "" 1832 "") 1833 1834;; ---------------------------------------------------------------------- 1835;; OR INSTRUCTIONS 1836;; ---------------------------------------------------------------------- 1837 1838(define_insn "bsetqi_msx" 1839 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU") 1840 (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0") 1841 (match_operand:QI 2 "single_one_operand" "Y2")))] 1842 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])" 1843 "bset\\t%V2,%0" 1844 [(set_attr "length" "8")]) 1845 1846(define_split 1847 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U") 1848 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") 1849 (match_operand:HI 2 "single_one_operand" "Y2")))] 1850 "TARGET_H8300SX" 1851 [(set (match_dup 0) 1852 (ior:QI (match_dup 1) 1853 (match_dup 2)))] 1854 { 1855 if (abs (INTVAL (operands[2])) > 0xFF) 1856 { 1857 operands[0] = adjust_address (operands[0], QImode, 0); 1858 operands[1] = adjust_address (operands[1], QImode, 0); 1859 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); 1860 } 1861 else 1862 { 1863 operands[0] = adjust_address (operands[0], QImode, 1); 1864 operands[1] = adjust_address (operands[1], QImode, 1); 1865 } 1866 }) 1867 1868(define_insn "bsethi_msx" 1869 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m") 1870 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") 1871 (match_operand:HI 2 "single_one_operand" "Y2")))] 1872 "TARGET_H8300SX" 1873 "bset\\t%V2,%0" 1874 [(set_attr "length" "8")]) 1875 1876(define_insn "iorqi3_1" 1877 [(set (match_operand:QI 0 "bit_operand" "=U,rQ") 1878 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0") 1879 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))] 1880 "TARGET_H8300SX || register_operand (operands[0], QImode) 1881 || single_one_operand (operands[2], QImode)" 1882 "@ 1883 bset\\t%V2,%R0 1884 or\\t%X2,%X0" 1885 [(set_attr "length" "8,*") 1886 (set_attr "length_table" "*,logicb") 1887 (set_attr "cc" "none_0hit,set_znv")]) 1888 1889 1890(define_expand "iorqi3" 1891 [(set (match_operand:QI 0 "register_operand" "") 1892 (ior:QI (match_operand:QI 1 "register_operand" "") 1893 (match_operand:QI 2 "h8300_src_operand" "")))] 1894 "" 1895 "") 1896 1897(define_expand "iorhi3" 1898 [(set (match_operand:HI 0 "register_operand" "") 1899 (ior:HI (match_operand:HI 1 "register_operand" "") 1900 (match_operand:HI 2 "h8300_src_operand" "")))] 1901 "" 1902 "") 1903 1904(define_expand "iorsi3" 1905 [(set (match_operand:SI 0 "register_operand" "") 1906 (ior:SI (match_operand:SI 1 "register_operand" "") 1907 (match_operand:SI 2 "h8300_src_operand" "")))] 1908 "" 1909 "") 1910 1911;; ---------------------------------------------------------------------- 1912;; XOR INSTRUCTIONS 1913;; ---------------------------------------------------------------------- 1914 1915(define_insn "bnotqi_msx" 1916 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU") 1917 (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0") 1918 (match_operand:QI 2 "single_one_operand" "Y2")))] 1919 "TARGET_H8300SX 1920 && rtx_equal_p (operands[0], operands[1])" 1921 "bnot\\t%V2,%0" 1922 [(set_attr "length" "8")]) 1923 1924(define_split 1925 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U") 1926 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") 1927 (match_operand:HI 2 "single_one_operand" "Y2")))] 1928 "TARGET_H8300SX" 1929 [(set (match_dup 0) 1930 (xor:QI (match_dup 1) 1931 (match_dup 2)))] 1932 { 1933 if (abs (INTVAL (operands[2])) > 0xFF) 1934 { 1935 operands[0] = adjust_address (operands[0], QImode, 0); 1936 operands[1] = adjust_address (operands[1], QImode, 0); 1937 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); 1938 } 1939 else 1940 { 1941 operands[0] = adjust_address (operands[0], QImode, 1); 1942 operands[1] = adjust_address (operands[1], QImode, 1); 1943 } 1944 }) 1945 1946(define_insn "bnothi_msx" 1947 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m") 1948 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") 1949 (match_operand:HI 2 "single_one_operand" "Y2")))] 1950 "TARGET_H8300SX" 1951 "bnot\\t%V2,%0" 1952 [(set_attr "length" "8")]) 1953 1954(define_insn "xorqi3_1" 1955 [(set (match_operand:QI 0 "bit_operand" "=U,r") 1956 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0") 1957 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))] 1958 "TARGET_H8300SX || register_operand (operands[0], QImode) 1959 || single_one_operand (operands[2], QImode)" 1960 "@ 1961 bnot\\t%V2,%R0 1962 xor\\t%X2,%X0" 1963 [(set_attr "length" "8,*") 1964 (set_attr "length_table" "*,logicb") 1965 (set_attr "cc" "none_0hit,set_znv")]) 1966 1967(define_expand "xorqi3" 1968 [(set (match_operand:QI 0 "register_operand" "") 1969 (xor:QI (match_operand:QI 1 "register_operand" "") 1970 (match_operand:QI 2 "h8300_src_operand" "")))] 1971 "" 1972 "") 1973 1974(define_expand "xorhi3" 1975 [(set (match_operand:HI 0 "register_operand" "") 1976 (xor:HI (match_operand:HI 1 "register_operand" "") 1977 (match_operand:HI 2 "h8300_src_operand" "")))] 1978 "" 1979 "") 1980 1981(define_expand "xorsi3" 1982 [(set (match_operand:SI 0 "register_operand" "") 1983 (xor:SI (match_operand:SI 1 "register_operand" "") 1984 (match_operand:SI 2 "h8300_src_operand" "")))] 1985 "" 1986 "") 1987 1988;; ---------------------------------------------------------------------- 1989;; {AND,IOR,XOR}{HI3,SI3} PATTERNS 1990;; ---------------------------------------------------------------------- 1991 1992;; We need a separate pattern here because machines other than the 1993;; original H8300 don't have to split the 16-bit operand into a pair 1994;; of high/low instructions, so we can accept literal addresses, that 1995;; have to be loaded into a register on H8300. 1996 1997(define_insn "*logicalhi3_sn" 1998 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") 1999 (match_operator:HI 3 "bit_operator" 2000 [(match_operand:HI 1 "h8300_dst_operand" "%0") 2001 (match_operand:HI 2 "h8300_src_operand" "rQi")]))] 2002 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)" 2003{ 2004 return output_logical_op (HImode, operands); 2005} 2006 [(set (attr "length") 2007 (symbol_ref "compute_logical_op_length (HImode, operands)")) 2008 (set (attr "cc") 2009 (symbol_ref "compute_logical_op_cc (HImode, operands)"))]) 2010 2011(define_insn "*logicalsi3_sn" 2012 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") 2013 (match_operator:SI 3 "bit_operator" 2014 [(match_operand:SI 1 "h8300_dst_operand" "%0") 2015 (match_operand:SI 2 "h8300_src_operand" "rQi")]))] 2016 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)" 2017{ 2018 return output_logical_op (SImode, operands); 2019} 2020 [(set (attr "length") 2021 (symbol_ref "compute_logical_op_length (SImode, operands)")) 2022 (set (attr "cc") 2023 (symbol_ref "compute_logical_op_cc (SImode, operands)"))]) 2024 2025(define_insn "*logicalhi3" 2026 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") 2027 (match_operator:HI 3 "bit_operator" 2028 [(match_operand:HI 1 "h8300_dst_operand" "%0") 2029 (match_operand:HI 2 "h8300_src_operand" "rQi")]))] 2030 "h8300_operands_match_p (operands)" 2031{ 2032 return output_logical_op (HImode, operands); 2033} 2034 [(set (attr "length") 2035 (symbol_ref "compute_logical_op_length (HImode, operands)")) 2036 (set (attr "cc") 2037 (symbol_ref "compute_logical_op_cc (HImode, operands)"))]) 2038 2039(define_insn "*logicalsi3" 2040 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") 2041 (match_operator:SI 3 "bit_operator" 2042 [(match_operand:SI 1 "h8300_dst_operand" "%0") 2043 (match_operand:SI 2 "h8300_src_operand" "rQi")]))] 2044 "h8300_operands_match_p (operands)" 2045{ 2046 return output_logical_op (SImode, operands); 2047} 2048 [(set (attr "length") 2049 (symbol_ref "compute_logical_op_length (SImode, operands)")) 2050 (set (attr "cc") 2051 (symbol_ref "compute_logical_op_cc (SImode, operands)"))]) 2052 2053;; ---------------------------------------------------------------------- 2054;; NEGATION INSTRUCTIONS 2055;; ---------------------------------------------------------------------- 2056 2057(define_expand "negqi2" 2058 [(set (match_operand:QI 0 "register_operand" "") 2059 (neg:QI (match_operand:QI 1 "register_operand" "")))] 2060 "" 2061 "") 2062 2063(define_insn "*negqi2" 2064 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ") 2065 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))] 2066 "" 2067 "neg %X0" 2068 [(set_attr "length_table" "unary") 2069 (set_attr "cc" "set_zn")]) 2070 2071(define_expand "neghi2" 2072 [(set (match_operand:HI 0 "register_operand" "") 2073 (neg:HI (match_operand:HI 1 "register_operand" "")))] 2074 "" 2075 { 2076 if (TARGET_H8300) 2077 { 2078 emit_insn (gen_neghi2_h8300 (operands[0], operands[1])); 2079 DONE; 2080 } 2081 }) 2082 2083(define_expand "neghi2_h8300" 2084 [(set (match_dup 2) 2085 (not:HI (match_operand:HI 1 "register_operand" ""))) 2086 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1))) 2087 (set (match_operand:HI 0 "register_operand" "") 2088 (match_dup 2))] 2089 "" 2090 { 2091 operands[2] = gen_reg_rtx (HImode); 2092 }) 2093 2094(define_insn "*neghi2_h8300hs" 2095 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") 2096 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))] 2097 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" 2098 "neg.w %T0" 2099 [(set_attr "length_table" "unary") 2100 (set_attr "cc" "set_zn")]) 2101 2102(define_expand "negsi2" 2103 [(set (match_operand:SI 0 "register_operand" "") 2104 (neg:SI (match_operand:SI 1 "register_operand" "")))] 2105 "" 2106 { 2107 if (TARGET_H8300) 2108 { 2109 emit_insn (gen_negsi2_h8300 (operands[0], operands[1])); 2110 DONE; 2111 } 2112 }) 2113 2114(define_expand "negsi2_h8300" 2115 [(set (match_dup 2) 2116 (not:SI (match_operand:SI 1 "register_operand" ""))) 2117 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1))) 2118 (set (match_operand:SI 0 "register_operand" "") 2119 (match_dup 2))] 2120 "" 2121 { 2122 operands[2] = gen_reg_rtx (SImode); 2123 }) 2124 2125(define_insn "*negsi2_h8300hs" 2126 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") 2127 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))] 2128 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" 2129 "neg.l %S0" 2130 [(set_attr "length_table" "unary") 2131 (set_attr "cc" "set_zn")]) 2132 2133(define_expand "negsf2" 2134 [(set (match_operand:SF 0 "register_operand" "") 2135 (neg:SF (match_operand:SF 1 "register_operand" "")))] 2136 "" 2137 "") 2138 2139(define_insn "*negsf2_h8300" 2140 [(set (match_operand:SF 0 "register_operand" "=r") 2141 (neg:SF (match_operand:SF 1 "register_operand" "0")))] 2142 "TARGET_H8300" 2143 "xor.b\\t#128,%z0" 2144 [(set_attr "length" "2")]) 2145 2146(define_insn "*negsf2_h8300hs" 2147 [(set (match_operand:SF 0 "register_operand" "=r") 2148 (neg:SF (match_operand:SF 1 "register_operand" "0")))] 2149 "TARGET_H8300H || TARGET_H8300S" 2150 "xor.w\\t#32768,%e0" 2151 [(set_attr "length" "4")]) 2152 2153;; ---------------------------------------------------------------------- 2154;; ABSOLUTE VALUE INSTRUCTIONS 2155;; ---------------------------------------------------------------------- 2156 2157(define_expand "abssf2" 2158 [(set (match_operand:SF 0 "register_operand" "") 2159 (abs:SF (match_operand:SF 1 "register_operand" "")))] 2160 "" 2161 "") 2162 2163(define_insn "*abssf2_h8300" 2164 [(set (match_operand:SF 0 "register_operand" "=r") 2165 (abs:SF (match_operand:SF 1 "register_operand" "0")))] 2166 "TARGET_H8300" 2167 "and.b\\t#127,%z0" 2168 [(set_attr "length" "2")]) 2169 2170(define_insn "*abssf2_h8300hs" 2171 [(set (match_operand:SF 0 "register_operand" "=r") 2172 (abs:SF (match_operand:SF 1 "register_operand" "0")))] 2173 "TARGET_H8300H || TARGET_H8300S" 2174 "and.w\\t#32767,%e0" 2175 [(set_attr "length" "4")]) 2176 2177;; ---------------------------------------------------------------------- 2178;; NOT INSTRUCTIONS 2179;; ---------------------------------------------------------------------- 2180 2181(define_expand "one_cmplqi2" 2182 [(set (match_operand:QI 0 "register_operand" "") 2183 (not:QI (match_operand:QI 1 "register_operand" "")))] 2184 "" 2185 "") 2186 2187(define_insn "*one_cmplqi2" 2188 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ") 2189 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))] 2190 "" 2191 "not %X0" 2192 [(set_attr "length_table" "unary") 2193 (set_attr "cc" "set_znv")]) 2194 2195(define_expand "one_cmplhi2" 2196 [(set (match_operand:HI 0 "register_operand" "") 2197 (not:HI (match_operand:HI 1 "register_operand" "")))] 2198 "" 2199 "") 2200 2201(define_insn "*one_cmplhi2_h8300" 2202 [(set (match_operand:HI 0 "register_operand" "=r") 2203 (not:HI (match_operand:HI 1 "register_operand" "0")))] 2204 "TARGET_H8300" 2205 "not %s0\;not %t0" 2206 [(set_attr "length" "4")]) 2207 2208(define_insn "*one_cmplhi2_h8300hs" 2209 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") 2210 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))] 2211 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" 2212 "not.w %T0" 2213 [(set_attr "cc" "set_znv") 2214 (set_attr "length_table" "unary")]) 2215 2216(define_expand "one_cmplsi2" 2217 [(set (match_operand:SI 0 "register_operand" "") 2218 (not:SI (match_operand:SI 1 "register_operand" "")))] 2219 "" 2220 "") 2221 2222(define_insn "*one_cmplsi2_h8300" 2223 [(set (match_operand:SI 0 "register_operand" "=r") 2224 (not:SI (match_operand:SI 1 "register_operand" "0")))] 2225 "TARGET_H8300" 2226 "not %w0\;not %x0\;not %y0\;not %z0" 2227 [(set_attr "length" "8")]) 2228 2229(define_insn "*one_cmplsi2_h8300hs" 2230 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") 2231 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))] 2232 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" 2233 "not.l %S0" 2234 [(set_attr "cc" "set_znv") 2235 (set_attr "length_table" "unary")]) 2236 2237;; ---------------------------------------------------------------------- 2238;; JUMP INSTRUCTIONS 2239;; ---------------------------------------------------------------------- 2240 2241;; Conditional jump instructions 2242 2243(define_expand "cbranchqi4" 2244 [(use (match_operator 0 "ordered_comparison_operator" 2245 [(match_operand:QI 1 "h8300_dst_operand" "") 2246 (match_operand:QI 2 "h8300_src_operand" "")])) 2247 (use (match_operand 3 ""))] 2248 "" 2249 { 2250 h8300_expand_branch (operands); 2251 DONE; 2252 }) 2253 2254(define_expand "cbranchhi4" 2255 [(use (match_operator 0 "ordered_comparison_operator" 2256 [(match_operand:HI 1 "h8300_dst_operand" "") 2257 (match_operand:HI 2 "h8300_src_operand" "")])) 2258 (use (match_operand 3 ""))] 2259 "" 2260 { 2261 /* Force operand1 into a register if we're compiling 2262 for the H8/300. */ 2263 if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx) 2264 && TARGET_H8300) 2265 operands[2] = force_reg (HImode, operands[2]); 2266 h8300_expand_branch (operands); 2267 DONE; 2268 }) 2269 2270(define_expand "cbranchsi4" 2271 [(use (match_operator 0 "ordered_comparison_operator" 2272 [(match_operand:SI 1 "h8300_dst_operand" "") 2273 (match_operand:SI 2 "h8300_src_operand" "")])) 2274 (use (match_operand 3 ""))] 2275 "TARGET_H8300H || TARGET_H8300S" 2276 { 2277 h8300_expand_branch (operands); 2278 DONE; 2279 }) 2280 2281(define_insn "branch_true" 2282 [(set (pc) 2283 (if_then_else (match_operator 1 "comparison_operator" 2284 [(cc0) (const_int 0)]) 2285 (label_ref (match_operand 0 "" "")) 2286 (pc)))] 2287 "" 2288{ 2289 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 2290 && (GET_CODE (operands[1]) == GT 2291 || GET_CODE (operands[1]) == GE 2292 || GET_CODE (operands[1]) == LE 2293 || GET_CODE (operands[1]) == LT)) 2294 { 2295 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 2296 return 0; 2297 } 2298 2299 if (get_attr_length (insn) == 2) 2300 return "b%j1 %l0"; 2301 else if (get_attr_length (insn) == 4) 2302 return "b%j1 %l0:16"; 2303 else 2304 return "b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:"; 2305} 2306 [(set_attr "type" "branch") 2307 (set_attr "cc" "none")]) 2308 2309(define_insn "branch_false" 2310 [(set (pc) 2311 (if_then_else (match_operator 1 "comparison_operator" 2312 [(cc0) (const_int 0)]) 2313 (pc) 2314 (label_ref (match_operand 0 "" ""))))] 2315 "" 2316{ 2317 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 2318 && (GET_CODE (operands[1]) == GT 2319 || GET_CODE (operands[1]) == GE 2320 || GET_CODE (operands[1]) == LE 2321 || GET_CODE (operands[1]) == LT)) 2322 { 2323 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 2324 return 0; 2325 } 2326 2327 if (get_attr_length (insn) == 2) 2328 return "b%k1 %l0"; 2329 else if (get_attr_length (insn) == 4) 2330 return "b%k1 %l0:16"; 2331 else 2332 return "b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:"; 2333} 2334 [(set_attr "type" "branch") 2335 (set_attr "cc" "none")]) 2336 2337(define_insn "*brabc" 2338 [(set (pc) 2339 (if_then_else (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU") 2340 (const_int 1) 2341 (match_operand:QI 2 "immediate_operand" "n")) 2342 (const_int 0)) 2343 (label_ref (match_operand 0 "" "")) 2344 (pc)))] 2345 "TARGET_H8300SX" 2346{ 2347 switch (get_attr_length (insn) 2348 - h8300_insn_length_from_table (insn, operands)) 2349 { 2350 case 2: 2351 return "bra/bc %2,%R1,%l0"; 2352 case 4: 2353 return "bra/bc %2,%R1,%l0:16"; 2354 default: 2355 return "bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:"; 2356 } 2357} 2358 [(set_attr "type" "bitbranch") 2359 (set_attr "length_table" "bitbranch") 2360 (set_attr "cc" "none")]) 2361 2362(define_insn "*brabs" 2363 [(set (pc) 2364 (if_then_else (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU") 2365 (const_int 1) 2366 (match_operand:QI 2 "immediate_operand" "n")) 2367 (const_int 0)) 2368 (label_ref (match_operand 0 "" "")) 2369 (pc)))] 2370 "TARGET_H8300SX" 2371{ 2372 switch (get_attr_length (insn) 2373 - h8300_insn_length_from_table (insn, operands)) 2374 { 2375 case 2: 2376 return "bra/bs %2,%R1,%l0"; 2377 case 4: 2378 return "bra/bs %2,%R1,%l0:16"; 2379 default: 2380 return "bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:"; 2381 } 2382} 2383 [(set_attr "type" "bitbranch") 2384 (set_attr "length_table" "bitbranch") 2385 (set_attr "cc" "none")]) 2386 2387;; Unconditional and other jump instructions. 2388 2389(define_insn "jump" 2390 [(set (pc) 2391 (label_ref (match_operand 0 "" "")))] 2392 "" 2393{ 2394 if (final_sequence != 0) 2395 { 2396 if (get_attr_length (insn) == 2) 2397 return "bra/s %l0"; 2398 else 2399 { 2400 /* The branch isn't short enough to use bra/s. Output the 2401 branch and delay slot in their normal order. 2402 2403 If this is a backward branch, it will now be branching two 2404 bytes further than previously thought. The length-based 2405 test for bra vs. jump is very conservative though, so the 2406 branch will still be within range. */ 2407 rtvec vec; 2408 int seen; 2409 2410 vec = XVEC (final_sequence, 0); 2411 final_sequence = 0; 2412 final_scan_insn (RTVEC_ELT (vec, 1), asm_out_file, optimize, 1, & seen); 2413 final_scan_insn (RTVEC_ELT (vec, 0), asm_out_file, optimize, 1, & seen); 2414 INSN_DELETED_P (RTVEC_ELT (vec, 1)) = 1; 2415 return ""; 2416 } 2417 } 2418 else if (get_attr_length (insn) == 2) 2419 return "bra %l0"; 2420 else if (get_attr_length (insn) == 4) 2421 return "bra %l0:16"; 2422 else 2423 return "jmp @%l0"; 2424} 2425 [(set_attr "type" "branch") 2426 (set (attr "delay_slot") 2427 (if_then_else (match_test "TARGET_H8300SX") 2428 (const_string "jump") 2429 (const_string "none"))) 2430 (set_attr "cc" "none")]) 2431 2432;; This is a define expand, because pointers may be either 16 or 32 bits. 2433 2434(define_expand "tablejump" 2435 [(parallel [(set (pc) (match_operand 0 "register_operand" "")) 2436 (use (label_ref (match_operand 1 "" "")))])] 2437 "" 2438 "") 2439 2440(define_insn "*tablejump_h8300" 2441 [(set (pc) (match_operand:HI 0 "register_operand" "r")) 2442 (use (label_ref (match_operand 1 "" "")))] 2443 "TARGET_H8300" 2444 "jmp @%0" 2445 [(set_attr "cc" "none") 2446 (set_attr "length" "2")]) 2447 2448(define_insn "*tablejump_h8300hs_advanced" 2449 [(set (pc) (match_operand:SI 0 "register_operand" "r")) 2450 (use (label_ref (match_operand 1 "" "")))] 2451 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE" 2452 "jmp @%0" 2453 [(set_attr "cc" "none") 2454 (set_attr "length" "2")]) 2455 2456(define_insn "*tablejump_h8300hs_normal" 2457 [(set (pc) (match_operand:HI 0 "register_operand" "r")) 2458 (use (label_ref (match_operand 1 "" "")))] 2459 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE" 2460 "jmp @%S0" 2461 [(set_attr "cc" "none") 2462 (set_attr "length" "2")]) 2463 2464;; This is a define expand, because pointers may be either 16 or 32 bits. 2465 2466(define_expand "indirect_jump" 2467 [(set (pc) (match_operand 0 "jump_address_operand" ""))] 2468 "" 2469 "") 2470 2471(define_insn "*indirect_jump_h8300" 2472 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))] 2473 "TARGET_H8300" 2474 "jmp @%0" 2475 [(set_attr "cc" "none") 2476 (set_attr "length" "2")]) 2477 2478(define_insn "*indirect_jump_h8300hs_advanced" 2479 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))] 2480 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE" 2481 "jmp @%0" 2482 [(set_attr "cc" "none") 2483 (set_attr "length" "2")]) 2484 2485(define_insn "*indirect_jump_h8300hs_normal" 2486 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))] 2487 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE" 2488 "jmp @%S0" 2489 [(set_attr "cc" "none") 2490 (set_attr "length" "2")]) 2491 2492;; Call subroutine with no return value. 2493 2494;; ??? Even though we use HImode here, this works on the H8/300H and H8S. 2495 2496(define_insn "call" 2497 [(call (match_operand:QI 0 "call_insn_operand" "or") 2498 (match_operand:HI 1 "general_operand" "g"))] 2499 "" 2500{ 2501 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF 2502 && SYMBOL_REF_FLAG (XEXP (operands[0], 0))) 2503 return "jsr\\t@%0:8"; 2504 else 2505 return "jsr\\t%0"; 2506} 2507 [(set_attr "type" "call") 2508 (set (attr "length") 2509 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "") 2510 (const_int 2) 2511 (const_int 4)))]) 2512 2513;; Call subroutine, returning value in operand 0 2514;; (which must be a hard register). 2515 2516;; ??? Even though we use HImode here, this works on the H8/300H and H8S. 2517 2518(define_insn "call_value" 2519 [(set (match_operand 0 "" "=r") 2520 (call (match_operand:QI 1 "call_insn_operand" "or") 2521 (match_operand:HI 2 "general_operand" "g")))] 2522 "" 2523{ 2524 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF 2525 && SYMBOL_REF_FLAG (XEXP (operands[1], 0))) 2526 return "jsr\\t@%1:8"; 2527 else 2528 return "jsr\\t%1"; 2529} 2530 [(set_attr "type" "call") 2531 (set (attr "length") 2532 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "") 2533 (const_int 2) 2534 (const_int 4)))]) 2535 2536(define_insn "nop" 2537 [(const_int 0)] 2538 "" 2539 "nop" 2540 [(set_attr "cc" "none") 2541 (set_attr "length" "2")]) 2542 2543;; ---------------------------------------------------------------------- 2544;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS 2545;; ---------------------------------------------------------------------- 2546 2547(define_expand "push_h8300" 2548 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG))) 2549 (match_operand:HI 0 "register_operand" ""))] 2550 "TARGET_H8300" 2551 "") 2552 2553(define_expand "push_h8300hs_advanced" 2554 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 2555 (match_operand:SI 0 "register_operand" ""))] 2556 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE" 2557 "") 2558 2559(define_expand "push_h8300hs_normal" 2560 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 2561 (match_operand:SI 0 "register_operand" ""))] 2562 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE" 2563 "") 2564 2565(define_expand "pop_h8300" 2566 [(set (match_operand:HI 0 "register_operand" "") 2567 (mem:HI (post_inc:HI (reg:HI SP_REG))))] 2568 "TARGET_H8300" 2569 "") 2570 2571(define_expand "pop_h8300hs_advanced" 2572 [(set (match_operand:SI 0 "register_operand" "") 2573 (mem:SI (post_inc:SI (reg:SI SP_REG))))] 2574 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE" 2575 "") 2576 2577(define_expand "pop_h8300hs_normal" 2578 [(set (match_operand:SI 0 "register_operand" "") 2579 (mem:SI (post_inc:HI (reg:HI SP_REG))))] 2580 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE" 2581 "") 2582 2583(define_insn "ldm_h8300sx" 2584 [(match_parallel 0 "h8300_ldm_parallel" 2585 [(set (match_operand:SI 1 "register_operand" "") 2586 (match_operand:SI 2 "memory_operand" ""))])] 2587 "TARGET_H8300S" 2588{ 2589 operands[3] = SET_DEST (XVECEXP (operands[0], 0, 2590 XVECLEN (operands[0], 0) - 2)); 2591 return "ldm.l\t@er7+,%S1-%S3"; 2592} 2593 [(set_attr "cc" "none") 2594 (set_attr "length" "4")]) 2595 2596(define_insn "stm_h8300sx" 2597 [(match_parallel 0 "h8300_stm_parallel" 2598 [(set (match_operand:SI 1 "memory_operand" "") 2599 (match_operand:SI 2 "register_operand" ""))])] 2600 "TARGET_H8300S" 2601{ 2602 operands[3] = SET_SRC (XVECEXP (operands[0], 0, 2603 XVECLEN (operands[0], 0) - 2)); 2604 return "stm.l\t%S2-%S3,@-er7"; 2605} 2606 [(set_attr "cc" "none") 2607 (set_attr "length" "4")]) 2608 2609(define_insn "return_h8sx" 2610 [(match_parallel 0 "h8300_return_parallel" 2611 [(return) 2612 (set (match_operand:SI 1 "register_operand" "") 2613 (match_operand:SI 2 "memory_operand" ""))])] 2614 "TARGET_H8300SX" 2615{ 2616 operands[3] = SET_DEST (XVECEXP (operands[0], 0, 2617 XVECLEN (operands[0], 0) - 2)); 2618 if (h8300_current_function_interrupt_function_p () 2619 || h8300_current_function_monitor_function_p ()) 2620 return "rte/l\t%S1-%S3"; 2621 else 2622 return "rts/l\t%S1-%S3"; 2623} 2624 [(set_attr "cc" "none") 2625 (set_attr "can_delay" "no") 2626 (set_attr "length" "2")]) 2627 2628(define_expand "return" 2629 [(return)] 2630 "h8300_can_use_return_insn_p ()" 2631 "") 2632 2633(define_insn "*return_1" 2634 [(return)] 2635 "reload_completed" 2636{ 2637 if (h8300_current_function_interrupt_function_p () 2638 || h8300_current_function_monitor_function_p ()) 2639 return "rte"; 2640 else 2641 return "rts"; 2642} 2643 [(set_attr "cc" "none") 2644 (set_attr "can_delay" "no") 2645 (set_attr "length" "2")]) 2646 2647(define_expand "prologue" 2648 [(const_int 0)] 2649 "" 2650 { 2651 h8300_expand_prologue (); 2652 DONE; 2653 }) 2654 2655(define_expand "epilogue" 2656 [(return)] 2657 "" 2658 { 2659 h8300_expand_epilogue (); 2660 DONE; 2661 }) 2662 2663(define_insn "monitor_prologue" 2664 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)] 2665 "" 2666{ 2667 if (TARGET_H8300) 2668 return "subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr"; 2669 else if (TARGET_H8300H && TARGET_NORMAL_MODE) 2670 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr"; 2671 else if (TARGET_H8300H) 2672 return "mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr"; 2673 else if (TARGET_H8300S && TARGET_NEXR ) 2674 return "mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr"; 2675 else if (TARGET_H8300S && TARGET_NEXR && TARGET_NORMAL_MODE) 2676 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr"; 2677 else if (TARGET_H8300S && TARGET_NORMAL_MODE) 2678 return "subs\\t#2,er7\;stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr"; 2679 else if (TARGET_H8300S) 2680 return "stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr"; 2681 gcc_unreachable (); 2682} 2683 [(set_attr "length" "20")]) 2684 2685;; ---------------------------------------------------------------------- 2686;; EXTEND INSTRUCTIONS 2687;; ---------------------------------------------------------------------- 2688 2689(define_expand "zero_extendqihi2" 2690 [(set (match_operand:HI 0 "register_operand" "") 2691 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))] 2692 "" 2693 "") 2694 2695(define_insn "*zero_extendqihi2_h8300" 2696 [(set (match_operand:HI 0 "register_operand" "=r,r") 2697 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))] 2698 "TARGET_H8300" 2699 "@ 2700 mov.b #0,%t0 2701 #" 2702 [(set_attr "length" "2,10")]) 2703 2704(define_insn "*zero_extendqihi2_h8300hs" 2705 [(set (match_operand:HI 0 "register_operand" "=r,r") 2706 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))] 2707 "TARGET_H8300H || TARGET_H8300S" 2708 "@ 2709 extu.w %T0 2710 #" 2711 [(set_attr "length" "2,10") 2712 (set_attr "cc" "set_znv,set_znv")]) 2713 2714;; Split the zero extension of a general operand (actually a memory 2715;; operand) into a load of the operand and the actual zero extension 2716;; so that 1) the length will be accurate, and 2) the zero extensions 2717;; appearing at the end of basic blocks may be merged. 2718 2719(define_split 2720 [(set (match_operand:HI 0 "register_operand" "") 2721 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))] 2722 "reload_completed" 2723 [(set (match_dup 2) 2724 (match_dup 1)) 2725 (set (match_dup 0) 2726 (zero_extend:HI (match_dup 2)))] 2727 { 2728 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0])); 2729 }) 2730 2731(define_expand "zero_extendqisi2" 2732 [(set (match_operand:SI 0 "register_operand" "") 2733 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))] 2734 "" 2735 { 2736 if (TARGET_H8300SX) 2737 operands[1] = force_reg (QImode, operands[1]); 2738 }) 2739 2740(define_insn "*zero_extendqisi2_h8300" 2741 [(set (match_operand:SI 0 "register_operand" "=r,r") 2742 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))] 2743 "TARGET_H8300" 2744 "@ 2745 mov.b #0,%x0\;sub.w %e0,%e0 2746 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0" 2747 [(set_attr "length" "4,8")]) 2748 2749(define_insn "*zero_extendqisi2_h8300hs" 2750 [(set (match_operand:SI 0 "register_operand" "=r,r") 2751 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))] 2752 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX" 2753 "#") 2754 2755(define_split 2756 [(set (match_operand:SI 0 "register_operand" "") 2757 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))] 2758 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX 2759 && reg_overlap_mentioned_p (operands[0], operands[1]) 2760 && reload_completed" 2761 [(set (match_dup 2) 2762 (match_dup 1)) 2763 (set (match_dup 3) 2764 (zero_extend:HI (match_dup 2))) 2765 (set (match_dup 0) 2766 (zero_extend:SI (match_dup 3)))] 2767 { 2768 operands[2] = gen_lowpart (QImode, operands[0]); 2769 operands[3] = gen_lowpart (HImode, operands[0]); 2770 }) 2771 2772(define_split 2773 [(set (match_operand:SI 0 "register_operand" "") 2774 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))] 2775 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX 2776 && !reg_overlap_mentioned_p (operands[0], operands[1]) 2777 && reload_completed" 2778 [(set (match_dup 0) 2779 (const_int 0)) 2780 (set (strict_low_part (match_dup 2)) 2781 (match_dup 1))] 2782 { 2783 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0])); 2784 }) 2785 2786(define_insn "*zero_extendqisi2_h8sx" 2787 [(set (match_operand:SI 0 "register_operand" "=r") 2788 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))] 2789 "TARGET_H8300SX" 2790 "extu.l\t#2,%0" 2791 [(set_attr "length" "2") 2792 (set_attr "cc" "set_znv")]) 2793 2794(define_expand "zero_extendhisi2" 2795 [(set (match_operand:SI 0 "register_operand" "") 2796 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] 2797 "" 2798 "") 2799 2800;; %e prints the high part of a CONST_INT, not the low part. Arggh. 2801(define_insn "*zero_extendhisi2_h8300" 2802 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 2803 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))] 2804 "TARGET_H8300" 2805 "@ 2806 sub.w %e0,%e0 2807 mov.w %f1,%f0\;sub.w %e0,%e0 2808 mov.w %e1,%f0\;sub.w %e0,%e0" 2809 [(set_attr "length" "2,4,6")]) 2810 2811(define_insn "*zero_extendhisi2_h8300hs" 2812 [(set (match_operand:SI 0 "register_operand" "=r") 2813 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))] 2814 "TARGET_H8300H || TARGET_H8300S" 2815 "extu.l %S0" 2816 [(set_attr "length" "2") 2817 (set_attr "cc" "set_znv")]) 2818 2819(define_expand "extendqihi2" 2820 [(set (match_operand:HI 0 "register_operand" "") 2821 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))] 2822 "" 2823 "") 2824 2825(define_insn "*extendqihi2_h8300" 2826 [(set (match_operand:HI 0 "register_operand" "=r,r") 2827 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))] 2828 "TARGET_H8300" 2829 "@ 2830 bld #7,%s0\;subx %t0,%t0 2831 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0" 2832 [(set_attr "length" "4,8")]) 2833 2834(define_insn "*extendqihi2_h8300hs" 2835 [(set (match_operand:HI 0 "register_operand" "=r") 2836 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))] 2837 "TARGET_H8300H || TARGET_H8300S" 2838 "exts.w %T0" 2839 [(set_attr "length" "2") 2840 (set_attr "cc" "set_znv")]) 2841 2842(define_expand "extendqisi2" 2843 [(set (match_operand:SI 0 "register_operand" "") 2844 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] 2845 "" 2846 "") 2847 2848(define_insn "*extendqisi2_h8300" 2849 [(set (match_operand:SI 0 "register_operand" "=r,r") 2850 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))] 2851 "TARGET_H8300" 2852 "@ 2853 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0 2854 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0" 2855 [(set_attr "length" "8,12")]) 2856 2857;; The following pattern is needed because without the pattern, the 2858;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit 2859;; shifts, one ashift and one ashiftrt. 2860 2861(define_insn_and_split "*extendqisi2_h8300hs" 2862 [(set (match_operand:SI 0 "register_operand" "=r") 2863 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))] 2864 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX" 2865 "#" 2866 "&& reload_completed" 2867 [(set (match_dup 2) 2868 (sign_extend:HI (match_dup 1))) 2869 (set (match_dup 0) 2870 (sign_extend:SI (match_dup 2)))] 2871 { 2872 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); 2873 }) 2874 2875(define_insn "*extendqisi2_h8sx" 2876 [(set (match_operand:SI 0 "register_operand" "=r") 2877 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))] 2878 "TARGET_H8300SX" 2879 "exts.l\t#2,%0" 2880 [(set_attr "length" "2") 2881 (set_attr "cc" "set_znv")]) 2882 2883(define_expand "extendhisi2" 2884 [(set (match_operand:SI 0 "register_operand" "") 2885 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] 2886 "" 2887 "") 2888 2889(define_insn "*extendhisi2_h8300" 2890 [(set (match_operand:SI 0 "register_operand" "=r,r") 2891 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))] 2892 "TARGET_H8300" 2893 "@ 2894 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0 2895 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0" 2896 [(set_attr "length" "6,10")]) 2897 2898(define_insn "*extendhisi2_h8300hs" 2899 [(set (match_operand:SI 0 "register_operand" "=r") 2900 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))] 2901 "TARGET_H8300H || TARGET_H8300S" 2902 "exts.l %S0" 2903 [(set_attr "length" "2") 2904 (set_attr "cc" "set_znv")]) 2905 2906;; ---------------------------------------------------------------------- 2907;; SHIFTS 2908;; ---------------------------------------------------------------------- 2909;; 2910;; We make some attempt to provide real efficient shifting. One example is 2911;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other 2912;; reg and moving 0 into the former reg. 2913;; 2914;; We also try to achieve this in a uniform way. IE: We don't try to achieve 2915;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would 2916;; give the optimizer more cracks at the code. However, we wish to do things 2917;; like optimizing shifting the sign bit to bit 0 by rotating the other way. 2918;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle 2919;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able 2920;; to detect cases it can optimize. 2921;; 2922;; For these and other fuzzy reasons, I've decided to go the less pretty but 2923;; easier "do it at insn emit time" route. 2924 2925;; QI BIT SHIFTS 2926 2927(define_expand "ashlqi3" 2928 [(set (match_operand:QI 0 "register_operand" "") 2929 (ashift:QI (match_operand:QI 1 "register_operand" "") 2930 (match_operand:QI 2 "nonmemory_operand" "")))] 2931 "" 2932 { 2933 if (expand_a_shift (QImode, ASHIFT, operands)) 2934 DONE; 2935 }) 2936 2937(define_expand "ashrqi3" 2938 [(set (match_operand:QI 0 "register_operand" "") 2939 (ashiftrt:QI (match_operand:QI 1 "register_operand" "") 2940 (match_operand:QI 2 "nonmemory_operand" "")))] 2941 "" 2942 { 2943 if (expand_a_shift (QImode, ASHIFTRT, operands)) 2944 DONE; 2945 }) 2946 2947(define_expand "lshrqi3" 2948 [(set (match_operand:QI 0 "register_operand" "") 2949 (lshiftrt:QI (match_operand:QI 1 "register_operand" "") 2950 (match_operand:QI 2 "nonmemory_operand" "")))] 2951 "" 2952 { 2953 if (expand_a_shift (QImode, LSHIFTRT, operands)) 2954 DONE; 2955 }) 2956 2957(define_insn "" 2958 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ") 2959 (match_operator:QI 3 "h8sx_unary_shift_operator" 2960 [(match_operand:QI 1 "h8300_dst_operand" "0") 2961 (match_operand:QI 2 "const_int_operand" "")]))] 2962 "h8300_operands_match_p (operands)" 2963{ 2964 return output_h8sx_shift (operands, 'b', 'X'); 2965} 2966 [(set_attr "length_table" "unary") 2967 (set_attr "cc" "set_znv")]) 2968 2969(define_insn "" 2970 [(set (match_operand:QI 0 "register_operand" "=r") 2971 (match_operator:QI 3 "h8sx_binary_shift_operator" 2972 [(match_operand:QI 1 "register_operand" "0") 2973 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))] 2974 "" 2975{ 2976 return output_h8sx_shift (operands, 'b', 'X'); 2977} 2978 [(set_attr "length" "4") 2979 (set_attr "cc" "set_znv")]) 2980 2981(define_insn "*shiftqi" 2982 [(set (match_operand:QI 0 "register_operand" "=r,r") 2983 (match_operator:QI 3 "nshift_operator" 2984 [(match_operand:QI 1 "register_operand" "0,0") 2985 (match_operand:QI 2 "nonmemory_operand" "R,rn")])) 2986 (clobber (match_scratch:QI 4 "=X,&r"))] 2987 "" 2988{ 2989 return output_a_shift (operands); 2990} 2991 [(set (attr "length") 2992 (symbol_ref "compute_a_shift_length (insn, operands)")) 2993 (set (attr "cc") 2994 (symbol_ref "compute_a_shift_cc (insn, operands)"))]) 2995 2996;; HI BIT SHIFTS 2997 2998(define_expand "ashlhi3" 2999 [(set (match_operand:HI 0 "register_operand" "") 3000 (ashift:HI (match_operand:HI 1 "register_operand" "") 3001 (match_operand:QI 2 "nonmemory_operand" "")))] 3002 "" 3003 { 3004 if (expand_a_shift (HImode, ASHIFT, operands)) 3005 DONE; 3006 }) 3007 3008(define_expand "lshrhi3" 3009 [(set (match_operand:HI 0 "register_operand" "") 3010 (lshiftrt:HI (match_operand:HI 1 "register_operand" "") 3011 (match_operand:QI 2 "nonmemory_operand" "")))] 3012 "" 3013 { 3014 if (expand_a_shift (HImode, LSHIFTRT, operands)) 3015 DONE; 3016 }) 3017 3018(define_expand "ashrhi3" 3019 [(set (match_operand:HI 0 "register_operand" "") 3020 (ashiftrt:HI (match_operand:HI 1 "register_operand" "") 3021 (match_operand:QI 2 "nonmemory_operand" "")))] 3022 "" 3023 { 3024 if (expand_a_shift (HImode, ASHIFTRT, operands)) 3025 DONE; 3026 }) 3027 3028(define_insn "" 3029 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") 3030 (match_operator:HI 3 "h8sx_unary_shift_operator" 3031 [(match_operand:HI 1 "h8300_dst_operand" "0") 3032 (match_operand:QI 2 "const_int_operand" "")]))] 3033 "h8300_operands_match_p (operands)" 3034{ 3035 return output_h8sx_shift (operands, 'w', 'T'); 3036} 3037 [(set_attr "length_table" "unary") 3038 (set_attr "cc" "set_znv")]) 3039 3040(define_insn "" 3041 [(set (match_operand:HI 0 "register_operand" "=r") 3042 (match_operator:HI 3 "h8sx_binary_shift_operator" 3043 [(match_operand:HI 1 "register_operand" "0") 3044 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))] 3045 "" 3046{ 3047 return output_h8sx_shift (operands, 'w', 'T'); 3048} 3049 [(set_attr "length" "4") 3050 (set_attr "cc" "set_znv")]) 3051 3052(define_insn "*shifthi" 3053 [(set (match_operand:HI 0 "register_operand" "=r,r") 3054 (match_operator:HI 3 "nshift_operator" 3055 [(match_operand:HI 1 "register_operand" "0,0") 3056 (match_operand:QI 2 "nonmemory_operand" "S,rn")])) 3057 (clobber (match_scratch:QI 4 "=X,&r"))] 3058 "" 3059{ 3060 return output_a_shift (operands); 3061} 3062 [(set (attr "length") 3063 (symbol_ref "compute_a_shift_length (insn, operands)")) 3064 (set (attr "cc") 3065 (symbol_ref "compute_a_shift_cc (insn, operands)"))]) 3066 3067;; SI BIT SHIFTS 3068 3069(define_expand "ashlsi3" 3070 [(set (match_operand:SI 0 "register_operand" "") 3071 (ashift:SI (match_operand:SI 1 "register_operand" "") 3072 (match_operand:QI 2 "nonmemory_operand" "")))] 3073 "" 3074 { 3075 if (expand_a_shift (SImode, ASHIFT, operands)) 3076 DONE; 3077 }) 3078 3079(define_expand "lshrsi3" 3080 [(set (match_operand:SI 0 "register_operand" "") 3081 (lshiftrt:SI (match_operand:SI 1 "register_operand" "") 3082 (match_operand:QI 2 "nonmemory_operand" "")))] 3083 "" 3084 { 3085 if (expand_a_shift (SImode, LSHIFTRT, operands)) 3086 DONE; 3087 }) 3088 3089(define_expand "ashrsi3" 3090 [(set (match_operand:SI 0 "register_operand" "") 3091 (ashiftrt:SI (match_operand:SI 1 "register_operand" "") 3092 (match_operand:QI 2 "nonmemory_operand" "")))] 3093 "" 3094 { 3095 if (expand_a_shift (SImode, ASHIFTRT, operands)) 3096 DONE; 3097 }) 3098 3099(define_insn "" 3100 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") 3101 (match_operator:SI 3 "h8sx_unary_shift_operator" 3102 [(match_operand:SI 1 "h8300_dst_operand" "0") 3103 (match_operand:QI 2 "const_int_operand" "")]))] 3104 "h8300_operands_match_p (operands)" 3105{ 3106 return output_h8sx_shift (operands, 'l', 'S'); 3107} 3108 [(set_attr "length_table" "unary") 3109 (set_attr "cc" "set_znv")]) 3110 3111(define_insn "" 3112 [(set (match_operand:SI 0 "register_operand" "=r") 3113 (match_operator:SI 3 "h8sx_binary_shift_operator" 3114 [(match_operand:SI 1 "register_operand" "0") 3115 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))] 3116 "" 3117{ 3118 return output_h8sx_shift (operands, 'l', 'S'); 3119} 3120 [(set_attr "length" "4") 3121 (set_attr "cc" "set_znv")]) 3122 3123(define_insn "*shiftsi" 3124 [(set (match_operand:SI 0 "register_operand" "=r,r") 3125 (match_operator:SI 3 "nshift_operator" 3126 [(match_operand:SI 1 "register_operand" "0,0") 3127 (match_operand:QI 2 "nonmemory_operand" "T,rn")])) 3128 (clobber (match_scratch:QI 4 "=X,&r"))] 3129 "" 3130{ 3131 return output_a_shift (operands); 3132} 3133 [(set (attr "length") 3134 (symbol_ref "compute_a_shift_length (insn, operands)")) 3135 (set (attr "cc") 3136 (symbol_ref "compute_a_shift_cc (insn, operands)"))]) 3137 3138;; Split a variable shift into a loop. If the register containing 3139;; the shift count dies, then we just use that register. 3140 3141(define_split 3142 [(set (match_operand 0 "register_operand" "") 3143 (match_operator 2 "nshift_operator" 3144 [(match_dup 0) 3145 (match_operand:QI 1 "register_operand" "")])) 3146 (clobber (match_operand:QI 3 "register_operand" ""))] 3147 "epilogue_completed 3148 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))" 3149 [(set (cc0) (compare (match_dup 1) (const_int 0))) 3150 (set (pc) 3151 (if_then_else (le (cc0) (const_int 0)) 3152 (label_ref (match_dup 5)) 3153 (pc))) 3154 (match_dup 4) 3155 (parallel 3156 [(set (match_dup 0) 3157 (match_op_dup 2 [(match_dup 0) (const_int 1)])) 3158 (clobber (scratch:QI))]) 3159 (set (match_dup 1) (plus:QI (match_dup 1) (const_int -1))) 3160 (set (cc0) (compare (match_dup 1) (const_int 0))) 3161 (set (pc) 3162 (if_then_else (ne (cc0) (const_int 0)) 3163 (label_ref (match_dup 4)) 3164 (pc))) 3165 (match_dup 5)] 3166 { 3167 operands[4] = gen_label_rtx (); 3168 operands[5] = gen_label_rtx (); 3169 }) 3170 3171(define_split 3172 [(set (match_operand 0 "register_operand" "") 3173 (match_operator 2 "nshift_operator" 3174 [(match_dup 0) 3175 (match_operand:QI 1 "register_operand" "")])) 3176 (clobber (match_operand:QI 3 "register_operand" ""))] 3177 "epilogue_completed 3178 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))" 3179 [(set (match_dup 3) 3180 (match_dup 1)) 3181 (set (cc0) (compare (match_dup 3) (const_int 0))) 3182 (set (pc) 3183 (if_then_else (le (cc0) (const_int 0)) 3184 (label_ref (match_dup 5)) 3185 (pc))) 3186 (match_dup 4) 3187 (parallel 3188 [(set (match_dup 0) 3189 (match_op_dup 2 [(match_dup 0) (const_int 1)])) 3190 (clobber (scratch:QI))]) 3191 (set (match_dup 3) (plus:QI (match_dup 3) (const_int -1))) 3192 (set (cc0) (compare (match_dup 3) (const_int 0))) 3193 (set (pc) 3194 (if_then_else (ne (cc0) (const_int 0)) 3195 (label_ref (match_dup 4)) 3196 (pc))) 3197 (match_dup 5)] 3198 { 3199 operands[4] = gen_label_rtx (); 3200 operands[5] = gen_label_rtx (); 3201 }) 3202 3203;; ---------------------------------------------------------------------- 3204;; ROTATIONS 3205;; ---------------------------------------------------------------------- 3206 3207(define_expand "rotlqi3" 3208 [(set (match_operand:QI 0 "register_operand" "") 3209 (rotate:QI (match_operand:QI 1 "register_operand" "") 3210 (match_operand:QI 2 "nonmemory_operand" "")))] 3211 "" 3212 { 3213 if (expand_a_rotate (operands)) 3214 DONE; 3215 }) 3216 3217(define_insn "rotlqi3_1" 3218 [(set (match_operand:QI 0 "register_operand" "=r") 3219 (rotate:QI (match_operand:QI 1 "register_operand" "0") 3220 (match_operand:QI 2 "immediate_operand" "")))] 3221 "" 3222{ 3223 return output_a_rotate (ROTATE, operands); 3224} 3225 [(set (attr "length") 3226 (symbol_ref "compute_a_rotate_length (operands)"))]) 3227 3228(define_expand "rotlhi3" 3229 [(set (match_operand:HI 0 "register_operand" "") 3230 (rotate:HI (match_operand:HI 1 "register_operand" "") 3231 (match_operand:QI 2 "nonmemory_operand" "")))] 3232 "" 3233 { 3234 if (expand_a_rotate (operands)) 3235 DONE; 3236 }) 3237 3238(define_insn "rotlhi3_1" 3239 [(set (match_operand:HI 0 "register_operand" "=r") 3240 (rotate:HI (match_operand:HI 1 "register_operand" "0") 3241 (match_operand:QI 2 "immediate_operand" "")))] 3242 "" 3243{ 3244 return output_a_rotate (ROTATE, operands); 3245} 3246 [(set (attr "length") 3247 (symbol_ref "compute_a_rotate_length (operands)"))]) 3248 3249(define_expand "rotlsi3" 3250 [(set (match_operand:SI 0 "register_operand" "") 3251 (rotate:SI (match_operand:SI 1 "register_operand" "") 3252 (match_operand:QI 2 "nonmemory_operand" "")))] 3253 "TARGET_H8300H || TARGET_H8300S" 3254 { 3255 if (expand_a_rotate (operands)) 3256 DONE; 3257 }) 3258 3259(define_insn "rotlsi3_1" 3260 [(set (match_operand:SI 0 "register_operand" "=r") 3261 (rotate:SI (match_operand:SI 1 "register_operand" "0") 3262 (match_operand:QI 2 "immediate_operand" "")))] 3263 "TARGET_H8300H || TARGET_H8300S" 3264{ 3265 return output_a_rotate (ROTATE, operands); 3266} 3267 [(set (attr "length") 3268 (symbol_ref "compute_a_rotate_length (operands)"))]) 3269 3270;; ----------------------------------------------------------------- 3271;; BIT FIELDS 3272;; ----------------------------------------------------------------- 3273;; The H8/300 has given 1/8th of its opcode space to bitfield 3274;; instructions so let's use them as well as we can. 3275 3276;; You'll never believe all these patterns perform one basic action -- 3277;; load a bit from the source, optionally invert the bit, then store it 3278;; in the destination (which is known to be zero). 3279;; 3280;; Combine obviously need some work to better identify this situation and 3281;; canonicalize the form better. 3282 3283;; 3284;; Normal loads with a 16bit destination. 3285;; 3286 3287(define_insn "" 3288 [(set (match_operand:HI 0 "register_operand" "=&r") 3289 (zero_extract:HI (match_operand:HI 1 "register_operand" "r") 3290 (const_int 1) 3291 (match_operand:HI 2 "immediate_operand" "n")))] 3292 "TARGET_H8300" 3293 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0" 3294 [(set_attr "length" "6")]) 3295 3296;; 3297;; Inverted loads with a 16bit destination. 3298;; 3299 3300(define_insn "" 3301 [(set (match_operand:HI 0 "register_operand" "=&r") 3302 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r") 3303 (match_operand:HI 3 "const_int_operand" "n")) 3304 (const_int 1) 3305 (match_operand:HI 2 "const_int_operand" "n")))] 3306 "(TARGET_H8300 || TARGET_H8300SX) 3307 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" 3308 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0" 3309 [(set_attr "length" "8")]) 3310 3311;; 3312;; Normal loads with a 32bit destination. 3313;; 3314 3315(define_insn "*extzv_1_r_h8300" 3316 [(set (match_operand:SI 0 "register_operand" "=&r") 3317 (zero_extract:SI (match_operand:HI 1 "register_operand" "r") 3318 (const_int 1) 3319 (match_operand 2 "const_int_operand" "n")))] 3320 "TARGET_H8300 && INTVAL (operands[2]) < 16" 3321{ 3322 return output_simode_bld (0, operands); 3323} 3324 [(set_attr "length" "8")]) 3325 3326(define_insn "*extzv_1_r_h8300hs" 3327 [(set (match_operand:SI 0 "register_operand" "=r,r") 3328 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r") 3329 (const_int 1) 3330 (match_operand 2 "const_int_operand" "n,n")))] 3331 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16" 3332{ 3333 return output_simode_bld (0, operands); 3334} 3335 [(set_attr "cc" "set_znv,set_znv") 3336 (set_attr "length" "8,6")]) 3337 3338;; 3339;; Inverted loads with a 32bit destination. 3340;; 3341 3342(define_insn "*extzv_1_r_inv_h8300" 3343 [(set (match_operand:SI 0 "register_operand" "=&r") 3344 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r") 3345 (match_operand:HI 3 "const_int_operand" "n")) 3346 (const_int 1) 3347 (match_operand 2 "const_int_operand" "n")))] 3348 "TARGET_H8300 && INTVAL (operands[2]) < 16 3349 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" 3350{ 3351 return output_simode_bld (1, operands); 3352} 3353 [(set_attr "length" "8")]) 3354 3355(define_insn "*extzv_1_r_inv_h8300hs" 3356 [(set (match_operand:SI 0 "register_operand" "=r,r") 3357 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r") 3358 (match_operand 3 "const_int_operand" "n,n")) 3359 (const_int 1) 3360 (match_operand 2 "const_int_operand" "n,n")))] 3361 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16 3362 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" 3363{ 3364 return output_simode_bld (1, operands); 3365} 3366 [(set_attr "cc" "set_znv,set_znv") 3367 (set_attr "length" "8,6")]) 3368 3369(define_expand "insv" 3370 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "") 3371 (match_operand:HI 1 "general_operand" "") 3372 (match_operand:HI 2 "general_operand" "")) 3373 (match_operand:HI 3 "general_operand" ""))] 3374 "TARGET_H8300 || TARGET_H8300SX" 3375 { 3376 if (TARGET_H8300SX) 3377 { 3378 if (GET_CODE (operands[1]) == CONST_INT 3379 && GET_CODE (operands[2]) == CONST_INT 3380 && INTVAL (operands[1]) <= 8 3381 && INTVAL (operands[2]) >= 0 3382 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8 3383 && memory_operand (operands[0], GET_MODE (operands[0]))) 3384 { 3385 /* If the source operand is zero, it's better to use AND rather 3386 than BFST. Likewise OR if the operand is all ones. */ 3387 if (GET_CODE (operands[3]) == CONST_INT) 3388 { 3389 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1; 3390 if ((INTVAL (operands[3]) & mask) == 0) 3391 FAIL; 3392 if ((INTVAL (operands[3]) & mask) == mask) 3393 FAIL; 3394 } 3395 if (! bit_memory_operand (operands[0], GET_MODE (operands[0]))) 3396 { 3397 if (!can_create_pseudo_p ()) 3398 FAIL; 3399 operands[0] = replace_equiv_address (operands[0], force_reg (Pmode, 3400 XEXP (operands[0], 0))); 3401 } 3402 operands[3] = gen_lowpart (QImode, operands[3]); 3403 if (! operands[3]) 3404 FAIL; 3405 if (! register_operand (operands[3], QImode)) 3406 { 3407 if (!can_create_pseudo_p ()) 3408 FAIL; 3409 operands[3] = force_reg (QImode, operands[3]); 3410 } 3411 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0), 3412 operands[3], operands[1], operands[2])); 3413 DONE; 3414 } 3415 FAIL; 3416 } 3417 3418 /* We only have single bit bit-field instructions. */ 3419 if (INTVAL (operands[1]) != 1) 3420 FAIL; 3421 3422 /* For now, we don't allow memory operands. */ 3423 if (GET_CODE (operands[0]) == MEM 3424 || GET_CODE (operands[3]) == MEM) 3425 FAIL; 3426 3427 if (GET_CODE (operands[3]) != REG) 3428 operands[3] = force_reg (HImode, operands[3]); 3429 }) 3430 3431(define_insn "" 3432 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r") 3433 (const_int 1) 3434 (match_operand:HI 1 "immediate_operand" "n")) 3435 (match_operand:HI 2 "register_operand" "r"))] 3436 "" 3437 "bld #0,%R2\;bst %Z1,%Y0 ; i1" 3438 [(set_attr "length" "4")]) 3439 3440(define_expand "extzv" 3441 [(set (match_operand:HI 0 "register_operand" "") 3442 (zero_extract:HI (match_operand:HI 1 "bit_operand" "") 3443 (match_operand:HI 2 "general_operand" "") 3444 (match_operand:HI 3 "general_operand" "")))] 3445 "TARGET_H8300 || TARGET_H8300SX" 3446 { 3447 if (TARGET_H8300SX) 3448 { 3449 if (GET_CODE (operands[2]) == CONST_INT 3450 && GET_CODE (operands[3]) == CONST_INT 3451 && INTVAL (operands[2]) <= 8 3452 && INTVAL (operands[3]) >= 0 3453 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8 3454 && memory_operand (operands[1], QImode)) 3455 { 3456 rtx temp; 3457 3458 /* Optimize the case where we're extracting into a paradoxical 3459 subreg. It's only necessary to extend to the inner reg. */ 3460 if (GET_CODE (operands[0]) == SUBREG 3461 && subreg_lowpart_p (operands[0]) 3462 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) 3463 < GET_MODE_SIZE (GET_MODE (operands[0]))) 3464 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) 3465 == MODE_INT)) 3466 operands[0] = SUBREG_REG (operands[0]); 3467 3468 if (!can_create_pseudo_p ()) 3469 temp = gen_lowpart (QImode, operands[0]); 3470 else 3471 temp = gen_reg_rtx (QImode); 3472 if (! temp) 3473 FAIL; 3474 if (! bit_memory_operand (operands[1], QImode)) 3475 { 3476 if (!can_create_pseudo_p ()) 3477 FAIL; 3478 operands[1] = replace_equiv_address (operands[1], 3479 force_reg (Pmode, XEXP (operands[1], 0))); 3480 } 3481 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3])); 3482 convert_move (operands[0], temp, 1); 3483 DONE; 3484 } 3485 FAIL; 3486 } 3487 3488 /* We only have single bit bit-field instructions. */ 3489 if (INTVAL (operands[2]) != 1) 3490 FAIL; 3491 3492 /* For now, we don't allow memory operands. */ 3493 if (GET_CODE (operands[1]) == MEM) 3494 FAIL; 3495 }) 3496 3497;; BAND, BOR, and BXOR patterns 3498 3499(define_insn "" 3500 [(set (match_operand:HI 0 "bit_operand" "=Ur") 3501 (match_operator:HI 4 "bit_operator" 3502 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r") 3503 (const_int 1) 3504 (match_operand:HI 2 "immediate_operand" "n")) 3505 (match_operand:HI 3 "bit_operand" "0")]))] 3506 "" 3507 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1" 3508 [(set_attr "length" "6")]) 3509 3510(define_insn "" 3511 [(set (match_operand:HI 0 "bit_operand" "=Ur") 3512 (match_operator:HI 5 "bit_operator" 3513 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r") 3514 (const_int 1) 3515 (match_operand:HI 2 "immediate_operand" "n")) 3516 (zero_extract:HI (match_operand:HI 3 "register_operand" "r") 3517 (const_int 1) 3518 (match_operand:HI 4 "immediate_operand" "n"))]))] 3519 "" 3520 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3" 3521 [(set_attr "length" "6")]) 3522 3523(define_insn "bfld" 3524 [(set (match_operand:QI 0 "register_operand" "=r") 3525 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU") 3526 (match_operand:QI 2 "immediate_operand" "n") 3527 (match_operand:QI 3 "immediate_operand" "n")))] 3528 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8" 3529{ 3530 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3]))) 3531 - (1 << INTVAL (operands[3]))); 3532 return "bfld %2,%1,%R0"; 3533} 3534 [(set_attr "cc" "none_0hit") 3535 (set_attr "length_table" "bitfield")]) 3536 3537(define_insn "bfst" 3538 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU") 3539 (match_operand:QI 2 "immediate_operand" "n") 3540 (match_operand:QI 3 "immediate_operand" "n")) 3541 (match_operand:QI 1 "register_operand" "r"))] 3542 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8" 3543{ 3544 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3]))) 3545 - (1 << INTVAL (operands[3]))); 3546 return "bfst %R1,%2,%0"; 3547} 3548 [(set_attr "cc" "none_0hit") 3549 (set_attr "length_table" "bitfield")]) 3550 3551(define_expand "cstoreqi4" 3552 [(use (match_operator 1 "eqne_operator" 3553 [(match_operand:QI 2 "h8300_dst_operand" "") 3554 (match_operand:QI 3 "h8300_src_operand" "")])) 3555 (clobber (match_operand:HI 0 "register_operand"))] 3556 "TARGET_H8300SX" 3557 { 3558 h8300_expand_store (operands); 3559 DONE; 3560 }) 3561 3562(define_expand "cstorehi4" 3563 [(use (match_operator 1 "eqne_operator" 3564 [(match_operand:HI 2 "h8300_dst_operand" "") 3565 (match_operand:HI 3 "h8300_src_operand" "")])) 3566 (clobber (match_operand:HI 0 "register_operand"))] 3567 "TARGET_H8300SX" 3568 { 3569 h8300_expand_store (operands); 3570 DONE; 3571 }) 3572 3573(define_expand "cstoresi4" 3574 [(use (match_operator 1 "eqne_operator" 3575 [(match_operand:SI 2 "h8300_dst_operand" "") 3576 (match_operand:SI 3 "h8300_src_operand" "")])) 3577 (clobber (match_operand:HI 0 "register_operand"))] 3578 "TARGET_H8300SX" 3579 { 3580 h8300_expand_store (operands); 3581 DONE; 3582 }) 3583 3584(define_insn "*bstzhireg" 3585 [(set (match_operand:HI 0 "register_operand" "=r") 3586 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))] 3587 "TARGET_H8300SX" 3588 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:" 3589 [(set_attr "cc" "clobber")]) 3590 3591(define_insn_and_split "*cmpstz" 3592 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,+WU") 3593 (const_int 1) 3594 (match_operand:QI 1 "immediate_operand" "n,n")) 3595 (match_operator:QI 2 "eqne_operator" 3596 [(match_operand 3 "h8300_dst_operand" "r,rQ") 3597 (match_operand 4 "h8300_src_operand" "I,rQi")]))] 3598 "TARGET_H8300SX 3599 && (GET_MODE (operands[3]) == GET_MODE (operands[4]) 3600 || GET_CODE (operands[4]) == CONST_INT) 3601 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT 3602 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4" 3603 "#" 3604 "reload_completed" 3605 [(set (cc0) (match_dup 5)) 3606 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1)) 3607 (match_op_dup:QI 2 [(cc0) (const_int 0)]))] 3608 { 3609 operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]); 3610 } 3611 [(set_attr "cc" "set_znv,compare")]) 3612 3613(define_insn "*bstz" 3614 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU") 3615 (const_int 1) 3616 (match_operand:QI 1 "immediate_operand" "n")) 3617 (eq:QI (cc0) (const_int 0)))] 3618 "TARGET_H8300SX && reload_completed" 3619 "bstz %1,%0" 3620 [(set_attr "cc" "none_0hit") 3621 (set_attr "length_table" "unary")]) 3622 3623(define_insn "*bistz" 3624 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU") 3625 (const_int 1) 3626 (match_operand:QI 1 "immediate_operand" "n")) 3627 (ne:QI (cc0) (const_int 0)))] 3628 "TARGET_H8300SX && reload_completed" 3629 "bistz %1,%0" 3630 [(set_attr "cc" "none_0hit") 3631 (set_attr "length_table" "unary")]) 3632 3633(define_insn_and_split "*cmpcondbset" 3634 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU") 3635 (if_then_else:QI (match_operator 1 "eqne_operator" 3636 [(match_operand 2 "h8300_dst_operand" "r,rQ") 3637 (match_operand 3 "h8300_src_operand" "I,rQi")]) 3638 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0") 3639 (match_operand:QI 5 "single_one_operand" "n,n")) 3640 (match_dup 4)))] 3641 "TARGET_H8300SX" 3642 "#" 3643 "reload_completed" 3644 [(set (cc0) (match_dup 6)) 3645 (set (match_dup 0) 3646 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)]) 3647 (ior:QI (match_dup 4) (match_dup 5)) 3648 (match_dup 4)))] 3649 { 3650 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]); 3651 } 3652 [(set_attr "cc" "set_znv,compare")]) 3653 3654(define_insn "*condbset" 3655 [(set (match_operand:QI 0 "bit_memory_operand" "=WU") 3656 (if_then_else:QI (match_operator:QI 2 "eqne_operator" 3657 [(cc0) (const_int 0)]) 3658 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0") 3659 (match_operand:QI 1 "single_one_operand" "n")) 3660 (match_dup 3)))] 3661 "TARGET_H8300SX && reload_completed" 3662 "bset/%j2\t%V1,%0" 3663 [(set_attr "cc" "none_0hit") 3664 (set_attr "length_table" "logicb")]) 3665 3666(define_insn_and_split "*cmpcondbclr" 3667 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU") 3668 (if_then_else:QI (match_operator 1 "eqne_operator" 3669 [(match_operand 2 "h8300_dst_operand" "r,rQ") 3670 (match_operand 3 "h8300_src_operand" "I,rQi")]) 3671 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0") 3672 (match_operand:QI 5 "single_zero_operand" "n,n")) 3673 (match_dup 4)))] 3674 "TARGET_H8300SX" 3675 "#" 3676 "reload_completed" 3677 [(set (cc0) (match_dup 6)) 3678 (set (match_dup 0) 3679 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)]) 3680 (and:QI (match_dup 4) (match_dup 5)) 3681 (match_dup 4)))] 3682 { 3683 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]); 3684 } 3685 [(set_attr "cc" "set_znv,compare")]) 3686 3687(define_insn "*condbclr" 3688 [(set (match_operand:QI 0 "bit_memory_operand" "=WU") 3689 (if_then_else:QI (match_operator:QI 2 "eqne_operator" 3690 [(cc0) (const_int 0)]) 3691 (and:QI (match_operand:QI 3 "bit_memory_operand" "0") 3692 (match_operand:QI 1 "single_zero_operand" "n")) 3693 (match_dup 3)))] 3694 "TARGET_H8300SX && reload_completed" 3695 "bclr/%j2\t%W1,%0" 3696 [(set_attr "cc" "none_0hit") 3697 (set_attr "length_table" "logicb")]) 3698 3699(define_insn_and_split "*cmpcondbsetreg" 3700 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU") 3701 (if_then_else:QI (match_operator 1 "eqne_operator" 3702 [(match_operand 2 "h8300_dst_operand" "r,rQ") 3703 (match_operand 3 "h8300_src_operand" "I,rQi")]) 3704 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0") 3705 (ashift:QI (const_int 1) 3706 (match_operand:QI 5 "register_operand" "r,r"))) 3707 (match_dup 4)))] 3708 "TARGET_H8300SX" 3709 "#" 3710 "reload_completed" 3711 [(set (cc0) (match_dup 6)) 3712 (set (match_dup 0) 3713 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)]) 3714 (ior:QI (match_dup 4) 3715 (ashift:QI (const_int 1) 3716 (match_operand:QI 5 "register_operand" "r,r"))) 3717 (match_dup 4)))] 3718 { 3719 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]); 3720 } 3721 [(set_attr "cc" "set_znv,compare")]) 3722 3723(define_insn "*condbsetreg" 3724 [(set (match_operand:QI 0 "bit_memory_operand" "=WU") 3725 (if_then_else:QI (match_operator:QI 2 "eqne_operator" 3726 [(cc0) (const_int 0)]) 3727 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0") 3728 (ashift:QI (const_int 1) 3729 (match_operand:QI 1 "register_operand" "r"))) 3730 (match_dup 3)))] 3731 "TARGET_H8300SX && reload_completed" 3732 "bset/%j2\t%R1,%0" 3733 [(set_attr "cc" "none_0hit") 3734 (set_attr "length_table" "logicb")]) 3735 3736(define_insn_and_split "*cmpcondbclrreg" 3737 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU") 3738 (if_then_else:QI (match_operator 1 "eqne_operator" 3739 [(match_operand 2 "h8300_dst_operand" "r,rQ") 3740 (match_operand 3 "h8300_src_operand" "I,rQi")]) 3741 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0") 3742 (ashift:QI (const_int 1) 3743 (match_operand:QI 5 "register_operand" "r,r"))) 3744 (match_dup 4)))] 3745 "TARGET_H8300SX" 3746 "#" 3747 "reload_completed" 3748 [(set (cc0) (match_dup 6)) 3749 (set (match_dup 0) 3750 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)]) 3751 (and:QI (match_dup 4) 3752 (ashift:QI (const_int 1) 3753 (match_operand:QI 5 "register_operand" "r,r"))) 3754 (match_dup 4)))] 3755 { 3756 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]); 3757 } 3758 [(set_attr "cc" "set_znv,compare")]) 3759 3760(define_insn "*condbclrreg" 3761 [(set (match_operand:QI 0 "bit_memory_operand" "=WU") 3762 (if_then_else:QI (match_operator:QI 2 "eqne_operator" 3763 [(cc0) (const_int 0)]) 3764 (and:QI (match_operand:QI 3 "bit_memory_operand" "0") 3765 (ashift:QI (const_int 1) 3766 (match_operand:QI 1 "register_operand" "r"))) 3767 (match_dup 3)))] 3768 "TARGET_H8300SX && reload_completed" 3769 "bclr/%j2\t%R1,%0" 3770 [(set_attr "cc" "none_0hit") 3771 (set_attr "length_table" "logicb")]) 3772 3773 3774;; ----------------------------------------------------------------- 3775;; COMBINE PATTERNS 3776;; ----------------------------------------------------------------- 3777 3778;; insv:SI 3779 3780(define_insn "*insv_si_1_n" 3781 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 3782 (const_int 1) 3783 (match_operand:SI 1 "const_int_operand" "n")) 3784 (match_operand:SI 2 "register_operand" "r"))] 3785 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16" 3786 "bld\\t#0,%w2\;bst\\t%Z1,%Y0" 3787 [(set_attr "length" "4")]) 3788 3789(define_insn "*insv_si_1_n_lshiftrt" 3790 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 3791 (const_int 1) 3792 (match_operand:SI 1 "const_int_operand" "n")) 3793 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 3794 (match_operand:SI 3 "const_int_operand" "n")))] 3795 "(TARGET_H8300H || TARGET_H8300S) 3796 && INTVAL (operands[1]) < 16 3797 && INTVAL (operands[3]) < 16" 3798 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0" 3799 [(set_attr "length" "4")]) 3800 3801(define_insn "*insv_si_1_n_lshiftrt_16" 3802 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 3803 (const_int 1) 3804 (match_operand:SI 1 "const_int_operand" "n")) 3805 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 3806 (const_int 16)))] 3807 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16" 3808 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0" 3809 [(set_attr "length" "6")]) 3810 3811(define_insn "*insv_si_8_8" 3812 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 3813 (const_int 8) 3814 (const_int 8)) 3815 (match_operand:SI 1 "register_operand" "r"))] 3816 "TARGET_H8300H || TARGET_H8300S" 3817 "mov.b\\t%w1,%x0" 3818 [(set_attr "length" "2")]) 3819 3820(define_insn "*insv_si_8_8_lshiftrt_8" 3821 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 3822 (const_int 8) 3823 (const_int 8)) 3824 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 3825 (const_int 8)))] 3826 "TARGET_H8300H || TARGET_H8300S" 3827 "mov.b\\t%x1,%x0" 3828 [(set_attr "length" "2")]) 3829 3830;; extzv:SI 3831 3832(define_insn "*extzv_8_8" 3833 [(set (match_operand:SI 0 "register_operand" "=r,r") 3834 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r") 3835 (const_int 8) 3836 (const_int 8)))] 3837 "TARGET_H8300H || TARGET_H8300S" 3838 "@ 3839 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0 3840 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0" 3841 [(set_attr "cc" "set_znv,clobber") 3842 (set_attr "length" "6,4")]) 3843 3844(define_insn "*extzv_8_16" 3845 [(set (match_operand:SI 0 "register_operand" "=r") 3846 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 3847 (const_int 8) 3848 (const_int 16)))] 3849 "TARGET_H8300H || TARGET_H8300S" 3850 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0" 3851 [(set_attr "cc" "set_znv") 3852 (set_attr "length" "6")]) 3853 3854(define_insn "*extzv_16_8" 3855 [(set (match_operand:SI 0 "register_operand" "=r") 3856 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 3857 (const_int 16) 3858 (const_int 8))) 3859 (clobber (match_scratch:SI 2 "=&r"))] 3860 "TARGET_H8300H" 3861 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0" 3862 [(set_attr "length" "8") 3863 (set_attr "cc" "set_znv")]) 3864 3865;; Extract the exponent of a float. 3866 3867(define_insn_and_split "*extzv_8_23" 3868 [(set (match_operand:SI 0 "register_operand" "=r") 3869 (zero_extract:SI (match_operand:SI 1 "register_operand" "0") 3870 (const_int 8) 3871 (const_int 23)))] 3872 "(TARGET_H8300H || TARGET_H8300S)" 3873 "#" 3874 "&& reload_completed" 3875 [(parallel [(set (match_dup 0) 3876 (ashift:SI (match_dup 0) 3877 (const_int 1))) 3878 (clobber (scratch:QI))]) 3879 (parallel [(set (match_dup 0) 3880 (lshiftrt:SI (match_dup 0) 3881 (const_int 24))) 3882 (clobber (scratch:QI))])] 3883 "") 3884 3885;; and:SI 3886 3887;; ((SImode) HImode) << 15 3888 3889(define_insn_and_split "*twoshifts_l16_r1" 3890 [(set (match_operand:SI 0 "register_operand" "=r") 3891 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") 3892 (const_int 15)) 3893 (const_int 2147450880)))] 3894 "(TARGET_H8300H || TARGET_H8300S)" 3895 "#" 3896 "&& reload_completed" 3897 [(parallel [(set (match_dup 0) 3898 (ashift:SI (match_dup 0) 3899 (const_int 16))) 3900 (clobber (scratch:QI))]) 3901 (parallel [(set (match_dup 0) 3902 (lshiftrt:SI (match_dup 0) 3903 (const_int 1))) 3904 (clobber (scratch:QI))])] 3905 "") 3906 3907;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B). 3908 3909(define_insn_and_split "*andsi3_ashift_n_lower" 3910 [(set (match_operand:SI 0 "register_operand" "=r,r") 3911 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0") 3912 (match_operand:QI 2 "const_int_operand" "S,n")) 3913 (match_operand:SI 3 "const_int_operand" "n,n"))) 3914 (clobber (match_scratch:QI 4 "=X,&r"))] 3915 "(TARGET_H8300H || TARGET_H8300S) 3916 && INTVAL (operands[2]) <= 15 3917 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)" 3918 "#" 3919 "&& reload_completed" 3920 [(parallel [(set (match_dup 5) 3921 (ashift:HI (match_dup 5) 3922 (match_dup 2))) 3923 (clobber (match_dup 4))]) 3924 (set (match_dup 0) 3925 (zero_extend:SI (match_dup 5)))] 3926 { 3927 operands[5] = gen_rtx_REG (HImode, REGNO (operands[0])); 3928 }) 3929 3930;; Accept (A >> 30) & 2 and the like. 3931 3932(define_insn "*andsi3_lshiftrt_n_sb" 3933 [(set (match_operand:SI 0 "register_operand" "=r") 3934 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 3935 (match_operand:SI 2 "const_int_operand" "n")) 3936 (match_operand:SI 3 "single_one_operand" "n")))] 3937 "(TARGET_H8300H || TARGET_H8300S) 3938 && exact_log2 (INTVAL (operands[3])) < 16 3939 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31" 3940{ 3941 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); 3942 return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0"; 3943} 3944 [(set_attr "length" "8")]) 3945 3946(define_insn_and_split "*andsi3_lshiftrt_9_sb" 3947 [(set (match_operand:SI 0 "register_operand" "=r") 3948 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 3949 (const_int 9)) 3950 (const_int 4194304)))] 3951 "TARGET_H8300H || TARGET_H8300S" 3952 "#" 3953 "&& reload_completed" 3954 [(set (match_dup 0) 3955 (and:SI (lshiftrt:SI (match_dup 0) 3956 (const_int 25)) 3957 (const_int 64))) 3958 (parallel [(set (match_dup 0) 3959 (ashift:SI (match_dup 0) 3960 (const_int 16))) 3961 (clobber (scratch:QI))])] 3962 "") 3963 3964;; plus:SI 3965 3966(define_insn "*addsi3_upper" 3967 [(set (match_operand:SI 0 "register_operand" "=r") 3968 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") 3969 (const_int 65536)) 3970 (match_operand:SI 2 "register_operand" "0")))] 3971 "TARGET_H8300H || TARGET_H8300S" 3972 "add.w\\t%f1,%e0" 3973 [(set_attr "length" "2")]) 3974 3975(define_insn "*addsi3_lshiftrt_16_zexthi" 3976 [(set (match_operand:SI 0 "register_operand" "=r") 3977 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 3978 (const_int 16)) 3979 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))] 3980 "TARGET_H8300H || TARGET_H8300S" 3981 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0" 3982 [(set_attr "length" "6")]) 3983 3984(define_insn_and_split "*addsi3_and_r_1" 3985 [(set (match_operand:SI 0 "register_operand" "=r") 3986 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r") 3987 (const_int 1)) 3988 (match_operand:SI 2 "register_operand" "0")))] 3989 "TARGET_H8300H || TARGET_H8300S" 3990 "#" 3991 "&& reload_completed" 3992 [(set (cc0) (compare (zero_extract:SI (match_dup 1) 3993 (const_int 1) 3994 (const_int 0)) 3995 (const_int 0))) 3996 (set (pc) 3997 (if_then_else (eq (cc0) 3998 (const_int 0)) 3999 (label_ref (match_dup 3)) 4000 (pc))) 4001 (set (match_dup 2) 4002 (plus:SI (match_dup 2) 4003 (const_int 1))) 4004 (match_dup 3)] 4005 { 4006 operands[3] = gen_label_rtx (); 4007 }) 4008 4009(define_insn_and_split "*addsi3_and_not_r_1" 4010 [(set (match_operand:SI 0 "register_operand" "=r") 4011 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r")) 4012 (const_int 1)) 4013 (match_operand:SI 2 "register_operand" "0")))] 4014 "TARGET_H8300H || TARGET_H8300S" 4015 "#" 4016 "&& reload_completed" 4017 [(set (cc0) (compare (zero_extract:SI (match_dup 1) 4018 (const_int 1) 4019 (const_int 0)) 4020 (const_int 0))) 4021 (set (pc) 4022 (if_then_else (ne (cc0) 4023 (const_int 0)) 4024 (label_ref (match_dup 3)) 4025 (pc))) 4026 (set (match_dup 2) 4027 (plus:SI (match_dup 2) 4028 (const_int 1))) 4029 (match_dup 3)] 4030 { 4031 operands[3] = gen_label_rtx (); 4032 }) 4033 4034;; [ix]or:HI 4035 4036(define_insn "*ixorhi3_zext" 4037 [(set (match_operand:HI 0 "register_operand" "=r") 4038 (match_operator:HI 1 "iorxor_operator" 4039 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r")) 4040 (match_operand:HI 3 "register_operand" "0")]))] 4041 "" 4042 "%c1.b\\t%X2,%s0" 4043 [(set_attr "length" "2")]) 4044 4045;; [ix]or:SI 4046 4047(define_insn "*ixorsi3_zext_qi" 4048 [(set (match_operand:SI 0 "register_operand" "=r") 4049 (match_operator:SI 1 "iorxor_operator" 4050 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r")) 4051 (match_operand:SI 3 "register_operand" "0")]))] 4052 "" 4053 "%c1.b\\t%X2,%w0" 4054 [(set_attr "length" "2")]) 4055 4056(define_insn "*ixorsi3_zext_hi" 4057 [(set (match_operand:SI 0 "register_operand" "=r") 4058 (match_operator:SI 1 "iorxor_operator" 4059 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r")) 4060 (match_operand:SI 3 "register_operand" "0")]))] 4061 "TARGET_H8300H || TARGET_H8300S" 4062 "%c1.w\\t%T2,%f0" 4063 [(set_attr "length" "2")]) 4064 4065(define_insn "*ixorsi3_ashift_16" 4066 [(set (match_operand:SI 0 "register_operand" "=r") 4067 (match_operator:SI 1 "iorxor_operator" 4068 [(ashift:SI (match_operand:SI 2 "register_operand" "r") 4069 (const_int 16)) 4070 (match_operand:SI 3 "register_operand" "0")]))] 4071 "TARGET_H8300H || TARGET_H8300S" 4072 "%c1.w\\t%f2,%e0" 4073 [(set_attr "length" "2")]) 4074 4075(define_insn "*ixorsi3_lshiftrt_16" 4076 [(set (match_operand:SI 0 "register_operand" "=r") 4077 (match_operator:SI 1 "iorxor_operator" 4078 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 4079 (const_int 16)) 4080 (match_operand:SI 3 "register_operand" "0")]))] 4081 "TARGET_H8300H || TARGET_H8300S" 4082 "%c1.w\\t%e2,%f0" 4083 [(set_attr "length" "2")]) 4084 4085;; ior:HI 4086 4087(define_insn "*iorhi3_ashift_8" 4088 [(set (match_operand:HI 0 "register_operand" "=r") 4089 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r") 4090 (const_int 8)) 4091 (match_operand:HI 2 "register_operand" "0")))] 4092 "" 4093 "or.b\\t%s1,%t0" 4094 [(set_attr "length" "2")]) 4095 4096(define_insn "*iorhi3_lshiftrt_8" 4097 [(set (match_operand:HI 0 "register_operand" "=r") 4098 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r") 4099 (const_int 8)) 4100 (match_operand:HI 2 "register_operand" "0")))] 4101 "" 4102 "or.b\\t%t1,%s0" 4103 [(set_attr "length" "2")]) 4104 4105(define_insn "*iorhi3_two_qi" 4106 [(set (match_operand:HI 0 "register_operand" "=r") 4107 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0")) 4108 (ashift:HI (match_operand:HI 2 "register_operand" "r") 4109 (const_int 8))))] 4110 "" 4111 "mov.b\\t%s2,%t0" 4112 [(set_attr "length" "2")]) 4113 4114(define_insn "*iorhi3_two_qi_mem" 4115 [(set (match_operand:HI 0 "register_operand" "=&r") 4116 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")) 4117 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0) 4118 (const_int 8))))] 4119 "" 4120 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0" 4121 [(set_attr "length" "16")]) 4122 4123(define_split 4124 [(set (match_operand:HI 0 "register_operand" "") 4125 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "")) 4126 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0) 4127 (const_int 8))))] 4128 "(TARGET_H8300H || TARGET_H8300S) 4129 && reload_completed 4130 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))" 4131 [(set (match_dup 0) 4132 (match_dup 3))] 4133 { 4134 operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0)); 4135 }) 4136 4137;; ior:SI 4138 4139(define_insn "*iorsi3_two_hi" 4140 [(set (match_operand:SI 0 "register_operand" "=r") 4141 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0")) 4142 (ashift:SI (match_operand:SI 2 "register_operand" "r") 4143 (const_int 16))))] 4144 "TARGET_H8300H || TARGET_H8300S" 4145 "mov.w\\t%f2,%e0" 4146 [(set_attr "length" "2")]) 4147 4148(define_insn_and_split "*iorsi3_two_qi_zext" 4149 [(set (match_operand:SI 0 "register_operand" "=&r") 4150 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")) 4151 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0) 4152 (const_int 8)) 4153 (const_int 65280))))] 4154 "TARGET_H8300H || TARGET_H8300S" 4155 "#" 4156 "&& reload_completed" 4157 [(set (match_dup 3) 4158 (ior:HI (zero_extend:HI (match_dup 1)) 4159 (ashift:HI (subreg:HI (match_dup 2) 0) 4160 (const_int 8)))) 4161 (set (match_dup 0) 4162 (zero_extend:SI (match_dup 3)))] 4163 { 4164 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 4165 }) 4166 4167(define_insn "*iorsi3_e2f" 4168 [(set (match_operand:SI 0 "register_operand" "=r") 4169 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0") 4170 (const_int -65536)) 4171 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 4172 (const_int 16))))] 4173 "TARGET_H8300H || TARGET_H8300S" 4174 "mov.w\\t%e2,%f0" 4175 [(set_attr "length" "2")]) 4176 4177(define_insn_and_split "*iorsi3_two_qi_sext" 4178 [(set (match_operand:SI 0 "register_operand" "=r") 4179 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0")) 4180 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r")) 4181 (const_int 8))))] 4182 "TARGET_H8300H || TARGET_H8300S" 4183 "#" 4184 "&& reload_completed" 4185 [(set (match_dup 3) 4186 (ior:HI (zero_extend:HI (match_dup 1)) 4187 (ashift:HI (match_dup 4) 4188 (const_int 8)))) 4189 (set (match_dup 0) 4190 (sign_extend:SI (match_dup 3)))] 4191 { 4192 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 4193 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2])); 4194 }) 4195 4196(define_insn "*iorsi3_w" 4197 [(set (match_operand:SI 0 "register_operand" "=r,&r") 4198 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0") 4199 (const_int -256)) 4200 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))] 4201 "TARGET_H8300H || TARGET_H8300S" 4202 "mov.b\\t%X2,%w0" 4203 [(set_attr "length" "2,8")]) 4204 4205(define_insn "*iorsi3_ashift_31" 4206 [(set (match_operand:SI 0 "register_operand" "=&r") 4207 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 4208 (const_int 31)) 4209 (match_operand:SI 2 "register_operand" "0")))] 4210 "TARGET_H8300H || TARGET_H8300S" 4211 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0" 4212 [(set_attr "length" "6") 4213 (set_attr "cc" "set_znv")]) 4214 4215(define_insn "*iorsi3_and_ashift" 4216 [(set (match_operand:SI 0 "register_operand" "=r") 4217 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 4218 (match_operand:SI 2 "const_int_operand" "n")) 4219 (match_operand:SI 3 "single_one_operand" "n")) 4220 (match_operand:SI 4 "register_operand" "0")))] 4221 "(TARGET_H8300H || TARGET_H8300S) 4222 && (INTVAL (operands[3]) & ~0xffff) == 0" 4223{ 4224 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3])) 4225 - INTVAL (operands[2])); 4226 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3]))); 4227 operands[2] = srcpos; 4228 operands[3] = dstpos; 4229 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0"; 4230} 4231 [(set_attr "length" "6")]) 4232 4233(define_insn "*iorsi3_and_lshiftrt" 4234 [(set (match_operand:SI 0 "register_operand" "=r") 4235 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 4236 (match_operand:SI 2 "const_int_operand" "n")) 4237 (match_operand:SI 3 "single_one_operand" "n")) 4238 (match_operand:SI 4 "register_operand" "0")))] 4239 "(TARGET_H8300H || TARGET_H8300S) 4240 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0" 4241{ 4242 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3])) 4243 + INTVAL (operands[2])); 4244 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3]))); 4245 operands[2] = srcpos; 4246 operands[3] = dstpos; 4247 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0"; 4248} 4249 [(set_attr "length" "6")]) 4250 4251(define_insn "*iorsi3_zero_extract" 4252 [(set (match_operand:SI 0 "register_operand" "=r") 4253 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 4254 (const_int 1) 4255 (match_operand:SI 2 "const_int_operand" "n")) 4256 (match_operand:SI 3 "register_operand" "0")))] 4257 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16" 4258 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0" 4259 [(set_attr "length" "6")]) 4260 4261(define_insn "*iorsi3_and_lshiftrt_n_sb" 4262 [(set (match_operand:SI 0 "register_operand" "=r") 4263 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 4264 (const_int 30)) 4265 (const_int 2)) 4266 (match_operand:SI 2 "register_operand" "0")))] 4267 "TARGET_H8300H || TARGET_H8300S" 4268 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0" 4269 [(set_attr "length" "8")]) 4270 4271(define_insn "*iorsi3_and_lshiftrt_9_sb" 4272 [(set (match_operand:SI 0 "register_operand" "=r") 4273 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 4274 (const_int 9)) 4275 (const_int 4194304)) 4276 (match_operand:SI 2 "register_operand" "0"))) 4277 (clobber (match_scratch:HI 3 "=&r"))] 4278 "TARGET_H8300H || TARGET_H8300S" 4279{ 4280 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 4281 return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0"; 4282 else 4283 return "rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0"; 4284} 4285 [(set_attr "length" "10")]) 4286 4287;; Used to OR the exponent of a float. 4288 4289(define_insn "*iorsi3_shift" 4290 [(set (match_operand:SI 0 "register_operand" "=r") 4291 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 4292 (const_int 23)) 4293 (match_operand:SI 2 "register_operand" "0"))) 4294 (clobber (match_scratch:SI 3 "=&r"))] 4295 "TARGET_H8300H || TARGET_H8300S" 4296 "#") 4297 4298(define_split 4299 [(set (match_operand:SI 0 "register_operand" "") 4300 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "") 4301 (const_int 23)) 4302 (match_dup 0))) 4303 (clobber (match_operand:SI 2 "register_operand" ""))] 4304 "(TARGET_H8300H || TARGET_H8300S) 4305 && epilogue_completed 4306 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 4307 && REGNO (operands[0]) != REGNO (operands[1])" 4308 [(parallel [(set (match_dup 3) 4309 (ashift:HI (match_dup 3) 4310 (const_int 7))) 4311 (clobber (scratch:QI))]) 4312 (set (match_dup 0) 4313 (ior:SI (ashift:SI (match_dup 1) 4314 (const_int 16)) 4315 (match_dup 0)))] 4316 { 4317 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1])); 4318 }) 4319 4320(define_split 4321 [(set (match_operand:SI 0 "register_operand" "") 4322 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "") 4323 (const_int 23)) 4324 (match_dup 0))) 4325 (clobber (match_operand:SI 2 "register_operand" ""))] 4326 "(TARGET_H8300H || TARGET_H8300S) 4327 && epilogue_completed 4328 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 4329 && REGNO (operands[0]) != REGNO (operands[1]))" 4330 [(set (match_dup 2) 4331 (match_dup 1)) 4332 (parallel [(set (match_dup 3) 4333 (ashift:HI (match_dup 3) 4334 (const_int 7))) 4335 (clobber (scratch:QI))]) 4336 (set (match_dup 0) 4337 (ior:SI (ashift:SI (match_dup 2) 4338 (const_int 16)) 4339 (match_dup 0)))] 4340 { 4341 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2])); 4342 }) 4343 4344(define_insn "*iorsi2_and_1_lshiftrt_1" 4345 [(set (match_operand:SI 0 "register_operand" "=r") 4346 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0") 4347 (const_int 1)) 4348 (lshiftrt:SI (match_dup 1) 4349 (const_int 1))))] 4350 "TARGET_H8300H || TARGET_H8300S" 4351 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0" 4352 [(set_attr "length" "6")]) 4353 4354(define_insn_and_split "*iorsi3_ashift_16_ashift_24" 4355 [(set (match_operand:SI 0 "register_operand" "=r") 4356 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") 4357 (const_int 16)) 4358 (ashift:SI (match_operand:SI 2 "register_operand" "r") 4359 (const_int 24))))] 4360 "TARGET_H8300H || TARGET_H8300S" 4361 "#" 4362 "&& reload_completed" 4363 [(set (match_dup 3) 4364 (ior:HI (ashift:HI (match_dup 4) 4365 (const_int 8)) 4366 (match_dup 3))) 4367 (parallel [(set (match_dup 0) 4368 (ashift:SI (match_dup 0) 4369 (const_int 16))) 4370 (clobber (scratch:QI))])] 4371 { 4372 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 4373 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2])); 4374 }) 4375 4376(define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem" 4377 [(set (match_operand:SI 0 "register_operand" "=&r") 4378 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0) 4379 (const_int 16)) 4380 (const_int 16711680)) 4381 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0) 4382 (const_int 24))))] 4383 "TARGET_H8300H || TARGET_H8300S" 4384 "#" 4385 "&& reload_completed" 4386 [(set (match_dup 3) 4387 (ior:HI (zero_extend:HI (match_dup 1)) 4388 (ashift:HI (subreg:HI (match_dup 2) 0) 4389 (const_int 8)))) 4390 (parallel [(set (match_dup 0) 4391 (ashift:SI (match_dup 0) 4392 (const_int 16))) 4393 (clobber (scratch:QI))])] 4394 { 4395 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 4396 }) 4397 4398;; Used to add the exponent of a float. 4399 4400(define_insn "*addsi3_shift" 4401 [(set (match_operand:SI 0 "register_operand" "=r") 4402 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") 4403 (const_int 8388608)) 4404 (match_operand:SI 2 "register_operand" "0"))) 4405 (clobber (match_scratch:SI 3 "=&r"))] 4406 "TARGET_H8300H || TARGET_H8300S" 4407 "#") 4408 4409(define_split 4410 [(set (match_operand:SI 0 "register_operand" "") 4411 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "") 4412 (const_int 8388608)) 4413 (match_dup 0))) 4414 (clobber (match_operand:SI 2 "register_operand" ""))] 4415 "(TARGET_H8300H || TARGET_H8300S) 4416 && epilogue_completed 4417 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 4418 && REGNO (operands[0]) != REGNO (operands[1])" 4419 [(parallel [(set (match_dup 3) 4420 (ashift:HI (match_dup 3) 4421 (const_int 7))) 4422 (clobber (scratch:QI))]) 4423 (set (match_dup 0) 4424 (plus:SI (mult:SI (match_dup 1) 4425 (const_int 65536)) 4426 (match_dup 0)))] 4427 { 4428 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1])); 4429 }) 4430 4431(define_split 4432 [(set (match_operand:SI 0 "register_operand" "") 4433 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "") 4434 (const_int 8388608)) 4435 (match_dup 0))) 4436 (clobber (match_operand:SI 2 "register_operand" ""))] 4437 "(TARGET_H8300H || TARGET_H8300S) 4438 && epilogue_completed 4439 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 4440 && REGNO (operands[0]) != REGNO (operands[1]))" 4441 [(set (match_dup 2) 4442 (match_dup 1)) 4443 (parallel [(set (match_dup 3) 4444 (ashift:HI (match_dup 3) 4445 (const_int 7))) 4446 (clobber (scratch:QI))]) 4447 (set (match_dup 0) 4448 (plus:SI (mult:SI (match_dup 2) 4449 (const_int 65536)) 4450 (match_dup 0)))] 4451 { 4452 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2])); 4453 }) 4454 4455;; ashift:SI 4456 4457(define_insn_and_split "*ashiftsi_sextqi_7" 4458 [(set (match_operand:SI 0 "register_operand" "=r") 4459 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0")) 4460 (const_int 7)))] 4461 "TARGET_H8300H || TARGET_H8300S" 4462 "#" 4463 "&& reload_completed" 4464 [(parallel [(set (match_dup 2) 4465 (ashift:HI (match_dup 2) 4466 (const_int 8))) 4467 (clobber (scratch:QI))]) 4468 (set (match_dup 0) 4469 (sign_extend:SI (match_dup 2))) 4470 (parallel [(set (match_dup 0) 4471 (ashiftrt:SI (match_dup 0) 4472 (const_int 1))) 4473 (clobber (scratch:QI))])] 4474 { 4475 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); 4476 }) 4477 4478;; Storing a part of HImode to QImode. 4479 4480(define_insn "" 4481 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 4482 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r") 4483 (const_int 8)) 1))] 4484 "" 4485 "mov.b\\t%t1,%R0" 4486 [(set_attr "cc" "set_znv") 4487 (set_attr "length" "8")]) 4488 4489;; Storing a part of SImode to QImode. 4490 4491(define_insn "" 4492 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 4493 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 4494 (const_int 8)) 3))] 4495 "" 4496 "mov.b\\t%x1,%R0" 4497 [(set_attr "cc" "set_znv") 4498 (set_attr "length" "8")]) 4499 4500(define_insn "" 4501 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 4502 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 4503 (const_int 16)) 3)) 4504 (clobber (match_scratch:SI 2 "=&r"))] 4505 "TARGET_H8300H || TARGET_H8300S" 4506 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0" 4507 [(set_attr "cc" "set_znv") 4508 (set_attr "length" "10")]) 4509 4510(define_insn "" 4511 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 4512 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 4513 (const_int 24)) 3)) 4514 (clobber (match_scratch:SI 2 "=&r"))] 4515 "TARGET_H8300H || TARGET_H8300S" 4516 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0" 4517 [(set_attr "cc" "set_znv") 4518 (set_attr "length" "10")]) 4519 4520(define_insn_and_split "" 4521 [(set (pc) 4522 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0) 4523 (const_int 1) 4524 (const_int 7)) 4525 (const_int 0)) 4526 (label_ref (match_operand 1 "" "")) 4527 (pc)))] 4528 "" 4529 "#" 4530 "" 4531 [(set (cc0) (compare (match_dup 0) 4532 (const_int 0))) 4533 (set (pc) 4534 (if_then_else (ge (cc0) 4535 (const_int 0)) 4536 (label_ref (match_dup 1)) 4537 (pc)))] 4538 "") 4539 4540(define_insn_and_split "" 4541 [(set (pc) 4542 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0) 4543 (const_int 1) 4544 (const_int 7)) 4545 (const_int 0)) 4546 (label_ref (match_operand 1 "" "")) 4547 (pc)))] 4548 "" 4549 "#" 4550 "" 4551 [(set (cc0) (compare (match_dup 0) 4552 (const_int 0))) 4553 (set (pc) 4554 (if_then_else (lt (cc0) 4555 (const_int 0)) 4556 (label_ref (match_dup 1)) 4557 (pc)))] 4558 "") 4559 4560;; ----------------------------------------------------------------- 4561;; PEEPHOLE PATTERNS 4562;; ----------------------------------------------------------------- 4563 4564;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B. 4565 4566(define_peephole2 4567 [(parallel [(set (match_operand:HI 0 "register_operand" "") 4568 (lshiftrt:HI (match_dup 0) 4569 (match_operand:HI 1 "const_int_operand" ""))) 4570 (clobber (match_operand:HI 2 "" ""))]) 4571 (set (match_dup 0) 4572 (and:HI (match_dup 0) 4573 (match_operand:HI 3 "const_int_operand" "")))] 4574 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))" 4575 [(set (match_dup 0) 4576 (and:HI (match_dup 0) 4577 (const_int 255))) 4578 (parallel [(set (match_dup 0) 4579 (lshiftrt:HI (match_dup 0) (match_dup 1))) 4580 (clobber (match_dup 2))])] 4581 "") 4582 4583;; Convert (A << B) & C to (A & 255) << B if C == 255 << B. 4584 4585(define_peephole2 4586 [(parallel [(set (match_operand:HI 0 "register_operand" "") 4587 (ashift:HI (match_dup 0) 4588 (match_operand:HI 1 "const_int_operand" ""))) 4589 (clobber (match_operand:HI 2 "" ""))]) 4590 (set (match_dup 0) 4591 (and:HI (match_dup 0) 4592 (match_operand:HI 3 "const_int_operand" "")))] 4593 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))" 4594 [(set (match_dup 0) 4595 (and:HI (match_dup 0) 4596 (const_int 255))) 4597 (parallel [(set (match_dup 0) 4598 (ashift:HI (match_dup 0) (match_dup 1))) 4599 (clobber (match_dup 2))])] 4600 "") 4601 4602;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B. 4603 4604(define_peephole2 4605 [(parallel [(set (match_operand:SI 0 "register_operand" "") 4606 (lshiftrt:SI (match_dup 0) 4607 (match_operand:SI 1 "const_int_operand" ""))) 4608 (clobber (match_operand:SI 2 "" ""))]) 4609 (set (match_dup 0) 4610 (and:SI (match_dup 0) 4611 (match_operand:SI 3 "const_int_operand" "")))] 4612 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))" 4613 [(set (match_dup 0) 4614 (and:SI (match_dup 0) 4615 (const_int 255))) 4616 (parallel [(set (match_dup 0) 4617 (lshiftrt:SI (match_dup 0) (match_dup 1))) 4618 (clobber (match_dup 2))])] 4619 "") 4620 4621;; Convert (A << B) & C to (A & 255) << B if C == 255 << B. 4622 4623(define_peephole2 4624 [(parallel [(set (match_operand:SI 0 "register_operand" "") 4625 (ashift:SI (match_dup 0) 4626 (match_operand:SI 1 "const_int_operand" ""))) 4627 (clobber (match_operand:SI 2 "" ""))]) 4628 (set (match_dup 0) 4629 (and:SI (match_dup 0) 4630 (match_operand:SI 3 "const_int_operand" "")))] 4631 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))" 4632 [(set (match_dup 0) 4633 (and:SI (match_dup 0) 4634 (const_int 255))) 4635 (parallel [(set (match_dup 0) 4636 (ashift:SI (match_dup 0) (match_dup 1))) 4637 (clobber (match_dup 2))])] 4638 "") 4639 4640;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B. 4641 4642(define_peephole2 4643 [(parallel [(set (match_operand:SI 0 "register_operand" "") 4644 (lshiftrt:SI (match_dup 0) 4645 (match_operand:SI 1 "const_int_operand" ""))) 4646 (clobber (match_operand:SI 2 "" ""))]) 4647 (set (match_dup 0) 4648 (and:SI (match_dup 0) 4649 (match_operand:SI 3 "const_int_operand" "")))] 4650 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))" 4651 [(set (match_dup 0) 4652 (and:SI (match_dup 0) 4653 (const_int 65535))) 4654 (parallel [(set (match_dup 0) 4655 (lshiftrt:SI (match_dup 0) (match_dup 1))) 4656 (clobber (match_dup 2))])] 4657 "") 4658 4659;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B. 4660 4661(define_peephole2 4662 [(parallel [(set (match_operand:SI 0 "register_operand" "") 4663 (ashift:SI (match_dup 0) 4664 (match_operand:SI 1 "const_int_operand" ""))) 4665 (clobber (match_operand:SI 2 "" ""))]) 4666 (set (match_dup 0) 4667 (and:SI (match_dup 0) 4668 (match_operand:SI 3 "const_int_operand" "")))] 4669 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))" 4670 [(set (match_dup 0) 4671 (and:SI (match_dup 0) 4672 (const_int 65535))) 4673 (parallel [(set (match_dup 0) 4674 (ashift:SI (match_dup 0) (match_dup 1))) 4675 (clobber (match_dup 2))])] 4676 "") 4677 4678;; Convert a QImode push into an SImode push so that the 4679;; define_peephole2 below can cram multiple pushes into one stm.l. 4680 4681(define_peephole2 4682 [(parallel [(set (reg:SI SP_REG) 4683 (plus:SI (reg:SI SP_REG) (const_int -4))) 4684 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3))) 4685 (match_operand:QI 0 "register_operand" ""))])] 4686 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" 4687 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4688 (match_dup 0))] 4689 { 4690 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); 4691 }) 4692 4693(define_peephole2 4694 [(parallel [(set (reg:HI SP_REG) 4695 (plus:HI (reg:HI SP_REG) (const_int -4))) 4696 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3))) 4697 (match_operand:QI 0 "register_operand" ""))])] 4698 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" 4699 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4700 (match_dup 0))] 4701 { 4702 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); 4703 }) 4704 4705;; Convert a HImode push into an SImode push so that the 4706;; define_peephole2 below can cram multiple pushes into one stm.l. 4707 4708(define_peephole2 4709 [(parallel [(set (reg:SI SP_REG) 4710 (plus:SI (reg:SI SP_REG) (const_int -4))) 4711 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2))) 4712 (match_operand:HI 0 "register_operand" ""))])] 4713 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" 4714 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4715 (match_dup 0))] 4716 { 4717 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); 4718 }) 4719 4720(define_peephole2 4721 [(parallel [(set (reg:HI SP_REG) 4722 (plus:HI (reg:HI SP_REG) (const_int -4))) 4723 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2))) 4724 (match_operand:HI 0 "register_operand" ""))])] 4725 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" 4726 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4727 (match_dup 0))] 4728 { 4729 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0])); 4730 }) 4731 4732;; Cram four pushes into stm.l. 4733 4734(define_peephole2 4735 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4736 (match_operand:SI 0 "register_operand" "")) 4737 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4738 (match_operand:SI 1 "register_operand" "")) 4739 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4740 (match_operand:SI 2 "register_operand" "")) 4741 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4742 (match_operand:SI 3 "register_operand" ""))] 4743 "TARGET_H8300S && !TARGET_NORMAL_MODE 4744 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS 4745 && REGNO (operands[1]) == REGNO (operands[0]) + 1 4746 && REGNO (operands[2]) == REGNO (operands[0]) + 2 4747 && REGNO (operands[3]) == REGNO (operands[0]) + 3 4748 && (TARGET_H8300SX || REGNO (operands[0]) == 0))" 4749 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4))) 4750 (match_dup 0)) 4751 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8))) 4752 (match_dup 1)) 4753 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12))) 4754 (match_dup 2)) 4755 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16))) 4756 (match_dup 3)) 4757 (set (reg:SI SP_REG) 4758 (plus:SI (reg:SI SP_REG) 4759 (const_int -16)))])] 4760 "") 4761 4762(define_peephole2 4763 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4764 (match_operand:SI 0 "register_operand" "")) 4765 (set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4766 (match_operand:SI 1 "register_operand" "")) 4767 (set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4768 (match_operand:SI 2 "register_operand" "")) 4769 (set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4770 (match_operand:SI 3 "register_operand" ""))] 4771 "TARGET_H8300S && TARGET_NORMAL_MODE 4772 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS 4773 && REGNO (operands[1]) == REGNO (operands[0]) + 1 4774 && REGNO (operands[2]) == REGNO (operands[0]) + 2 4775 && REGNO (operands[3]) == REGNO (operands[0]) + 3 4776 && (TARGET_H8300SX || REGNO (operands[0]) == 0))" 4777 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4))) 4778 (match_dup 0)) 4779 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8))) 4780 (match_dup 1)) 4781 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12))) 4782 (match_dup 2)) 4783 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16))) 4784 (match_dup 3)) 4785 (set (reg:HI SP_REG) 4786 (plus:HI (reg:HI SP_REG) 4787 (const_int -16)))])] 4788 "") 4789 4790;; Cram three pushes into stm.l. 4791 4792(define_peephole2 4793 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4794 (match_operand:SI 0 "register_operand" "")) 4795 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4796 (match_operand:SI 1 "register_operand" "")) 4797 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4798 (match_operand:SI 2 "register_operand" ""))] 4799 "TARGET_H8300S && !TARGET_NORMAL_MODE 4800 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS 4801 && REGNO (operands[1]) == REGNO (operands[0]) + 1 4802 && REGNO (operands[2]) == REGNO (operands[0]) + 2 4803 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))" 4804 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4))) 4805 (match_dup 0)) 4806 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8))) 4807 (match_dup 1)) 4808 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12))) 4809 (match_dup 2)) 4810 (set (reg:SI SP_REG) 4811 (plus:SI (reg:SI SP_REG) 4812 (const_int -12)))])] 4813 "") 4814 4815(define_peephole2 4816 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4817 (match_operand:SI 0 "register_operand" "")) 4818 (set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4819 (match_operand:SI 1 "register_operand" "")) 4820 (set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4821 (match_operand:SI 2 "register_operand" ""))] 4822 "TARGET_H8300S && TARGET_NORMAL_MODE 4823 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS 4824 && REGNO (operands[1]) == REGNO (operands[0]) + 1 4825 && REGNO (operands[2]) == REGNO (operands[0]) + 2 4826 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))" 4827 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4))) 4828 (match_dup 0)) 4829 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8))) 4830 (match_dup 1)) 4831 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12))) 4832 (match_dup 2)) 4833 (set (reg:HI SP_REG) 4834 (plus:HI (reg:HI SP_REG) 4835 (const_int -12)))])] 4836 "") 4837 4838;; Cram two pushes into stm.l. 4839 4840(define_peephole2 4841 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4842 (match_operand:SI 0 "register_operand" "")) 4843 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4844 (match_operand:SI 1 "register_operand" ""))] 4845 "TARGET_H8300S && !TARGET_NORMAL_MODE 4846 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS 4847 && REGNO (operands[1]) == REGNO (operands[0]) + 1 4848 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))" 4849 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4))) 4850 (match_dup 0)) 4851 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8))) 4852 (match_dup 1)) 4853 (set (reg:SI SP_REG) 4854 (plus:SI (reg:SI SP_REG) 4855 (const_int -8)))])] 4856 "") 4857 4858(define_peephole2 4859 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4860 (match_operand:SI 0 "register_operand" "")) 4861 (set (mem:SI (pre_dec:HI (reg:HI SP_REG))) 4862 (match_operand:SI 1 "register_operand" ""))] 4863 "TARGET_H8300S && TARGET_NORMAL_MODE 4864 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS 4865 && REGNO (operands[1]) == REGNO (operands[0]) + 1 4866 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))" 4867 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4))) 4868 (match_dup 0)) 4869 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8))) 4870 (match_dup 1)) 4871 (set (reg:HI SP_REG) 4872 (plus:HI (reg:HI SP_REG) 4873 (const_int -8)))])] 4874 "") 4875 4876;; Turn 4877;; 4878;; mov.w #2,r0 4879;; add.w r7,r0 (6 bytes) 4880;; 4881;; into 4882;; 4883;; mov.w r7,r0 4884;; adds #2,r0 (4 bytes) 4885 4886(define_peephole2 4887 [(set (match_operand:HI 0 "register_operand" "") 4888 (match_operand:HI 1 "const_int_operand" "")) 4889 (set (match_dup 0) 4890 (plus:HI (match_dup 0) 4891 (match_operand:HI 2 "register_operand" "")))] 4892 "REG_P (operands[0]) && REG_P (operands[2]) 4893 && REGNO (operands[0]) != REGNO (operands[2]) 4894 && (satisfies_constraint_J (operands[1]) 4895 || satisfies_constraint_L (operands[1]) 4896 || satisfies_constraint_N (operands[1]))" 4897 [(set (match_dup 0) 4898 (match_dup 2)) 4899 (set (match_dup 0) 4900 (plus:HI (match_dup 0) 4901 (match_dup 1)))] 4902 "") 4903 4904;; Turn 4905;; 4906;; sub.l er0,er0 4907;; add.b #4,r0l 4908;; add.l er7,er0 (6 bytes) 4909;; 4910;; into 4911;; 4912;; mov.l er7,er0 4913;; adds #4,er0 (4 bytes) 4914 4915(define_peephole2 4916 [(set (match_operand:SI 0 "register_operand" "") 4917 (match_operand:SI 1 "const_int_operand" "")) 4918 (set (match_dup 0) 4919 (plus:SI (match_dup 0) 4920 (match_operand:SI 2 "register_operand" "")))] 4921 "(TARGET_H8300H || TARGET_H8300S) 4922 && REG_P (operands[0]) && REG_P (operands[2]) 4923 && REGNO (operands[0]) != REGNO (operands[2]) 4924 && (satisfies_constraint_L (operands[1]) 4925 || satisfies_constraint_N (operands[1]))" 4926 [(set (match_dup 0) 4927 (match_dup 2)) 4928 (set (match_dup 0) 4929 (plus:SI (match_dup 0) 4930 (match_dup 1)))] 4931 "") 4932 4933;; Turn 4934;; 4935;; mov.l er7,er0 4936;; add.l #10,er0 (takes 8 bytes) 4937;; 4938;; into 4939;; 4940;; sub.l er0,er0 4941;; add.b #10,r0l 4942;; add.l er7,er0 (takes 6 bytes) 4943 4944(define_peephole2 4945 [(set (match_operand:SI 0 "register_operand" "") 4946 (match_operand:SI 1 "register_operand" "")) 4947 (set (match_dup 0) 4948 (plus:SI (match_dup 0) 4949 (match_operand:SI 2 "const_int_operand" "")))] 4950 "(TARGET_H8300H || TARGET_H8300S) 4951 && REG_P (operands[0]) && REG_P (operands[1]) 4952 && REGNO (operands[0]) != REGNO (operands[1]) 4953 && !satisfies_constraint_L (operands[2]) 4954 && !satisfies_constraint_N (operands[2]) 4955 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2]) 4956 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2]) 4957 || INTVAL (operands[2]) == 0xffff 4958 || INTVAL (operands[2]) == 0xfffe)" 4959 [(set (match_dup 0) 4960 (match_dup 2)) 4961 (set (match_dup 0) 4962 (plus:SI (match_dup 0) 4963 (match_dup 1)))] 4964 "") 4965 4966;; Turn 4967;; 4968;; subs #1,er4 4969;; mov.w r4,r4 4970;; bne .L2028 4971;; 4972;; into 4973;; 4974;; dec.w #1,r4 4975;; bne .L2028 4976 4977(define_peephole2 4978 [(set (match_operand:HI 0 "register_operand" "") 4979 (plus:HI (match_dup 0) 4980 (match_operand 1 "incdec_operand" ""))) 4981 (set (cc0) (compare (match_dup 0) 4982 (const_int 0))) 4983 (set (pc) 4984 (if_then_else (match_operator 3 "eqne_operator" 4985 [(cc0) (const_int 0)]) 4986 (label_ref (match_operand 2 "" "")) 4987 (pc)))] 4988 "TARGET_H8300H || TARGET_H8300S" 4989 [(set (match_operand:HI 0 "register_operand" "") 4990 (unspec:HI [(match_dup 0) 4991 (match_dup 1)] 4992 UNSPEC_INCDEC)) 4993 (set (cc0) (compare (match_dup 0) 4994 (const_int 0))) 4995 (set (pc) 4996 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 4997 (label_ref (match_dup 2)) 4998 (pc)))] 4999 "") 5000 5001;; The SImode version of the previous pattern. 5002 5003(define_peephole2 5004 [(set (match_operand:SI 0 "register_operand" "") 5005 (plus:SI (match_dup 0) 5006 (match_operand 1 "incdec_operand" ""))) 5007 (set (cc0) (compare (match_dup 0) 5008 (const_int 0))) 5009 (set (pc) 5010 (if_then_else (match_operator 3 "eqne_operator" 5011 [(cc0) (const_int 0)]) 5012 (label_ref (match_operand 2 "" "")) 5013 (pc)))] 5014 "TARGET_H8300H || TARGET_H8300S" 5015 [(set (match_operand:SI 0 "register_operand" "") 5016 (unspec:SI [(match_dup 0) 5017 (match_dup 1)] 5018 UNSPEC_INCDEC)) 5019 (set (cc0) (compare (match_dup 0) 5020 (const_int 0))) 5021 (set (pc) 5022 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 5023 (label_ref (match_dup 2)) 5024 (pc)))] 5025 "") 5026 5027(define_peephole2 5028 [(parallel [(set (cc0) 5029 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "") 5030 (const_int 1) 5031 (const_int 7)) 5032 (const_int 0))) 5033 (clobber (scratch:QI))]) 5034 (set (pc) 5035 (if_then_else (match_operator 1 "eqne_operator" 5036 [(cc0) (const_int 0)]) 5037 (label_ref (match_operand 2 "" "")) 5038 (pc)))] 5039 "TARGET_H8300H || TARGET_H8300S" 5040 [(set (cc0) (compare (match_dup 0) 5041 (const_int 0))) 5042 (set (pc) 5043 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 5044 (label_ref (match_dup 2)) 5045 (pc)))] 5046 { 5047 operands[3] = ((GET_CODE (operands[1]) == EQ) 5048 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx) 5049 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx)); 5050 }) 5051 5052;; The next three peephole2's will try to transform 5053;; 5054;; mov.b A,r0l (or mov.l A,er0) 5055;; and.l #CST,er0 5056;; 5057;; into 5058;; 5059;; sub.l er0 5060;; mov.b A,r0l 5061;; and.b #CST,r0l (if CST is not 255) 5062 5063(define_peephole2 5064 [(set (match_operand:QI 0 "register_operand" "") 5065 (match_operand:QI 1 "general_operand" "")) 5066 (set (match_operand:SI 2 "register_operand" "") 5067 (and:SI (match_dup 2) 5068 (const_int 255)))] 5069 "(TARGET_H8300H || TARGET_H8300S) 5070 && !reg_overlap_mentioned_p (operands[2], operands[1]) 5071 && REGNO (operands[0]) == REGNO (operands[2])" 5072 [(set (match_dup 2) 5073 (const_int 0)) 5074 (set (strict_low_part (match_dup 0)) 5075 (match_dup 1))] 5076 "") 5077 5078(define_peephole2 5079 [(set (match_operand:SI 0 "register_operand" "") 5080 (match_operand:SI 1 "general_operand" "")) 5081 (set (match_dup 0) 5082 (and:SI (match_dup 0) 5083 (const_int 255)))] 5084 "(TARGET_H8300H || TARGET_H8300S) 5085 && !reg_overlap_mentioned_p (operands[0], operands[1]) 5086 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1])) 5087 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))" 5088 [(set (match_dup 0) 5089 (const_int 0)) 5090 (set (strict_low_part (match_dup 2)) 5091 (match_dup 3))] 5092 { 5093 operands[2] = gen_lowpart (QImode, operands[0]); 5094 operands[3] = gen_lowpart (QImode, operands[1]); 5095 }) 5096 5097(define_peephole2 5098 [(set (match_operand 0 "register_operand" "") 5099 (match_operand 1 "general_operand" "")) 5100 (set (match_operand:SI 2 "register_operand" "") 5101 (and:SI (match_dup 2) 5102 (match_operand:SI 3 "const_int_qi_operand" "")))] 5103 "(TARGET_H8300H || TARGET_H8300S) 5104 && (GET_MODE (operands[0]) == QImode 5105 || GET_MODE (operands[0]) == HImode 5106 || GET_MODE (operands[0]) == SImode) 5107 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 5108 && REGNO (operands[0]) == REGNO (operands[2]) 5109 && !reg_overlap_mentioned_p (operands[2], operands[1]) 5110 && !(GET_MODE (operands[1]) != QImode 5111 && GET_CODE (operands[1]) == MEM 5112 && !offsettable_memref_p (operands[1])) 5113 && !(GET_MODE (operands[1]) != QImode 5114 && GET_CODE (operands[1]) == MEM 5115 && MEM_VOLATILE_P (operands[1]))" 5116 [(set (match_dup 2) 5117 (const_int 0)) 5118 (set (strict_low_part (match_dup 4)) 5119 (match_dup 5)) 5120 (set (match_dup 2) 5121 (and:SI (match_dup 2) 5122 (match_dup 6)))] 5123 { 5124 operands[4] = gen_lowpart (QImode, operands[0]); 5125 operands[5] = gen_lowpart (QImode, operands[1]); 5126 operands[6] = GEN_INT (~0xff | INTVAL (operands[3])); 5127 }) 5128 5129(define_peephole2 5130 [(set (match_operand:SI 0 "register_operand" "") 5131 (match_operand:SI 1 "register_operand" "")) 5132 (set (match_dup 0) 5133 (and:SI (match_dup 0) 5134 (const_int 65280)))] 5135 "(TARGET_H8300H || TARGET_H8300S) 5136 && !reg_overlap_mentioned_p (operands[0], operands[1])" 5137 [(set (match_dup 0) 5138 (const_int 0)) 5139 (set (zero_extract:SI (match_dup 0) 5140 (const_int 8) 5141 (const_int 8)) 5142 (lshiftrt:SI (match_dup 1) 5143 (const_int 8)))] 5144 "") 5145 5146;; If a load of mem:SI is followed by an AND that turns off the upper 5147;; half, then we can load mem:HI instead. 5148 5149(define_peephole2 5150 [(set (match_operand:SI 0 "register_operand" "") 5151 (match_operand:SI 1 "memory_operand" "")) 5152 (set (match_dup 0) 5153 (and:SI (match_dup 0) 5154 (match_operand:SI 2 "const_int_operand" "")))] 5155 "(TARGET_H8300H || TARGET_H8300S) 5156 && !MEM_VOLATILE_P (operands[1]) 5157 && offsettable_memref_p (operands[1]) 5158 && (INTVAL (operands[2]) & ~0xffff) == 0 5159 && INTVAL (operands[2]) != 255" 5160 [(set (match_dup 3) 5161 (match_dup 4)) 5162 (set (match_dup 0) 5163 (and:SI (match_dup 0) 5164 (match_dup 2)))] 5165 { 5166 operands[3] = gen_lowpart (HImode, operands[0]); 5167 operands[4] = gen_lowpart (HImode, operands[1]); 5168 }) 5169 5170;; Convert a memory comparison to a move if there is a scratch register. 5171 5172(define_peephole2 5173 [(match_scratch:QI 1 "r") 5174 (set (cc0) 5175 (compare (match_operand:QI 0 "memory_operand" "") 5176 (const_int 0)))] 5177 "" 5178 [(set (match_dup 1) 5179 (match_dup 0)) 5180 (set (cc0) (compare (match_dup 1) 5181 (const_int 0)))] 5182 "") 5183 5184(define_peephole2 5185 [(match_scratch:HI 1 "r") 5186 (set (cc0) 5187 (compare (match_operand:HI 0 "memory_operand" "") 5188 (const_int 0)))] 5189 "TARGET_H8300H || TARGET_H8300S" 5190 [(set (match_dup 1) 5191 (match_dup 0)) 5192 (set (cc0) (compare (match_dup 1) 5193 (const_int 0)))] 5194 "") 5195 5196(define_peephole2 5197 [(match_scratch:SI 1 "r") 5198 (set (cc0) 5199 (compare (match_operand:SI 0 "memory_operand" "") 5200 (const_int 0)))] 5201 "TARGET_H8300H || TARGET_H8300S" 5202 [(set (match_dup 1) 5203 (match_dup 0)) 5204 (set (cc0) (compare (match_dup 1) 5205 (const_int 0)))] 5206 "") 5207 5208 5209;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve 5210;; the equivalent with shorter sequences. Here is the summary. Cases 5211;; are grouped for each define_peephole2. 5212;; 5213;; reg const_int use insn 5214;; -------------------------------------------------------- 5215;; dead -2 eq/ne inc.l 5216;; dead -1 eq/ne inc.l 5217;; dead 1 eq/ne dec.l 5218;; dead 2 eq/ne dec.l 5219;; 5220;; dead 1 ge/lt shar.l 5221;; dead 3 (H8S) ge/lt shar.l 5222;; 5223;; dead 1 geu/ltu shar.l 5224;; dead 3 (H8S) geu/ltu shar.l 5225;; 5226;; ---- 255 ge/lt mov.b 5227;; 5228;; ---- 255 geu/ltu mov.b 5229 5230;; Transform 5231;; 5232;; cmp.w #1,r0 5233;; bne .L1 5234;; 5235;; into 5236;; 5237;; dec.w #1,r0 5238;; bne .L1 5239 5240(define_peephole2 5241 [(set (cc0) 5242 (compare (match_operand:HI 0 "register_operand" "") 5243 (match_operand:HI 1 "incdec_operand" ""))) 5244 (set (pc) 5245 (if_then_else (match_operator 3 "eqne_operator" 5246 [(cc0) (const_int 0)]) 5247 (label_ref (match_operand 2 "" "")) 5248 (pc)))] 5249 "(TARGET_H8300H || TARGET_H8300S) 5250 && INTVAL (operands[1]) != 0 5251 && peep2_reg_dead_p (1, operands[0])" 5252 [(set (match_dup 0) 5253 (unspec:HI [(match_dup 0) 5254 (match_dup 4)] 5255 UNSPEC_INCDEC)) 5256 (set (cc0) (compare (match_dup 0) 5257 (const_int 0))) 5258 (set (pc) 5259 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 5260 (label_ref (match_dup 2)) 5261 (pc)))] 5262 { 5263 operands[4] = GEN_INT (- INTVAL (operands[1])); 5264 }) 5265 5266;; Transform 5267;; 5268;; cmp.w #1,r0 5269;; bgt .L1 5270;; 5271;; into 5272;; 5273;; shar.w r0 5274;; bgt .L1 5275 5276(define_peephole2 5277 [(set (cc0) 5278 (compare (match_operand:HI 0 "register_operand" "") 5279 (match_operand:HI 1 "const_int_operand" ""))) 5280 (set (pc) 5281 (if_then_else (match_operator 2 "gtle_operator" 5282 [(cc0) (const_int 0)]) 5283 (label_ref (match_operand 3 "" "")) 5284 (pc)))] 5285 "(TARGET_H8300H || TARGET_H8300S) 5286 && peep2_reg_dead_p (1, operands[0]) 5287 && (INTVAL (operands[1]) == 1 5288 || (TARGET_H8300S && INTVAL (operands[1]) == 3))" 5289 [(parallel [(set (match_dup 0) 5290 (ashiftrt:HI (match_dup 0) 5291 (match_dup 4))) 5292 (clobber (scratch:QI))]) 5293 (set (cc0) (compare (match_dup 0) 5294 (const_int 0))) 5295 (set (pc) 5296 (if_then_else (match_dup 2) 5297 (label_ref (match_dup 3)) 5298 (pc)))] 5299 { 5300 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); 5301 }) 5302 5303;; Transform 5304;; 5305;; cmp.w #1,r0 5306;; bhi .L1 5307;; 5308;; into 5309;; 5310;; shar.w r0 5311;; bne .L1 5312 5313(define_peephole2 5314 [(set (cc0) 5315 (compare (match_operand:HI 0 "register_operand" "") 5316 (match_operand:HI 1 "const_int_operand" ""))) 5317 (set (pc) 5318 (if_then_else (match_operator 2 "gtuleu_operator" 5319 [(cc0) (const_int 0)]) 5320 (label_ref (match_operand 3 "" "")) 5321 (pc)))] 5322 "(TARGET_H8300H || TARGET_H8300S) 5323 && peep2_reg_dead_p (1, operands[0]) 5324 && (INTVAL (operands[1]) == 1 5325 || (TARGET_H8300S && INTVAL (operands[1]) == 3))" 5326 [(parallel [(set (match_dup 0) 5327 (ashiftrt:HI (match_dup 0) 5328 (match_dup 4))) 5329 (clobber (scratch:QI))]) 5330 (set (cc0) (compare (match_dup 0) 5331 (const_int 0))) 5332 (set (pc) 5333 (if_then_else (match_dup 5) 5334 (label_ref (match_dup 3)) 5335 (pc)))] 5336 { 5337 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); 5338 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, 5339 VOIDmode, cc0_rtx, const0_rtx); 5340 }) 5341 5342;; Transform 5343;; 5344;; cmp.w #255,r0 5345;; bgt .L1 5346;; 5347;; into 5348;; 5349;; mov.b r0h,r0h 5350;; bgt .L1 5351 5352(define_peephole2 5353 [(set (cc0) 5354 (compare (match_operand:HI 0 "register_operand" "") 5355 (const_int 255))) 5356 (set (pc) 5357 (if_then_else (match_operator 1 "gtle_operator" 5358 [(cc0) (const_int 0)]) 5359 (label_ref (match_operand 2 "" "")) 5360 (pc)))] 5361 "TARGET_H8300H || TARGET_H8300S" 5362 [(set (cc0) (compare (and:HI (match_dup 0) 5363 (const_int -256)) 5364 (const_int 0))) 5365 (set (pc) 5366 (if_then_else (match_dup 1) 5367 (label_ref (match_dup 2)) 5368 (pc)))] 5369 "") 5370 5371;; Transform 5372;; 5373;; cmp.w #255,r0 5374;; bhi .L1 5375;; 5376;; into 5377;; 5378;; mov.b r0h,r0h 5379;; bne .L1 5380 5381(define_peephole2 5382 [(set (cc0) 5383 (compare (match_operand:HI 0 "register_operand" "") 5384 (const_int 255))) 5385 (set (pc) 5386 (if_then_else (match_operator 1 "gtuleu_operator" 5387 [(cc0) (const_int 0)]) 5388 (label_ref (match_operand 2 "" "")) 5389 (pc)))] 5390 "TARGET_H8300H || TARGET_H8300S" 5391 [(set (cc0) (compare (and:HI (match_dup 0) 5392 (const_int -256)) 5393 (const_int 0))) 5394 (set (pc) 5395 (if_then_else (match_dup 3) 5396 (label_ref (match_dup 2)) 5397 (pc)))] 5398 { 5399 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ, 5400 VOIDmode, cc0_rtx, const0_rtx); 5401 }) 5402 5403;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve 5404;; the equivalent with shorter sequences. Here is the summary. Cases 5405;; are grouped for each define_peephole2. 5406;; 5407;; reg const_int use insn 5408;; -------------------------------------------------------- 5409;; live -2 eq/ne copy and inc.l 5410;; live -1 eq/ne copy and inc.l 5411;; live 1 eq/ne copy and dec.l 5412;; live 2 eq/ne copy and dec.l 5413;; 5414;; dead -2 eq/ne inc.l 5415;; dead -1 eq/ne inc.l 5416;; dead 1 eq/ne dec.l 5417;; dead 2 eq/ne dec.l 5418;; 5419;; dead -131072 eq/ne inc.w and test 5420;; dead -65536 eq/ne inc.w and test 5421;; dead 65536 eq/ne dec.w and test 5422;; dead 131072 eq/ne dec.w and test 5423;; 5424;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test 5425;; dead 0x0000??00 eq/ne xor.b and test 5426;; dead 0x0000ffff eq/ne not.w and test 5427;; 5428;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l 5429;; dead 0xffff??ff eq/ne xor.b and not.l 5430;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l 5431;; dead 0x80000000 eq/ne rotl.l and dec.l 5432;; 5433;; live 1 ge/lt copy and shar.l 5434;; live 3 (H8S) ge/lt copy and shar.l 5435;; 5436;; live 1 geu/ltu copy and shar.l 5437;; live 3 (H8S) geu/ltu copy and shar.l 5438;; 5439;; dead 1 ge/lt shar.l 5440;; dead 3 (H8S) ge/lt shar.l 5441;; 5442;; dead 1 geu/ltu shar.l 5443;; dead 3 (H8S) geu/ltu shar.l 5444;; 5445;; dead 3 (H8/300H) ge/lt and.b and test 5446;; dead 7 ge/lt and.b and test 5447;; dead 15 ge/lt and.b and test 5448;; dead 31 ge/lt and.b and test 5449;; dead 63 ge/lt and.b and test 5450;; dead 127 ge/lt and.b and test 5451;; dead 255 ge/lt and.b and test 5452;; 5453;; dead 3 (H8/300H) geu/ltu and.b and test 5454;; dead 7 geu/ltu and.b and test 5455;; dead 15 geu/ltu and.b and test 5456;; dead 31 geu/ltu and.b and test 5457;; dead 63 geu/ltu and.b and test 5458;; dead 127 geu/ltu and.b and test 5459;; dead 255 geu/ltu and.b and test 5460;; 5461;; ---- 65535 ge/lt mov.w 5462;; 5463;; ---- 65535 geu/ltu mov.w 5464 5465;; Transform 5466;; 5467;; cmp.l #1,er0 5468;; beq .L1 5469;; 5470;; into 5471;; 5472;; dec.l #1,er0 5473;; beq .L1 5474 5475(define_peephole2 5476 [(set (cc0) 5477 (compare (match_operand:SI 0 "register_operand" "") 5478 (match_operand:SI 1 "incdec_operand" ""))) 5479 (set (pc) 5480 (if_then_else (match_operator 3 "eqne_operator" 5481 [(cc0) (const_int 0)]) 5482 (label_ref (match_operand 2 "" "")) 5483 (pc)))] 5484 "(TARGET_H8300H || TARGET_H8300S) 5485 && INTVAL (operands[1]) != 0 5486 && peep2_reg_dead_p (1, operands[0])" 5487 [(set (match_dup 0) 5488 (unspec:SI [(match_dup 0) 5489 (match_dup 4)] 5490 UNSPEC_INCDEC)) 5491 (set (cc0) (compare (match_dup 0) 5492 (const_int 0))) 5493 (set (pc) 5494 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 5495 (label_ref (match_dup 2)) 5496 (pc)))] 5497 { 5498 operands[4] = GEN_INT (- INTVAL (operands[1])); 5499 }) 5500 5501;; Transform 5502;; 5503;; cmp.l #65536,er0 5504;; beq .L1 5505;; 5506;; into 5507;; 5508;; dec.l #1,e0 5509;; beq .L1 5510 5511(define_peephole2 5512 [(set (cc0) 5513 (compare (match_operand:SI 0 "register_operand" "") 5514 (match_operand:SI 1 "const_int_operand" ""))) 5515 (set (pc) 5516 (if_then_else (match_operator 3 "eqne_operator" 5517 [(cc0) (const_int 0)]) 5518 (label_ref (match_operand 2 "" "")) 5519 (pc)))] 5520 "(TARGET_H8300H || TARGET_H8300S) 5521 && peep2_reg_dead_p (1, operands[0]) 5522 && (INTVAL (operands[1]) == -131072 5523 || INTVAL (operands[1]) == -65536 5524 || INTVAL (operands[1]) == 65536 5525 || INTVAL (operands[1]) == 131072)" 5526 [(set (match_dup 0) 5527 (plus:SI (match_dup 0) 5528 (match_dup 4))) 5529 (set (cc0) (compare (match_dup 0) 5530 (const_int 0))) 5531 (set (pc) 5532 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 5533 (label_ref (match_dup 2)) 5534 (pc)))] 5535 { 5536 operands[4] = GEN_INT (- INTVAL (operands[1])); 5537 }) 5538 5539;; Transform 5540;; 5541;; cmp.l #100,er0 5542;; beq .L1 5543;; 5544;; into 5545;; 5546;; xor.b #100,er0 5547;; mov.l er0,er0 5548;; beq .L1 5549 5550(define_peephole2 5551 [(set (cc0) 5552 (compare (match_operand:SI 0 "register_operand" "") 5553 (match_operand:SI 1 "const_int_operand" ""))) 5554 (set (pc) 5555 (if_then_else (match_operator 3 "eqne_operator" 5556 [(cc0) (const_int 0)]) 5557 (label_ref (match_operand 2 "" "")) 5558 (pc)))] 5559 "(TARGET_H8300H || TARGET_H8300S) 5560 && peep2_reg_dead_p (1, operands[0]) 5561 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1]) 5562 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1]) 5563 || INTVAL (operands[1]) == 0x0000ffff) 5564 && INTVAL (operands[1]) != 0 5565 && INTVAL (operands[1]) != 1 5566 && INTVAL (operands[1]) != 2" 5567 [(set (match_dup 0) 5568 (xor:SI (match_dup 0) 5569 (match_dup 1))) 5570 (set (cc0) (compare (match_dup 0) 5571 (const_int 0))) 5572 (set (pc) 5573 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 5574 (label_ref (match_dup 2)) 5575 (pc)))] 5576 "") 5577 5578;; Transform 5579;; 5580;; cmp.l #-100,er0 5581;; beq .L1 5582;; 5583;; into 5584;; 5585;; xor.b #99,er0 5586;; not.l er0 5587;; beq .L1 5588 5589(define_peephole2 5590 [(set (cc0) 5591 (compare (match_operand:SI 0 "register_operand" "") 5592 (match_operand:SI 1 "const_int_operand" ""))) 5593 (set (pc) 5594 (if_then_else (match_operator 3 "eqne_operator" 5595 [(cc0) (const_int 0)]) 5596 (label_ref (match_operand 2 "" "")) 5597 (pc)))] 5598 "(TARGET_H8300H || TARGET_H8300S) 5599 && peep2_reg_dead_p (1, operands[0]) 5600 && ((INTVAL (operands[1]) | 0x00ff) == -1 5601 || (INTVAL (operands[1]) | 0xff00) == -1) 5602 && INTVAL (operands[1]) != -1 5603 && INTVAL (operands[1]) != -2" 5604 [(set (match_dup 0) 5605 (xor:SI (match_dup 0) 5606 (match_dup 4))) 5607 (set (match_dup 0) 5608 (not:SI (match_dup 0))) 5609 (set (cc0) (compare (match_dup 0) 5610 (const_int 0))) 5611 (set (pc) 5612 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 5613 (label_ref (match_dup 2)) 5614 (pc)))] 5615 { 5616 operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1); 5617 }) 5618 5619;; Transform 5620;; 5621;; cmp.l #-2147483648,er0 5622;; beq .L1 5623;; 5624;; into 5625;; 5626;; rotl.l er0 5627;; dec.l #1,er0 5628;; beq .L1 5629 5630(define_peephole2 5631 [(set (cc0) 5632 (compare (match_operand:SI 0 "register_operand" "") 5633 (match_operand:SI 1 "const_int_operand" ""))) 5634 (set (pc) 5635 (if_then_else (match_operator 3 "eqne_operator" 5636 [(cc0) (const_int 0)]) 5637 (label_ref (match_operand 2 "" "")) 5638 (pc)))] 5639 "(TARGET_H8300H || TARGET_H8300S) 5640 && peep2_reg_dead_p (1, operands[0]) 5641 && (INTVAL (operands[1]) == -2147483647 - 1 5642 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))" 5643 [(set (match_dup 0) 5644 (rotate:SI (match_dup 0) 5645 (match_dup 4))) 5646 (set (match_dup 0) 5647 (unspec:SI [(match_dup 0) 5648 (const_int -1)] 5649 UNSPEC_INCDEC)) 5650 (set (cc0) (compare (match_dup 0) 5651 (const_int 0))) 5652 (set (pc) 5653 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 5654 (label_ref (match_dup 2)) 5655 (pc)))] 5656 { 5657 operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2); 5658 }) 5659 5660;; Transform 5661;; 5662;; cmp.l #1,er0 5663;; bgt .L1 5664;; 5665;; into 5666;; 5667;; mov.l er0,er1 5668;; shar.l er1 5669;; bgt .L1 5670 5671;; We avoid this transformation if we see more than one copy of the 5672;; same compare insn immediately before this one. 5673 5674(define_peephole2 5675 [(match_scratch:SI 4 "r") 5676 (set (cc0) 5677 (compare (match_operand:SI 0 "register_operand" "") 5678 (match_operand:SI 1 "const_int_operand" ""))) 5679 (set (pc) 5680 (if_then_else (match_operator 2 "gtle_operator" 5681 [(cc0) (const_int 0)]) 5682 (label_ref (match_operand 3 "" "")) 5683 (pc)))] 5684 "(TARGET_H8300H || TARGET_H8300S) 5685 && !peep2_reg_dead_p (1, operands[0]) 5686 && (INTVAL (operands[1]) == 1 5687 || (TARGET_H8300S && INTVAL (operands[1]) == 3)) 5688 && !same_cmp_preceding_p (insn)" 5689 [(set (match_dup 4) 5690 (match_dup 0)) 5691 (parallel [(set (match_dup 4) 5692 (ashiftrt:SI (match_dup 4) 5693 (match_dup 5))) 5694 (clobber (scratch:QI))]) 5695 (set (cc0) (compare (match_dup 4) 5696 (const_int 0))) 5697 (set (pc) 5698 (if_then_else (match_dup 2) 5699 (label_ref (match_dup 3)) 5700 (pc)))] 5701 { 5702 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); 5703 }) 5704 5705;; Transform 5706;; 5707;; cmp.l #1,er0 5708;; bhi .L1 5709;; 5710;; into 5711;; 5712;; mov.l er0,er1 5713;; shar.l er1 5714;; bne .L1 5715 5716;; We avoid this transformation if we see more than one copy of the 5717;; same compare insn immediately before this one. 5718 5719(define_peephole2 5720 [(match_scratch:SI 4 "r") 5721 (set (cc0) 5722 (compare (match_operand:SI 0 "register_operand" "") 5723 (match_operand:SI 1 "const_int_operand" ""))) 5724 (set (pc) 5725 (if_then_else (match_operator 2 "gtuleu_operator" 5726 [(cc0) (const_int 0)]) 5727 (label_ref (match_operand 3 "" "")) 5728 (pc)))] 5729 "(TARGET_H8300H || TARGET_H8300S) 5730 && !peep2_reg_dead_p (1, operands[0]) 5731 && (INTVAL (operands[1]) == 1 5732 || (TARGET_H8300S && INTVAL (operands[1]) == 3)) 5733 && !same_cmp_preceding_p (insn)" 5734 [(set (match_dup 4) 5735 (match_dup 0)) 5736 (parallel [(set (match_dup 4) 5737 (ashiftrt:SI (match_dup 4) 5738 (match_dup 5))) 5739 (clobber (scratch:QI))]) 5740 (set (cc0) (compare (match_dup 4) 5741 (const_int 0))) 5742 (set (pc) 5743 (if_then_else (match_dup 6) 5744 (label_ref (match_dup 3)) 5745 (pc)))] 5746 { 5747 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); 5748 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, 5749 VOIDmode, cc0_rtx, const0_rtx); 5750 }) 5751 5752;; Transform 5753;; 5754;; cmp.l #1,er0 5755;; bgt .L1 5756;; 5757;; into 5758;; 5759;; shar.l er0 5760;; bgt .L1 5761 5762(define_peephole2 5763 [(set (cc0) 5764 (compare (match_operand:SI 0 "register_operand" "") 5765 (match_operand:SI 1 "const_int_operand" ""))) 5766 (set (pc) 5767 (if_then_else (match_operator 2 "gtle_operator" 5768 [(cc0) (const_int 0)]) 5769 (label_ref (match_operand 3 "" "")) 5770 (pc)))] 5771 "(TARGET_H8300H || TARGET_H8300S) 5772 && peep2_reg_dead_p (1, operands[0]) 5773 && (INTVAL (operands[1]) == 1 5774 || (TARGET_H8300S && INTVAL (operands[1]) == 3))" 5775 [(parallel [(set (match_dup 0) 5776 (ashiftrt:SI (match_dup 0) 5777 (match_dup 4))) 5778 (clobber (scratch:QI))]) 5779 (set (cc0) (compare (match_dup 0) 5780 (const_int 0))) 5781 (set (pc) 5782 (if_then_else (match_dup 2) 5783 (label_ref (match_dup 3)) 5784 (pc)))] 5785 { 5786 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); 5787 }) 5788 5789;; Transform 5790;; 5791;; cmp.l #1,er0 5792;; bhi .L1 5793;; 5794;; into 5795;; 5796;; shar.l er0 5797;; bne .L1 5798 5799(define_peephole2 5800 [(set (cc0) 5801 (compare (match_operand:SI 0 "register_operand" "") 5802 (match_operand:SI 1 "const_int_operand" ""))) 5803 (set (pc) 5804 (if_then_else (match_operator 2 "gtuleu_operator" 5805 [(cc0) (const_int 0)]) 5806 (label_ref (match_operand 3 "" "")) 5807 (pc)))] 5808 "(TARGET_H8300H || TARGET_H8300S) 5809 && peep2_reg_dead_p (1, operands[0]) 5810 && (INTVAL (operands[1]) == 1 5811 || (TARGET_H8300S && INTVAL (operands[1]) == 3))" 5812 [(parallel [(set (match_dup 0) 5813 (ashiftrt:SI (match_dup 0) 5814 (match_dup 4))) 5815 (clobber (scratch:QI))]) 5816 (set (cc0) (compare (match_dup 0) 5817 (const_int 0))) 5818 (set (pc) 5819 (if_then_else (match_dup 5) 5820 (label_ref (match_dup 3)) 5821 (pc)))] 5822 { 5823 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); 5824 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, 5825 VOIDmode, cc0_rtx, const0_rtx); 5826 }) 5827 5828;; Transform 5829;; 5830;; cmp.l #15,er0 5831;; bgt .L1 5832;; 5833;; into 5834;; 5835;; and #240,r0l 5836;; mov.l er0,er0 5837;; bgt .L1 5838 5839(define_peephole2 5840 [(set (cc0) 5841 (compare (match_operand:SI 0 "register_operand" "") 5842 (match_operand:SI 1 "const_int_operand" ""))) 5843 (set (pc) 5844 (if_then_else (match_operator 2 "gtle_operator" 5845 [(cc0) (const_int 0)]) 5846 (label_ref (match_operand 3 "" "")) 5847 (pc)))] 5848 "(TARGET_H8300H || TARGET_H8300S) 5849 && peep2_reg_dead_p (1, operands[0]) 5850 && ((TARGET_H8300H && INTVAL (operands[1]) == 3) 5851 || INTVAL (operands[1]) == 7 5852 || INTVAL (operands[1]) == 15 5853 || INTVAL (operands[1]) == 31 5854 || INTVAL (operands[1]) == 63 5855 || INTVAL (operands[1]) == 127 5856 || INTVAL (operands[1]) == 255)" 5857 [(set (match_dup 0) 5858 (and:SI (match_dup 0) 5859 (match_dup 4))) 5860 (set (cc0) (compare (match_dup 0) 5861 (const_int 0))) 5862 (set (pc) 5863 (if_then_else (match_dup 2) 5864 (label_ref (match_dup 3)) 5865 (pc)))] 5866 { 5867 operands[4] = GEN_INT (~INTVAL (operands[1])); 5868 }) 5869 5870;; Transform 5871;; 5872;; cmp.l #15,er0 5873;; bhi .L1 5874;; 5875;; into 5876;; 5877;; and #240,r0l 5878;; mov.l er0,er0 5879;; bne .L1 5880 5881(define_peephole2 5882 [(set (cc0) 5883 (compare (match_operand:SI 0 "register_operand" "") 5884 (match_operand:SI 1 "const_int_operand" ""))) 5885 (set (pc) 5886 (if_then_else (match_operator 2 "gtuleu_operator" 5887 [(cc0) (const_int 0)]) 5888 (label_ref (match_operand 3 "" "")) 5889 (pc)))] 5890 "(TARGET_H8300H || TARGET_H8300S) 5891 && peep2_reg_dead_p (1, operands[0]) 5892 && ((TARGET_H8300H && INTVAL (operands[1]) == 3) 5893 || INTVAL (operands[1]) == 7 5894 || INTVAL (operands[1]) == 15 5895 || INTVAL (operands[1]) == 31 5896 || INTVAL (operands[1]) == 63 5897 || INTVAL (operands[1]) == 127 5898 || INTVAL (operands[1]) == 255)" 5899 [(set (match_dup 0) 5900 (and:SI (match_dup 0) 5901 (match_dup 4))) 5902 (set (cc0) (compare (match_dup 0) 5903 (const_int 0))) 5904 (set (pc) 5905 (if_then_else (match_dup 5) 5906 (label_ref (match_dup 3)) 5907 (pc)))] 5908 { 5909 operands[4] = GEN_INT (~INTVAL (operands[1])); 5910 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ, 5911 VOIDmode, cc0_rtx, const0_rtx); 5912 }) 5913 5914;; Transform 5915;; 5916;; cmp.l #65535,er0 5917;; bgt .L1 5918;; 5919;; into 5920;; 5921;; mov.l e0,e0 5922;; bgt .L1 5923 5924(define_peephole2 5925 [(set (cc0) 5926 (compare (match_operand:SI 0 "register_operand" "") 5927 (const_int 65535))) 5928 (set (pc) 5929 (if_then_else (match_operator 1 "gtle_operator" 5930 [(cc0) (const_int 0)]) 5931 (label_ref (match_operand 2 "" "")) 5932 (pc)))] 5933 "TARGET_H8300H || TARGET_H8300S" 5934 [(set (cc0) (compare (and:SI (match_dup 0) 5935 (const_int -65536)) 5936 (const_int 0))) 5937 (set (pc) 5938 (if_then_else (match_dup 1) 5939 (label_ref (match_dup 2)) 5940 (pc)))] 5941 "") 5942 5943;; Transform 5944;; 5945;; cmp.l #65535,er0 5946;; bhi .L1 5947;; 5948;; into 5949;; 5950;; mov.l e0,e0 5951;; bne .L1 5952 5953(define_peephole2 5954 [(set (cc0) 5955 (compare (match_operand:SI 0 "register_operand" "") 5956 (const_int 65535))) 5957 (set (pc) 5958 (if_then_else (match_operator 1 "gtuleu_operator" 5959 [(cc0) (const_int 0)]) 5960 (label_ref (match_operand 2 "" "")) 5961 (pc)))] 5962 "TARGET_H8300H || TARGET_H8300S" 5963 [(set (cc0) (compare (and:SI (match_dup 0) 5964 (const_int -65536)) 5965 (const_int 0))) 5966 (set (pc) 5967 (if_then_else (match_dup 3) 5968 (label_ref (match_dup 2)) 5969 (pc)))] 5970 { 5971 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ, 5972 VOIDmode, cc0_rtx, const0_rtx); 5973 }) 5974 5975;; Transform 5976;; 5977;; cmp.l #1,er0 5978;; beq .L1 5979;; 5980;; into 5981;; 5982;; mov.l er0,er1 5983;; dec.l #1,er1 5984;; beq .L1 5985 5986;; We avoid this transformation if we see more than one copy of the 5987;; same compare insn. 5988 5989(define_peephole2 5990 [(match_scratch:SI 4 "r") 5991 (set (cc0) 5992 (compare (match_operand:SI 0 "register_operand" "") 5993 (match_operand:SI 1 "incdec_operand" ""))) 5994 (set (pc) 5995 (if_then_else (match_operator 3 "eqne_operator" 5996 [(cc0) (const_int 0)]) 5997 (label_ref (match_operand 2 "" "")) 5998 (pc)))] 5999 "(TARGET_H8300H || TARGET_H8300S) 6000 && INTVAL (operands[1]) != 0 6001 && !peep2_reg_dead_p (1, operands[0]) 6002 && !same_cmp_following_p (insn)" 6003 [(set (match_dup 4) 6004 (match_dup 0)) 6005 (set (match_dup 4) 6006 (unspec:SI [(match_dup 4) 6007 (match_dup 5)] 6008 UNSPEC_INCDEC)) 6009 (set (cc0) (compare (match_dup 4) 6010 (const_int 0))) 6011 (set (pc) 6012 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 6013 (label_ref (match_dup 2)) 6014 (pc)))] 6015 { 6016 operands[5] = GEN_INT (- INTVAL (operands[1])); 6017 }) 6018;; Narrow the mode of testing if possible. 6019 6020(define_peephole2 6021 [(set (match_operand:HI 0 "register_operand" "") 6022 (and:HI (match_dup 0) 6023 (match_operand:HI 1 "const_int_qi_operand" ""))) 6024 (set (cc0) (compare (match_dup 0) 6025 (const_int 0))) 6026 (set (pc) 6027 (if_then_else (match_operator 3 "eqne_operator" 6028 [(cc0) (const_int 0)]) 6029 (label_ref (match_operand 2 "" "")) 6030 (pc)))] 6031 "peep2_reg_dead_p (2, operands[0])" 6032 [(set (match_dup 4) 6033 (and:QI (match_dup 4) 6034 (match_dup 5))) 6035 (set (cc0) (compare (match_dup 4) 6036 (const_int 0))) 6037 (set (pc) 6038 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 6039 (label_ref (match_dup 2)) 6040 (pc)))] 6041 { 6042 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0])); 6043 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode); 6044 }) 6045 6046(define_peephole2 6047 [(set (match_operand:SI 0 "register_operand" "") 6048 (and:SI (match_dup 0) 6049 (match_operand:SI 1 "const_int_qi_operand" ""))) 6050 (set (cc0) (compare (match_dup 0) 6051 (const_int 0))) 6052 (set (pc) 6053 (if_then_else (match_operator 3 "eqne_operator" 6054 [(cc0) (const_int 0)]) 6055 (label_ref (match_operand 2 "" "")) 6056 (pc)))] 6057 "peep2_reg_dead_p (2, operands[0])" 6058 [(set (match_dup 4) 6059 (and:QI (match_dup 4) 6060 (match_dup 5))) 6061 (set (cc0) (compare (match_dup 4) 6062 (const_int 0))) 6063 (set (pc) 6064 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 6065 (label_ref (match_dup 2)) 6066 (pc)))] 6067 { 6068 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0])); 6069 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode); 6070 }) 6071 6072(define_peephole2 6073 [(set (match_operand:SI 0 "register_operand" "") 6074 (and:SI (match_dup 0) 6075 (match_operand:SI 1 "const_int_hi_operand" ""))) 6076 (set (cc0) (compare (match_dup 0) 6077 (const_int 0))) 6078 (set (pc) 6079 (if_then_else (match_operator 3 "eqne_operator" 6080 [(cc0) (const_int 0)]) 6081 (label_ref (match_operand 2 "" "")) 6082 (pc)))] 6083 "peep2_reg_dead_p (2, operands[0])" 6084 [(set (match_dup 4) 6085 (and:HI (match_dup 4) 6086 (match_dup 5))) 6087 (set (cc0) (compare (match_dup 4) 6088 (const_int 0))) 6089 (set (pc) 6090 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)]) 6091 (label_ref (match_dup 2)) 6092 (pc)))] 6093 { 6094 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0])); 6095 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode); 6096 }) 6097 6098(define_peephole2 6099 [(set (match_operand:SI 0 "register_operand" "") 6100 (and:SI (match_dup 0) 6101 (match_operand:SI 1 "const_int_qi_operand" ""))) 6102 (set (match_dup 0) 6103 (xor:SI (match_dup 0) 6104 (match_operand:SI 2 "const_int_qi_operand" ""))) 6105 (set (cc0) (compare (match_dup 0) 6106 (const_int 0))) 6107 (set (pc) 6108 (if_then_else (match_operator 4 "eqne_operator" 6109 [(cc0) (const_int 0)]) 6110 (label_ref (match_operand 3 "" "")) 6111 (pc)))] 6112 "peep2_reg_dead_p (3, operands[0]) 6113 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0" 6114 [(set (match_dup 5) 6115 (and:QI (match_dup 5) 6116 (match_dup 6))) 6117 (set (match_dup 5) 6118 (xor:QI (match_dup 5) 6119 (match_dup 7))) 6120 (set (cc0) (compare (match_dup 5) 6121 (const_int 0))) 6122 (set (pc) 6123 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)]) 6124 (label_ref (match_dup 3)) 6125 (pc)))] 6126 { 6127 operands[5] = gen_rtx_REG (QImode, REGNO (operands[0])); 6128 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode); 6129 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode); 6130 }) 6131 6132;; These triggers right at the end of allocation of locals in the 6133;; prologue (and possibly at other places). 6134 6135;; stack adjustment of -4, generate one push 6136;; 6137;; before : 6 bytes, 10 clocks 6138;; after : 4 bytes, 10 clocks 6139 6140(define_peephole2 6141 [(set (reg:SI SP_REG) 6142 (plus:SI (reg:SI SP_REG) 6143 (const_int -4))) 6144 (set (mem:SI (reg:SI SP_REG)) 6145 (match_operand:SI 0 "register_operand" ""))] 6146 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE 6147 && REGNO (operands[0]) != SP_REG" 6148 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 6149 (match_dup 0))] 6150 "") 6151 6152;; stack adjustment of -12, generate one push 6153;; 6154;; before : 10 bytes, 14 clocks 6155;; after : 8 bytes, 14 clocks 6156 6157(define_peephole2 6158 [(set (reg:SI SP_REG) 6159 (plus:SI (reg:SI SP_REG) 6160 (const_int -12))) 6161 (set (mem:SI (reg:SI SP_REG)) 6162 (match_operand:SI 0 "register_operand" ""))] 6163 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE 6164 && REGNO (operands[0]) != SP_REG" 6165 [(set (reg:SI SP_REG) 6166 (plus:SI (reg:SI SP_REG) 6167 (const_int -4))) 6168 (set (reg:SI SP_REG) 6169 (plus:SI (reg:SI SP_REG) 6170 (const_int -4))) 6171 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 6172 (match_dup 0))] 6173 "") 6174 6175;; Transform 6176;; 6177;; mov dst,reg 6178;; op src,reg 6179;; mov reg,dst 6180;; 6181;; into 6182;; 6183;; op src,dst 6184;; 6185;; if "reg" dies at the end of the sequence. 6186 6187(define_peephole2 6188 [(set (match_operand 0 "register_operand" "") 6189 (match_operand 1 "memory_operand" "")) 6190 (set (match_dup 0) 6191 (match_operator 2 "h8sx_binary_memory_operator" 6192 [(match_dup 0) 6193 (match_operand 3 "h8300_src_operand" "")])) 6194 (set (match_operand 4 "memory_operand" "") 6195 (match_dup 0))] 6196 "0 /* Disable because it breaks compiling fp-bit.c. */ 6197 && TARGET_H8300SX 6198 && peep2_reg_dead_p (3, operands[0]) 6199 && !reg_overlap_mentioned_p (operands[0], operands[3]) 6200 && !reg_overlap_mentioned_p (operands[0], operands[4]) 6201 && h8sx_mergeable_memrefs_p (operands[4], operands[1])" 6202 [(set (match_dup 4) 6203 (match_dup 5))] 6204 { 6205 operands[5] = shallow_copy_rtx (operands[2]); 6206 XEXP (operands[5], 0) = operands[1]; 6207 }) 6208 6209;; Transform 6210;; 6211;; mov src,reg 6212;; op reg,dst 6213;; 6214;; into 6215;; 6216;; op src,dst 6217;; 6218;; if "reg" dies in the second insn. 6219 6220(define_peephole2 6221 [(set (match_operand 0 "register_operand" "") 6222 (match_operand 1 "h8300_src_operand" "")) 6223 (set (match_operand 2 "h8300_dst_operand" "") 6224 (match_operator 3 "h8sx_binary_memory_operator" 6225 [(match_operand 4 "h8300_dst_operand" "") 6226 (match_dup 0)]))] 6227 "0 /* Disable because it breaks compiling fp-bit.c. */ 6228 && TARGET_H8300SX 6229 && peep2_reg_dead_p (2, operands[0]) 6230 && !reg_overlap_mentioned_p (operands[0], operands[4])" 6231 [(set (match_dup 2) 6232 (match_dup 5))] 6233 { 6234 operands[5] = shallow_copy_rtx (operands[3]); 6235 XEXP (operands[5], 1) = operands[1]; 6236 }) 6237 6238;; Transform 6239;; 6240;; mov dst,reg 6241;; op reg 6242;; mov reg,dst 6243;; 6244;; into 6245;; 6246;; op dst 6247;; 6248;; if "reg" dies at the end of the sequence. 6249 6250(define_peephole2 6251 [(set (match_operand 0 "register_operand" "") 6252 (match_operand 1 "memory_operand" "")) 6253 (set (match_dup 0) 6254 (match_operator 2 "h8sx_unary_memory_operator" 6255 [(match_dup 0)])) 6256 (set (match_operand 3 "memory_operand" "") 6257 (match_dup 0))] 6258 "TARGET_H8300SX 6259 && peep2_reg_dead_p (3, operands[0]) 6260 && !reg_overlap_mentioned_p (operands[0], operands[3]) 6261 && h8sx_mergeable_memrefs_p (operands[3], operands[1])" 6262 [(set (match_dup 3) 6263 (match_dup 4))] 6264 { 6265 operands[4] = shallow_copy_rtx (operands[2]); 6266 XEXP (operands[4], 0) = operands[1]; 6267 }) 6268 6269;; Transform 6270;; 6271;; mov src1,reg 6272;; cmp reg,src2 6273;; 6274;; into 6275;; 6276;; cmp src1,src2 6277;; 6278;; if "reg" dies in the comparison. 6279 6280(define_peephole2 6281 [(set (match_operand 0 "register_operand" "") 6282 (match_operand 1 "h8300_dst_operand" "")) 6283 (set (cc0) 6284 (compare (match_dup 0) 6285 (match_operand 2 "h8300_src_operand" "")))] 6286 "TARGET_H8300SX 6287 && peep2_reg_dead_p (2, operands[0]) 6288 && !reg_overlap_mentioned_p (operands[0], operands[2]) 6289 && operands[2] != const0_rtx" 6290 [(set (cc0) 6291 (compare (match_dup 1) 6292 (match_dup 2)))]) 6293 6294;; Likewise for the second operand. 6295 6296(define_peephole2 6297 [(set (match_operand 0 "register_operand" "") 6298 (match_operand 1 "h8300_src_operand" "")) 6299 (set (cc0) 6300 (compare (match_operand 2 "h8300_dst_operand" "") 6301 (match_dup 0)))] 6302 "TARGET_H8300SX 6303 && peep2_reg_dead_p (2, operands[0]) 6304 && !reg_overlap_mentioned_p (operands[0], operands[2])" 6305 [(set (cc0) 6306 (compare (match_dup 2) 6307 (match_dup 1)))]) 6308 6309;; Combine two moves. 6310 6311(define_peephole2 6312 [(set (match_operand 0 "register_operand" "") 6313 (match_operand 1 "h8300_src_operand" "")) 6314 (set (match_operand 2 "h8300_dst_operand" "") 6315 (match_dup 0))] 6316 "TARGET_H8300SX 6317 && peep2_reg_dead_p (2, operands[0]) 6318 && !reg_overlap_mentioned_p (operands[0], operands[2])" 6319 [(set (match_dup 2) 6320 (match_dup 1))]) 6321 6322 6323