1 /* Subroutines for insn-output.c for Renesas H8/300. 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 4 Free Software Foundation, Inc. 5 Contributed by Steve Chamberlain (sac@cygnus.com), 6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 GCC is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GCC; see the file COPYING3. If not see 22 <http://www.gnu.org/licenses/>. */ 23 24 #include "config.h" 25 #include "system.h" 26 #include "coretypes.h" 27 #include "tm.h" 28 #include "rtl.h" 29 #include "tree.h" 30 #include "regs.h" 31 #include "hard-reg-set.h" 32 #include "real.h" 33 #include "insn-config.h" 34 #include "conditions.h" 35 #include "output.h" 36 #include "insn-attr.h" 37 #include "flags.h" 38 #include "recog.h" 39 #include "expr.h" 40 #include "function.h" 41 #include "optabs.h" 42 #include "toplev.h" 43 #include "c-pragma.h" 44 #include "tm_p.h" 45 #include "ggc.h" 46 #include "target.h" 47 #include "target-def.h" 48 49 /* Classifies a h8300_src_operand or h8300_dst_operand. 50 51 H8OP_IMMEDIATE 52 A constant operand of some sort. 53 54 H8OP_REGISTER 55 An ordinary register. 56 57 H8OP_MEM_ABSOLUTE 58 A memory reference with a constant address. 59 60 H8OP_MEM_BASE 61 A memory reference with a register as its address. 62 63 H8OP_MEM_COMPLEX 64 Some other kind of memory reference. */ 65 enum h8300_operand_class 66 { 67 H8OP_IMMEDIATE, 68 H8OP_REGISTER, 69 H8OP_MEM_ABSOLUTE, 70 H8OP_MEM_BASE, 71 H8OP_MEM_COMPLEX, 72 NUM_H8OPS 73 }; 74 75 /* For a general two-operand instruction, element [X][Y] gives 76 the length of the opcode fields when the first operand has class 77 (X + 1) and the second has class Y. */ 78 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS]; 79 80 /* Forward declarations. */ 81 static const char *byte_reg (rtx, int); 82 static int h8300_interrupt_function_p (tree); 83 static int h8300_saveall_function_p (tree); 84 static int h8300_monitor_function_p (tree); 85 static int h8300_os_task_function_p (tree); 86 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool); 87 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT); 88 static unsigned int compute_saved_regs (void); 89 static void push (int); 90 static void pop (int); 91 static const char *cond_string (enum rtx_code); 92 static unsigned int h8300_asm_insn_count (const char *); 93 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *); 94 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *); 95 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *); 96 #ifndef OBJECT_FORMAT_ELF 97 static void h8300_asm_named_section (const char *, unsigned int, tree); 98 #endif 99 static int h8300_and_costs (rtx); 100 static int h8300_shift_costs (rtx); 101 static void h8300_push_pop (int, int, bool, bool); 102 static int h8300_stack_offset_p (rtx, int); 103 static int h8300_ldm_stm_regno (rtx, int, int, int); 104 static void h8300_reorg (void); 105 static unsigned int h8300_constant_length (rtx); 106 static unsigned int h8300_displacement_length (rtx, int); 107 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *); 108 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *); 109 static unsigned int h8300_unary_length (rtx); 110 static unsigned int h8300_short_immediate_length (rtx); 111 static unsigned int h8300_bitfield_length (rtx, rtx); 112 static unsigned int h8300_binary_length (rtx, const h8300_length_table *); 113 static bool h8300_short_move_mem_p (rtx, enum rtx_code); 114 static unsigned int h8300_move_length (rtx *, const h8300_length_table *); 115 static bool h8300_hard_regno_scratch_ok (unsigned int); 116 117 /* CPU_TYPE, says what cpu we're compiling for. */ 118 int cpu_type; 119 120 /* True if a #pragma interrupt has been seen for the current function. */ 121 static int pragma_interrupt; 122 123 /* True if a #pragma saveall has been seen for the current function. */ 124 static int pragma_saveall; 125 126 static const char *const names_big[] = 127 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }; 128 129 static const char *const names_extended[] = 130 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" }; 131 132 static const char *const names_upper_extended[] = 133 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" }; 134 135 /* Points to one of the above. */ 136 /* ??? The above could be put in an array indexed by CPU_TYPE. */ 137 const char * const *h8_reg_names; 138 139 /* Various operations needed by the following, indexed by CPU_TYPE. */ 140 141 const char *h8_push_op, *h8_pop_op, *h8_mov_op; 142 143 /* Value of MOVE_RATIO. */ 144 int h8300_move_ratio; 145 146 /* See below where shifts are handled for explanation of this enum. */ 147 148 enum shift_alg 149 { 150 SHIFT_INLINE, 151 SHIFT_ROT_AND, 152 SHIFT_SPECIAL, 153 SHIFT_LOOP 154 }; 155 156 /* Symbols of the various shifts which can be used as indices. */ 157 158 enum shift_type 159 { 160 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT 161 }; 162 163 /* Macros to keep the shift algorithm tables small. */ 164 #define INL SHIFT_INLINE 165 #define ROT SHIFT_ROT_AND 166 #define LOP SHIFT_LOOP 167 #define SPC SHIFT_SPECIAL 168 169 /* The shift algorithms for each machine, mode, shift type, and shift 170 count are defined below. The three tables below correspond to 171 QImode, HImode, and SImode, respectively. Each table is organized 172 by, in the order of indices, machine, shift type, and shift count. */ 173 174 static enum shift_alg shift_alg_qi[3][3][8] = { 175 { 176 /* TARGET_H8300 */ 177 /* 0 1 2 3 4 5 6 7 */ 178 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 179 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 180 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ 181 }, 182 { 183 /* TARGET_H8300H */ 184 /* 0 1 2 3 4 5 6 7 */ 185 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 186 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 187 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ 188 }, 189 { 190 /* TARGET_H8300S */ 191 /* 0 1 2 3 4 5 6 7 */ 192 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */ 193 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */ 194 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */ 195 } 196 }; 197 198 static enum shift_alg shift_alg_hi[3][3][16] = { 199 { 200 /* TARGET_H8300 */ 201 /* 0 1 2 3 4 5 6 7 */ 202 /* 8 9 10 11 12 13 14 15 */ 203 { INL, INL, INL, INL, INL, INL, INL, SPC, 204 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 205 { INL, INL, INL, INL, INL, LOP, LOP, SPC, 206 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 207 { INL, INL, INL, INL, INL, LOP, LOP, SPC, 208 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 209 }, 210 { 211 /* TARGET_H8300H */ 212 /* 0 1 2 3 4 5 6 7 */ 213 /* 8 9 10 11 12 13 14 15 */ 214 { INL, INL, INL, INL, INL, INL, INL, SPC, 215 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 216 { INL, INL, INL, INL, INL, INL, INL, SPC, 217 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 218 { INL, INL, INL, INL, INL, INL, INL, SPC, 219 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 220 }, 221 { 222 /* TARGET_H8300S */ 223 /* 0 1 2 3 4 5 6 7 */ 224 /* 8 9 10 11 12 13 14 15 */ 225 { INL, INL, INL, INL, INL, INL, INL, INL, 226 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 227 { INL, INL, INL, INL, INL, INL, INL, INL, 228 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 229 { INL, INL, INL, INL, INL, INL, INL, INL, 230 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 231 } 232 }; 233 234 static enum shift_alg shift_alg_si[3][3][32] = { 235 { 236 /* TARGET_H8300 */ 237 /* 0 1 2 3 4 5 6 7 */ 238 /* 8 9 10 11 12 13 14 15 */ 239 /* 16 17 18 19 20 21 22 23 */ 240 /* 24 25 26 27 28 29 30 31 */ 241 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 242 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, 243 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP, 244 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */ 245 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC, 247 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP, 248 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */ 249 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 250 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 251 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP, 252 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ 253 }, 254 { 255 /* TARGET_H8300H */ 256 /* 0 1 2 3 4 5 6 7 */ 257 /* 8 9 10 11 12 13 14 15 */ 258 /* 16 17 18 19 20 21 22 23 */ 259 /* 24 25 26 27 28 29 30 31 */ 260 { INL, INL, INL, INL, INL, LOP, LOP, LOP, 261 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 262 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, 263 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 264 { INL, INL, INL, INL, INL, LOP, LOP, LOP, 265 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 266 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, 267 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 268 { INL, INL, INL, INL, INL, LOP, LOP, LOP, 269 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, 270 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, 271 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ 272 }, 273 { 274 /* TARGET_H8300S */ 275 /* 0 1 2 3 4 5 6 7 */ 276 /* 8 9 10 11 12 13 14 15 */ 277 /* 16 17 18 19 20 21 22 23 */ 278 /* 24 25 26 27 28 29 30 31 */ 279 { INL, INL, INL, INL, INL, INL, INL, INL, 280 INL, INL, INL, LOP, LOP, LOP, LOP, SPC, 281 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, 282 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 283 { INL, INL, INL, INL, INL, INL, INL, INL, 284 INL, INL, INL, LOP, LOP, LOP, LOP, SPC, 285 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, 286 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 287 { INL, INL, INL, INL, INL, INL, INL, INL, 288 INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 289 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, 290 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ 291 } 292 }; 293 294 #undef INL 295 #undef ROT 296 #undef LOP 297 #undef SPC 298 299 enum h8_cpu 300 { 301 H8_300, 302 H8_300H, 303 H8_S 304 }; 305 306 /* Initialize various cpu specific globals at start up. */ 307 308 void 309 h8300_init_once (void) 310 { 311 static const char *const h8_push_ops[2] = { "push" , "push.l" }; 312 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" }; 313 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; 314 315 if (TARGET_H8300) 316 { 317 cpu_type = (int) CPU_H8300; 318 h8_reg_names = names_big; 319 } 320 else 321 { 322 /* For this we treat the H8/300H and H8S the same. */ 323 cpu_type = (int) CPU_H8300H; 324 h8_reg_names = names_extended; 325 } 326 h8_push_op = h8_push_ops[cpu_type]; 327 h8_pop_op = h8_pop_ops[cpu_type]; 328 h8_mov_op = h8_mov_ops[cpu_type]; 329 330 if (!TARGET_H8300S && TARGET_MAC) 331 { 332 error ("-ms2600 is used without -ms"); 333 target_flags |= MASK_H8300S_1; 334 } 335 336 if (TARGET_H8300 && TARGET_NORMAL_MODE) 337 { 338 error ("-mn is used without -mh or -ms"); 339 target_flags ^= MASK_NORMAL_MODE; 340 } 341 342 /* Some of the shifts are optimized for speed by default. 343 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html 344 If optimizing for size, change shift_alg for those shift to 345 SHIFT_LOOP. */ 346 if (optimize_size) 347 { 348 /* H8/300 */ 349 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP; 350 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP; 351 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP; 352 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP; 353 354 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP; 355 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP; 356 357 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 358 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 359 360 /* H8/300H */ 361 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; 362 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; 363 364 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; 365 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; 366 367 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; 368 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; 369 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 370 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 371 372 /* H8S */ 373 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 374 } 375 376 /* Work out a value for MOVE_RATIO. */ 377 if (!TARGET_H8300SX) 378 { 379 /* Memory-memory moves are quite expensive without the 380 h8sx instructions. */ 381 h8300_move_ratio = 3; 382 } 383 else if (flag_omit_frame_pointer) 384 { 385 /* movmd sequences are fairly cheap when er6 isn't fixed. They can 386 sometimes be as short as two individual memory-to-memory moves, 387 but since they use all the call-saved registers, it seems better 388 to allow up to three moves here. */ 389 h8300_move_ratio = 4; 390 } 391 else if (optimize_size) 392 { 393 /* In this case we don't use movmd sequences since they tend 394 to be longer than calls to memcpy(). Memory-to-memory 395 moves are cheaper than for !TARGET_H8300SX, so it makes 396 sense to have a slightly higher threshold. */ 397 h8300_move_ratio = 4; 398 } 399 else 400 { 401 /* We use movmd sequences for some moves since it can be quicker 402 than calling memcpy(). The sequences will need to save and 403 restore er6 though, so bump up the cost. */ 404 h8300_move_ratio = 6; 405 } 406 } 407 408 /* Implement REG_CLASS_FROM_LETTER. 409 410 Some patterns need to use er6 as a scratch register. This is 411 difficult to arrange since er6 is the frame pointer and usually 412 can't be spilled. 413 414 Such patterns should define two alternatives, one which allows only 415 er6 and one which allows any general register. The former alternative 416 should have a 'd' constraint while the latter should be disparaged and 417 use 'D'. 418 419 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS. 420 However, there are cases where they should be NO_REGS: 421 422 - 'd' should be NO_REGS when reloading a function that uses the 423 frame pointer. In this case, DESTINATION_REGS won't contain any 424 spillable registers, so the first alternative can't be used. 425 426 - -fno-omit-frame-pointer means that the frame pointer will 427 always be in use. It's therefore better to map 'd' to NO_REGS 428 before reload so that register allocator will pick the second 429 alternative. 430 431 - we would like 'D' to be be NO_REGS when the frame pointer isn't 432 live, but we the frame pointer may turn out to be needed after 433 we start reload, and then we may have already decided we don't 434 have a choice, so we can't do that. Forcing the register 435 allocator to use er6 if possible might produce better code for 436 small functions: it's more efficient to save and restore er6 in 437 the prologue & epilogue than to do it in a define_split. 438 Hopefully disparaging 'D' will have a similar effect, without 439 forcing a reload failure if the frame pointer is found to be 440 needed too late. */ 441 442 enum reg_class 443 h8300_reg_class_from_letter (int c) 444 { 445 switch (c) 446 { 447 case 'a': 448 return MAC_REGS; 449 450 case 'c': 451 return COUNTER_REGS; 452 453 case 'd': 454 if (!flag_omit_frame_pointer && !reload_completed) 455 return NO_REGS; 456 if (frame_pointer_needed && reload_in_progress) 457 return NO_REGS; 458 return DESTINATION_REGS; 459 460 case 'D': 461 /* The meaning of a constraint shouldn't change dynamically, so 462 we can't make this NO_REGS. */ 463 return GENERAL_REGS; 464 465 case 'f': 466 return SOURCE_REGS; 467 468 default: 469 return NO_REGS; 470 } 471 } 472 473 /* Return the byte register name for a register rtx X. B should be 0 474 if you want a lower byte register. B should be 1 if you want an 475 upper byte register. */ 476 477 static const char * 478 byte_reg (rtx x, int b) 479 { 480 static const char *const names_small[] = { 481 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", 482 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h" 483 }; 484 485 gcc_assert (REG_P (x)); 486 487 return names_small[REGNO (x) * 2 + b]; 488 } 489 490 /* REGNO must be saved/restored across calls if this macro is true. */ 491 492 #define WORD_REG_USED(regno) \ 493 (regno < SP_REG \ 494 /* No need to save registers if this function will not return. */ \ 495 && ! TREE_THIS_VOLATILE (current_function_decl) \ 496 && (h8300_saveall_function_p (current_function_decl) \ 497 /* Save any call saved register that was used. */ \ 498 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \ 499 /* Save the frame pointer if it was used. */ \ 500 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \ 501 /* Save any register used in an interrupt handler. */ \ 502 || (h8300_current_function_interrupt_function_p () \ 503 && df_regs_ever_live_p (regno)) \ 504 /* Save call clobbered registers in non-leaf interrupt \ 505 handlers. */ \ 506 || (h8300_current_function_interrupt_function_p () \ 507 && call_used_regs[regno] \ 508 && !current_function_is_leaf))) 509 510 /* We use this to wrap all emitted insns in the prologue. */ 511 static rtx 512 F (rtx x, bool set_it) 513 { 514 if (set_it) 515 RTX_FRAME_RELATED_P (x) = 1; 516 return x; 517 } 518 519 /* Mark all the subexpressions of the PARALLEL rtx PAR as 520 frame-related. Return PAR. 521 522 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a 523 PARALLEL rtx other than the first if they do not have the 524 FRAME_RELATED flag set on them. */ 525 static rtx 526 Fpa (rtx par) 527 { 528 int len = XVECLEN (par, 0); 529 int i; 530 531 for (i = 0; i < len; i++) 532 F (XVECEXP (par, 0, i), true); 533 534 return par; 535 } 536 537 /* Output assembly language to FILE for the operation OP with operand size 538 SIZE to adjust the stack pointer. */ 539 540 static void 541 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue) 542 { 543 /* If the frame size is 0, we don't have anything to do. */ 544 if (size == 0) 545 return; 546 547 /* H8/300 cannot add/subtract a large constant with a single 548 instruction. If a temporary register is available, load the 549 constant to it and then do the addition. */ 550 if (TARGET_H8300 551 && size > 4 552 && !h8300_current_function_interrupt_function_p () 553 && !(cfun->static_chain_decl != NULL && sign < 0)) 554 { 555 rtx r3 = gen_rtx_REG (Pmode, 3); 556 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue); 557 F (emit_insn (gen_addhi3 (stack_pointer_rtx, 558 stack_pointer_rtx, r3)), in_prologue); 559 } 560 else 561 { 562 /* The stack adjustment made here is further optimized by the 563 splitter. In case of H8/300, the splitter always splits the 564 addition emitted here to make the adjustment interrupt-safe. 565 FIXME: We don't always tag those, because we don't know what 566 the splitter will do. */ 567 if (Pmode == HImode) 568 { 569 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx, 570 stack_pointer_rtx, GEN_INT (sign * size))); 571 if (size < 4) 572 F (x, in_prologue); 573 } 574 else 575 F (emit_insn (gen_addsi3 (stack_pointer_rtx, 576 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue); 577 } 578 } 579 580 /* Round up frame size SIZE. */ 581 582 static HOST_WIDE_INT 583 round_frame_size (HOST_WIDE_INT size) 584 { 585 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1) 586 & -STACK_BOUNDARY / BITS_PER_UNIT); 587 } 588 589 /* Compute which registers to push/pop. 590 Return a bit vector of registers. */ 591 592 static unsigned int 593 compute_saved_regs (void) 594 { 595 unsigned int saved_regs = 0; 596 int regno; 597 598 /* Construct a bit vector of registers to be pushed/popped. */ 599 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 600 { 601 if (WORD_REG_USED (regno)) 602 saved_regs |= 1 << regno; 603 } 604 605 /* Don't push/pop the frame pointer as it is treated separately. */ 606 if (frame_pointer_needed) 607 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM); 608 609 return saved_regs; 610 } 611 612 /* Emit an insn to push register RN. */ 613 614 static void 615 push (int rn) 616 { 617 rtx reg = gen_rtx_REG (word_mode, rn); 618 rtx x; 619 620 if (TARGET_H8300) 621 x = gen_push_h8300 (reg); 622 else if (!TARGET_NORMAL_MODE) 623 x = gen_push_h8300hs_advanced (reg); 624 else 625 x = gen_push_h8300hs_normal (reg); 626 x = F (emit_insn (x), true); 627 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0); 628 } 629 630 /* Emit an insn to pop register RN. */ 631 632 static void 633 pop (int rn) 634 { 635 rtx reg = gen_rtx_REG (word_mode, rn); 636 rtx x; 637 638 if (TARGET_H8300) 639 x = gen_pop_h8300 (reg); 640 else if (!TARGET_NORMAL_MODE) 641 x = gen_pop_h8300hs_advanced (reg); 642 else 643 x = gen_pop_h8300hs_normal (reg); 644 x = emit_insn (x); 645 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0); 646 } 647 648 /* Emit an instruction to push or pop NREGS consecutive registers 649 starting at register REGNO. POP_P selects a pop rather than a 650 push and RETURN_P is true if the instruction should return. 651 652 It must be possible to do the requested operation in a single 653 instruction. If NREGS == 1 && !RETURN_P, use a normal push 654 or pop insn. Otherwise emit a parallel of the form: 655 656 (parallel 657 [(return) ;; if RETURN_P 658 (save or restore REGNO) 659 (save or restore REGNO + 1) 660 ... 661 (save or restore REGNO + NREGS - 1) 662 (set sp (plus sp (const_int adjust)))] */ 663 664 static void 665 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p) 666 { 667 int i, j; 668 rtvec vec; 669 rtx sp, offset, x; 670 671 /* See whether we can use a simple push or pop. */ 672 if (!return_p && nregs == 1) 673 { 674 if (pop_p) 675 pop (regno); 676 else 677 push (regno); 678 return; 679 } 680 681 /* We need one element for the return insn, if present, one for each 682 register, and one for stack adjustment. */ 683 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1); 684 sp = stack_pointer_rtx; 685 i = 0; 686 687 /* Add the return instruction. */ 688 if (return_p) 689 { 690 RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode); 691 i++; 692 } 693 694 /* Add the register moves. */ 695 for (j = 0; j < nregs; j++) 696 { 697 rtx lhs, rhs; 698 699 if (pop_p) 700 { 701 /* Register REGNO + NREGS - 1 is popped first. Before the 702 stack adjustment, its slot is at address @sp. */ 703 lhs = gen_rtx_REG (SImode, regno + j); 704 rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4)); 705 } 706 else 707 { 708 /* Register REGNO is pushed first and will be stored at @(-4,sp). */ 709 lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4)); 710 rhs = gen_rtx_REG (SImode, regno + j); 711 } 712 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs); 713 } 714 715 /* Add the stack adjustment. */ 716 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4); 717 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp, 718 gen_rtx_PLUS (Pmode, sp, offset)); 719 720 x = gen_rtx_PARALLEL (VOIDmode, vec); 721 if (!pop_p) 722 x = Fpa (x); 723 724 if (return_p) 725 emit_jump_insn (x); 726 else 727 emit_insn (x); 728 } 729 730 /* Return true if X has the value sp + OFFSET. */ 731 732 static int 733 h8300_stack_offset_p (rtx x, int offset) 734 { 735 if (offset == 0) 736 return x == stack_pointer_rtx; 737 738 return (GET_CODE (x) == PLUS 739 && XEXP (x, 0) == stack_pointer_rtx 740 && GET_CODE (XEXP (x, 1)) == CONST_INT 741 && INTVAL (XEXP (x, 1)) == offset); 742 } 743 744 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in 745 something that may be an ldm or stm instruction. If it fits 746 the required template, return the register it loads or stores, 747 otherwise return -1. 748 749 LOAD_P is true if X should be a load, false if it should be a store. 750 NREGS is the number of registers that the whole instruction is expected 751 to load or store. INDEX is the index of the register that X should 752 load or store, relative to the lowest-numbered register. */ 753 754 static int 755 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs) 756 { 757 int regindex, memindex, offset; 758 759 if (load_p) 760 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4; 761 else 762 memindex = 0, regindex = 1, offset = (index + 1) * -4; 763 764 if (GET_CODE (x) == SET 765 && GET_CODE (XEXP (x, regindex)) == REG 766 && GET_CODE (XEXP (x, memindex)) == MEM 767 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset)) 768 return REGNO (XEXP (x, regindex)); 769 770 return -1; 771 } 772 773 /* Return true if the elements of VEC starting at FIRST describe an 774 ldm or stm instruction (LOAD_P says which). */ 775 776 int 777 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first) 778 { 779 rtx last; 780 int nregs, i, regno, adjust; 781 782 /* There must be a stack adjustment, a register move, and at least one 783 other operation (a return or another register move). */ 784 if (GET_NUM_ELEM (vec) < 3) 785 return false; 786 787 /* Get the range of registers to be pushed or popped. */ 788 nregs = GET_NUM_ELEM (vec) - first - 1; 789 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs); 790 791 /* Check that the call to h8300_ldm_stm_regno succeeded and 792 that we're only dealing with GPRs. */ 793 if (regno < 0 || regno + nregs > 8) 794 return false; 795 796 /* 2-register h8s instructions must start with an even-numbered register. 797 3- and 4-register instructions must start with er0 or er4. */ 798 if (!TARGET_H8300SX) 799 { 800 if ((regno & 1) != 0) 801 return false; 802 if (nregs > 2 && (regno & 3) != 0) 803 return false; 804 } 805 806 /* Check the other loads or stores. */ 807 for (i = 1; i < nregs; i++) 808 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs) 809 != regno + i) 810 return false; 811 812 /* Check the stack adjustment. */ 813 last = RTVEC_ELT (vec, first + nregs); 814 adjust = (load_p ? nregs : -nregs) * 4; 815 return (GET_CODE (last) == SET 816 && SET_DEST (last) == stack_pointer_rtx 817 && h8300_stack_offset_p (SET_SRC (last), adjust)); 818 } 819 820 /* This is what the stack looks like after the prolog of 821 a function with a frame has been set up: 822 823 <args> 824 PC 825 FP <- fp 826 <locals> 827 <saved registers> <- sp 828 829 This is what the stack looks like after the prolog of 830 a function which doesn't have a frame: 831 832 <args> 833 PC 834 <locals> 835 <saved registers> <- sp 836 */ 837 838 /* Generate RTL code for the function prologue. */ 839 840 void 841 h8300_expand_prologue (void) 842 { 843 int regno; 844 int saved_regs; 845 int n_regs; 846 847 /* If the current function has the OS_Task attribute set, then 848 we have a naked prologue. */ 849 if (h8300_os_task_function_p (current_function_decl)) 850 return; 851 852 if (h8300_monitor_function_p (current_function_decl)) 853 /* My understanding of monitor functions is they act just like 854 interrupt functions, except the prologue must mask 855 interrupts. */ 856 emit_insn (gen_monitor_prologue ()); 857 858 if (frame_pointer_needed) 859 { 860 /* Push fp. */ 861 push (HARD_FRAME_POINTER_REGNUM); 862 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true); 863 } 864 865 /* Push the rest of the registers in ascending order. */ 866 saved_regs = compute_saved_regs (); 867 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs) 868 { 869 n_regs = 1; 870 if (saved_regs & (1 << regno)) 871 { 872 if (TARGET_H8300S) 873 { 874 /* See how many registers we can push at the same time. */ 875 if ((!TARGET_H8300SX || (regno & 3) == 0) 876 && ((saved_regs >> regno) & 0x0f) == 0x0f) 877 n_regs = 4; 878 879 else if ((!TARGET_H8300SX || (regno & 3) == 0) 880 && ((saved_regs >> regno) & 0x07) == 0x07) 881 n_regs = 3; 882 883 else if ((!TARGET_H8300SX || (regno & 1) == 0) 884 && ((saved_regs >> regno) & 0x03) == 0x03) 885 n_regs = 2; 886 } 887 888 h8300_push_pop (regno, n_regs, false, false); 889 } 890 } 891 892 /* Leave room for locals. */ 893 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true); 894 } 895 896 /* Return nonzero if we can use "rts" for the function currently being 897 compiled. */ 898 899 int 900 h8300_can_use_return_insn_p (void) 901 { 902 return (reload_completed 903 && !frame_pointer_needed 904 && get_frame_size () == 0 905 && compute_saved_regs () == 0); 906 } 907 908 /* Generate RTL code for the function epilogue. */ 909 910 void 911 h8300_expand_epilogue (void) 912 { 913 int regno; 914 int saved_regs; 915 int n_regs; 916 HOST_WIDE_INT frame_size; 917 bool returned_p; 918 919 if (h8300_os_task_function_p (current_function_decl)) 920 /* OS_Task epilogues are nearly naked -- they just have an 921 rts instruction. */ 922 return; 923 924 frame_size = round_frame_size (get_frame_size ()); 925 returned_p = false; 926 927 /* Deallocate locals. */ 928 h8300_emit_stack_adjustment (1, frame_size, false); 929 930 /* Pop the saved registers in descending order. */ 931 saved_regs = compute_saved_regs (); 932 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs) 933 { 934 n_regs = 1; 935 if (saved_regs & (1 << regno)) 936 { 937 if (TARGET_H8300S) 938 { 939 /* See how many registers we can pop at the same time. */ 940 if ((TARGET_H8300SX || (regno & 3) == 3) 941 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f) 942 n_regs = 4; 943 944 else if ((TARGET_H8300SX || (regno & 3) == 2) 945 && ((saved_regs << 2 >> regno) & 0x07) == 0x07) 946 n_regs = 3; 947 948 else if ((TARGET_H8300SX || (regno & 1) == 1) 949 && ((saved_regs << 1 >> regno) & 0x03) == 0x03) 950 n_regs = 2; 951 } 952 953 /* See if this pop would be the last insn before the return. 954 If so, use rte/l or rts/l instead of pop or ldm.l. */ 955 if (TARGET_H8300SX 956 && !frame_pointer_needed 957 && frame_size == 0 958 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0) 959 returned_p = true; 960 961 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p); 962 } 963 } 964 965 /* Pop frame pointer if we had one. */ 966 if (frame_pointer_needed) 967 { 968 if (TARGET_H8300SX) 969 returned_p = true; 970 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p); 971 } 972 973 if (!returned_p) 974 emit_jump_insn (gen_rtx_RETURN (VOIDmode)); 975 } 976 977 /* Return nonzero if the current function is an interrupt 978 function. */ 979 980 int 981 h8300_current_function_interrupt_function_p (void) 982 { 983 return (h8300_interrupt_function_p (current_function_decl) 984 || h8300_monitor_function_p (current_function_decl)); 985 } 986 987 /* Output assembly code for the start of the file. */ 988 989 static void 990 h8300_file_start (void) 991 { 992 default_file_start (); 993 994 if (TARGET_H8300H) 995 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file); 996 else if (TARGET_H8300SX) 997 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file); 998 else if (TARGET_H8300S) 999 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file); 1000 } 1001 1002 /* Output assembly language code for the end of file. */ 1003 1004 static void 1005 h8300_file_end (void) 1006 { 1007 fputs ("\t.end\n", asm_out_file); 1008 } 1009 1010 /* Split an add of a small constant into two adds/subs insns. 1011 1012 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec 1013 instead of adds/subs. */ 1014 1015 void 1016 split_adds_subs (enum machine_mode mode, rtx *operands) 1017 { 1018 HOST_WIDE_INT val = INTVAL (operands[1]); 1019 rtx reg = operands[0]; 1020 HOST_WIDE_INT sign = 1; 1021 HOST_WIDE_INT amount; 1022 rtx (*gen_add) (rtx, rtx, rtx); 1023 1024 /* Force VAL to be positive so that we do not have to consider the 1025 sign. */ 1026 if (val < 0) 1027 { 1028 val = -val; 1029 sign = -1; 1030 } 1031 1032 switch (mode) 1033 { 1034 case HImode: 1035 gen_add = gen_addhi3; 1036 break; 1037 1038 case SImode: 1039 gen_add = gen_addsi3; 1040 break; 1041 1042 default: 1043 gcc_unreachable (); 1044 } 1045 1046 /* Try different amounts in descending order. */ 1047 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2; 1048 amount > 0; 1049 amount /= 2) 1050 { 1051 for (; val >= amount; val -= amount) 1052 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount))); 1053 } 1054 1055 return; 1056 } 1057 1058 /* Handle machine specific pragmas for compatibility with existing 1059 compilers for the H8/300. 1060 1061 pragma saveall generates prologue/epilogue code which saves and 1062 restores all the registers on function entry. 1063 1064 pragma interrupt saves and restores all registers, and exits with 1065 an rte instruction rather than an rts. A pointer to a function 1066 with this attribute may be safely used in an interrupt vector. */ 1067 1068 void 1069 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1070 { 1071 pragma_interrupt = 1; 1072 } 1073 1074 void 1075 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1076 { 1077 pragma_saveall = 1; 1078 } 1079 1080 /* If the next function argument with MODE and TYPE is to be passed in 1081 a register, return a reg RTX for the hard register in which to pass 1082 the argument. CUM represents the state after the last argument. 1083 If the argument is to be pushed, NULL_RTX is returned. */ 1084 1085 rtx 1086 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, 1087 tree type, int named) 1088 { 1089 static const char *const hand_list[] = { 1090 "__main", 1091 "__cmpsi2", 1092 "__divhi3", 1093 "__modhi3", 1094 "__udivhi3", 1095 "__umodhi3", 1096 "__divsi3", 1097 "__modsi3", 1098 "__udivsi3", 1099 "__umodsi3", 1100 "__mulhi3", 1101 "__mulsi3", 1102 "__reg_memcpy", 1103 "__reg_memset", 1104 "__ucmpsi2", 1105 0, 1106 }; 1107 1108 rtx result = NULL_RTX; 1109 const char *fname; 1110 int regpass = 0; 1111 1112 /* Never pass unnamed arguments in registers. */ 1113 if (!named) 1114 return NULL_RTX; 1115 1116 /* Pass 3 regs worth of data in regs when user asked on the command line. */ 1117 if (TARGET_QUICKCALL) 1118 regpass = 3; 1119 1120 /* If calling hand written assembler, use 4 regs of args. */ 1121 if (cum->libcall) 1122 { 1123 const char * const *p; 1124 1125 fname = XSTR (cum->libcall, 0); 1126 1127 /* See if this libcall is one of the hand coded ones. */ 1128 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) 1129 ; 1130 1131 if (*p) 1132 regpass = 4; 1133 } 1134 1135 if (regpass) 1136 { 1137 int size; 1138 1139 if (mode == BLKmode) 1140 size = int_size_in_bytes (type); 1141 else 1142 size = GET_MODE_SIZE (mode); 1143 1144 if (size + cum->nbytes <= regpass * UNITS_PER_WORD 1145 && cum->nbytes / UNITS_PER_WORD <= 3) 1146 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); 1147 } 1148 1149 return result; 1150 } 1151 1152 /* Compute the cost of an and insn. */ 1153 1154 static int 1155 h8300_and_costs (rtx x) 1156 { 1157 rtx operands[4]; 1158 1159 if (GET_MODE (x) == QImode) 1160 return 1; 1161 1162 if (GET_MODE (x) != HImode 1163 && GET_MODE (x) != SImode) 1164 return 100; 1165 1166 operands[0] = NULL; 1167 operands[1] = XEXP (x, 0); 1168 operands[2] = XEXP (x, 1); 1169 operands[3] = x; 1170 return compute_logical_op_length (GET_MODE (x), operands) / 2; 1171 } 1172 1173 /* Compute the cost of a shift insn. */ 1174 1175 static int 1176 h8300_shift_costs (rtx x) 1177 { 1178 rtx operands[4]; 1179 1180 if (GET_MODE (x) != QImode 1181 && GET_MODE (x) != HImode 1182 && GET_MODE (x) != SImode) 1183 return 100; 1184 1185 operands[0] = NULL; 1186 operands[1] = NULL; 1187 operands[2] = XEXP (x, 1); 1188 operands[3] = x; 1189 return compute_a_shift_length (NULL, operands) / 2; 1190 } 1191 1192 /* Worker function for TARGET_RTX_COSTS. */ 1193 1194 static bool 1195 h8300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed) 1196 { 1197 if (TARGET_H8300SX && outer_code == MEM) 1198 { 1199 /* Estimate the number of execution states needed to calculate 1200 the address. */ 1201 if (register_operand (x, VOIDmode) 1202 || GET_CODE (x) == POST_INC 1203 || GET_CODE (x) == POST_DEC 1204 || CONSTANT_P (x)) 1205 *total = 0; 1206 else 1207 *total = COSTS_N_INSNS (1); 1208 return true; 1209 } 1210 1211 switch (code) 1212 { 1213 case CONST_INT: 1214 { 1215 HOST_WIDE_INT n = INTVAL (x); 1216 1217 if (TARGET_H8300SX) 1218 { 1219 /* Constant operands need the same number of processor 1220 states as register operands. Although we could try to 1221 use a size-based cost for !speed, the lack of 1222 of a mode makes the results very unpredictable. */ 1223 *total = 0; 1224 return true; 1225 } 1226 if (-4 <= n || n <= 4) 1227 { 1228 switch ((int) n) 1229 { 1230 case 0: 1231 *total = 0; 1232 return true; 1233 case 1: 1234 case 2: 1235 case -1: 1236 case -2: 1237 *total = 0 + (outer_code == SET); 1238 return true; 1239 case 4: 1240 case -4: 1241 if (TARGET_H8300H || TARGET_H8300S) 1242 *total = 0 + (outer_code == SET); 1243 else 1244 *total = 1; 1245 return true; 1246 } 1247 } 1248 *total = 1; 1249 return true; 1250 } 1251 1252 case CONST: 1253 case LABEL_REF: 1254 case SYMBOL_REF: 1255 if (TARGET_H8300SX) 1256 { 1257 /* See comment for CONST_INT. */ 1258 *total = 0; 1259 return true; 1260 } 1261 *total = 3; 1262 return true; 1263 1264 case CONST_DOUBLE: 1265 *total = 20; 1266 return true; 1267 1268 case COMPARE: 1269 if (XEXP (x, 1) == const0_rtx) 1270 *total = 0; 1271 return false; 1272 1273 case AND: 1274 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode) 1275 || !h8300_src_operand (XEXP (x, 1), VOIDmode)) 1276 return false; 1277 *total = COSTS_N_INSNS (h8300_and_costs (x)); 1278 return true; 1279 1280 /* We say that MOD and DIV are so expensive because otherwise we'll 1281 generate some really horrible code for division of a power of two. */ 1282 case MOD: 1283 case DIV: 1284 case UMOD: 1285 case UDIV: 1286 if (TARGET_H8300SX) 1287 switch (GET_MODE (x)) 1288 { 1289 case QImode: 1290 case HImode: 1291 *total = COSTS_N_INSNS (!speed ? 4 : 10); 1292 return false; 1293 1294 case SImode: 1295 *total = COSTS_N_INSNS (!speed ? 4 : 18); 1296 return false; 1297 1298 default: 1299 break; 1300 } 1301 *total = COSTS_N_INSNS (12); 1302 return true; 1303 1304 case MULT: 1305 if (TARGET_H8300SX) 1306 switch (GET_MODE (x)) 1307 { 1308 case QImode: 1309 case HImode: 1310 *total = COSTS_N_INSNS (2); 1311 return false; 1312 1313 case SImode: 1314 *total = COSTS_N_INSNS (5); 1315 return false; 1316 1317 default: 1318 break; 1319 } 1320 *total = COSTS_N_INSNS (4); 1321 return true; 1322 1323 case ASHIFT: 1324 case ASHIFTRT: 1325 case LSHIFTRT: 1326 if (h8sx_binary_shift_operator (x, VOIDmode)) 1327 { 1328 *total = COSTS_N_INSNS (2); 1329 return false; 1330 } 1331 else if (h8sx_unary_shift_operator (x, VOIDmode)) 1332 { 1333 *total = COSTS_N_INSNS (1); 1334 return false; 1335 } 1336 *total = COSTS_N_INSNS (h8300_shift_costs (x)); 1337 return true; 1338 1339 case ROTATE: 1340 case ROTATERT: 1341 if (GET_MODE (x) == HImode) 1342 *total = 2; 1343 else 1344 *total = 8; 1345 return true; 1346 1347 default: 1348 *total = COSTS_N_INSNS (1); 1349 return false; 1350 } 1351 } 1352 1353 /* Documentation for the machine specific operand escapes: 1354 1355 'E' like s but negative. 1356 'F' like t but negative. 1357 'G' constant just the negative 1358 'R' print operand as a byte:8 address if appropriate, else fall back to 1359 'X' handling. 1360 'S' print operand as a long word 1361 'T' print operand as a word 1362 'V' find the set bit, and print its number. 1363 'W' find the clear bit, and print its number. 1364 'X' print operand as a byte 1365 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. 1366 If this operand isn't a register, fall back to 'R' handling. 1367 'Z' print int & 7. 1368 'c' print the opcode corresponding to rtl 1369 'e' first word of 32-bit value - if reg, then least reg. if mem 1370 then least. if const then most sig word 1371 'f' second word of 32-bit value - if reg, then biggest reg. if mem 1372 then +2. if const then least sig word 1373 'j' print operand as condition code. 1374 'k' print operand as reverse condition code. 1375 'm' convert an integer operand to a size suffix (.b, .w or .l) 1376 'o' print an integer without a leading '#' 1377 's' print as low byte of 16-bit value 1378 't' print as high byte of 16-bit value 1379 'w' print as low byte of 32-bit value 1380 'x' print as 2nd byte of 32-bit value 1381 'y' print as 3rd byte of 32-bit value 1382 'z' print as msb of 32-bit value 1383 */ 1384 1385 /* Return assembly language string which identifies a comparison type. */ 1386 1387 static const char * 1388 cond_string (enum rtx_code code) 1389 { 1390 switch (code) 1391 { 1392 case NE: 1393 return "ne"; 1394 case EQ: 1395 return "eq"; 1396 case GE: 1397 return "ge"; 1398 case GT: 1399 return "gt"; 1400 case LE: 1401 return "le"; 1402 case LT: 1403 return "lt"; 1404 case GEU: 1405 return "hs"; 1406 case GTU: 1407 return "hi"; 1408 case LEU: 1409 return "ls"; 1410 case LTU: 1411 return "lo"; 1412 default: 1413 gcc_unreachable (); 1414 } 1415 } 1416 1417 /* Print operand X using operand code CODE to assembly language output file 1418 FILE. */ 1419 1420 void 1421 print_operand (FILE *file, rtx x, int code) 1422 { 1423 /* This is used for communication between codes V,W,Z and Y. */ 1424 static int bitint; 1425 1426 switch (code) 1427 { 1428 case 'E': 1429 switch (GET_CODE (x)) 1430 { 1431 case REG: 1432 fprintf (file, "%sl", names_big[REGNO (x)]); 1433 break; 1434 case CONST_INT: 1435 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff); 1436 break; 1437 default: 1438 gcc_unreachable (); 1439 } 1440 break; 1441 case 'F': 1442 switch (GET_CODE (x)) 1443 { 1444 case REG: 1445 fprintf (file, "%sh", names_big[REGNO (x)]); 1446 break; 1447 case CONST_INT: 1448 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8); 1449 break; 1450 default: 1451 gcc_unreachable (); 1452 } 1453 break; 1454 case 'G': 1455 gcc_assert (GET_CODE (x) == CONST_INT); 1456 fprintf (file, "#%ld", 0xff & (-INTVAL (x))); 1457 break; 1458 case 'S': 1459 if (GET_CODE (x) == REG) 1460 fprintf (file, "%s", names_extended[REGNO (x)]); 1461 else 1462 goto def; 1463 break; 1464 case 'T': 1465 if (GET_CODE (x) == REG) 1466 fprintf (file, "%s", names_big[REGNO (x)]); 1467 else 1468 goto def; 1469 break; 1470 case 'V': 1471 bitint = exact_log2 (INTVAL (x) & 0xff); 1472 gcc_assert (bitint >= 0); 1473 fprintf (file, "#%d", bitint); 1474 break; 1475 case 'W': 1476 bitint = exact_log2 ((~INTVAL (x)) & 0xff); 1477 gcc_assert (bitint >= 0); 1478 fprintf (file, "#%d", bitint); 1479 break; 1480 case 'R': 1481 case 'X': 1482 if (GET_CODE (x) == REG) 1483 fprintf (file, "%s", byte_reg (x, 0)); 1484 else 1485 goto def; 1486 break; 1487 case 'Y': 1488 gcc_assert (bitint >= 0); 1489 if (GET_CODE (x) == REG) 1490 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); 1491 else 1492 print_operand (file, x, 'R'); 1493 bitint = -1; 1494 break; 1495 case 'Z': 1496 bitint = INTVAL (x); 1497 fprintf (file, "#%d", bitint & 7); 1498 break; 1499 case 'c': 1500 switch (GET_CODE (x)) 1501 { 1502 case IOR: 1503 fprintf (file, "or"); 1504 break; 1505 case XOR: 1506 fprintf (file, "xor"); 1507 break; 1508 case AND: 1509 fprintf (file, "and"); 1510 break; 1511 default: 1512 break; 1513 } 1514 break; 1515 case 'e': 1516 switch (GET_CODE (x)) 1517 { 1518 case REG: 1519 if (TARGET_H8300) 1520 fprintf (file, "%s", names_big[REGNO (x)]); 1521 else 1522 fprintf (file, "%s", names_upper_extended[REGNO (x)]); 1523 break; 1524 case MEM: 1525 print_operand (file, x, 0); 1526 break; 1527 case CONST_INT: 1528 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff)); 1529 break; 1530 case CONST_DOUBLE: 1531 { 1532 long val; 1533 REAL_VALUE_TYPE rv; 1534 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 1535 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 1536 fprintf (file, "#%ld", ((val >> 16) & 0xffff)); 1537 break; 1538 } 1539 default: 1540 gcc_unreachable (); 1541 break; 1542 } 1543 break; 1544 case 'f': 1545 switch (GET_CODE (x)) 1546 { 1547 case REG: 1548 if (TARGET_H8300) 1549 fprintf (file, "%s", names_big[REGNO (x) + 1]); 1550 else 1551 fprintf (file, "%s", names_big[REGNO (x)]); 1552 break; 1553 case MEM: 1554 x = adjust_address (x, HImode, 2); 1555 print_operand (file, x, 0); 1556 break; 1557 case CONST_INT: 1558 fprintf (file, "#%ld", INTVAL (x) & 0xffff); 1559 break; 1560 case CONST_DOUBLE: 1561 { 1562 long val; 1563 REAL_VALUE_TYPE rv; 1564 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 1565 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 1566 fprintf (file, "#%ld", (val & 0xffff)); 1567 break; 1568 } 1569 default: 1570 gcc_unreachable (); 1571 } 1572 break; 1573 case 'j': 1574 fputs (cond_string (GET_CODE (x)), file); 1575 break; 1576 case 'k': 1577 fputs (cond_string (reverse_condition (GET_CODE (x))), file); 1578 break; 1579 case 'm': 1580 gcc_assert (GET_CODE (x) == CONST_INT); 1581 switch (INTVAL (x)) 1582 { 1583 case 1: 1584 fputs (".b", file); 1585 break; 1586 1587 case 2: 1588 fputs (".w", file); 1589 break; 1590 1591 case 4: 1592 fputs (".l", file); 1593 break; 1594 1595 default: 1596 gcc_unreachable (); 1597 } 1598 break; 1599 case 'o': 1600 print_operand_address (file, x); 1601 break; 1602 case 's': 1603 if (GET_CODE (x) == CONST_INT) 1604 fprintf (file, "#%ld", (INTVAL (x)) & 0xff); 1605 else 1606 fprintf (file, "%s", byte_reg (x, 0)); 1607 break; 1608 case 't': 1609 if (GET_CODE (x) == CONST_INT) 1610 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1611 else 1612 fprintf (file, "%s", byte_reg (x, 1)); 1613 break; 1614 case 'w': 1615 if (GET_CODE (x) == CONST_INT) 1616 fprintf (file, "#%ld", INTVAL (x) & 0xff); 1617 else 1618 fprintf (file, "%s", 1619 byte_reg (x, TARGET_H8300 ? 2 : 0)); 1620 break; 1621 case 'x': 1622 if (GET_CODE (x) == CONST_INT) 1623 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1624 else 1625 fprintf (file, "%s", 1626 byte_reg (x, TARGET_H8300 ? 3 : 1)); 1627 break; 1628 case 'y': 1629 if (GET_CODE (x) == CONST_INT) 1630 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff); 1631 else 1632 fprintf (file, "%s", byte_reg (x, 0)); 1633 break; 1634 case 'z': 1635 if (GET_CODE (x) == CONST_INT) 1636 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff); 1637 else 1638 fprintf (file, "%s", byte_reg (x, 1)); 1639 break; 1640 1641 default: 1642 def: 1643 switch (GET_CODE (x)) 1644 { 1645 case REG: 1646 switch (GET_MODE (x)) 1647 { 1648 case QImode: 1649 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */ 1650 fprintf (file, "%s", byte_reg (x, 0)); 1651 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */ 1652 fprintf (file, "%s", names_big[REGNO (x)]); 1653 #endif 1654 break; 1655 case HImode: 1656 fprintf (file, "%s", names_big[REGNO (x)]); 1657 break; 1658 case SImode: 1659 case SFmode: 1660 fprintf (file, "%s", names_extended[REGNO (x)]); 1661 break; 1662 default: 1663 gcc_unreachable (); 1664 } 1665 break; 1666 1667 case MEM: 1668 { 1669 rtx addr = XEXP (x, 0); 1670 1671 fprintf (file, "@"); 1672 output_address (addr); 1673 1674 /* Add a length suffix to constant addresses. Although this 1675 is often unnecessary, it helps to avoid ambiguity in the 1676 syntax of mova. If we wrote an insn like: 1677 1678 mova/w.l @(1,@foo.b),er0 1679 1680 then .b would be considered part of the symbol name. 1681 Adding a length after foo will avoid this. */ 1682 if (CONSTANT_P (addr)) 1683 switch (code) 1684 { 1685 case 'R': 1686 /* Used for mov.b and bit operations. */ 1687 if (h8300_eightbit_constant_address_p (addr)) 1688 { 1689 fprintf (file, ":8"); 1690 break; 1691 } 1692 1693 /* Fall through. We should not get here if we are 1694 processing bit operations on H8/300 or H8/300H 1695 because 'U' constraint does not allow bit 1696 operations on the tiny area on these machines. */ 1697 1698 case 'X': 1699 case 'T': 1700 case 'S': 1701 if (h8300_constant_length (addr) == 2) 1702 fprintf (file, ":16"); 1703 else 1704 fprintf (file, ":32"); 1705 break; 1706 default: 1707 break; 1708 } 1709 } 1710 break; 1711 1712 case CONST_INT: 1713 case SYMBOL_REF: 1714 case CONST: 1715 case LABEL_REF: 1716 fprintf (file, "#"); 1717 print_operand_address (file, x); 1718 break; 1719 case CONST_DOUBLE: 1720 { 1721 long val; 1722 REAL_VALUE_TYPE rv; 1723 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 1724 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 1725 fprintf (file, "#%ld", val); 1726 break; 1727 } 1728 default: 1729 break; 1730 } 1731 } 1732 } 1733 1734 /* Output assembly language output for the address ADDR to FILE. */ 1735 1736 void 1737 print_operand_address (FILE *file, rtx addr) 1738 { 1739 rtx index; 1740 int size; 1741 1742 switch (GET_CODE (addr)) 1743 { 1744 case REG: 1745 fprintf (file, "%s", h8_reg_names[REGNO (addr)]); 1746 break; 1747 1748 case PRE_DEC: 1749 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1750 break; 1751 1752 case POST_INC: 1753 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); 1754 break; 1755 1756 case PRE_INC: 1757 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1758 break; 1759 1760 case POST_DEC: 1761 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]); 1762 break; 1763 1764 case PLUS: 1765 fprintf (file, "("); 1766 1767 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size); 1768 if (GET_CODE (index) == REG) 1769 { 1770 /* reg,foo */ 1771 print_operand_address (file, XEXP (addr, 1)); 1772 fprintf (file, ","); 1773 switch (size) 1774 { 1775 case 0: 1776 print_operand_address (file, index); 1777 break; 1778 1779 case 1: 1780 print_operand (file, index, 'X'); 1781 fputs (".b", file); 1782 break; 1783 1784 case 2: 1785 print_operand (file, index, 'T'); 1786 fputs (".w", file); 1787 break; 1788 1789 case 4: 1790 print_operand (file, index, 'S'); 1791 fputs (".l", file); 1792 break; 1793 } 1794 /* print_operand_address (file, XEXP (addr, 0)); */ 1795 } 1796 else 1797 { 1798 /* foo+k */ 1799 print_operand_address (file, XEXP (addr, 0)); 1800 fprintf (file, "+"); 1801 print_operand_address (file, XEXP (addr, 1)); 1802 } 1803 fprintf (file, ")"); 1804 break; 1805 1806 case CONST_INT: 1807 { 1808 /* Since the H8/300 only has 16-bit pointers, negative values are also 1809 those >= 32768. This happens for example with pointer minus a 1810 constant. We don't want to turn (char *p - 2) into 1811 (char *p + 65534) because loop unrolling can build upon this 1812 (IE: char *p + 131068). */ 1813 int n = INTVAL (addr); 1814 if (TARGET_H8300) 1815 n = (int) (short) n; 1816 fprintf (file, "%d", n); 1817 break; 1818 } 1819 1820 default: 1821 output_addr_const (file, addr); 1822 break; 1823 } 1824 } 1825 1826 /* Output all insn addresses and their sizes into the assembly language 1827 output file. This is helpful for debugging whether the length attributes 1828 in the md file are correct. This is not meant to be a user selectable 1829 option. */ 1830 1831 void 1832 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED, 1833 int num_operands ATTRIBUTE_UNUSED) 1834 { 1835 /* This holds the last insn address. */ 1836 static int last_insn_address = 0; 1837 1838 const int uid = INSN_UID (insn); 1839 1840 if (TARGET_ADDRESSES) 1841 { 1842 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid), 1843 INSN_ADDRESSES (uid) - last_insn_address); 1844 last_insn_address = INSN_ADDRESSES (uid); 1845 } 1846 } 1847 1848 /* Prepare for an SI sized move. */ 1849 1850 int 1851 h8300_expand_movsi (rtx operands[]) 1852 { 1853 rtx src = operands[1]; 1854 rtx dst = operands[0]; 1855 if (!reload_in_progress && !reload_completed) 1856 { 1857 if (!register_operand (dst, GET_MODE (dst))) 1858 { 1859 rtx tmp = gen_reg_rtx (GET_MODE (dst)); 1860 emit_move_insn (tmp, src); 1861 operands[1] = tmp; 1862 } 1863 } 1864 return 0; 1865 } 1866 1867 /* Given FROM and TO register numbers, say whether this elimination is allowed. 1868 Frame pointer elimination is automatically handled. 1869 1870 For the h8300, if frame pointer elimination is being done, we would like to 1871 convert ap and rp into sp, not fp. 1872 1873 All other eliminations are valid. */ 1874 1875 static bool 1876 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 1877 { 1878 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); 1879 } 1880 1881 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). 1882 Define the offset between two registers, one to be eliminated, and 1883 the other its replacement, at the start of a routine. */ 1884 1885 int 1886 h8300_initial_elimination_offset (int from, int to) 1887 { 1888 /* The number of bytes that the return address takes on the stack. */ 1889 int pc_size = POINTER_SIZE / BITS_PER_UNIT; 1890 1891 /* The number of bytes that the saved frame pointer takes on the stack. */ 1892 int fp_size = frame_pointer_needed * UNITS_PER_WORD; 1893 1894 /* The number of bytes that the saved registers, excluding the frame 1895 pointer, take on the stack. */ 1896 int saved_regs_size = 0; 1897 1898 /* The number of bytes that the locals takes on the stack. */ 1899 int frame_size = round_frame_size (get_frame_size ()); 1900 1901 int regno; 1902 1903 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 1904 if (WORD_REG_USED (regno)) 1905 saved_regs_size += UNITS_PER_WORD; 1906 1907 /* Adjust saved_regs_size because the above loop took the frame 1908 pointer int account. */ 1909 saved_regs_size -= fp_size; 1910 1911 switch (to) 1912 { 1913 case HARD_FRAME_POINTER_REGNUM: 1914 switch (from) 1915 { 1916 case ARG_POINTER_REGNUM: 1917 return pc_size + fp_size; 1918 case RETURN_ADDRESS_POINTER_REGNUM: 1919 return fp_size; 1920 case FRAME_POINTER_REGNUM: 1921 return -saved_regs_size; 1922 default: 1923 gcc_unreachable (); 1924 } 1925 break; 1926 case STACK_POINTER_REGNUM: 1927 switch (from) 1928 { 1929 case ARG_POINTER_REGNUM: 1930 return pc_size + saved_regs_size + frame_size; 1931 case RETURN_ADDRESS_POINTER_REGNUM: 1932 return saved_regs_size + frame_size; 1933 case FRAME_POINTER_REGNUM: 1934 return frame_size; 1935 default: 1936 gcc_unreachable (); 1937 } 1938 break; 1939 default: 1940 gcc_unreachable (); 1941 } 1942 gcc_unreachable (); 1943 } 1944 1945 /* Worker function for RETURN_ADDR_RTX. */ 1946 1947 rtx 1948 h8300_return_addr_rtx (int count, rtx frame) 1949 { 1950 rtx ret; 1951 1952 if (count == 0) 1953 ret = gen_rtx_MEM (Pmode, 1954 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)); 1955 else if (flag_omit_frame_pointer) 1956 return (rtx) 0; 1957 else 1958 ret = gen_rtx_MEM (Pmode, 1959 memory_address (Pmode, 1960 plus_constant (frame, UNITS_PER_WORD))); 1961 set_mem_alias_set (ret, get_frame_alias_set ()); 1962 return ret; 1963 } 1964 1965 /* Update the condition code from the insn. */ 1966 1967 void 1968 notice_update_cc (rtx body, rtx insn) 1969 { 1970 rtx set; 1971 1972 switch (get_attr_cc (insn)) 1973 { 1974 case CC_NONE: 1975 /* Insn does not affect CC at all. */ 1976 break; 1977 1978 case CC_NONE_0HIT: 1979 /* Insn does not change CC, but the 0'th operand has been changed. */ 1980 if (cc_status.value1 != 0 1981 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) 1982 cc_status.value1 = 0; 1983 if (cc_status.value2 != 0 1984 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2)) 1985 cc_status.value2 = 0; 1986 break; 1987 1988 case CC_SET_ZN: 1989 /* Insn sets the Z,N flags of CC to recog_data.operand[0]. 1990 The V flag is unusable. The C flag may or may not be known but 1991 that's ok because alter_cond will change tests to use EQ/NE. */ 1992 CC_STATUS_INIT; 1993 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; 1994 set = single_set (insn); 1995 cc_status.value1 = SET_SRC (set); 1996 if (SET_DEST (set) != cc0_rtx) 1997 cc_status.value2 = SET_DEST (set); 1998 break; 1999 2000 case CC_SET_ZNV: 2001 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. 2002 The C flag may or may not be known but that's ok because 2003 alter_cond will change tests to use EQ/NE. */ 2004 CC_STATUS_INIT; 2005 cc_status.flags |= CC_NO_CARRY; 2006 set = single_set (insn); 2007 cc_status.value1 = SET_SRC (set); 2008 if (SET_DEST (set) != cc0_rtx) 2009 { 2010 /* If the destination is STRICT_LOW_PART, strip off 2011 STRICT_LOW_PART. */ 2012 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) 2013 cc_status.value2 = XEXP (SET_DEST (set), 0); 2014 else 2015 cc_status.value2 = SET_DEST (set); 2016 } 2017 break; 2018 2019 case CC_COMPARE: 2020 /* The insn is a compare instruction. */ 2021 CC_STATUS_INIT; 2022 cc_status.value1 = SET_SRC (body); 2023 break; 2024 2025 case CC_CLOBBER: 2026 /* Insn doesn't leave CC in a usable state. */ 2027 CC_STATUS_INIT; 2028 break; 2029 } 2030 } 2031 2032 /* Given that X occurs in an address of the form (plus X constant), 2033 return the part of X that is expected to be a register. There are 2034 four kinds of addressing mode to recognize: 2035 2036 @(dd,Rn) 2037 @(dd,RnL.b) 2038 @(dd,Rn.w) 2039 @(dd,ERn.l) 2040 2041 If SIZE is nonnull, and the address is one of the last three forms, 2042 set *SIZE to the index multiplication factor. Set it to 0 for 2043 plain @(dd,Rn) addresses. 2044 2045 MODE is the mode of the value being accessed. It can be VOIDmode 2046 if the address is known to be valid, but its mode is unknown. */ 2047 2048 rtx 2049 h8300_get_index (rtx x, enum machine_mode mode, int *size) 2050 { 2051 int dummy, factor; 2052 2053 if (size == 0) 2054 size = &dummy; 2055 2056 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode)); 2057 if (TARGET_H8300SX 2058 && factor <= 4 2059 && (mode == VOIDmode 2060 || GET_MODE_CLASS (mode) == MODE_INT 2061 || GET_MODE_CLASS (mode) == MODE_FLOAT)) 2062 { 2063 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND) 2064 { 2065 /* When accessing byte-sized values, the index can be 2066 a zero-extended QImode or HImode register. */ 2067 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0))); 2068 return XEXP (x, 0); 2069 } 2070 else 2071 { 2072 /* We're looking for addresses of the form: 2073 2074 (mult X I) 2075 or (mult (zero_extend X) I) 2076 2077 where I is the size of the operand being accessed. 2078 The canonical form of the second expression is: 2079 2080 (and (mult (subreg X) I) J) 2081 2082 where J == GET_MODE_MASK (GET_MODE (X)) * I. */ 2083 rtx index; 2084 2085 if (GET_CODE (x) == AND 2086 && GET_CODE (XEXP (x, 1)) == CONST_INT 2087 && (factor == 0 2088 || INTVAL (XEXP (x, 1)) == 0xff * factor 2089 || INTVAL (XEXP (x, 1)) == 0xffff * factor)) 2090 { 2091 index = XEXP (x, 0); 2092 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1); 2093 } 2094 else 2095 { 2096 index = x; 2097 *size = 4; 2098 } 2099 2100 if (GET_CODE (index) == MULT 2101 && GET_CODE (XEXP (index, 1)) == CONST_INT 2102 && (factor == 0 || factor == INTVAL (XEXP (index, 1)))) 2103 return XEXP (index, 0); 2104 } 2105 } 2106 *size = 0; 2107 return x; 2108 } 2109 2110 static const h8300_length_table addb_length_table = 2111 { 2112 /* #xx Rs @aa @Rs @xx */ 2113 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */ 2114 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */ 2115 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */ 2116 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */ 2117 }; 2118 2119 static const h8300_length_table addw_length_table = 2120 { 2121 /* #xx Rs @aa @Rs @xx */ 2122 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */ 2123 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */ 2124 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */ 2125 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */ 2126 }; 2127 2128 static const h8300_length_table addl_length_table = 2129 { 2130 /* #xx Rs @aa @Rs @xx */ 2131 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */ 2132 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */ 2133 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */ 2134 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */ 2135 }; 2136 2137 #define logicb_length_table addb_length_table 2138 #define logicw_length_table addw_length_table 2139 2140 static const h8300_length_table logicl_length_table = 2141 { 2142 /* #xx Rs @aa @Rs @xx */ 2143 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */ 2144 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */ 2145 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */ 2146 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */ 2147 }; 2148 2149 static const h8300_length_table movb_length_table = 2150 { 2151 /* #xx Rs @aa @Rs @xx */ 2152 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */ 2153 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */ 2154 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */ 2155 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */ 2156 }; 2157 2158 #define movw_length_table movb_length_table 2159 2160 static const h8300_length_table movl_length_table = 2161 { 2162 /* #xx Rs @aa @Rs @xx */ 2163 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */ 2164 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */ 2165 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */ 2166 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */ 2167 }; 2168 2169 /* Return the size of the given address or displacement constant. */ 2170 2171 static unsigned int 2172 h8300_constant_length (rtx constant) 2173 { 2174 /* Check for (@d:16,Reg). */ 2175 if (GET_CODE (constant) == CONST_INT 2176 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff)) 2177 return 2; 2178 2179 /* Check for (@d:16,Reg) in cases where the displacement is 2180 an absolute address. */ 2181 if (Pmode == HImode || h8300_tiny_constant_address_p (constant)) 2182 return 2; 2183 2184 return 4; 2185 } 2186 2187 /* Return the size of a displacement field in address ADDR, which should 2188 have the form (plus X constant). SIZE is the number of bytes being 2189 accessed. */ 2190 2191 static unsigned int 2192 h8300_displacement_length (rtx addr, int size) 2193 { 2194 rtx offset; 2195 2196 offset = XEXP (addr, 1); 2197 2198 /* Check for @(d:2,Reg). */ 2199 if (register_operand (XEXP (addr, 0), VOIDmode) 2200 && GET_CODE (offset) == CONST_INT 2201 && (INTVAL (offset) == size 2202 || INTVAL (offset) == size * 2 2203 || INTVAL (offset) == size * 3)) 2204 return 0; 2205 2206 return h8300_constant_length (offset); 2207 } 2208 2209 /* Store the class of operand OP in *OPCLASS and return the length of any 2210 extra operand fields. SIZE is the number of bytes in OP. OPCLASS 2211 can be null if only the length is needed. */ 2212 2213 static unsigned int 2214 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass) 2215 { 2216 enum h8300_operand_class dummy; 2217 2218 if (opclass == 0) 2219 opclass = &dummy; 2220 2221 if (CONSTANT_P (op)) 2222 { 2223 *opclass = H8OP_IMMEDIATE; 2224 2225 /* Byte-sized immediates are stored in the opcode fields. */ 2226 if (size == 1) 2227 return 0; 2228 2229 /* If this is a 32-bit instruction, see whether the constant 2230 will fit into a 16-bit immediate field. */ 2231 if (TARGET_H8300SX 2232 && size == 4 2233 && GET_CODE (op) == CONST_INT 2234 && IN_RANGE (INTVAL (op), 0, 0xffff)) 2235 return 2; 2236 2237 return size; 2238 } 2239 else if (GET_CODE (op) == MEM) 2240 { 2241 op = XEXP (op, 0); 2242 if (CONSTANT_P (op)) 2243 { 2244 *opclass = H8OP_MEM_ABSOLUTE; 2245 return h8300_constant_length (op); 2246 } 2247 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1))) 2248 { 2249 *opclass = H8OP_MEM_COMPLEX; 2250 return h8300_displacement_length (op, size); 2251 } 2252 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) 2253 { 2254 *opclass = H8OP_MEM_COMPLEX; 2255 return 0; 2256 } 2257 else if (register_operand (op, VOIDmode)) 2258 { 2259 *opclass = H8OP_MEM_BASE; 2260 return 0; 2261 } 2262 } 2263 gcc_assert (register_operand (op, VOIDmode)); 2264 *opclass = H8OP_REGISTER; 2265 return 0; 2266 } 2267 2268 /* Return the length of the instruction described by TABLE given that 2269 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand 2270 and OP2 must be an h8300_src_operand. */ 2271 2272 static unsigned int 2273 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table) 2274 { 2275 enum h8300_operand_class op1_class, op2_class; 2276 unsigned int size, immediate_length; 2277 2278 size = GET_MODE_SIZE (GET_MODE (op1)); 2279 immediate_length = (h8300_classify_operand (op1, size, &op1_class) 2280 + h8300_classify_operand (op2, size, &op2_class)); 2281 return immediate_length + (*table)[op1_class - 1][op2_class]; 2282 } 2283 2284 /* Return the length of a unary instruction such as neg or not given that 2285 its operand is OP. */ 2286 2287 unsigned int 2288 h8300_unary_length (rtx op) 2289 { 2290 enum h8300_operand_class opclass; 2291 unsigned int size, operand_length; 2292 2293 size = GET_MODE_SIZE (GET_MODE (op)); 2294 operand_length = h8300_classify_operand (op, size, &opclass); 2295 switch (opclass) 2296 { 2297 case H8OP_REGISTER: 2298 return 2; 2299 2300 case H8OP_MEM_BASE: 2301 return (size == 4 ? 6 : 4); 2302 2303 case H8OP_MEM_ABSOLUTE: 2304 return operand_length + (size == 4 ? 6 : 4); 2305 2306 case H8OP_MEM_COMPLEX: 2307 return operand_length + 6; 2308 2309 default: 2310 gcc_unreachable (); 2311 } 2312 } 2313 2314 /* Likewise short immediate instructions such as add.w #xx:3,OP. */ 2315 2316 static unsigned int 2317 h8300_short_immediate_length (rtx op) 2318 { 2319 enum h8300_operand_class opclass; 2320 unsigned int size, operand_length; 2321 2322 size = GET_MODE_SIZE (GET_MODE (op)); 2323 operand_length = h8300_classify_operand (op, size, &opclass); 2324 2325 switch (opclass) 2326 { 2327 case H8OP_REGISTER: 2328 return 2; 2329 2330 case H8OP_MEM_BASE: 2331 case H8OP_MEM_ABSOLUTE: 2332 case H8OP_MEM_COMPLEX: 2333 return 4 + operand_length; 2334 2335 default: 2336 gcc_unreachable (); 2337 } 2338 } 2339 2340 /* Likewise bitfield load and store instructions. */ 2341 2342 static unsigned int 2343 h8300_bitfield_length (rtx op, rtx op2) 2344 { 2345 enum h8300_operand_class opclass; 2346 unsigned int size, operand_length; 2347 2348 if (GET_CODE (op) == REG) 2349 op = op2; 2350 gcc_assert (GET_CODE (op) != REG); 2351 2352 size = GET_MODE_SIZE (GET_MODE (op)); 2353 operand_length = h8300_classify_operand (op, size, &opclass); 2354 2355 switch (opclass) 2356 { 2357 case H8OP_MEM_BASE: 2358 case H8OP_MEM_ABSOLUTE: 2359 case H8OP_MEM_COMPLEX: 2360 return 4 + operand_length; 2361 2362 default: 2363 gcc_unreachable (); 2364 } 2365 } 2366 2367 /* Calculate the length of general binary instruction INSN using TABLE. */ 2368 2369 static unsigned int 2370 h8300_binary_length (rtx insn, const h8300_length_table *table) 2371 { 2372 rtx set; 2373 2374 set = single_set (insn); 2375 gcc_assert (set); 2376 2377 if (BINARY_P (SET_SRC (set))) 2378 return h8300_length_from_table (XEXP (SET_SRC (set), 0), 2379 XEXP (SET_SRC (set), 1), table); 2380 else 2381 { 2382 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY); 2383 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0), 2384 XEXP (XEXP (SET_SRC (set), 1), 1), 2385 table); 2386 } 2387 } 2388 2389 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte 2390 memory reference and either (1) it has the form @(d:16,Rn) or 2391 (2) its address has the code given by INC_CODE. */ 2392 2393 static bool 2394 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code) 2395 { 2396 rtx addr; 2397 unsigned int size; 2398 2399 if (GET_CODE (op) != MEM) 2400 return false; 2401 2402 addr = XEXP (op, 0); 2403 size = GET_MODE_SIZE (GET_MODE (op)); 2404 if (size != 1 && size != 2) 2405 return false; 2406 2407 return (GET_CODE (addr) == inc_code 2408 || (GET_CODE (addr) == PLUS 2409 && GET_CODE (XEXP (addr, 0)) == REG 2410 && h8300_displacement_length (addr, size) == 2)); 2411 } 2412 2413 /* Calculate the length of move instruction INSN using the given length 2414 table. Although the tables are correct for most cases, there is some 2415 irregularity in the length of mov.b and mov.w. The following forms: 2416 2417 mov @ERs+, Rd 2418 mov @(d:16,ERs), Rd 2419 mov Rs, @-ERd 2420 mov Rs, @(d:16,ERd) 2421 2422 are two bytes shorter than most other "mov Rs, @complex" or 2423 "mov @complex,Rd" combinations. */ 2424 2425 static unsigned int 2426 h8300_move_length (rtx *operands, const h8300_length_table *table) 2427 { 2428 unsigned int size; 2429 2430 size = h8300_length_from_table (operands[0], operands[1], table); 2431 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC)) 2432 size -= 2; 2433 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC)) 2434 size -= 2; 2435 return size; 2436 } 2437 2438 /* Return the length of a mova instruction with the given operands. 2439 DEST is the register destination, SRC is the source address and 2440 OFFSET is the 16-bit or 32-bit displacement. */ 2441 2442 static unsigned int 2443 h8300_mova_length (rtx dest, rtx src, rtx offset) 2444 { 2445 unsigned int size; 2446 2447 size = (2 2448 + h8300_constant_length (offset) 2449 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0)); 2450 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest)) 2451 size += 2; 2452 return size; 2453 } 2454 2455 /* Compute the length of INSN based on its length_table attribute. 2456 OPERANDS is the array of its operands. */ 2457 2458 unsigned int 2459 h8300_insn_length_from_table (rtx insn, rtx * operands) 2460 { 2461 switch (get_attr_length_table (insn)) 2462 { 2463 case LENGTH_TABLE_NONE: 2464 gcc_unreachable (); 2465 2466 case LENGTH_TABLE_ADDB: 2467 return h8300_binary_length (insn, &addb_length_table); 2468 2469 case LENGTH_TABLE_ADDW: 2470 return h8300_binary_length (insn, &addw_length_table); 2471 2472 case LENGTH_TABLE_ADDL: 2473 return h8300_binary_length (insn, &addl_length_table); 2474 2475 case LENGTH_TABLE_LOGICB: 2476 return h8300_binary_length (insn, &logicb_length_table); 2477 2478 case LENGTH_TABLE_MOVB: 2479 return h8300_move_length (operands, &movb_length_table); 2480 2481 case LENGTH_TABLE_MOVW: 2482 return h8300_move_length (operands, &movw_length_table); 2483 2484 case LENGTH_TABLE_MOVL: 2485 return h8300_move_length (operands, &movl_length_table); 2486 2487 case LENGTH_TABLE_MOVA: 2488 return h8300_mova_length (operands[0], operands[1], operands[2]); 2489 2490 case LENGTH_TABLE_MOVA_ZERO: 2491 return h8300_mova_length (operands[0], operands[1], const0_rtx); 2492 2493 case LENGTH_TABLE_UNARY: 2494 return h8300_unary_length (operands[0]); 2495 2496 case LENGTH_TABLE_MOV_IMM4: 2497 return 2 + h8300_classify_operand (operands[0], 0, 0); 2498 2499 case LENGTH_TABLE_SHORT_IMMEDIATE: 2500 return h8300_short_immediate_length (operands[0]); 2501 2502 case LENGTH_TABLE_BITFIELD: 2503 return h8300_bitfield_length (operands[0], operands[1]); 2504 2505 case LENGTH_TABLE_BITBRANCH: 2506 return h8300_bitfield_length (operands[1], operands[2]) - 2; 2507 2508 default: 2509 gcc_unreachable (); 2510 } 2511 } 2512 2513 /* Return true if LHS and RHS are memory references that can be mapped 2514 to the same h8sx assembly operand. LHS appears as the destination of 2515 an instruction and RHS appears as a source. 2516 2517 Three cases are allowed: 2518 2519 - RHS is @+Rn or @-Rn, LHS is @Rn 2520 - RHS is @Rn, LHS is @Rn+ or @Rn- 2521 - RHS and LHS have the same address and neither has side effects. */ 2522 2523 bool 2524 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs) 2525 { 2526 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM) 2527 { 2528 rhs = XEXP (rhs, 0); 2529 lhs = XEXP (lhs, 0); 2530 2531 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC) 2532 return rtx_equal_p (XEXP (rhs, 0), lhs); 2533 2534 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC) 2535 return rtx_equal_p (rhs, XEXP (lhs, 0)); 2536 2537 if (rtx_equal_p (rhs, lhs)) 2538 return true; 2539 } 2540 return false; 2541 } 2542 2543 /* Return true if OPERANDS[1] can be mapped to the same assembly 2544 operand as OPERANDS[0]. */ 2545 2546 bool 2547 h8300_operands_match_p (rtx *operands) 2548 { 2549 if (register_operand (operands[0], VOIDmode) 2550 && register_operand (operands[1], VOIDmode)) 2551 return true; 2552 2553 if (h8sx_mergeable_memrefs_p (operands[0], operands[1])) 2554 return true; 2555 2556 return false; 2557 } 2558 2559 /* Try using movmd to move LENGTH bytes from memory region SRC to memory 2560 region DEST. The two regions do not overlap and have the common 2561 alignment given by ALIGNMENT. Return true on success. 2562 2563 Using movmd for variable-length moves seems to involve some 2564 complex trade-offs. For instance: 2565 2566 - Preparing for a movmd instruction is similar to preparing 2567 for a memcpy. The main difference is that the arguments 2568 are moved into er4, er5 and er6 rather than er0, er1 and er2. 2569 2570 - Since movmd clobbers the frame pointer, we need to save 2571 and restore it somehow when frame_pointer_needed. This can 2572 sometimes make movmd sequences longer than calls to memcpy(). 2573 2574 - The counter register is 16 bits, so the instruction is only 2575 suitable for variable-length moves when sizeof (size_t) == 2. 2576 That's only true in normal mode. 2577 2578 - We will often lack static alignment information. Falling back 2579 on movmd.b would likely be slower than calling memcpy(), at least 2580 for big moves. 2581 2582 This function therefore only uses movmd when the length is a 2583 known constant, and only then if -fomit-frame-pointer is in 2584 effect or if we're not optimizing for size. 2585 2586 At the moment the function uses movmd for all in-range constants, 2587 but it might be better to fall back on memcpy() for large moves 2588 if ALIGNMENT == 1. */ 2589 2590 bool 2591 h8sx_emit_movmd (rtx dest, rtx src, rtx length, 2592 HOST_WIDE_INT alignment) 2593 { 2594 if (!flag_omit_frame_pointer && optimize_size) 2595 return false; 2596 2597 if (GET_CODE (length) == CONST_INT) 2598 { 2599 rtx dest_reg, src_reg, first_dest, first_src; 2600 HOST_WIDE_INT n; 2601 int factor; 2602 2603 /* Use movmd.l if the alignment allows it, otherwise fall back 2604 on movmd.b. */ 2605 factor = (alignment >= 2 ? 4 : 1); 2606 2607 /* Make sure the length is within range. We can handle counter 2608 values up to 65536, although HImode truncation will make 2609 the count appear negative in rtl dumps. */ 2610 n = INTVAL (length); 2611 if (n <= 0 || n / factor > 65536) 2612 return false; 2613 2614 /* Create temporary registers for the source and destination 2615 pointers. Initialize them to the start of each region. */ 2616 dest_reg = copy_addr_to_reg (XEXP (dest, 0)); 2617 src_reg = copy_addr_to_reg (XEXP (src, 0)); 2618 2619 /* Create references to the movmd source and destination blocks. */ 2620 first_dest = replace_equiv_address (dest, dest_reg); 2621 first_src = replace_equiv_address (src, src_reg); 2622 2623 set_mem_size (first_dest, GEN_INT (n & -factor)); 2624 set_mem_size (first_src, GEN_INT (n & -factor)); 2625 2626 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode)); 2627 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor))); 2628 2629 if ((n & -factor) != n) 2630 { 2631 /* Move SRC and DEST past the region we just copied. 2632 This is done to update the memory attributes. */ 2633 dest = adjust_address (dest, BLKmode, n & -factor); 2634 src = adjust_address (src, BLKmode, n & -factor); 2635 2636 /* Replace the addresses with the source and destination 2637 registers, which movmd has left with the right values. */ 2638 dest = replace_equiv_address (dest, dest_reg); 2639 src = replace_equiv_address (src, src_reg); 2640 2641 /* Mop up the left-over bytes. */ 2642 if (n & 2) 2643 emit_move_insn (adjust_address (dest, HImode, 0), 2644 adjust_address (src, HImode, 0)); 2645 if (n & 1) 2646 emit_move_insn (adjust_address (dest, QImode, n & 2), 2647 adjust_address (src, QImode, n & 2)); 2648 } 2649 return true; 2650 } 2651 return false; 2652 } 2653 2654 /* Move ADDR into er6 after pushing its old value onto the stack. */ 2655 2656 void 2657 h8300_swap_into_er6 (rtx addr) 2658 { 2659 push (HARD_FRAME_POINTER_REGNUM); 2660 emit_move_insn (hard_frame_pointer_rtx, addr); 2661 if (REGNO (addr) == SP_REG) 2662 emit_move_insn (hard_frame_pointer_rtx, 2663 plus_constant (hard_frame_pointer_rtx, 2664 GET_MODE_SIZE (word_mode))); 2665 } 2666 2667 /* Move the current value of er6 into ADDR and pop its old value 2668 from the stack. */ 2669 2670 void 2671 h8300_swap_out_of_er6 (rtx addr) 2672 { 2673 if (REGNO (addr) != SP_REG) 2674 emit_move_insn (addr, hard_frame_pointer_rtx); 2675 pop (HARD_FRAME_POINTER_REGNUM); 2676 } 2677 2678 /* Return the length of mov instruction. */ 2679 2680 unsigned int 2681 compute_mov_length (rtx *operands) 2682 { 2683 /* If the mov instruction involves a memory operand, we compute the 2684 length, assuming the largest addressing mode is used, and then 2685 adjust later in the function. Otherwise, we compute and return 2686 the exact length in one step. */ 2687 enum machine_mode mode = GET_MODE (operands[0]); 2688 rtx dest = operands[0]; 2689 rtx src = operands[1]; 2690 rtx addr; 2691 2692 if (GET_CODE (src) == MEM) 2693 addr = XEXP (src, 0); 2694 else if (GET_CODE (dest) == MEM) 2695 addr = XEXP (dest, 0); 2696 else 2697 addr = NULL_RTX; 2698 2699 if (TARGET_H8300) 2700 { 2701 unsigned int base_length; 2702 2703 switch (mode) 2704 { 2705 case QImode: 2706 if (addr == NULL_RTX) 2707 return 2; 2708 2709 /* The eightbit addressing is available only in QImode, so 2710 go ahead and take care of it. */ 2711 if (h8300_eightbit_constant_address_p (addr)) 2712 return 2; 2713 2714 base_length = 4; 2715 break; 2716 2717 case HImode: 2718 if (addr == NULL_RTX) 2719 { 2720 if (REG_P (src)) 2721 return 2; 2722 2723 if (src == const0_rtx) 2724 return 2; 2725 2726 return 4; 2727 } 2728 2729 base_length = 4; 2730 break; 2731 2732 case SImode: 2733 if (addr == NULL_RTX) 2734 { 2735 if (REG_P (src)) 2736 return 4; 2737 2738 if (GET_CODE (src) == CONST_INT) 2739 { 2740 if (src == const0_rtx) 2741 return 4; 2742 2743 if ((INTVAL (src) & 0xffff) == 0) 2744 return 6; 2745 2746 if ((INTVAL (src) & 0xffff) == 0) 2747 return 6; 2748 2749 if ((INTVAL (src) & 0xffff) 2750 == ((INTVAL (src) >> 16) & 0xffff)) 2751 return 6; 2752 } 2753 return 8; 2754 } 2755 2756 base_length = 8; 2757 break; 2758 2759 case SFmode: 2760 if (addr == NULL_RTX) 2761 { 2762 if (REG_P (src)) 2763 return 4; 2764 2765 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G')) 2766 return 4; 2767 2768 return 8; 2769 } 2770 2771 base_length = 8; 2772 break; 2773 2774 default: 2775 gcc_unreachable (); 2776 } 2777 2778 /* Adjust the length based on the addressing mode used. 2779 Specifically, we subtract the difference between the actual 2780 length and the longest one, which is @(d:16,Rs). For SImode 2781 and SFmode, we double the adjustment because two mov.w are 2782 used to do the job. */ 2783 2784 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */ 2785 if (GET_CODE (addr) == PRE_DEC 2786 || GET_CODE (addr) == POST_INC) 2787 { 2788 if (mode == QImode || mode == HImode) 2789 return base_length - 2; 2790 else 2791 /* In SImode and SFmode, we use two mov.w instructions, so 2792 double the adjustment. */ 2793 return base_length - 4; 2794 } 2795 2796 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that 2797 in SImode and SFmode, the second mov.w involves an address 2798 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract 2799 only 2 bytes. */ 2800 if (GET_CODE (addr) == REG) 2801 return base_length - 2; 2802 2803 return base_length; 2804 } 2805 else 2806 { 2807 unsigned int base_length; 2808 2809 switch (mode) 2810 { 2811 case QImode: 2812 if (addr == NULL_RTX) 2813 return 2; 2814 2815 /* The eightbit addressing is available only in QImode, so 2816 go ahead and take care of it. */ 2817 if (h8300_eightbit_constant_address_p (addr)) 2818 return 2; 2819 2820 base_length = 8; 2821 break; 2822 2823 case HImode: 2824 if (addr == NULL_RTX) 2825 { 2826 if (REG_P (src)) 2827 return 2; 2828 2829 if (src == const0_rtx) 2830 return 2; 2831 2832 return 4; 2833 } 2834 2835 base_length = 8; 2836 break; 2837 2838 case SImode: 2839 if (addr == NULL_RTX) 2840 { 2841 if (REG_P (src)) 2842 { 2843 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG) 2844 return 4; 2845 else 2846 return 2; 2847 } 2848 2849 if (GET_CODE (src) == CONST_INT) 2850 { 2851 int val = INTVAL (src); 2852 2853 if (val == 0) 2854 return 2; 2855 2856 if (val == (val & 0x00ff) || val == (val & 0xff00)) 2857 return 4; 2858 2859 switch (val & 0xffffffff) 2860 { 2861 case 0xffffffff: 2862 case 0xfffffffe: 2863 case 0xfffffffc: 2864 case 0x0000ffff: 2865 case 0x0000fffe: 2866 case 0xffff0000: 2867 case 0xfffe0000: 2868 case 0x00010000: 2869 case 0x00020000: 2870 return 4; 2871 } 2872 } 2873 return 6; 2874 } 2875 2876 base_length = 10; 2877 break; 2878 2879 case SFmode: 2880 if (addr == NULL_RTX) 2881 { 2882 if (REG_P (src)) 2883 return 2; 2884 2885 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G')) 2886 return 2; 2887 2888 return 6; 2889 } 2890 2891 base_length = 10; 2892 break; 2893 2894 default: 2895 gcc_unreachable (); 2896 } 2897 2898 /* Adjust the length based on the addressing mode used. 2899 Specifically, we subtract the difference between the actual 2900 length and the longest one, which is @(d:24,ERs). */ 2901 2902 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */ 2903 if (GET_CODE (addr) == PRE_DEC 2904 || GET_CODE (addr) == POST_INC) 2905 return base_length - 6; 2906 2907 /* @ERs and @ERd are 6 bytes shorter than the longest. */ 2908 if (GET_CODE (addr) == REG) 2909 return base_length - 6; 2910 2911 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the 2912 longest. */ 2913 if (GET_CODE (addr) == PLUS 2914 && GET_CODE (XEXP (addr, 0)) == REG 2915 && GET_CODE (XEXP (addr, 1)) == CONST_INT 2916 && INTVAL (XEXP (addr, 1)) > -32768 2917 && INTVAL (XEXP (addr, 1)) < 32767) 2918 return base_length - 4; 2919 2920 /* @aa:16 is 4 bytes shorter than the longest. */ 2921 if (h8300_tiny_constant_address_p (addr)) 2922 return base_length - 4; 2923 2924 /* @aa:24 is 2 bytes shorter than the longest. */ 2925 if (CONSTANT_P (addr)) 2926 return base_length - 2; 2927 2928 return base_length; 2929 } 2930 } 2931 2932 /* Output an addition insn. */ 2933 2934 const char * 2935 output_plussi (rtx *operands) 2936 { 2937 enum machine_mode mode = GET_MODE (operands[0]); 2938 2939 gcc_assert (mode == SImode); 2940 2941 if (TARGET_H8300) 2942 { 2943 if (GET_CODE (operands[2]) == REG) 2944 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; 2945 2946 if (GET_CODE (operands[2]) == CONST_INT) 2947 { 2948 HOST_WIDE_INT n = INTVAL (operands[2]); 2949 2950 if ((n & 0xffffff) == 0) 2951 return "add\t%z2,%z0"; 2952 if ((n & 0xffff) == 0) 2953 return "add\t%y2,%y0\n\taddx\t%z2,%z0"; 2954 if ((n & 0xff) == 0) 2955 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; 2956 } 2957 2958 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; 2959 } 2960 else 2961 { 2962 if (GET_CODE (operands[2]) == CONST_INT 2963 && register_operand (operands[1], VOIDmode)) 2964 { 2965 HOST_WIDE_INT intval = INTVAL (operands[2]); 2966 2967 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 2968 return "add.l\t%S2,%S0"; 2969 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 2970 return "sub.l\t%G2,%S0"; 2971 2972 /* See if we can finish with 2 bytes. */ 2973 2974 switch ((unsigned int) intval & 0xffffffff) 2975 { 2976 case 0x00000001: 2977 case 0x00000002: 2978 case 0x00000004: 2979 return "adds\t%2,%S0"; 2980 2981 case 0xffffffff: 2982 case 0xfffffffe: 2983 case 0xfffffffc: 2984 return "subs\t%G2,%S0"; 2985 2986 case 0x00010000: 2987 case 0x00020000: 2988 operands[2] = GEN_INT (intval >> 16); 2989 return "inc.w\t%2,%e0"; 2990 2991 case 0xffff0000: 2992 case 0xfffe0000: 2993 operands[2] = GEN_INT (intval >> 16); 2994 return "dec.w\t%G2,%e0"; 2995 } 2996 2997 /* See if we can finish with 4 bytes. */ 2998 if ((intval & 0xffff) == 0) 2999 { 3000 operands[2] = GEN_INT (intval >> 16); 3001 return "add.w\t%2,%e0"; 3002 } 3003 } 3004 3005 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 3006 { 3007 operands[2] = GEN_INT (-INTVAL (operands[2])); 3008 return "sub.l\t%S2,%S0"; 3009 } 3010 return "add.l\t%S2,%S0"; 3011 } 3012 } 3013 3014 /* ??? It would be much easier to add the h8sx stuff if a single function 3015 classified the addition as either inc/dec, adds/subs, add.w or add.l. */ 3016 /* Compute the length of an addition insn. */ 3017 3018 unsigned int 3019 compute_plussi_length (rtx *operands) 3020 { 3021 enum machine_mode mode = GET_MODE (operands[0]); 3022 3023 gcc_assert (mode == SImode); 3024 3025 if (TARGET_H8300) 3026 { 3027 if (GET_CODE (operands[2]) == REG) 3028 return 6; 3029 3030 if (GET_CODE (operands[2]) == CONST_INT) 3031 { 3032 HOST_WIDE_INT n = INTVAL (operands[2]); 3033 3034 if ((n & 0xffffff) == 0) 3035 return 2; 3036 if ((n & 0xffff) == 0) 3037 return 4; 3038 if ((n & 0xff) == 0) 3039 return 6; 3040 } 3041 3042 return 8; 3043 } 3044 else 3045 { 3046 if (GET_CODE (operands[2]) == CONST_INT 3047 && register_operand (operands[1], VOIDmode)) 3048 { 3049 HOST_WIDE_INT intval = INTVAL (operands[2]); 3050 3051 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 3052 return 2; 3053 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 3054 return 2; 3055 3056 /* See if we can finish with 2 bytes. */ 3057 3058 switch ((unsigned int) intval & 0xffffffff) 3059 { 3060 case 0x00000001: 3061 case 0x00000002: 3062 case 0x00000004: 3063 return 2; 3064 3065 case 0xffffffff: 3066 case 0xfffffffe: 3067 case 0xfffffffc: 3068 return 2; 3069 3070 case 0x00010000: 3071 case 0x00020000: 3072 return 2; 3073 3074 case 0xffff0000: 3075 case 0xfffe0000: 3076 return 2; 3077 } 3078 3079 /* See if we can finish with 4 bytes. */ 3080 if ((intval & 0xffff) == 0) 3081 return 4; 3082 } 3083 3084 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 3085 return h8300_length_from_table (operands[0], 3086 GEN_INT (-INTVAL (operands[2])), 3087 &addl_length_table); 3088 else 3089 return h8300_length_from_table (operands[0], operands[2], 3090 &addl_length_table); 3091 return 6; 3092 } 3093 } 3094 3095 /* Compute which flag bits are valid after an addition insn. */ 3096 3097 int 3098 compute_plussi_cc (rtx *operands) 3099 { 3100 enum machine_mode mode = GET_MODE (operands[0]); 3101 3102 gcc_assert (mode == SImode); 3103 3104 if (TARGET_H8300) 3105 { 3106 return CC_CLOBBER; 3107 } 3108 else 3109 { 3110 if (GET_CODE (operands[2]) == CONST_INT 3111 && register_operand (operands[1], VOIDmode)) 3112 { 3113 HOST_WIDE_INT intval = INTVAL (operands[2]); 3114 3115 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 3116 return CC_SET_ZN; 3117 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 3118 return CC_SET_ZN; 3119 3120 /* See if we can finish with 2 bytes. */ 3121 3122 switch ((unsigned int) intval & 0xffffffff) 3123 { 3124 case 0x00000001: 3125 case 0x00000002: 3126 case 0x00000004: 3127 return CC_NONE_0HIT; 3128 3129 case 0xffffffff: 3130 case 0xfffffffe: 3131 case 0xfffffffc: 3132 return CC_NONE_0HIT; 3133 3134 case 0x00010000: 3135 case 0x00020000: 3136 return CC_CLOBBER; 3137 3138 case 0xffff0000: 3139 case 0xfffe0000: 3140 return CC_CLOBBER; 3141 } 3142 3143 /* See if we can finish with 4 bytes. */ 3144 if ((intval & 0xffff) == 0) 3145 return CC_CLOBBER; 3146 } 3147 3148 return CC_SET_ZN; 3149 } 3150 } 3151 3152 /* Output a logical insn. */ 3153 3154 const char * 3155 output_logical_op (enum machine_mode mode, rtx *operands) 3156 { 3157 /* Figure out the logical op that we need to perform. */ 3158 enum rtx_code code = GET_CODE (operands[3]); 3159 /* Pretend that every byte is affected if both operands are registers. */ 3160 const unsigned HOST_WIDE_INT intval = 3161 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3162 /* Always use the full instruction if the 3163 first operand is in memory. It is better 3164 to use define_splits to generate the shorter 3165 sequence where valid. */ 3166 && register_operand (operands[1], VOIDmode) 3167 ? INTVAL (operands[2]) : 0x55555555); 3168 /* The determinant of the algorithm. If we perform an AND, 0 3169 affects a bit. Otherwise, 1 affects a bit. */ 3170 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3171 /* Break up DET into pieces. */ 3172 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3173 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3174 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; 3175 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; 3176 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3177 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3178 int lower_half_easy_p = 0; 3179 int upper_half_easy_p = 0; 3180 /* The name of an insn. */ 3181 const char *opname; 3182 char insn_buf[100]; 3183 3184 switch (code) 3185 { 3186 case AND: 3187 opname = "and"; 3188 break; 3189 case IOR: 3190 opname = "or"; 3191 break; 3192 case XOR: 3193 opname = "xor"; 3194 break; 3195 default: 3196 gcc_unreachable (); 3197 } 3198 3199 switch (mode) 3200 { 3201 case HImode: 3202 /* First, see if we can finish with one insn. */ 3203 if ((TARGET_H8300H || TARGET_H8300S) 3204 && b0 != 0 3205 && b1 != 0) 3206 { 3207 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname); 3208 output_asm_insn (insn_buf, operands); 3209 } 3210 else 3211 { 3212 /* Take care of the lower byte. */ 3213 if (b0 != 0) 3214 { 3215 sprintf (insn_buf, "%s\t%%s2,%%s0", opname); 3216 output_asm_insn (insn_buf, operands); 3217 } 3218 /* Take care of the upper byte. */ 3219 if (b1 != 0) 3220 { 3221 sprintf (insn_buf, "%s\t%%t2,%%t0", opname); 3222 output_asm_insn (insn_buf, operands); 3223 } 3224 } 3225 break; 3226 case SImode: 3227 if (TARGET_H8300H || TARGET_H8300S) 3228 { 3229 /* Determine if the lower half can be taken care of in no more 3230 than two bytes. */ 3231 lower_half_easy_p = (b0 == 0 3232 || b1 == 0 3233 || (code != IOR && w0 == 0xffff)); 3234 3235 /* Determine if the upper half can be taken care of in no more 3236 than two bytes. */ 3237 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3238 || (code == AND && w1 == 0xff00)); 3239 } 3240 3241 /* Check if doing everything with one insn is no worse than 3242 using multiple insns. */ 3243 if ((TARGET_H8300H || TARGET_H8300S) 3244 && w0 != 0 && w1 != 0 3245 && !(lower_half_easy_p && upper_half_easy_p) 3246 && !(code == IOR && w1 == 0xffff 3247 && (w0 & 0x8000) != 0 && lower_half_easy_p)) 3248 { 3249 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname); 3250 output_asm_insn (insn_buf, operands); 3251 } 3252 else 3253 { 3254 /* Take care of the lower and upper words individually. For 3255 each word, we try different methods in the order of 3256 3257 1) the special insn (in case of AND or XOR), 3258 2) the word-wise insn, and 3259 3) The byte-wise insn. */ 3260 if (w0 == 0xffff 3261 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3262 output_asm_insn ((code == AND) 3263 ? "sub.w\t%f0,%f0" : "not.w\t%f0", 3264 operands); 3265 else if ((TARGET_H8300H || TARGET_H8300S) 3266 && (b0 != 0) 3267 && (b1 != 0)) 3268 { 3269 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname); 3270 output_asm_insn (insn_buf, operands); 3271 } 3272 else 3273 { 3274 if (b0 != 0) 3275 { 3276 sprintf (insn_buf, "%s\t%%w2,%%w0", opname); 3277 output_asm_insn (insn_buf, operands); 3278 } 3279 if (b1 != 0) 3280 { 3281 sprintf (insn_buf, "%s\t%%x2,%%x0", opname); 3282 output_asm_insn (insn_buf, operands); 3283 } 3284 } 3285 3286 if ((w1 == 0xffff) 3287 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3288 output_asm_insn ((code == AND) 3289 ? "sub.w\t%e0,%e0" : "not.w\t%e0", 3290 operands); 3291 else if ((TARGET_H8300H || TARGET_H8300S) 3292 && code == IOR 3293 && w1 == 0xffff 3294 && (w0 & 0x8000) != 0) 3295 { 3296 output_asm_insn ("exts.l\t%S0", operands); 3297 } 3298 else if ((TARGET_H8300H || TARGET_H8300S) 3299 && code == AND 3300 && w1 == 0xff00) 3301 { 3302 output_asm_insn ("extu.w\t%e0", operands); 3303 } 3304 else if (TARGET_H8300H || TARGET_H8300S) 3305 { 3306 if (w1 != 0) 3307 { 3308 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname); 3309 output_asm_insn (insn_buf, operands); 3310 } 3311 } 3312 else 3313 { 3314 if (b2 != 0) 3315 { 3316 sprintf (insn_buf, "%s\t%%y2,%%y0", opname); 3317 output_asm_insn (insn_buf, operands); 3318 } 3319 if (b3 != 0) 3320 { 3321 sprintf (insn_buf, "%s\t%%z2,%%z0", opname); 3322 output_asm_insn (insn_buf, operands); 3323 } 3324 } 3325 } 3326 break; 3327 default: 3328 gcc_unreachable (); 3329 } 3330 return ""; 3331 } 3332 3333 /* Compute the length of a logical insn. */ 3334 3335 unsigned int 3336 compute_logical_op_length (enum machine_mode mode, rtx *operands) 3337 { 3338 /* Figure out the logical op that we need to perform. */ 3339 enum rtx_code code = GET_CODE (operands[3]); 3340 /* Pretend that every byte is affected if both operands are registers. */ 3341 const unsigned HOST_WIDE_INT intval = 3342 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3343 /* Always use the full instruction if the 3344 first operand is in memory. It is better 3345 to use define_splits to generate the shorter 3346 sequence where valid. */ 3347 && register_operand (operands[1], VOIDmode) 3348 ? INTVAL (operands[2]) : 0x55555555); 3349 /* The determinant of the algorithm. If we perform an AND, 0 3350 affects a bit. Otherwise, 1 affects a bit. */ 3351 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3352 /* Break up DET into pieces. */ 3353 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3354 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3355 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; 3356 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; 3357 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3358 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3359 int lower_half_easy_p = 0; 3360 int upper_half_easy_p = 0; 3361 /* Insn length. */ 3362 unsigned int length = 0; 3363 3364 switch (mode) 3365 { 3366 case HImode: 3367 /* First, see if we can finish with one insn. */ 3368 if ((TARGET_H8300H || TARGET_H8300S) 3369 && b0 != 0 3370 && b1 != 0) 3371 { 3372 length = h8300_length_from_table (operands[1], operands[2], 3373 &logicw_length_table); 3374 } 3375 else 3376 { 3377 /* Take care of the lower byte. */ 3378 if (b0 != 0) 3379 length += 2; 3380 3381 /* Take care of the upper byte. */ 3382 if (b1 != 0) 3383 length += 2; 3384 } 3385 break; 3386 case SImode: 3387 if (TARGET_H8300H || TARGET_H8300S) 3388 { 3389 /* Determine if the lower half can be taken care of in no more 3390 than two bytes. */ 3391 lower_half_easy_p = (b0 == 0 3392 || b1 == 0 3393 || (code != IOR && w0 == 0xffff)); 3394 3395 /* Determine if the upper half can be taken care of in no more 3396 than two bytes. */ 3397 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3398 || (code == AND && w1 == 0xff00)); 3399 } 3400 3401 /* Check if doing everything with one insn is no worse than 3402 using multiple insns. */ 3403 if ((TARGET_H8300H || TARGET_H8300S) 3404 && w0 != 0 && w1 != 0 3405 && !(lower_half_easy_p && upper_half_easy_p) 3406 && !(code == IOR && w1 == 0xffff 3407 && (w0 & 0x8000) != 0 && lower_half_easy_p)) 3408 { 3409 length = h8300_length_from_table (operands[1], operands[2], 3410 &logicl_length_table); 3411 } 3412 else 3413 { 3414 /* Take care of the lower and upper words individually. For 3415 each word, we try different methods in the order of 3416 3417 1) the special insn (in case of AND or XOR), 3418 2) the word-wise insn, and 3419 3) The byte-wise insn. */ 3420 if (w0 == 0xffff 3421 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3422 { 3423 length += 2; 3424 } 3425 else if ((TARGET_H8300H || TARGET_H8300S) 3426 && (b0 != 0) 3427 && (b1 != 0)) 3428 { 3429 length += 4; 3430 } 3431 else 3432 { 3433 if (b0 != 0) 3434 length += 2; 3435 3436 if (b1 != 0) 3437 length += 2; 3438 } 3439 3440 if (w1 == 0xffff 3441 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3442 { 3443 length += 2; 3444 } 3445 else if ((TARGET_H8300H || TARGET_H8300S) 3446 && code == IOR 3447 && w1 == 0xffff 3448 && (w0 & 0x8000) != 0) 3449 { 3450 length += 2; 3451 } 3452 else if ((TARGET_H8300H || TARGET_H8300S) 3453 && code == AND 3454 && w1 == 0xff00) 3455 { 3456 length += 2; 3457 } 3458 else if (TARGET_H8300H || TARGET_H8300S) 3459 { 3460 if (w1 != 0) 3461 length += 4; 3462 } 3463 else 3464 { 3465 if (b2 != 0) 3466 length += 2; 3467 3468 if (b3 != 0) 3469 length += 2; 3470 } 3471 } 3472 break; 3473 default: 3474 gcc_unreachable (); 3475 } 3476 return length; 3477 } 3478 3479 /* Compute which flag bits are valid after a logical insn. */ 3480 3481 int 3482 compute_logical_op_cc (enum machine_mode mode, rtx *operands) 3483 { 3484 /* Figure out the logical op that we need to perform. */ 3485 enum rtx_code code = GET_CODE (operands[3]); 3486 /* Pretend that every byte is affected if both operands are registers. */ 3487 const unsigned HOST_WIDE_INT intval = 3488 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3489 /* Always use the full instruction if the 3490 first operand is in memory. It is better 3491 to use define_splits to generate the shorter 3492 sequence where valid. */ 3493 && register_operand (operands[1], VOIDmode) 3494 ? INTVAL (operands[2]) : 0x55555555); 3495 /* The determinant of the algorithm. If we perform an AND, 0 3496 affects a bit. Otherwise, 1 affects a bit. */ 3497 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3498 /* Break up DET into pieces. */ 3499 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3500 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3501 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3502 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3503 int lower_half_easy_p = 0; 3504 int upper_half_easy_p = 0; 3505 /* Condition code. */ 3506 enum attr_cc cc = CC_CLOBBER; 3507 3508 switch (mode) 3509 { 3510 case HImode: 3511 /* First, see if we can finish with one insn. */ 3512 if ((TARGET_H8300H || TARGET_H8300S) 3513 && b0 != 0 3514 && b1 != 0) 3515 { 3516 cc = CC_SET_ZNV; 3517 } 3518 break; 3519 case SImode: 3520 if (TARGET_H8300H || TARGET_H8300S) 3521 { 3522 /* Determine if the lower half can be taken care of in no more 3523 than two bytes. */ 3524 lower_half_easy_p = (b0 == 0 3525 || b1 == 0 3526 || (code != IOR && w0 == 0xffff)); 3527 3528 /* Determine if the upper half can be taken care of in no more 3529 than two bytes. */ 3530 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3531 || (code == AND && w1 == 0xff00)); 3532 } 3533 3534 /* Check if doing everything with one insn is no worse than 3535 using multiple insns. */ 3536 if ((TARGET_H8300H || TARGET_H8300S) 3537 && w0 != 0 && w1 != 0 3538 && !(lower_half_easy_p && upper_half_easy_p) 3539 && !(code == IOR && w1 == 0xffff 3540 && (w0 & 0x8000) != 0 && lower_half_easy_p)) 3541 { 3542 cc = CC_SET_ZNV; 3543 } 3544 else 3545 { 3546 if ((TARGET_H8300H || TARGET_H8300S) 3547 && code == IOR 3548 && w1 == 0xffff 3549 && (w0 & 0x8000) != 0) 3550 { 3551 cc = CC_SET_ZNV; 3552 } 3553 } 3554 break; 3555 default: 3556 gcc_unreachable (); 3557 } 3558 return cc; 3559 } 3560 3561 /* Expand a conditional branch. */ 3562 3563 void 3564 h8300_expand_branch (rtx operands[]) 3565 { 3566 enum rtx_code code = GET_CODE (operands[0]); 3567 rtx op0 = operands[1]; 3568 rtx op1 = operands[2]; 3569 rtx label = operands[3]; 3570 rtx tmp; 3571 3572 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); 3573 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp)); 3574 3575 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx); 3576 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 3577 gen_rtx_LABEL_REF (VOIDmode, label), 3578 pc_rtx); 3579 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); 3580 } 3581 3582 3583 /* Expand a conditional store. */ 3584 3585 void 3586 h8300_expand_store (rtx operands[]) 3587 { 3588 rtx dest = operands[0]; 3589 enum rtx_code code = GET_CODE (operands[1]); 3590 rtx op0 = operands[2]; 3591 rtx op1 = operands[3]; 3592 rtx tmp; 3593 3594 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); 3595 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp)); 3596 3597 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx); 3598 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); 3599 } 3600 3601 /* Shifts. 3602 3603 We devote a fair bit of code to getting efficient shifts since we 3604 can only shift one bit at a time on the H8/300 and H8/300H and only 3605 one or two bits at a time on the H8S. 3606 3607 All shift code falls into one of the following ways of 3608 implementation: 3609 3610 o SHIFT_INLINE: Emit straight line code for the shift; this is used 3611 when a straight line shift is about the same size or smaller than 3612 a loop. 3613 3614 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask 3615 off the bits we don't need. This is used when only a few of the 3616 bits in the original value will survive in the shifted value. 3617 3618 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to 3619 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline 3620 shifts can be added if the shift count is slightly more than 8 or 3621 16. This case also includes other oddballs that are not worth 3622 explaining here. 3623 3624 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts. 3625 3626 For each shift count, we try to use code that has no trade-off 3627 between code size and speed whenever possible. 3628 3629 If the trade-off is unavoidable, we try to be reasonable. 3630 Specifically, the fastest version is one instruction longer than 3631 the shortest version, we take the fastest version. We also provide 3632 the use a way to switch back to the shortest version with -Os. 3633 3634 For the details of the shift algorithms for various shift counts, 3635 refer to shift_alg_[qhs]i. */ 3636 3637 /* Classify a shift with the given mode and code. OP is the shift amount. */ 3638 3639 enum h8sx_shift_type 3640 h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op) 3641 { 3642 if (!TARGET_H8300SX) 3643 return H8SX_SHIFT_NONE; 3644 3645 switch (code) 3646 { 3647 case ASHIFT: 3648 case LSHIFTRT: 3649 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */ 3650 if (GET_CODE (op) != CONST_INT) 3651 return H8SX_SHIFT_BINARY; 3652 3653 /* Reject out-of-range shift amounts. */ 3654 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode)) 3655 return H8SX_SHIFT_NONE; 3656 3657 /* Power-of-2 shifts are effectively unary operations. */ 3658 if (exact_log2 (INTVAL (op)) >= 0) 3659 return H8SX_SHIFT_UNARY; 3660 3661 return H8SX_SHIFT_BINARY; 3662 3663 case ASHIFTRT: 3664 if (op == const1_rtx || op == const2_rtx) 3665 return H8SX_SHIFT_UNARY; 3666 return H8SX_SHIFT_NONE; 3667 3668 case ROTATE: 3669 if (GET_CODE (op) == CONST_INT 3670 && (INTVAL (op) == 1 3671 || INTVAL (op) == 2 3672 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2 3673 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1)) 3674 return H8SX_SHIFT_UNARY; 3675 return H8SX_SHIFT_NONE; 3676 3677 default: 3678 return H8SX_SHIFT_NONE; 3679 } 3680 } 3681 3682 /* Return the asm template for a single h8sx shift instruction. 3683 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2] 3684 is the source and OPERANDS[3] is the shift. SUFFIX is the 3685 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand 3686 prefix for the destination operand. */ 3687 3688 const char * 3689 output_h8sx_shift (rtx *operands, int suffix, int optype) 3690 { 3691 static char buffer[16]; 3692 const char *stem; 3693 3694 switch (GET_CODE (operands[3])) 3695 { 3696 case ASHIFT: 3697 stem = "shll"; 3698 break; 3699 3700 case ASHIFTRT: 3701 stem = "shar"; 3702 break; 3703 3704 case LSHIFTRT: 3705 stem = "shlr"; 3706 break; 3707 3708 case ROTATE: 3709 stem = "rotl"; 3710 if (INTVAL (operands[2]) > 2) 3711 { 3712 /* This is really a right rotate. */ 3713 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0])) 3714 - INTVAL (operands[2])); 3715 stem = "rotr"; 3716 } 3717 break; 3718 3719 default: 3720 gcc_unreachable (); 3721 } 3722 if (operands[2] == const1_rtx) 3723 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype); 3724 else 3725 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype); 3726 return buffer; 3727 } 3728 3729 /* Emit code to do shifts. */ 3730 3731 bool 3732 expand_a_shift (enum machine_mode mode, int code, rtx operands[]) 3733 { 3734 switch (h8sx_classify_shift (mode, code, operands[2])) 3735 { 3736 case H8SX_SHIFT_BINARY: 3737 operands[1] = force_reg (mode, operands[1]); 3738 return false; 3739 3740 case H8SX_SHIFT_UNARY: 3741 return false; 3742 3743 case H8SX_SHIFT_NONE: 3744 break; 3745 } 3746 3747 emit_move_insn (copy_rtx (operands[0]), operands[1]); 3748 3749 /* Need a loop to get all the bits we want - we generate the 3750 code at emit time, but need to allocate a scratch reg now. */ 3751 3752 emit_insn (gen_rtx_PARALLEL 3753 (VOIDmode, 3754 gen_rtvec (2, 3755 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]), 3756 gen_rtx_fmt_ee (code, mode, 3757 copy_rtx (operands[0]), operands[2])), 3758 gen_rtx_CLOBBER (VOIDmode, 3759 gen_rtx_SCRATCH (QImode))))); 3760 return true; 3761 } 3762 3763 /* Symbols of the various modes which can be used as indices. */ 3764 3765 enum shift_mode 3766 { 3767 QIshift, HIshift, SIshift 3768 }; 3769 3770 /* For single bit shift insns, record assembler and what bits of the 3771 condition code are valid afterwards (represented as various CC_FOO 3772 bits, 0 means CC isn't left in a usable state). */ 3773 3774 struct shift_insn 3775 { 3776 const char *const assembler; 3777 const int cc_valid; 3778 }; 3779 3780 /* Assembler instruction shift table. 3781 3782 These tables are used to look up the basic shifts. 3783 They are indexed by cpu, shift_type, and mode. */ 3784 3785 static const struct shift_insn shift_one[2][3][3] = 3786 { 3787 /* H8/300 */ 3788 { 3789 /* SHIFT_ASHIFT */ 3790 { 3791 { "shll\t%X0", CC_SET_ZNV }, 3792 { "add.w\t%T0,%T0", CC_SET_ZN }, 3793 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER } 3794 }, 3795 /* SHIFT_LSHIFTRT */ 3796 { 3797 { "shlr\t%X0", CC_SET_ZNV }, 3798 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER }, 3799 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } 3800 }, 3801 /* SHIFT_ASHIFTRT */ 3802 { 3803 { "shar\t%X0", CC_SET_ZNV }, 3804 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER }, 3805 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } 3806 } 3807 }, 3808 /* H8/300H */ 3809 { 3810 /* SHIFT_ASHIFT */ 3811 { 3812 { "shll.b\t%X0", CC_SET_ZNV }, 3813 { "shll.w\t%T0", CC_SET_ZNV }, 3814 { "shll.l\t%S0", CC_SET_ZNV } 3815 }, 3816 /* SHIFT_LSHIFTRT */ 3817 { 3818 { "shlr.b\t%X0", CC_SET_ZNV }, 3819 { "shlr.w\t%T0", CC_SET_ZNV }, 3820 { "shlr.l\t%S0", CC_SET_ZNV } 3821 }, 3822 /* SHIFT_ASHIFTRT */ 3823 { 3824 { "shar.b\t%X0", CC_SET_ZNV }, 3825 { "shar.w\t%T0", CC_SET_ZNV }, 3826 { "shar.l\t%S0", CC_SET_ZNV } 3827 } 3828 } 3829 }; 3830 3831 static const struct shift_insn shift_two[3][3] = 3832 { 3833 /* SHIFT_ASHIFT */ 3834 { 3835 { "shll.b\t#2,%X0", CC_SET_ZNV }, 3836 { "shll.w\t#2,%T0", CC_SET_ZNV }, 3837 { "shll.l\t#2,%S0", CC_SET_ZNV } 3838 }, 3839 /* SHIFT_LSHIFTRT */ 3840 { 3841 { "shlr.b\t#2,%X0", CC_SET_ZNV }, 3842 { "shlr.w\t#2,%T0", CC_SET_ZNV }, 3843 { "shlr.l\t#2,%S0", CC_SET_ZNV } 3844 }, 3845 /* SHIFT_ASHIFTRT */ 3846 { 3847 { "shar.b\t#2,%X0", CC_SET_ZNV }, 3848 { "shar.w\t#2,%T0", CC_SET_ZNV }, 3849 { "shar.l\t#2,%S0", CC_SET_ZNV } 3850 } 3851 }; 3852 3853 /* Rotates are organized by which shift they'll be used in implementing. 3854 There's no need to record whether the cc is valid afterwards because 3855 it is the AND insn that will decide this. */ 3856 3857 static const char *const rotate_one[2][3][3] = 3858 { 3859 /* H8/300 */ 3860 { 3861 /* SHIFT_ASHIFT */ 3862 { 3863 "rotr\t%X0", 3864 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", 3865 0 3866 }, 3867 /* SHIFT_LSHIFTRT */ 3868 { 3869 "rotl\t%X0", 3870 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3871 0 3872 }, 3873 /* SHIFT_ASHIFTRT */ 3874 { 3875 "rotl\t%X0", 3876 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3877 0 3878 } 3879 }, 3880 /* H8/300H */ 3881 { 3882 /* SHIFT_ASHIFT */ 3883 { 3884 "rotr.b\t%X0", 3885 "rotr.w\t%T0", 3886 "rotr.l\t%S0" 3887 }, 3888 /* SHIFT_LSHIFTRT */ 3889 { 3890 "rotl.b\t%X0", 3891 "rotl.w\t%T0", 3892 "rotl.l\t%S0" 3893 }, 3894 /* SHIFT_ASHIFTRT */ 3895 { 3896 "rotl.b\t%X0", 3897 "rotl.w\t%T0", 3898 "rotl.l\t%S0" 3899 } 3900 } 3901 }; 3902 3903 static const char *const rotate_two[3][3] = 3904 { 3905 /* SHIFT_ASHIFT */ 3906 { 3907 "rotr.b\t#2,%X0", 3908 "rotr.w\t#2,%T0", 3909 "rotr.l\t#2,%S0" 3910 }, 3911 /* SHIFT_LSHIFTRT */ 3912 { 3913 "rotl.b\t#2,%X0", 3914 "rotl.w\t#2,%T0", 3915 "rotl.l\t#2,%S0" 3916 }, 3917 /* SHIFT_ASHIFTRT */ 3918 { 3919 "rotl.b\t#2,%X0", 3920 "rotl.w\t#2,%T0", 3921 "rotl.l\t#2,%S0" 3922 } 3923 }; 3924 3925 struct shift_info { 3926 /* Shift algorithm. */ 3927 enum shift_alg alg; 3928 3929 /* The number of bits to be shifted by shift1 and shift2. Valid 3930 when ALG is SHIFT_SPECIAL. */ 3931 unsigned int remainder; 3932 3933 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */ 3934 const char *special; 3935 3936 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE 3937 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 3938 const char *shift1; 3939 3940 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE 3941 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 3942 const char *shift2; 3943 3944 /* CC status for SHIFT_INLINE. */ 3945 int cc_inline; 3946 3947 /* CC status for SHIFT_SPECIAL. */ 3948 int cc_special; 3949 }; 3950 3951 static void get_shift_alg (enum shift_type, 3952 enum shift_mode, unsigned int, 3953 struct shift_info *); 3954 3955 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the 3956 best algorithm for doing the shift. The assembler code is stored 3957 in the pointers in INFO. We achieve the maximum efficiency in most 3958 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in 3959 SImode in particular have a lot of room to optimize. 3960 3961 We first determine the strategy of the shift algorithm by a table 3962 lookup. If that tells us to use a hand crafted assembly code, we 3963 go into the big switch statement to find what that is. Otherwise, 3964 we resort to a generic way, such as inlining. In either case, the 3965 result is returned through INFO. */ 3966 3967 static void 3968 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode, 3969 unsigned int count, struct shift_info *info) 3970 { 3971 enum h8_cpu cpu; 3972 3973 /* Find the target CPU. */ 3974 if (TARGET_H8300) 3975 cpu = H8_300; 3976 else if (TARGET_H8300H) 3977 cpu = H8_300H; 3978 else 3979 cpu = H8_S; 3980 3981 /* Find the shift algorithm. */ 3982 info->alg = SHIFT_LOOP; 3983 switch (shift_mode) 3984 { 3985 case QIshift: 3986 if (count < GET_MODE_BITSIZE (QImode)) 3987 info->alg = shift_alg_qi[cpu][shift_type][count]; 3988 break; 3989 3990 case HIshift: 3991 if (count < GET_MODE_BITSIZE (HImode)) 3992 info->alg = shift_alg_hi[cpu][shift_type][count]; 3993 break; 3994 3995 case SIshift: 3996 if (count < GET_MODE_BITSIZE (SImode)) 3997 info->alg = shift_alg_si[cpu][shift_type][count]; 3998 break; 3999 4000 default: 4001 gcc_unreachable (); 4002 } 4003 4004 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */ 4005 switch (info->alg) 4006 { 4007 case SHIFT_INLINE: 4008 info->remainder = count; 4009 /* Fall through. */ 4010 4011 case SHIFT_LOOP: 4012 /* It is up to the caller to know that looping clobbers cc. */ 4013 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 4014 info->shift2 = shift_two[shift_type][shift_mode].assembler; 4015 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 4016 goto end; 4017 4018 case SHIFT_ROT_AND: 4019 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode]; 4020 info->shift2 = rotate_two[shift_type][shift_mode]; 4021 info->cc_inline = CC_CLOBBER; 4022 goto end; 4023 4024 case SHIFT_SPECIAL: 4025 /* REMAINDER is 0 for most cases, so initialize it to 0. */ 4026 info->remainder = 0; 4027 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 4028 info->shift2 = shift_two[shift_type][shift_mode].assembler; 4029 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 4030 info->cc_special = CC_CLOBBER; 4031 break; 4032 } 4033 4034 /* Here we only deal with SHIFT_SPECIAL. */ 4035 switch (shift_mode) 4036 { 4037 case QIshift: 4038 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated 4039 through the entire value. */ 4040 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7); 4041 info->special = "shll\t%X0\n\tsubx\t%X0,%X0"; 4042 goto end; 4043 4044 case HIshift: 4045 if (count == 7) 4046 { 4047 switch (shift_type) 4048 { 4049 case SHIFT_ASHIFT: 4050 if (TARGET_H8300) 4051 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0"; 4052 else 4053 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; 4054 goto end; 4055 case SHIFT_LSHIFTRT: 4056 if (TARGET_H8300) 4057 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0"; 4058 else 4059 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; 4060 goto end; 4061 case SHIFT_ASHIFTRT: 4062 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; 4063 goto end; 4064 } 4065 } 4066 else if ((8 <= count && count <= 13) 4067 || (TARGET_H8300S && count == 14)) 4068 { 4069 info->remainder = count - 8; 4070 4071 switch (shift_type) 4072 { 4073 case SHIFT_ASHIFT: 4074 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; 4075 goto end; 4076 case SHIFT_LSHIFTRT: 4077 if (TARGET_H8300) 4078 { 4079 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0"; 4080 info->shift1 = "shlr.b\t%s0"; 4081 info->cc_inline = CC_SET_ZNV; 4082 } 4083 else 4084 { 4085 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0"; 4086 info->cc_special = CC_SET_ZNV; 4087 } 4088 goto end; 4089 case SHIFT_ASHIFTRT: 4090 if (TARGET_H8300) 4091 { 4092 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0"; 4093 info->shift1 = "shar.b\t%s0"; 4094 } 4095 else 4096 { 4097 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0"; 4098 info->cc_special = CC_SET_ZNV; 4099 } 4100 goto end; 4101 } 4102 } 4103 else if (count == 14) 4104 { 4105 switch (shift_type) 4106 { 4107 case SHIFT_ASHIFT: 4108 if (TARGET_H8300) 4109 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0"; 4110 goto end; 4111 case SHIFT_LSHIFTRT: 4112 if (TARGET_H8300) 4113 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0"; 4114 goto end; 4115 case SHIFT_ASHIFTRT: 4116 if (TARGET_H8300) 4117 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0"; 4118 else if (TARGET_H8300H) 4119 { 4120 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0"; 4121 info->cc_special = CC_SET_ZNV; 4122 } 4123 else /* TARGET_H8300S */ 4124 gcc_unreachable (); 4125 goto end; 4126 } 4127 } 4128 else if (count == 15) 4129 { 4130 switch (shift_type) 4131 { 4132 case SHIFT_ASHIFT: 4133 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0"; 4134 goto end; 4135 case SHIFT_LSHIFTRT: 4136 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0"; 4137 goto end; 4138 case SHIFT_ASHIFTRT: 4139 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; 4140 goto end; 4141 } 4142 } 4143 gcc_unreachable (); 4144 4145 case SIshift: 4146 if (TARGET_H8300 && 8 <= count && count <= 9) 4147 { 4148 info->remainder = count - 8; 4149 4150 switch (shift_type) 4151 { 4152 case SHIFT_ASHIFT: 4153 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0"; 4154 goto end; 4155 case SHIFT_LSHIFTRT: 4156 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0"; 4157 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0"; 4158 goto end; 4159 case SHIFT_ASHIFTRT: 4160 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0"; 4161 goto end; 4162 } 4163 } 4164 else if (count == 8 && !TARGET_H8300) 4165 { 4166 switch (shift_type) 4167 { 4168 case SHIFT_ASHIFT: 4169 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0"; 4170 goto end; 4171 case SHIFT_LSHIFTRT: 4172 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0"; 4173 goto end; 4174 case SHIFT_ASHIFTRT: 4175 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0"; 4176 goto end; 4177 } 4178 } 4179 else if (count == 15 && TARGET_H8300) 4180 { 4181 switch (shift_type) 4182 { 4183 case SHIFT_ASHIFT: 4184 gcc_unreachable (); 4185 case SHIFT_LSHIFTRT: 4186 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0"; 4187 goto end; 4188 case SHIFT_ASHIFTRT: 4189 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0"; 4190 goto end; 4191 } 4192 } 4193 else if (count == 15 && !TARGET_H8300) 4194 { 4195 switch (shift_type) 4196 { 4197 case SHIFT_ASHIFT: 4198 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0"; 4199 info->cc_special = CC_SET_ZNV; 4200 goto end; 4201 case SHIFT_LSHIFTRT: 4202 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0"; 4203 info->cc_special = CC_SET_ZNV; 4204 goto end; 4205 case SHIFT_ASHIFTRT: 4206 gcc_unreachable (); 4207 } 4208 } 4209 else if ((TARGET_H8300 && 16 <= count && count <= 20) 4210 || (TARGET_H8300H && 16 <= count && count <= 19) 4211 || (TARGET_H8300S && 16 <= count && count <= 21)) 4212 { 4213 info->remainder = count - 16; 4214 4215 switch (shift_type) 4216 { 4217 case SHIFT_ASHIFT: 4218 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 4219 if (TARGET_H8300) 4220 info->shift1 = "add.w\t%e0,%e0"; 4221 goto end; 4222 case SHIFT_LSHIFTRT: 4223 if (TARGET_H8300) 4224 { 4225 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0"; 4226 info->shift1 = "shlr\t%x0\n\trotxr\t%w0"; 4227 } 4228 else 4229 { 4230 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0"; 4231 info->cc_special = CC_SET_ZNV; 4232 } 4233 goto end; 4234 case SHIFT_ASHIFTRT: 4235 if (TARGET_H8300) 4236 { 4237 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0"; 4238 info->shift1 = "shar\t%x0\n\trotxr\t%w0"; 4239 } 4240 else 4241 { 4242 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0"; 4243 info->cc_special = CC_SET_ZNV; 4244 } 4245 goto end; 4246 } 4247 } 4248 else if (TARGET_H8300 && 24 <= count && count <= 28) 4249 { 4250 info->remainder = count - 24; 4251 4252 switch (shift_type) 4253 { 4254 case SHIFT_ASHIFT: 4255 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0"; 4256 info->shift1 = "shll.b\t%z0"; 4257 info->cc_inline = CC_SET_ZNV; 4258 goto end; 4259 case SHIFT_LSHIFTRT: 4260 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0"; 4261 info->shift1 = "shlr.b\t%w0"; 4262 info->cc_inline = CC_SET_ZNV; 4263 goto end; 4264 case SHIFT_ASHIFTRT: 4265 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0"; 4266 info->shift1 = "shar.b\t%w0"; 4267 info->cc_inline = CC_SET_ZNV; 4268 goto end; 4269 } 4270 } 4271 else if ((TARGET_H8300H && count == 24) 4272 || (TARGET_H8300S && 24 <= count && count <= 25)) 4273 { 4274 info->remainder = count - 24; 4275 4276 switch (shift_type) 4277 { 4278 case SHIFT_ASHIFT: 4279 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 4280 goto end; 4281 case SHIFT_LSHIFTRT: 4282 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; 4283 info->cc_special = CC_SET_ZNV; 4284 goto end; 4285 case SHIFT_ASHIFTRT: 4286 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 4287 info->cc_special = CC_SET_ZNV; 4288 goto end; 4289 } 4290 } 4291 else if (!TARGET_H8300 && count == 28) 4292 { 4293 switch (shift_type) 4294 { 4295 case SHIFT_ASHIFT: 4296 if (TARGET_H8300H) 4297 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4298 else 4299 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 4300 goto end; 4301 case SHIFT_LSHIFTRT: 4302 if (TARGET_H8300H) 4303 { 4304 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4305 info->cc_special = CC_SET_ZNV; 4306 } 4307 else 4308 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 4309 goto end; 4310 case SHIFT_ASHIFTRT: 4311 gcc_unreachable (); 4312 } 4313 } 4314 else if (!TARGET_H8300 && count == 29) 4315 { 4316 switch (shift_type) 4317 { 4318 case SHIFT_ASHIFT: 4319 if (TARGET_H8300H) 4320 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4321 else 4322 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4323 goto end; 4324 case SHIFT_LSHIFTRT: 4325 if (TARGET_H8300H) 4326 { 4327 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4328 info->cc_special = CC_SET_ZNV; 4329 } 4330 else 4331 { 4332 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4333 info->cc_special = CC_SET_ZNV; 4334 } 4335 goto end; 4336 case SHIFT_ASHIFTRT: 4337 gcc_unreachable (); 4338 } 4339 } 4340 else if (!TARGET_H8300 && count == 30) 4341 { 4342 switch (shift_type) 4343 { 4344 case SHIFT_ASHIFT: 4345 if (TARGET_H8300H) 4346 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4347 else 4348 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 4349 goto end; 4350 case SHIFT_LSHIFTRT: 4351 if (TARGET_H8300H) 4352 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4353 else 4354 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 4355 goto end; 4356 case SHIFT_ASHIFTRT: 4357 gcc_unreachable (); 4358 } 4359 } 4360 else if (count == 31) 4361 { 4362 if (TARGET_H8300) 4363 { 4364 switch (shift_type) 4365 { 4366 case SHIFT_ASHIFT: 4367 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0"; 4368 goto end; 4369 case SHIFT_LSHIFTRT: 4370 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0"; 4371 goto end; 4372 case SHIFT_ASHIFTRT: 4373 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0"; 4374 goto end; 4375 } 4376 } 4377 else 4378 { 4379 switch (shift_type) 4380 { 4381 case SHIFT_ASHIFT: 4382 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0"; 4383 info->cc_special = CC_SET_ZNV; 4384 goto end; 4385 case SHIFT_LSHIFTRT: 4386 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0"; 4387 info->cc_special = CC_SET_ZNV; 4388 goto end; 4389 case SHIFT_ASHIFTRT: 4390 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0"; 4391 info->cc_special = CC_SET_ZNV; 4392 goto end; 4393 } 4394 } 4395 } 4396 gcc_unreachable (); 4397 4398 default: 4399 gcc_unreachable (); 4400 } 4401 4402 end: 4403 if (!TARGET_H8300S) 4404 info->shift2 = NULL; 4405 } 4406 4407 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be 4408 needed for some shift with COUNT and MODE. Return 0 otherwise. */ 4409 4410 int 4411 h8300_shift_needs_scratch_p (int count, enum machine_mode mode) 4412 { 4413 enum h8_cpu cpu; 4414 int a, lr, ar; 4415 4416 if (GET_MODE_BITSIZE (mode) <= count) 4417 return 1; 4418 4419 /* Find out the target CPU. */ 4420 if (TARGET_H8300) 4421 cpu = H8_300; 4422 else if (TARGET_H8300H) 4423 cpu = H8_300H; 4424 else 4425 cpu = H8_S; 4426 4427 /* Find the shift algorithm. */ 4428 switch (mode) 4429 { 4430 case QImode: 4431 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count]; 4432 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count]; 4433 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count]; 4434 break; 4435 4436 case HImode: 4437 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count]; 4438 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count]; 4439 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count]; 4440 break; 4441 4442 case SImode: 4443 a = shift_alg_si[cpu][SHIFT_ASHIFT][count]; 4444 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count]; 4445 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count]; 4446 break; 4447 4448 default: 4449 gcc_unreachable (); 4450 } 4451 4452 /* On H8/300H, count == 8 uses a scratch register. */ 4453 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP 4454 || (TARGET_H8300H && mode == SImode && count == 8)); 4455 } 4456 4457 /* Output the assembler code for doing shifts. */ 4458 4459 const char * 4460 output_a_shift (rtx *operands) 4461 { 4462 static int loopend_lab; 4463 rtx shift = operands[3]; 4464 enum machine_mode mode = GET_MODE (shift); 4465 enum rtx_code code = GET_CODE (shift); 4466 enum shift_type shift_type; 4467 enum shift_mode shift_mode; 4468 struct shift_info info; 4469 int n; 4470 4471 loopend_lab++; 4472 4473 switch (mode) 4474 { 4475 case QImode: 4476 shift_mode = QIshift; 4477 break; 4478 case HImode: 4479 shift_mode = HIshift; 4480 break; 4481 case SImode: 4482 shift_mode = SIshift; 4483 break; 4484 default: 4485 gcc_unreachable (); 4486 } 4487 4488 switch (code) 4489 { 4490 case ASHIFTRT: 4491 shift_type = SHIFT_ASHIFTRT; 4492 break; 4493 case LSHIFTRT: 4494 shift_type = SHIFT_LSHIFTRT; 4495 break; 4496 case ASHIFT: 4497 shift_type = SHIFT_ASHIFT; 4498 break; 4499 default: 4500 gcc_unreachable (); 4501 } 4502 4503 /* This case must be taken care of by one of the two splitters 4504 that convert a variable shift into a loop. */ 4505 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4506 4507 n = INTVAL (operands[2]); 4508 4509 /* If the count is negative, make it 0. */ 4510 if (n < 0) 4511 n = 0; 4512 /* If the count is too big, truncate it. 4513 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4514 do the intuitive thing. */ 4515 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4516 n = GET_MODE_BITSIZE (mode); 4517 4518 get_shift_alg (shift_type, shift_mode, n, &info); 4519 4520 switch (info.alg) 4521 { 4522 case SHIFT_SPECIAL: 4523 output_asm_insn (info.special, operands); 4524 /* Fall through. */ 4525 4526 case SHIFT_INLINE: 4527 n = info.remainder; 4528 4529 /* Emit two bit shifts first. */ 4530 if (info.shift2 != NULL) 4531 { 4532 for (; n > 1; n -= 2) 4533 output_asm_insn (info.shift2, operands); 4534 } 4535 4536 /* Now emit one bit shifts for any residual. */ 4537 for (; n > 0; n--) 4538 output_asm_insn (info.shift1, operands); 4539 return ""; 4540 4541 case SHIFT_ROT_AND: 4542 { 4543 int m = GET_MODE_BITSIZE (mode) - n; 4544 const int mask = (shift_type == SHIFT_ASHIFT 4545 ? ((1 << m) - 1) << n 4546 : (1 << m) - 1); 4547 char insn_buf[200]; 4548 4549 /* Not all possibilities of rotate are supported. They shouldn't 4550 be generated, but let's watch for 'em. */ 4551 gcc_assert (info.shift1); 4552 4553 /* Emit two bit rotates first. */ 4554 if (info.shift2 != NULL) 4555 { 4556 for (; m > 1; m -= 2) 4557 output_asm_insn (info.shift2, operands); 4558 } 4559 4560 /* Now single bit rotates for any residual. */ 4561 for (; m > 0; m--) 4562 output_asm_insn (info.shift1, operands); 4563 4564 /* Now mask off the high bits. */ 4565 switch (mode) 4566 { 4567 case QImode: 4568 sprintf (insn_buf, "and\t#%d,%%X0", mask); 4569 break; 4570 4571 case HImode: 4572 gcc_assert (TARGET_H8300H || TARGET_H8300S); 4573 sprintf (insn_buf, "and.w\t#%d,%%T0", mask); 4574 break; 4575 4576 default: 4577 gcc_unreachable (); 4578 } 4579 4580 output_asm_insn (insn_buf, operands); 4581 return ""; 4582 } 4583 4584 case SHIFT_LOOP: 4585 /* A loop to shift by a "large" constant value. 4586 If we have shift-by-2 insns, use them. */ 4587 if (info.shift2 != NULL) 4588 { 4589 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, 4590 names_big[REGNO (operands[4])]); 4591 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4592 output_asm_insn (info.shift2, operands); 4593 output_asm_insn ("add #0xff,%X4", operands); 4594 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4595 if (n % 2) 4596 output_asm_insn (info.shift1, operands); 4597 } 4598 else 4599 { 4600 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, 4601 names_big[REGNO (operands[4])]); 4602 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4603 output_asm_insn (info.shift1, operands); 4604 output_asm_insn ("add #0xff,%X4", operands); 4605 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4606 } 4607 return ""; 4608 4609 default: 4610 gcc_unreachable (); 4611 } 4612 } 4613 4614 /* Count the number of assembly instructions in a string TEMPL. */ 4615 4616 static unsigned int 4617 h8300_asm_insn_count (const char *templ) 4618 { 4619 unsigned int count = 1; 4620 4621 for (; *templ; templ++) 4622 if (*templ == '\n') 4623 count++; 4624 4625 return count; 4626 } 4627 4628 /* Compute the length of a shift insn. */ 4629 4630 unsigned int 4631 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands) 4632 { 4633 rtx shift = operands[3]; 4634 enum machine_mode mode = GET_MODE (shift); 4635 enum rtx_code code = GET_CODE (shift); 4636 enum shift_type shift_type; 4637 enum shift_mode shift_mode; 4638 struct shift_info info; 4639 unsigned int wlength = 0; 4640 4641 switch (mode) 4642 { 4643 case QImode: 4644 shift_mode = QIshift; 4645 break; 4646 case HImode: 4647 shift_mode = HIshift; 4648 break; 4649 case SImode: 4650 shift_mode = SIshift; 4651 break; 4652 default: 4653 gcc_unreachable (); 4654 } 4655 4656 switch (code) 4657 { 4658 case ASHIFTRT: 4659 shift_type = SHIFT_ASHIFTRT; 4660 break; 4661 case LSHIFTRT: 4662 shift_type = SHIFT_LSHIFTRT; 4663 break; 4664 case ASHIFT: 4665 shift_type = SHIFT_ASHIFT; 4666 break; 4667 default: 4668 gcc_unreachable (); 4669 } 4670 4671 if (GET_CODE (operands[2]) != CONST_INT) 4672 { 4673 /* Get the assembler code to do one shift. */ 4674 get_shift_alg (shift_type, shift_mode, 1, &info); 4675 4676 return (4 + h8300_asm_insn_count (info.shift1)) * 2; 4677 } 4678 else 4679 { 4680 int n = INTVAL (operands[2]); 4681 4682 /* If the count is negative, make it 0. */ 4683 if (n < 0) 4684 n = 0; 4685 /* If the count is too big, truncate it. 4686 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4687 do the intuitive thing. */ 4688 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4689 n = GET_MODE_BITSIZE (mode); 4690 4691 get_shift_alg (shift_type, shift_mode, n, &info); 4692 4693 switch (info.alg) 4694 { 4695 case SHIFT_SPECIAL: 4696 wlength += h8300_asm_insn_count (info.special); 4697 4698 /* Every assembly instruction used in SHIFT_SPECIAL case 4699 takes 2 bytes except xor.l, which takes 4 bytes, so if we 4700 see xor.l, we just pretend that xor.l counts as two insns 4701 so that the insn length will be computed correctly. */ 4702 if (strstr (info.special, "xor.l") != NULL) 4703 wlength++; 4704 4705 /* Fall through. */ 4706 4707 case SHIFT_INLINE: 4708 n = info.remainder; 4709 4710 if (info.shift2 != NULL) 4711 { 4712 wlength += h8300_asm_insn_count (info.shift2) * (n / 2); 4713 n = n % 2; 4714 } 4715 4716 wlength += h8300_asm_insn_count (info.shift1) * n; 4717 4718 return 2 * wlength; 4719 4720 case SHIFT_ROT_AND: 4721 { 4722 int m = GET_MODE_BITSIZE (mode) - n; 4723 4724 /* Not all possibilities of rotate are supported. They shouldn't 4725 be generated, but let's watch for 'em. */ 4726 gcc_assert (info.shift1); 4727 4728 if (info.shift2 != NULL) 4729 { 4730 wlength += h8300_asm_insn_count (info.shift2) * (m / 2); 4731 m = m % 2; 4732 } 4733 4734 wlength += h8300_asm_insn_count (info.shift1) * m; 4735 4736 /* Now mask off the high bits. */ 4737 switch (mode) 4738 { 4739 case QImode: 4740 wlength += 1; 4741 break; 4742 case HImode: 4743 wlength += 2; 4744 break; 4745 case SImode: 4746 gcc_assert (!TARGET_H8300); 4747 wlength += 3; 4748 break; 4749 default: 4750 gcc_unreachable (); 4751 } 4752 return 2 * wlength; 4753 } 4754 4755 case SHIFT_LOOP: 4756 /* A loop to shift by a "large" constant value. 4757 If we have shift-by-2 insns, use them. */ 4758 if (info.shift2 != NULL) 4759 { 4760 wlength += 3 + h8300_asm_insn_count (info.shift2); 4761 if (n % 2) 4762 wlength += h8300_asm_insn_count (info.shift1); 4763 } 4764 else 4765 { 4766 wlength += 3 + h8300_asm_insn_count (info.shift1); 4767 } 4768 return 2 * wlength; 4769 4770 default: 4771 gcc_unreachable (); 4772 } 4773 } 4774 } 4775 4776 /* Compute which flag bits are valid after a shift insn. */ 4777 4778 int 4779 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands) 4780 { 4781 rtx shift = operands[3]; 4782 enum machine_mode mode = GET_MODE (shift); 4783 enum rtx_code code = GET_CODE (shift); 4784 enum shift_type shift_type; 4785 enum shift_mode shift_mode; 4786 struct shift_info info; 4787 int n; 4788 4789 switch (mode) 4790 { 4791 case QImode: 4792 shift_mode = QIshift; 4793 break; 4794 case HImode: 4795 shift_mode = HIshift; 4796 break; 4797 case SImode: 4798 shift_mode = SIshift; 4799 break; 4800 default: 4801 gcc_unreachable (); 4802 } 4803 4804 switch (code) 4805 { 4806 case ASHIFTRT: 4807 shift_type = SHIFT_ASHIFTRT; 4808 break; 4809 case LSHIFTRT: 4810 shift_type = SHIFT_LSHIFTRT; 4811 break; 4812 case ASHIFT: 4813 shift_type = SHIFT_ASHIFT; 4814 break; 4815 default: 4816 gcc_unreachable (); 4817 } 4818 4819 /* This case must be taken care of by one of the two splitters 4820 that convert a variable shift into a loop. */ 4821 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4822 4823 n = INTVAL (operands[2]); 4824 4825 /* If the count is negative, make it 0. */ 4826 if (n < 0) 4827 n = 0; 4828 /* If the count is too big, truncate it. 4829 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4830 do the intuitive thing. */ 4831 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4832 n = GET_MODE_BITSIZE (mode); 4833 4834 get_shift_alg (shift_type, shift_mode, n, &info); 4835 4836 switch (info.alg) 4837 { 4838 case SHIFT_SPECIAL: 4839 if (info.remainder == 0) 4840 return info.cc_special; 4841 4842 /* Fall through. */ 4843 4844 case SHIFT_INLINE: 4845 return info.cc_inline; 4846 4847 case SHIFT_ROT_AND: 4848 /* This case always ends with an and instruction. */ 4849 return CC_SET_ZNV; 4850 4851 case SHIFT_LOOP: 4852 /* A loop to shift by a "large" constant value. 4853 If we have shift-by-2 insns, use them. */ 4854 if (info.shift2 != NULL) 4855 { 4856 if (n % 2) 4857 return info.cc_inline; 4858 } 4859 return CC_CLOBBER; 4860 4861 default: 4862 gcc_unreachable (); 4863 } 4864 } 4865 4866 /* A rotation by a non-constant will cause a loop to be generated, in 4867 which a rotation by one bit is used. A rotation by a constant, 4868 including the one in the loop, will be taken care of by 4869 output_a_rotate () at the insn emit time. */ 4870 4871 int 4872 expand_a_rotate (rtx operands[]) 4873 { 4874 rtx dst = operands[0]; 4875 rtx src = operands[1]; 4876 rtx rotate_amount = operands[2]; 4877 enum machine_mode mode = GET_MODE (dst); 4878 4879 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY) 4880 return false; 4881 4882 /* We rotate in place. */ 4883 emit_move_insn (dst, src); 4884 4885 if (GET_CODE (rotate_amount) != CONST_INT) 4886 { 4887 rtx counter = gen_reg_rtx (QImode); 4888 rtx start_label = gen_label_rtx (); 4889 rtx end_label = gen_label_rtx (); 4890 4891 /* If the rotate amount is less than or equal to 0, 4892 we go out of the loop. */ 4893 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX, 4894 QImode, 0, end_label); 4895 4896 /* Initialize the loop counter. */ 4897 emit_move_insn (counter, rotate_amount); 4898 4899 emit_label (start_label); 4900 4901 /* Rotate by one bit. */ 4902 switch (mode) 4903 { 4904 case QImode: 4905 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx)); 4906 break; 4907 case HImode: 4908 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx)); 4909 break; 4910 case SImode: 4911 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx)); 4912 break; 4913 default: 4914 gcc_unreachable (); 4915 } 4916 4917 /* Decrement the counter by 1. */ 4918 emit_insn (gen_addqi3 (counter, counter, constm1_rtx)); 4919 4920 /* If the loop counter is nonzero, we go back to the beginning 4921 of the loop. */ 4922 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1, 4923 start_label); 4924 4925 emit_label (end_label); 4926 } 4927 else 4928 { 4929 /* Rotate by AMOUNT bits. */ 4930 switch (mode) 4931 { 4932 case QImode: 4933 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount)); 4934 break; 4935 case HImode: 4936 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount)); 4937 break; 4938 case SImode: 4939 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount)); 4940 break; 4941 default: 4942 gcc_unreachable (); 4943 } 4944 } 4945 4946 return 1; 4947 } 4948 4949 /* Output a rotate insn. */ 4950 4951 const char * 4952 output_a_rotate (enum rtx_code code, rtx *operands) 4953 { 4954 rtx dst = operands[0]; 4955 rtx rotate_amount = operands[2]; 4956 enum shift_mode rotate_mode; 4957 enum shift_type rotate_type; 4958 const char *insn_buf; 4959 int bits; 4960 int amount; 4961 enum machine_mode mode = GET_MODE (dst); 4962 4963 gcc_assert (GET_CODE (rotate_amount) == CONST_INT); 4964 4965 switch (mode) 4966 { 4967 case QImode: 4968 rotate_mode = QIshift; 4969 break; 4970 case HImode: 4971 rotate_mode = HIshift; 4972 break; 4973 case SImode: 4974 rotate_mode = SIshift; 4975 break; 4976 default: 4977 gcc_unreachable (); 4978 } 4979 4980 switch (code) 4981 { 4982 case ROTATERT: 4983 rotate_type = SHIFT_ASHIFT; 4984 break; 4985 case ROTATE: 4986 rotate_type = SHIFT_LSHIFTRT; 4987 break; 4988 default: 4989 gcc_unreachable (); 4990 } 4991 4992 amount = INTVAL (rotate_amount); 4993 4994 /* Clean up AMOUNT. */ 4995 if (amount < 0) 4996 amount = 0; 4997 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 4998 amount = GET_MODE_BITSIZE (mode); 4999 5000 /* Determine the faster direction. After this phase, amount will be 5001 at most a half of GET_MODE_BITSIZE (mode). */ 5002 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 5003 { 5004 /* Flip the direction. */ 5005 amount = GET_MODE_BITSIZE (mode) - amount; 5006 rotate_type = 5007 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 5008 } 5009 5010 /* See if a byte swap (in HImode) or a word swap (in SImode) can 5011 boost up the rotation. */ 5012 if ((mode == HImode && TARGET_H8300 && amount >= 5) 5013 || (mode == HImode && TARGET_H8300H && amount >= 6) 5014 || (mode == HImode && TARGET_H8300S && amount == 8) 5015 || (mode == SImode && TARGET_H8300H && amount >= 10) 5016 || (mode == SImode && TARGET_H8300S && amount >= 13)) 5017 { 5018 switch (mode) 5019 { 5020 case HImode: 5021 /* This code works on any family. */ 5022 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0"; 5023 output_asm_insn (insn_buf, operands); 5024 break; 5025 5026 case SImode: 5027 /* This code works on the H8/300H and H8S. */ 5028 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0"; 5029 output_asm_insn (insn_buf, operands); 5030 break; 5031 5032 default: 5033 gcc_unreachable (); 5034 } 5035 5036 /* Adjust AMOUNT and flip the direction. */ 5037 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 5038 rotate_type = 5039 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 5040 } 5041 5042 /* Output rotate insns. */ 5043 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2) 5044 { 5045 if (bits == 2) 5046 insn_buf = rotate_two[rotate_type][rotate_mode]; 5047 else 5048 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode]; 5049 5050 for (; amount >= bits; amount -= bits) 5051 output_asm_insn (insn_buf, operands); 5052 } 5053 5054 return ""; 5055 } 5056 5057 /* Compute the length of a rotate insn. */ 5058 5059 unsigned int 5060 compute_a_rotate_length (rtx *operands) 5061 { 5062 rtx src = operands[1]; 5063 rtx amount_rtx = operands[2]; 5064 enum machine_mode mode = GET_MODE (src); 5065 int amount; 5066 unsigned int length = 0; 5067 5068 gcc_assert (GET_CODE (amount_rtx) == CONST_INT); 5069 5070 amount = INTVAL (amount_rtx); 5071 5072 /* Clean up AMOUNT. */ 5073 if (amount < 0) 5074 amount = 0; 5075 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 5076 amount = GET_MODE_BITSIZE (mode); 5077 5078 /* Determine the faster direction. After this phase, amount 5079 will be at most a half of GET_MODE_BITSIZE (mode). */ 5080 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 5081 /* Flip the direction. */ 5082 amount = GET_MODE_BITSIZE (mode) - amount; 5083 5084 /* See if a byte swap (in HImode) or a word swap (in SImode) can 5085 boost up the rotation. */ 5086 if ((mode == HImode && TARGET_H8300 && amount >= 5) 5087 || (mode == HImode && TARGET_H8300H && amount >= 6) 5088 || (mode == HImode && TARGET_H8300S && amount == 8) 5089 || (mode == SImode && TARGET_H8300H && amount >= 10) 5090 || (mode == SImode && TARGET_H8300S && amount >= 13)) 5091 { 5092 /* Adjust AMOUNT and flip the direction. */ 5093 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 5094 length += 6; 5095 } 5096 5097 /* We use 2-bit rotations on the H8S. */ 5098 if (TARGET_H8300S) 5099 amount = amount / 2 + amount % 2; 5100 5101 /* The H8/300 uses three insns to rotate one bit, taking 6 5102 length. */ 5103 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2); 5104 5105 return length; 5106 } 5107 5108 /* Fix the operands of a gen_xxx so that it could become a bit 5109 operating insn. */ 5110 5111 int 5112 fix_bit_operand (rtx *operands, enum rtx_code code) 5113 { 5114 /* The bit_operand predicate accepts any memory during RTL generation, but 5115 only 'U' memory afterwards, so if this is a MEM operand, we must force 5116 it to be valid for 'U' by reloading the address. */ 5117 5118 if (code == AND 5119 ? single_zero_operand (operands[2], QImode) 5120 : single_one_operand (operands[2], QImode)) 5121 { 5122 /* OK to have a memory dest. */ 5123 if (GET_CODE (operands[0]) == MEM 5124 && !OK_FOR_U (operands[0])) 5125 { 5126 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]), 5127 copy_to_mode_reg (Pmode, 5128 XEXP (operands[0], 0))); 5129 MEM_COPY_ATTRIBUTES (mem, operands[0]); 5130 operands[0] = mem; 5131 } 5132 5133 if (GET_CODE (operands[1]) == MEM 5134 && !OK_FOR_U (operands[1])) 5135 { 5136 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]), 5137 copy_to_mode_reg (Pmode, 5138 XEXP (operands[1], 0))); 5139 MEM_COPY_ATTRIBUTES (mem, operands[0]); 5140 operands[1] = mem; 5141 } 5142 return 0; 5143 } 5144 5145 /* Dest and src op must be register. */ 5146 5147 operands[1] = force_reg (QImode, operands[1]); 5148 { 5149 rtx res = gen_reg_rtx (QImode); 5150 switch (code) 5151 { 5152 case AND: 5153 emit_insn (gen_andqi3_1 (res, operands[1], operands[2])); 5154 break; 5155 case IOR: 5156 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2])); 5157 break; 5158 case XOR: 5159 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2])); 5160 break; 5161 default: 5162 gcc_unreachable (); 5163 } 5164 emit_insn (gen_movqi (operands[0], res)); 5165 } 5166 return 1; 5167 } 5168 5169 /* Return nonzero if FUNC is an interrupt function as specified 5170 by the "interrupt" attribute. */ 5171 5172 static int 5173 h8300_interrupt_function_p (tree func) 5174 { 5175 tree a; 5176 5177 if (TREE_CODE (func) != FUNCTION_DECL) 5178 return 0; 5179 5180 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); 5181 return a != NULL_TREE; 5182 } 5183 5184 /* Return nonzero if FUNC is a saveall function as specified by the 5185 "saveall" attribute. */ 5186 5187 static int 5188 h8300_saveall_function_p (tree func) 5189 { 5190 tree a; 5191 5192 if (TREE_CODE (func) != FUNCTION_DECL) 5193 return 0; 5194 5195 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func)); 5196 return a != NULL_TREE; 5197 } 5198 5199 /* Return nonzero if FUNC is an OS_Task function as specified 5200 by the "OS_Task" attribute. */ 5201 5202 static int 5203 h8300_os_task_function_p (tree func) 5204 { 5205 tree a; 5206 5207 if (TREE_CODE (func) != FUNCTION_DECL) 5208 return 0; 5209 5210 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func)); 5211 return a != NULL_TREE; 5212 } 5213 5214 /* Return nonzero if FUNC is a monitor function as specified 5215 by the "monitor" attribute. */ 5216 5217 static int 5218 h8300_monitor_function_p (tree func) 5219 { 5220 tree a; 5221 5222 if (TREE_CODE (func) != FUNCTION_DECL) 5223 return 0; 5224 5225 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func)); 5226 return a != NULL_TREE; 5227 } 5228 5229 /* Return nonzero if FUNC is a function that should be called 5230 through the function vector. */ 5231 5232 int 5233 h8300_funcvec_function_p (tree func) 5234 { 5235 tree a; 5236 5237 if (TREE_CODE (func) != FUNCTION_DECL) 5238 return 0; 5239 5240 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func)); 5241 return a != NULL_TREE; 5242 } 5243 5244 /* Return nonzero if DECL is a variable that's in the eight bit 5245 data area. */ 5246 5247 int 5248 h8300_eightbit_data_p (tree decl) 5249 { 5250 tree a; 5251 5252 if (TREE_CODE (decl) != VAR_DECL) 5253 return 0; 5254 5255 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl)); 5256 return a != NULL_TREE; 5257 } 5258 5259 /* Return nonzero if DECL is a variable that's in the tiny 5260 data area. */ 5261 5262 int 5263 h8300_tiny_data_p (tree decl) 5264 { 5265 tree a; 5266 5267 if (TREE_CODE (decl) != VAR_DECL) 5268 return 0; 5269 5270 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl)); 5271 return a != NULL_TREE; 5272 } 5273 5274 /* Generate an 'interrupt_handler' attribute for decls. We convert 5275 all the pragmas to corresponding attributes. */ 5276 5277 static void 5278 h8300_insert_attributes (tree node, tree *attributes) 5279 { 5280 if (TREE_CODE (node) == FUNCTION_DECL) 5281 { 5282 if (pragma_interrupt) 5283 { 5284 pragma_interrupt = 0; 5285 5286 /* Add an 'interrupt_handler' attribute. */ 5287 *attributes = tree_cons (get_identifier ("interrupt_handler"), 5288 NULL, *attributes); 5289 } 5290 5291 if (pragma_saveall) 5292 { 5293 pragma_saveall = 0; 5294 5295 /* Add an 'saveall' attribute. */ 5296 *attributes = tree_cons (get_identifier ("saveall"), 5297 NULL, *attributes); 5298 } 5299 } 5300 } 5301 5302 /* Supported attributes: 5303 5304 interrupt_handler: output a prologue and epilogue suitable for an 5305 interrupt handler. 5306 5307 saveall: output a prologue and epilogue that saves and restores 5308 all registers except the stack pointer. 5309 5310 function_vector: This function should be called through the 5311 function vector. 5312 5313 eightbit_data: This variable lives in the 8-bit data area and can 5314 be referenced with 8-bit absolute memory addresses. 5315 5316 tiny_data: This variable lives in the tiny data area and can be 5317 referenced with 16-bit absolute memory references. */ 5318 5319 static const struct attribute_spec h8300_attribute_table[] = 5320 { 5321 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ 5322 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute }, 5323 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute }, 5324 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute }, 5325 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute }, 5326 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute }, 5327 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute }, 5328 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute }, 5329 { NULL, 0, 0, false, false, false, NULL } 5330 }; 5331 5332 5333 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in 5334 struct attribute_spec.handler. */ 5335 static tree 5336 h8300_handle_fndecl_attribute (tree *node, tree name, 5337 tree args ATTRIBUTE_UNUSED, 5338 int flags ATTRIBUTE_UNUSED, 5339 bool *no_add_attrs) 5340 { 5341 if (TREE_CODE (*node) != FUNCTION_DECL) 5342 { 5343 warning (OPT_Wattributes, "%qE attribute only applies to functions", 5344 name); 5345 *no_add_attrs = true; 5346 } 5347 5348 return NULL_TREE; 5349 } 5350 5351 /* Handle an "eightbit_data" attribute; arguments as in 5352 struct attribute_spec.handler. */ 5353 static tree 5354 h8300_handle_eightbit_data_attribute (tree *node, tree name, 5355 tree args ATTRIBUTE_UNUSED, 5356 int flags ATTRIBUTE_UNUSED, 5357 bool *no_add_attrs) 5358 { 5359 tree decl = *node; 5360 5361 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 5362 { 5363 DECL_SECTION_NAME (decl) = build_string (7, ".eight"); 5364 } 5365 else 5366 { 5367 warning (OPT_Wattributes, "%qE attribute ignored", 5368 name); 5369 *no_add_attrs = true; 5370 } 5371 5372 return NULL_TREE; 5373 } 5374 5375 /* Handle an "tiny_data" attribute; arguments as in 5376 struct attribute_spec.handler. */ 5377 static tree 5378 h8300_handle_tiny_data_attribute (tree *node, tree name, 5379 tree args ATTRIBUTE_UNUSED, 5380 int flags ATTRIBUTE_UNUSED, 5381 bool *no_add_attrs) 5382 { 5383 tree decl = *node; 5384 5385 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 5386 { 5387 DECL_SECTION_NAME (decl) = build_string (6, ".tiny"); 5388 } 5389 else 5390 { 5391 warning (OPT_Wattributes, "%qE attribute ignored", 5392 name); 5393 *no_add_attrs = true; 5394 } 5395 5396 return NULL_TREE; 5397 } 5398 5399 /* Mark function vectors, and various small data objects. */ 5400 5401 static void 5402 h8300_encode_section_info (tree decl, rtx rtl, int first) 5403 { 5404 int extra_flags = 0; 5405 5406 default_encode_section_info (decl, rtl, first); 5407 5408 if (TREE_CODE (decl) == FUNCTION_DECL 5409 && h8300_funcvec_function_p (decl)) 5410 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION; 5411 else if (TREE_CODE (decl) == VAR_DECL 5412 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) 5413 { 5414 if (h8300_eightbit_data_p (decl)) 5415 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA; 5416 else if (first && h8300_tiny_data_p (decl)) 5417 extra_flags = SYMBOL_FLAG_TINY_DATA; 5418 } 5419 5420 if (extra_flags) 5421 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; 5422 } 5423 5424 /* Output a single-bit extraction. */ 5425 5426 const char * 5427 output_simode_bld (int bild, rtx operands[]) 5428 { 5429 if (TARGET_H8300) 5430 { 5431 /* Clear the destination register. */ 5432 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); 5433 5434 /* Now output the bit load or bit inverse load, and store it in 5435 the destination. */ 5436 if (bild) 5437 output_asm_insn ("bild\t%Z2,%Y1", operands); 5438 else 5439 output_asm_insn ("bld\t%Z2,%Y1", operands); 5440 5441 output_asm_insn ("bst\t#0,%w0", operands); 5442 } 5443 else 5444 { 5445 /* Determine if we can clear the destination first. */ 5446 int clear_first = (REG_P (operands[0]) && REG_P (operands[1]) 5447 && REGNO (operands[0]) != REGNO (operands[1])); 5448 5449 if (clear_first) 5450 output_asm_insn ("sub.l\t%S0,%S0", operands); 5451 5452 /* Output the bit load or bit inverse load. */ 5453 if (bild) 5454 output_asm_insn ("bild\t%Z2,%Y1", operands); 5455 else 5456 output_asm_insn ("bld\t%Z2,%Y1", operands); 5457 5458 if (!clear_first) 5459 output_asm_insn ("xor.l\t%S0,%S0", operands); 5460 5461 /* Perform the bit store. */ 5462 output_asm_insn ("rotxl.l\t%S0", operands); 5463 } 5464 5465 /* All done. */ 5466 return ""; 5467 } 5468 5469 /* Delayed-branch scheduling is more effective if we have some idea 5470 how long each instruction will be. Use a shorten_branches pass 5471 to get an initial estimate. */ 5472 5473 static void 5474 h8300_reorg (void) 5475 { 5476 if (flag_delayed_branch) 5477 shorten_branches (get_insns ()); 5478 } 5479 5480 #ifndef OBJECT_FORMAT_ELF 5481 static void 5482 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED, 5483 tree decl) 5484 { 5485 /* ??? Perhaps we should be using default_coff_asm_named_section. */ 5486 fprintf (asm_out_file, "\t.section %s\n", name); 5487 } 5488 #endif /* ! OBJECT_FORMAT_ELF */ 5489 5490 /* Nonzero if X is a constant address suitable as an 8-bit absolute, 5491 which is a special case of the 'R' operand. */ 5492 5493 int 5494 h8300_eightbit_constant_address_p (rtx x) 5495 { 5496 /* The ranges of the 8-bit area. */ 5497 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode); 5498 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode); 5499 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode); 5500 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode); 5501 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode); 5502 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode); 5503 5504 unsigned HOST_WIDE_INT addr; 5505 5506 /* We accept symbols declared with eightbit_data. */ 5507 if (GET_CODE (x) == SYMBOL_REF) 5508 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0; 5509 5510 if (GET_CODE (x) != CONST_INT) 5511 return 0; 5512 5513 addr = INTVAL (x); 5514 5515 return (0 5516 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2)) 5517 || (TARGET_H8300H && IN_RANGE (addr, h1, h2)) 5518 || (TARGET_H8300S && IN_RANGE (addr, s1, s2))); 5519 } 5520 5521 /* Nonzero if X is a constant address suitable as an 16-bit absolute 5522 on H8/300H and H8S. */ 5523 5524 int 5525 h8300_tiny_constant_address_p (rtx x) 5526 { 5527 /* The ranges of the 16-bit area. */ 5528 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode); 5529 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode); 5530 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode); 5531 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode); 5532 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode); 5533 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode); 5534 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode); 5535 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode); 5536 5537 unsigned HOST_WIDE_INT addr; 5538 5539 switch (GET_CODE (x)) 5540 { 5541 case SYMBOL_REF: 5542 /* In the normal mode, any symbol fits in the 16-bit absolute 5543 address range. We also accept symbols declared with 5544 tiny_data. */ 5545 return (TARGET_NORMAL_MODE 5546 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0); 5547 5548 case CONST_INT: 5549 addr = INTVAL (x); 5550 return (TARGET_NORMAL_MODE 5551 || (TARGET_H8300H 5552 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4))) 5553 || (TARGET_H8300S 5554 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4)))); 5555 5556 case CONST: 5557 return TARGET_NORMAL_MODE; 5558 5559 default: 5560 return 0; 5561 } 5562 5563 } 5564 5565 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory 5566 locations that can be accessed as a 16-bit word. */ 5567 5568 int 5569 byte_accesses_mergeable_p (rtx addr1, rtx addr2) 5570 { 5571 HOST_WIDE_INT offset1, offset2; 5572 rtx reg1, reg2; 5573 5574 if (REG_P (addr1)) 5575 { 5576 reg1 = addr1; 5577 offset1 = 0; 5578 } 5579 else if (GET_CODE (addr1) == PLUS 5580 && REG_P (XEXP (addr1, 0)) 5581 && GET_CODE (XEXP (addr1, 1)) == CONST_INT) 5582 { 5583 reg1 = XEXP (addr1, 0); 5584 offset1 = INTVAL (XEXP (addr1, 1)); 5585 } 5586 else 5587 return 0; 5588 5589 if (REG_P (addr2)) 5590 { 5591 reg2 = addr2; 5592 offset2 = 0; 5593 } 5594 else if (GET_CODE (addr2) == PLUS 5595 && REG_P (XEXP (addr2, 0)) 5596 && GET_CODE (XEXP (addr2, 1)) == CONST_INT) 5597 { 5598 reg2 = XEXP (addr2, 0); 5599 offset2 = INTVAL (XEXP (addr2, 1)); 5600 } 5601 else 5602 return 0; 5603 5604 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx) 5605 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx)) 5606 && offset1 % 2 == 0 5607 && offset1 + 1 == offset2) 5608 return 1; 5609 5610 return 0; 5611 } 5612 5613 /* Return nonzero if we have the same comparison insn as I3 two insns 5614 before I3. I3 is assumed to be a comparison insn. */ 5615 5616 int 5617 same_cmp_preceding_p (rtx i3) 5618 { 5619 rtx i1, i2; 5620 5621 /* Make sure we have a sequence of three insns. */ 5622 i2 = prev_nonnote_insn (i3); 5623 if (i2 == NULL_RTX) 5624 return 0; 5625 i1 = prev_nonnote_insn (i2); 5626 if (i1 == NULL_RTX) 5627 return 0; 5628 5629 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5630 && any_condjump_p (i2) && onlyjump_p (i2)); 5631 } 5632 5633 /* Return nonzero if we have the same comparison insn as I1 two insns 5634 after I1. I1 is assumed to be a comparison insn. */ 5635 5636 int 5637 same_cmp_following_p (rtx i1) 5638 { 5639 rtx i2, i3; 5640 5641 /* Make sure we have a sequence of three insns. */ 5642 i2 = next_nonnote_insn (i1); 5643 if (i2 == NULL_RTX) 5644 return 0; 5645 i3 = next_nonnote_insn (i2); 5646 if (i3 == NULL_RTX) 5647 return 0; 5648 5649 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5650 && any_condjump_p (i2) && onlyjump_p (i2)); 5651 } 5652 5653 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes 5654 (or pops) N registers. OPERANDS are assumed to be an array of 5655 registers. */ 5656 5657 int 5658 h8300_regs_ok_for_stm (int n, rtx operands[]) 5659 { 5660 switch (n) 5661 { 5662 case 2: 5663 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) 5664 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) 5665 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5)); 5666 case 3: 5667 return ((REGNO (operands[0]) == 0 5668 && REGNO (operands[1]) == 1 5669 && REGNO (operands[2]) == 2) 5670 || (REGNO (operands[0]) == 4 5671 && REGNO (operands[1]) == 5 5672 && REGNO (operands[2]) == 6)); 5673 5674 case 4: 5675 return (REGNO (operands[0]) == 0 5676 && REGNO (operands[1]) == 1 5677 && REGNO (operands[2]) == 2 5678 && REGNO (operands[3]) == 3); 5679 default: 5680 gcc_unreachable (); 5681 } 5682 } 5683 5684 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ 5685 5686 int 5687 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, 5688 unsigned int new_reg) 5689 { 5690 /* Interrupt functions can only use registers that have already been 5691 saved by the prologue, even if they would normally be 5692 call-clobbered. */ 5693 5694 if (h8300_current_function_interrupt_function_p () 5695 && !df_regs_ever_live_p (new_reg)) 5696 return 0; 5697 5698 return 1; 5699 } 5700 5701 /* Returns true if register REGNO is safe to be allocated as a scratch 5702 register in the current function. */ 5703 5704 static bool 5705 h8300_hard_regno_scratch_ok (unsigned int regno) 5706 { 5707 if (h8300_current_function_interrupt_function_p () 5708 && ! WORD_REG_USED (regno)) 5709 return false; 5710 5711 return true; 5712 } 5713 5714 5715 /* Return nonzero if X is a legitimate constant. */ 5716 5717 int 5718 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED) 5719 { 5720 return 1; 5721 } 5722 5723 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */ 5724 5725 static int 5726 h8300_rtx_ok_for_base_p (rtx x, int strict) 5727 { 5728 /* Strip off SUBREG if any. */ 5729 if (GET_CODE (x) == SUBREG) 5730 x = SUBREG_REG (x); 5731 5732 return (REG_P (x) 5733 && (strict 5734 ? REG_OK_FOR_BASE_STRICT_P (x) 5735 : REG_OK_FOR_BASE_NONSTRICT_P (x))); 5736 } 5737 5738 /* Return nozero if X is a legitimate address. On the H8/300, a 5739 legitimate address has the form REG, REG+CONSTANT_ADDRESS or 5740 CONSTANT_ADDRESS. */ 5741 5742 static bool 5743 h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) 5744 { 5745 /* The register indirect addresses like @er0 is always valid. */ 5746 if (h8300_rtx_ok_for_base_p (x, strict)) 5747 return 1; 5748 5749 if (CONSTANT_ADDRESS_P (x)) 5750 return 1; 5751 5752 if (TARGET_H8300SX 5753 && ( GET_CODE (x) == PRE_INC 5754 || GET_CODE (x) == PRE_DEC 5755 || GET_CODE (x) == POST_INC 5756 || GET_CODE (x) == POST_DEC) 5757 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict)) 5758 return 1; 5759 5760 if (GET_CODE (x) == PLUS 5761 && CONSTANT_ADDRESS_P (XEXP (x, 1)) 5762 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0), 5763 mode, 0), strict)) 5764 return 1; 5765 5766 return 0; 5767 } 5768 5769 /* Worker function for HARD_REGNO_NREGS. 5770 5771 We pretend the MAC register is 32bits -- we don't have any data 5772 types on the H8 series to handle more than 32bits. */ 5773 5774 int 5775 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode) 5776 { 5777 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 5778 } 5779 5780 /* Worker function for HARD_REGNO_MODE_OK. */ 5781 5782 int 5783 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode) 5784 { 5785 if (TARGET_H8300) 5786 /* If an even reg, then anything goes. Otherwise the mode must be 5787 QI or HI. */ 5788 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode); 5789 else 5790 /* MAC register can only be of SImode. Otherwise, anything 5791 goes. */ 5792 return regno == MAC_REG ? mode == SImode : 1; 5793 } 5794 5795 /* Perform target dependent optabs initialization. */ 5796 static void 5797 h8300_init_libfuncs (void) 5798 { 5799 set_optab_libfunc (smul_optab, HImode, "__mulhi3"); 5800 set_optab_libfunc (sdiv_optab, HImode, "__divhi3"); 5801 set_optab_libfunc (udiv_optab, HImode, "__udivhi3"); 5802 set_optab_libfunc (smod_optab, HImode, "__modhi3"); 5803 set_optab_libfunc (umod_optab, HImode, "__umodhi3"); 5804 } 5805 5806 /* Worker function for TARGET_RETURN_IN_MEMORY. */ 5807 5808 static bool 5809 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 5810 { 5811 return (TYPE_MODE (type) == BLKmode 5812 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8)); 5813 } 5814 5815 /* We emit the entire trampoline here. Depending on the pointer size, 5816 we use a different trampoline. 5817 5818 Pmode == HImode 5819 vvvv context 5820 1 0000 7903xxxx mov.w #0x1234,r3 5821 2 0004 5A00xxxx jmp @0x1234 5822 ^^^^ function 5823 5824 Pmode == SImode 5825 vvvvvvvv context 5826 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 5827 3 0006 5Axxxxxx jmp @0x123456 5828 ^^^^^^ function 5829 */ 5830 5831 static void 5832 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) 5833 { 5834 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 5835 rtx mem; 5836 5837 if (Pmode == HImode) 5838 { 5839 mem = adjust_address (m_tramp, HImode, 0); 5840 emit_move_insn (mem, GEN_INT (0x7903)); 5841 mem = adjust_address (m_tramp, Pmode, 2); 5842 emit_move_insn (mem, cxt); 5843 mem = adjust_address (m_tramp, HImode, 4); 5844 emit_move_insn (mem, GEN_INT (0x5a00)); 5845 mem = adjust_address (m_tramp, Pmode, 6); 5846 emit_move_insn (mem, fnaddr); 5847 } 5848 else 5849 { 5850 rtx tem; 5851 5852 mem = adjust_address (m_tramp, HImode, 0); 5853 emit_move_insn (mem, GEN_INT (0x7a03)); 5854 mem = adjust_address (m_tramp, Pmode, 2); 5855 emit_move_insn (mem, cxt); 5856 5857 tem = copy_to_reg (fnaddr); 5858 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); 5859 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); 5860 mem = adjust_address (m_tramp, SImode, 6); 5861 emit_move_insn (mem, tem); 5862 } 5863 } 5864 5865 /* Initialize the GCC target structure. */ 5866 #undef TARGET_ATTRIBUTE_TABLE 5867 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table 5868 5869 #undef TARGET_ASM_ALIGNED_HI_OP 5870 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 5871 5872 #undef TARGET_ASM_FILE_START 5873 #define TARGET_ASM_FILE_START h8300_file_start 5874 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 5875 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 5876 5877 #undef TARGET_ASM_FILE_END 5878 #define TARGET_ASM_FILE_END h8300_file_end 5879 5880 #undef TARGET_ENCODE_SECTION_INFO 5881 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info 5882 5883 #undef TARGET_INSERT_ATTRIBUTES 5884 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes 5885 5886 #undef TARGET_RTX_COSTS 5887 #define TARGET_RTX_COSTS h8300_rtx_costs 5888 5889 #undef TARGET_INIT_LIBFUNCS 5890 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs 5891 5892 #undef TARGET_RETURN_IN_MEMORY 5893 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory 5894 5895 #undef TARGET_MACHINE_DEPENDENT_REORG 5896 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg 5897 5898 #undef TARGET_HARD_REGNO_SCRATCH_OK 5899 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok 5900 5901 #undef TARGET_LEGITIMATE_ADDRESS_P 5902 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p 5903 5904 #undef TARGET_DEFAULT_TARGET_FLAGS 5905 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT 5906 5907 #undef TARGET_CAN_ELIMINATE 5908 #define TARGET_CAN_ELIMINATE h8300_can_eliminate 5909 5910 #undef TARGET_TRAMPOLINE_INIT 5911 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init 5912 5913 struct gcc_target targetm = TARGET_INITIALIZER; 5914