1 /* Subroutines for insn-output.c for Renesas H8/300. 2 Copyright (C) 1992-2018 Free Software Foundation, Inc. 3 Contributed by Steve Chamberlain (sac@cygnus.com), 4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #define IN_TARGET_CODE 1 23 24 #include "config.h" 25 #include "system.h" 26 #include "coretypes.h" 27 #include "backend.h" 28 #include "target.h" 29 #include "rtl.h" 30 #include "tree.h" 31 #include "df.h" 32 #include "memmodel.h" 33 #include "tm_p.h" 34 #include "stringpool.h" 35 #include "attribs.h" 36 #include "optabs.h" 37 #include "regs.h" 38 #include "emit-rtl.h" 39 #include "recog.h" 40 #include "diagnostic-core.h" 41 #include "alias.h" 42 #include "stor-layout.h" 43 #include "varasm.h" 44 #include "calls.h" 45 #include "conditions.h" 46 #include "output.h" 47 #include "insn-attr.h" 48 #include "flags.h" 49 #include "explow.h" 50 #include "expr.h" 51 #include "tm-constrs.h" 52 #include "builtins.h" 53 54 /* This file should be included last. */ 55 #include "target-def.h" 56 57 /* Classifies a h8300_src_operand or h8300_dst_operand. 58 59 H8OP_IMMEDIATE 60 A constant operand of some sort. 61 62 H8OP_REGISTER 63 An ordinary register. 64 65 H8OP_MEM_ABSOLUTE 66 A memory reference with a constant address. 67 68 H8OP_MEM_BASE 69 A memory reference with a register as its address. 70 71 H8OP_MEM_COMPLEX 72 Some other kind of memory reference. */ 73 enum h8300_operand_class 74 { 75 H8OP_IMMEDIATE, 76 H8OP_REGISTER, 77 H8OP_MEM_ABSOLUTE, 78 H8OP_MEM_BASE, 79 H8OP_MEM_COMPLEX, 80 NUM_H8OPS 81 }; 82 83 /* For a general two-operand instruction, element [X][Y] gives 84 the length of the opcode fields when the first operand has class 85 (X + 1) and the second has class Y. */ 86 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS]; 87 88 /* Forward declarations. */ 89 static const char *byte_reg (rtx, int); 90 static int h8300_interrupt_function_p (tree); 91 static int h8300_saveall_function_p (tree); 92 static int h8300_monitor_function_p (tree); 93 static int h8300_os_task_function_p (tree); 94 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool); 95 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT); 96 static unsigned int compute_saved_regs (void); 97 static const char *cond_string (enum rtx_code); 98 static unsigned int h8300_asm_insn_count (const char *); 99 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *); 100 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *); 101 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *); 102 static void h8300_print_operand_address (FILE *, machine_mode, rtx); 103 static void h8300_print_operand (FILE *, rtx, int); 104 static bool h8300_print_operand_punct_valid_p (unsigned char code); 105 #ifndef OBJECT_FORMAT_ELF 106 static void h8300_asm_named_section (const char *, unsigned int, tree); 107 #endif 108 static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t); 109 static int h8300_and_costs (rtx); 110 static int h8300_shift_costs (rtx); 111 static void h8300_push_pop (int, int, bool, bool); 112 static int h8300_stack_offset_p (rtx, int); 113 static int h8300_ldm_stm_regno (rtx, int, int, int); 114 static void h8300_reorg (void); 115 static unsigned int h8300_constant_length (rtx); 116 static unsigned int h8300_displacement_length (rtx, int); 117 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *); 118 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *); 119 static unsigned int h8300_unary_length (rtx); 120 static unsigned int h8300_short_immediate_length (rtx); 121 static unsigned int h8300_bitfield_length (rtx, rtx); 122 static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *); 123 static bool h8300_short_move_mem_p (rtx, enum rtx_code); 124 static unsigned int h8300_move_length (rtx *, const h8300_length_table *); 125 static bool h8300_hard_regno_scratch_ok (unsigned int); 126 static rtx h8300_get_index (rtx, machine_mode mode, int *); 127 128 /* CPU_TYPE, says what cpu we're compiling for. */ 129 int cpu_type; 130 131 /* True if a #pragma interrupt has been seen for the current function. */ 132 static int pragma_interrupt; 133 134 /* True if a #pragma saveall has been seen for the current function. */ 135 static int pragma_saveall; 136 137 static const char *const names_big[] = 138 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }; 139 140 static const char *const names_extended[] = 141 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" }; 142 143 static const char *const names_upper_extended[] = 144 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" }; 145 146 /* Points to one of the above. */ 147 /* ??? The above could be put in an array indexed by CPU_TYPE. */ 148 const char * const *h8_reg_names; 149 150 /* Various operations needed by the following, indexed by CPU_TYPE. */ 151 152 const char *h8_push_op, *h8_pop_op, *h8_mov_op; 153 154 /* Value of MOVE_RATIO. */ 155 int h8300_move_ratio; 156 157 /* See below where shifts are handled for explanation of this enum. */ 158 159 enum shift_alg 160 { 161 SHIFT_INLINE, 162 SHIFT_ROT_AND, 163 SHIFT_SPECIAL, 164 SHIFT_LOOP 165 }; 166 167 /* Symbols of the various shifts which can be used as indices. */ 168 169 enum shift_type 170 { 171 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT 172 }; 173 174 /* Macros to keep the shift algorithm tables small. */ 175 #define INL SHIFT_INLINE 176 #define ROT SHIFT_ROT_AND 177 #define LOP SHIFT_LOOP 178 #define SPC SHIFT_SPECIAL 179 180 /* The shift algorithms for each machine, mode, shift type, and shift 181 count are defined below. The three tables below correspond to 182 QImode, HImode, and SImode, respectively. Each table is organized 183 by, in the order of indices, machine, shift type, and shift count. */ 184 185 static enum shift_alg shift_alg_qi[3][3][8] = { 186 { 187 /* TARGET_H8300 */ 188 /* 0 1 2 3 4 5 6 7 */ 189 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 190 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 191 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ 192 }, 193 { 194 /* TARGET_H8300H */ 195 /* 0 1 2 3 4 5 6 7 */ 196 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 197 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 198 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ 199 }, 200 { 201 /* TARGET_H8300S */ 202 /* 0 1 2 3 4 5 6 7 */ 203 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */ 204 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */ 205 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */ 206 } 207 }; 208 209 static enum shift_alg shift_alg_hi[3][3][16] = { 210 { 211 /* TARGET_H8300 */ 212 /* 0 1 2 3 4 5 6 7 */ 213 /* 8 9 10 11 12 13 14 15 */ 214 { INL, INL, INL, INL, INL, INL, INL, SPC, 215 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 216 { INL, INL, INL, INL, INL, LOP, LOP, SPC, 217 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 218 { INL, INL, INL, INL, INL, LOP, LOP, SPC, 219 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 220 }, 221 { 222 /* TARGET_H8300H */ 223 /* 0 1 2 3 4 5 6 7 */ 224 /* 8 9 10 11 12 13 14 15 */ 225 { INL, INL, INL, INL, INL, INL, INL, SPC, 226 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 227 { INL, INL, INL, INL, INL, INL, INL, SPC, 228 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 229 { INL, INL, INL, INL, INL, INL, INL, SPC, 230 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 231 }, 232 { 233 /* TARGET_H8300S */ 234 /* 0 1 2 3 4 5 6 7 */ 235 /* 8 9 10 11 12 13 14 15 */ 236 { INL, INL, INL, INL, INL, INL, INL, INL, 237 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 238 { INL, INL, INL, INL, INL, INL, INL, INL, 239 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 240 { INL, INL, INL, INL, INL, INL, INL, INL, 241 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 242 } 243 }; 244 245 static enum shift_alg shift_alg_si[3][3][32] = { 246 { 247 /* TARGET_H8300 */ 248 /* 0 1 2 3 4 5 6 7 */ 249 /* 8 9 10 11 12 13 14 15 */ 250 /* 16 17 18 19 20 21 22 23 */ 251 /* 24 25 26 27 28 29 30 31 */ 252 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 253 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, 254 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP, 255 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */ 256 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 257 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC, 258 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP, 259 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */ 260 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 261 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 262 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP, 263 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ 264 }, 265 { 266 /* TARGET_H8300H */ 267 /* 0 1 2 3 4 5 6 7 */ 268 /* 8 9 10 11 12 13 14 15 */ 269 /* 16 17 18 19 20 21 22 23 */ 270 /* 24 25 26 27 28 29 30 31 */ 271 { INL, INL, INL, INL, INL, LOP, LOP, LOP, 272 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 273 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, 274 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 275 { INL, INL, INL, INL, INL, LOP, LOP, LOP, 276 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 277 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, 278 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 279 { INL, INL, INL, INL, INL, LOP, LOP, LOP, 280 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, 281 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, 282 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ 283 }, 284 { 285 /* TARGET_H8300S */ 286 /* 0 1 2 3 4 5 6 7 */ 287 /* 8 9 10 11 12 13 14 15 */ 288 /* 16 17 18 19 20 21 22 23 */ 289 /* 24 25 26 27 28 29 30 31 */ 290 { INL, INL, INL, INL, INL, INL, INL, INL, 291 INL, INL, INL, LOP, LOP, LOP, LOP, SPC, 292 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, 293 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 294 { INL, INL, INL, INL, INL, INL, INL, INL, 295 INL, INL, INL, LOP, LOP, LOP, LOP, SPC, 296 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, 297 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 298 { INL, INL, INL, INL, INL, INL, INL, INL, 299 INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 300 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, 301 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ 302 } 303 }; 304 305 #undef INL 306 #undef ROT 307 #undef LOP 308 #undef SPC 309 310 enum h8_cpu 311 { 312 H8_300, 313 H8_300H, 314 H8_S 315 }; 316 317 /* Initialize various cpu specific globals at start up. */ 318 319 static void 320 h8300_option_override (void) 321 { 322 static const char *const h8_push_ops[2] = { "push" , "push.l" }; 323 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" }; 324 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; 325 326 #ifndef OBJECT_FORMAT_ELF 327 if (TARGET_H8300SX) 328 { 329 error ("-msx is not supported in coff"); 330 target_flags |= MASK_H8300S; 331 } 332 #endif 333 334 if (TARGET_H8300) 335 { 336 cpu_type = (int) CPU_H8300; 337 h8_reg_names = names_big; 338 } 339 else 340 { 341 /* For this we treat the H8/300H and H8S the same. */ 342 cpu_type = (int) CPU_H8300H; 343 h8_reg_names = names_extended; 344 } 345 h8_push_op = h8_push_ops[cpu_type]; 346 h8_pop_op = h8_pop_ops[cpu_type]; 347 h8_mov_op = h8_mov_ops[cpu_type]; 348 349 if (!TARGET_H8300S && TARGET_MAC) 350 { 351 error ("-ms2600 is used without -ms"); 352 target_flags |= MASK_H8300S_1; 353 } 354 355 if (TARGET_H8300 && TARGET_NORMAL_MODE) 356 { 357 error ("-mn is used without -mh or -ms or -msx"); 358 target_flags ^= MASK_NORMAL_MODE; 359 } 360 361 if (! TARGET_H8300S && TARGET_EXR) 362 { 363 error ("-mexr is used without -ms"); 364 target_flags |= MASK_H8300S_1; 365 } 366 367 if (TARGET_H8300 && TARGET_INT32) 368 { 369 error ("-mint32 is not supported for H8300 and H8300L targets"); 370 target_flags ^= MASK_INT32; 371 } 372 373 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR)) 374 { 375 error ("-mexr is used without -ms or -msx"); 376 target_flags |= MASK_H8300S_1; 377 } 378 379 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR)) 380 { 381 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \ 382 - Option ignored!"); 383 } 384 385 #ifdef H8300_LINUX 386 if ((TARGET_NORMAL_MODE)) 387 { 388 error ("-mn is not supported for linux targets"); 389 target_flags ^= MASK_NORMAL_MODE; 390 } 391 #endif 392 393 /* Some of the shifts are optimized for speed by default. 394 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html 395 If optimizing for size, change shift_alg for those shift to 396 SHIFT_LOOP. */ 397 if (optimize_size) 398 { 399 /* H8/300 */ 400 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP; 401 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP; 402 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP; 403 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP; 404 405 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP; 406 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP; 407 408 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 409 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 410 411 /* H8/300H */ 412 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; 413 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; 414 415 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; 416 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; 417 418 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; 419 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; 420 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 421 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 422 423 /* H8S */ 424 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 425 } 426 427 /* Work out a value for MOVE_RATIO. */ 428 if (!TARGET_H8300SX) 429 { 430 /* Memory-memory moves are quite expensive without the 431 h8sx instructions. */ 432 h8300_move_ratio = 3; 433 } 434 else if (flag_omit_frame_pointer) 435 { 436 /* movmd sequences are fairly cheap when er6 isn't fixed. They can 437 sometimes be as short as two individual memory-to-memory moves, 438 but since they use all the call-saved registers, it seems better 439 to allow up to three moves here. */ 440 h8300_move_ratio = 4; 441 } 442 else if (optimize_size) 443 { 444 /* In this case we don't use movmd sequences since they tend 445 to be longer than calls to memcpy(). Memory-to-memory 446 moves are cheaper than for !TARGET_H8300SX, so it makes 447 sense to have a slightly higher threshold. */ 448 h8300_move_ratio = 4; 449 } 450 else 451 { 452 /* We use movmd sequences for some moves since it can be quicker 453 than calling memcpy(). The sequences will need to save and 454 restore er6 though, so bump up the cost. */ 455 h8300_move_ratio = 6; 456 } 457 458 /* This target defaults to strict volatile bitfields. */ 459 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) 460 flag_strict_volatile_bitfields = 1; 461 } 462 463 /* Return the byte register name for a register rtx X. B should be 0 464 if you want a lower byte register. B should be 1 if you want an 465 upper byte register. */ 466 467 static const char * 468 byte_reg (rtx x, int b) 469 { 470 static const char *const names_small[] = { 471 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", 472 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h" 473 }; 474 475 gcc_assert (REG_P (x)); 476 477 return names_small[REGNO (x) * 2 + b]; 478 } 479 480 /* REGNO must be saved/restored across calls if this macro is true. */ 481 482 #define WORD_REG_USED(regno) \ 483 (regno < SP_REG \ 484 /* No need to save registers if this function will not return. */ \ 485 && ! TREE_THIS_VOLATILE (current_function_decl) \ 486 && (h8300_saveall_function_p (current_function_decl) \ 487 /* Save any call saved register that was used. */ \ 488 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \ 489 /* Save the frame pointer if it was used. */ \ 490 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \ 491 /* Save any register used in an interrupt handler. */ \ 492 || (h8300_current_function_interrupt_function_p () \ 493 && df_regs_ever_live_p (regno)) \ 494 /* Save call clobbered registers in non-leaf interrupt \ 495 handlers. */ \ 496 || (h8300_current_function_interrupt_function_p () \ 497 && call_used_regs[regno] \ 498 && !crtl->is_leaf))) 499 500 /* We use this to wrap all emitted insns in the prologue. */ 501 static rtx_insn * 502 F (rtx_insn *x, bool set_it) 503 { 504 if (set_it) 505 RTX_FRAME_RELATED_P (x) = 1; 506 return x; 507 } 508 509 /* Mark all the subexpressions of the PARALLEL rtx PAR as 510 frame-related. Return PAR. 511 512 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a 513 PARALLEL rtx other than the first if they do not have the 514 FRAME_RELATED flag set on them. */ 515 static rtx 516 Fpa (rtx par) 517 { 518 int len = XVECLEN (par, 0); 519 int i; 520 521 for (i = 0; i < len; i++) 522 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1; 523 524 return par; 525 } 526 527 /* Output assembly language to FILE for the operation OP with operand size 528 SIZE to adjust the stack pointer. */ 529 530 static void 531 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue) 532 { 533 /* If the frame size is 0, we don't have anything to do. */ 534 if (size == 0) 535 return; 536 537 /* H8/300 cannot add/subtract a large constant with a single 538 instruction. If a temporary register is available, load the 539 constant to it and then do the addition. */ 540 if (TARGET_H8300 541 && size > 4 542 && !h8300_current_function_interrupt_function_p () 543 && !(cfun->static_chain_decl != NULL && sign < 0)) 544 { 545 rtx r3 = gen_rtx_REG (Pmode, 3); 546 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue); 547 F (emit_insn (gen_addhi3 (stack_pointer_rtx, 548 stack_pointer_rtx, r3)), in_prologue); 549 } 550 else 551 { 552 /* The stack adjustment made here is further optimized by the 553 splitter. In case of H8/300, the splitter always splits the 554 addition emitted here to make the adjustment interrupt-safe. 555 FIXME: We don't always tag those, because we don't know what 556 the splitter will do. */ 557 if (Pmode == HImode) 558 { 559 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx, 560 stack_pointer_rtx, 561 GEN_INT (sign * size))); 562 if (size < 4) 563 F (x, in_prologue); 564 } 565 else 566 F (emit_insn (gen_addsi3 (stack_pointer_rtx, 567 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue); 568 } 569 } 570 571 /* Round up frame size SIZE. */ 572 573 static HOST_WIDE_INT 574 round_frame_size (HOST_WIDE_INT size) 575 { 576 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1) 577 & -STACK_BOUNDARY / BITS_PER_UNIT); 578 } 579 580 /* Compute which registers to push/pop. 581 Return a bit vector of registers. */ 582 583 static unsigned int 584 compute_saved_regs (void) 585 { 586 unsigned int saved_regs = 0; 587 int regno; 588 589 /* Construct a bit vector of registers to be pushed/popped. */ 590 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 591 { 592 if (WORD_REG_USED (regno)) 593 saved_regs |= 1 << regno; 594 } 595 596 /* Don't push/pop the frame pointer as it is treated separately. */ 597 if (frame_pointer_needed) 598 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM); 599 600 return saved_regs; 601 } 602 603 /* Emit an insn to push register RN. */ 604 605 static rtx 606 push (int rn, bool in_prologue) 607 { 608 rtx reg = gen_rtx_REG (word_mode, rn); 609 rtx x; 610 611 if (TARGET_H8300) 612 x = gen_push_h8300 (reg); 613 else if (!TARGET_NORMAL_MODE) 614 x = gen_push_h8300hs_advanced (reg); 615 else 616 x = gen_push_h8300hs_normal (reg); 617 x = F (emit_insn (x), in_prologue); 618 add_reg_note (x, REG_INC, stack_pointer_rtx); 619 return x; 620 } 621 622 /* Emit an insn to pop register RN. */ 623 624 static rtx 625 pop (int rn) 626 { 627 rtx reg = gen_rtx_REG (word_mode, rn); 628 rtx x; 629 630 if (TARGET_H8300) 631 x = gen_pop_h8300 (reg); 632 else if (!TARGET_NORMAL_MODE) 633 x = gen_pop_h8300hs_advanced (reg); 634 else 635 x = gen_pop_h8300hs_normal (reg); 636 x = emit_insn (x); 637 add_reg_note (x, REG_INC, stack_pointer_rtx); 638 return x; 639 } 640 641 /* Emit an instruction to push or pop NREGS consecutive registers 642 starting at register REGNO. POP_P selects a pop rather than a 643 push and RETURN_P is true if the instruction should return. 644 645 It must be possible to do the requested operation in a single 646 instruction. If NREGS == 1 && !RETURN_P, use a normal push 647 or pop insn. Otherwise emit a parallel of the form: 648 649 (parallel 650 [(return) ;; if RETURN_P 651 (save or restore REGNO) 652 (save or restore REGNO + 1) 653 ... 654 (save or restore REGNO + NREGS - 1) 655 (set sp (plus sp (const_int adjust)))] */ 656 657 static void 658 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p) 659 { 660 int i, j; 661 rtvec vec; 662 rtx sp, offset, x; 663 664 /* See whether we can use a simple push or pop. */ 665 if (!return_p && nregs == 1) 666 { 667 if (pop_p) 668 pop (regno); 669 else 670 push (regno, false); 671 return; 672 } 673 674 /* We need one element for the return insn, if present, one for each 675 register, and one for stack adjustment. */ 676 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1); 677 sp = stack_pointer_rtx; 678 i = 0; 679 680 /* Add the return instruction. */ 681 if (return_p) 682 { 683 RTVEC_ELT (vec, i) = ret_rtx; 684 i++; 685 } 686 687 /* Add the register moves. */ 688 for (j = 0; j < nregs; j++) 689 { 690 rtx lhs, rhs; 691 692 if (pop_p) 693 { 694 /* Register REGNO + NREGS - 1 is popped first. Before the 695 stack adjustment, its slot is at address @sp. */ 696 lhs = gen_rtx_REG (SImode, regno + j); 697 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, 698 (nregs - j - 1) * 4)); 699 } 700 else 701 { 702 /* Register REGNO is pushed first and will be stored at @(-4,sp). */ 703 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4)); 704 rhs = gen_rtx_REG (SImode, regno + j); 705 } 706 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs); 707 } 708 709 /* Add the stack adjustment. */ 710 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4); 711 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset)); 712 713 x = gen_rtx_PARALLEL (VOIDmode, vec); 714 if (!pop_p) 715 x = Fpa (x); 716 717 if (return_p) 718 emit_jump_insn (x); 719 else 720 emit_insn (x); 721 } 722 723 /* Return true if X has the value sp + OFFSET. */ 724 725 static int 726 h8300_stack_offset_p (rtx x, int offset) 727 { 728 if (offset == 0) 729 return x == stack_pointer_rtx; 730 731 return (GET_CODE (x) == PLUS 732 && XEXP (x, 0) == stack_pointer_rtx 733 && GET_CODE (XEXP (x, 1)) == CONST_INT 734 && INTVAL (XEXP (x, 1)) == offset); 735 } 736 737 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in 738 something that may be an ldm or stm instruction. If it fits 739 the required template, return the register it loads or stores, 740 otherwise return -1. 741 742 LOAD_P is true if X should be a load, false if it should be a store. 743 NREGS is the number of registers that the whole instruction is expected 744 to load or store. INDEX is the index of the register that X should 745 load or store, relative to the lowest-numbered register. */ 746 747 static int 748 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs) 749 { 750 int regindex, memindex, offset; 751 752 if (load_p) 753 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4; 754 else 755 memindex = 0, regindex = 1, offset = (index + 1) * -4; 756 757 if (GET_CODE (x) == SET 758 && GET_CODE (XEXP (x, regindex)) == REG 759 && GET_CODE (XEXP (x, memindex)) == MEM 760 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset)) 761 return REGNO (XEXP (x, regindex)); 762 763 return -1; 764 } 765 766 /* Return true if the elements of VEC starting at FIRST describe an 767 ldm or stm instruction (LOAD_P says which). */ 768 769 int 770 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first) 771 { 772 rtx last; 773 int nregs, i, regno, adjust; 774 775 /* There must be a stack adjustment, a register move, and at least one 776 other operation (a return or another register move). */ 777 if (GET_NUM_ELEM (vec) < 3) 778 return false; 779 780 /* Get the range of registers to be pushed or popped. */ 781 nregs = GET_NUM_ELEM (vec) - first - 1; 782 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs); 783 784 /* Check that the call to h8300_ldm_stm_regno succeeded and 785 that we're only dealing with GPRs. */ 786 if (regno < 0 || regno + nregs > 8) 787 return false; 788 789 /* 2-register h8s instructions must start with an even-numbered register. 790 3- and 4-register instructions must start with er0 or er4. */ 791 if (!TARGET_H8300SX) 792 { 793 if ((regno & 1) != 0) 794 return false; 795 if (nregs > 2 && (regno & 3) != 0) 796 return false; 797 } 798 799 /* Check the other loads or stores. */ 800 for (i = 1; i < nregs; i++) 801 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs) 802 != regno + i) 803 return false; 804 805 /* Check the stack adjustment. */ 806 last = RTVEC_ELT (vec, first + nregs); 807 adjust = (load_p ? nregs : -nregs) * 4; 808 return (GET_CODE (last) == SET 809 && SET_DEST (last) == stack_pointer_rtx 810 && h8300_stack_offset_p (SET_SRC (last), adjust)); 811 } 812 813 /* This is what the stack looks like after the prolog of 814 a function with a frame has been set up: 815 816 <args> 817 PC 818 FP <- fp 819 <locals> 820 <saved registers> <- sp 821 822 This is what the stack looks like after the prolog of 823 a function which doesn't have a frame: 824 825 <args> 826 PC 827 <locals> 828 <saved registers> <- sp 829 */ 830 831 /* Generate RTL code for the function prologue. */ 832 833 void 834 h8300_expand_prologue (void) 835 { 836 int regno; 837 int saved_regs; 838 int n_regs; 839 840 /* If the current function has the OS_Task attribute set, then 841 we have a naked prologue. */ 842 if (h8300_os_task_function_p (current_function_decl)) 843 return; 844 845 if (h8300_monitor_function_p (current_function_decl)) 846 /* The monitor function act as normal functions, which means it 847 can accept parameters and return values. In addition to this, 848 interrupts are masked in prologue and return with "rte" in epilogue. */ 849 emit_insn (gen_monitor_prologue ()); 850 851 if (frame_pointer_needed) 852 { 853 /* Push fp. */ 854 push (HARD_FRAME_POINTER_REGNUM, true); 855 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true); 856 } 857 858 /* Push the rest of the registers in ascending order. */ 859 saved_regs = compute_saved_regs (); 860 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs) 861 { 862 n_regs = 1; 863 if (saved_regs & (1 << regno)) 864 { 865 if (TARGET_H8300S) 866 { 867 /* See how many registers we can push at the same time. */ 868 if ((!TARGET_H8300SX || (regno & 3) == 0) 869 && ((saved_regs >> regno) & 0x0f) == 0x0f) 870 n_regs = 4; 871 872 else if ((!TARGET_H8300SX || (regno & 3) == 0) 873 && ((saved_regs >> regno) & 0x07) == 0x07) 874 n_regs = 3; 875 876 else if ((!TARGET_H8300SX || (regno & 1) == 0) 877 && ((saved_regs >> regno) & 0x03) == 0x03) 878 n_regs = 2; 879 } 880 881 h8300_push_pop (regno, n_regs, false, false); 882 } 883 } 884 885 /* Leave room for locals. */ 886 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true); 887 888 if (flag_stack_usage_info) 889 current_function_static_stack_size 890 = round_frame_size (get_frame_size ()) 891 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD) 892 + (frame_pointer_needed ? UNITS_PER_WORD : 0); 893 } 894 895 /* Return nonzero if we can use "rts" for the function currently being 896 compiled. */ 897 898 int 899 h8300_can_use_return_insn_p (void) 900 { 901 return (reload_completed 902 && !frame_pointer_needed 903 && get_frame_size () == 0 904 && compute_saved_regs () == 0); 905 } 906 907 /* Generate RTL code for the function epilogue. */ 908 909 void 910 h8300_expand_epilogue (void) 911 { 912 int regno; 913 int saved_regs; 914 int n_regs; 915 HOST_WIDE_INT frame_size; 916 bool returned_p; 917 918 if (h8300_os_task_function_p (current_function_decl)) 919 /* OS_Task epilogues are nearly naked -- they just have an 920 rts instruction. */ 921 return; 922 923 frame_size = round_frame_size (get_frame_size ()); 924 returned_p = false; 925 926 /* Deallocate locals. */ 927 h8300_emit_stack_adjustment (1, frame_size, false); 928 929 /* Pop the saved registers in descending order. */ 930 saved_regs = compute_saved_regs (); 931 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs) 932 { 933 n_regs = 1; 934 if (saved_regs & (1 << regno)) 935 { 936 if (TARGET_H8300S) 937 { 938 /* See how many registers we can pop at the same time. */ 939 if ((TARGET_H8300SX || (regno & 3) == 3) 940 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f) 941 n_regs = 4; 942 943 else if ((TARGET_H8300SX || (regno & 3) == 2) 944 && ((saved_regs << 2 >> regno) & 0x07) == 0x07) 945 n_regs = 3; 946 947 else if ((TARGET_H8300SX || (regno & 1) == 1) 948 && ((saved_regs << 1 >> regno) & 0x03) == 0x03) 949 n_regs = 2; 950 } 951 952 /* See if this pop would be the last insn before the return. 953 If so, use rte/l or rts/l instead of pop or ldm.l. */ 954 if (TARGET_H8300SX 955 && !frame_pointer_needed 956 && frame_size == 0 957 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0) 958 returned_p = true; 959 960 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p); 961 } 962 } 963 964 /* Pop frame pointer if we had one. */ 965 if (frame_pointer_needed) 966 { 967 if (TARGET_H8300SX) 968 returned_p = true; 969 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p); 970 } 971 972 if (!returned_p) 973 emit_jump_insn (ret_rtx); 974 } 975 976 /* Return nonzero if the current function is an interrupt 977 function. */ 978 979 int 980 h8300_current_function_interrupt_function_p (void) 981 { 982 return (h8300_interrupt_function_p (current_function_decl)); 983 } 984 985 int 986 h8300_current_function_monitor_function_p () 987 { 988 return (h8300_monitor_function_p (current_function_decl)); 989 } 990 991 /* Output assembly code for the start of the file. */ 992 993 static void 994 h8300_file_start (void) 995 { 996 default_file_start (); 997 998 if (TARGET_H8300SX) 999 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file); 1000 else if (TARGET_H8300S) 1001 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file); 1002 else if (TARGET_H8300H) 1003 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file); 1004 } 1005 1006 /* Output assembly language code for the end of file. */ 1007 1008 static void 1009 h8300_file_end (void) 1010 { 1011 fputs ("\t.end\n", asm_out_file); 1012 } 1013 1014 /* Split an add of a small constant into two adds/subs insns. 1015 1016 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec 1017 instead of adds/subs. */ 1018 1019 void 1020 split_adds_subs (machine_mode mode, rtx *operands) 1021 { 1022 HOST_WIDE_INT val = INTVAL (operands[1]); 1023 rtx reg = operands[0]; 1024 HOST_WIDE_INT sign = 1; 1025 HOST_WIDE_INT amount; 1026 rtx (*gen_add) (rtx, rtx, rtx); 1027 1028 /* Force VAL to be positive so that we do not have to consider the 1029 sign. */ 1030 if (val < 0) 1031 { 1032 val = -val; 1033 sign = -1; 1034 } 1035 1036 switch (mode) 1037 { 1038 case E_HImode: 1039 gen_add = gen_addhi3; 1040 break; 1041 1042 case E_SImode: 1043 gen_add = gen_addsi3; 1044 break; 1045 1046 default: 1047 gcc_unreachable (); 1048 } 1049 1050 /* Try different amounts in descending order. */ 1051 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2; 1052 amount > 0; 1053 amount /= 2) 1054 { 1055 for (; val >= amount; val -= amount) 1056 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount))); 1057 } 1058 1059 return; 1060 } 1061 1062 /* Handle machine specific pragmas for compatibility with existing 1063 compilers for the H8/300. 1064 1065 pragma saveall generates prologue/epilogue code which saves and 1066 restores all the registers on function entry. 1067 1068 pragma interrupt saves and restores all registers, and exits with 1069 an rte instruction rather than an rts. A pointer to a function 1070 with this attribute may be safely used in an interrupt vector. */ 1071 1072 void 1073 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1074 { 1075 pragma_interrupt = 1; 1076 } 1077 1078 void 1079 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1080 { 1081 pragma_saveall = 1; 1082 } 1083 1084 /* If the next function argument with MODE and TYPE is to be passed in 1085 a register, return a reg RTX for the hard register in which to pass 1086 the argument. CUM represents the state after the last argument. 1087 If the argument is to be pushed, NULL_RTX is returned. 1088 1089 On the H8/300 all normal args are pushed, unless -mquickcall in which 1090 case the first 3 arguments are passed in registers. */ 1091 1092 static rtx 1093 h8300_function_arg (cumulative_args_t cum_v, machine_mode mode, 1094 const_tree type, bool named) 1095 { 1096 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1097 1098 static const char *const hand_list[] = { 1099 "__main", 1100 "__cmpsi2", 1101 "__divhi3", 1102 "__modhi3", 1103 "__udivhi3", 1104 "__umodhi3", 1105 "__divsi3", 1106 "__modsi3", 1107 "__udivsi3", 1108 "__umodsi3", 1109 "__mulhi3", 1110 "__mulsi3", 1111 "__reg_memcpy", 1112 "__reg_memset", 1113 "__ucmpsi2", 1114 0, 1115 }; 1116 1117 rtx result = NULL_RTX; 1118 const char *fname; 1119 int regpass = 0; 1120 1121 /* Never pass unnamed arguments in registers. */ 1122 if (!named) 1123 return NULL_RTX; 1124 1125 /* Pass 3 regs worth of data in regs when user asked on the command line. */ 1126 if (TARGET_QUICKCALL) 1127 regpass = 3; 1128 1129 /* If calling hand written assembler, use 4 regs of args. */ 1130 if (cum->libcall) 1131 { 1132 const char * const *p; 1133 1134 fname = XSTR (cum->libcall, 0); 1135 1136 /* See if this libcall is one of the hand coded ones. */ 1137 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) 1138 ; 1139 1140 if (*p) 1141 regpass = 4; 1142 } 1143 1144 if (regpass) 1145 { 1146 int size; 1147 1148 if (mode == BLKmode) 1149 size = int_size_in_bytes (type); 1150 else 1151 size = GET_MODE_SIZE (mode); 1152 1153 if (size + cum->nbytes <= regpass * UNITS_PER_WORD 1154 && cum->nbytes / UNITS_PER_WORD <= 3) 1155 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); 1156 } 1157 1158 return result; 1159 } 1160 1161 /* Update the data in CUM to advance over an argument 1162 of mode MODE and data type TYPE. 1163 (TYPE is null for libcalls where that information may not be available.) */ 1164 1165 static void 1166 h8300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, 1167 const_tree type, bool named ATTRIBUTE_UNUSED) 1168 { 1169 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1170 1171 cum->nbytes += (mode != BLKmode 1172 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD 1173 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD); 1174 } 1175 1176 1177 /* Implements TARGET_REGISTER_MOVE_COST. 1178 1179 Any SI register-to-register move may need to be reloaded, 1180 so inmplement h8300_register_move_cost to return > 2 so that reload never 1181 shortcuts. */ 1182 1183 static int 1184 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 1185 reg_class_t from, reg_class_t to) 1186 { 1187 if (from == MAC_REGS || to == MAC_REG) 1188 return 6; 1189 else 1190 return 3; 1191 } 1192 1193 /* Compute the cost of an and insn. */ 1194 1195 static int 1196 h8300_and_costs (rtx x) 1197 { 1198 rtx operands[4]; 1199 1200 if (GET_MODE (x) == QImode) 1201 return 1; 1202 1203 if (GET_MODE (x) != HImode 1204 && GET_MODE (x) != SImode) 1205 return 100; 1206 1207 operands[0] = NULL; 1208 operands[1] = XEXP (x, 0); 1209 operands[2] = XEXP (x, 1); 1210 operands[3] = x; 1211 return compute_logical_op_length (GET_MODE (x), operands) / 2; 1212 } 1213 1214 /* Compute the cost of a shift insn. */ 1215 1216 static int 1217 h8300_shift_costs (rtx x) 1218 { 1219 rtx operands[4]; 1220 1221 if (GET_MODE (x) != QImode 1222 && GET_MODE (x) != HImode 1223 && GET_MODE (x) != SImode) 1224 return 100; 1225 1226 operands[0] = NULL; 1227 operands[1] = NULL; 1228 operands[2] = XEXP (x, 1); 1229 operands[3] = x; 1230 return compute_a_shift_length (NULL, operands) / 2; 1231 } 1232 1233 /* Worker function for TARGET_RTX_COSTS. */ 1234 1235 static bool 1236 h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, 1237 int opno ATTRIBUTE_UNUSED, int *total, bool speed) 1238 { 1239 int code = GET_CODE (x); 1240 1241 if (TARGET_H8300SX && outer_code == MEM) 1242 { 1243 /* Estimate the number of execution states needed to calculate 1244 the address. */ 1245 if (register_operand (x, VOIDmode) 1246 || GET_CODE (x) == POST_INC 1247 || GET_CODE (x) == POST_DEC 1248 || CONSTANT_P (x)) 1249 *total = 0; 1250 else 1251 *total = COSTS_N_INSNS (1); 1252 return true; 1253 } 1254 1255 switch (code) 1256 { 1257 case CONST_INT: 1258 { 1259 HOST_WIDE_INT n = INTVAL (x); 1260 1261 if (TARGET_H8300SX) 1262 { 1263 /* Constant operands need the same number of processor 1264 states as register operands. Although we could try to 1265 use a size-based cost for !speed, the lack of 1266 of a mode makes the results very unpredictable. */ 1267 *total = 0; 1268 return true; 1269 } 1270 if (n >= -4 && n <= 4) 1271 { 1272 switch ((int) n) 1273 { 1274 case 0: 1275 *total = 0; 1276 return true; 1277 case 1: 1278 case 2: 1279 case -1: 1280 case -2: 1281 *total = 0 + (outer_code == SET); 1282 return true; 1283 case 4: 1284 case -4: 1285 if (TARGET_H8300H || TARGET_H8300S) 1286 *total = 0 + (outer_code == SET); 1287 else 1288 *total = 1; 1289 return true; 1290 } 1291 } 1292 *total = 1; 1293 return true; 1294 } 1295 1296 case CONST: 1297 case LABEL_REF: 1298 case SYMBOL_REF: 1299 if (TARGET_H8300SX) 1300 { 1301 /* See comment for CONST_INT. */ 1302 *total = 0; 1303 return true; 1304 } 1305 *total = 3; 1306 return true; 1307 1308 case CONST_DOUBLE: 1309 *total = 20; 1310 return true; 1311 1312 case COMPARE: 1313 if (XEXP (x, 1) == const0_rtx) 1314 *total = 0; 1315 return false; 1316 1317 case AND: 1318 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode) 1319 || !h8300_src_operand (XEXP (x, 1), VOIDmode)) 1320 return false; 1321 *total = COSTS_N_INSNS (h8300_and_costs (x)); 1322 return true; 1323 1324 /* We say that MOD and DIV are so expensive because otherwise we'll 1325 generate some really horrible code for division of a power of two. */ 1326 case MOD: 1327 case DIV: 1328 case UMOD: 1329 case UDIV: 1330 if (TARGET_H8300SX) 1331 switch (GET_MODE (x)) 1332 { 1333 case E_QImode: 1334 case E_HImode: 1335 *total = COSTS_N_INSNS (!speed ? 4 : 10); 1336 return false; 1337 1338 case E_SImode: 1339 *total = COSTS_N_INSNS (!speed ? 4 : 18); 1340 return false; 1341 1342 default: 1343 break; 1344 } 1345 *total = COSTS_N_INSNS (12); 1346 return true; 1347 1348 case MULT: 1349 if (TARGET_H8300SX) 1350 switch (GET_MODE (x)) 1351 { 1352 case E_QImode: 1353 case E_HImode: 1354 *total = COSTS_N_INSNS (2); 1355 return false; 1356 1357 case E_SImode: 1358 *total = COSTS_N_INSNS (5); 1359 return false; 1360 1361 default: 1362 break; 1363 } 1364 *total = COSTS_N_INSNS (4); 1365 return true; 1366 1367 case ASHIFT: 1368 case ASHIFTRT: 1369 case LSHIFTRT: 1370 if (h8sx_binary_shift_operator (x, VOIDmode)) 1371 { 1372 *total = COSTS_N_INSNS (2); 1373 return false; 1374 } 1375 else if (h8sx_unary_shift_operator (x, VOIDmode)) 1376 { 1377 *total = COSTS_N_INSNS (1); 1378 return false; 1379 } 1380 *total = COSTS_N_INSNS (h8300_shift_costs (x)); 1381 return true; 1382 1383 case ROTATE: 1384 case ROTATERT: 1385 if (GET_MODE (x) == HImode) 1386 *total = 2; 1387 else 1388 *total = 8; 1389 return true; 1390 1391 default: 1392 *total = COSTS_N_INSNS (1); 1393 return false; 1394 } 1395 } 1396 1397 /* Documentation for the machine specific operand escapes: 1398 1399 'E' like s but negative. 1400 'F' like t but negative. 1401 'G' constant just the negative 1402 'R' print operand as a byte:8 address if appropriate, else fall back to 1403 'X' handling. 1404 'S' print operand as a long word 1405 'T' print operand as a word 1406 'V' find the set bit, and print its number. 1407 'W' find the clear bit, and print its number. 1408 'X' print operand as a byte 1409 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. 1410 If this operand isn't a register, fall back to 'R' handling. 1411 'Z' print int & 7. 1412 'c' print the opcode corresponding to rtl 1413 'e' first word of 32-bit value - if reg, then least reg. if mem 1414 then least. if const then most sig word 1415 'f' second word of 32-bit value - if reg, then biggest reg. if mem 1416 then +2. if const then least sig word 1417 'j' print operand as condition code. 1418 'k' print operand as reverse condition code. 1419 'm' convert an integer operand to a size suffix (.b, .w or .l) 1420 'o' print an integer without a leading '#' 1421 's' print as low byte of 16-bit value 1422 't' print as high byte of 16-bit value 1423 'w' print as low byte of 32-bit value 1424 'x' print as 2nd byte of 32-bit value 1425 'y' print as 3rd byte of 32-bit value 1426 'z' print as msb of 32-bit value 1427 */ 1428 1429 /* Return assembly language string which identifies a comparison type. */ 1430 1431 static const char * 1432 cond_string (enum rtx_code code) 1433 { 1434 switch (code) 1435 { 1436 case NE: 1437 return "ne"; 1438 case EQ: 1439 return "eq"; 1440 case GE: 1441 return "ge"; 1442 case GT: 1443 return "gt"; 1444 case LE: 1445 return "le"; 1446 case LT: 1447 return "lt"; 1448 case GEU: 1449 return "hs"; 1450 case GTU: 1451 return "hi"; 1452 case LEU: 1453 return "ls"; 1454 case LTU: 1455 return "lo"; 1456 default: 1457 gcc_unreachable (); 1458 } 1459 } 1460 1461 /* Print operand X using operand code CODE to assembly language output file 1462 FILE. */ 1463 1464 static void 1465 h8300_print_operand (FILE *file, rtx x, int code) 1466 { 1467 /* This is used for communication between codes V,W,Z and Y. */ 1468 static int bitint; 1469 1470 switch (code) 1471 { 1472 case 'C': 1473 if (h8300_constant_length (x) == 2) 1474 fprintf (file, ":16"); 1475 else 1476 fprintf (file, ":32"); 1477 return; 1478 case 'E': 1479 switch (GET_CODE (x)) 1480 { 1481 case REG: 1482 fprintf (file, "%sl", names_big[REGNO (x)]); 1483 break; 1484 case CONST_INT: 1485 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff); 1486 break; 1487 default: 1488 gcc_unreachable (); 1489 } 1490 break; 1491 case 'F': 1492 switch (GET_CODE (x)) 1493 { 1494 case REG: 1495 fprintf (file, "%sh", names_big[REGNO (x)]); 1496 break; 1497 case CONST_INT: 1498 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8); 1499 break; 1500 default: 1501 gcc_unreachable (); 1502 } 1503 break; 1504 case 'G': 1505 gcc_assert (GET_CODE (x) == CONST_INT); 1506 fprintf (file, "#%ld", 0xff & (-INTVAL (x))); 1507 break; 1508 case 'S': 1509 if (GET_CODE (x) == REG) 1510 fprintf (file, "%s", names_extended[REGNO (x)]); 1511 else 1512 goto def; 1513 break; 1514 case 'T': 1515 if (GET_CODE (x) == REG) 1516 fprintf (file, "%s", names_big[REGNO (x)]); 1517 else 1518 goto def; 1519 break; 1520 case 'V': 1521 bitint = (INTVAL (x) & 0xffff); 1522 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1) 1523 bitint = exact_log2 (bitint & 0xff); 1524 else 1525 bitint = exact_log2 ((bitint >> 8) & 0xff); 1526 gcc_assert (bitint >= 0); 1527 fprintf (file, "#%d", bitint); 1528 break; 1529 case 'W': 1530 bitint = ((~INTVAL (x)) & 0xffff); 1531 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 ) 1532 bitint = exact_log2 (bitint & 0xff); 1533 else 1534 bitint = (exact_log2 ((bitint >> 8) & 0xff)); 1535 gcc_assert (bitint >= 0); 1536 fprintf (file, "#%d", bitint); 1537 break; 1538 case 'R': 1539 case 'X': 1540 if (GET_CODE (x) == REG) 1541 fprintf (file, "%s", byte_reg (x, 0)); 1542 else 1543 goto def; 1544 break; 1545 case 'Y': 1546 gcc_assert (bitint >= 0); 1547 if (GET_CODE (x) == REG) 1548 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); 1549 else 1550 h8300_print_operand (file, x, 'R'); 1551 bitint = -1; 1552 break; 1553 case 'Z': 1554 bitint = INTVAL (x); 1555 fprintf (file, "#%d", bitint & 7); 1556 break; 1557 case 'c': 1558 switch (GET_CODE (x)) 1559 { 1560 case IOR: 1561 fprintf (file, "or"); 1562 break; 1563 case XOR: 1564 fprintf (file, "xor"); 1565 break; 1566 case AND: 1567 fprintf (file, "and"); 1568 break; 1569 default: 1570 break; 1571 } 1572 break; 1573 case 'e': 1574 switch (GET_CODE (x)) 1575 { 1576 case REG: 1577 if (TARGET_H8300) 1578 fprintf (file, "%s", names_big[REGNO (x)]); 1579 else 1580 fprintf (file, "%s", names_upper_extended[REGNO (x)]); 1581 break; 1582 case MEM: 1583 h8300_print_operand (file, x, 0); 1584 break; 1585 case CONST_INT: 1586 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff)); 1587 break; 1588 case CONST_DOUBLE: 1589 { 1590 long val; 1591 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); 1592 fprintf (file, "#%ld", ((val >> 16) & 0xffff)); 1593 break; 1594 } 1595 default: 1596 gcc_unreachable (); 1597 break; 1598 } 1599 break; 1600 case 'f': 1601 switch (GET_CODE (x)) 1602 { 1603 case REG: 1604 if (TARGET_H8300) 1605 fprintf (file, "%s", names_big[REGNO (x) + 1]); 1606 else 1607 fprintf (file, "%s", names_big[REGNO (x)]); 1608 break; 1609 case MEM: 1610 x = adjust_address (x, HImode, 2); 1611 h8300_print_operand (file, x, 0); 1612 break; 1613 case CONST_INT: 1614 fprintf (file, "#%ld", INTVAL (x) & 0xffff); 1615 break; 1616 case CONST_DOUBLE: 1617 { 1618 long val; 1619 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); 1620 fprintf (file, "#%ld", (val & 0xffff)); 1621 break; 1622 } 1623 default: 1624 gcc_unreachable (); 1625 } 1626 break; 1627 case 'j': 1628 fputs (cond_string (GET_CODE (x)), file); 1629 break; 1630 case 'k': 1631 fputs (cond_string (reverse_condition (GET_CODE (x))), file); 1632 break; 1633 case 'm': 1634 gcc_assert (GET_CODE (x) == CONST_INT); 1635 switch (INTVAL (x)) 1636 { 1637 case 1: 1638 fputs (".b", file); 1639 break; 1640 1641 case 2: 1642 fputs (".w", file); 1643 break; 1644 1645 case 4: 1646 fputs (".l", file); 1647 break; 1648 1649 default: 1650 gcc_unreachable (); 1651 } 1652 break; 1653 case 'o': 1654 h8300_print_operand_address (file, VOIDmode, x); 1655 break; 1656 case 's': 1657 if (GET_CODE (x) == CONST_INT) 1658 fprintf (file, "#%ld", (INTVAL (x)) & 0xff); 1659 else 1660 fprintf (file, "%s", byte_reg (x, 0)); 1661 break; 1662 case 't': 1663 if (GET_CODE (x) == CONST_INT) 1664 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1665 else 1666 fprintf (file, "%s", byte_reg (x, 1)); 1667 break; 1668 case 'w': 1669 if (GET_CODE (x) == CONST_INT) 1670 fprintf (file, "#%ld", INTVAL (x) & 0xff); 1671 else 1672 fprintf (file, "%s", 1673 byte_reg (x, TARGET_H8300 ? 2 : 0)); 1674 break; 1675 case 'x': 1676 if (GET_CODE (x) == CONST_INT) 1677 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1678 else 1679 fprintf (file, "%s", 1680 byte_reg (x, TARGET_H8300 ? 3 : 1)); 1681 break; 1682 case 'y': 1683 if (GET_CODE (x) == CONST_INT) 1684 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff); 1685 else 1686 fprintf (file, "%s", byte_reg (x, 0)); 1687 break; 1688 case 'z': 1689 if (GET_CODE (x) == CONST_INT) 1690 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff); 1691 else 1692 fprintf (file, "%s", byte_reg (x, 1)); 1693 break; 1694 1695 default: 1696 def: 1697 switch (GET_CODE (x)) 1698 { 1699 case REG: 1700 switch (GET_MODE (x)) 1701 { 1702 case E_QImode: 1703 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */ 1704 fprintf (file, "%s", byte_reg (x, 0)); 1705 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */ 1706 fprintf (file, "%s", names_big[REGNO (x)]); 1707 #endif 1708 break; 1709 case E_HImode: 1710 fprintf (file, "%s", names_big[REGNO (x)]); 1711 break; 1712 case E_SImode: 1713 case E_SFmode: 1714 fprintf (file, "%s", names_extended[REGNO (x)]); 1715 break; 1716 default: 1717 gcc_unreachable (); 1718 } 1719 break; 1720 1721 case MEM: 1722 { 1723 rtx addr = XEXP (x, 0); 1724 1725 fprintf (file, "@"); 1726 output_address (GET_MODE (x), addr); 1727 1728 /* Add a length suffix to constant addresses. Although this 1729 is often unnecessary, it helps to avoid ambiguity in the 1730 syntax of mova. If we wrote an insn like: 1731 1732 mova/w.l @(1,@foo.b),er0 1733 1734 then .b would be considered part of the symbol name. 1735 Adding a length after foo will avoid this. */ 1736 if (CONSTANT_P (addr)) 1737 switch (code) 1738 { 1739 case 'R': 1740 /* Used for mov.b and bit operations. */ 1741 if (h8300_eightbit_constant_address_p (addr)) 1742 { 1743 fprintf (file, ":8"); 1744 break; 1745 } 1746 1747 /* FALLTHRU */ 1748 1749 /* We should not get here if we are processing bit 1750 operations on H8/300 or H8/300H because 'U' 1751 constraint does not allow bit operations on the 1752 tiny area on these machines. */ 1753 1754 case 'X': 1755 case 'T': 1756 case 'S': 1757 if (h8300_constant_length (addr) == 2) 1758 fprintf (file, ":16"); 1759 else 1760 fprintf (file, ":32"); 1761 break; 1762 default: 1763 break; 1764 } 1765 } 1766 break; 1767 1768 case CONST_INT: 1769 case SYMBOL_REF: 1770 case CONST: 1771 case LABEL_REF: 1772 fprintf (file, "#"); 1773 h8300_print_operand_address (file, VOIDmode, x); 1774 break; 1775 case CONST_DOUBLE: 1776 { 1777 long val; 1778 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); 1779 fprintf (file, "#%ld", val); 1780 break; 1781 } 1782 default: 1783 break; 1784 } 1785 } 1786 } 1787 1788 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ 1789 1790 static bool 1791 h8300_print_operand_punct_valid_p (unsigned char code) 1792 { 1793 return (code == '#'); 1794 } 1795 1796 /* Output assembly language output for the address ADDR to FILE. */ 1797 1798 static void 1799 h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr) 1800 { 1801 rtx index; 1802 int size; 1803 1804 switch (GET_CODE (addr)) 1805 { 1806 case REG: 1807 fprintf (file, "%s", h8_reg_names[REGNO (addr)]); 1808 break; 1809 1810 case PRE_DEC: 1811 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1812 break; 1813 1814 case POST_INC: 1815 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); 1816 break; 1817 1818 case PRE_INC: 1819 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1820 break; 1821 1822 case POST_DEC: 1823 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]); 1824 break; 1825 1826 case PLUS: 1827 fprintf (file, "("); 1828 1829 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size); 1830 if (GET_CODE (index) == REG) 1831 { 1832 /* reg,foo */ 1833 h8300_print_operand_address (file, mode, XEXP (addr, 1)); 1834 fprintf (file, ","); 1835 switch (size) 1836 { 1837 case 0: 1838 h8300_print_operand_address (file, mode, index); 1839 break; 1840 1841 case 1: 1842 h8300_print_operand (file, index, 'X'); 1843 fputs (".b", file); 1844 break; 1845 1846 case 2: 1847 h8300_print_operand (file, index, 'T'); 1848 fputs (".w", file); 1849 break; 1850 1851 case 4: 1852 h8300_print_operand (file, index, 'S'); 1853 fputs (".l", file); 1854 break; 1855 } 1856 /* h8300_print_operand_address (file, XEXP (addr, 0)); */ 1857 } 1858 else 1859 { 1860 /* foo+k */ 1861 h8300_print_operand_address (file, mode, XEXP (addr, 0)); 1862 fprintf (file, "+"); 1863 h8300_print_operand_address (file, mode, XEXP (addr, 1)); 1864 } 1865 fprintf (file, ")"); 1866 break; 1867 1868 case CONST_INT: 1869 { 1870 /* Since the H8/300 only has 16-bit pointers, negative values are also 1871 those >= 32768. This happens for example with pointer minus a 1872 constant. We don't want to turn (char *p - 2) into 1873 (char *p + 65534) because loop unrolling can build upon this 1874 (IE: char *p + 131068). */ 1875 int n = INTVAL (addr); 1876 if (TARGET_H8300) 1877 n = (int) (short) n; 1878 fprintf (file, "%d", n); 1879 break; 1880 } 1881 1882 default: 1883 output_addr_const (file, addr); 1884 break; 1885 } 1886 } 1887 1888 /* Output all insn addresses and their sizes into the assembly language 1889 output file. This is helpful for debugging whether the length attributes 1890 in the md file are correct. This is not meant to be a user selectable 1891 option. */ 1892 1893 void 1894 final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED, 1895 int num_operands ATTRIBUTE_UNUSED) 1896 { 1897 /* This holds the last insn address. */ 1898 static int last_insn_address = 0; 1899 1900 const int uid = INSN_UID (insn); 1901 1902 if (TARGET_ADDRESSES) 1903 { 1904 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid), 1905 INSN_ADDRESSES (uid) - last_insn_address); 1906 last_insn_address = INSN_ADDRESSES (uid); 1907 } 1908 } 1909 1910 /* Prepare for an SI sized move. */ 1911 1912 int 1913 h8300_expand_movsi (rtx operands[]) 1914 { 1915 rtx src = operands[1]; 1916 rtx dst = operands[0]; 1917 if (!reload_in_progress && !reload_completed) 1918 { 1919 if (!register_operand (dst, GET_MODE (dst))) 1920 { 1921 rtx tmp = gen_reg_rtx (GET_MODE (dst)); 1922 emit_move_insn (tmp, src); 1923 operands[1] = tmp; 1924 } 1925 } 1926 return 0; 1927 } 1928 1929 /* Given FROM and TO register numbers, say whether this elimination is allowed. 1930 Frame pointer elimination is automatically handled. 1931 1932 For the h8300, if frame pointer elimination is being done, we would like to 1933 convert ap and rp into sp, not fp. 1934 1935 All other eliminations are valid. */ 1936 1937 static bool 1938 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 1939 { 1940 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); 1941 } 1942 1943 /* Conditionally modify register usage based on target flags. */ 1944 1945 static void 1946 h8300_conditional_register_usage (void) 1947 { 1948 if (!TARGET_MAC) 1949 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1; 1950 } 1951 1952 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). 1953 Define the offset between two registers, one to be eliminated, and 1954 the other its replacement, at the start of a routine. */ 1955 1956 int 1957 h8300_initial_elimination_offset (int from, int to) 1958 { 1959 /* The number of bytes that the return address takes on the stack. */ 1960 int pc_size = POINTER_SIZE / BITS_PER_UNIT; 1961 1962 /* The number of bytes that the saved frame pointer takes on the stack. */ 1963 int fp_size = frame_pointer_needed * UNITS_PER_WORD; 1964 1965 /* The number of bytes that the saved registers, excluding the frame 1966 pointer, take on the stack. */ 1967 int saved_regs_size = 0; 1968 1969 /* The number of bytes that the locals takes on the stack. */ 1970 int frame_size = round_frame_size (get_frame_size ()); 1971 1972 int regno; 1973 1974 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 1975 if (WORD_REG_USED (regno)) 1976 saved_regs_size += UNITS_PER_WORD; 1977 1978 /* Adjust saved_regs_size because the above loop took the frame 1979 pointer int account. */ 1980 saved_regs_size -= fp_size; 1981 1982 switch (to) 1983 { 1984 case HARD_FRAME_POINTER_REGNUM: 1985 switch (from) 1986 { 1987 case ARG_POINTER_REGNUM: 1988 return pc_size + fp_size; 1989 case RETURN_ADDRESS_POINTER_REGNUM: 1990 return fp_size; 1991 case FRAME_POINTER_REGNUM: 1992 return -saved_regs_size; 1993 default: 1994 gcc_unreachable (); 1995 } 1996 break; 1997 case STACK_POINTER_REGNUM: 1998 switch (from) 1999 { 2000 case ARG_POINTER_REGNUM: 2001 return pc_size + saved_regs_size + frame_size; 2002 case RETURN_ADDRESS_POINTER_REGNUM: 2003 return saved_regs_size + frame_size; 2004 case FRAME_POINTER_REGNUM: 2005 return frame_size; 2006 default: 2007 gcc_unreachable (); 2008 } 2009 break; 2010 default: 2011 gcc_unreachable (); 2012 } 2013 gcc_unreachable (); 2014 } 2015 2016 /* Worker function for RETURN_ADDR_RTX. */ 2017 2018 rtx 2019 h8300_return_addr_rtx (int count, rtx frame) 2020 { 2021 rtx ret; 2022 2023 if (count == 0) 2024 ret = gen_rtx_MEM (Pmode, 2025 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)); 2026 else if (flag_omit_frame_pointer) 2027 return (rtx) 0; 2028 else 2029 ret = gen_rtx_MEM (Pmode, 2030 memory_address (Pmode, 2031 plus_constant (Pmode, frame, 2032 UNITS_PER_WORD))); 2033 set_mem_alias_set (ret, get_frame_alias_set ()); 2034 return ret; 2035 } 2036 2037 /* Update the condition code from the insn. */ 2038 2039 void 2040 notice_update_cc (rtx body, rtx_insn *insn) 2041 { 2042 rtx set; 2043 2044 switch (get_attr_cc (insn)) 2045 { 2046 case CC_NONE: 2047 /* Insn does not affect CC at all. */ 2048 break; 2049 2050 case CC_NONE_0HIT: 2051 /* Insn does not change CC, but the 0'th operand has been changed. */ 2052 if (cc_status.value1 != 0 2053 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) 2054 cc_status.value1 = 0; 2055 if (cc_status.value2 != 0 2056 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2)) 2057 cc_status.value2 = 0; 2058 break; 2059 2060 case CC_SET_ZN: 2061 /* Insn sets the Z,N flags of CC to recog_data.operand[0]. 2062 The V flag is unusable. The C flag may or may not be known but 2063 that's ok because alter_cond will change tests to use EQ/NE. */ 2064 CC_STATUS_INIT; 2065 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; 2066 set = single_set (insn); 2067 cc_status.value1 = SET_SRC (set); 2068 if (SET_DEST (set) != cc0_rtx) 2069 cc_status.value2 = SET_DEST (set); 2070 break; 2071 2072 case CC_SET_ZNV: 2073 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. 2074 The C flag may or may not be known but that's ok because 2075 alter_cond will change tests to use EQ/NE. */ 2076 CC_STATUS_INIT; 2077 cc_status.flags |= CC_NO_CARRY; 2078 set = single_set (insn); 2079 cc_status.value1 = SET_SRC (set); 2080 if (SET_DEST (set) != cc0_rtx) 2081 { 2082 /* If the destination is STRICT_LOW_PART, strip off 2083 STRICT_LOW_PART. */ 2084 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) 2085 cc_status.value2 = XEXP (SET_DEST (set), 0); 2086 else 2087 cc_status.value2 = SET_DEST (set); 2088 } 2089 break; 2090 2091 case CC_COMPARE: 2092 /* The insn is a compare instruction. */ 2093 CC_STATUS_INIT; 2094 cc_status.value1 = SET_SRC (body); 2095 break; 2096 2097 case CC_CLOBBER: 2098 /* Insn doesn't leave CC in a usable state. */ 2099 CC_STATUS_INIT; 2100 break; 2101 } 2102 } 2103 2104 /* Given that X occurs in an address of the form (plus X constant), 2105 return the part of X that is expected to be a register. There are 2106 four kinds of addressing mode to recognize: 2107 2108 @(dd,Rn) 2109 @(dd,RnL.b) 2110 @(dd,Rn.w) 2111 @(dd,ERn.l) 2112 2113 If SIZE is nonnull, and the address is one of the last three forms, 2114 set *SIZE to the index multiplication factor. Set it to 0 for 2115 plain @(dd,Rn) addresses. 2116 2117 MODE is the mode of the value being accessed. It can be VOIDmode 2118 if the address is known to be valid, but its mode is unknown. */ 2119 2120 static rtx 2121 h8300_get_index (rtx x, machine_mode mode, int *size) 2122 { 2123 int dummy, factor; 2124 2125 if (size == 0) 2126 size = &dummy; 2127 2128 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode)); 2129 if (TARGET_H8300SX 2130 && factor <= 4 2131 && (mode == VOIDmode 2132 || GET_MODE_CLASS (mode) == MODE_INT 2133 || GET_MODE_CLASS (mode) == MODE_FLOAT)) 2134 { 2135 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND) 2136 { 2137 /* When accessing byte-sized values, the index can be 2138 a zero-extended QImode or HImode register. */ 2139 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0))); 2140 return XEXP (x, 0); 2141 } 2142 else 2143 { 2144 /* We're looking for addresses of the form: 2145 2146 (mult X I) 2147 or (mult (zero_extend X) I) 2148 2149 where I is the size of the operand being accessed. 2150 The canonical form of the second expression is: 2151 2152 (and (mult (subreg X) I) J) 2153 2154 where J == GET_MODE_MASK (GET_MODE (X)) * I. */ 2155 rtx index; 2156 2157 if (GET_CODE (x) == AND 2158 && GET_CODE (XEXP (x, 1)) == CONST_INT 2159 && (factor == 0 2160 || INTVAL (XEXP (x, 1)) == 0xff * factor 2161 || INTVAL (XEXP (x, 1)) == 0xffff * factor)) 2162 { 2163 index = XEXP (x, 0); 2164 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1); 2165 } 2166 else 2167 { 2168 index = x; 2169 *size = 4; 2170 } 2171 2172 if (GET_CODE (index) == MULT 2173 && GET_CODE (XEXP (index, 1)) == CONST_INT 2174 && (factor == 0 || factor == INTVAL (XEXP (index, 1)))) 2175 return XEXP (index, 0); 2176 } 2177 } 2178 *size = 0; 2179 return x; 2180 } 2181 2182 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. 2183 2184 On the H8/300, the predecrement and postincrement address depend thus 2185 (the amount of decrement or increment being the length of the operand). */ 2186 2187 static bool 2188 h8300_mode_dependent_address_p (const_rtx addr, 2189 addr_space_t as ATTRIBUTE_UNUSED) 2190 { 2191 if (GET_CODE (addr) == PLUS 2192 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0)) 2193 return true; 2194 2195 return false; 2196 } 2197 2198 static const h8300_length_table addb_length_table = 2199 { 2200 /* #xx Rs @aa @Rs @xx */ 2201 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */ 2202 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */ 2203 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */ 2204 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */ 2205 }; 2206 2207 static const h8300_length_table addw_length_table = 2208 { 2209 /* #xx Rs @aa @Rs @xx */ 2210 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */ 2211 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */ 2212 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */ 2213 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */ 2214 }; 2215 2216 static const h8300_length_table addl_length_table = 2217 { 2218 /* #xx Rs @aa @Rs @xx */ 2219 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */ 2220 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */ 2221 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */ 2222 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */ 2223 }; 2224 2225 #define logicb_length_table addb_length_table 2226 #define logicw_length_table addw_length_table 2227 2228 static const h8300_length_table logicl_length_table = 2229 { 2230 /* #xx Rs @aa @Rs @xx */ 2231 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */ 2232 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */ 2233 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */ 2234 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */ 2235 }; 2236 2237 static const h8300_length_table movb_length_table = 2238 { 2239 /* #xx Rs @aa @Rs @xx */ 2240 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */ 2241 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */ 2242 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */ 2243 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */ 2244 }; 2245 2246 #define movw_length_table movb_length_table 2247 2248 static const h8300_length_table movl_length_table = 2249 { 2250 /* #xx Rs @aa @Rs @xx */ 2251 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */ 2252 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */ 2253 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */ 2254 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */ 2255 }; 2256 2257 /* Return the size of the given address or displacement constant. */ 2258 2259 static unsigned int 2260 h8300_constant_length (rtx constant) 2261 { 2262 /* Check for (@d:16,Reg). */ 2263 if (GET_CODE (constant) == CONST_INT 2264 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff)) 2265 return 2; 2266 2267 /* Check for (@d:16,Reg) in cases where the displacement is 2268 an absolute address. */ 2269 if (Pmode == HImode || h8300_tiny_constant_address_p (constant)) 2270 return 2; 2271 2272 return 4; 2273 } 2274 2275 /* Return the size of a displacement field in address ADDR, which should 2276 have the form (plus X constant). SIZE is the number of bytes being 2277 accessed. */ 2278 2279 static unsigned int 2280 h8300_displacement_length (rtx addr, int size) 2281 { 2282 rtx offset; 2283 2284 offset = XEXP (addr, 1); 2285 2286 /* Check for @(d:2,Reg). */ 2287 if (register_operand (XEXP (addr, 0), VOIDmode) 2288 && GET_CODE (offset) == CONST_INT 2289 && (INTVAL (offset) == size 2290 || INTVAL (offset) == size * 2 2291 || INTVAL (offset) == size * 3)) 2292 return 0; 2293 2294 return h8300_constant_length (offset); 2295 } 2296 2297 /* Store the class of operand OP in *OPCLASS and return the length of any 2298 extra operand fields. SIZE is the number of bytes in OP. OPCLASS 2299 can be null if only the length is needed. */ 2300 2301 static unsigned int 2302 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass) 2303 { 2304 enum h8300_operand_class dummy; 2305 2306 if (opclass == 0) 2307 opclass = &dummy; 2308 2309 if (CONSTANT_P (op)) 2310 { 2311 *opclass = H8OP_IMMEDIATE; 2312 2313 /* Byte-sized immediates are stored in the opcode fields. */ 2314 if (size == 1) 2315 return 0; 2316 2317 /* If this is a 32-bit instruction, see whether the constant 2318 will fit into a 16-bit immediate field. */ 2319 if (TARGET_H8300SX 2320 && size == 4 2321 && GET_CODE (op) == CONST_INT 2322 && IN_RANGE (INTVAL (op), 0, 0xffff)) 2323 return 2; 2324 2325 return size; 2326 } 2327 else if (GET_CODE (op) == MEM) 2328 { 2329 op = XEXP (op, 0); 2330 if (CONSTANT_P (op)) 2331 { 2332 *opclass = H8OP_MEM_ABSOLUTE; 2333 return h8300_constant_length (op); 2334 } 2335 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1))) 2336 { 2337 *opclass = H8OP_MEM_COMPLEX; 2338 return h8300_displacement_length (op, size); 2339 } 2340 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) 2341 { 2342 *opclass = H8OP_MEM_COMPLEX; 2343 return 0; 2344 } 2345 else if (register_operand (op, VOIDmode)) 2346 { 2347 *opclass = H8OP_MEM_BASE; 2348 return 0; 2349 } 2350 } 2351 gcc_assert (register_operand (op, VOIDmode)); 2352 *opclass = H8OP_REGISTER; 2353 return 0; 2354 } 2355 2356 /* Return the length of the instruction described by TABLE given that 2357 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand 2358 and OP2 must be an h8300_src_operand. */ 2359 2360 static unsigned int 2361 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table) 2362 { 2363 enum h8300_operand_class op1_class, op2_class; 2364 unsigned int size, immediate_length; 2365 2366 size = GET_MODE_SIZE (GET_MODE (op1)); 2367 immediate_length = (h8300_classify_operand (op1, size, &op1_class) 2368 + h8300_classify_operand (op2, size, &op2_class)); 2369 return immediate_length + (*table)[op1_class - 1][op2_class]; 2370 } 2371 2372 /* Return the length of a unary instruction such as neg or not given that 2373 its operand is OP. */ 2374 2375 unsigned int 2376 h8300_unary_length (rtx op) 2377 { 2378 enum h8300_operand_class opclass; 2379 unsigned int size, operand_length; 2380 2381 size = GET_MODE_SIZE (GET_MODE (op)); 2382 operand_length = h8300_classify_operand (op, size, &opclass); 2383 switch (opclass) 2384 { 2385 case H8OP_REGISTER: 2386 return 2; 2387 2388 case H8OP_MEM_BASE: 2389 return (size == 4 ? 6 : 4); 2390 2391 case H8OP_MEM_ABSOLUTE: 2392 return operand_length + (size == 4 ? 6 : 4); 2393 2394 case H8OP_MEM_COMPLEX: 2395 return operand_length + 6; 2396 2397 default: 2398 gcc_unreachable (); 2399 } 2400 } 2401 2402 /* Likewise short immediate instructions such as add.w #xx:3,OP. */ 2403 2404 static unsigned int 2405 h8300_short_immediate_length (rtx op) 2406 { 2407 enum h8300_operand_class opclass; 2408 unsigned int size, operand_length; 2409 2410 size = GET_MODE_SIZE (GET_MODE (op)); 2411 operand_length = h8300_classify_operand (op, size, &opclass); 2412 2413 switch (opclass) 2414 { 2415 case H8OP_REGISTER: 2416 return 2; 2417 2418 case H8OP_MEM_BASE: 2419 case H8OP_MEM_ABSOLUTE: 2420 case H8OP_MEM_COMPLEX: 2421 return 4 + operand_length; 2422 2423 default: 2424 gcc_unreachable (); 2425 } 2426 } 2427 2428 /* Likewise bitfield load and store instructions. */ 2429 2430 static unsigned int 2431 h8300_bitfield_length (rtx op, rtx op2) 2432 { 2433 enum h8300_operand_class opclass; 2434 unsigned int size, operand_length; 2435 2436 if (GET_CODE (op) == REG) 2437 op = op2; 2438 gcc_assert (GET_CODE (op) != REG); 2439 2440 size = GET_MODE_SIZE (GET_MODE (op)); 2441 operand_length = h8300_classify_operand (op, size, &opclass); 2442 2443 switch (opclass) 2444 { 2445 case H8OP_MEM_BASE: 2446 case H8OP_MEM_ABSOLUTE: 2447 case H8OP_MEM_COMPLEX: 2448 return 4 + operand_length; 2449 2450 default: 2451 gcc_unreachable (); 2452 } 2453 } 2454 2455 /* Calculate the length of general binary instruction INSN using TABLE. */ 2456 2457 static unsigned int 2458 h8300_binary_length (rtx_insn *insn, const h8300_length_table *table) 2459 { 2460 rtx set; 2461 2462 set = single_set (insn); 2463 gcc_assert (set); 2464 2465 if (BINARY_P (SET_SRC (set))) 2466 return h8300_length_from_table (XEXP (SET_SRC (set), 0), 2467 XEXP (SET_SRC (set), 1), table); 2468 else 2469 { 2470 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY); 2471 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0), 2472 XEXP (XEXP (SET_SRC (set), 1), 1), 2473 table); 2474 } 2475 } 2476 2477 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte 2478 memory reference and either (1) it has the form @(d:16,Rn) or 2479 (2) its address has the code given by INC_CODE. */ 2480 2481 static bool 2482 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code) 2483 { 2484 rtx addr; 2485 unsigned int size; 2486 2487 if (GET_CODE (op) != MEM) 2488 return false; 2489 2490 addr = XEXP (op, 0); 2491 size = GET_MODE_SIZE (GET_MODE (op)); 2492 if (size != 1 && size != 2) 2493 return false; 2494 2495 return (GET_CODE (addr) == inc_code 2496 || (GET_CODE (addr) == PLUS 2497 && GET_CODE (XEXP (addr, 0)) == REG 2498 && h8300_displacement_length (addr, size) == 2)); 2499 } 2500 2501 /* Calculate the length of move instruction INSN using the given length 2502 table. Although the tables are correct for most cases, there is some 2503 irregularity in the length of mov.b and mov.w. The following forms: 2504 2505 mov @ERs+, Rd 2506 mov @(d:16,ERs), Rd 2507 mov Rs, @-ERd 2508 mov Rs, @(d:16,ERd) 2509 2510 are two bytes shorter than most other "mov Rs, @complex" or 2511 "mov @complex,Rd" combinations. */ 2512 2513 static unsigned int 2514 h8300_move_length (rtx *operands, const h8300_length_table *table) 2515 { 2516 unsigned int size; 2517 2518 size = h8300_length_from_table (operands[0], operands[1], table); 2519 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC)) 2520 size -= 2; 2521 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC)) 2522 size -= 2; 2523 return size; 2524 } 2525 2526 /* Return the length of a mova instruction with the given operands. 2527 DEST is the register destination, SRC is the source address and 2528 OFFSET is the 16-bit or 32-bit displacement. */ 2529 2530 static unsigned int 2531 h8300_mova_length (rtx dest, rtx src, rtx offset) 2532 { 2533 unsigned int size; 2534 2535 size = (2 2536 + h8300_constant_length (offset) 2537 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0)); 2538 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest)) 2539 size += 2; 2540 return size; 2541 } 2542 2543 /* Compute the length of INSN based on its length_table attribute. 2544 OPERANDS is the array of its operands. */ 2545 2546 unsigned int 2547 h8300_insn_length_from_table (rtx_insn *insn, rtx * operands) 2548 { 2549 switch (get_attr_length_table (insn)) 2550 { 2551 case LENGTH_TABLE_NONE: 2552 gcc_unreachable (); 2553 2554 case LENGTH_TABLE_ADDB: 2555 return h8300_binary_length (insn, &addb_length_table); 2556 2557 case LENGTH_TABLE_ADDW: 2558 return h8300_binary_length (insn, &addw_length_table); 2559 2560 case LENGTH_TABLE_ADDL: 2561 return h8300_binary_length (insn, &addl_length_table); 2562 2563 case LENGTH_TABLE_LOGICB: 2564 return h8300_binary_length (insn, &logicb_length_table); 2565 2566 case LENGTH_TABLE_MOVB: 2567 return h8300_move_length (operands, &movb_length_table); 2568 2569 case LENGTH_TABLE_MOVW: 2570 return h8300_move_length (operands, &movw_length_table); 2571 2572 case LENGTH_TABLE_MOVL: 2573 return h8300_move_length (operands, &movl_length_table); 2574 2575 case LENGTH_TABLE_MOVA: 2576 return h8300_mova_length (operands[0], operands[1], operands[2]); 2577 2578 case LENGTH_TABLE_MOVA_ZERO: 2579 return h8300_mova_length (operands[0], operands[1], const0_rtx); 2580 2581 case LENGTH_TABLE_UNARY: 2582 return h8300_unary_length (operands[0]); 2583 2584 case LENGTH_TABLE_MOV_IMM4: 2585 return 2 + h8300_classify_operand (operands[0], 0, 0); 2586 2587 case LENGTH_TABLE_SHORT_IMMEDIATE: 2588 return h8300_short_immediate_length (operands[0]); 2589 2590 case LENGTH_TABLE_BITFIELD: 2591 return h8300_bitfield_length (operands[0], operands[1]); 2592 2593 case LENGTH_TABLE_BITBRANCH: 2594 return h8300_bitfield_length (operands[1], operands[2]) - 2; 2595 2596 default: 2597 gcc_unreachable (); 2598 } 2599 } 2600 2601 /* Return true if LHS and RHS are memory references that can be mapped 2602 to the same h8sx assembly operand. LHS appears as the destination of 2603 an instruction and RHS appears as a source. 2604 2605 Three cases are allowed: 2606 2607 - RHS is @+Rn or @-Rn, LHS is @Rn 2608 - RHS is @Rn, LHS is @Rn+ or @Rn- 2609 - RHS and LHS have the same address and neither has side effects. */ 2610 2611 bool 2612 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs) 2613 { 2614 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM) 2615 { 2616 rhs = XEXP (rhs, 0); 2617 lhs = XEXP (lhs, 0); 2618 2619 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC) 2620 return rtx_equal_p (XEXP (rhs, 0), lhs); 2621 2622 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC) 2623 return rtx_equal_p (rhs, XEXP (lhs, 0)); 2624 2625 if (rtx_equal_p (rhs, lhs)) 2626 return true; 2627 } 2628 return false; 2629 } 2630 2631 /* Return true if OPERANDS[1] can be mapped to the same assembly 2632 operand as OPERANDS[0]. */ 2633 2634 bool 2635 h8300_operands_match_p (rtx *operands) 2636 { 2637 if (register_operand (operands[0], VOIDmode) 2638 && register_operand (operands[1], VOIDmode)) 2639 return true; 2640 2641 if (h8sx_mergeable_memrefs_p (operands[0], operands[1])) 2642 return true; 2643 2644 return false; 2645 } 2646 2647 /* Try using movmd to move LENGTH bytes from memory region SRC to memory 2648 region DEST. The two regions do not overlap and have the common 2649 alignment given by ALIGNMENT. Return true on success. 2650 2651 Using movmd for variable-length moves seems to involve some 2652 complex trade-offs. For instance: 2653 2654 - Preparing for a movmd instruction is similar to preparing 2655 for a memcpy. The main difference is that the arguments 2656 are moved into er4, er5 and er6 rather than er0, er1 and er2. 2657 2658 - Since movmd clobbers the frame pointer, we need to save 2659 and restore it somehow when frame_pointer_needed. This can 2660 sometimes make movmd sequences longer than calls to memcpy(). 2661 2662 - The counter register is 16 bits, so the instruction is only 2663 suitable for variable-length moves when sizeof (size_t) == 2. 2664 That's only true in normal mode. 2665 2666 - We will often lack static alignment information. Falling back 2667 on movmd.b would likely be slower than calling memcpy(), at least 2668 for big moves. 2669 2670 This function therefore only uses movmd when the length is a 2671 known constant, and only then if -fomit-frame-pointer is in 2672 effect or if we're not optimizing for size. 2673 2674 At the moment the function uses movmd for all in-range constants, 2675 but it might be better to fall back on memcpy() for large moves 2676 if ALIGNMENT == 1. */ 2677 2678 bool 2679 h8sx_emit_movmd (rtx dest, rtx src, rtx length, 2680 HOST_WIDE_INT alignment) 2681 { 2682 if (!flag_omit_frame_pointer && optimize_size) 2683 return false; 2684 2685 if (GET_CODE (length) == CONST_INT) 2686 { 2687 rtx dest_reg, src_reg, first_dest, first_src; 2688 HOST_WIDE_INT n; 2689 int factor; 2690 2691 /* Use movmd.l if the alignment allows it, otherwise fall back 2692 on movmd.b. */ 2693 factor = (alignment >= 2 ? 4 : 1); 2694 2695 /* Make sure the length is within range. We can handle counter 2696 values up to 65536, although HImode truncation will make 2697 the count appear negative in rtl dumps. */ 2698 n = INTVAL (length); 2699 if (n <= 0 || n / factor > 65536) 2700 return false; 2701 2702 /* Create temporary registers for the source and destination 2703 pointers. Initialize them to the start of each region. */ 2704 dest_reg = copy_addr_to_reg (XEXP (dest, 0)); 2705 src_reg = copy_addr_to_reg (XEXP (src, 0)); 2706 2707 /* Create references to the movmd source and destination blocks. */ 2708 first_dest = replace_equiv_address (dest, dest_reg); 2709 first_src = replace_equiv_address (src, src_reg); 2710 2711 set_mem_size (first_dest, n & -factor); 2712 set_mem_size (first_src, n & -factor); 2713 2714 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode)); 2715 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor))); 2716 2717 if ((n & -factor) != n) 2718 { 2719 /* Move SRC and DEST past the region we just copied. 2720 This is done to update the memory attributes. */ 2721 dest = adjust_address (dest, BLKmode, n & -factor); 2722 src = adjust_address (src, BLKmode, n & -factor); 2723 2724 /* Replace the addresses with the source and destination 2725 registers, which movmd has left with the right values. */ 2726 dest = replace_equiv_address (dest, dest_reg); 2727 src = replace_equiv_address (src, src_reg); 2728 2729 /* Mop up the left-over bytes. */ 2730 if (n & 2) 2731 emit_move_insn (adjust_address (dest, HImode, 0), 2732 adjust_address (src, HImode, 0)); 2733 if (n & 1) 2734 emit_move_insn (adjust_address (dest, QImode, n & 2), 2735 adjust_address (src, QImode, n & 2)); 2736 } 2737 return true; 2738 } 2739 return false; 2740 } 2741 2742 /* Move ADDR into er6 after pushing its old value onto the stack. */ 2743 2744 void 2745 h8300_swap_into_er6 (rtx addr) 2746 { 2747 rtx insn = push (HARD_FRAME_POINTER_REGNUM, false); 2748 if (frame_pointer_needed) 2749 add_reg_note (insn, REG_CFA_DEF_CFA, 2750 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx), 2751 2 * UNITS_PER_WORD)); 2752 else 2753 add_reg_note (insn, REG_CFA_ADJUST_CFA, 2754 gen_rtx_SET (stack_pointer_rtx, 2755 plus_constant (Pmode, stack_pointer_rtx, 4))); 2756 2757 emit_move_insn (hard_frame_pointer_rtx, addr); 2758 if (REGNO (addr) == SP_REG) 2759 emit_move_insn (hard_frame_pointer_rtx, 2760 plus_constant (Pmode, hard_frame_pointer_rtx, 2761 GET_MODE_SIZE (word_mode))); 2762 } 2763 2764 /* Move the current value of er6 into ADDR and pop its old value 2765 from the stack. */ 2766 2767 void 2768 h8300_swap_out_of_er6 (rtx addr) 2769 { 2770 rtx insn; 2771 2772 if (REGNO (addr) != SP_REG) 2773 emit_move_insn (addr, hard_frame_pointer_rtx); 2774 2775 insn = pop (HARD_FRAME_POINTER_REGNUM); 2776 if (frame_pointer_needed) 2777 add_reg_note (insn, REG_CFA_DEF_CFA, 2778 plus_constant (Pmode, hard_frame_pointer_rtx, 2779 2 * UNITS_PER_WORD)); 2780 else 2781 add_reg_note (insn, REG_CFA_ADJUST_CFA, 2782 gen_rtx_SET (stack_pointer_rtx, 2783 plus_constant (Pmode, stack_pointer_rtx, -4))); 2784 } 2785 2786 /* Return the length of mov instruction. */ 2787 2788 unsigned int 2789 compute_mov_length (rtx *operands) 2790 { 2791 /* If the mov instruction involves a memory operand, we compute the 2792 length, assuming the largest addressing mode is used, and then 2793 adjust later in the function. Otherwise, we compute and return 2794 the exact length in one step. */ 2795 machine_mode mode = GET_MODE (operands[0]); 2796 rtx dest = operands[0]; 2797 rtx src = operands[1]; 2798 rtx addr; 2799 2800 if (GET_CODE (src) == MEM) 2801 addr = XEXP (src, 0); 2802 else if (GET_CODE (dest) == MEM) 2803 addr = XEXP (dest, 0); 2804 else 2805 addr = NULL_RTX; 2806 2807 if (TARGET_H8300) 2808 { 2809 unsigned int base_length; 2810 2811 switch (mode) 2812 { 2813 case E_QImode: 2814 if (addr == NULL_RTX) 2815 return 2; 2816 2817 /* The eightbit addressing is available only in QImode, so 2818 go ahead and take care of it. */ 2819 if (h8300_eightbit_constant_address_p (addr)) 2820 return 2; 2821 2822 base_length = 4; 2823 break; 2824 2825 case E_HImode: 2826 if (addr == NULL_RTX) 2827 { 2828 if (REG_P (src)) 2829 return 2; 2830 2831 if (src == const0_rtx) 2832 return 2; 2833 2834 return 4; 2835 } 2836 2837 base_length = 4; 2838 break; 2839 2840 case E_SImode: 2841 if (addr == NULL_RTX) 2842 { 2843 if (REG_P (src)) 2844 return 4; 2845 2846 if (GET_CODE (src) == CONST_INT) 2847 { 2848 if (src == const0_rtx) 2849 return 4; 2850 2851 if ((INTVAL (src) & 0xffff) == 0) 2852 return 6; 2853 2854 if ((INTVAL (src) & 0xffff) == 0) 2855 return 6; 2856 2857 if ((INTVAL (src) & 0xffff) 2858 == ((INTVAL (src) >> 16) & 0xffff)) 2859 return 6; 2860 } 2861 return 8; 2862 } 2863 2864 base_length = 8; 2865 break; 2866 2867 case E_SFmode: 2868 if (addr == NULL_RTX) 2869 { 2870 if (REG_P (src)) 2871 return 4; 2872 2873 if (satisfies_constraint_G (src)) 2874 return 4; 2875 2876 return 8; 2877 } 2878 2879 base_length = 8; 2880 break; 2881 2882 default: 2883 gcc_unreachable (); 2884 } 2885 2886 /* Adjust the length based on the addressing mode used. 2887 Specifically, we subtract the difference between the actual 2888 length and the longest one, which is @(d:16,Rs). For SImode 2889 and SFmode, we double the adjustment because two mov.w are 2890 used to do the job. */ 2891 2892 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */ 2893 if (GET_CODE (addr) == PRE_DEC 2894 || GET_CODE (addr) == POST_INC) 2895 { 2896 if (mode == QImode || mode == HImode) 2897 return base_length - 2; 2898 else 2899 /* In SImode and SFmode, we use two mov.w instructions, so 2900 double the adjustment. */ 2901 return base_length - 4; 2902 } 2903 2904 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that 2905 in SImode and SFmode, the second mov.w involves an address 2906 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract 2907 only 2 bytes. */ 2908 if (GET_CODE (addr) == REG) 2909 return base_length - 2; 2910 2911 return base_length; 2912 } 2913 else 2914 { 2915 unsigned int base_length; 2916 2917 switch (mode) 2918 { 2919 case E_QImode: 2920 if (addr == NULL_RTX) 2921 return 2; 2922 2923 /* The eightbit addressing is available only in QImode, so 2924 go ahead and take care of it. */ 2925 if (h8300_eightbit_constant_address_p (addr)) 2926 return 2; 2927 2928 base_length = 8; 2929 break; 2930 2931 case E_HImode: 2932 if (addr == NULL_RTX) 2933 { 2934 if (REG_P (src)) 2935 return 2; 2936 2937 if (src == const0_rtx) 2938 return 2; 2939 2940 return 4; 2941 } 2942 2943 base_length = 8; 2944 break; 2945 2946 case E_SImode: 2947 if (addr == NULL_RTX) 2948 { 2949 if (REG_P (src)) 2950 { 2951 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG) 2952 return 4; 2953 else 2954 return 2; 2955 } 2956 2957 if (GET_CODE (src) == CONST_INT) 2958 { 2959 int val = INTVAL (src); 2960 2961 if (val == 0) 2962 return 2; 2963 2964 if (val == (val & 0x00ff) || val == (val & 0xff00)) 2965 return 4; 2966 2967 switch (val & 0xffffffff) 2968 { 2969 case 0xffffffff: 2970 case 0xfffffffe: 2971 case 0xfffffffc: 2972 case 0x0000ffff: 2973 case 0x0000fffe: 2974 case 0xffff0000: 2975 case 0xfffe0000: 2976 case 0x00010000: 2977 case 0x00020000: 2978 return 4; 2979 } 2980 } 2981 return 6; 2982 } 2983 2984 base_length = 10; 2985 break; 2986 2987 case E_SFmode: 2988 if (addr == NULL_RTX) 2989 { 2990 if (REG_P (src)) 2991 return 2; 2992 2993 if (satisfies_constraint_G (src)) 2994 return 2; 2995 2996 return 6; 2997 } 2998 2999 base_length = 10; 3000 break; 3001 3002 default: 3003 gcc_unreachable (); 3004 } 3005 3006 /* Adjust the length based on the addressing mode used. 3007 Specifically, we subtract the difference between the actual 3008 length and the longest one, which is @(d:24,ERs). */ 3009 3010 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */ 3011 if (GET_CODE (addr) == PRE_DEC 3012 || GET_CODE (addr) == POST_INC) 3013 return base_length - 6; 3014 3015 /* @ERs and @ERd are 6 bytes shorter than the longest. */ 3016 if (GET_CODE (addr) == REG) 3017 return base_length - 6; 3018 3019 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the 3020 longest. */ 3021 if (GET_CODE (addr) == PLUS 3022 && GET_CODE (XEXP (addr, 0)) == REG 3023 && GET_CODE (XEXP (addr, 1)) == CONST_INT 3024 && INTVAL (XEXP (addr, 1)) > -32768 3025 && INTVAL (XEXP (addr, 1)) < 32767) 3026 return base_length - 4; 3027 3028 /* @aa:16 is 4 bytes shorter than the longest. */ 3029 if (h8300_tiny_constant_address_p (addr)) 3030 return base_length - 4; 3031 3032 /* @aa:24 is 2 bytes shorter than the longest. */ 3033 if (CONSTANT_P (addr)) 3034 return base_length - 2; 3035 3036 return base_length; 3037 } 3038 } 3039 3040 /* Output an addition insn. */ 3041 3042 const char * 3043 output_plussi (rtx *operands) 3044 { 3045 machine_mode mode = GET_MODE (operands[0]); 3046 3047 gcc_assert (mode == SImode); 3048 3049 if (TARGET_H8300) 3050 { 3051 if (GET_CODE (operands[2]) == REG) 3052 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; 3053 3054 if (GET_CODE (operands[2]) == CONST_INT) 3055 { 3056 HOST_WIDE_INT n = INTVAL (operands[2]); 3057 3058 if ((n & 0xffffff) == 0) 3059 return "add\t%z2,%z0"; 3060 if ((n & 0xffff) == 0) 3061 return "add\t%y2,%y0\n\taddx\t%z2,%z0"; 3062 if ((n & 0xff) == 0) 3063 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; 3064 } 3065 3066 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; 3067 } 3068 else 3069 { 3070 if (GET_CODE (operands[2]) == CONST_INT 3071 && register_operand (operands[1], VOIDmode)) 3072 { 3073 HOST_WIDE_INT intval = INTVAL (operands[2]); 3074 3075 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 3076 return "add.l\t%S2,%S0"; 3077 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 3078 return "sub.l\t%G2,%S0"; 3079 3080 /* See if we can finish with 2 bytes. */ 3081 3082 switch ((unsigned int) intval & 0xffffffff) 3083 { 3084 case 0x00000001: 3085 case 0x00000002: 3086 case 0x00000004: 3087 return "adds\t%2,%S0"; 3088 3089 case 0xffffffff: 3090 case 0xfffffffe: 3091 case 0xfffffffc: 3092 return "subs\t%G2,%S0"; 3093 3094 case 0x00010000: 3095 case 0x00020000: 3096 operands[2] = GEN_INT (intval >> 16); 3097 return "inc.w\t%2,%e0"; 3098 3099 case 0xffff0000: 3100 case 0xfffe0000: 3101 operands[2] = GEN_INT (intval >> 16); 3102 return "dec.w\t%G2,%e0"; 3103 } 3104 3105 /* See if we can finish with 4 bytes. */ 3106 if ((intval & 0xffff) == 0) 3107 { 3108 operands[2] = GEN_INT (intval >> 16); 3109 return "add.w\t%2,%e0"; 3110 } 3111 } 3112 3113 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 3114 { 3115 operands[2] = GEN_INT (-INTVAL (operands[2])); 3116 return "sub.l\t%S2,%S0"; 3117 } 3118 return "add.l\t%S2,%S0"; 3119 } 3120 } 3121 3122 /* ??? It would be much easier to add the h8sx stuff if a single function 3123 classified the addition as either inc/dec, adds/subs, add.w or add.l. */ 3124 /* Compute the length of an addition insn. */ 3125 3126 unsigned int 3127 compute_plussi_length (rtx *operands) 3128 { 3129 machine_mode mode = GET_MODE (operands[0]); 3130 3131 gcc_assert (mode == SImode); 3132 3133 if (TARGET_H8300) 3134 { 3135 if (GET_CODE (operands[2]) == REG) 3136 return 6; 3137 3138 if (GET_CODE (operands[2]) == CONST_INT) 3139 { 3140 HOST_WIDE_INT n = INTVAL (operands[2]); 3141 3142 if ((n & 0xffffff) == 0) 3143 return 2; 3144 if ((n & 0xffff) == 0) 3145 return 4; 3146 if ((n & 0xff) == 0) 3147 return 6; 3148 } 3149 3150 return 8; 3151 } 3152 else 3153 { 3154 if (GET_CODE (operands[2]) == CONST_INT 3155 && register_operand (operands[1], VOIDmode)) 3156 { 3157 HOST_WIDE_INT intval = INTVAL (operands[2]); 3158 3159 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 3160 return 2; 3161 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 3162 return 2; 3163 3164 /* See if we can finish with 2 bytes. */ 3165 3166 switch ((unsigned int) intval & 0xffffffff) 3167 { 3168 case 0x00000001: 3169 case 0x00000002: 3170 case 0x00000004: 3171 return 2; 3172 3173 case 0xffffffff: 3174 case 0xfffffffe: 3175 case 0xfffffffc: 3176 return 2; 3177 3178 case 0x00010000: 3179 case 0x00020000: 3180 return 2; 3181 3182 case 0xffff0000: 3183 case 0xfffe0000: 3184 return 2; 3185 } 3186 3187 /* See if we can finish with 4 bytes. */ 3188 if ((intval & 0xffff) == 0) 3189 return 4; 3190 } 3191 3192 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 3193 return h8300_length_from_table (operands[0], 3194 GEN_INT (-INTVAL (operands[2])), 3195 &addl_length_table); 3196 else 3197 return h8300_length_from_table (operands[0], operands[2], 3198 &addl_length_table); 3199 return 6; 3200 } 3201 } 3202 3203 /* Compute which flag bits are valid after an addition insn. */ 3204 3205 enum attr_cc 3206 compute_plussi_cc (rtx *operands) 3207 { 3208 machine_mode mode = GET_MODE (operands[0]); 3209 3210 gcc_assert (mode == SImode); 3211 3212 if (TARGET_H8300) 3213 { 3214 return CC_CLOBBER; 3215 } 3216 else 3217 { 3218 if (GET_CODE (operands[2]) == CONST_INT 3219 && register_operand (operands[1], VOIDmode)) 3220 { 3221 HOST_WIDE_INT intval = INTVAL (operands[2]); 3222 3223 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 3224 return CC_SET_ZN; 3225 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 3226 return CC_SET_ZN; 3227 3228 /* See if we can finish with 2 bytes. */ 3229 3230 switch ((unsigned int) intval & 0xffffffff) 3231 { 3232 case 0x00000001: 3233 case 0x00000002: 3234 case 0x00000004: 3235 return CC_NONE_0HIT; 3236 3237 case 0xffffffff: 3238 case 0xfffffffe: 3239 case 0xfffffffc: 3240 return CC_NONE_0HIT; 3241 3242 case 0x00010000: 3243 case 0x00020000: 3244 return CC_CLOBBER; 3245 3246 case 0xffff0000: 3247 case 0xfffe0000: 3248 return CC_CLOBBER; 3249 } 3250 3251 /* See if we can finish with 4 bytes. */ 3252 if ((intval & 0xffff) == 0) 3253 return CC_CLOBBER; 3254 } 3255 3256 return CC_SET_ZN; 3257 } 3258 } 3259 3260 /* Output a logical insn. */ 3261 3262 const char * 3263 output_logical_op (machine_mode mode, rtx *operands) 3264 { 3265 /* Figure out the logical op that we need to perform. */ 3266 enum rtx_code code = GET_CODE (operands[3]); 3267 /* Pretend that every byte is affected if both operands are registers. */ 3268 const unsigned HOST_WIDE_INT intval = 3269 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3270 /* Always use the full instruction if the 3271 first operand is in memory. It is better 3272 to use define_splits to generate the shorter 3273 sequence where valid. */ 3274 && register_operand (operands[1], VOIDmode) 3275 ? INTVAL (operands[2]) : 0x55555555); 3276 /* The determinant of the algorithm. If we perform an AND, 0 3277 affects a bit. Otherwise, 1 affects a bit. */ 3278 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3279 /* Break up DET into pieces. */ 3280 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3281 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3282 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; 3283 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; 3284 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3285 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3286 int lower_half_easy_p = 0; 3287 int upper_half_easy_p = 0; 3288 /* The name of an insn. */ 3289 const char *opname; 3290 char insn_buf[100]; 3291 3292 switch (code) 3293 { 3294 case AND: 3295 opname = "and"; 3296 break; 3297 case IOR: 3298 opname = "or"; 3299 break; 3300 case XOR: 3301 opname = "xor"; 3302 break; 3303 default: 3304 gcc_unreachable (); 3305 } 3306 3307 switch (mode) 3308 { 3309 case E_HImode: 3310 /* First, see if we can finish with one insn. */ 3311 if ((TARGET_H8300H || TARGET_H8300S) 3312 && b0 != 0 3313 && b1 != 0) 3314 { 3315 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname); 3316 output_asm_insn (insn_buf, operands); 3317 } 3318 else 3319 { 3320 /* Take care of the lower byte. */ 3321 if (b0 != 0) 3322 { 3323 sprintf (insn_buf, "%s\t%%s2,%%s0", opname); 3324 output_asm_insn (insn_buf, operands); 3325 } 3326 /* Take care of the upper byte. */ 3327 if (b1 != 0) 3328 { 3329 sprintf (insn_buf, "%s\t%%t2,%%t0", opname); 3330 output_asm_insn (insn_buf, operands); 3331 } 3332 } 3333 break; 3334 case E_SImode: 3335 if (TARGET_H8300H || TARGET_H8300S) 3336 { 3337 /* Determine if the lower half can be taken care of in no more 3338 than two bytes. */ 3339 lower_half_easy_p = (b0 == 0 3340 || b1 == 0 3341 || (code != IOR && w0 == 0xffff)); 3342 3343 /* Determine if the upper half can be taken care of in no more 3344 than two bytes. */ 3345 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3346 || (code == AND && w1 == 0xff00)); 3347 } 3348 3349 /* Check if doing everything with one insn is no worse than 3350 using multiple insns. */ 3351 if ((TARGET_H8300H || TARGET_H8300S) 3352 && w0 != 0 && w1 != 0 3353 && !(lower_half_easy_p && upper_half_easy_p) 3354 && !(code == IOR && w1 == 0xffff 3355 && (w0 & 0x8000) != 0 && lower_half_easy_p)) 3356 { 3357 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname); 3358 output_asm_insn (insn_buf, operands); 3359 } 3360 else 3361 { 3362 /* Take care of the lower and upper words individually. For 3363 each word, we try different methods in the order of 3364 3365 1) the special insn (in case of AND or XOR), 3366 2) the word-wise insn, and 3367 3) The byte-wise insn. */ 3368 if (w0 == 0xffff 3369 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3370 output_asm_insn ((code == AND) 3371 ? "sub.w\t%f0,%f0" : "not.w\t%f0", 3372 operands); 3373 else if ((TARGET_H8300H || TARGET_H8300S) 3374 && (b0 != 0) 3375 && (b1 != 0)) 3376 { 3377 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname); 3378 output_asm_insn (insn_buf, operands); 3379 } 3380 else 3381 { 3382 if (b0 != 0) 3383 { 3384 sprintf (insn_buf, "%s\t%%w2,%%w0", opname); 3385 output_asm_insn (insn_buf, operands); 3386 } 3387 if (b1 != 0) 3388 { 3389 sprintf (insn_buf, "%s\t%%x2,%%x0", opname); 3390 output_asm_insn (insn_buf, operands); 3391 } 3392 } 3393 3394 if ((w1 == 0xffff) 3395 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3396 output_asm_insn ((code == AND) 3397 ? "sub.w\t%e0,%e0" : "not.w\t%e0", 3398 operands); 3399 else if ((TARGET_H8300H || TARGET_H8300S) 3400 && code == IOR 3401 && w1 == 0xffff 3402 && (w0 & 0x8000) != 0) 3403 { 3404 output_asm_insn ("exts.l\t%S0", operands); 3405 } 3406 else if ((TARGET_H8300H || TARGET_H8300S) 3407 && code == AND 3408 && w1 == 0xff00) 3409 { 3410 output_asm_insn ("extu.w\t%e0", operands); 3411 } 3412 else if (TARGET_H8300H || TARGET_H8300S) 3413 { 3414 if (w1 != 0) 3415 { 3416 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname); 3417 output_asm_insn (insn_buf, operands); 3418 } 3419 } 3420 else 3421 { 3422 if (b2 != 0) 3423 { 3424 sprintf (insn_buf, "%s\t%%y2,%%y0", opname); 3425 output_asm_insn (insn_buf, operands); 3426 } 3427 if (b3 != 0) 3428 { 3429 sprintf (insn_buf, "%s\t%%z2,%%z0", opname); 3430 output_asm_insn (insn_buf, operands); 3431 } 3432 } 3433 } 3434 break; 3435 default: 3436 gcc_unreachable (); 3437 } 3438 return ""; 3439 } 3440 3441 /* Compute the length of a logical insn. */ 3442 3443 unsigned int 3444 compute_logical_op_length (machine_mode mode, rtx *operands) 3445 { 3446 /* Figure out the logical op that we need to perform. */ 3447 enum rtx_code code = GET_CODE (operands[3]); 3448 /* Pretend that every byte is affected if both operands are registers. */ 3449 const unsigned HOST_WIDE_INT intval = 3450 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3451 /* Always use the full instruction if the 3452 first operand is in memory. It is better 3453 to use define_splits to generate the shorter 3454 sequence where valid. */ 3455 && register_operand (operands[1], VOIDmode) 3456 ? INTVAL (operands[2]) : 0x55555555); 3457 /* The determinant of the algorithm. If we perform an AND, 0 3458 affects a bit. Otherwise, 1 affects a bit. */ 3459 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3460 /* Break up DET into pieces. */ 3461 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3462 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3463 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; 3464 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; 3465 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3466 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3467 int lower_half_easy_p = 0; 3468 int upper_half_easy_p = 0; 3469 /* Insn length. */ 3470 unsigned int length = 0; 3471 3472 switch (mode) 3473 { 3474 case E_HImode: 3475 /* First, see if we can finish with one insn. */ 3476 if ((TARGET_H8300H || TARGET_H8300S) 3477 && b0 != 0 3478 && b1 != 0) 3479 { 3480 length = h8300_length_from_table (operands[1], operands[2], 3481 &logicw_length_table); 3482 } 3483 else 3484 { 3485 /* Take care of the lower byte. */ 3486 if (b0 != 0) 3487 length += 2; 3488 3489 /* Take care of the upper byte. */ 3490 if (b1 != 0) 3491 length += 2; 3492 } 3493 break; 3494 case E_SImode: 3495 if (TARGET_H8300H || TARGET_H8300S) 3496 { 3497 /* Determine if the lower half can be taken care of in no more 3498 than two bytes. */ 3499 lower_half_easy_p = (b0 == 0 3500 || b1 == 0 3501 || (code != IOR && w0 == 0xffff)); 3502 3503 /* Determine if the upper half can be taken care of in no more 3504 than two bytes. */ 3505 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3506 || (code == AND && w1 == 0xff00)); 3507 } 3508 3509 /* Check if doing everything with one insn is no worse than 3510 using multiple insns. */ 3511 if ((TARGET_H8300H || TARGET_H8300S) 3512 && w0 != 0 && w1 != 0 3513 && !(lower_half_easy_p && upper_half_easy_p) 3514 && !(code == IOR && w1 == 0xffff 3515 && (w0 & 0x8000) != 0 && lower_half_easy_p)) 3516 { 3517 length = h8300_length_from_table (operands[1], operands[2], 3518 &logicl_length_table); 3519 } 3520 else 3521 { 3522 /* Take care of the lower and upper words individually. For 3523 each word, we try different methods in the order of 3524 3525 1) the special insn (in case of AND or XOR), 3526 2) the word-wise insn, and 3527 3) The byte-wise insn. */ 3528 if (w0 == 0xffff 3529 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3530 { 3531 length += 2; 3532 } 3533 else if ((TARGET_H8300H || TARGET_H8300S) 3534 && (b0 != 0) 3535 && (b1 != 0)) 3536 { 3537 length += 4; 3538 } 3539 else 3540 { 3541 if (b0 != 0) 3542 length += 2; 3543 3544 if (b1 != 0) 3545 length += 2; 3546 } 3547 3548 if (w1 == 0xffff 3549 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3550 { 3551 length += 2; 3552 } 3553 else if ((TARGET_H8300H || TARGET_H8300S) 3554 && code == IOR 3555 && w1 == 0xffff 3556 && (w0 & 0x8000) != 0) 3557 { 3558 length += 2; 3559 } 3560 else if ((TARGET_H8300H || TARGET_H8300S) 3561 && code == AND 3562 && w1 == 0xff00) 3563 { 3564 length += 2; 3565 } 3566 else if (TARGET_H8300H || TARGET_H8300S) 3567 { 3568 if (w1 != 0) 3569 length += 4; 3570 } 3571 else 3572 { 3573 if (b2 != 0) 3574 length += 2; 3575 3576 if (b3 != 0) 3577 length += 2; 3578 } 3579 } 3580 break; 3581 default: 3582 gcc_unreachable (); 3583 } 3584 return length; 3585 } 3586 3587 /* Compute which flag bits are valid after a logical insn. */ 3588 3589 enum attr_cc 3590 compute_logical_op_cc (machine_mode mode, rtx *operands) 3591 { 3592 /* Figure out the logical op that we need to perform. */ 3593 enum rtx_code code = GET_CODE (operands[3]); 3594 /* Pretend that every byte is affected if both operands are registers. */ 3595 const unsigned HOST_WIDE_INT intval = 3596 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3597 /* Always use the full instruction if the 3598 first operand is in memory. It is better 3599 to use define_splits to generate the shorter 3600 sequence where valid. */ 3601 && register_operand (operands[1], VOIDmode) 3602 ? INTVAL (operands[2]) : 0x55555555); 3603 /* The determinant of the algorithm. If we perform an AND, 0 3604 affects a bit. Otherwise, 1 affects a bit. */ 3605 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3606 /* Break up DET into pieces. */ 3607 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3608 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3609 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3610 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3611 int lower_half_easy_p = 0; 3612 int upper_half_easy_p = 0; 3613 /* Condition code. */ 3614 enum attr_cc cc = CC_CLOBBER; 3615 3616 switch (mode) 3617 { 3618 case E_HImode: 3619 /* First, see if we can finish with one insn. */ 3620 if ((TARGET_H8300H || TARGET_H8300S) 3621 && b0 != 0 3622 && b1 != 0) 3623 { 3624 cc = CC_SET_ZNV; 3625 } 3626 break; 3627 case E_SImode: 3628 if (TARGET_H8300H || TARGET_H8300S) 3629 { 3630 /* Determine if the lower half can be taken care of in no more 3631 than two bytes. */ 3632 lower_half_easy_p = (b0 == 0 3633 || b1 == 0 3634 || (code != IOR && w0 == 0xffff)); 3635 3636 /* Determine if the upper half can be taken care of in no more 3637 than two bytes. */ 3638 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3639 || (code == AND && w1 == 0xff00)); 3640 } 3641 3642 /* Check if doing everything with one insn is no worse than 3643 using multiple insns. */ 3644 if ((TARGET_H8300H || TARGET_H8300S) 3645 && w0 != 0 && w1 != 0 3646 && !(lower_half_easy_p && upper_half_easy_p) 3647 && !(code == IOR && w1 == 0xffff 3648 && (w0 & 0x8000) != 0 && lower_half_easy_p)) 3649 { 3650 cc = CC_SET_ZNV; 3651 } 3652 else 3653 { 3654 if ((TARGET_H8300H || TARGET_H8300S) 3655 && code == IOR 3656 && w1 == 0xffff 3657 && (w0 & 0x8000) != 0) 3658 { 3659 cc = CC_SET_ZNV; 3660 } 3661 } 3662 break; 3663 default: 3664 gcc_unreachable (); 3665 } 3666 return cc; 3667 } 3668 3669 /* Expand a conditional branch. */ 3670 3671 void 3672 h8300_expand_branch (rtx operands[]) 3673 { 3674 enum rtx_code code = GET_CODE (operands[0]); 3675 rtx op0 = operands[1]; 3676 rtx op1 = operands[2]; 3677 rtx label = operands[3]; 3678 rtx tmp; 3679 3680 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); 3681 emit_insn (gen_rtx_SET (cc0_rtx, tmp)); 3682 3683 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx); 3684 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 3685 gen_rtx_LABEL_REF (VOIDmode, label), 3686 pc_rtx); 3687 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp)); 3688 } 3689 3690 3691 /* Expand a conditional store. */ 3692 3693 void 3694 h8300_expand_store (rtx operands[]) 3695 { 3696 rtx dest = operands[0]; 3697 enum rtx_code code = GET_CODE (operands[1]); 3698 rtx op0 = operands[2]; 3699 rtx op1 = operands[3]; 3700 rtx tmp; 3701 3702 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); 3703 emit_insn (gen_rtx_SET (cc0_rtx, tmp)); 3704 3705 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx); 3706 emit_insn (gen_rtx_SET (dest, tmp)); 3707 } 3708 3709 /* Shifts. 3710 3711 We devote a fair bit of code to getting efficient shifts since we 3712 can only shift one bit at a time on the H8/300 and H8/300H and only 3713 one or two bits at a time on the H8S. 3714 3715 All shift code falls into one of the following ways of 3716 implementation: 3717 3718 o SHIFT_INLINE: Emit straight line code for the shift; this is used 3719 when a straight line shift is about the same size or smaller than 3720 a loop. 3721 3722 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask 3723 off the bits we don't need. This is used when only a few of the 3724 bits in the original value will survive in the shifted value. 3725 3726 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to 3727 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline 3728 shifts can be added if the shift count is slightly more than 8 or 3729 16. This case also includes other oddballs that are not worth 3730 explaining here. 3731 3732 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts. 3733 3734 For each shift count, we try to use code that has no trade-off 3735 between code size and speed whenever possible. 3736 3737 If the trade-off is unavoidable, we try to be reasonable. 3738 Specifically, the fastest version is one instruction longer than 3739 the shortest version, we take the fastest version. We also provide 3740 the use a way to switch back to the shortest version with -Os. 3741 3742 For the details of the shift algorithms for various shift counts, 3743 refer to shift_alg_[qhs]i. */ 3744 3745 /* Classify a shift with the given mode and code. OP is the shift amount. */ 3746 3747 enum h8sx_shift_type 3748 h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op) 3749 { 3750 if (!TARGET_H8300SX) 3751 return H8SX_SHIFT_NONE; 3752 3753 switch (code) 3754 { 3755 case ASHIFT: 3756 case LSHIFTRT: 3757 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */ 3758 if (GET_CODE (op) != CONST_INT) 3759 return H8SX_SHIFT_BINARY; 3760 3761 /* Reject out-of-range shift amounts. */ 3762 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode)) 3763 return H8SX_SHIFT_NONE; 3764 3765 /* Power-of-2 shifts are effectively unary operations. */ 3766 if (exact_log2 (INTVAL (op)) >= 0) 3767 return H8SX_SHIFT_UNARY; 3768 3769 return H8SX_SHIFT_BINARY; 3770 3771 case ASHIFTRT: 3772 if (op == const1_rtx || op == const2_rtx) 3773 return H8SX_SHIFT_UNARY; 3774 return H8SX_SHIFT_NONE; 3775 3776 case ROTATE: 3777 if (GET_CODE (op) == CONST_INT 3778 && (INTVAL (op) == 1 3779 || INTVAL (op) == 2 3780 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2 3781 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1)) 3782 return H8SX_SHIFT_UNARY; 3783 return H8SX_SHIFT_NONE; 3784 3785 default: 3786 return H8SX_SHIFT_NONE; 3787 } 3788 } 3789 3790 /* Return the asm template for a single h8sx shift instruction. 3791 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2] 3792 is the source and OPERANDS[3] is the shift. SUFFIX is the 3793 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand 3794 prefix for the destination operand. */ 3795 3796 const char * 3797 output_h8sx_shift (rtx *operands, int suffix, int optype) 3798 { 3799 static char buffer[16]; 3800 const char *stem; 3801 3802 switch (GET_CODE (operands[3])) 3803 { 3804 case ASHIFT: 3805 stem = "shll"; 3806 break; 3807 3808 case ASHIFTRT: 3809 stem = "shar"; 3810 break; 3811 3812 case LSHIFTRT: 3813 stem = "shlr"; 3814 break; 3815 3816 case ROTATE: 3817 stem = "rotl"; 3818 if (INTVAL (operands[2]) > 2) 3819 { 3820 /* This is really a right rotate. */ 3821 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0])) 3822 - INTVAL (operands[2])); 3823 stem = "rotr"; 3824 } 3825 break; 3826 3827 default: 3828 gcc_unreachable (); 3829 } 3830 if (operands[2] == const1_rtx) 3831 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype); 3832 else 3833 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype); 3834 return buffer; 3835 } 3836 3837 /* Emit code to do shifts. */ 3838 3839 bool 3840 expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[]) 3841 { 3842 switch (h8sx_classify_shift (mode, code, operands[2])) 3843 { 3844 case H8SX_SHIFT_BINARY: 3845 operands[1] = force_reg (mode, operands[1]); 3846 return false; 3847 3848 case H8SX_SHIFT_UNARY: 3849 return false; 3850 3851 case H8SX_SHIFT_NONE: 3852 break; 3853 } 3854 3855 emit_move_insn (copy_rtx (operands[0]), operands[1]); 3856 3857 /* Need a loop to get all the bits we want - we generate the 3858 code at emit time, but need to allocate a scratch reg now. */ 3859 3860 emit_insn (gen_rtx_PARALLEL 3861 (VOIDmode, 3862 gen_rtvec (2, 3863 gen_rtx_SET (copy_rtx (operands[0]), 3864 gen_rtx_fmt_ee (code, mode, 3865 copy_rtx (operands[0]), operands[2])), 3866 gen_rtx_CLOBBER (VOIDmode, 3867 gen_rtx_SCRATCH (QImode))))); 3868 return true; 3869 } 3870 3871 /* Symbols of the various modes which can be used as indices. */ 3872 3873 enum shift_mode 3874 { 3875 QIshift, HIshift, SIshift 3876 }; 3877 3878 /* For single bit shift insns, record assembler and what bits of the 3879 condition code are valid afterwards (represented as various CC_FOO 3880 bits, 0 means CC isn't left in a usable state). */ 3881 3882 struct shift_insn 3883 { 3884 const char *const assembler; 3885 const enum attr_cc cc_valid; 3886 }; 3887 3888 /* Assembler instruction shift table. 3889 3890 These tables are used to look up the basic shifts. 3891 They are indexed by cpu, shift_type, and mode. */ 3892 3893 static const struct shift_insn shift_one[2][3][3] = 3894 { 3895 /* H8/300 */ 3896 { 3897 /* SHIFT_ASHIFT */ 3898 { 3899 { "shll\t%X0", CC_SET_ZNV }, 3900 { "add.w\t%T0,%T0", CC_SET_ZN }, 3901 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER } 3902 }, 3903 /* SHIFT_LSHIFTRT */ 3904 { 3905 { "shlr\t%X0", CC_SET_ZNV }, 3906 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER }, 3907 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } 3908 }, 3909 /* SHIFT_ASHIFTRT */ 3910 { 3911 { "shar\t%X0", CC_SET_ZNV }, 3912 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER }, 3913 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } 3914 } 3915 }, 3916 /* H8/300H */ 3917 { 3918 /* SHIFT_ASHIFT */ 3919 { 3920 { "shll.b\t%X0", CC_SET_ZNV }, 3921 { "shll.w\t%T0", CC_SET_ZNV }, 3922 { "shll.l\t%S0", CC_SET_ZNV } 3923 }, 3924 /* SHIFT_LSHIFTRT */ 3925 { 3926 { "shlr.b\t%X0", CC_SET_ZNV }, 3927 { "shlr.w\t%T0", CC_SET_ZNV }, 3928 { "shlr.l\t%S0", CC_SET_ZNV } 3929 }, 3930 /* SHIFT_ASHIFTRT */ 3931 { 3932 { "shar.b\t%X0", CC_SET_ZNV }, 3933 { "shar.w\t%T0", CC_SET_ZNV }, 3934 { "shar.l\t%S0", CC_SET_ZNV } 3935 } 3936 } 3937 }; 3938 3939 static const struct shift_insn shift_two[3][3] = 3940 { 3941 /* SHIFT_ASHIFT */ 3942 { 3943 { "shll.b\t#2,%X0", CC_SET_ZNV }, 3944 { "shll.w\t#2,%T0", CC_SET_ZNV }, 3945 { "shll.l\t#2,%S0", CC_SET_ZNV } 3946 }, 3947 /* SHIFT_LSHIFTRT */ 3948 { 3949 { "shlr.b\t#2,%X0", CC_SET_ZNV }, 3950 { "shlr.w\t#2,%T0", CC_SET_ZNV }, 3951 { "shlr.l\t#2,%S0", CC_SET_ZNV } 3952 }, 3953 /* SHIFT_ASHIFTRT */ 3954 { 3955 { "shar.b\t#2,%X0", CC_SET_ZNV }, 3956 { "shar.w\t#2,%T0", CC_SET_ZNV }, 3957 { "shar.l\t#2,%S0", CC_SET_ZNV } 3958 } 3959 }; 3960 3961 /* Rotates are organized by which shift they'll be used in implementing. 3962 There's no need to record whether the cc is valid afterwards because 3963 it is the AND insn that will decide this. */ 3964 3965 static const char *const rotate_one[2][3][3] = 3966 { 3967 /* H8/300 */ 3968 { 3969 /* SHIFT_ASHIFT */ 3970 { 3971 "rotr\t%X0", 3972 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", 3973 0 3974 }, 3975 /* SHIFT_LSHIFTRT */ 3976 { 3977 "rotl\t%X0", 3978 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3979 0 3980 }, 3981 /* SHIFT_ASHIFTRT */ 3982 { 3983 "rotl\t%X0", 3984 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3985 0 3986 } 3987 }, 3988 /* H8/300H */ 3989 { 3990 /* SHIFT_ASHIFT */ 3991 { 3992 "rotr.b\t%X0", 3993 "rotr.w\t%T0", 3994 "rotr.l\t%S0" 3995 }, 3996 /* SHIFT_LSHIFTRT */ 3997 { 3998 "rotl.b\t%X0", 3999 "rotl.w\t%T0", 4000 "rotl.l\t%S0" 4001 }, 4002 /* SHIFT_ASHIFTRT */ 4003 { 4004 "rotl.b\t%X0", 4005 "rotl.w\t%T0", 4006 "rotl.l\t%S0" 4007 } 4008 } 4009 }; 4010 4011 static const char *const rotate_two[3][3] = 4012 { 4013 /* SHIFT_ASHIFT */ 4014 { 4015 "rotr.b\t#2,%X0", 4016 "rotr.w\t#2,%T0", 4017 "rotr.l\t#2,%S0" 4018 }, 4019 /* SHIFT_LSHIFTRT */ 4020 { 4021 "rotl.b\t#2,%X0", 4022 "rotl.w\t#2,%T0", 4023 "rotl.l\t#2,%S0" 4024 }, 4025 /* SHIFT_ASHIFTRT */ 4026 { 4027 "rotl.b\t#2,%X0", 4028 "rotl.w\t#2,%T0", 4029 "rotl.l\t#2,%S0" 4030 } 4031 }; 4032 4033 struct shift_info { 4034 /* Shift algorithm. */ 4035 enum shift_alg alg; 4036 4037 /* The number of bits to be shifted by shift1 and shift2. Valid 4038 when ALG is SHIFT_SPECIAL. */ 4039 unsigned int remainder; 4040 4041 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */ 4042 const char *special; 4043 4044 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE 4045 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 4046 const char *shift1; 4047 4048 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE 4049 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 4050 const char *shift2; 4051 4052 /* CC status for SHIFT_INLINE. */ 4053 enum attr_cc cc_inline; 4054 4055 /* CC status for SHIFT_SPECIAL. */ 4056 enum attr_cc cc_special; 4057 }; 4058 4059 static void get_shift_alg (enum shift_type, 4060 enum shift_mode, unsigned int, 4061 struct shift_info *); 4062 4063 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the 4064 best algorithm for doing the shift. The assembler code is stored 4065 in the pointers in INFO. We achieve the maximum efficiency in most 4066 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in 4067 SImode in particular have a lot of room to optimize. 4068 4069 We first determine the strategy of the shift algorithm by a table 4070 lookup. If that tells us to use a hand crafted assembly code, we 4071 go into the big switch statement to find what that is. Otherwise, 4072 we resort to a generic way, such as inlining. In either case, the 4073 result is returned through INFO. */ 4074 4075 static void 4076 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode, 4077 unsigned int count, struct shift_info *info) 4078 { 4079 enum h8_cpu cpu; 4080 4081 /* Find the target CPU. */ 4082 if (TARGET_H8300) 4083 cpu = H8_300; 4084 else if (TARGET_H8300S) 4085 cpu = H8_S; 4086 else 4087 cpu = H8_300H; 4088 4089 /* Find the shift algorithm. */ 4090 info->alg = SHIFT_LOOP; 4091 switch (shift_mode) 4092 { 4093 case QIshift: 4094 if (count < GET_MODE_BITSIZE (QImode)) 4095 info->alg = shift_alg_qi[cpu][shift_type][count]; 4096 break; 4097 4098 case HIshift: 4099 if (count < GET_MODE_BITSIZE (HImode)) 4100 info->alg = shift_alg_hi[cpu][shift_type][count]; 4101 break; 4102 4103 case SIshift: 4104 if (count < GET_MODE_BITSIZE (SImode)) 4105 info->alg = shift_alg_si[cpu][shift_type][count]; 4106 break; 4107 4108 default: 4109 gcc_unreachable (); 4110 } 4111 4112 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */ 4113 switch (info->alg) 4114 { 4115 case SHIFT_INLINE: 4116 info->remainder = count; 4117 /* Fall through. */ 4118 4119 case SHIFT_LOOP: 4120 /* It is up to the caller to know that looping clobbers cc. */ 4121 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 4122 info->shift2 = shift_two[shift_type][shift_mode].assembler; 4123 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 4124 goto end; 4125 4126 case SHIFT_ROT_AND: 4127 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode]; 4128 info->shift2 = rotate_two[shift_type][shift_mode]; 4129 info->cc_inline = CC_CLOBBER; 4130 goto end; 4131 4132 case SHIFT_SPECIAL: 4133 /* REMAINDER is 0 for most cases, so initialize it to 0. */ 4134 info->remainder = 0; 4135 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 4136 info->shift2 = shift_two[shift_type][shift_mode].assembler; 4137 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 4138 info->cc_special = CC_CLOBBER; 4139 break; 4140 } 4141 4142 /* Here we only deal with SHIFT_SPECIAL. */ 4143 switch (shift_mode) 4144 { 4145 case QIshift: 4146 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated 4147 through the entire value. */ 4148 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7); 4149 info->special = "shll\t%X0\n\tsubx\t%X0,%X0"; 4150 goto end; 4151 4152 case HIshift: 4153 if (count == 7) 4154 { 4155 switch (shift_type) 4156 { 4157 case SHIFT_ASHIFT: 4158 if (TARGET_H8300) 4159 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0"; 4160 else 4161 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; 4162 goto end; 4163 case SHIFT_LSHIFTRT: 4164 if (TARGET_H8300) 4165 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0"; 4166 else 4167 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; 4168 goto end; 4169 case SHIFT_ASHIFTRT: 4170 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; 4171 goto end; 4172 } 4173 } 4174 else if ((count >= 8 && count <= 13) 4175 || (TARGET_H8300S && count == 14)) 4176 { 4177 info->remainder = count - 8; 4178 4179 switch (shift_type) 4180 { 4181 case SHIFT_ASHIFT: 4182 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; 4183 goto end; 4184 case SHIFT_LSHIFTRT: 4185 if (TARGET_H8300) 4186 { 4187 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0"; 4188 info->shift1 = "shlr.b\t%s0"; 4189 info->cc_inline = CC_SET_ZNV; 4190 } 4191 else 4192 { 4193 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0"; 4194 info->cc_special = CC_SET_ZNV; 4195 } 4196 goto end; 4197 case SHIFT_ASHIFTRT: 4198 if (TARGET_H8300) 4199 { 4200 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0"; 4201 info->shift1 = "shar.b\t%s0"; 4202 } 4203 else 4204 { 4205 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0"; 4206 info->cc_special = CC_SET_ZNV; 4207 } 4208 goto end; 4209 } 4210 } 4211 else if (count == 14) 4212 { 4213 switch (shift_type) 4214 { 4215 case SHIFT_ASHIFT: 4216 if (TARGET_H8300) 4217 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0"; 4218 goto end; 4219 case SHIFT_LSHIFTRT: 4220 if (TARGET_H8300) 4221 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0"; 4222 goto end; 4223 case SHIFT_ASHIFTRT: 4224 if (TARGET_H8300) 4225 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0"; 4226 else if (TARGET_H8300H) 4227 { 4228 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0"; 4229 info->cc_special = CC_SET_ZNV; 4230 } 4231 else /* TARGET_H8300S */ 4232 gcc_unreachable (); 4233 goto end; 4234 } 4235 } 4236 else if (count == 15) 4237 { 4238 switch (shift_type) 4239 { 4240 case SHIFT_ASHIFT: 4241 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0"; 4242 goto end; 4243 case SHIFT_LSHIFTRT: 4244 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0"; 4245 goto end; 4246 case SHIFT_ASHIFTRT: 4247 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; 4248 goto end; 4249 } 4250 } 4251 gcc_unreachable (); 4252 4253 case SIshift: 4254 if (TARGET_H8300 && count >= 8 && count <= 9) 4255 { 4256 info->remainder = count - 8; 4257 4258 switch (shift_type) 4259 { 4260 case SHIFT_ASHIFT: 4261 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0"; 4262 goto end; 4263 case SHIFT_LSHIFTRT: 4264 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0"; 4265 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0"; 4266 goto end; 4267 case SHIFT_ASHIFTRT: 4268 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0"; 4269 goto end; 4270 } 4271 } 4272 else if (count == 8 && !TARGET_H8300) 4273 { 4274 switch (shift_type) 4275 { 4276 case SHIFT_ASHIFT: 4277 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0"; 4278 goto end; 4279 case SHIFT_LSHIFTRT: 4280 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0"; 4281 goto end; 4282 case SHIFT_ASHIFTRT: 4283 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0"; 4284 goto end; 4285 } 4286 } 4287 else if (count == 15 && TARGET_H8300) 4288 { 4289 switch (shift_type) 4290 { 4291 case SHIFT_ASHIFT: 4292 gcc_unreachable (); 4293 case SHIFT_LSHIFTRT: 4294 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0"; 4295 goto end; 4296 case SHIFT_ASHIFTRT: 4297 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0"; 4298 goto end; 4299 } 4300 } 4301 else if (count == 15 && !TARGET_H8300) 4302 { 4303 switch (shift_type) 4304 { 4305 case SHIFT_ASHIFT: 4306 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0"; 4307 info->cc_special = CC_SET_ZNV; 4308 goto end; 4309 case SHIFT_LSHIFTRT: 4310 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0"; 4311 info->cc_special = CC_SET_ZNV; 4312 goto end; 4313 case SHIFT_ASHIFTRT: 4314 gcc_unreachable (); 4315 } 4316 } 4317 else if ((TARGET_H8300 && count >= 16 && count <= 20) 4318 || (TARGET_H8300H && count >= 16 && count <= 19) 4319 || (TARGET_H8300S && count >= 16 && count <= 21)) 4320 { 4321 info->remainder = count - 16; 4322 4323 switch (shift_type) 4324 { 4325 case SHIFT_ASHIFT: 4326 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 4327 if (TARGET_H8300) 4328 info->shift1 = "add.w\t%e0,%e0"; 4329 goto end; 4330 case SHIFT_LSHIFTRT: 4331 if (TARGET_H8300) 4332 { 4333 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0"; 4334 info->shift1 = "shlr\t%x0\n\trotxr\t%w0"; 4335 } 4336 else 4337 { 4338 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0"; 4339 info->cc_special = CC_SET_ZNV; 4340 } 4341 goto end; 4342 case SHIFT_ASHIFTRT: 4343 if (TARGET_H8300) 4344 { 4345 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0"; 4346 info->shift1 = "shar\t%x0\n\trotxr\t%w0"; 4347 } 4348 else 4349 { 4350 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0"; 4351 info->cc_special = CC_SET_ZNV; 4352 } 4353 goto end; 4354 } 4355 } 4356 else if (TARGET_H8300 && count >= 24 && count <= 28) 4357 { 4358 info->remainder = count - 24; 4359 4360 switch (shift_type) 4361 { 4362 case SHIFT_ASHIFT: 4363 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0"; 4364 info->shift1 = "shll.b\t%z0"; 4365 info->cc_inline = CC_SET_ZNV; 4366 goto end; 4367 case SHIFT_LSHIFTRT: 4368 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0"; 4369 info->shift1 = "shlr.b\t%w0"; 4370 info->cc_inline = CC_SET_ZNV; 4371 goto end; 4372 case SHIFT_ASHIFTRT: 4373 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0"; 4374 info->shift1 = "shar.b\t%w0"; 4375 info->cc_inline = CC_SET_ZNV; 4376 goto end; 4377 } 4378 } 4379 else if ((TARGET_H8300H && count == 24) 4380 || (TARGET_H8300S && count >= 24 && count <= 25)) 4381 { 4382 info->remainder = count - 24; 4383 4384 switch (shift_type) 4385 { 4386 case SHIFT_ASHIFT: 4387 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 4388 goto end; 4389 case SHIFT_LSHIFTRT: 4390 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; 4391 info->cc_special = CC_SET_ZNV; 4392 goto end; 4393 case SHIFT_ASHIFTRT: 4394 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 4395 info->cc_special = CC_SET_ZNV; 4396 goto end; 4397 } 4398 } 4399 else if (!TARGET_H8300 && count == 28) 4400 { 4401 switch (shift_type) 4402 { 4403 case SHIFT_ASHIFT: 4404 if (TARGET_H8300H) 4405 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4406 else 4407 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 4408 goto end; 4409 case SHIFT_LSHIFTRT: 4410 if (TARGET_H8300H) 4411 { 4412 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4413 info->cc_special = CC_SET_ZNV; 4414 } 4415 else 4416 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 4417 goto end; 4418 case SHIFT_ASHIFTRT: 4419 gcc_unreachable (); 4420 } 4421 } 4422 else if (!TARGET_H8300 && count == 29) 4423 { 4424 switch (shift_type) 4425 { 4426 case SHIFT_ASHIFT: 4427 if (TARGET_H8300H) 4428 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4429 else 4430 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4431 goto end; 4432 case SHIFT_LSHIFTRT: 4433 if (TARGET_H8300H) 4434 { 4435 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4436 info->cc_special = CC_SET_ZNV; 4437 } 4438 else 4439 { 4440 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4441 info->cc_special = CC_SET_ZNV; 4442 } 4443 goto end; 4444 case SHIFT_ASHIFTRT: 4445 gcc_unreachable (); 4446 } 4447 } 4448 else if (!TARGET_H8300 && count == 30) 4449 { 4450 switch (shift_type) 4451 { 4452 case SHIFT_ASHIFT: 4453 if (TARGET_H8300H) 4454 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4455 else 4456 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 4457 goto end; 4458 case SHIFT_LSHIFTRT: 4459 if (TARGET_H8300H) 4460 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4461 else 4462 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 4463 goto end; 4464 case SHIFT_ASHIFTRT: 4465 gcc_unreachable (); 4466 } 4467 } 4468 else if (count == 31) 4469 { 4470 if (TARGET_H8300) 4471 { 4472 switch (shift_type) 4473 { 4474 case SHIFT_ASHIFT: 4475 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0"; 4476 goto end; 4477 case SHIFT_LSHIFTRT: 4478 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0"; 4479 goto end; 4480 case SHIFT_ASHIFTRT: 4481 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0"; 4482 goto end; 4483 } 4484 } 4485 else 4486 { 4487 switch (shift_type) 4488 { 4489 case SHIFT_ASHIFT: 4490 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0"; 4491 info->cc_special = CC_SET_ZNV; 4492 goto end; 4493 case SHIFT_LSHIFTRT: 4494 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0"; 4495 info->cc_special = CC_SET_ZNV; 4496 goto end; 4497 case SHIFT_ASHIFTRT: 4498 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0"; 4499 info->cc_special = CC_SET_ZNV; 4500 goto end; 4501 } 4502 } 4503 } 4504 gcc_unreachable (); 4505 4506 default: 4507 gcc_unreachable (); 4508 } 4509 4510 end: 4511 if (!TARGET_H8300S) 4512 info->shift2 = NULL; 4513 } 4514 4515 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be 4516 needed for some shift with COUNT and MODE. Return 0 otherwise. */ 4517 4518 int 4519 h8300_shift_needs_scratch_p (int count, machine_mode mode) 4520 { 4521 enum h8_cpu cpu; 4522 int a, lr, ar; 4523 4524 if (GET_MODE_BITSIZE (mode) <= count) 4525 return 1; 4526 4527 /* Find out the target CPU. */ 4528 if (TARGET_H8300) 4529 cpu = H8_300; 4530 else if (TARGET_H8300S) 4531 cpu = H8_S; 4532 else 4533 cpu = H8_300H; 4534 4535 /* Find the shift algorithm. */ 4536 switch (mode) 4537 { 4538 case E_QImode: 4539 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count]; 4540 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count]; 4541 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count]; 4542 break; 4543 4544 case E_HImode: 4545 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count]; 4546 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count]; 4547 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count]; 4548 break; 4549 4550 case E_SImode: 4551 a = shift_alg_si[cpu][SHIFT_ASHIFT][count]; 4552 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count]; 4553 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count]; 4554 break; 4555 4556 default: 4557 gcc_unreachable (); 4558 } 4559 4560 /* On H8/300H, count == 8 uses a scratch register. */ 4561 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP 4562 || (TARGET_H8300H && mode == SImode && count == 8)); 4563 } 4564 4565 /* Output the assembler code for doing shifts. */ 4566 4567 const char * 4568 output_a_shift (rtx *operands) 4569 { 4570 static int loopend_lab; 4571 rtx shift = operands[3]; 4572 machine_mode mode = GET_MODE (shift); 4573 enum rtx_code code = GET_CODE (shift); 4574 enum shift_type shift_type; 4575 enum shift_mode shift_mode; 4576 struct shift_info info; 4577 int n; 4578 4579 loopend_lab++; 4580 4581 switch (mode) 4582 { 4583 case E_QImode: 4584 shift_mode = QIshift; 4585 break; 4586 case E_HImode: 4587 shift_mode = HIshift; 4588 break; 4589 case E_SImode: 4590 shift_mode = SIshift; 4591 break; 4592 default: 4593 gcc_unreachable (); 4594 } 4595 4596 switch (code) 4597 { 4598 case ASHIFTRT: 4599 shift_type = SHIFT_ASHIFTRT; 4600 break; 4601 case LSHIFTRT: 4602 shift_type = SHIFT_LSHIFTRT; 4603 break; 4604 case ASHIFT: 4605 shift_type = SHIFT_ASHIFT; 4606 break; 4607 default: 4608 gcc_unreachable (); 4609 } 4610 4611 /* This case must be taken care of by one of the two splitters 4612 that convert a variable shift into a loop. */ 4613 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4614 4615 n = INTVAL (operands[2]); 4616 4617 /* If the count is negative, make it 0. */ 4618 if (n < 0) 4619 n = 0; 4620 /* If the count is too big, truncate it. 4621 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4622 do the intuitive thing. */ 4623 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4624 n = GET_MODE_BITSIZE (mode); 4625 4626 get_shift_alg (shift_type, shift_mode, n, &info); 4627 4628 switch (info.alg) 4629 { 4630 case SHIFT_SPECIAL: 4631 output_asm_insn (info.special, operands); 4632 /* Fall through. */ 4633 4634 case SHIFT_INLINE: 4635 n = info.remainder; 4636 4637 /* Emit two bit shifts first. */ 4638 if (info.shift2 != NULL) 4639 { 4640 for (; n > 1; n -= 2) 4641 output_asm_insn (info.shift2, operands); 4642 } 4643 4644 /* Now emit one bit shifts for any residual. */ 4645 for (; n > 0; n--) 4646 output_asm_insn (info.shift1, operands); 4647 return ""; 4648 4649 case SHIFT_ROT_AND: 4650 { 4651 int m = GET_MODE_BITSIZE (mode) - n; 4652 const int mask = (shift_type == SHIFT_ASHIFT 4653 ? ((1 << m) - 1) << n 4654 : (1 << m) - 1); 4655 char insn_buf[200]; 4656 4657 /* Not all possibilities of rotate are supported. They shouldn't 4658 be generated, but let's watch for 'em. */ 4659 gcc_assert (info.shift1); 4660 4661 /* Emit two bit rotates first. */ 4662 if (info.shift2 != NULL) 4663 { 4664 for (; m > 1; m -= 2) 4665 output_asm_insn (info.shift2, operands); 4666 } 4667 4668 /* Now single bit rotates for any residual. */ 4669 for (; m > 0; m--) 4670 output_asm_insn (info.shift1, operands); 4671 4672 /* Now mask off the high bits. */ 4673 switch (mode) 4674 { 4675 case E_QImode: 4676 sprintf (insn_buf, "and\t#%d,%%X0", mask); 4677 break; 4678 4679 case E_HImode: 4680 gcc_assert (TARGET_H8300H || TARGET_H8300S); 4681 sprintf (insn_buf, "and.w\t#%d,%%T0", mask); 4682 break; 4683 4684 default: 4685 gcc_unreachable (); 4686 } 4687 4688 output_asm_insn (insn_buf, operands); 4689 return ""; 4690 } 4691 4692 case SHIFT_LOOP: 4693 /* A loop to shift by a "large" constant value. 4694 If we have shift-by-2 insns, use them. */ 4695 if (info.shift2 != NULL) 4696 { 4697 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, 4698 names_big[REGNO (operands[4])]); 4699 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4700 output_asm_insn (info.shift2, operands); 4701 output_asm_insn ("add #0xff,%X4", operands); 4702 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4703 if (n % 2) 4704 output_asm_insn (info.shift1, operands); 4705 } 4706 else 4707 { 4708 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, 4709 names_big[REGNO (operands[4])]); 4710 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4711 output_asm_insn (info.shift1, operands); 4712 output_asm_insn ("add #0xff,%X4", operands); 4713 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4714 } 4715 return ""; 4716 4717 default: 4718 gcc_unreachable (); 4719 } 4720 } 4721 4722 /* Count the number of assembly instructions in a string TEMPL. */ 4723 4724 static unsigned int 4725 h8300_asm_insn_count (const char *templ) 4726 { 4727 unsigned int count = 1; 4728 4729 for (; *templ; templ++) 4730 if (*templ == '\n') 4731 count++; 4732 4733 return count; 4734 } 4735 4736 /* Compute the length of a shift insn. */ 4737 4738 unsigned int 4739 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands) 4740 { 4741 rtx shift = operands[3]; 4742 machine_mode mode = GET_MODE (shift); 4743 enum rtx_code code = GET_CODE (shift); 4744 enum shift_type shift_type; 4745 enum shift_mode shift_mode; 4746 struct shift_info info; 4747 unsigned int wlength = 0; 4748 4749 switch (mode) 4750 { 4751 case E_QImode: 4752 shift_mode = QIshift; 4753 break; 4754 case E_HImode: 4755 shift_mode = HIshift; 4756 break; 4757 case E_SImode: 4758 shift_mode = SIshift; 4759 break; 4760 default: 4761 gcc_unreachable (); 4762 } 4763 4764 switch (code) 4765 { 4766 case ASHIFTRT: 4767 shift_type = SHIFT_ASHIFTRT; 4768 break; 4769 case LSHIFTRT: 4770 shift_type = SHIFT_LSHIFTRT; 4771 break; 4772 case ASHIFT: 4773 shift_type = SHIFT_ASHIFT; 4774 break; 4775 default: 4776 gcc_unreachable (); 4777 } 4778 4779 if (GET_CODE (operands[2]) != CONST_INT) 4780 { 4781 /* Get the assembler code to do one shift. */ 4782 get_shift_alg (shift_type, shift_mode, 1, &info); 4783 4784 return (4 + h8300_asm_insn_count (info.shift1)) * 2; 4785 } 4786 else 4787 { 4788 int n = INTVAL (operands[2]); 4789 4790 /* If the count is negative, make it 0. */ 4791 if (n < 0) 4792 n = 0; 4793 /* If the count is too big, truncate it. 4794 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4795 do the intuitive thing. */ 4796 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4797 n = GET_MODE_BITSIZE (mode); 4798 4799 get_shift_alg (shift_type, shift_mode, n, &info); 4800 4801 switch (info.alg) 4802 { 4803 case SHIFT_SPECIAL: 4804 wlength += h8300_asm_insn_count (info.special); 4805 4806 /* Every assembly instruction used in SHIFT_SPECIAL case 4807 takes 2 bytes except xor.l, which takes 4 bytes, so if we 4808 see xor.l, we just pretend that xor.l counts as two insns 4809 so that the insn length will be computed correctly. */ 4810 if (strstr (info.special, "xor.l") != NULL) 4811 wlength++; 4812 4813 /* Fall through. */ 4814 4815 case SHIFT_INLINE: 4816 n = info.remainder; 4817 4818 if (info.shift2 != NULL) 4819 { 4820 wlength += h8300_asm_insn_count (info.shift2) * (n / 2); 4821 n = n % 2; 4822 } 4823 4824 wlength += h8300_asm_insn_count (info.shift1) * n; 4825 4826 return 2 * wlength; 4827 4828 case SHIFT_ROT_AND: 4829 { 4830 int m = GET_MODE_BITSIZE (mode) - n; 4831 4832 /* Not all possibilities of rotate are supported. They shouldn't 4833 be generated, but let's watch for 'em. */ 4834 gcc_assert (info.shift1); 4835 4836 if (info.shift2 != NULL) 4837 { 4838 wlength += h8300_asm_insn_count (info.shift2) * (m / 2); 4839 m = m % 2; 4840 } 4841 4842 wlength += h8300_asm_insn_count (info.shift1) * m; 4843 4844 /* Now mask off the high bits. */ 4845 switch (mode) 4846 { 4847 case E_QImode: 4848 wlength += 1; 4849 break; 4850 case E_HImode: 4851 wlength += 2; 4852 break; 4853 case E_SImode: 4854 gcc_assert (!TARGET_H8300); 4855 wlength += 3; 4856 break; 4857 default: 4858 gcc_unreachable (); 4859 } 4860 return 2 * wlength; 4861 } 4862 4863 case SHIFT_LOOP: 4864 /* A loop to shift by a "large" constant value. 4865 If we have shift-by-2 insns, use them. */ 4866 if (info.shift2 != NULL) 4867 { 4868 wlength += 3 + h8300_asm_insn_count (info.shift2); 4869 if (n % 2) 4870 wlength += h8300_asm_insn_count (info.shift1); 4871 } 4872 else 4873 { 4874 wlength += 3 + h8300_asm_insn_count (info.shift1); 4875 } 4876 return 2 * wlength; 4877 4878 default: 4879 gcc_unreachable (); 4880 } 4881 } 4882 } 4883 4884 /* Compute which flag bits are valid after a shift insn. */ 4885 4886 enum attr_cc 4887 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands) 4888 { 4889 rtx shift = operands[3]; 4890 machine_mode mode = GET_MODE (shift); 4891 enum rtx_code code = GET_CODE (shift); 4892 enum shift_type shift_type; 4893 enum shift_mode shift_mode; 4894 struct shift_info info; 4895 int n; 4896 4897 switch (mode) 4898 { 4899 case E_QImode: 4900 shift_mode = QIshift; 4901 break; 4902 case E_HImode: 4903 shift_mode = HIshift; 4904 break; 4905 case E_SImode: 4906 shift_mode = SIshift; 4907 break; 4908 default: 4909 gcc_unreachable (); 4910 } 4911 4912 switch (code) 4913 { 4914 case ASHIFTRT: 4915 shift_type = SHIFT_ASHIFTRT; 4916 break; 4917 case LSHIFTRT: 4918 shift_type = SHIFT_LSHIFTRT; 4919 break; 4920 case ASHIFT: 4921 shift_type = SHIFT_ASHIFT; 4922 break; 4923 default: 4924 gcc_unreachable (); 4925 } 4926 4927 /* This case must be taken care of by one of the two splitters 4928 that convert a variable shift into a loop. */ 4929 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4930 4931 n = INTVAL (operands[2]); 4932 4933 /* If the count is negative, make it 0. */ 4934 if (n < 0) 4935 n = 0; 4936 /* If the count is too big, truncate it. 4937 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4938 do the intuitive thing. */ 4939 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4940 n = GET_MODE_BITSIZE (mode); 4941 4942 get_shift_alg (shift_type, shift_mode, n, &info); 4943 4944 switch (info.alg) 4945 { 4946 case SHIFT_SPECIAL: 4947 if (info.remainder == 0) 4948 return info.cc_special; 4949 4950 /* Fall through. */ 4951 4952 case SHIFT_INLINE: 4953 return info.cc_inline; 4954 4955 case SHIFT_ROT_AND: 4956 /* This case always ends with an and instruction. */ 4957 return CC_SET_ZNV; 4958 4959 case SHIFT_LOOP: 4960 /* A loop to shift by a "large" constant value. 4961 If we have shift-by-2 insns, use them. */ 4962 if (info.shift2 != NULL) 4963 { 4964 if (n % 2) 4965 return info.cc_inline; 4966 } 4967 return CC_CLOBBER; 4968 4969 default: 4970 gcc_unreachable (); 4971 } 4972 } 4973 4974 /* A rotation by a non-constant will cause a loop to be generated, in 4975 which a rotation by one bit is used. A rotation by a constant, 4976 including the one in the loop, will be taken care of by 4977 output_a_rotate () at the insn emit time. */ 4978 4979 int 4980 expand_a_rotate (rtx operands[]) 4981 { 4982 rtx dst = operands[0]; 4983 rtx src = operands[1]; 4984 rtx rotate_amount = operands[2]; 4985 machine_mode mode = GET_MODE (dst); 4986 4987 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY) 4988 return false; 4989 4990 /* We rotate in place. */ 4991 emit_move_insn (dst, src); 4992 4993 if (GET_CODE (rotate_amount) != CONST_INT) 4994 { 4995 rtx counter = gen_reg_rtx (QImode); 4996 rtx_code_label *start_label = gen_label_rtx (); 4997 rtx_code_label *end_label = gen_label_rtx (); 4998 4999 /* If the rotate amount is less than or equal to 0, 5000 we go out of the loop. */ 5001 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX, 5002 QImode, 0, end_label); 5003 5004 /* Initialize the loop counter. */ 5005 emit_move_insn (counter, rotate_amount); 5006 5007 emit_label (start_label); 5008 5009 /* Rotate by one bit. */ 5010 switch (mode) 5011 { 5012 case E_QImode: 5013 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx)); 5014 break; 5015 case E_HImode: 5016 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx)); 5017 break; 5018 case E_SImode: 5019 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx)); 5020 break; 5021 default: 5022 gcc_unreachable (); 5023 } 5024 5025 /* Decrement the counter by 1. */ 5026 emit_insn (gen_addqi3 (counter, counter, constm1_rtx)); 5027 5028 /* If the loop counter is nonzero, we go back to the beginning 5029 of the loop. */ 5030 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1, 5031 start_label); 5032 5033 emit_label (end_label); 5034 } 5035 else 5036 { 5037 /* Rotate by AMOUNT bits. */ 5038 switch (mode) 5039 { 5040 case E_QImode: 5041 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount)); 5042 break; 5043 case E_HImode: 5044 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount)); 5045 break; 5046 case E_SImode: 5047 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount)); 5048 break; 5049 default: 5050 gcc_unreachable (); 5051 } 5052 } 5053 5054 return 1; 5055 } 5056 5057 /* Output a rotate insn. */ 5058 5059 const char * 5060 output_a_rotate (enum rtx_code code, rtx *operands) 5061 { 5062 rtx dst = operands[0]; 5063 rtx rotate_amount = operands[2]; 5064 enum shift_mode rotate_mode; 5065 enum shift_type rotate_type; 5066 const char *insn_buf; 5067 int bits; 5068 int amount; 5069 machine_mode mode = GET_MODE (dst); 5070 5071 gcc_assert (GET_CODE (rotate_amount) == CONST_INT); 5072 5073 switch (mode) 5074 { 5075 case E_QImode: 5076 rotate_mode = QIshift; 5077 break; 5078 case E_HImode: 5079 rotate_mode = HIshift; 5080 break; 5081 case E_SImode: 5082 rotate_mode = SIshift; 5083 break; 5084 default: 5085 gcc_unreachable (); 5086 } 5087 5088 switch (code) 5089 { 5090 case ROTATERT: 5091 rotate_type = SHIFT_ASHIFT; 5092 break; 5093 case ROTATE: 5094 rotate_type = SHIFT_LSHIFTRT; 5095 break; 5096 default: 5097 gcc_unreachable (); 5098 } 5099 5100 amount = INTVAL (rotate_amount); 5101 5102 /* Clean up AMOUNT. */ 5103 if (amount < 0) 5104 amount = 0; 5105 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 5106 amount = GET_MODE_BITSIZE (mode); 5107 5108 /* Determine the faster direction. After this phase, amount will be 5109 at most a half of GET_MODE_BITSIZE (mode). */ 5110 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 5111 { 5112 /* Flip the direction. */ 5113 amount = GET_MODE_BITSIZE (mode) - amount; 5114 rotate_type = 5115 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 5116 } 5117 5118 /* See if a byte swap (in HImode) or a word swap (in SImode) can 5119 boost up the rotation. */ 5120 if ((mode == HImode && TARGET_H8300 && amount >= 5) 5121 || (mode == HImode && TARGET_H8300H && amount >= 6) 5122 || (mode == HImode && TARGET_H8300S && amount == 8) 5123 || (mode == SImode && TARGET_H8300H && amount >= 10) 5124 || (mode == SImode && TARGET_H8300S && amount >= 13)) 5125 { 5126 switch (mode) 5127 { 5128 case E_HImode: 5129 /* This code works on any family. */ 5130 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0"; 5131 output_asm_insn (insn_buf, operands); 5132 break; 5133 5134 case E_SImode: 5135 /* This code works on the H8/300H and H8S. */ 5136 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0"; 5137 output_asm_insn (insn_buf, operands); 5138 break; 5139 5140 default: 5141 gcc_unreachable (); 5142 } 5143 5144 /* Adjust AMOUNT and flip the direction. */ 5145 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 5146 rotate_type = 5147 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 5148 } 5149 5150 /* Output rotate insns. */ 5151 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2) 5152 { 5153 if (bits == 2) 5154 insn_buf = rotate_two[rotate_type][rotate_mode]; 5155 else 5156 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode]; 5157 5158 for (; amount >= bits; amount -= bits) 5159 output_asm_insn (insn_buf, operands); 5160 } 5161 5162 return ""; 5163 } 5164 5165 /* Compute the length of a rotate insn. */ 5166 5167 unsigned int 5168 compute_a_rotate_length (rtx *operands) 5169 { 5170 rtx src = operands[1]; 5171 rtx amount_rtx = operands[2]; 5172 machine_mode mode = GET_MODE (src); 5173 int amount; 5174 unsigned int length = 0; 5175 5176 gcc_assert (GET_CODE (amount_rtx) == CONST_INT); 5177 5178 amount = INTVAL (amount_rtx); 5179 5180 /* Clean up AMOUNT. */ 5181 if (amount < 0) 5182 amount = 0; 5183 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 5184 amount = GET_MODE_BITSIZE (mode); 5185 5186 /* Determine the faster direction. After this phase, amount 5187 will be at most a half of GET_MODE_BITSIZE (mode). */ 5188 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 5189 /* Flip the direction. */ 5190 amount = GET_MODE_BITSIZE (mode) - amount; 5191 5192 /* See if a byte swap (in HImode) or a word swap (in SImode) can 5193 boost up the rotation. */ 5194 if ((mode == HImode && TARGET_H8300 && amount >= 5) 5195 || (mode == HImode && TARGET_H8300H && amount >= 6) 5196 || (mode == HImode && TARGET_H8300S && amount == 8) 5197 || (mode == SImode && TARGET_H8300H && amount >= 10) 5198 || (mode == SImode && TARGET_H8300S && amount >= 13)) 5199 { 5200 /* Adjust AMOUNT and flip the direction. */ 5201 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 5202 length += 6; 5203 } 5204 5205 /* We use 2-bit rotations on the H8S. */ 5206 if (TARGET_H8300S) 5207 amount = amount / 2 + amount % 2; 5208 5209 /* The H8/300 uses three insns to rotate one bit, taking 6 5210 length. */ 5211 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2); 5212 5213 return length; 5214 } 5215 5216 /* Fix the operands of a gen_xxx so that it could become a bit 5217 operating insn. */ 5218 5219 int 5220 fix_bit_operand (rtx *operands, enum rtx_code code) 5221 { 5222 /* The bit_operand predicate accepts any memory during RTL generation, but 5223 only 'U' memory afterwards, so if this is a MEM operand, we must force 5224 it to be valid for 'U' by reloading the address. */ 5225 5226 if (code == AND 5227 ? single_zero_operand (operands[2], QImode) 5228 : single_one_operand (operands[2], QImode)) 5229 { 5230 /* OK to have a memory dest. */ 5231 if (GET_CODE (operands[0]) == MEM 5232 && !satisfies_constraint_U (operands[0])) 5233 { 5234 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]), 5235 copy_to_mode_reg (Pmode, 5236 XEXP (operands[0], 0))); 5237 MEM_COPY_ATTRIBUTES (mem, operands[0]); 5238 operands[0] = mem; 5239 } 5240 5241 if (GET_CODE (operands[1]) == MEM 5242 && !satisfies_constraint_U (operands[1])) 5243 { 5244 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]), 5245 copy_to_mode_reg (Pmode, 5246 XEXP (operands[1], 0))); 5247 MEM_COPY_ATTRIBUTES (mem, operands[0]); 5248 operands[1] = mem; 5249 } 5250 return 0; 5251 } 5252 5253 /* Dest and src op must be register. */ 5254 5255 operands[1] = force_reg (QImode, operands[1]); 5256 { 5257 rtx res = gen_reg_rtx (QImode); 5258 switch (code) 5259 { 5260 case AND: 5261 emit_insn (gen_andqi3_1 (res, operands[1], operands[2])); 5262 break; 5263 case IOR: 5264 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2])); 5265 break; 5266 case XOR: 5267 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2])); 5268 break; 5269 default: 5270 gcc_unreachable (); 5271 } 5272 emit_insn (gen_movqi (operands[0], res)); 5273 } 5274 return 1; 5275 } 5276 5277 /* Return nonzero if FUNC is an interrupt function as specified 5278 by the "interrupt" attribute. */ 5279 5280 static int 5281 h8300_interrupt_function_p (tree func) 5282 { 5283 tree a; 5284 5285 if (TREE_CODE (func) != FUNCTION_DECL) 5286 return 0; 5287 5288 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); 5289 return a != NULL_TREE; 5290 } 5291 5292 /* Return nonzero if FUNC is a saveall function as specified by the 5293 "saveall" attribute. */ 5294 5295 static int 5296 h8300_saveall_function_p (tree func) 5297 { 5298 tree a; 5299 5300 if (TREE_CODE (func) != FUNCTION_DECL) 5301 return 0; 5302 5303 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func)); 5304 return a != NULL_TREE; 5305 } 5306 5307 /* Return nonzero if FUNC is an OS_Task function as specified 5308 by the "OS_Task" attribute. */ 5309 5310 static int 5311 h8300_os_task_function_p (tree func) 5312 { 5313 tree a; 5314 5315 if (TREE_CODE (func) != FUNCTION_DECL) 5316 return 0; 5317 5318 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func)); 5319 return a != NULL_TREE; 5320 } 5321 5322 /* Return nonzero if FUNC is a monitor function as specified 5323 by the "monitor" attribute. */ 5324 5325 static int 5326 h8300_monitor_function_p (tree func) 5327 { 5328 tree a; 5329 5330 if (TREE_CODE (func) != FUNCTION_DECL) 5331 return 0; 5332 5333 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func)); 5334 return a != NULL_TREE; 5335 } 5336 5337 /* Return nonzero if FUNC is a function that should be called 5338 through the function vector. */ 5339 5340 int 5341 h8300_funcvec_function_p (tree func) 5342 { 5343 tree a; 5344 5345 if (TREE_CODE (func) != FUNCTION_DECL) 5346 return 0; 5347 5348 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func)); 5349 return a != NULL_TREE; 5350 } 5351 5352 /* Return nonzero if DECL is a variable that's in the eight bit 5353 data area. */ 5354 5355 int 5356 h8300_eightbit_data_p (tree decl) 5357 { 5358 tree a; 5359 5360 if (TREE_CODE (decl) != VAR_DECL) 5361 return 0; 5362 5363 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl)); 5364 return a != NULL_TREE; 5365 } 5366 5367 /* Return nonzero if DECL is a variable that's in the tiny 5368 data area. */ 5369 5370 int 5371 h8300_tiny_data_p (tree decl) 5372 { 5373 tree a; 5374 5375 if (TREE_CODE (decl) != VAR_DECL) 5376 return 0; 5377 5378 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl)); 5379 return a != NULL_TREE; 5380 } 5381 5382 /* Generate an 'interrupt_handler' attribute for decls. We convert 5383 all the pragmas to corresponding attributes. */ 5384 5385 static void 5386 h8300_insert_attributes (tree node, tree *attributes) 5387 { 5388 if (TREE_CODE (node) == FUNCTION_DECL) 5389 { 5390 if (pragma_interrupt) 5391 { 5392 pragma_interrupt = 0; 5393 5394 /* Add an 'interrupt_handler' attribute. */ 5395 *attributes = tree_cons (get_identifier ("interrupt_handler"), 5396 NULL, *attributes); 5397 } 5398 5399 if (pragma_saveall) 5400 { 5401 pragma_saveall = 0; 5402 5403 /* Add an 'saveall' attribute. */ 5404 *attributes = tree_cons (get_identifier ("saveall"), 5405 NULL, *attributes); 5406 } 5407 } 5408 } 5409 5410 /* Supported attributes: 5411 5412 interrupt_handler: output a prologue and epilogue suitable for an 5413 interrupt handler. 5414 5415 saveall: output a prologue and epilogue that saves and restores 5416 all registers except the stack pointer. 5417 5418 function_vector: This function should be called through the 5419 function vector. 5420 5421 eightbit_data: This variable lives in the 8-bit data area and can 5422 be referenced with 8-bit absolute memory addresses. 5423 5424 tiny_data: This variable lives in the tiny data area and can be 5425 referenced with 16-bit absolute memory references. */ 5426 5427 static const struct attribute_spec h8300_attribute_table[] = 5428 { 5429 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, 5430 affects_type_identity, handler, exclude } */ 5431 { "interrupt_handler", 0, 0, true, false, false, false, 5432 h8300_handle_fndecl_attribute, NULL }, 5433 { "saveall", 0, 0, true, false, false, false, 5434 h8300_handle_fndecl_attribute, NULL }, 5435 { "OS_Task", 0, 0, true, false, false, false, 5436 h8300_handle_fndecl_attribute, NULL }, 5437 { "monitor", 0, 0, true, false, false, false, 5438 h8300_handle_fndecl_attribute, NULL }, 5439 { "function_vector", 0, 0, true, false, false, false, 5440 h8300_handle_fndecl_attribute, NULL }, 5441 { "eightbit_data", 0, 0, true, false, false, false, 5442 h8300_handle_eightbit_data_attribute, NULL }, 5443 { "tiny_data", 0, 0, true, false, false, false, 5444 h8300_handle_tiny_data_attribute, NULL }, 5445 { NULL, 0, 0, false, false, false, false, NULL, NULL } 5446 }; 5447 5448 5449 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in 5450 struct attribute_spec.handler. */ 5451 static tree 5452 h8300_handle_fndecl_attribute (tree *node, tree name, 5453 tree args ATTRIBUTE_UNUSED, 5454 int flags ATTRIBUTE_UNUSED, 5455 bool *no_add_attrs) 5456 { 5457 if (TREE_CODE (*node) != FUNCTION_DECL) 5458 { 5459 warning (OPT_Wattributes, "%qE attribute only applies to functions", 5460 name); 5461 *no_add_attrs = true; 5462 } 5463 5464 return NULL_TREE; 5465 } 5466 5467 /* Handle an "eightbit_data" attribute; arguments as in 5468 struct attribute_spec.handler. */ 5469 static tree 5470 h8300_handle_eightbit_data_attribute (tree *node, tree name, 5471 tree args ATTRIBUTE_UNUSED, 5472 int flags ATTRIBUTE_UNUSED, 5473 bool *no_add_attrs) 5474 { 5475 tree decl = *node; 5476 5477 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 5478 { 5479 set_decl_section_name (decl, ".eight"); 5480 } 5481 else 5482 { 5483 warning (OPT_Wattributes, "%qE attribute ignored", 5484 name); 5485 *no_add_attrs = true; 5486 } 5487 5488 return NULL_TREE; 5489 } 5490 5491 /* Handle an "tiny_data" attribute; arguments as in 5492 struct attribute_spec.handler. */ 5493 static tree 5494 h8300_handle_tiny_data_attribute (tree *node, tree name, 5495 tree args ATTRIBUTE_UNUSED, 5496 int flags ATTRIBUTE_UNUSED, 5497 bool *no_add_attrs) 5498 { 5499 tree decl = *node; 5500 5501 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 5502 { 5503 set_decl_section_name (decl, ".tiny"); 5504 } 5505 else 5506 { 5507 warning (OPT_Wattributes, "%qE attribute ignored", 5508 name); 5509 *no_add_attrs = true; 5510 } 5511 5512 return NULL_TREE; 5513 } 5514 5515 /* Mark function vectors, and various small data objects. */ 5516 5517 static void 5518 h8300_encode_section_info (tree decl, rtx rtl, int first) 5519 { 5520 int extra_flags = 0; 5521 5522 default_encode_section_info (decl, rtl, first); 5523 5524 if (TREE_CODE (decl) == FUNCTION_DECL 5525 && h8300_funcvec_function_p (decl)) 5526 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION; 5527 else if (TREE_CODE (decl) == VAR_DECL 5528 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) 5529 { 5530 if (h8300_eightbit_data_p (decl)) 5531 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA; 5532 else if (first && h8300_tiny_data_p (decl)) 5533 extra_flags = SYMBOL_FLAG_TINY_DATA; 5534 } 5535 5536 if (extra_flags) 5537 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; 5538 } 5539 5540 /* Output a single-bit extraction. */ 5541 5542 const char * 5543 output_simode_bld (int bild, rtx operands[]) 5544 { 5545 if (TARGET_H8300) 5546 { 5547 /* Clear the destination register. */ 5548 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); 5549 5550 /* Now output the bit load or bit inverse load, and store it in 5551 the destination. */ 5552 if (bild) 5553 output_asm_insn ("bild\t%Z2,%Y1", operands); 5554 else 5555 output_asm_insn ("bld\t%Z2,%Y1", operands); 5556 5557 output_asm_insn ("bst\t#0,%w0", operands); 5558 } 5559 else 5560 { 5561 /* Determine if we can clear the destination first. */ 5562 int clear_first = (REG_P (operands[0]) && REG_P (operands[1]) 5563 && REGNO (operands[0]) != REGNO (operands[1])); 5564 5565 if (clear_first) 5566 output_asm_insn ("sub.l\t%S0,%S0", operands); 5567 5568 /* Output the bit load or bit inverse load. */ 5569 if (bild) 5570 output_asm_insn ("bild\t%Z2,%Y1", operands); 5571 else 5572 output_asm_insn ("bld\t%Z2,%Y1", operands); 5573 5574 if (!clear_first) 5575 output_asm_insn ("xor.l\t%S0,%S0", operands); 5576 5577 /* Perform the bit store. */ 5578 output_asm_insn ("rotxl.l\t%S0", operands); 5579 } 5580 5581 /* All done. */ 5582 return ""; 5583 } 5584 5585 /* Delayed-branch scheduling is more effective if we have some idea 5586 how long each instruction will be. Use a shorten_branches pass 5587 to get an initial estimate. */ 5588 5589 static void 5590 h8300_reorg (void) 5591 { 5592 if (flag_delayed_branch) 5593 shorten_branches (get_insns ()); 5594 } 5595 5596 #ifndef OBJECT_FORMAT_ELF 5597 static void 5598 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED, 5599 tree decl) 5600 { 5601 /* ??? Perhaps we should be using default_coff_asm_named_section. */ 5602 fprintf (asm_out_file, "\t.section %s\n", name); 5603 } 5604 #endif /* ! OBJECT_FORMAT_ELF */ 5605 5606 /* Nonzero if X is a constant address suitable as an 8-bit absolute, 5607 which is a special case of the 'R' operand. */ 5608 5609 int 5610 h8300_eightbit_constant_address_p (rtx x) 5611 { 5612 /* The ranges of the 8-bit area. */ 5613 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode); 5614 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode); 5615 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode); 5616 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode); 5617 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode); 5618 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode); 5619 5620 unsigned HOST_WIDE_INT addr; 5621 5622 /* We accept symbols declared with eightbit_data. */ 5623 if (GET_CODE (x) == SYMBOL_REF) 5624 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0; 5625 5626 if (GET_CODE (x) == CONST 5627 && GET_CODE (XEXP (x, 0)) == PLUS 5628 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 5629 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0) 5630 return 1; 5631 5632 if (GET_CODE (x) != CONST_INT) 5633 return 0; 5634 5635 addr = INTVAL (x); 5636 5637 return (0 5638 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2)) 5639 || (TARGET_H8300H && IN_RANGE (addr, h1, h2)) 5640 || (TARGET_H8300S && IN_RANGE (addr, s1, s2))); 5641 } 5642 5643 /* Nonzero if X is a constant address suitable as an 16-bit absolute 5644 on H8/300H and H8S. */ 5645 5646 int 5647 h8300_tiny_constant_address_p (rtx x) 5648 { 5649 /* The ranges of the 16-bit area. */ 5650 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode); 5651 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode); 5652 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode); 5653 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode); 5654 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode); 5655 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode); 5656 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode); 5657 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode); 5658 5659 unsigned HOST_WIDE_INT addr; 5660 5661 switch (GET_CODE (x)) 5662 { 5663 case SYMBOL_REF: 5664 /* In the normal mode, any symbol fits in the 16-bit absolute 5665 address range. We also accept symbols declared with 5666 tiny_data. */ 5667 return (TARGET_NORMAL_MODE 5668 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0); 5669 5670 case CONST_INT: 5671 addr = INTVAL (x); 5672 return (TARGET_NORMAL_MODE 5673 || (TARGET_H8300H 5674 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4))) 5675 || (TARGET_H8300S 5676 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4)))); 5677 5678 case CONST: 5679 return TARGET_NORMAL_MODE; 5680 5681 default: 5682 return 0; 5683 } 5684 5685 } 5686 5687 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory 5688 locations that can be accessed as a 16-bit word. */ 5689 5690 int 5691 byte_accesses_mergeable_p (rtx addr1, rtx addr2) 5692 { 5693 HOST_WIDE_INT offset1, offset2; 5694 rtx reg1, reg2; 5695 5696 if (REG_P (addr1)) 5697 { 5698 reg1 = addr1; 5699 offset1 = 0; 5700 } 5701 else if (GET_CODE (addr1) == PLUS 5702 && REG_P (XEXP (addr1, 0)) 5703 && GET_CODE (XEXP (addr1, 1)) == CONST_INT) 5704 { 5705 reg1 = XEXP (addr1, 0); 5706 offset1 = INTVAL (XEXP (addr1, 1)); 5707 } 5708 else 5709 return 0; 5710 5711 if (REG_P (addr2)) 5712 { 5713 reg2 = addr2; 5714 offset2 = 0; 5715 } 5716 else if (GET_CODE (addr2) == PLUS 5717 && REG_P (XEXP (addr2, 0)) 5718 && GET_CODE (XEXP (addr2, 1)) == CONST_INT) 5719 { 5720 reg2 = XEXP (addr2, 0); 5721 offset2 = INTVAL (XEXP (addr2, 1)); 5722 } 5723 else 5724 return 0; 5725 5726 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx) 5727 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx)) 5728 && offset1 % 2 == 0 5729 && offset1 + 1 == offset2) 5730 return 1; 5731 5732 return 0; 5733 } 5734 5735 /* Return nonzero if we have the same comparison insn as I3 two insns 5736 before I3. I3 is assumed to be a comparison insn. */ 5737 5738 int 5739 same_cmp_preceding_p (rtx_insn *i3) 5740 { 5741 rtx_insn *i1, *i2; 5742 5743 /* Make sure we have a sequence of three insns. */ 5744 i2 = prev_nonnote_insn (i3); 5745 if (i2 == NULL) 5746 return 0; 5747 i1 = prev_nonnote_insn (i2); 5748 if (i1 == NULL) 5749 return 0; 5750 5751 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5752 && any_condjump_p (i2) && onlyjump_p (i2)); 5753 } 5754 5755 /* Return nonzero if we have the same comparison insn as I1 two insns 5756 after I1. I1 is assumed to be a comparison insn. */ 5757 5758 int 5759 same_cmp_following_p (rtx_insn *i1) 5760 { 5761 rtx_insn *i2, *i3; 5762 5763 /* Make sure we have a sequence of three insns. */ 5764 i2 = next_nonnote_insn (i1); 5765 if (i2 == NULL) 5766 return 0; 5767 i3 = next_nonnote_insn (i2); 5768 if (i3 == NULL) 5769 return 0; 5770 5771 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5772 && any_condjump_p (i2) && onlyjump_p (i2)); 5773 } 5774 5775 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes 5776 (or pops) N registers. OPERANDS are assumed to be an array of 5777 registers. */ 5778 5779 int 5780 h8300_regs_ok_for_stm (int n, rtx operands[]) 5781 { 5782 switch (n) 5783 { 5784 case 2: 5785 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) 5786 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) 5787 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5)); 5788 case 3: 5789 return ((REGNO (operands[0]) == 0 5790 && REGNO (operands[1]) == 1 5791 && REGNO (operands[2]) == 2) 5792 || (REGNO (operands[0]) == 4 5793 && REGNO (operands[1]) == 5 5794 && REGNO (operands[2]) == 6)); 5795 5796 case 4: 5797 return (REGNO (operands[0]) == 0 5798 && REGNO (operands[1]) == 1 5799 && REGNO (operands[2]) == 2 5800 && REGNO (operands[3]) == 3); 5801 default: 5802 gcc_unreachable (); 5803 } 5804 } 5805 5806 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ 5807 5808 int 5809 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, 5810 unsigned int new_reg) 5811 { 5812 /* Interrupt functions can only use registers that have already been 5813 saved by the prologue, even if they would normally be 5814 call-clobbered. */ 5815 5816 if (h8300_current_function_interrupt_function_p () 5817 && !df_regs_ever_live_p (new_reg)) 5818 return 0; 5819 5820 return 1; 5821 } 5822 5823 /* Returns true if register REGNO is safe to be allocated as a scratch 5824 register in the current function. */ 5825 5826 static bool 5827 h8300_hard_regno_scratch_ok (unsigned int regno) 5828 { 5829 if (h8300_current_function_interrupt_function_p () 5830 && ! WORD_REG_USED (regno)) 5831 return false; 5832 5833 return true; 5834 } 5835 5836 5837 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */ 5838 5839 static int 5840 h8300_rtx_ok_for_base_p (rtx x, int strict) 5841 { 5842 /* Strip off SUBREG if any. */ 5843 if (GET_CODE (x) == SUBREG) 5844 x = SUBREG_REG (x); 5845 5846 return (REG_P (x) 5847 && (strict 5848 ? REG_OK_FOR_BASE_STRICT_P (x) 5849 : REG_OK_FOR_BASE_NONSTRICT_P (x))); 5850 } 5851 5852 /* Return nozero if X is a legitimate address. On the H8/300, a 5853 legitimate address has the form REG, REG+CONSTANT_ADDRESS or 5854 CONSTANT_ADDRESS. */ 5855 5856 static bool 5857 h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict) 5858 { 5859 /* The register indirect addresses like @er0 is always valid. */ 5860 if (h8300_rtx_ok_for_base_p (x, strict)) 5861 return 1; 5862 5863 if (CONSTANT_ADDRESS_P (x)) 5864 return 1; 5865 5866 if (TARGET_H8300SX 5867 && ( GET_CODE (x) == PRE_INC 5868 || GET_CODE (x) == PRE_DEC 5869 || GET_CODE (x) == POST_INC 5870 || GET_CODE (x) == POST_DEC) 5871 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict)) 5872 return 1; 5873 5874 if (GET_CODE (x) == PLUS 5875 && CONSTANT_ADDRESS_P (XEXP (x, 1)) 5876 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0), 5877 mode, 0), strict)) 5878 return 1; 5879 5880 return 0; 5881 } 5882 5883 /* Implement TARGET_HARD_REGNO_MODE_OK. */ 5884 5885 static bool 5886 h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 5887 { 5888 if (TARGET_H8300) 5889 /* If an even reg, then anything goes. Otherwise the mode must be 5890 QI or HI. */ 5891 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode); 5892 else 5893 /* MAC register can only be of SImode. Otherwise, anything 5894 goes. */ 5895 return regno == MAC_REG ? mode == SImode : 1; 5896 } 5897 5898 /* Implement TARGET_MODES_TIEABLE_P. */ 5899 5900 static bool 5901 h8300_modes_tieable_p (machine_mode mode1, machine_mode mode2) 5902 { 5903 return (mode1 == mode2 5904 || ((mode1 == QImode 5905 || mode1 == HImode 5906 || ((TARGET_H8300H || TARGET_H8300S) && mode1 == SImode)) 5907 && (mode2 == QImode 5908 || mode2 == HImode 5909 || ((TARGET_H8300H || TARGET_H8300S) && mode2 == SImode)))); 5910 } 5911 5912 /* Helper function for the move patterns. Make sure a move is legitimate. */ 5913 5914 bool 5915 h8300_move_ok (rtx dest, rtx src) 5916 { 5917 rtx addr, other; 5918 5919 /* Validate that at least one operand is a register. */ 5920 if (MEM_P (dest)) 5921 { 5922 if (MEM_P (src) || CONSTANT_P (src)) 5923 return false; 5924 addr = XEXP (dest, 0); 5925 other = src; 5926 } 5927 else if (MEM_P (src)) 5928 { 5929 addr = XEXP (src, 0); 5930 other = dest; 5931 } 5932 else 5933 return true; 5934 5935 /* Validate that auto-inc doesn't affect OTHER. */ 5936 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC) 5937 return true; 5938 addr = XEXP (addr, 0); 5939 5940 if (addr == stack_pointer_rtx) 5941 return register_no_sp_elim_operand (other, VOIDmode); 5942 else 5943 return !reg_overlap_mentioned_p(other, addr); 5944 } 5945 5946 /* Perform target dependent optabs initialization. */ 5947 static void 5948 h8300_init_libfuncs (void) 5949 { 5950 set_optab_libfunc (smul_optab, HImode, "__mulhi3"); 5951 set_optab_libfunc (sdiv_optab, HImode, "__divhi3"); 5952 set_optab_libfunc (udiv_optab, HImode, "__udivhi3"); 5953 set_optab_libfunc (smod_optab, HImode, "__modhi3"); 5954 set_optab_libfunc (umod_optab, HImode, "__umodhi3"); 5955 } 5956 5957 /* Worker function for TARGET_FUNCTION_VALUE. 5958 5959 On the H8 the return value is in R0/R1. */ 5960 5961 static rtx 5962 h8300_function_value (const_tree ret_type, 5963 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 5964 bool outgoing ATTRIBUTE_UNUSED) 5965 { 5966 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG); 5967 } 5968 5969 /* Worker function for TARGET_LIBCALL_VALUE. 5970 5971 On the H8 the return value is in R0/R1. */ 5972 5973 static rtx 5974 h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) 5975 { 5976 return gen_rtx_REG (mode, R0_REG); 5977 } 5978 5979 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. 5980 5981 On the H8, R0 is the only register thus used. */ 5982 5983 static bool 5984 h8300_function_value_regno_p (const unsigned int regno) 5985 { 5986 return (regno == R0_REG); 5987 } 5988 5989 /* Worker function for TARGET_RETURN_IN_MEMORY. */ 5990 5991 static bool 5992 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 5993 { 5994 return (TYPE_MODE (type) == BLKmode 5995 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8)); 5996 } 5997 5998 /* We emit the entire trampoline here. Depending on the pointer size, 5999 we use a different trampoline. 6000 6001 Pmode == HImode 6002 vvvv context 6003 1 0000 7903xxxx mov.w #0x1234,r3 6004 2 0004 5A00xxxx jmp @0x1234 6005 ^^^^ function 6006 6007 Pmode == SImode 6008 vvvvvvvv context 6009 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 6010 3 0006 5Axxxxxx jmp @0x123456 6011 ^^^^^^ function 6012 */ 6013 6014 static void 6015 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) 6016 { 6017 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 6018 rtx mem; 6019 6020 if (Pmode == HImode) 6021 { 6022 mem = adjust_address (m_tramp, HImode, 0); 6023 emit_move_insn (mem, GEN_INT (0x7903)); 6024 mem = adjust_address (m_tramp, Pmode, 2); 6025 emit_move_insn (mem, cxt); 6026 mem = adjust_address (m_tramp, HImode, 4); 6027 emit_move_insn (mem, GEN_INT (0x5a00)); 6028 mem = adjust_address (m_tramp, Pmode, 6); 6029 emit_move_insn (mem, fnaddr); 6030 } 6031 else 6032 { 6033 rtx tem; 6034 6035 mem = adjust_address (m_tramp, HImode, 0); 6036 emit_move_insn (mem, GEN_INT (0x7a03)); 6037 mem = adjust_address (m_tramp, Pmode, 2); 6038 emit_move_insn (mem, cxt); 6039 6040 tem = copy_to_reg (fnaddr); 6041 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); 6042 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); 6043 mem = adjust_address (m_tramp, SImode, 6); 6044 emit_move_insn (mem, tem); 6045 } 6046 } 6047 6048 /* Implement PUSH_ROUNDING. 6049 6050 On the H8/300, @-sp really pushes a byte if you ask it to - but that's 6051 dangerous, so we claim that it always pushes a word, then we catch 6052 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output. 6053 6054 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4 6055 and doing a similar thing. */ 6056 6057 poly_int64 6058 h8300_push_rounding (poly_int64 bytes) 6059 { 6060 return ((bytes + PARM_BOUNDARY / 8 - 1) & (-PARM_BOUNDARY / 8)); 6061 } 6062 6063 /* Initialize the GCC target structure. */ 6064 #undef TARGET_ATTRIBUTE_TABLE 6065 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table 6066 6067 #undef TARGET_ASM_ALIGNED_HI_OP 6068 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 6069 6070 #undef TARGET_ASM_FILE_START 6071 #define TARGET_ASM_FILE_START h8300_file_start 6072 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 6073 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 6074 6075 #undef TARGET_ASM_FILE_END 6076 #define TARGET_ASM_FILE_END h8300_file_end 6077 6078 #undef TARGET_PRINT_OPERAND 6079 #define TARGET_PRINT_OPERAND h8300_print_operand 6080 #undef TARGET_PRINT_OPERAND_ADDRESS 6081 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address 6082 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 6083 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p 6084 6085 #undef TARGET_ENCODE_SECTION_INFO 6086 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info 6087 6088 #undef TARGET_INSERT_ATTRIBUTES 6089 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes 6090 6091 #undef TARGET_REGISTER_MOVE_COST 6092 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost 6093 6094 #undef TARGET_RTX_COSTS 6095 #define TARGET_RTX_COSTS h8300_rtx_costs 6096 6097 #undef TARGET_INIT_LIBFUNCS 6098 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs 6099 6100 #undef TARGET_FUNCTION_VALUE 6101 #define TARGET_FUNCTION_VALUE h8300_function_value 6102 6103 #undef TARGET_LIBCALL_VALUE 6104 #define TARGET_LIBCALL_VALUE h8300_libcall_value 6105 6106 #undef TARGET_FUNCTION_VALUE_REGNO_P 6107 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p 6108 6109 #undef TARGET_RETURN_IN_MEMORY 6110 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory 6111 6112 #undef TARGET_FUNCTION_ARG 6113 #define TARGET_FUNCTION_ARG h8300_function_arg 6114 6115 #undef TARGET_FUNCTION_ARG_ADVANCE 6116 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance 6117 6118 #undef TARGET_MACHINE_DEPENDENT_REORG 6119 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg 6120 6121 #undef TARGET_HARD_REGNO_SCRATCH_OK 6122 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok 6123 6124 #undef TARGET_HARD_REGNO_MODE_OK 6125 #define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok 6126 6127 #undef TARGET_MODES_TIEABLE_P 6128 #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p 6129 6130 #undef TARGET_LRA_P 6131 #define TARGET_LRA_P hook_bool_void_false 6132 6133 #undef TARGET_LEGITIMATE_ADDRESS_P 6134 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p 6135 6136 #undef TARGET_CAN_ELIMINATE 6137 #define TARGET_CAN_ELIMINATE h8300_can_eliminate 6138 6139 #undef TARGET_CONDITIONAL_REGISTER_USAGE 6140 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage 6141 6142 #undef TARGET_TRAMPOLINE_INIT 6143 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init 6144 6145 #undef TARGET_OPTION_OVERRIDE 6146 #define TARGET_OPTION_OVERRIDE h8300_option_override 6147 6148 #undef TARGET_MODE_DEPENDENT_ADDRESS_P 6149 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p 6150 6151 struct gcc_target targetm = TARGET_INITIALIZER; 6152