1;; Predicate definitions for Frv. 2;; Copyright (C) 2005-2020 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Return true if operand is a GPR register. 21 22(define_predicate "integer_register_operand" 23 (match_code "reg,subreg") 24{ 25 if (GET_MODE (op) != mode && mode != VOIDmode) 26 return FALSE; 27 28 if (GET_CODE (op) == SUBREG) 29 { 30 if (GET_CODE (SUBREG_REG (op)) != REG) 31 return register_operand (op, mode); 32 33 op = SUBREG_REG (op); 34 } 35 36 if (GET_CODE (op) != REG) 37 return FALSE; 38 39 return GPR_AP_OR_PSEUDO_P (REGNO (op)); 40}) 41 42;; Return 1 is OP is a memory operand, or will be turned into one by 43;; reload. 44 45(define_predicate "frv_load_operand" 46 (match_code "reg,subreg,mem") 47{ 48 if (GET_MODE (op) != mode && mode != VOIDmode) 49 return FALSE; 50 51 if (reload_in_progress) 52 { 53 rtx tmp = op; 54 if (GET_CODE (tmp) == SUBREG) 55 tmp = SUBREG_REG (tmp); 56 if (GET_CODE (tmp) == REG 57 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER) 58 op = reg_equiv_memory_loc (REGNO (tmp)); 59 } 60 61 return op && memory_operand (op, mode); 62}) 63 64;; Return true if operand is a GPR register. Do not allow SUBREG's 65;; here, in order to prevent a combine bug. 66 67(define_predicate "gpr_no_subreg_operand" 68 (match_code "reg") 69{ 70 if (GET_MODE (op) != mode && mode != VOIDmode) 71 return FALSE; 72 73 if (GET_CODE (op) != REG) 74 return FALSE; 75 76 return GPR_OR_PSEUDO_P (REGNO (op)); 77}) 78 79;; Return 1 if operand is a GPR register or a FPR register. 80 81(define_predicate "gpr_or_fpr_operand" 82 (match_code "reg,subreg") 83{ 84 int regno; 85 86 if (GET_MODE (op) != mode && mode != VOIDmode) 87 return FALSE; 88 89 if (GET_CODE (op) == SUBREG) 90 { 91 if (GET_CODE (SUBREG_REG (op)) != REG) 92 return register_operand (op, mode); 93 94 op = SUBREG_REG (op); 95 } 96 97 if (GET_CODE (op) != REG) 98 return FALSE; 99 100 regno = REGNO (op); 101 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER) 102 return TRUE; 103 104 return FALSE; 105}) 106 107;; Return 1 if operand is a GPR register or 12-bit signed immediate. 108 109(define_predicate "gpr_or_int12_operand" 110 (match_code "reg,subreg,const_int,const") 111{ 112 if (GET_CODE (op) == CONST_INT) 113 return IN_RANGE (INTVAL (op), -2048, 2047); 114 115 if (got12_operand (op, mode)) 116 return true; 117 118 if (GET_MODE (op) != mode && mode != VOIDmode) 119 return FALSE; 120 121 if (GET_CODE (op) == SUBREG) 122 { 123 if (GET_CODE (SUBREG_REG (op)) != REG) 124 return register_operand (op, mode); 125 126 op = SUBREG_REG (op); 127 } 128 129 if (GET_CODE (op) != REG) 130 return FALSE; 131 132 return GPR_OR_PSEUDO_P (REGNO (op)); 133}) 134 135;; Return 1 if operand is a GPR register, or a FPR register, or a 12 136;; bit signed immediate. 137 138(define_predicate "gpr_fpr_or_int12_operand" 139 (match_code "reg,subreg,const_int") 140{ 141 int regno; 142 143 if (GET_CODE (op) == CONST_INT) 144 return IN_RANGE (INTVAL (op), -2048, 2047); 145 146 if (GET_MODE (op) != mode && mode != VOIDmode) 147 return FALSE; 148 149 if (GET_CODE (op) == SUBREG) 150 { 151 if (GET_CODE (SUBREG_REG (op)) != REG) 152 return register_operand (op, mode); 153 154 op = SUBREG_REG (op); 155 } 156 157 if (GET_CODE (op) != REG) 158 return FALSE; 159 160 regno = REGNO (op); 161 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER) 162 return TRUE; 163 164 return FALSE; 165}) 166 167;; Return 1 if operand is a register or 10-bit signed immediate. 168 169(define_predicate "gpr_or_int10_operand" 170 (match_code "reg,subreg,const_int") 171{ 172 if (GET_CODE (op) == CONST_INT) 173 return IN_RANGE (INTVAL (op), -512, 511); 174 175 if (GET_MODE (op) != mode && mode != VOIDmode) 176 return FALSE; 177 178 if (GET_CODE (op) == SUBREG) 179 { 180 if (GET_CODE (SUBREG_REG (op)) != REG) 181 return register_operand (op, mode); 182 183 op = SUBREG_REG (op); 184 } 185 186 if (GET_CODE (op) != REG) 187 return FALSE; 188 189 return GPR_OR_PSEUDO_P (REGNO (op)); 190}) 191 192;; Return 1 if operand is a register or an integer immediate. 193 194(define_predicate "gpr_or_int_operand" 195 (match_code "reg,subreg,const_int") 196{ 197 if (GET_CODE (op) == CONST_INT) 198 return TRUE; 199 200 if (GET_MODE (op) != mode && mode != VOIDmode) 201 return FALSE; 202 203 if (GET_CODE (op) == SUBREG) 204 { 205 if (GET_CODE (SUBREG_REG (op)) != REG) 206 return register_operand (op, mode); 207 208 op = SUBREG_REG (op); 209 } 210 211 if (GET_CODE (op) != REG) 212 return FALSE; 213 214 return GPR_OR_PSEUDO_P (REGNO (op)); 215}) 216 217;; Return true if operand is something that can be an input for a move 218;; operation. 219 220(define_predicate "move_source_operand" 221 (match_code "reg,subreg,const_int,mem,const_double,const,symbol_ref,label_ref") 222{ 223 rtx subreg; 224 enum rtx_code code; 225 226 switch (GET_CODE (op)) 227 { 228 default: 229 break; 230 231 case CONST_INT: 232 case CONST_DOUBLE: 233 return immediate_operand (op, mode); 234 235 case SUBREG: 236 if (GET_MODE (op) != mode && mode != VOIDmode) 237 return FALSE; 238 239 subreg = SUBREG_REG (op); 240 code = GET_CODE (subreg); 241 if (code == MEM) 242 return frv_legitimate_address_p_1 (mode, XEXP (subreg, 0), 243 reload_completed, FALSE, FALSE); 244 245 return (code == REG); 246 247 case REG: 248 if (GET_MODE (op) != mode && mode != VOIDmode) 249 return FALSE; 250 251 return TRUE; 252 253 case MEM: 254 return frv_legitimate_memory_operand (op, mode, FALSE); 255 } 256 257 return FALSE; 258}) 259 260;; Return true if operand is something that can be an output for a 261;; move operation. 262 263(define_predicate "move_destination_operand" 264 (match_code "reg,subreg,mem") 265{ 266 rtx subreg; 267 enum rtx_code code; 268 269 switch (GET_CODE (op)) 270 { 271 default: 272 break; 273 274 case SUBREG: 275 if (GET_MODE (op) != mode && mode != VOIDmode) 276 return FALSE; 277 278 subreg = SUBREG_REG (op); 279 code = GET_CODE (subreg); 280 if (code == MEM) 281 return frv_legitimate_address_p_1 (mode, XEXP (subreg, 0), 282 reload_completed, FALSE, FALSE); 283 284 return (code == REG); 285 286 case REG: 287 if (GET_MODE (op) != mode && mode != VOIDmode) 288 return FALSE; 289 290 return TRUE; 291 292 case MEM: 293 return frv_legitimate_memory_operand (op, mode, FALSE); 294 } 295 296 return FALSE; 297}) 298 299;; Return true if we the operand is a valid destination for a movcc_fp 300;; instruction. This means rejecting fcc_operands, since we need 301;; scratch registers to write to them. 302 303(define_predicate "movcc_fp_destination_operand" 304 (match_code "reg,subreg,mem") 305{ 306 if (fcc_operand (op, mode)) 307 return FALSE; 308 309 return move_destination_operand (op, mode); 310}) 311 312;; Return true if operand is something that can be an input for a 313;; conditional move operation. 314 315(define_predicate "condexec_source_operand" 316 (match_code "reg,subreg,const_int,mem,const_double") 317{ 318 rtx subreg; 319 enum rtx_code code; 320 321 switch (GET_CODE (op)) 322 { 323 default: 324 break; 325 326 case CONST_INT: 327 case CONST_DOUBLE: 328 return ZERO_P (op); 329 330 case SUBREG: 331 if (GET_MODE (op) != mode && mode != VOIDmode) 332 return FALSE; 333 334 subreg = SUBREG_REG (op); 335 code = GET_CODE (subreg); 336 if (code == MEM) 337 return frv_legitimate_address_p_1 (mode, XEXP (subreg, 0), 338 reload_completed, TRUE, FALSE); 339 340 return (code == REG); 341 342 case REG: 343 if (GET_MODE (op) != mode && mode != VOIDmode) 344 return FALSE; 345 346 return TRUE; 347 348 case MEM: 349 return frv_legitimate_memory_operand (op, mode, TRUE); 350 } 351 352 return FALSE; 353}) 354 355;; Return true if operand is something that can be an output for a 356;; conditional move operation. 357 358(define_predicate "condexec_dest_operand" 359 (match_code "reg,subreg,mem") 360{ 361 rtx subreg; 362 enum rtx_code code; 363 364 switch (GET_CODE (op)) 365 { 366 default: 367 break; 368 369 case SUBREG: 370 if (GET_MODE (op) != mode && mode != VOIDmode) 371 return FALSE; 372 373 subreg = SUBREG_REG (op); 374 code = GET_CODE (subreg); 375 if (code == MEM) 376 return frv_legitimate_address_p_1 (mode, XEXP (subreg, 0), 377 reload_completed, TRUE, FALSE); 378 379 return (code == REG); 380 381 case REG: 382 if (GET_MODE (op) != mode && mode != VOIDmode) 383 return FALSE; 384 385 return TRUE; 386 387 case MEM: 388 return frv_legitimate_memory_operand (op, mode, TRUE); 389 } 390 391 return FALSE; 392}) 393 394;; Return true if operand is a register of any flavor or a 0 of the 395;; appropriate type. 396 397(define_predicate "reg_or_0_operand" 398 (match_code "reg,subreg,const_int,const_double") 399{ 400 switch (GET_CODE (op)) 401 { 402 default: 403 break; 404 405 case REG: 406 case SUBREG: 407 if (GET_MODE (op) != mode && mode != VOIDmode) 408 return FALSE; 409 410 return register_operand (op, mode); 411 412 case CONST_INT: 413 case CONST_DOUBLE: 414 return ZERO_P (op); 415 } 416 417 return FALSE; 418}) 419 420;; Return true if operand is the link register. 421 422(define_predicate "lr_operand" 423 (match_code "reg") 424{ 425 if (GET_CODE (op) != REG) 426 return FALSE; 427 428 if (GET_MODE (op) != mode && mode != VOIDmode) 429 return FALSE; 430 431 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER) 432 return FALSE; 433 434 return TRUE; 435}) 436 437;; Return true if operand is a gpr register or a valid memory operand. 438 439(define_predicate "gpr_or_memory_operand" 440 (match_code "reg,subreg,mem") 441{ 442 return (integer_register_operand (op, mode) 443 || frv_legitimate_memory_operand (op, mode, FALSE)); 444}) 445 446;; Return true if operand is a gpr register, a valid memory operand, 447;; or a memory operand that can be made valid using an additional gpr 448;; register. 449 450(define_predicate "gpr_or_memory_operand_with_scratch" 451 (match_code "reg,subreg,mem") 452{ 453 rtx addr; 454 455 if (gpr_or_memory_operand (op, mode)) 456 return TRUE; 457 458 if (GET_CODE (op) != MEM) 459 return FALSE; 460 461 if (GET_MODE (op) != mode) 462 return FALSE; 463 464 addr = XEXP (op, 0); 465 466 if (GET_CODE (addr) != PLUS) 467 return FALSE; 468 469 if (!integer_register_operand (XEXP (addr, 0), Pmode)) 470 return FALSE; 471 472 if (GET_CODE (XEXP (addr, 1)) != CONST_INT) 473 return FALSE; 474 475 return TRUE; 476}) 477 478;; Return true if operand is a fpr register or a valid memory 479;; operation. 480 481(define_predicate "fpr_or_memory_operand" 482 (match_code "reg,subreg,mem") 483{ 484 return (fpr_operand (op, mode) 485 || frv_legitimate_memory_operand (op, mode, FALSE)); 486}) 487 488;; Return 1 if operand is a 12-bit signed immediate. 489 490(define_predicate "int12_operand" 491 (match_code "const_int") 492{ 493 if (GET_CODE (op) != CONST_INT) 494 return FALSE; 495 496 return IN_RANGE (INTVAL (op), -2048, 2047); 497}) 498 499;; Return 1 if operand is an integer constant that takes 2 500;; instructions to load up and can be split into sethi/setlo 501;; instructions.. 502 503(define_predicate "int_2word_operand" 504 (match_code "const_int,const_double,symbol_ref,label_ref,const") 505{ 506 HOST_WIDE_INT value; 507 long l; 508 509 switch (GET_CODE (op)) 510 { 511 default: 512 break; 513 514 case LABEL_REF: 515 if (TARGET_FDPIC) 516 return FALSE; 517 518 return (flag_pic == 0); 519 520 case CONST: 521 if (flag_pic || TARGET_FDPIC) 522 return FALSE; 523 524 op = XEXP (op, 0); 525 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT) 526 op = XEXP (op, 0); 527 return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF; 528 529 case SYMBOL_REF: 530 if (TARGET_FDPIC) 531 return FALSE; 532 533 /* small data references are already 1 word */ 534 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op)); 535 536 case CONST_INT: 537 return ! IN_RANGE (INTVAL (op), -32768, 32767); 538 539 case CONST_DOUBLE: 540 if (GET_MODE (op) == SFmode) 541 { 542 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l); 543 value = l; 544 return ! IN_RANGE (value, -32768, 32767); 545 } 546 else if (GET_MODE (op) == VOIDmode) 547 { 548 value = CONST_DOUBLE_LOW (op); 549 return ! IN_RANGE (value, -32768, 32767); 550 } 551 break; 552 } 553 554 return FALSE; 555}) 556 557;; Return true if operand is the uClinux PIC register. 558 559(define_predicate "fdpic_operand" 560 (match_code "reg") 561{ 562 if (!TARGET_FDPIC) 563 return FALSE; 564 565 if (GET_CODE (op) != REG) 566 return FALSE; 567 568 if (GET_MODE (op) != mode && mode != VOIDmode) 569 return FALSE; 570 571 if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER) 572 return FALSE; 573 574 return TRUE; 575}) 576 577;; TODO: Add a comment here. 578 579(define_predicate "fdpic_fptr_operand" 580 (match_code "reg") 581{ 582 if (GET_MODE (op) != mode && mode != VOIDmode) 583 return FALSE; 584 if (GET_CODE (op) != REG) 585 return FALSE; 586 if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER) 587 return FALSE; 588 return TRUE; 589}) 590 591;; An address operand that may use a pair of registers, an addressing 592;; mode that we reject in general. 593 594(define_predicate "ldd_address_operand" 595 (match_code "reg,subreg,plus") 596{ 597 if (GET_MODE (op) != mode && GET_MODE (op) != VOIDmode) 598 return FALSE; 599 600 return frv_legitimate_address_p_1 (DImode, op, reload_completed, FALSE, TRUE); 601}) 602 603;; TODO: Add a comment here. 604 605(define_predicate "got12_operand" 606 (match_code "const") 607{ 608 struct frv_unspec unspec; 609 610 if (frv_const_unspec_p (op, &unspec)) 611 switch (unspec.reloc) 612 { 613 case R_FRV_GOT12: 614 case R_FRV_GOTOFF12: 615 case R_FRV_FUNCDESC_GOT12: 616 case R_FRV_FUNCDESC_GOTOFF12: 617 case R_FRV_GPREL12: 618 case R_FRV_TLSMOFF12: 619 return true; 620 } 621 return false; 622}) 623 624;; Return true if OP is a valid const-unspec expression. 625 626(define_predicate "const_unspec_operand" 627 (match_code "const") 628{ 629 struct frv_unspec unspec; 630 631 return frv_const_unspec_p (op, &unspec); 632}) 633 634;; Return true if operand is an icc register. 635 636(define_predicate "icc_operand" 637 (match_code "reg") 638{ 639 int regno; 640 641 if (GET_MODE (op) != mode && mode != VOIDmode) 642 return FALSE; 643 644 if (GET_CODE (op) != REG) 645 return FALSE; 646 647 regno = REGNO (op); 648 return ICC_OR_PSEUDO_P (regno); 649}) 650 651;; Return true if operand is an fcc register. 652 653(define_predicate "fcc_operand" 654 (match_code "reg") 655{ 656 int regno; 657 658 if (GET_MODE (op) != mode && mode != VOIDmode) 659 return FALSE; 660 661 if (GET_CODE (op) != REG) 662 return FALSE; 663 664 regno = REGNO (op); 665 return FCC_OR_PSEUDO_P (regno); 666}) 667 668;; Return true if operand is either an fcc or icc register. 669 670(define_predicate "cc_operand" 671 (match_code "reg") 672{ 673 int regno; 674 675 if (GET_MODE (op) != mode && mode != VOIDmode) 676 return FALSE; 677 678 if (GET_CODE (op) != REG) 679 return FALSE; 680 681 regno = REGNO (op); 682 if (CC_OR_PSEUDO_P (regno)) 683 return TRUE; 684 685 return FALSE; 686}) 687 688;; Return true if operand is an integer CCR register. 689 690(define_predicate "icr_operand" 691 (match_code "reg") 692{ 693 int regno; 694 695 if (GET_MODE (op) != mode && mode != VOIDmode) 696 return FALSE; 697 698 if (GET_CODE (op) != REG) 699 return FALSE; 700 701 regno = REGNO (op); 702 return ICR_OR_PSEUDO_P (regno); 703}) 704 705;; Return true if operand is an fcc register. 706 707(define_predicate "fcr_operand" 708 (match_code "reg") 709{ 710 int regno; 711 712 if (GET_MODE (op) != mode && mode != VOIDmode) 713 return FALSE; 714 715 if (GET_CODE (op) != REG) 716 return FALSE; 717 718 regno = REGNO (op); 719 return FCR_OR_PSEUDO_P (regno); 720}) 721 722;; Return true if operand is either an fcc or icc register. 723 724(define_predicate "cr_operand" 725 (match_code "reg") 726{ 727 int regno; 728 729 if (GET_MODE (op) != mode && mode != VOIDmode) 730 return FALSE; 731 732 if (GET_CODE (op) != REG) 733 return FALSE; 734 735 regno = REGNO (op); 736 if (CR_OR_PSEUDO_P (regno)) 737 return TRUE; 738 739 return FALSE; 740}) 741 742;; Return true if operand is a FPR register. 743 744(define_predicate "fpr_operand" 745 (match_code "reg,subreg") 746{ 747 if (GET_MODE (op) != mode && mode != VOIDmode) 748 return FALSE; 749 750 if (GET_CODE (op) == SUBREG) 751 { 752 if (GET_CODE (SUBREG_REG (op)) != REG) 753 return register_operand (op, mode); 754 755 op = SUBREG_REG (op); 756 } 757 758 if (GET_CODE (op) != REG) 759 return FALSE; 760 761 return FPR_OR_PSEUDO_P (REGNO (op)); 762}) 763 764;; Return true if operand is an even GPR or FPR register. 765 766(define_predicate "even_reg_operand" 767 (match_code "reg,subreg") 768{ 769 int regno; 770 771 if (GET_MODE (op) != mode && mode != VOIDmode) 772 return FALSE; 773 774 if (GET_CODE (op) == SUBREG) 775 { 776 if (GET_CODE (SUBREG_REG (op)) != REG) 777 return register_operand (op, mode); 778 779 op = SUBREG_REG (op); 780 } 781 782 if (GET_CODE (op) != REG) 783 return FALSE; 784 785 regno = REGNO (op); 786 if (regno >= FIRST_PSEUDO_REGISTER) 787 return TRUE; 788 789 if (GPR_P (regno)) 790 return (((regno - GPR_FIRST) & 1) == 0); 791 792 if (FPR_P (regno)) 793 return (((regno - FPR_FIRST) & 1) == 0); 794 795 return FALSE; 796}) 797 798;; Return true if operand is an odd GPR register. 799 800(define_predicate "odd_reg_operand" 801 (match_code "reg,subreg") 802{ 803 int regno; 804 805 if (GET_MODE (op) != mode && mode != VOIDmode) 806 return FALSE; 807 808 if (GET_CODE (op) == SUBREG) 809 { 810 if (GET_CODE (SUBREG_REG (op)) != REG) 811 return register_operand (op, mode); 812 813 op = SUBREG_REG (op); 814 } 815 816 if (GET_CODE (op) != REG) 817 return FALSE; 818 819 regno = REGNO (op); 820 /* Assume that reload will give us an even register. */ 821 if (regno >= FIRST_PSEUDO_REGISTER) 822 return FALSE; 823 824 if (GPR_P (regno)) 825 return (((regno - GPR_FIRST) & 1) != 0); 826 827 if (FPR_P (regno)) 828 return (((regno - FPR_FIRST) & 1) != 0); 829 830 return FALSE; 831}) 832 833;; Return true if operand is an even GPR register. 834 835(define_predicate "even_gpr_operand" 836 (match_code "reg,subreg") 837{ 838 int regno; 839 840 if (GET_MODE (op) != mode && mode != VOIDmode) 841 return FALSE; 842 843 if (GET_CODE (op) == SUBREG) 844 { 845 if (GET_CODE (SUBREG_REG (op)) != REG) 846 return register_operand (op, mode); 847 848 op = SUBREG_REG (op); 849 } 850 851 if (GET_CODE (op) != REG) 852 return FALSE; 853 854 regno = REGNO (op); 855 if (regno >= FIRST_PSEUDO_REGISTER) 856 return TRUE; 857 858 if (! GPR_P (regno)) 859 return FALSE; 860 861 return (((regno - GPR_FIRST) & 1) == 0); 862}) 863 864;; Return true if operand is an odd GPR register. 865 866(define_predicate "odd_gpr_operand" 867 (match_code "reg,subreg") 868{ 869 int regno; 870 871 if (GET_MODE (op) != mode && mode != VOIDmode) 872 return FALSE; 873 874 if (GET_CODE (op) == SUBREG) 875 { 876 if (GET_CODE (SUBREG_REG (op)) != REG) 877 return register_operand (op, mode); 878 879 op = SUBREG_REG (op); 880 } 881 882 if (GET_CODE (op) != REG) 883 return FALSE; 884 885 regno = REGNO (op); 886 /* Assume that reload will give us an even register. */ 887 if (regno >= FIRST_PSEUDO_REGISTER) 888 return FALSE; 889 890 if (! GPR_P (regno)) 891 return FALSE; 892 893 return (((regno - GPR_FIRST) & 1) != 0); 894}) 895 896;; Return true if operand is a quad aligned FPR register. 897 898(define_predicate "quad_fpr_operand" 899 (match_code "reg,subreg") 900{ 901 int regno; 902 903 if (GET_MODE (op) != mode && mode != VOIDmode) 904 return FALSE; 905 906 if (GET_CODE (op) == SUBREG) 907 { 908 if (GET_CODE (SUBREG_REG (op)) != REG) 909 return register_operand (op, mode); 910 911 op = SUBREG_REG (op); 912 } 913 914 if (GET_CODE (op) != REG) 915 return FALSE; 916 917 regno = REGNO (op); 918 if (regno >= FIRST_PSEUDO_REGISTER) 919 return TRUE; 920 921 if (! FPR_P (regno)) 922 return FALSE; 923 924 return (((regno - FPR_FIRST) & 3) == 0); 925}) 926 927;; Return true if operand is an even FPR register. 928 929(define_predicate "even_fpr_operand" 930 (match_code "reg,subreg") 931{ 932 int regno; 933 934 if (GET_MODE (op) != mode && mode != VOIDmode) 935 return FALSE; 936 937 if (GET_CODE (op) == SUBREG) 938 { 939 if (GET_CODE (SUBREG_REG (op)) != REG) 940 return register_operand (op, mode); 941 942 op = SUBREG_REG (op); 943 } 944 945 if (GET_CODE (op) != REG) 946 return FALSE; 947 948 regno = REGNO (op); 949 if (regno >= FIRST_PSEUDO_REGISTER) 950 return TRUE; 951 952 if (! FPR_P (regno)) 953 return FALSE; 954 955 return (((regno - FPR_FIRST) & 1) == 0); 956}) 957 958;; Return true if operand is an odd FPR register. 959 960(define_predicate "odd_fpr_operand" 961 (match_code "reg,subreg") 962{ 963 int regno; 964 965 if (GET_MODE (op) != mode && mode != VOIDmode) 966 return FALSE; 967 968 if (GET_CODE (op) == SUBREG) 969 { 970 if (GET_CODE (SUBREG_REG (op)) != REG) 971 return register_operand (op, mode); 972 973 op = SUBREG_REG (op); 974 } 975 976 if (GET_CODE (op) != REG) 977 return FALSE; 978 979 regno = REGNO (op); 980 /* Assume that reload will give us an even register. */ 981 if (regno >= FIRST_PSEUDO_REGISTER) 982 return FALSE; 983 984 if (! FPR_P (regno)) 985 return FALSE; 986 987 return (((regno - FPR_FIRST) & 1) != 0); 988}) 989 990;; Return true if operand is a 2 word memory address that can be 991;; loaded in one instruction to load or store. We assume the stack 992;; and frame pointers are suitably aligned, and variables in the small 993;; data area. FIXME -- at some we should recognize other globals and 994;; statics. We can't assume that any old pointer is aligned, given 995;; that arguments could be passed on an odd word on the stack and the 996;; address taken and passed through to another function. 997 998(define_predicate "dbl_memory_one_insn_operand" 999 (match_code "mem") 1000{ 1001 rtx addr; 1002 rtx addr_reg; 1003 1004 if (! TARGET_DWORD) 1005 return FALSE; 1006 1007 if (GET_CODE (op) != MEM) 1008 return FALSE; 1009 1010 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD) 1011 return FALSE; 1012 1013 addr = XEXP (op, 0); 1014 if (GET_CODE (addr) == REG) 1015 addr_reg = addr; 1016 1017 else if (GET_CODE (addr) == PLUS) 1018 { 1019 rtx addr0 = XEXP (addr, 0); 1020 rtx addr1 = XEXP (addr, 1); 1021 1022 if (GET_CODE (addr0) != REG) 1023 return FALSE; 1024 1025 if (got12_operand (addr1, VOIDmode)) 1026 return TRUE; 1027 1028 if (GET_CODE (addr1) != CONST_INT) 1029 return FALSE; 1030 1031 if ((INTVAL (addr1) & 7) != 0) 1032 return FALSE; 1033 1034 addr_reg = addr0; 1035 } 1036 1037 else 1038 return FALSE; 1039 1040 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx) 1041 return TRUE; 1042 1043 return FALSE; 1044}) 1045 1046;; Return true if operand is a 2 word memory address that needs to use 1047;; two instructions to load or store. 1048 1049(define_predicate "dbl_memory_two_insn_operand" 1050 (match_code "mem") 1051{ 1052 if (GET_CODE (op) != MEM) 1053 return FALSE; 1054 1055 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD) 1056 return FALSE; 1057 1058 if (! TARGET_DWORD) 1059 return TRUE; 1060 1061 return ! dbl_memory_one_insn_operand (op, mode); 1062}) 1063 1064;; Return true if operand is a memory reference suitable for a call. 1065 1066(define_predicate "call_operand" 1067 (match_code "reg,subreg,const_int,const,symbol_ref") 1068{ 1069 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT) 1070 return FALSE; 1071 1072 if (GET_CODE (op) == SYMBOL_REF) 1073 return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op); 1074 1075 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should 1076 never occur anyway), but prevents reload from not handling the case 1077 properly of a call through a pointer on a function that calls 1078 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */ 1079 return gpr_or_int12_operand (op, mode); 1080}) 1081 1082;; Return true if operand is a memory reference suitable for a 1083;; sibcall. 1084 1085(define_predicate "sibcall_operand" 1086 (match_code "reg,subreg,const_int,const") 1087{ 1088 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT) 1089 return FALSE; 1090 1091 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should 1092 never occur anyway), but prevents reload from not handling the case 1093 properly of a call through a pointer on a function that calls 1094 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */ 1095 return gpr_or_int12_operand (op, mode); 1096}) 1097 1098;; Return 1 if operand is an integer constant with the bottom 16 bits 1099;; clear. 1100 1101(define_predicate "upper_int16_operand" 1102 (match_code "const_int") 1103{ 1104 if (GET_CODE (op) != CONST_INT) 1105 return FALSE; 1106 1107 return ((INTVAL (op) & 0xffff) == 0); 1108}) 1109 1110;; Return 1 if operand is a 16-bit unsigned immediate. 1111 1112(define_predicate "uint16_operand" 1113 (match_code "const_int") 1114{ 1115 if (GET_CODE (op) != CONST_INT) 1116 return FALSE; 1117 1118 return IN_RANGE (INTVAL (op), 0, 0xffff); 1119}) 1120 1121;; Returns 1 if OP is either a SYMBOL_REF or a constant. 1122 1123(define_predicate "symbolic_operand" 1124 (match_code "symbol_ref,const,const_int") 1125{ 1126 enum rtx_code c = GET_CODE (op); 1127 1128 if (c == CONST) 1129 { 1130 /* Allow (const:SI (plus:SI (symbol_ref) (const_int))). */ 1131 return GET_MODE (op) == SImode 1132 && GET_CODE (XEXP (op, 0)) == PLUS 1133 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF 1134 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT; 1135 } 1136 1137 return c == SYMBOL_REF || c == CONST_INT; 1138}) 1139 1140;; Return true if operator is a kind of relational operator. 1141 1142(define_predicate "relational_operator" 1143 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu") 1144{ 1145 return (integer_relational_operator (op, mode) 1146 || float_relational_operator (op, mode)); 1147}) 1148 1149;; Return true if OP is a relational operator suitable for CCmode, 1150;; CC_UNSmode or CC_NZmode. 1151 1152(define_predicate "integer_relational_operator" 1153 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu") 1154{ 1155 if (mode != VOIDmode && mode != GET_MODE (op)) 1156 return FALSE; 1157 1158 /* The allowable relations depend on the mode of the ICC register. */ 1159 switch (GET_CODE (op)) 1160 { 1161 default: 1162 return FALSE; 1163 1164 case EQ: 1165 case NE: 1166 case LT: 1167 case GE: 1168 return (GET_MODE (XEXP (op, 0)) == CC_NZmode 1169 || GET_MODE (XEXP (op, 0)) == CCmode); 1170 1171 case LE: 1172 case GT: 1173 return GET_MODE (XEXP (op, 0)) == CCmode; 1174 1175 case GTU: 1176 case GEU: 1177 case LTU: 1178 case LEU: 1179 return (GET_MODE (XEXP (op, 0)) == CC_NZmode 1180 || GET_MODE (XEXP (op, 0)) == CC_UNSmode); 1181 } 1182}) 1183 1184;; Return true if operator is a floating point relational operator. 1185 1186(define_predicate "float_relational_operator" 1187 (match_code "eq,ne,le,lt,ge,gt") 1188{ 1189 if (mode != VOIDmode && mode != GET_MODE (op)) 1190 return FALSE; 1191 1192 switch (GET_CODE (op)) 1193 { 1194 default: 1195 return FALSE; 1196 1197 case EQ: case NE: 1198 case LE: case LT: 1199 case GE: case GT: 1200#if 0 1201 case UEQ: case UNE: 1202 case ULE: case ULT: 1203 case UGE: case UGT: 1204 case ORDERED: 1205 case UNORDERED: 1206#endif 1207 return GET_MODE (XEXP (op, 0)) == CC_FPmode; 1208 } 1209}) 1210 1211;; Return true if operator is EQ/NE of a conditional execution 1212;; register. 1213 1214(define_predicate "ccr_eqne_operator" 1215 (match_code "eq,ne") 1216{ 1217 machine_mode op_mode = GET_MODE (op); 1218 rtx op0; 1219 rtx op1; 1220 int regno; 1221 1222 if (mode != VOIDmode && op_mode != mode) 1223 return FALSE; 1224 1225 switch (GET_CODE (op)) 1226 { 1227 default: 1228 return FALSE; 1229 1230 case EQ: 1231 case NE: 1232 break; 1233 } 1234 1235 op1 = XEXP (op, 1); 1236 if (op1 != const0_rtx) 1237 return FALSE; 1238 1239 op0 = XEXP (op, 0); 1240 if (GET_CODE (op0) != REG) 1241 return FALSE; 1242 1243 regno = REGNO (op0); 1244 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno)) 1245 return TRUE; 1246 1247 return FALSE; 1248}) 1249 1250;; Return true if operator is a minimum or maximum operator (both 1251;; signed and unsigned). 1252 1253(define_predicate "minmax_operator" 1254 (match_code "smin,smax,umin,umax") 1255{ 1256 if (mode != VOIDmode && mode != GET_MODE (op)) 1257 return FALSE; 1258 1259 switch (GET_CODE (op)) 1260 { 1261 default: 1262 return FALSE; 1263 1264 case SMIN: 1265 case SMAX: 1266 case UMIN: 1267 case UMAX: 1268 break; 1269 } 1270 1271 return TRUE; 1272}) 1273 1274;; Return true if operator is an integer binary operator that can 1275;; executed conditionally and takes 1 cycle. 1276 1277(define_predicate "condexec_si_binary_operator" 1278 (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt") 1279{ 1280 machine_mode op_mode = GET_MODE (op); 1281 1282 if (mode != VOIDmode && op_mode != mode) 1283 return FALSE; 1284 1285 switch (GET_CODE (op)) 1286 { 1287 default: 1288 return FALSE; 1289 1290 case PLUS: 1291 case MINUS: 1292 case AND: 1293 case IOR: 1294 case XOR: 1295 case ASHIFT: 1296 case ASHIFTRT: 1297 case LSHIFTRT: 1298 return TRUE; 1299 } 1300}) 1301 1302;; Return true if operator is an integer binary operator that can be 1303;; executed conditionally by a media instruction. 1304 1305(define_predicate "condexec_si_media_operator" 1306 (match_code "and,ior,xor") 1307{ 1308 machine_mode op_mode = GET_MODE (op); 1309 1310 if (mode != VOIDmode && op_mode != mode) 1311 return FALSE; 1312 1313 switch (GET_CODE (op)) 1314 { 1315 default: 1316 return FALSE; 1317 1318 case AND: 1319 case IOR: 1320 case XOR: 1321 return TRUE; 1322 } 1323}) 1324 1325;; Return true if operator is an integer division operator that can 1326;; executed conditionally. 1327 1328(define_predicate "condexec_si_divide_operator" 1329 (match_code "div,udiv") 1330{ 1331 machine_mode op_mode = GET_MODE (op); 1332 1333 if (mode != VOIDmode && op_mode != mode) 1334 return FALSE; 1335 1336 switch (GET_CODE (op)) 1337 { 1338 default: 1339 return FALSE; 1340 1341 case DIV: 1342 case UDIV: 1343 return TRUE; 1344 } 1345}) 1346 1347;; Return true if operator is an integer unary operator that can 1348;; executed conditionally. 1349 1350(define_predicate "condexec_si_unary_operator" 1351 (match_code "not,neg") 1352{ 1353 machine_mode op_mode = GET_MODE (op); 1354 1355 if (mode != VOIDmode && op_mode != mode) 1356 return FALSE; 1357 1358 switch (GET_CODE (op)) 1359 { 1360 default: 1361 return FALSE; 1362 1363 case NEG: 1364 case NOT: 1365 return TRUE; 1366 } 1367}) 1368 1369;; Return true if operator is an addition or subtraction 1370;; expression. Such expressions can be evaluated conditionally by 1371;; floating-point instructions. 1372 1373(define_predicate "condexec_sf_add_operator" 1374 (match_code "plus,minus") 1375{ 1376 machine_mode op_mode = GET_MODE (op); 1377 1378 if (mode != VOIDmode && op_mode != mode) 1379 return FALSE; 1380 1381 switch (GET_CODE (op)) 1382 { 1383 default: 1384 return FALSE; 1385 1386 case PLUS: 1387 case MINUS: 1388 return TRUE; 1389 } 1390}) 1391 1392;; Return true if operator is a conversion-type expression that can be 1393;; evaluated conditionally by floating-point instructions. 1394 1395(define_predicate "condexec_sf_conv_operator" 1396 (match_code "abs,neg") 1397{ 1398 machine_mode op_mode = GET_MODE (op); 1399 1400 if (mode != VOIDmode && op_mode != mode) 1401 return FALSE; 1402 1403 switch (GET_CODE (op)) 1404 { 1405 default: 1406 return FALSE; 1407 1408 case NEG: 1409 case ABS: 1410 return TRUE; 1411 } 1412}) 1413 1414;; Return true if OP is an integer binary operator that can be 1415;; combined with a (set ... (compare:CC_NZ ...)) pattern. 1416 1417(define_predicate "intop_compare_operator" 1418 (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt") 1419{ 1420 if (mode != VOIDmode && GET_MODE (op) != mode) 1421 return FALSE; 1422 1423 switch (GET_CODE (op)) 1424 { 1425 default: 1426 return FALSE; 1427 1428 case PLUS: 1429 case MINUS: 1430 case AND: 1431 case IOR: 1432 case XOR: 1433 case ASHIFTRT: 1434 case LSHIFTRT: 1435 return GET_MODE (op) == SImode; 1436 } 1437}) 1438 1439;; Return 1 if operand is a register or 6-bit signed immediate. 1440 1441(define_predicate "fpr_or_int6_operand" 1442 (match_code "reg,subreg,const_int") 1443{ 1444 if (GET_CODE (op) == CONST_INT) 1445 return IN_RANGE (INTVAL (op), -32, 31); 1446 1447 if (GET_MODE (op) != mode && mode != VOIDmode) 1448 return FALSE; 1449 1450 if (GET_CODE (op) == SUBREG) 1451 { 1452 if (GET_CODE (SUBREG_REG (op)) != REG) 1453 return register_operand (op, mode); 1454 1455 op = SUBREG_REG (op); 1456 } 1457 1458 if (GET_CODE (op) != REG) 1459 return FALSE; 1460 1461 return FPR_OR_PSEUDO_P (REGNO (op)); 1462}) 1463 1464;; Return 1 if operand is a 6-bit signed immediate. 1465 1466(define_predicate "int6_operand" 1467 (match_code "const_int") 1468{ 1469 if (GET_CODE (op) != CONST_INT) 1470 return FALSE; 1471 1472 return IN_RANGE (INTVAL (op), -32, 31); 1473}) 1474 1475;; Return 1 if operand is a 5-bit signed immediate. 1476 1477(define_predicate "int5_operand" 1478 (match_code "const_int") 1479{ 1480 return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), -16, 15); 1481}) 1482 1483;; Return 1 if operand is a 5-bit unsigned immediate. 1484 1485(define_predicate "uint5_operand" 1486 (match_code "const_int") 1487{ 1488 return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 31); 1489}) 1490 1491;; Return 1 if operand is a 4-bit unsigned immediate. 1492 1493(define_predicate "uint4_operand" 1494 (match_code "const_int") 1495{ 1496 return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 15); 1497}) 1498 1499;; Return 1 if operand is a 1-bit unsigned immediate (0 or 1). 1500 1501(define_predicate "uint1_operand" 1502 (match_code "const_int") 1503{ 1504 return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 1); 1505}) 1506 1507;; Return 1 if operand is a valid ACC register number. 1508 1509(define_predicate "acc_operand" 1510 (match_code "reg,subreg") 1511{ 1512 return ((mode == VOIDmode || mode == GET_MODE (op)) 1513 && REG_P (op) && ACC_P (REGNO (op)) 1514 && ((REGNO (op) - ACC_FIRST) & ~ACC_MASK) == 0); 1515}) 1516 1517;; Return 1 if operand is a valid even ACC register number. 1518 1519(define_predicate "even_acc_operand" 1520 (match_code "reg,subreg") 1521{ 1522 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 1) == 0; 1523}) 1524 1525;; Return 1 if operand is zero or four. 1526 1527(define_predicate "quad_acc_operand" 1528 (match_code "reg,subreg") 1529{ 1530 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 3) == 0; 1531}) 1532 1533;; Return 1 if operand is a valid ACCG register number. 1534 1535(define_predicate "accg_operand" 1536 (match_code "reg,subreg") 1537{ 1538 return ((mode == VOIDmode || mode == GET_MODE (op)) 1539 && REG_P (op) && ACCG_P (REGNO (op)) 1540 && ((REGNO (op) - ACCG_FIRST) & ~ACC_MASK) == 0); 1541}) 1542