1 /* Copyright (C) 1997-2019 Free Software Foundation, Inc. 2 Contributed by Red Hat, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #define IN_TARGET_CODE 1 21 22 #include "config.h" 23 #include "system.h" 24 #include "coretypes.h" 25 #include "backend.h" 26 #include "target.h" 27 #include "rtl.h" 28 #include "tree.h" 29 #include "df.h" 30 #include "memmodel.h" 31 #include "tm_p.h" 32 #include "stringpool.h" 33 #include "attribs.h" 34 #include "optabs.h" 35 #include "regs.h" 36 #include "emit-rtl.h" 37 #include "recog.h" 38 #include "diagnostic-core.h" 39 #include "fold-const.h" 40 #include "varasm.h" 41 #include "stor-layout.h" 42 #include "output.h" 43 #include "insn-attr.h" 44 #include "explow.h" 45 #include "expr.h" 46 #include "cfgrtl.h" 47 #include "langhooks.h" 48 #include "dumpfile.h" 49 #include "builtins.h" 50 #include "ifcvt.h" 51 #include "rtl-iter.h" 52 53 /* This file should be included last. */ 54 #include "target-def.h" 55 56 #ifndef FRV_INLINE 57 #define FRV_INLINE inline 58 #endif 59 60 /* The maximum number of distinct NOP patterns. There are three: 61 nop, fnop and mnop. */ 62 #define NUM_NOP_PATTERNS 3 63 64 /* Classification of instructions and units: integer, floating-point/media, 65 branch and control. */ 66 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS }; 67 68 /* The DFA names of the units, in packet order. */ 69 static const char *const frv_unit_names[] = 70 { 71 "c", 72 "i0", "f0", 73 "i1", "f1", 74 "i2", "f2", 75 "i3", "f3", 76 "b0", "b1" 77 }; 78 79 /* The classification of each unit in frv_unit_names[]. */ 80 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] = 81 { 82 GROUP_C, 83 GROUP_I, GROUP_FM, 84 GROUP_I, GROUP_FM, 85 GROUP_I, GROUP_FM, 86 GROUP_I, GROUP_FM, 87 GROUP_B, GROUP_B 88 }; 89 90 /* Return the DFA unit code associated with the Nth unit of integer 91 or floating-point group GROUP, */ 92 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1] 93 94 /* Return the number of integer or floating-point unit UNIT 95 (1 for I1, 2 for F2, etc.). */ 96 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2) 97 98 /* The DFA unit number for each unit in frv_unit_names[]. */ 99 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)]; 100 101 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue 102 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if 103 no instruction of type T has been seen. */ 104 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1]; 105 106 /* An array of dummy nop INSNs, one for each type of nop that the 107 target supports. */ 108 static GTY(()) rtx_insn *frv_nops[NUM_NOP_PATTERNS]; 109 110 /* The number of nop instructions in frv_nops[]. */ 111 static unsigned int frv_num_nops; 112 113 /* The type of access. FRV_IO_UNKNOWN means the access can be either 114 a read or a write. */ 115 enum frv_io_type { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE }; 116 117 /* Information about one __builtin_read or __builtin_write access, or 118 the combination of several such accesses. The most general value 119 is all-zeros (an unknown access to an unknown address). */ 120 struct frv_io { 121 enum frv_io_type type; 122 123 /* The constant address being accessed, or zero if not known. */ 124 HOST_WIDE_INT const_address; 125 126 /* The run-time address, as used in operand 0 of the membar pattern. */ 127 rtx var_address; 128 }; 129 130 /* Return true if instruction INSN should be packed with the following 131 instruction. */ 132 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode) 133 134 /* Set the value of PACKING_FLAG_P(INSN). */ 135 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode) 136 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode) 137 138 /* Loop with REG set to each hard register in rtx X. */ 139 #define FOR_EACH_REGNO(REG, X) \ 140 for (REG = REGNO (X); REG < END_REGNO (X); REG++) 141 142 /* This structure contains machine specific function data. */ 143 struct GTY(()) machine_function 144 { 145 /* True if we have created an rtx that relies on the stack frame. */ 146 int frame_needed; 147 148 /* True if this function contains at least one __builtin_{read,write}*. */ 149 bool has_membar_p; 150 }; 151 152 /* Temporary register allocation support structure. */ 153 typedef struct frv_tmp_reg_struct 154 { 155 HARD_REG_SET regs; /* possible registers to allocate */ 156 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */ 157 } 158 frv_tmp_reg_t; 159 160 /* Register state information for VLIW re-packing phase. */ 161 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */ 162 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */ 163 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */ 164 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */ 165 166 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE) 167 168 typedef unsigned char regstate_t; 169 170 /* Used in frv_frame_accessor_t to indicate the direction of a register-to- 171 memory move. */ 172 enum frv_stack_op 173 { 174 FRV_LOAD, 175 FRV_STORE 176 }; 177 178 /* Information required by frv_frame_access. */ 179 typedef struct 180 { 181 /* This field is FRV_LOAD if registers are to be loaded from the stack and 182 FRV_STORE if they should be stored onto the stack. FRV_STORE implies 183 the move is being done by the prologue code while FRV_LOAD implies it 184 is being done by the epilogue. */ 185 enum frv_stack_op op; 186 187 /* The base register to use when accessing the stack. This may be the 188 frame pointer, stack pointer, or a temporary. The choice of register 189 depends on which part of the frame is being accessed and how big the 190 frame is. */ 191 rtx base; 192 193 /* The offset of BASE from the bottom of the current frame, in bytes. */ 194 int base_offset; 195 } frv_frame_accessor_t; 196 197 /* Conditional execution support gathered together in one structure. */ 198 typedef struct 199 { 200 /* Linked list of insns to add if the conditional execution conversion was 201 successful. Each link points to an EXPR_LIST which points to the pattern 202 of the insn to add, and the insn to be inserted before. */ 203 rtx added_insns_list; 204 205 /* Identify which registers are safe to allocate for if conversions to 206 conditional execution. We keep the last allocated register in the 207 register classes between COND_EXEC statements. This will mean we allocate 208 different registers for each different COND_EXEC group if we can. This 209 might allow the scheduler to intermix two different COND_EXEC sections. */ 210 frv_tmp_reg_t tmp_reg; 211 212 /* For nested IFs, identify which CC registers are used outside of setting 213 via a compare isnsn, and using via a check insn. This will allow us to 214 know if we can rewrite the register to use a different register that will 215 be paired with the CR register controlling the nested IF-THEN blocks. */ 216 HARD_REG_SET nested_cc_ok_rewrite; 217 218 /* Temporary registers allocated to hold constants during conditional 219 execution. */ 220 rtx scratch_regs[FIRST_PSEUDO_REGISTER]; 221 222 /* Current number of temp registers available. */ 223 int cur_scratch_regs; 224 225 /* Number of nested conditional execution blocks. */ 226 int num_nested_cond_exec; 227 228 /* Map of insns that set up constants in scratch registers. */ 229 bitmap scratch_insns_bitmap; 230 231 /* Conditional execution test register (CC0..CC7). */ 232 rtx cr_reg; 233 234 /* Conditional execution compare register that is paired with cr_reg, so that 235 nested compares can be done. The csubcc and caddcc instructions don't 236 have enough bits to specify both a CC register to be set and a CR register 237 to do the test on, so the same bit number is used for both. Needless to 238 say, this is rather inconvenient for GCC. */ 239 rtx nested_cc_reg; 240 241 /* Extra CR registers used for &&, ||. */ 242 rtx extra_int_cr; 243 rtx extra_fp_cr; 244 245 /* Previous CR used in nested if, to make sure we are dealing with the same 246 nested if as the previous statement. */ 247 rtx last_nested_if_cr; 248 } 249 frv_ifcvt_t; 250 251 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt; 252 253 /* Map register number to smallest register class. */ 254 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; 255 256 /* Cached value of frv_stack_info. */ 257 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0; 258 259 /* Forward references */ 260 261 static void frv_option_override (void); 262 static bool frv_legitimate_address_p (machine_mode, rtx, bool); 263 static int frv_default_flags_for_cpu (void); 264 static int frv_string_begins_with (const char *, const char *); 265 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int); 266 static void frv_print_operand (FILE *, rtx, int); 267 static void frv_print_operand_address (FILE *, machine_mode, rtx); 268 static bool frv_print_operand_punct_valid_p (unsigned char code); 269 static void frv_print_operand_memory_reference_reg 270 (FILE *, rtx); 271 static void frv_print_operand_memory_reference (FILE *, rtx, int); 272 static int frv_print_operand_jump_hint (rtx_insn *); 273 static const char *comparison_string (enum rtx_code, rtx); 274 static rtx frv_function_value (const_tree, const_tree, 275 bool); 276 static rtx frv_libcall_value (machine_mode, 277 const_rtx); 278 static FRV_INLINE int frv_regno_ok_for_base_p (int, int); 279 static rtx single_set_pattern (rtx); 280 static int frv_function_contains_far_jump (void); 281 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *, 282 enum reg_class, 283 machine_mode, 284 int, int); 285 static rtx frv_frame_offset_rtx (int); 286 static rtx frv_frame_mem (machine_mode, rtx, int); 287 static rtx frv_dwarf_store (rtx, int); 288 static void frv_frame_insn (rtx, rtx); 289 static void frv_frame_access (frv_frame_accessor_t*, 290 rtx, int); 291 static void frv_frame_access_multi (frv_frame_accessor_t*, 292 frv_stack_t *, int); 293 static void frv_frame_access_standard_regs (enum frv_stack_op, 294 frv_stack_t *); 295 static struct machine_function *frv_init_machine_status (void); 296 static rtx frv_int_to_acc (enum insn_code, int, rtx); 297 static machine_mode frv_matching_accg_mode (machine_mode); 298 static rtx frv_read_argument (tree, unsigned int); 299 static rtx frv_read_iacc_argument (machine_mode, tree, unsigned int); 300 static int frv_check_constant_argument (enum insn_code, int, rtx); 301 static rtx frv_legitimize_target (enum insn_code, rtx); 302 static rtx frv_legitimize_argument (enum insn_code, int, rtx); 303 static rtx frv_legitimize_tls_address (rtx, enum tls_model); 304 static rtx frv_legitimize_address (rtx, rtx, machine_mode); 305 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx); 306 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx); 307 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx); 308 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx); 309 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx); 310 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree); 311 static rtx frv_expand_int_void2arg (enum insn_code, tree); 312 static rtx frv_expand_prefetches (enum insn_code, tree); 313 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree); 314 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree); 315 static rtx frv_expand_mclracc_builtin (tree); 316 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree); 317 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree); 318 static rtx frv_expand_noargs_builtin (enum insn_code); 319 static void frv_split_iacc_move (rtx, rtx); 320 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx); 321 static void frv_ifcvt_add_insn (rtx, rtx_insn *, int); 322 static rtx frv_ifcvt_rewrite_mem (rtx, machine_mode, rtx); 323 static rtx frv_ifcvt_load_value (rtx, rtx); 324 static unsigned int frv_insn_unit (rtx_insn *); 325 static bool frv_issues_to_branch_unit_p (rtx_insn *); 326 static int frv_cond_flags (rtx); 327 static bool frv_regstate_conflict_p (regstate_t, regstate_t); 328 static bool frv_registers_conflict_p (rtx); 329 static void frv_registers_update_1 (rtx, const_rtx, void *); 330 static void frv_registers_update (rtx); 331 static void frv_start_packet (void); 332 static void frv_start_packet_block (void); 333 static void frv_finish_packet (void (*) (void)); 334 static bool frv_pack_insn_p (rtx_insn *); 335 static void frv_add_insn_to_packet (rtx_insn *); 336 static void frv_insert_nop_in_packet (rtx_insn *); 337 static bool frv_for_each_packet (void (*) (void)); 338 static bool frv_sort_insn_group_1 (enum frv_insn_group, 339 unsigned int, unsigned int, 340 unsigned int, unsigned int, 341 state_t); 342 static int frv_compare_insns (const void *, const void *); 343 static void frv_sort_insn_group (enum frv_insn_group); 344 static void frv_reorder_packet (void); 345 static void frv_fill_unused_units (enum frv_insn_group); 346 static void frv_align_label (void); 347 static void frv_reorg_packet (void); 348 static void frv_register_nop (rtx); 349 static void frv_reorg (void); 350 static void frv_pack_insns (void); 351 static void frv_function_prologue (FILE *); 352 static void frv_function_epilogue (FILE *); 353 static bool frv_assemble_integer (rtx, unsigned, int); 354 static void frv_init_builtins (void); 355 static rtx frv_expand_builtin (tree, rtx, rtx, machine_mode, int); 356 static void frv_init_libfuncs (void); 357 static bool frv_in_small_data_p (const_tree); 358 static void frv_asm_output_mi_thunk 359 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); 360 static void frv_setup_incoming_varargs (cumulative_args_t, 361 machine_mode, 362 tree, int *, int); 363 static rtx frv_expand_builtin_saveregs (void); 364 static void frv_expand_builtin_va_start (tree, rtx); 365 static bool frv_rtx_costs (rtx, machine_mode, int, int, 366 int*, bool); 367 static int frv_register_move_cost (machine_mode, 368 reg_class_t, reg_class_t); 369 static int frv_memory_move_cost (machine_mode, 370 reg_class_t, bool); 371 static void frv_asm_out_constructor (rtx, int); 372 static void frv_asm_out_destructor (rtx, int); 373 static bool frv_function_symbol_referenced_p (rtx); 374 static bool frv_legitimate_constant_p (machine_mode, rtx); 375 static bool frv_cannot_force_const_mem (machine_mode, rtx); 376 static const char *unspec_got_name (int); 377 static void frv_output_const_unspec (FILE *, 378 const struct frv_unspec *); 379 static bool frv_function_ok_for_sibcall (tree, tree); 380 static rtx frv_struct_value_rtx (tree, int); 381 static bool frv_must_pass_in_stack (machine_mode mode, const_tree type); 382 static int frv_arg_partial_bytes (cumulative_args_t, machine_mode, 383 tree, bool); 384 static rtx frv_function_arg (cumulative_args_t, machine_mode, 385 const_tree, bool); 386 static rtx frv_function_incoming_arg (cumulative_args_t, machine_mode, 387 const_tree, bool); 388 static void frv_function_arg_advance (cumulative_args_t, machine_mode, 389 const_tree, bool); 390 static unsigned int frv_function_arg_boundary (machine_mode, 391 const_tree); 392 static void frv_output_dwarf_dtprel (FILE *, int, rtx) 393 ATTRIBUTE_UNUSED; 394 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t, 395 machine_mode, 396 secondary_reload_info *); 397 static bool frv_frame_pointer_required (void); 398 static bool frv_can_eliminate (const int, const int); 399 static void frv_conditional_register_usage (void); 400 static void frv_trampoline_init (rtx, tree, rtx); 401 static bool frv_class_likely_spilled_p (reg_class_t); 402 static unsigned int frv_hard_regno_nregs (unsigned int, machine_mode); 403 static bool frv_hard_regno_mode_ok (unsigned int, machine_mode); 404 static bool frv_modes_tieable_p (machine_mode, machine_mode); 405 406 /* Initialize the GCC target structure. */ 407 #undef TARGET_PRINT_OPERAND 408 #define TARGET_PRINT_OPERAND frv_print_operand 409 #undef TARGET_PRINT_OPERAND_ADDRESS 410 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address 411 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 412 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p 413 #undef TARGET_ASM_FUNCTION_PROLOGUE 414 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue 415 #undef TARGET_ASM_FUNCTION_EPILOGUE 416 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue 417 #undef TARGET_ASM_INTEGER 418 #define TARGET_ASM_INTEGER frv_assemble_integer 419 #undef TARGET_OPTION_OVERRIDE 420 #define TARGET_OPTION_OVERRIDE frv_option_override 421 #undef TARGET_INIT_BUILTINS 422 #define TARGET_INIT_BUILTINS frv_init_builtins 423 #undef TARGET_EXPAND_BUILTIN 424 #define TARGET_EXPAND_BUILTIN frv_expand_builtin 425 #undef TARGET_INIT_LIBFUNCS 426 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs 427 #undef TARGET_IN_SMALL_DATA_P 428 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p 429 #undef TARGET_REGISTER_MOVE_COST 430 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost 431 #undef TARGET_MEMORY_MOVE_COST 432 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost 433 #undef TARGET_RTX_COSTS 434 #define TARGET_RTX_COSTS frv_rtx_costs 435 #undef TARGET_ASM_CONSTRUCTOR 436 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor 437 #undef TARGET_ASM_DESTRUCTOR 438 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor 439 440 #undef TARGET_ASM_OUTPUT_MI_THUNK 441 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk 442 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 443 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 444 445 #undef TARGET_SCHED_ISSUE_RATE 446 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate 447 448 #undef TARGET_LEGITIMIZE_ADDRESS 449 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address 450 451 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 452 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall 453 #undef TARGET_LEGITIMATE_CONSTANT_P 454 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p 455 #undef TARGET_CANNOT_FORCE_CONST_MEM 456 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem 457 458 #undef TARGET_HAVE_TLS 459 #define TARGET_HAVE_TLS HAVE_AS_TLS 460 461 #undef TARGET_STRUCT_VALUE_RTX 462 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx 463 #undef TARGET_MUST_PASS_IN_STACK 464 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack 465 #undef TARGET_PASS_BY_REFERENCE 466 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack 467 #undef TARGET_ARG_PARTIAL_BYTES 468 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes 469 #undef TARGET_FUNCTION_ARG 470 #define TARGET_FUNCTION_ARG frv_function_arg 471 #undef TARGET_FUNCTION_INCOMING_ARG 472 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg 473 #undef TARGET_FUNCTION_ARG_ADVANCE 474 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance 475 #undef TARGET_FUNCTION_ARG_BOUNDARY 476 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary 477 478 #undef TARGET_EXPAND_BUILTIN_SAVEREGS 479 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs 480 #undef TARGET_SETUP_INCOMING_VARARGS 481 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs 482 #undef TARGET_MACHINE_DEPENDENT_REORG 483 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg 484 485 #undef TARGET_EXPAND_BUILTIN_VA_START 486 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start 487 488 #if HAVE_AS_TLS 489 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL 490 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel 491 #endif 492 493 #undef TARGET_CLASS_LIKELY_SPILLED_P 494 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p 495 496 #undef TARGET_SECONDARY_RELOAD 497 #define TARGET_SECONDARY_RELOAD frv_secondary_reload 498 499 #undef TARGET_LRA_P 500 #define TARGET_LRA_P hook_bool_void_false 501 502 #undef TARGET_LEGITIMATE_ADDRESS_P 503 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p 504 505 #undef TARGET_FRAME_POINTER_REQUIRED 506 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required 507 508 #undef TARGET_CAN_ELIMINATE 509 #define TARGET_CAN_ELIMINATE frv_can_eliminate 510 511 #undef TARGET_CONDITIONAL_REGISTER_USAGE 512 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage 513 514 #undef TARGET_TRAMPOLINE_INIT 515 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init 516 517 #undef TARGET_FUNCTION_VALUE 518 #define TARGET_FUNCTION_VALUE frv_function_value 519 #undef TARGET_LIBCALL_VALUE 520 #define TARGET_LIBCALL_VALUE frv_libcall_value 521 522 #undef TARGET_HARD_REGNO_NREGS 523 #define TARGET_HARD_REGNO_NREGS frv_hard_regno_nregs 524 #undef TARGET_HARD_REGNO_MODE_OK 525 #define TARGET_HARD_REGNO_MODE_OK frv_hard_regno_mode_ok 526 #undef TARGET_MODES_TIEABLE_P 527 #define TARGET_MODES_TIEABLE_P frv_modes_tieable_p 528 #undef TARGET_CONSTANT_ALIGNMENT 529 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings 530 531 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE 532 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed 533 534 struct gcc_target targetm = TARGET_INITIALIZER; 535 536 #define FRV_SYMBOL_REF_TLS_P(RTX) \ 537 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 538 539 540 /* Any function call that satisfies the machine-independent 541 requirements is eligible on FR-V. */ 542 543 static bool 544 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, 545 tree exp ATTRIBUTE_UNUSED) 546 { 547 return true; 548 } 549 550 /* Return true if SYMBOL is a small data symbol and relocation RELOC 551 can be used to access it directly in a load or store. */ 552 553 static FRV_INLINE bool 554 frv_small_data_reloc_p (rtx symbol, int reloc) 555 { 556 return (GET_CODE (symbol) == SYMBOL_REF 557 && SYMBOL_REF_SMALL_P (symbol) 558 && (!TARGET_FDPIC || flag_pic == 1) 559 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12)); 560 } 561 562 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC 563 appropriately. */ 564 565 bool 566 frv_const_unspec_p (rtx x, struct frv_unspec *unspec) 567 { 568 if (GET_CODE (x) == CONST) 569 { 570 unspec->offset = 0; 571 x = XEXP (x, 0); 572 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) 573 { 574 unspec->offset += INTVAL (XEXP (x, 1)); 575 x = XEXP (x, 0); 576 } 577 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT) 578 { 579 unspec->symbol = XVECEXP (x, 0, 0); 580 unspec->reloc = INTVAL (XVECEXP (x, 0, 1)); 581 582 if (unspec->offset == 0) 583 return true; 584 585 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc) 586 && unspec->offset > 0 587 && unspec->offset < g_switch_value) 588 return true; 589 } 590 } 591 return false; 592 } 593 594 /* Decide whether we can force certain constants to memory. If we 595 decide we can't, the caller should be able to cope with it in 596 another way. 597 598 We never allow constants to be forced into memory for TARGET_FDPIC. 599 This is necessary for several reasons: 600 601 1. Since frv_legitimate_constant_p rejects constant pool addresses, the 602 target-independent code will try to force them into the constant 603 pool, thus leading to infinite recursion. 604 605 2. We can never introduce new constant pool references during reload. 606 Any such reference would require use of the pseudo FDPIC register. 607 608 3. We can't represent a constant added to a function pointer (which is 609 not the same as a pointer to a function+constant). 610 611 4. In many cases, it's more efficient to calculate the constant in-line. */ 612 613 static bool 614 frv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, 615 rtx x ATTRIBUTE_UNUSED) 616 { 617 return TARGET_FDPIC; 618 } 619 620 static int 621 frv_default_flags_for_cpu (void) 622 { 623 switch (frv_cpu_type) 624 { 625 case FRV_CPU_GENERIC: 626 return MASK_DEFAULT_FRV; 627 628 case FRV_CPU_FR550: 629 return MASK_DEFAULT_FR550; 630 631 case FRV_CPU_FR500: 632 case FRV_CPU_TOMCAT: 633 return MASK_DEFAULT_FR500; 634 635 case FRV_CPU_FR450: 636 return MASK_DEFAULT_FR450; 637 638 case FRV_CPU_FR405: 639 case FRV_CPU_FR400: 640 return MASK_DEFAULT_FR400; 641 642 case FRV_CPU_FR300: 643 case FRV_CPU_SIMPLE: 644 return MASK_DEFAULT_SIMPLE; 645 646 default: 647 gcc_unreachable (); 648 } 649 } 650 651 /* Implement TARGET_OPTION_OVERRIDE. */ 652 653 static void 654 frv_option_override (void) 655 { 656 int regno; 657 unsigned int i; 658 659 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit); 660 661 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the 662 linker about linking pic and non-pic code. */ 663 if (TARGET_LIBPIC) 664 { 665 if (!flag_pic) /* -fPIC */ 666 flag_pic = 2; 667 668 if (!global_options_set.x_g_switch_value) /* -G0 */ 669 { 670 g_switch_value = 0; 671 } 672 } 673 674 /* A C expression whose value is a register class containing hard 675 register REGNO. In general there is more than one such class; 676 choose a class which is "minimal", meaning that no smaller class 677 also contains the register. */ 678 679 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 680 { 681 enum reg_class rclass; 682 683 if (GPR_P (regno)) 684 { 685 int gpr_reg = regno - GPR_FIRST; 686 687 if (gpr_reg == GR8_REG) 688 rclass = GR8_REGS; 689 690 else if (gpr_reg == GR9_REG) 691 rclass = GR9_REGS; 692 693 else if (gpr_reg == GR14_REG) 694 rclass = FDPIC_FPTR_REGS; 695 696 else if (gpr_reg == FDPIC_REGNO) 697 rclass = FDPIC_REGS; 698 699 else if ((gpr_reg & 3) == 0) 700 rclass = QUAD_REGS; 701 702 else if ((gpr_reg & 1) == 0) 703 rclass = EVEN_REGS; 704 705 else 706 rclass = GPR_REGS; 707 } 708 709 else if (FPR_P (regno)) 710 { 711 int fpr_reg = regno - GPR_FIRST; 712 if ((fpr_reg & 3) == 0) 713 rclass = QUAD_FPR_REGS; 714 715 else if ((fpr_reg & 1) == 0) 716 rclass = FEVEN_REGS; 717 718 else 719 rclass = FPR_REGS; 720 } 721 722 else if (regno == LR_REGNO) 723 rclass = LR_REG; 724 725 else if (regno == LCR_REGNO) 726 rclass = LCR_REG; 727 728 else if (ICC_P (regno)) 729 rclass = ICC_REGS; 730 731 else if (FCC_P (regno)) 732 rclass = FCC_REGS; 733 734 else if (ICR_P (regno)) 735 rclass = ICR_REGS; 736 737 else if (FCR_P (regno)) 738 rclass = FCR_REGS; 739 740 else if (ACC_P (regno)) 741 { 742 int r = regno - ACC_FIRST; 743 if ((r & 3) == 0) 744 rclass = QUAD_ACC_REGS; 745 else if ((r & 1) == 0) 746 rclass = EVEN_ACC_REGS; 747 else 748 rclass = ACC_REGS; 749 } 750 751 else if (ACCG_P (regno)) 752 rclass = ACCG_REGS; 753 754 else 755 rclass = NO_REGS; 756 757 regno_reg_class[regno] = rclass; 758 } 759 760 /* Check for small data option */ 761 if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC) 762 g_switch_value = SDATA_DEFAULT_SIZE; 763 764 /* There is no single unaligned SI op for PIC code. Sometimes we 765 need to use ".4byte" and sometimes we need to use ".picptr". 766 See frv_assemble_integer for details. */ 767 if (flag_pic || TARGET_FDPIC) 768 targetm.asm_out.unaligned_op.si = 0; 769 770 if ((target_flags_explicit & MASK_LINKED_FP) == 0) 771 target_flags |= MASK_LINKED_FP; 772 773 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0) 774 target_flags |= MASK_OPTIMIZE_MEMBAR; 775 776 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++) 777 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]); 778 779 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++) 780 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes); 781 782 init_machine_status = frv_init_machine_status; 783 } 784 785 786 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */ 787 788 static int 789 frv_string_begins_with (const char *name, const char *prefix) 790 { 791 const int prefix_len = strlen (prefix); 792 793 /* Remember: NAME's length includes the null terminator. */ 794 return (strncmp (name, prefix, prefix_len) == 0); 795 } 796 797 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ 798 799 static void 800 frv_conditional_register_usage (void) 801 { 802 int i; 803 804 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++) 805 fixed_regs[i] = call_used_regs[i] = 1; 806 807 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++) 808 fixed_regs[i] = call_used_regs[i] = 1; 809 810 /* Reserve the registers used for conditional execution. At present, we need 811 1 ICC and 1 ICR register. */ 812 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1; 813 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1; 814 815 if (TARGET_FIXED_CC) 816 { 817 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1; 818 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1; 819 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1; 820 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1; 821 } 822 823 if (TARGET_FDPIC) 824 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] = 825 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0; 826 827 #if 0 828 /* If -fpic, SDA_BASE_REG is the PIC register. */ 829 if (g_switch_value == 0 && !flag_pic) 830 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0; 831 832 if (!flag_pic) 833 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0; 834 #endif 835 } 836 837 838 /* 839 * Compute the stack frame layout 840 * 841 * Register setup: 842 * +---------------+-----------------------+-----------------------+ 843 * |Register |type |caller-save/callee-save| 844 * +---------------+-----------------------+-----------------------+ 845 * |GR0 |Zero register | - | 846 * |GR1 |Stack pointer(SP) | - | 847 * |GR2 |Frame pointer(FP) | - | 848 * |GR3 |Hidden parameter | caller save | 849 * |GR4-GR7 | - | caller save | 850 * |GR8-GR13 |Argument register | caller save | 851 * |GR14-GR15 | - | caller save | 852 * |GR16-GR31 | - | callee save | 853 * |GR32-GR47 | - | caller save | 854 * |GR48-GR63 | - | callee save | 855 * |FR0-FR15 | - | caller save | 856 * |FR16-FR31 | - | callee save | 857 * |FR32-FR47 | - | caller save | 858 * |FR48-FR63 | - | callee save | 859 * +---------------+-----------------------+-----------------------+ 860 * 861 * Stack frame setup: 862 * Low 863 * SP-> |-----------------------------------| 864 * | Argument area | 865 * |-----------------------------------| 866 * | Register save area | 867 * |-----------------------------------| 868 * | Local variable save area | 869 * FP-> |-----------------------------------| 870 * | Old FP | 871 * |-----------------------------------| 872 * | Hidden parameter save area | 873 * |-----------------------------------| 874 * | Return address(LR) storage area | 875 * |-----------------------------------| 876 * | Padding for alignment | 877 * |-----------------------------------| 878 * | Register argument area | 879 * OLD SP-> |-----------------------------------| 880 * | Parameter area | 881 * |-----------------------------------| 882 * High 883 * 884 * Argument area/Parameter area: 885 * 886 * When a function is called, this area is used for argument transfer. When 887 * the argument is set up by the caller function, this area is referred to as 888 * the argument area. When the argument is referenced by the callee function, 889 * this area is referred to as the parameter area. The area is allocated when 890 * all arguments cannot be placed on the argument register at the time of 891 * argument transfer. 892 * 893 * Register save area: 894 * 895 * This is a register save area that must be guaranteed for the caller 896 * function. This area is not secured when the register save operation is not 897 * needed. 898 * 899 * Local variable save area: 900 * 901 * This is the area for local variables and temporary variables. 902 * 903 * Old FP: 904 * 905 * This area stores the FP value of the caller function. 906 * 907 * Hidden parameter save area: 908 * 909 * This area stores the start address of the return value storage 910 * area for a struct/union return function. 911 * When a struct/union is used as the return value, the caller 912 * function stores the return value storage area start address in 913 * register GR3 and passes it to the caller function. 914 * The callee function interprets the address stored in the GR3 915 * as the return value storage area start address. 916 * When register GR3 needs to be saved into memory, the callee 917 * function saves it in the hidden parameter save area. This 918 * area is not secured when the save operation is not needed. 919 * 920 * Return address(LR) storage area: 921 * 922 * This area saves the LR. The LR stores the address of a return to the caller 923 * function for the purpose of function calling. 924 * 925 * Argument register area: 926 * 927 * This area saves the argument register. This area is not secured when the 928 * save operation is not needed. 929 * 930 * Argument: 931 * 932 * Arguments, the count of which equals the count of argument registers (6 933 * words), are positioned in registers GR8 to GR13 and delivered to the callee 934 * function. When a struct/union return function is called, the return value 935 * area address is stored in register GR3. Arguments not placed in the 936 * argument registers will be stored in the stack argument area for transfer 937 * purposes. When an 8-byte type argument is to be delivered using registers, 938 * it is divided into two and placed in two registers for transfer. When 939 * argument registers must be saved to memory, the callee function secures an 940 * argument register save area in the stack. In this case, a continuous 941 * argument register save area must be established in the parameter area. The 942 * argument register save area must be allocated as needed to cover the size of 943 * the argument register to be saved. If the function has a variable count of 944 * arguments, it saves all argument registers in the argument register save 945 * area. 946 * 947 * Argument Extension Format: 948 * 949 * When an argument is to be stored in the stack, its type is converted to an 950 * extended type in accordance with the individual argument type. The argument 951 * is freed by the caller function after the return from the callee function is 952 * made. 953 * 954 * +-----------------------+---------------+------------------------+ 955 * | Argument Type |Extended Type |Stack Storage Size(byte)| 956 * +-----------------------+---------------+------------------------+ 957 * |char |int | 4 | 958 * |signed char |int | 4 | 959 * |unsigned char |int | 4 | 960 * |[signed] short int |int | 4 | 961 * |unsigned short int |int | 4 | 962 * |[signed] int |No extension | 4 | 963 * |unsigned int |No extension | 4 | 964 * |[signed] long int |No extension | 4 | 965 * |unsigned long int |No extension | 4 | 966 * |[signed] long long int |No extension | 8 | 967 * |unsigned long long int |No extension | 8 | 968 * |float |double | 8 | 969 * |double |No extension | 8 | 970 * |long double |No extension | 8 | 971 * |pointer |No extension | 4 | 972 * |struct/union |- | 4 (*1) | 973 * +-----------------------+---------------+------------------------+ 974 * 975 * When a struct/union is to be delivered as an argument, the caller copies it 976 * to the local variable area and delivers the address of that area. 977 * 978 * Return Value: 979 * 980 * +-------------------------------+----------------------+ 981 * |Return Value Type |Return Value Interface| 982 * +-------------------------------+----------------------+ 983 * |void |None | 984 * |[signed|unsigned] char |GR8 | 985 * |[signed|unsigned] short int |GR8 | 986 * |[signed|unsigned] int |GR8 | 987 * |[signed|unsigned] long int |GR8 | 988 * |pointer |GR8 | 989 * |[signed|unsigned] long long int|GR8 & GR9 | 990 * |float |GR8 | 991 * |double |GR8 & GR9 | 992 * |long double |GR8 & GR9 | 993 * |struct/union |(*1) | 994 * +-------------------------------+----------------------+ 995 * 996 * When a struct/union is used as the return value, the caller function stores 997 * the start address of the return value storage area into GR3 and then passes 998 * it to the callee function. The callee function interprets GR3 as the start 999 * address of the return value storage area. When this address needs to be 1000 * saved in memory, the callee function secures the hidden parameter save area 1001 * and saves the address in that area. 1002 */ 1003 1004 frv_stack_t * 1005 frv_stack_info (void) 1006 { 1007 static frv_stack_t info, zero_info; 1008 frv_stack_t *info_ptr = &info; 1009 tree fndecl = current_function_decl; 1010 int varargs_p = 0; 1011 tree cur_arg; 1012 tree next_arg; 1013 int range; 1014 int alignment; 1015 int offset; 1016 1017 /* If we've already calculated the values and reload is complete, 1018 just return now. */ 1019 if (frv_stack_cache) 1020 return frv_stack_cache; 1021 1022 /* Zero all fields. */ 1023 info = zero_info; 1024 1025 /* Set up the register range information. */ 1026 info_ptr->regs[STACK_REGS_GPR].name = "gpr"; 1027 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1; 1028 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST; 1029 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE; 1030 1031 info_ptr->regs[STACK_REGS_FPR].name = "fpr"; 1032 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST; 1033 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST; 1034 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE; 1035 1036 info_ptr->regs[STACK_REGS_LR].name = "lr"; 1037 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO; 1038 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO; 1039 info_ptr->regs[STACK_REGS_LR].special_p = 1; 1040 1041 info_ptr->regs[STACK_REGS_CC].name = "cc"; 1042 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST; 1043 info_ptr->regs[STACK_REGS_CC].last = CC_LAST; 1044 info_ptr->regs[STACK_REGS_CC].field_p = TRUE; 1045 1046 info_ptr->regs[STACK_REGS_LCR].name = "lcr"; 1047 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO; 1048 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO; 1049 1050 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg"; 1051 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM; 1052 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM; 1053 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1; 1054 info_ptr->regs[STACK_REGS_STDARG].special_p = 1; 1055 1056 info_ptr->regs[STACK_REGS_STRUCT].name = "struct"; 1057 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM; 1058 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM; 1059 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1; 1060 1061 info_ptr->regs[STACK_REGS_FP].name = "fp"; 1062 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM; 1063 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM; 1064 info_ptr->regs[STACK_REGS_FP].special_p = 1; 1065 1066 /* Determine if this is a stdarg function. If so, allocate space to store 1067 the 6 arguments. */ 1068 if (cfun->stdarg) 1069 varargs_p = 1; 1070 1071 else 1072 { 1073 /* Find the last argument, and see if it is __builtin_va_alist. */ 1074 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg) 1075 { 1076 next_arg = DECL_CHAIN (cur_arg); 1077 if (next_arg == (tree)0) 1078 { 1079 if (DECL_NAME (cur_arg) 1080 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist")) 1081 varargs_p = 1; 1082 1083 break; 1084 } 1085 } 1086 } 1087 1088 /* Iterate over all of the register ranges. */ 1089 for (range = 0; range < STACK_REGS_MAX; range++) 1090 { 1091 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); 1092 int first = reg_ptr->first; 1093 int last = reg_ptr->last; 1094 int size_1word = 0; 1095 int size_2words = 0; 1096 int regno; 1097 1098 /* Calculate which registers need to be saved & save area size. */ 1099 switch (range) 1100 { 1101 default: 1102 for (regno = first; regno <= last; regno++) 1103 { 1104 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno]) 1105 || (crtl->calls_eh_return 1106 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM)) 1107 || (!TARGET_FDPIC && flag_pic 1108 && crtl->uses_pic_offset_table && regno == PIC_REGNO)) 1109 { 1110 info_ptr->save_p[regno] = REG_SAVE_1WORD; 1111 size_1word += UNITS_PER_WORD; 1112 } 1113 } 1114 break; 1115 1116 /* Calculate whether we need to create a frame after everything else 1117 has been processed. */ 1118 case STACK_REGS_FP: 1119 break; 1120 1121 case STACK_REGS_LR: 1122 if (df_regs_ever_live_p (LR_REGNO) 1123 || profile_flag 1124 /* This is set for __builtin_return_address, etc. */ 1125 || cfun->machine->frame_needed 1126 || (TARGET_LINKED_FP && frame_pointer_needed) 1127 || (!TARGET_FDPIC && flag_pic 1128 && crtl->uses_pic_offset_table)) 1129 { 1130 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; 1131 size_1word += UNITS_PER_WORD; 1132 } 1133 break; 1134 1135 case STACK_REGS_STDARG: 1136 if (varargs_p) 1137 { 1138 /* If this is a stdarg function with a non varardic 1139 argument split between registers and the stack, 1140 adjust the saved registers downward. */ 1141 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD) 1142 / UNITS_PER_WORD); 1143 1144 for (regno = first; regno <= last; regno++) 1145 { 1146 info_ptr->save_p[regno] = REG_SAVE_1WORD; 1147 size_1word += UNITS_PER_WORD; 1148 } 1149 1150 info_ptr->stdarg_size = size_1word; 1151 } 1152 break; 1153 1154 case STACK_REGS_STRUCT: 1155 if (cfun->returns_struct) 1156 { 1157 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; 1158 size_1word += UNITS_PER_WORD; 1159 } 1160 break; 1161 } 1162 1163 1164 if (size_1word) 1165 { 1166 /* If this is a field, it only takes one word. */ 1167 if (reg_ptr->field_p) 1168 size_1word = UNITS_PER_WORD; 1169 1170 /* Determine which register pairs can be saved together. */ 1171 else if (reg_ptr->dword_p && TARGET_DWORD) 1172 { 1173 for (regno = first; regno < last; regno += 2) 1174 { 1175 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1]) 1176 { 1177 size_2words += 2 * UNITS_PER_WORD; 1178 size_1word -= 2 * UNITS_PER_WORD; 1179 info_ptr->save_p[regno] = REG_SAVE_2WORDS; 1180 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE; 1181 } 1182 } 1183 } 1184 1185 reg_ptr->size_1word = size_1word; 1186 reg_ptr->size_2words = size_2words; 1187 1188 if (! reg_ptr->special_p) 1189 { 1190 info_ptr->regs_size_1word += size_1word; 1191 info_ptr->regs_size_2words += size_2words; 1192 } 1193 } 1194 } 1195 1196 /* Set up the sizes of each field in the frame body, making the sizes 1197 of each be divisible by the size of a dword if dword operations might 1198 be used, or the size of a word otherwise. */ 1199 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD); 1200 1201 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment); 1202 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words 1203 + info_ptr->regs_size_1word, 1204 alignment); 1205 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment); 1206 1207 info_ptr->pretend_size = crtl->args.pretend_args_size; 1208 1209 /* Work out the size of the frame, excluding the header. Both the frame 1210 body and register parameter area will be dword-aligned. */ 1211 info_ptr->total_size 1212 = (ADDR_ALIGN (info_ptr->parameter_size 1213 + info_ptr->regs_size 1214 + info_ptr->vars_size, 1215 2 * UNITS_PER_WORD) 1216 + ADDR_ALIGN (info_ptr->pretend_size 1217 + info_ptr->stdarg_size, 1218 2 * UNITS_PER_WORD)); 1219 1220 /* See if we need to create a frame at all, if so add header area. */ 1221 if (info_ptr->total_size > 0 1222 || frame_pointer_needed 1223 || info_ptr->regs[STACK_REGS_LR].size_1word > 0 1224 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0) 1225 { 1226 offset = info_ptr->parameter_size; 1227 info_ptr->header_size = 4 * UNITS_PER_WORD; 1228 info_ptr->total_size += 4 * UNITS_PER_WORD; 1229 1230 /* Calculate the offsets to save normal register pairs. */ 1231 for (range = 0; range < STACK_REGS_MAX; range++) 1232 { 1233 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); 1234 if (! reg_ptr->special_p) 1235 { 1236 int first = reg_ptr->first; 1237 int last = reg_ptr->last; 1238 int regno; 1239 1240 for (regno = first; regno <= last; regno++) 1241 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS 1242 && regno != FRAME_POINTER_REGNUM 1243 && (regno < FIRST_ARG_REGNUM 1244 || regno > LAST_ARG_REGNUM)) 1245 { 1246 info_ptr->reg_offset[regno] = offset; 1247 offset += 2 * UNITS_PER_WORD; 1248 } 1249 } 1250 } 1251 1252 /* Calculate the offsets to save normal single registers. */ 1253 for (range = 0; range < STACK_REGS_MAX; range++) 1254 { 1255 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); 1256 if (! reg_ptr->special_p) 1257 { 1258 int first = reg_ptr->first; 1259 int last = reg_ptr->last; 1260 int regno; 1261 1262 for (regno = first; regno <= last; regno++) 1263 if (info_ptr->save_p[regno] == REG_SAVE_1WORD 1264 && regno != FRAME_POINTER_REGNUM 1265 && (regno < FIRST_ARG_REGNUM 1266 || regno > LAST_ARG_REGNUM)) 1267 { 1268 info_ptr->reg_offset[regno] = offset; 1269 offset += UNITS_PER_WORD; 1270 } 1271 } 1272 } 1273 1274 /* Calculate the offset to save the local variables at. */ 1275 offset = ADDR_ALIGN (offset, alignment); 1276 if (info_ptr->vars_size) 1277 { 1278 info_ptr->vars_offset = offset; 1279 offset += info_ptr->vars_size; 1280 } 1281 1282 /* Align header to a dword-boundary. */ 1283 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD); 1284 1285 /* Calculate the offsets in the fixed frame. */ 1286 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD; 1287 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset; 1288 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD; 1289 1290 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; 1291 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD; 1292 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD; 1293 1294 if (cfun->returns_struct) 1295 { 1296 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; 1297 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD; 1298 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD; 1299 } 1300 1301 /* Calculate the offsets to store the arguments passed in registers 1302 for stdarg functions. The register pairs are first and the single 1303 register if any is last. The register save area starts on a 1304 dword-boundary. */ 1305 if (info_ptr->stdarg_size) 1306 { 1307 int first = info_ptr->regs[STACK_REGS_STDARG].first; 1308 int last = info_ptr->regs[STACK_REGS_STDARG].last; 1309 int regno; 1310 1311 /* Skip the header. */ 1312 offset += 4 * UNITS_PER_WORD; 1313 for (regno = first; regno <= last; regno++) 1314 { 1315 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS) 1316 { 1317 info_ptr->reg_offset[regno] = offset; 1318 offset += 2 * UNITS_PER_WORD; 1319 } 1320 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD) 1321 { 1322 info_ptr->reg_offset[regno] = offset; 1323 offset += UNITS_PER_WORD; 1324 } 1325 } 1326 } 1327 } 1328 1329 if (reload_completed) 1330 frv_stack_cache = info_ptr; 1331 1332 return info_ptr; 1333 } 1334 1335 1336 /* Print the information about the frv stack offsets, etc. when debugging. */ 1337 1338 void 1339 frv_debug_stack (frv_stack_t *info) 1340 { 1341 int range; 1342 1343 if (!info) 1344 info = frv_stack_info (); 1345 1346 fprintf (stderr, "\nStack information for function %s:\n", 1347 ((current_function_decl && DECL_NAME (current_function_decl)) 1348 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) 1349 : "<unknown>")); 1350 1351 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size); 1352 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size); 1353 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size); 1354 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n", 1355 info->regs_size, info->regs_size_1word, info->regs_size_2words); 1356 1357 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size); 1358 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size); 1359 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset); 1360 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset); 1361 1362 for (range = 0; range < STACK_REGS_MAX; range++) 1363 { 1364 frv_stack_regs_t *regs = &(info->regs[range]); 1365 if ((regs->size_1word + regs->size_2words) > 0) 1366 { 1367 int first = regs->first; 1368 int last = regs->last; 1369 int regno; 1370 1371 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =", 1372 regs->name, regs->size_1word + regs->size_2words, 1373 regs->size_1word, regs->size_2words); 1374 1375 for (regno = first; regno <= last; regno++) 1376 { 1377 if (info->save_p[regno] == REG_SAVE_1WORD) 1378 fprintf (stderr, " %s (%d)", reg_names[regno], 1379 info->reg_offset[regno]); 1380 1381 else if (info->save_p[regno] == REG_SAVE_2WORDS) 1382 fprintf (stderr, " %s-%s (%d)", reg_names[regno], 1383 reg_names[regno+1], info->reg_offset[regno]); 1384 } 1385 1386 fputc ('\n', stderr); 1387 } 1388 } 1389 1390 fflush (stderr); 1391 } 1392 1393 1394 1395 1396 /* Used during final to control the packing of insns. The value is 1397 1 if the current instruction should be packed with the next one, 1398 0 if it shouldn't or -1 if packing is disabled altogether. */ 1399 1400 static int frv_insn_packing_flag; 1401 1402 /* True if the current function contains a far jump. */ 1403 1404 static int 1405 frv_function_contains_far_jump (void) 1406 { 1407 rtx_insn *insn = get_insns (); 1408 while (insn != NULL 1409 && !(JUMP_P (insn) 1410 && get_attr_far_jump (insn) == FAR_JUMP_YES)) 1411 insn = NEXT_INSN (insn); 1412 return (insn != NULL); 1413 } 1414 1415 /* For the FRV, this function makes sure that a function with far jumps 1416 will return correctly. It also does the VLIW packing. */ 1417 1418 static void 1419 frv_function_prologue (FILE *file) 1420 { 1421 /* If no frame was created, check whether the function uses a call 1422 instruction to implement a far jump. If so, save the link in gr3 and 1423 replace all returns to LR with returns to GR3. GR3 is used because it 1424 is call-clobbered, because is not available to the register allocator, 1425 and because all functions that take a hidden argument pointer will have 1426 a stack frame. */ 1427 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ()) 1428 { 1429 rtx_insn *insn; 1430 1431 /* Just to check that the above comment is true. */ 1432 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3)); 1433 1434 /* Generate the instruction that saves the link register. */ 1435 fprintf (file, "\tmovsg lr,gr3\n"); 1436 1437 /* Replace the LR with GR3 in *return_internal patterns. The insn 1438 will now return using jmpl @(gr3,0) rather than bralr. We cannot 1439 simply emit a different assembly directive because bralr and jmpl 1440 execute in different units. */ 1441 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn)) 1442 if (JUMP_P (insn)) 1443 { 1444 rtx pattern = PATTERN (insn); 1445 if (GET_CODE (pattern) == PARALLEL 1446 && XVECLEN (pattern, 0) >= 2 1447 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN 1448 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE) 1449 { 1450 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0); 1451 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO) 1452 SET_REGNO (address, GPR_FIRST + 3); 1453 } 1454 } 1455 } 1456 1457 frv_pack_insns (); 1458 1459 /* Allow the garbage collector to free the nops created by frv_reorg. */ 1460 memset (frv_nops, 0, sizeof (frv_nops)); 1461 } 1462 1463 1464 /* Return the next available temporary register in a given class. */ 1465 1466 static rtx 1467 frv_alloc_temp_reg ( 1468 frv_tmp_reg_t *info, /* which registers are available */ 1469 enum reg_class rclass, /* register class desired */ 1470 machine_mode mode, /* mode to allocate register with */ 1471 int mark_as_used, /* register not available after allocation */ 1472 int no_abort) /* return NULL instead of aborting */ 1473 { 1474 int regno = info->next_reg[ (int)rclass ]; 1475 int orig_regno = regno; 1476 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ]; 1477 int i, nr; 1478 1479 for (;;) 1480 { 1481 if (TEST_HARD_REG_BIT (*reg_in_class, regno) 1482 && TEST_HARD_REG_BIT (info->regs, regno)) 1483 break; 1484 1485 if (++regno >= FIRST_PSEUDO_REGISTER) 1486 regno = 0; 1487 if (regno == orig_regno) 1488 { 1489 gcc_assert (no_abort); 1490 return NULL_RTX; 1491 } 1492 } 1493 1494 nr = hard_regno_nregs (regno, mode); 1495 info->next_reg[ (int)rclass ] = regno + nr; 1496 1497 if (mark_as_used) 1498 for (i = 0; i < nr; i++) 1499 CLEAR_HARD_REG_BIT (info->regs, regno+i); 1500 1501 return gen_rtx_REG (mode, regno); 1502 } 1503 1504 1505 /* Return an rtx with the value OFFSET, which will either be a register or a 1506 signed 12-bit integer. It can be used as the second operand in an "add" 1507 instruction, or as the index in a load or store. 1508 1509 The function returns a constant rtx if OFFSET is small enough, otherwise 1510 it loads the constant into register OFFSET_REGNO and returns that. */ 1511 static rtx 1512 frv_frame_offset_rtx (int offset) 1513 { 1514 rtx offset_rtx = GEN_INT (offset); 1515 if (IN_RANGE (offset, -2048, 2047)) 1516 return offset_rtx; 1517 else 1518 { 1519 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO); 1520 if (IN_RANGE (offset, -32768, 32767)) 1521 emit_insn (gen_movsi (reg_rtx, offset_rtx)); 1522 else 1523 { 1524 emit_insn (gen_movsi_high (reg_rtx, offset_rtx)); 1525 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx)); 1526 } 1527 return reg_rtx; 1528 } 1529 } 1530 1531 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The 1532 prologue and epilogue uses such expressions to access the stack. */ 1533 static rtx 1534 frv_frame_mem (machine_mode mode, rtx base, int offset) 1535 { 1536 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, 1537 base, 1538 frv_frame_offset_rtx (offset))); 1539 } 1540 1541 /* Generate a frame-related expression: 1542 1543 (set REG (mem (plus (sp) (const_int OFFSET)))). 1544 1545 Such expressions are used in FRAME_RELATED_EXPR notes for more complex 1546 instructions. Marking the expressions as frame-related is superfluous if 1547 the note contains just a single set. But if the note contains a PARALLEL 1548 or SEQUENCE that has several sets, each set must be individually marked 1549 as frame-related. */ 1550 static rtx 1551 frv_dwarf_store (rtx reg, int offset) 1552 { 1553 rtx set = gen_rtx_SET (gen_rtx_MEM (GET_MODE (reg), 1554 plus_constant (Pmode, stack_pointer_rtx, 1555 offset)), 1556 reg); 1557 RTX_FRAME_RELATED_P (set) = 1; 1558 return set; 1559 } 1560 1561 /* Emit a frame-related instruction whose pattern is PATTERN. The 1562 instruction is the last in a sequence that cumulatively performs the 1563 operation described by DWARF_PATTERN. The instruction is marked as 1564 frame-related and has a REG_FRAME_RELATED_EXPR note containing 1565 DWARF_PATTERN. */ 1566 static void 1567 frv_frame_insn (rtx pattern, rtx dwarf_pattern) 1568 { 1569 rtx insn = emit_insn (pattern); 1570 RTX_FRAME_RELATED_P (insn) = 1; 1571 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, 1572 dwarf_pattern, 1573 REG_NOTES (insn)); 1574 } 1575 1576 /* Emit instructions that transfer REG to or from the memory location (sp + 1577 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is 1578 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this 1579 function to store registers and only the epilogue uses it to load them. 1580 1581 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET). 1582 The generated instruction will use BASE as its base register. BASE may 1583 simply be the stack pointer, but if several accesses are being made to a 1584 region far away from the stack pointer, it may be more efficient to set 1585 up a temporary instead. 1586 1587 Store instructions will be frame-related and will be annotated with the 1588 overall effect of the store. Load instructions will be followed by a 1589 (use) to prevent later optimizations from zapping them. 1590 1591 The function takes care of the moves to and from SPRs, using TEMP_REGNO 1592 as a temporary in such cases. */ 1593 static void 1594 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) 1595 { 1596 machine_mode mode = GET_MODE (reg); 1597 rtx mem = frv_frame_mem (mode, 1598 accessor->base, 1599 stack_offset - accessor->base_offset); 1600 1601 if (accessor->op == FRV_LOAD) 1602 { 1603 if (SPR_P (REGNO (reg))) 1604 { 1605 rtx temp = gen_rtx_REG (mode, TEMP_REGNO); 1606 emit_insn (gen_rtx_SET (temp, mem)); 1607 emit_insn (gen_rtx_SET (reg, temp)); 1608 } 1609 else 1610 { 1611 /* We cannot use reg+reg addressing for DImode access. */ 1612 if (mode == DImode 1613 && GET_CODE (XEXP (mem, 0)) == PLUS 1614 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG 1615 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) 1616 { 1617 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); 1618 1619 emit_move_insn (temp, 1620 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), 1621 XEXP (XEXP (mem, 0), 1))); 1622 mem = gen_rtx_MEM (DImode, temp); 1623 } 1624 emit_insn (gen_rtx_SET (reg, mem)); 1625 } 1626 emit_use (reg); 1627 } 1628 else 1629 { 1630 if (SPR_P (REGNO (reg))) 1631 { 1632 rtx temp = gen_rtx_REG (mode, TEMP_REGNO); 1633 emit_insn (gen_rtx_SET (temp, reg)); 1634 frv_frame_insn (gen_rtx_SET (mem, temp), 1635 frv_dwarf_store (reg, stack_offset)); 1636 } 1637 else if (mode == DImode) 1638 { 1639 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE 1640 with a separate save for each register. */ 1641 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg)); 1642 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1); 1643 rtx set1 = frv_dwarf_store (reg1, stack_offset); 1644 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4); 1645 1646 /* Also we cannot use reg+reg addressing. */ 1647 if (GET_CODE (XEXP (mem, 0)) == PLUS 1648 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG 1649 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) 1650 { 1651 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); 1652 emit_move_insn (temp, 1653 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), 1654 XEXP (XEXP (mem, 0), 1))); 1655 mem = gen_rtx_MEM (DImode, temp); 1656 } 1657 1658 frv_frame_insn (gen_rtx_SET (mem, reg), 1659 gen_rtx_PARALLEL (VOIDmode, 1660 gen_rtvec (2, set1, set2))); 1661 } 1662 else 1663 frv_frame_insn (gen_rtx_SET (mem, reg), 1664 frv_dwarf_store (reg, stack_offset)); 1665 } 1666 } 1667 1668 /* A function that uses frv_frame_access to transfer a group of registers to 1669 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO 1670 is the stack information generated by frv_stack_info, and REG_SET is the 1671 number of the register set to transfer. */ 1672 static void 1673 frv_frame_access_multi (frv_frame_accessor_t *accessor, 1674 frv_stack_t *info, 1675 int reg_set) 1676 { 1677 frv_stack_regs_t *regs_info; 1678 int regno; 1679 1680 regs_info = &info->regs[reg_set]; 1681 for (regno = regs_info->first; regno <= regs_info->last; regno++) 1682 if (info->save_p[regno]) 1683 frv_frame_access (accessor, 1684 info->save_p[regno] == REG_SAVE_2WORDS 1685 ? gen_rtx_REG (DImode, regno) 1686 : gen_rtx_REG (SImode, regno), 1687 info->reg_offset[regno]); 1688 } 1689 1690 /* Save or restore callee-saved registers that are kept outside the frame 1691 header. The function saves the registers if OP is FRV_STORE and restores 1692 them if OP is FRV_LOAD. INFO is the stack information generated by 1693 frv_stack_info. */ 1694 static void 1695 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info) 1696 { 1697 frv_frame_accessor_t accessor; 1698 1699 accessor.op = op; 1700 accessor.base = stack_pointer_rtx; 1701 accessor.base_offset = 0; 1702 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR); 1703 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR); 1704 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR); 1705 } 1706 1707 1708 /* Called after register allocation to add any instructions needed for the 1709 prologue. Using a prologue insn is favored compared to putting all of the 1710 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since 1711 it allows the scheduler to intermix instructions with the saves of 1712 the caller saved registers. In some cases, it might be necessary 1713 to emit a barrier instruction as the last insn to prevent such 1714 scheduling. 1715 1716 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 1717 so that the debug info generation code can handle them properly. */ 1718 void 1719 frv_expand_prologue (void) 1720 { 1721 frv_stack_t *info = frv_stack_info (); 1722 rtx sp = stack_pointer_rtx; 1723 rtx fp = frame_pointer_rtx; 1724 frv_frame_accessor_t accessor; 1725 1726 if (TARGET_DEBUG_STACK) 1727 frv_debug_stack (info); 1728 1729 if (flag_stack_usage_info) 1730 current_function_static_stack_size = info->total_size; 1731 1732 if (info->total_size == 0) 1733 return; 1734 1735 /* We're interested in three areas of the frame here: 1736 1737 A: the register save area 1738 B: the old FP 1739 C: the header after B 1740 1741 If the frame pointer isn't used, we'll have to set up A, B and C 1742 using the stack pointer. If the frame pointer is used, we'll access 1743 them as follows: 1744 1745 A: set up using sp 1746 B: set up using sp or a temporary (see below) 1747 C: set up using fp 1748 1749 We set up B using the stack pointer if the frame is small enough. 1750 Otherwise, it's more efficient to copy the old stack pointer into a 1751 temporary and use that. 1752 1753 Note that it's important to make sure the prologue and epilogue use the 1754 same registers to access A and C, since doing otherwise will confuse 1755 the aliasing code. */ 1756 1757 /* Set up ACCESSOR for accessing region B above. If the frame pointer 1758 isn't used, the same method will serve for C. */ 1759 accessor.op = FRV_STORE; 1760 if (frame_pointer_needed && info->total_size > 2048) 1761 { 1762 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO); 1763 accessor.base_offset = info->total_size; 1764 emit_insn (gen_movsi (accessor.base, sp)); 1765 } 1766 else 1767 { 1768 accessor.base = stack_pointer_rtx; 1769 accessor.base_offset = 0; 1770 } 1771 1772 /* Allocate the stack space. */ 1773 { 1774 rtx asm_offset = frv_frame_offset_rtx (-info->total_size); 1775 rtx dwarf_offset = GEN_INT (-info->total_size); 1776 1777 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset), 1778 gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, dwarf_offset))); 1779 } 1780 1781 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET) 1782 and point the new one to that location. */ 1783 if (frame_pointer_needed) 1784 { 1785 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; 1786 1787 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is 1788 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack 1789 pointer. */ 1790 rtx asm_src = plus_constant (Pmode, accessor.base, 1791 fp_offset - accessor.base_offset); 1792 rtx dwarf_src = plus_constant (Pmode, sp, fp_offset); 1793 1794 /* Store the old frame pointer at (sp + FP_OFFSET). */ 1795 frv_frame_access (&accessor, fp, fp_offset); 1796 1797 /* Set up the new frame pointer. */ 1798 frv_frame_insn (gen_rtx_SET (fp, asm_src), 1799 gen_rtx_SET (fp, dwarf_src)); 1800 1801 /* Access region C from the frame pointer. */ 1802 accessor.base = fp; 1803 accessor.base_offset = fp_offset; 1804 } 1805 1806 /* Set up region C. */ 1807 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT); 1808 frv_frame_access_multi (&accessor, info, STACK_REGS_LR); 1809 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG); 1810 1811 /* Set up region A. */ 1812 frv_frame_access_standard_regs (FRV_STORE, info); 1813 1814 /* If this is a varargs/stdarg function, issue a blockage to prevent the 1815 scheduler from moving loads before the stores saving the registers. */ 1816 if (info->stdarg_size > 0) 1817 emit_insn (gen_blockage ()); 1818 1819 /* Set up pic register/small data register for this function. */ 1820 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table) 1821 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO), 1822 gen_rtx_REG (Pmode, LR_REGNO), 1823 gen_rtx_REG (SImode, OFFSET_REGNO))); 1824 } 1825 1826 1827 /* Under frv, all of the work is done via frv_expand_epilogue, but 1828 this function provides a convenient place to do cleanup. */ 1829 1830 static void 1831 frv_function_epilogue (FILE *) 1832 { 1833 frv_stack_cache = (frv_stack_t *)0; 1834 1835 /* Zap last used registers for conditional execution. */ 1836 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg)); 1837 1838 /* Release the bitmap of created insns. */ 1839 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap); 1840 } 1841 1842 1843 /* Called after register allocation to add any instructions needed for the 1844 epilogue. Using an epilogue insn is favored compared to putting all of the 1845 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since 1846 it allows the scheduler to intermix instructions with the saves of 1847 the caller saved registers. In some cases, it might be necessary 1848 to emit a barrier instruction as the last insn to prevent such 1849 scheduling. */ 1850 1851 void 1852 frv_expand_epilogue (bool emit_return) 1853 { 1854 frv_stack_t *info = frv_stack_info (); 1855 rtx fp = frame_pointer_rtx; 1856 rtx sp = stack_pointer_rtx; 1857 rtx return_addr; 1858 int fp_offset; 1859 1860 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; 1861 1862 /* Restore the stack pointer to its original value if alloca or the like 1863 is used. */ 1864 if (! crtl->sp_is_unchanging) 1865 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset))); 1866 1867 /* Restore the callee-saved registers that were used in this function. */ 1868 frv_frame_access_standard_regs (FRV_LOAD, info); 1869 1870 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if 1871 no return instruction should be emitted. */ 1872 if (info->save_p[LR_REGNO]) 1873 { 1874 int lr_offset; 1875 rtx mem; 1876 1877 /* Use the same method to access the link register's slot as we did in 1878 the prologue. In other words, use the frame pointer if available, 1879 otherwise use the stack pointer. 1880 1881 LR_OFFSET is the offset of the link register's slot from the start 1882 of the frame and MEM is a memory rtx for it. */ 1883 lr_offset = info->reg_offset[LR_REGNO]; 1884 if (frame_pointer_needed) 1885 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset); 1886 else 1887 mem = frv_frame_mem (Pmode, sp, lr_offset); 1888 1889 /* Load the old link register into a GPR. */ 1890 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO); 1891 emit_insn (gen_rtx_SET (return_addr, mem)); 1892 } 1893 else 1894 return_addr = gen_rtx_REG (Pmode, LR_REGNO); 1895 1896 /* Restore the old frame pointer. Emit a USE afterwards to make sure 1897 the load is preserved. */ 1898 if (frame_pointer_needed) 1899 { 1900 emit_insn (gen_rtx_SET (fp, gen_rtx_MEM (Pmode, fp))); 1901 emit_use (fp); 1902 } 1903 1904 /* Deallocate the stack frame. */ 1905 if (info->total_size != 0) 1906 { 1907 rtx offset = frv_frame_offset_rtx (info->total_size); 1908 emit_insn (gen_stack_adjust (sp, sp, offset)); 1909 } 1910 1911 /* If this function uses eh_return, add the final stack adjustment now. */ 1912 if (crtl->calls_eh_return) 1913 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX)); 1914 1915 if (emit_return) 1916 emit_jump_insn (gen_epilogue_return (return_addr)); 1917 else 1918 { 1919 rtx lr = return_addr; 1920 1921 if (REGNO (return_addr) != LR_REGNO) 1922 { 1923 lr = gen_rtx_REG (Pmode, LR_REGNO); 1924 emit_move_insn (lr, return_addr); 1925 } 1926 1927 emit_use (lr); 1928 } 1929 } 1930 1931 1932 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */ 1933 1934 static void 1935 frv_asm_output_mi_thunk (FILE *file, 1936 tree thunk_fndecl ATTRIBUTE_UNUSED, 1937 HOST_WIDE_INT delta, 1938 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, 1939 tree function) 1940 { 1941 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0); 1942 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM]; 1943 const char *name_jmp = reg_names[JUMP_REGNO]; 1944 const char *parallel = (frv_issue_rate () > 1 ? ".p" : ""); 1945 1946 /* Do the add using an addi if possible. */ 1947 if (IN_RANGE (delta, -2048, 2047)) 1948 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); 1949 else 1950 { 1951 const char *const name_add = reg_names[TEMP_REGNO]; 1952 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n", 1953 parallel, delta, name_add); 1954 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n", 1955 delta, name_add); 1956 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0); 1957 } 1958 1959 if (TARGET_FDPIC) 1960 { 1961 const char *name_pic = reg_names[FDPIC_REGNO]; 1962 name_jmp = reg_names[FDPIC_FPTR_REGNO]; 1963 1964 if (flag_pic != 1) 1965 { 1966 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel); 1967 assemble_name (file, name_func); 1968 fprintf (file, "),%s\n", name_jmp); 1969 1970 fprintf (file, "\tsetlo #gotofffuncdesclo("); 1971 assemble_name (file, name_func); 1972 fprintf (file, "),%s\n", name_jmp); 1973 1974 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp); 1975 } 1976 else 1977 { 1978 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic); 1979 assemble_name (file, name_func); 1980 fprintf (file, "\t)), %s\n", name_jmp); 1981 } 1982 } 1983 else if (!flag_pic) 1984 { 1985 fprintf (file, "\tsethi%s #hi(", parallel); 1986 assemble_name (file, name_func); 1987 fprintf (file, "),%s\n", name_jmp); 1988 1989 fprintf (file, "\tsetlo #lo("); 1990 assemble_name (file, name_func); 1991 fprintf (file, "),%s\n", name_jmp); 1992 } 1993 else 1994 { 1995 /* Use JUMP_REGNO as a temporary PIC register. */ 1996 const char *name_lr = reg_names[LR_REGNO]; 1997 const char *name_gppic = name_jmp; 1998 const char *name_tmp = reg_names[TEMP_REGNO]; 1999 2000 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp); 2001 fprintf (file, "\tcall 1f\n"); 2002 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic); 2003 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr); 2004 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp); 2005 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp); 2006 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic); 2007 2008 fprintf (file, "\tsethi%s #gprelhi(", parallel); 2009 assemble_name (file, name_func); 2010 fprintf (file, "),%s\n", name_tmp); 2011 2012 fprintf (file, "\tsetlo #gprello("); 2013 assemble_name (file, name_func); 2014 fprintf (file, "),%s\n", name_tmp); 2015 2016 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp); 2017 } 2018 2019 /* Jump to the function address. */ 2020 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]); 2021 } 2022 2023 2024 2025 /* On frv, create a frame whenever we need to create stack. */ 2026 2027 static bool 2028 frv_frame_pointer_required (void) 2029 { 2030 /* If we forgoing the usual linkage requirements, we only need 2031 a frame pointer if the stack pointer might change. */ 2032 if (!TARGET_LINKED_FP) 2033 return !crtl->sp_is_unchanging; 2034 2035 if (! crtl->is_leaf) 2036 return true; 2037 2038 if (get_frame_size () != 0) 2039 return true; 2040 2041 if (cfun->stdarg) 2042 return true; 2043 2044 if (!crtl->sp_is_unchanging) 2045 return true; 2046 2047 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table) 2048 return true; 2049 2050 if (profile_flag) 2051 return true; 2052 2053 if (cfun->machine->frame_needed) 2054 return true; 2055 2056 return false; 2057 } 2058 2059 2060 /* Worker function for TARGET_CAN_ELIMINATE. */ 2061 2062 bool 2063 frv_can_eliminate (const int from, const int to) 2064 { 2065 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM 2066 ? ! frame_pointer_needed 2067 : true); 2068 } 2069 2070 /* This function returns the initial difference between the specified 2071 pair of registers. */ 2072 2073 /* See frv_stack_info for more details on the frv stack frame. */ 2074 2075 int 2076 frv_initial_elimination_offset (int from, int to) 2077 { 2078 frv_stack_t *info = frv_stack_info (); 2079 int ret = 0; 2080 2081 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM) 2082 ret = info->total_size - info->pretend_size; 2083 2084 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM) 2085 ret = info->reg_offset[FRAME_POINTER_REGNUM]; 2086 2087 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) 2088 ret = (info->total_size 2089 - info->reg_offset[FRAME_POINTER_REGNUM] 2090 - info->pretend_size); 2091 2092 else 2093 gcc_unreachable (); 2094 2095 if (TARGET_DEBUG_STACK) 2096 fprintf (stderr, "Eliminate %s to %s by adding %d\n", 2097 reg_names [from], reg_names[to], ret); 2098 2099 return ret; 2100 } 2101 2102 2103 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ 2104 2105 static void 2106 frv_setup_incoming_varargs (cumulative_args_t cum_v, 2107 machine_mode mode, 2108 tree type ATTRIBUTE_UNUSED, 2109 int *pretend_size, 2110 int second_time) 2111 { 2112 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2113 2114 if (TARGET_DEBUG_ARG) 2115 fprintf (stderr, 2116 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n", 2117 *cum, GET_MODE_NAME (mode), *pretend_size, second_time); 2118 } 2119 2120 2121 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */ 2122 2123 static rtx 2124 frv_expand_builtin_saveregs (void) 2125 { 2126 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS; 2127 2128 if (TARGET_DEBUG_ARG) 2129 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n", 2130 offset); 2131 2132 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset)); 2133 } 2134 2135 2136 /* Expand __builtin_va_start to do the va_start macro. */ 2137 2138 static void 2139 frv_expand_builtin_va_start (tree valist, rtx nextarg) 2140 { 2141 tree t; 2142 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS; 2143 2144 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, 2145 GEN_INT (UNITS_PER_WORD * num)); 2146 2147 if (TARGET_DEBUG_ARG) 2148 { 2149 fprintf (stderr, "va_start: args_info = %d, num = %d\n", 2150 crtl->args.info, num); 2151 2152 debug_rtx (nextarg); 2153 } 2154 2155 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, 2156 fold_convert (TREE_TYPE (valist), 2157 make_tree (sizetype, nextarg))); 2158 TREE_SIDE_EFFECTS (t) = 1; 2159 2160 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 2161 } 2162 2163 2164 /* Expand a block move operation, and return 1 if successful. Return 0 2165 if we should let the compiler generate normal code. 2166 2167 operands[0] is the destination 2168 operands[1] is the source 2169 operands[2] is the length 2170 operands[3] is the alignment */ 2171 2172 /* Maximum number of loads to do before doing the stores */ 2173 #ifndef MAX_MOVE_REG 2174 #define MAX_MOVE_REG 4 2175 #endif 2176 2177 /* Maximum number of total loads to do. */ 2178 #ifndef TOTAL_MOVE_REG 2179 #define TOTAL_MOVE_REG 8 2180 #endif 2181 2182 int 2183 frv_expand_block_move (rtx operands[]) 2184 { 2185 rtx orig_dest = operands[0]; 2186 rtx orig_src = operands[1]; 2187 rtx bytes_rtx = operands[2]; 2188 rtx align_rtx = operands[3]; 2189 int constp = (GET_CODE (bytes_rtx) == CONST_INT); 2190 int align; 2191 int bytes; 2192 int offset; 2193 int num_reg; 2194 int i; 2195 rtx src_reg; 2196 rtx dest_reg; 2197 rtx src_addr; 2198 rtx dest_addr; 2199 rtx src_mem; 2200 rtx dest_mem; 2201 rtx tmp_reg; 2202 rtx stores[MAX_MOVE_REG]; 2203 int move_bytes; 2204 machine_mode mode; 2205 2206 /* If this is not a fixed size move, just call memcpy. */ 2207 if (! constp) 2208 return FALSE; 2209 2210 /* This should be a fixed size alignment. */ 2211 gcc_assert (GET_CODE (align_rtx) == CONST_INT); 2212 2213 align = INTVAL (align_rtx); 2214 2215 /* Anything to move? */ 2216 bytes = INTVAL (bytes_rtx); 2217 if (bytes <= 0) 2218 return TRUE; 2219 2220 /* Don't support real large moves. */ 2221 if (bytes > TOTAL_MOVE_REG*align) 2222 return FALSE; 2223 2224 /* Move the address into scratch registers. */ 2225 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); 2226 src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); 2227 2228 num_reg = offset = 0; 2229 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) 2230 { 2231 /* Calculate the correct offset for src/dest. */ 2232 if (offset == 0) 2233 { 2234 src_addr = src_reg; 2235 dest_addr = dest_reg; 2236 } 2237 else 2238 { 2239 src_addr = plus_constant (Pmode, src_reg, offset); 2240 dest_addr = plus_constant (Pmode, dest_reg, offset); 2241 } 2242 2243 /* Generate the appropriate load and store, saving the stores 2244 for later. */ 2245 if (bytes >= 4 && align >= 4) 2246 mode = SImode; 2247 else if (bytes >= 2 && align >= 2) 2248 mode = HImode; 2249 else 2250 mode = QImode; 2251 2252 move_bytes = GET_MODE_SIZE (mode); 2253 tmp_reg = gen_reg_rtx (mode); 2254 src_mem = change_address (orig_src, mode, src_addr); 2255 dest_mem = change_address (orig_dest, mode, dest_addr); 2256 emit_insn (gen_rtx_SET (tmp_reg, src_mem)); 2257 stores[num_reg++] = gen_rtx_SET (dest_mem, tmp_reg); 2258 2259 if (num_reg >= MAX_MOVE_REG) 2260 { 2261 for (i = 0; i < num_reg; i++) 2262 emit_insn (stores[i]); 2263 num_reg = 0; 2264 } 2265 } 2266 2267 for (i = 0; i < num_reg; i++) 2268 emit_insn (stores[i]); 2269 2270 return TRUE; 2271 } 2272 2273 2274 /* Expand a block clear operation, and return 1 if successful. Return 0 2275 if we should let the compiler generate normal code. 2276 2277 operands[0] is the destination 2278 operands[1] is the length 2279 operands[3] is the alignment */ 2280 2281 int 2282 frv_expand_block_clear (rtx operands[]) 2283 { 2284 rtx orig_dest = operands[0]; 2285 rtx bytes_rtx = operands[1]; 2286 rtx align_rtx = operands[3]; 2287 int constp = (GET_CODE (bytes_rtx) == CONST_INT); 2288 int align; 2289 int bytes; 2290 int offset; 2291 rtx dest_reg; 2292 rtx dest_addr; 2293 rtx dest_mem; 2294 int clear_bytes; 2295 machine_mode mode; 2296 2297 /* If this is not a fixed size move, just call memcpy. */ 2298 if (! constp) 2299 return FALSE; 2300 2301 /* This should be a fixed size alignment. */ 2302 gcc_assert (GET_CODE (align_rtx) == CONST_INT); 2303 2304 align = INTVAL (align_rtx); 2305 2306 /* Anything to move? */ 2307 bytes = INTVAL (bytes_rtx); 2308 if (bytes <= 0) 2309 return TRUE; 2310 2311 /* Don't support real large clears. */ 2312 if (bytes > TOTAL_MOVE_REG*align) 2313 return FALSE; 2314 2315 /* Move the address into a scratch register. */ 2316 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); 2317 2318 offset = 0; 2319 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes)) 2320 { 2321 /* Calculate the correct offset for src/dest. */ 2322 dest_addr = ((offset == 0) 2323 ? dest_reg 2324 : plus_constant (Pmode, dest_reg, offset)); 2325 2326 /* Generate the appropriate store of gr0. */ 2327 if (bytes >= 4 && align >= 4) 2328 mode = SImode; 2329 else if (bytes >= 2 && align >= 2) 2330 mode = HImode; 2331 else 2332 mode = QImode; 2333 2334 clear_bytes = GET_MODE_SIZE (mode); 2335 dest_mem = change_address (orig_dest, mode, dest_addr); 2336 emit_insn (gen_rtx_SET (dest_mem, const0_rtx)); 2337 } 2338 2339 return TRUE; 2340 } 2341 2342 2343 /* The following variable is used to output modifiers of assembler 2344 code of the current output insn. */ 2345 2346 static rtx *frv_insn_operands; 2347 2348 /* The following function is used to add assembler insn code suffix .p 2349 if it is necessary. */ 2350 2351 const char * 2352 frv_asm_output_opcode (FILE *f, const char *ptr) 2353 { 2354 int c; 2355 2356 if (frv_insn_packing_flag <= 0) 2357 return ptr; 2358 2359 for (; *ptr && *ptr != ' ' && *ptr != '\t';) 2360 { 2361 c = *ptr++; 2362 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z') 2363 || (*ptr >= 'A' && *ptr <= 'Z'))) 2364 { 2365 int letter = *ptr++; 2366 2367 c = atoi (ptr); 2368 frv_print_operand (f, frv_insn_operands [c], letter); 2369 while ((c = *ptr) >= '0' && c <= '9') 2370 ptr++; 2371 } 2372 else 2373 fputc (c, f); 2374 } 2375 2376 fprintf (f, ".p"); 2377 2378 return ptr; 2379 } 2380 2381 /* Set up the packing bit for the current output insn. Note that this 2382 function is not called for asm insns. */ 2383 2384 void 2385 frv_final_prescan_insn (rtx_insn *insn, rtx *opvec, 2386 int noperands ATTRIBUTE_UNUSED) 2387 { 2388 if (INSN_P (insn)) 2389 { 2390 if (frv_insn_packing_flag >= 0) 2391 { 2392 frv_insn_operands = opvec; 2393 frv_insn_packing_flag = PACKING_FLAG_P (insn); 2394 } 2395 else if (recog_memoized (insn) >= 0 2396 && get_attr_acc_group (insn) == ACC_GROUP_ODD) 2397 /* Packing optimizations have been disabled, but INSN can only 2398 be issued in M1. Insert an mnop in M0. */ 2399 fprintf (asm_out_file, "\tmnop.p\n"); 2400 } 2401 } 2402 2403 2404 2405 /* A C expression whose value is RTL representing the address in a stack frame 2406 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is 2407 an RTL expression for the address of the stack frame itself. 2408 2409 If you don't define this macro, the default is to return the value of 2410 FRAMEADDR--that is, the stack frame address is also the address of the stack 2411 word that points to the previous frame. */ 2412 2413 /* The default is correct, but we need to make sure the frame gets created. */ 2414 rtx 2415 frv_dynamic_chain_address (rtx frame) 2416 { 2417 cfun->machine->frame_needed = 1; 2418 return frame; 2419 } 2420 2421 2422 /* A C expression whose value is RTL representing the value of the return 2423 address for the frame COUNT steps up from the current frame, after the 2424 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame 2425 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is 2426 defined. 2427 2428 The value of the expression must always be the correct address when COUNT is 2429 zero, but may be `NULL_RTX' if there is not way to determine the return 2430 address of other frames. */ 2431 2432 rtx 2433 frv_return_addr_rtx (int count, rtx frame) 2434 { 2435 if (count != 0) 2436 return const0_rtx; 2437 cfun->machine->frame_needed = 1; 2438 return gen_rtx_MEM (Pmode, plus_constant (Pmode, frame, 8)); 2439 } 2440 2441 /* Given a memory reference MEMREF, interpret the referenced memory as 2442 an array of MODE values, and return a reference to the element 2443 specified by INDEX. Assume that any pre-modification implicit in 2444 MEMREF has already happened. 2445 2446 MEMREF must be a legitimate operand for modes larger than SImode. 2447 frv_legitimate_address_p forbids register+register addresses, which 2448 this function cannot handle. */ 2449 rtx 2450 frv_index_memory (rtx memref, machine_mode mode, int index) 2451 { 2452 rtx base = XEXP (memref, 0); 2453 if (GET_CODE (base) == PRE_MODIFY) 2454 base = XEXP (base, 0); 2455 return change_address (memref, mode, 2456 plus_constant (Pmode, base, 2457 index * GET_MODE_SIZE (mode))); 2458 } 2459 2460 2461 /* Print a memory address as an operand to reference that memory location. */ 2462 static void 2463 frv_print_operand_address (FILE * stream, machine_mode /* mode */, rtx x) 2464 { 2465 if (GET_CODE (x) == MEM) 2466 x = XEXP (x, 0); 2467 2468 switch (GET_CODE (x)) 2469 { 2470 case REG: 2471 fputs (reg_names [ REGNO (x)], stream); 2472 return; 2473 2474 case CONST_INT: 2475 fprintf (stream, "%ld", (long) INTVAL (x)); 2476 return; 2477 2478 case SYMBOL_REF: 2479 assemble_name (stream, XSTR (x, 0)); 2480 return; 2481 2482 case LABEL_REF: 2483 case CONST: 2484 output_addr_const (stream, x); 2485 return; 2486 2487 case PLUS: 2488 /* Poorly constructed asm statements can trigger this alternative. 2489 See gcc/testsuite/gcc.dg/asm-4.c for an example. */ 2490 frv_print_operand_memory_reference (stream, x, 0); 2491 return; 2492 2493 default: 2494 break; 2495 } 2496 2497 fatal_insn ("bad insn to frv_print_operand_address:", x); 2498 } 2499 2500 2501 static void 2502 frv_print_operand_memory_reference_reg (FILE * stream, rtx x) 2503 { 2504 int regno = true_regnum (x); 2505 if (GPR_P (regno)) 2506 fputs (reg_names[regno], stream); 2507 else 2508 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x); 2509 } 2510 2511 /* Print a memory reference suitable for the ld/st instructions. */ 2512 2513 static void 2514 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset) 2515 { 2516 struct frv_unspec unspec; 2517 rtx x0 = NULL_RTX; 2518 rtx x1 = NULL_RTX; 2519 2520 switch (GET_CODE (x)) 2521 { 2522 case SUBREG: 2523 case REG: 2524 x0 = x; 2525 break; 2526 2527 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */ 2528 x0 = XEXP (x, 0); 2529 x1 = XEXP (XEXP (x, 1), 1); 2530 break; 2531 2532 case CONST_INT: 2533 x1 = x; 2534 break; 2535 2536 case PLUS: 2537 x0 = XEXP (x, 0); 2538 x1 = XEXP (x, 1); 2539 if (GET_CODE (x0) == CONST_INT) 2540 { 2541 x0 = XEXP (x, 1); 2542 x1 = XEXP (x, 0); 2543 } 2544 break; 2545 2546 default: 2547 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); 2548 break; 2549 2550 } 2551 2552 if (addr_offset) 2553 { 2554 if (!x1) 2555 x1 = const0_rtx; 2556 else if (GET_CODE (x1) != CONST_INT) 2557 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); 2558 } 2559 2560 fputs ("@(", stream); 2561 if (!x0) 2562 fputs (reg_names[GPR_R0], stream); 2563 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG) 2564 frv_print_operand_memory_reference_reg (stream, x0); 2565 else 2566 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); 2567 2568 fputs (",", stream); 2569 if (!x1) 2570 fputs (reg_names [GPR_R0], stream); 2571 2572 else 2573 { 2574 switch (GET_CODE (x1)) 2575 { 2576 case SUBREG: 2577 case REG: 2578 frv_print_operand_memory_reference_reg (stream, x1); 2579 break; 2580 2581 case CONST_INT: 2582 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset)); 2583 break; 2584 2585 case CONST: 2586 if (!frv_const_unspec_p (x1, &unspec)) 2587 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1); 2588 frv_output_const_unspec (stream, &unspec); 2589 break; 2590 2591 default: 2592 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); 2593 } 2594 } 2595 2596 fputs (")", stream); 2597 } 2598 2599 2600 /* Return 2 for likely branches and 0 for non-likely branches */ 2601 2602 #define FRV_JUMP_LIKELY 2 2603 #define FRV_JUMP_NOT_LIKELY 0 2604 2605 static int 2606 frv_print_operand_jump_hint (rtx_insn *insn) 2607 { 2608 rtx note; 2609 rtx labelref; 2610 int ret; 2611 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN; 2612 2613 gcc_assert (JUMP_P (insn)); 2614 2615 /* Assume any non-conditional jump is likely. */ 2616 if (! any_condjump_p (insn)) 2617 ret = FRV_JUMP_LIKELY; 2618 2619 else 2620 { 2621 labelref = condjump_label (insn); 2622 if (labelref) 2623 { 2624 rtx label = XEXP (labelref, 0); 2625 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label)) 2626 ? BACKWARD 2627 : FORWARD); 2628 } 2629 2630 note = find_reg_note (insn, REG_BR_PROB, 0); 2631 if (!note) 2632 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY); 2633 2634 else 2635 { 2636 ret = ((profile_probability::from_reg_br_prob_note (XINT (note, 0)) 2637 >= profile_probability::even ()) 2638 ? FRV_JUMP_LIKELY 2639 : FRV_JUMP_NOT_LIKELY); 2640 } 2641 } 2642 2643 #if 0 2644 if (TARGET_DEBUG) 2645 { 2646 char *direction; 2647 2648 switch (jump_type) 2649 { 2650 default: 2651 case UNKNOWN: direction = "unknown jump direction"; break; 2652 case BACKWARD: direction = "jump backward"; break; 2653 case FORWARD: direction = "jump forward"; break; 2654 } 2655 2656 fprintf (stderr, 2657 "%s: uid %ld, %s, probability = %d, max prob. = %d, hint = %d\n", 2658 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), 2659 (long)INSN_UID (insn), direction, prob, 2660 REG_BR_PROB_BASE, ret); 2661 } 2662 #endif 2663 2664 return ret; 2665 } 2666 2667 2668 /* Return the comparison operator to use for CODE given that the ICC 2669 register is OP0. */ 2670 2671 static const char * 2672 comparison_string (enum rtx_code code, rtx op0) 2673 { 2674 bool is_nz_p = GET_MODE (op0) == CC_NZmode; 2675 switch (code) 2676 { 2677 default: output_operand_lossage ("bad condition code"); return ""; 2678 case EQ: return "eq"; 2679 case NE: return "ne"; 2680 case LT: return is_nz_p ? "n" : "lt"; 2681 case LE: return "le"; 2682 case GT: return "gt"; 2683 case GE: return is_nz_p ? "p" : "ge"; 2684 case LTU: return is_nz_p ? "no" : "c"; 2685 case LEU: return is_nz_p ? "eq" : "ls"; 2686 case GTU: return is_nz_p ? "ne" : "hi"; 2687 case GEU: return is_nz_p ? "ra" : "nc"; 2688 } 2689 } 2690 2691 /* Print an operand to an assembler instruction. 2692 2693 `%' followed by a letter and a digit says to output an operand in an 2694 alternate fashion. Four letters have standard, built-in meanings 2695 described below. The hook `TARGET_PRINT_OPERAND' can define 2696 additional letters with nonstandard meanings. 2697 2698 `%cDIGIT' can be used to substitute an operand that is a constant value 2699 without the syntax that normally indicates an immediate operand. 2700 2701 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated 2702 before printing. 2703 2704 `%aDIGIT' can be used to substitute an operand as if it were a memory 2705 reference, with the actual operand treated as the address. This may be 2706 useful when outputting a "load address" instruction, because often the 2707 assembler syntax for such an instruction requires you to write the operand 2708 as if it were a memory reference. 2709 2710 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction. 2711 2712 `%=' outputs a number which is unique to each instruction in the entire 2713 compilation. This is useful for making local labels to be referred to more 2714 than once in a single template that generates multiple assembler 2715 instructions. 2716 2717 `%' followed by a punctuation character specifies a substitution that 2718 does not use an operand. Only one case is standard: `%%' outputs a 2719 `%' into the assembler code. Other nonstandard cases can be defined 2720 in the `TARGET_PRINT_OPERAND' hook. You must also define which 2721 punctuation characters are valid with the 2722 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */ 2723 2724 static void 2725 frv_print_operand (FILE * file, rtx x, int code) 2726 { 2727 struct frv_unspec unspec; 2728 HOST_WIDE_INT value; 2729 int offset; 2730 2731 if (code != 0 && !ISALPHA (code)) 2732 value = 0; 2733 2734 else if (GET_CODE (x) == CONST_INT) 2735 value = INTVAL (x); 2736 2737 else if (GET_CODE (x) == CONST_DOUBLE) 2738 { 2739 if (GET_MODE (x) == SFmode) 2740 { 2741 long l; 2742 2743 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l); 2744 value = l; 2745 } 2746 2747 else if (GET_MODE (x) == VOIDmode) 2748 value = CONST_DOUBLE_LOW (x); 2749 2750 else 2751 fatal_insn ("bad insn in frv_print_operand, bad const_double", x); 2752 } 2753 2754 else 2755 value = 0; 2756 2757 switch (code) 2758 { 2759 2760 case '.': 2761 /* Output r0. */ 2762 fputs (reg_names[GPR_R0], file); 2763 break; 2764 2765 case '#': 2766 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn)); 2767 break; 2768 2769 case '@': 2770 /* Output small data area base register (gr16). */ 2771 fputs (reg_names[SDA_BASE_REG], file); 2772 break; 2773 2774 case '~': 2775 /* Output pic register (gr17). */ 2776 fputs (reg_names[PIC_REGNO], file); 2777 break; 2778 2779 case '*': 2780 /* Output the temporary integer CCR register. */ 2781 fputs (reg_names[ICR_TEMP], file); 2782 break; 2783 2784 case '&': 2785 /* Output the temporary integer CC register. */ 2786 fputs (reg_names[ICC_TEMP], file); 2787 break; 2788 2789 /* case 'a': print an address. */ 2790 2791 case 'C': 2792 /* Print appropriate test for integer branch false operation. */ 2793 fputs (comparison_string (reverse_condition (GET_CODE (x)), 2794 XEXP (x, 0)), file); 2795 break; 2796 2797 case 'c': 2798 /* Print appropriate test for integer branch true operation. */ 2799 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file); 2800 break; 2801 2802 case 'e': 2803 /* Print 1 for a NE and 0 for an EQ to give the final argument 2804 for a conditional instruction. */ 2805 if (GET_CODE (x) == NE) 2806 fputs ("1", file); 2807 2808 else if (GET_CODE (x) == EQ) 2809 fputs ("0", file); 2810 2811 else 2812 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x); 2813 break; 2814 2815 case 'F': 2816 /* Print appropriate test for floating point branch false operation. */ 2817 switch (GET_CODE (x)) 2818 { 2819 default: 2820 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x); 2821 2822 case EQ: fputs ("ne", file); break; 2823 case NE: fputs ("eq", file); break; 2824 case LT: fputs ("uge", file); break; 2825 case LE: fputs ("ug", file); break; 2826 case GT: fputs ("ule", file); break; 2827 case GE: fputs ("ul", file); break; 2828 } 2829 break; 2830 2831 case 'f': 2832 /* Print appropriate test for floating point branch true operation. */ 2833 switch (GET_CODE (x)) 2834 { 2835 default: 2836 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x); 2837 2838 case EQ: fputs ("eq", file); break; 2839 case NE: fputs ("ne", file); break; 2840 case LT: fputs ("lt", file); break; 2841 case LE: fputs ("le", file); break; 2842 case GT: fputs ("gt", file); break; 2843 case GE: fputs ("ge", file); break; 2844 } 2845 break; 2846 2847 case 'g': 2848 /* Print appropriate GOT function. */ 2849 if (GET_CODE (x) != CONST_INT) 2850 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x); 2851 fputs (unspec_got_name (INTVAL (x)), file); 2852 break; 2853 2854 case 'I': 2855 /* Print 'i' if the operand is a constant, or is a memory reference that 2856 adds a constant. */ 2857 if (GET_CODE (x) == MEM) 2858 x = ((GET_CODE (XEXP (x, 0)) == PLUS) 2859 ? XEXP (XEXP (x, 0), 1) 2860 : XEXP (x, 0)); 2861 else if (GET_CODE (x) == PLUS) 2862 x = XEXP (x, 1); 2863 2864 switch (GET_CODE (x)) 2865 { 2866 default: 2867 break; 2868 2869 case CONST_INT: 2870 case SYMBOL_REF: 2871 case CONST: 2872 fputs ("i", file); 2873 break; 2874 } 2875 break; 2876 2877 case 'i': 2878 /* For jump instructions, print 'i' if the operand is a constant or 2879 is an expression that adds a constant. */ 2880 if (GET_CODE (x) == CONST_INT) 2881 fputs ("i", file); 2882 2883 else 2884 { 2885 if (GET_CODE (x) == CONST_INT 2886 || (GET_CODE (x) == PLUS 2887 && (GET_CODE (XEXP (x, 1)) == CONST_INT 2888 || GET_CODE (XEXP (x, 0)) == CONST_INT))) 2889 fputs ("i", file); 2890 } 2891 break; 2892 2893 case 'L': 2894 /* Print the lower register of a double word register pair */ 2895 if (GET_CODE (x) == REG) 2896 fputs (reg_names[ REGNO (x)+1 ], file); 2897 else 2898 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x); 2899 break; 2900 2901 /* case 'l': print a LABEL_REF. */ 2902 2903 case 'M': 2904 case 'N': 2905 /* Print a memory reference for ld/st/jmp, %N prints a memory reference 2906 for the second word of double memory operations. */ 2907 offset = (code == 'M') ? 0 : UNITS_PER_WORD; 2908 switch (GET_CODE (x)) 2909 { 2910 default: 2911 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x); 2912 2913 case MEM: 2914 frv_print_operand_memory_reference (file, XEXP (x, 0), offset); 2915 break; 2916 2917 case REG: 2918 case SUBREG: 2919 case CONST_INT: 2920 case PLUS: 2921 case SYMBOL_REF: 2922 frv_print_operand_memory_reference (file, x, offset); 2923 break; 2924 } 2925 break; 2926 2927 case 'O': 2928 /* Print the opcode of a command. */ 2929 switch (GET_CODE (x)) 2930 { 2931 default: 2932 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x); 2933 2934 case PLUS: fputs ("add", file); break; 2935 case MINUS: fputs ("sub", file); break; 2936 case AND: fputs ("and", file); break; 2937 case IOR: fputs ("or", file); break; 2938 case XOR: fputs ("xor", file); break; 2939 case ASHIFT: fputs ("sll", file); break; 2940 case ASHIFTRT: fputs ("sra", file); break; 2941 case LSHIFTRT: fputs ("srl", file); break; 2942 } 2943 break; 2944 2945 /* case 'n': negate and print a constant int. */ 2946 2947 case 'P': 2948 /* Print PIC label using operand as the number. */ 2949 if (GET_CODE (x) != CONST_INT) 2950 fatal_insn ("bad insn to frv_print_operand, P modifier:", x); 2951 2952 fprintf (file, ".LCF%ld", (long)INTVAL (x)); 2953 break; 2954 2955 case 'U': 2956 /* Print 'u' if the operand is a update load/store. */ 2957 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY) 2958 fputs ("u", file); 2959 break; 2960 2961 case 'z': 2962 /* If value is 0, print gr0, otherwise it must be a register. */ 2963 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0) 2964 fputs (reg_names[GPR_R0], file); 2965 2966 else if (GET_CODE (x) == REG) 2967 fputs (reg_names [REGNO (x)], file); 2968 2969 else 2970 fatal_insn ("bad insn in frv_print_operand, z case", x); 2971 break; 2972 2973 case 'x': 2974 /* Print constant in hex. */ 2975 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) 2976 { 2977 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value); 2978 break; 2979 } 2980 2981 /* Fall through. */ 2982 2983 case '\0': 2984 if (GET_CODE (x) == REG) 2985 fputs (reg_names [REGNO (x)], file); 2986 2987 else if (GET_CODE (x) == CONST_INT 2988 || GET_CODE (x) == CONST_DOUBLE) 2989 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value); 2990 2991 else if (frv_const_unspec_p (x, &unspec)) 2992 frv_output_const_unspec (file, &unspec); 2993 2994 else if (GET_CODE (x) == MEM) 2995 frv_print_operand_address (file, GET_MODE (x), XEXP (x, 0)); 2996 2997 else if (CONSTANT_ADDRESS_P (x)) 2998 frv_print_operand_address (file, VOIDmode, x); 2999 3000 else 3001 fatal_insn ("bad insn in frv_print_operand, 0 case", x); 3002 3003 break; 3004 3005 default: 3006 fatal_insn ("frv_print_operand: unknown code", x); 3007 break; 3008 } 3009 3010 return; 3011 } 3012 3013 static bool 3014 frv_print_operand_punct_valid_p (unsigned char code) 3015 { 3016 return (code == '.' || code == '#' || code == '@' || code == '~' 3017 || code == '*' || code == '&'); 3018 } 3019 3020 3021 /* A C statement (sans semicolon) for initializing the variable CUM for the 3022 state at the beginning of the argument list. The variable has type 3023 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type 3024 of the function which will receive the args, or 0 if the args are to a 3025 compiler support library function. The value of INDIRECT is nonzero when 3026 processing an indirect call, for example a call through a function pointer. 3027 The value of INDIRECT is zero for a call to an explicitly named function, a 3028 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find 3029 arguments for the function being compiled. 3030 3031 When processing a call to a compiler support library function, LIBNAME 3032 identifies which one. It is a `symbol_ref' rtx which contains the name of 3033 the function, as a string. LIBNAME is 0 when an ordinary C function call is 3034 being processed. Thus, each time this macro is called, either LIBNAME or 3035 FNTYPE is nonzero, but never both of them at once. */ 3036 3037 void 3038 frv_init_cumulative_args (CUMULATIVE_ARGS *cum, 3039 tree fntype, 3040 rtx libname, 3041 tree fndecl, 3042 int incoming) 3043 { 3044 *cum = FIRST_ARG_REGNUM; 3045 3046 if (TARGET_DEBUG_ARG) 3047 { 3048 fprintf (stderr, "\ninit_cumulative_args:"); 3049 if (!fndecl && fntype) 3050 fputs (" indirect", stderr); 3051 3052 if (incoming) 3053 fputs (" incoming", stderr); 3054 3055 if (fntype) 3056 { 3057 tree ret_type = TREE_TYPE (fntype); 3058 fprintf (stderr, " return=%s,", 3059 get_tree_code_name (TREE_CODE (ret_type))); 3060 } 3061 3062 if (libname && GET_CODE (libname) == SYMBOL_REF) 3063 fprintf (stderr, " libname=%s", XSTR (libname, 0)); 3064 3065 if (cfun->returns_struct) 3066 fprintf (stderr, " return-struct"); 3067 3068 putc ('\n', stderr); 3069 } 3070 } 3071 3072 3073 /* Return true if we should pass an argument on the stack rather than 3074 in registers. */ 3075 3076 static bool 3077 frv_must_pass_in_stack (machine_mode mode, const_tree type) 3078 { 3079 if (mode == BLKmode) 3080 return true; 3081 if (type == NULL) 3082 return false; 3083 return AGGREGATE_TYPE_P (type); 3084 } 3085 3086 /* If defined, a C expression that gives the alignment boundary, in bits, of an 3087 argument with the specified mode and type. If it is not defined, 3088 `PARM_BOUNDARY' is used for all arguments. */ 3089 3090 static unsigned int 3091 frv_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED, 3092 const_tree type ATTRIBUTE_UNUSED) 3093 { 3094 return BITS_PER_WORD; 3095 } 3096 3097 static rtx 3098 frv_function_arg_1 (cumulative_args_t cum_v, machine_mode mode, 3099 const_tree type ATTRIBUTE_UNUSED, bool named, 3100 bool incoming ATTRIBUTE_UNUSED) 3101 { 3102 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 3103 3104 machine_mode xmode = (mode == BLKmode) ? SImode : mode; 3105 int arg_num = *cum; 3106 rtx ret; 3107 const char *debstr; 3108 3109 /* Return a marker for use in the call instruction. */ 3110 if (xmode == VOIDmode) 3111 { 3112 ret = const0_rtx; 3113 debstr = "<0>"; 3114 } 3115 3116 else if (arg_num <= LAST_ARG_REGNUM) 3117 { 3118 ret = gen_rtx_REG (xmode, arg_num); 3119 debstr = reg_names[arg_num]; 3120 } 3121 3122 else 3123 { 3124 ret = NULL_RTX; 3125 debstr = "memory"; 3126 } 3127 3128 if (TARGET_DEBUG_ARG) 3129 fprintf (stderr, 3130 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n", 3131 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr); 3132 3133 return ret; 3134 } 3135 3136 static rtx 3137 frv_function_arg (cumulative_args_t cum, machine_mode mode, 3138 const_tree type, bool named) 3139 { 3140 return frv_function_arg_1 (cum, mode, type, named, false); 3141 } 3142 3143 static rtx 3144 frv_function_incoming_arg (cumulative_args_t cum, machine_mode mode, 3145 const_tree type, bool named) 3146 { 3147 return frv_function_arg_1 (cum, mode, type, named, true); 3148 } 3149 3150 3151 /* A C statement (sans semicolon) to update the summarizer variable CUM to 3152 advance past an argument in the argument list. The values MODE, TYPE and 3153 NAMED describe that argument. Once this is done, the variable CUM is 3154 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. 3155 3156 This macro need not do anything if the argument in question was passed on 3157 the stack. The compiler knows how to track the amount of stack space used 3158 for arguments without any special help. */ 3159 3160 static void 3161 frv_function_arg_advance (cumulative_args_t cum_v, 3162 machine_mode mode, 3163 const_tree type ATTRIBUTE_UNUSED, 3164 bool named) 3165 { 3166 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 3167 3168 machine_mode xmode = (mode == BLKmode) ? SImode : mode; 3169 int bytes = GET_MODE_SIZE (xmode); 3170 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 3171 int arg_num = *cum; 3172 3173 *cum = arg_num + words; 3174 3175 if (TARGET_DEBUG_ARG) 3176 fprintf (stderr, 3177 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n", 3178 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD); 3179 } 3180 3181 3182 /* A C expression for the number of words, at the beginning of an argument, 3183 must be put in registers. The value must be zero for arguments that are 3184 passed entirely in registers or that are entirely pushed on the stack. 3185 3186 On some machines, certain arguments must be passed partially in registers 3187 and partially in memory. On these machines, typically the first N words of 3188 arguments are passed in registers, and the rest on the stack. If a 3189 multi-word argument (a `double' or a structure) crosses that boundary, its 3190 first few words must be passed in registers and the rest must be pushed. 3191 This macro tells the compiler when this occurs, and how many of the words 3192 should go in registers. 3193 3194 `FUNCTION_ARG' for these arguments should return the first register to be 3195 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for 3196 the called function. */ 3197 3198 static int 3199 frv_arg_partial_bytes (cumulative_args_t cum, machine_mode mode, 3200 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED) 3201 { 3202 3203 machine_mode xmode = (mode == BLKmode) ? SImode : mode; 3204 int bytes = GET_MODE_SIZE (xmode); 3205 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 3206 int arg_num = *get_cumulative_args (cum); 3207 int ret; 3208 3209 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1) 3210 ? LAST_ARG_REGNUM - arg_num + 1 3211 : 0); 3212 ret *= UNITS_PER_WORD; 3213 3214 if (TARGET_DEBUG_ARG && ret) 3215 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret); 3216 3217 return ret; 3218 } 3219 3220 3221 /* Implements TARGET_FUNCTION_VALUE. */ 3222 3223 static rtx 3224 frv_function_value (const_tree valtype, 3225 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 3226 bool outgoing ATTRIBUTE_UNUSED) 3227 { 3228 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM); 3229 } 3230 3231 3232 /* Implements TARGET_LIBCALL_VALUE. */ 3233 3234 static rtx 3235 frv_libcall_value (machine_mode mode, 3236 const_rtx fun ATTRIBUTE_UNUSED) 3237 { 3238 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); 3239 } 3240 3241 3242 /* Implements FUNCTION_VALUE_REGNO_P. */ 3243 3244 bool 3245 frv_function_value_regno_p (const unsigned int regno) 3246 { 3247 return (regno == RETURN_VALUE_REGNUM); 3248 } 3249 3250 /* Return true if a register is ok to use as a base or index register. */ 3251 3252 static FRV_INLINE int 3253 frv_regno_ok_for_base_p (int regno, int strict_p) 3254 { 3255 if (GPR_P (regno)) 3256 return TRUE; 3257 3258 if (strict_p) 3259 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno])); 3260 3261 if (regno == ARG_POINTER_REGNUM) 3262 return TRUE; 3263 3264 return (regno >= FIRST_PSEUDO_REGISTER); 3265 } 3266 3267 3268 /* A C compound statement with a conditional `goto LABEL;' executed if X (an 3269 RTX) is a legitimate memory address on the target machine for a memory 3270 operand of mode MODE. 3271 3272 It usually pays to define several simpler macros to serve as subroutines for 3273 this one. Otherwise it may be too complicated to understand. 3274 3275 This macro must exist in two variants: a strict variant and a non-strict 3276 one. The strict variant is used in the reload pass. It must be defined so 3277 that any pseudo-register that has not been allocated a hard register is 3278 considered a memory reference. In contexts where some kind of register is 3279 required, a pseudo-register with no hard register must be rejected. 3280 3281 The non-strict variant is used in other passes. It must be defined to 3282 accept all pseudo-registers in every context where some kind of register is 3283 required. 3284 3285 Compiler source files that want to use the strict variant of this macro 3286 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' 3287 conditional to define the strict variant in that case and the non-strict 3288 variant otherwise. 3289 3290 Normally, constant addresses which are the sum of a `symbol_ref' and an 3291 integer are stored inside a `const' RTX to mark them as constant. 3292 Therefore, there is no need to recognize such sums specifically as 3293 legitimate addresses. Normally you would simply recognize any `const' as 3294 legitimate. 3295 3296 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle 3297 constant sums that are not marked with `const'. It assumes that a 3298 naked `plus' indicates indexing. If so, then you *must* reject such 3299 naked constant sums as illegitimate addresses, so that none of them 3300 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */ 3301 3302 int 3303 frv_legitimate_address_p_1 (machine_mode mode, 3304 rtx x, 3305 int strict_p, 3306 int condexec_p, 3307 int allow_double_reg_p) 3308 { 3309 rtx x0, x1; 3310 int ret = 0; 3311 HOST_WIDE_INT value; 3312 unsigned regno0; 3313 3314 if (FRV_SYMBOL_REF_TLS_P (x)) 3315 return 0; 3316 3317 switch (GET_CODE (x)) 3318 { 3319 default: 3320 break; 3321 3322 case SUBREG: 3323 x = SUBREG_REG (x); 3324 if (GET_CODE (x) != REG) 3325 break; 3326 3327 /* Fall through. */ 3328 3329 case REG: 3330 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p); 3331 break; 3332 3333 case PRE_MODIFY: 3334 x0 = XEXP (x, 0); 3335 x1 = XEXP (x, 1); 3336 if (GET_CODE (x0) != REG 3337 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p) 3338 || GET_CODE (x1) != PLUS 3339 || ! rtx_equal_p (x0, XEXP (x1, 0)) 3340 || GET_CODE (XEXP (x1, 1)) != REG 3341 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p)) 3342 break; 3343 3344 ret = 1; 3345 break; 3346 3347 case CONST_INT: 3348 /* 12-bit immediate */ 3349 if (condexec_p) 3350 ret = FALSE; 3351 else 3352 { 3353 ret = IN_RANGE (INTVAL (x), -2048, 2047); 3354 3355 /* If we can't use load/store double operations, make sure we can 3356 address the second word. */ 3357 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) 3358 ret = IN_RANGE (INTVAL (x) + GET_MODE_SIZE (mode) - 1, 3359 -2048, 2047); 3360 } 3361 break; 3362 3363 case PLUS: 3364 x0 = XEXP (x, 0); 3365 x1 = XEXP (x, 1); 3366 3367 if (GET_CODE (x0) == SUBREG) 3368 x0 = SUBREG_REG (x0); 3369 3370 if (GET_CODE (x0) != REG) 3371 break; 3372 3373 regno0 = REGNO (x0); 3374 if (!frv_regno_ok_for_base_p (regno0, strict_p)) 3375 break; 3376 3377 switch (GET_CODE (x1)) 3378 { 3379 default: 3380 break; 3381 3382 case SUBREG: 3383 x1 = SUBREG_REG (x1); 3384 if (GET_CODE (x1) != REG) 3385 break; 3386 3387 /* Fall through. */ 3388 3389 case REG: 3390 /* Do not allow reg+reg addressing for modes > 1 word if we 3391 can't depend on having move double instructions. */ 3392 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD) 3393 ret = FALSE; 3394 else 3395 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p); 3396 break; 3397 3398 case CONST_INT: 3399 /* 12-bit immediate */ 3400 if (condexec_p) 3401 ret = FALSE; 3402 else 3403 { 3404 value = INTVAL (x1); 3405 ret = IN_RANGE (value, -2048, 2047); 3406 3407 /* If we can't use load/store double operations, make sure we can 3408 address the second word. */ 3409 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) 3410 ret = IN_RANGE (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); 3411 } 3412 break; 3413 3414 case CONST: 3415 if (!condexec_p && got12_operand (x1, VOIDmode)) 3416 ret = TRUE; 3417 break; 3418 3419 } 3420 break; 3421 } 3422 3423 if (TARGET_DEBUG_ADDR) 3424 { 3425 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n", 3426 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ", 3427 (condexec_p) ? ", inside conditional code" : ""); 3428 debug_rtx (x); 3429 } 3430 3431 return ret; 3432 } 3433 3434 bool 3435 frv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) 3436 { 3437 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE); 3438 } 3439 3440 /* Given an ADDR, generate code to inline the PLT. */ 3441 static rtx 3442 gen_inlined_tls_plt (rtx addr) 3443 { 3444 rtx retval, dest; 3445 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG); 3446 3447 3448 dest = gen_reg_rtx (DImode); 3449 3450 if (flag_pic == 1) 3451 { 3452 /* 3453 -fpic version: 3454 3455 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8 3456 calll #gettlsoff(ADDR)@(gr8, gr0) 3457 */ 3458 emit_insn (gen_tls_lddi (dest, addr, picreg)); 3459 } 3460 else 3461 { 3462 /* 3463 -fPIC version: 3464 3465 sethi.p #gottlsdeschi(ADDR), gr8 3466 setlo #gottlsdesclo(ADDR), gr8 3467 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8 3468 calll #gettlsoff(ADDR)@(gr8, gr0) 3469 */ 3470 rtx reguse = gen_reg_rtx (Pmode); 3471 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI))); 3472 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr)); 3473 } 3474 3475 retval = gen_reg_rtx (Pmode); 3476 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg)); 3477 return retval; 3478 } 3479 3480 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns 3481 the destination address. */ 3482 static rtx 3483 gen_tlsmoff (rtx addr, rtx reg) 3484 { 3485 rtx dest = gen_reg_rtx (Pmode); 3486 3487 if (TARGET_BIG_TLS) 3488 { 3489 /* sethi.p #tlsmoffhi(x), grA 3490 setlo #tlsmofflo(x), grA 3491 */ 3492 dest = gen_reg_rtx (Pmode); 3493 emit_insn (gen_tlsoff_hilo (dest, addr, 3494 GEN_INT (R_FRV_TLSMOFFHI))); 3495 dest = gen_rtx_PLUS (Pmode, dest, reg); 3496 } 3497 else 3498 { 3499 /* addi grB, #tlsmoff12(x), grC 3500 -or- 3501 ld/st @(grB, #tlsmoff12(x)), grC 3502 */ 3503 dest = gen_reg_rtx (Pmode); 3504 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg, 3505 GEN_INT (R_FRV_TLSMOFF12))); 3506 } 3507 return dest; 3508 } 3509 3510 /* Generate code for a TLS address. */ 3511 static rtx 3512 frv_legitimize_tls_address (rtx addr, enum tls_model model) 3513 { 3514 rtx dest, tp = gen_rtx_REG (Pmode, 29); 3515 rtx picreg = get_hard_reg_initial_val (Pmode, 15); 3516 3517 switch (model) 3518 { 3519 case TLS_MODEL_INITIAL_EXEC: 3520 if (flag_pic == 1) 3521 { 3522 /* -fpic version. 3523 ldi @(gr15, #gottlsoff12(x)), gr5 3524 */ 3525 dest = gen_reg_rtx (Pmode); 3526 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg)); 3527 dest = gen_rtx_PLUS (Pmode, tp, dest); 3528 } 3529 else 3530 { 3531 /* -fPIC or anything else. 3532 3533 sethi.p #gottlsoffhi(x), gr14 3534 setlo #gottlsofflo(x), gr14 3535 ld #tlsoff(x)@(gr15, gr14), gr9 3536 */ 3537 rtx tmp = gen_reg_rtx (Pmode); 3538 dest = gen_reg_rtx (Pmode); 3539 emit_insn (gen_tlsoff_hilo (tmp, addr, 3540 GEN_INT (R_FRV_GOTTLSOFF_HI))); 3541 3542 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr)); 3543 dest = gen_rtx_PLUS (Pmode, tp, dest); 3544 } 3545 break; 3546 case TLS_MODEL_LOCAL_DYNAMIC: 3547 { 3548 rtx reg, retval; 3549 3550 if (TARGET_INLINE_PLT) 3551 retval = gen_inlined_tls_plt (GEN_INT (0)); 3552 else 3553 { 3554 /* call #gettlsoff(0) */ 3555 retval = gen_reg_rtx (Pmode); 3556 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg)); 3557 } 3558 3559 reg = gen_reg_rtx (Pmode); 3560 emit_insn (gen_rtx_SET (reg, gen_rtx_PLUS (Pmode, retval, tp))); 3561 3562 dest = gen_tlsmoff (addr, reg); 3563 3564 /* 3565 dest = gen_reg_rtx (Pmode); 3566 emit_insn (gen_tlsoff_hilo (dest, addr, 3567 GEN_INT (R_FRV_TLSMOFFHI))); 3568 dest = gen_rtx_PLUS (Pmode, dest, reg); 3569 */ 3570 break; 3571 } 3572 case TLS_MODEL_LOCAL_EXEC: 3573 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29)); 3574 break; 3575 case TLS_MODEL_GLOBAL_DYNAMIC: 3576 { 3577 rtx retval; 3578 3579 if (TARGET_INLINE_PLT) 3580 retval = gen_inlined_tls_plt (addr); 3581 else 3582 { 3583 /* call #gettlsoff(x) */ 3584 retval = gen_reg_rtx (Pmode); 3585 emit_insn (gen_call_gettlsoff (retval, addr, picreg)); 3586 } 3587 dest = gen_rtx_PLUS (Pmode, retval, tp); 3588 break; 3589 } 3590 default: 3591 gcc_unreachable (); 3592 } 3593 3594 return dest; 3595 } 3596 3597 rtx 3598 frv_legitimize_address (rtx x, 3599 rtx oldx ATTRIBUTE_UNUSED, 3600 machine_mode mode ATTRIBUTE_UNUSED) 3601 { 3602 if (GET_CODE (x) == SYMBOL_REF) 3603 { 3604 enum tls_model model = SYMBOL_REF_TLS_MODEL (x); 3605 if (model != 0) 3606 return frv_legitimize_tls_address (x, model); 3607 } 3608 3609 return x; 3610 } 3611 3612 /* Test whether a local function descriptor is canonical, i.e., 3613 whether we can use FUNCDESC_GOTOFF to compute the address of the 3614 function. */ 3615 3616 static bool 3617 frv_local_funcdesc_p (rtx fnx) 3618 { 3619 tree fn; 3620 enum symbol_visibility vis; 3621 bool ret; 3622 3623 if (! SYMBOL_REF_LOCAL_P (fnx)) 3624 return FALSE; 3625 3626 fn = SYMBOL_REF_DECL (fnx); 3627 3628 if (! fn) 3629 return FALSE; 3630 3631 vis = DECL_VISIBILITY (fn); 3632 3633 if (vis == VISIBILITY_PROTECTED) 3634 /* Private function descriptors for protected functions are not 3635 canonical. Temporarily change the visibility to global. */ 3636 vis = VISIBILITY_DEFAULT; 3637 else if (flag_shlib) 3638 /* If we're already compiling for a shared library (that, unlike 3639 executables, can't assume that the existence of a definition 3640 implies local binding), we can skip the re-testing. */ 3641 return TRUE; 3642 3643 ret = default_binds_local_p_1 (fn, flag_pic); 3644 3645 DECL_VISIBILITY (fn) = vis; 3646 3647 return ret; 3648 } 3649 3650 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC 3651 register. */ 3652 3653 rtx 3654 frv_gen_GPsym2reg (rtx dest, rtx src) 3655 { 3656 tree gp = get_identifier ("_gp"); 3657 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp)); 3658 3659 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12)); 3660 } 3661 3662 static const char * 3663 unspec_got_name (int i) 3664 { 3665 switch (i) 3666 { 3667 case R_FRV_GOT12: return "got12"; 3668 case R_FRV_GOTHI: return "gothi"; 3669 case R_FRV_GOTLO: return "gotlo"; 3670 case R_FRV_FUNCDESC: return "funcdesc"; 3671 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12"; 3672 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi"; 3673 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo"; 3674 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue"; 3675 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12"; 3676 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi"; 3677 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo"; 3678 case R_FRV_GOTOFF12: return "gotoff12"; 3679 case R_FRV_GOTOFFHI: return "gotoffhi"; 3680 case R_FRV_GOTOFFLO: return "gotofflo"; 3681 case R_FRV_GPREL12: return "gprel12"; 3682 case R_FRV_GPRELHI: return "gprelhi"; 3683 case R_FRV_GPRELLO: return "gprello"; 3684 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi"; 3685 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo"; 3686 case R_FRV_TLSMOFFHI: return "tlsmoffhi"; 3687 case R_FRV_TLSMOFFLO: return "tlsmofflo"; 3688 case R_FRV_TLSMOFF12: return "tlsmoff12"; 3689 case R_FRV_TLSDESCHI: return "tlsdeschi"; 3690 case R_FRV_TLSDESCLO: return "tlsdesclo"; 3691 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi"; 3692 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo"; 3693 default: gcc_unreachable (); 3694 } 3695 } 3696 3697 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset 3698 is added inside the relocation operator. */ 3699 3700 static void 3701 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec) 3702 { 3703 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc)); 3704 output_addr_const (stream, plus_constant (Pmode, unspec->symbol, 3705 unspec->offset)); 3706 fputs (")", stream); 3707 } 3708 3709 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo) 3710 or #gotoff12(foo) for some small data symbol foo. If so, return foo, 3711 otherwise return ORIG_X. */ 3712 3713 rtx 3714 frv_find_base_term (rtx x) 3715 { 3716 struct frv_unspec unspec; 3717 3718 if (frv_const_unspec_p (x, &unspec) 3719 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc)) 3720 return plus_constant (Pmode, unspec.symbol, unspec.offset); 3721 3722 return x; 3723 } 3724 3725 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if 3726 the operand is used by a predicated instruction. */ 3727 3728 int 3729 frv_legitimate_memory_operand (rtx op, machine_mode mode, int condexec_p) 3730 { 3731 return ((GET_MODE (op) == mode || mode == VOIDmode) 3732 && GET_CODE (op) == MEM 3733 && frv_legitimate_address_p_1 (mode, XEXP (op, 0), 3734 reload_completed, condexec_p, FALSE)); 3735 } 3736 3737 void 3738 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall) 3739 { 3740 rtx lr = gen_rtx_REG (Pmode, LR_REGNO); 3741 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG); 3742 rtx c, rvrtx=0; 3743 rtx addr; 3744 3745 if (ret_value) 3746 { 3747 rvrtx = operands[0]; 3748 operands ++; 3749 } 3750 3751 addr = XEXP (operands[0], 0); 3752 3753 /* Inline PLTs if we're optimizing for speed. We'd like to inline 3754 any calls that would involve a PLT, but can't tell, since we 3755 don't know whether an extern function is going to be provided by 3756 a separate translation unit or imported from a separate module. 3757 When compiling for shared libraries, if the function has default 3758 visibility, we assume it's overridable, so we inline the PLT, but 3759 for executables, we don't really have a way to make a good 3760 decision: a function is as likely to be imported from a shared 3761 library as it is to be defined in the executable itself. We 3762 assume executables will get global functions defined locally, 3763 whereas shared libraries will have them potentially overridden, 3764 so we only inline PLTs when compiling for shared libraries. 3765 3766 In order to mark a function as local to a shared library, any 3767 non-default visibility attribute suffices. Unfortunately, 3768 there's no simple way to tag a function declaration as ``in a 3769 different module'', which we could then use to trigger PLT 3770 inlining on executables. There's -minline-plt, but it affects 3771 all external functions, so one would have to also mark function 3772 declarations available in the same module with non-default 3773 visibility, which is advantageous in itself. */ 3774 if (GET_CODE (addr) == SYMBOL_REF 3775 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT) 3776 || sibcall)) 3777 { 3778 rtx x, dest; 3779 dest = gen_reg_rtx (SImode); 3780 if (flag_pic != 1) 3781 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG, 3782 GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); 3783 else 3784 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG, 3785 GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); 3786 emit_insn (x); 3787 crtl->uses_pic_offset_table = TRUE; 3788 addr = dest; 3789 } 3790 else if (GET_CODE (addr) == SYMBOL_REF) 3791 { 3792 /* These are always either local, or handled through a local 3793 PLT. */ 3794 if (ret_value) 3795 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1], 3796 operands[2], picreg, lr); 3797 else 3798 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr); 3799 emit_call_insn (c); 3800 return; 3801 } 3802 else if (! ldd_address_operand (addr, Pmode)) 3803 addr = force_reg (Pmode, addr); 3804 3805 picreg = gen_reg_rtx (DImode); 3806 emit_insn (gen_movdi_ldd (picreg, addr)); 3807 3808 if (sibcall && ret_value) 3809 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx); 3810 else if (sibcall) 3811 c = gen_sibcall_fdpicdi (picreg, const0_rtx); 3812 else if (ret_value) 3813 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr); 3814 else 3815 c = gen_call_fdpicdi (picreg, const0_rtx, lr); 3816 emit_call_insn (c); 3817 } 3818 3819 /* Look for a SYMBOL_REF of a function in an rtx. We always want to 3820 process these separately from any offsets, such that we add any 3821 offsets to the function descriptor (the actual pointer), not to the 3822 function address. */ 3823 3824 static bool 3825 frv_function_symbol_referenced_p (rtx x) 3826 { 3827 const char *format; 3828 int length; 3829 int j; 3830 3831 if (GET_CODE (x) == SYMBOL_REF) 3832 return SYMBOL_REF_FUNCTION_P (x); 3833 3834 length = GET_RTX_LENGTH (GET_CODE (x)); 3835 format = GET_RTX_FORMAT (GET_CODE (x)); 3836 3837 for (j = 0; j < length; ++j) 3838 { 3839 switch (format[j]) 3840 { 3841 case 'e': 3842 if (frv_function_symbol_referenced_p (XEXP (x, j))) 3843 return TRUE; 3844 break; 3845 3846 case 'V': 3847 case 'E': 3848 if (XVEC (x, j) != 0) 3849 { 3850 int k; 3851 for (k = 0; k < XVECLEN (x, j); ++k) 3852 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k))) 3853 return TRUE; 3854 } 3855 break; 3856 3857 default: 3858 /* Nothing to do. */ 3859 break; 3860 } 3861 } 3862 3863 return FALSE; 3864 } 3865 3866 /* Return true if the memory operand is one that can be conditionally 3867 executed. */ 3868 3869 int 3870 condexec_memory_operand (rtx op, machine_mode mode) 3871 { 3872 machine_mode op_mode = GET_MODE (op); 3873 rtx addr; 3874 3875 if (mode != VOIDmode && op_mode != mode) 3876 return FALSE; 3877 3878 switch (op_mode) 3879 { 3880 default: 3881 return FALSE; 3882 3883 case E_QImode: 3884 case E_HImode: 3885 case E_SImode: 3886 case E_SFmode: 3887 break; 3888 } 3889 3890 if (GET_CODE (op) != MEM) 3891 return FALSE; 3892 3893 addr = XEXP (op, 0); 3894 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE); 3895 } 3896 3897 /* Return true if the bare return instruction can be used outside of the 3898 epilog code. For frv, we only do it if there was no stack allocation. */ 3899 3900 int 3901 direct_return_p (void) 3902 { 3903 frv_stack_t *info; 3904 3905 if (!reload_completed) 3906 return FALSE; 3907 3908 info = frv_stack_info (); 3909 return (info->total_size == 0); 3910 } 3911 3912 3913 void 3914 frv_emit_move (machine_mode mode, rtx dest, rtx src) 3915 { 3916 if (GET_CODE (src) == SYMBOL_REF) 3917 { 3918 enum tls_model model = SYMBOL_REF_TLS_MODEL (src); 3919 if (model != 0) 3920 src = frv_legitimize_tls_address (src, model); 3921 } 3922 3923 switch (mode) 3924 { 3925 case E_SImode: 3926 if (frv_emit_movsi (dest, src)) 3927 return; 3928 break; 3929 3930 case E_QImode: 3931 case E_HImode: 3932 case E_DImode: 3933 case E_SFmode: 3934 case E_DFmode: 3935 if (!reload_in_progress 3936 && !reload_completed 3937 && !register_operand (dest, mode) 3938 && !reg_or_0_operand (src, mode)) 3939 src = copy_to_mode_reg (mode, src); 3940 break; 3941 3942 default: 3943 gcc_unreachable (); 3944 } 3945 3946 emit_insn (gen_rtx_SET (dest, src)); 3947 } 3948 3949 /* Emit code to handle a MOVSI, adding in the small data register or pic 3950 register if needed to load up addresses. Return TRUE if the appropriate 3951 instructions are emitted. */ 3952 3953 int 3954 frv_emit_movsi (rtx dest, rtx src) 3955 { 3956 int base_regno = -1; 3957 int unspec = 0; 3958 rtx sym = src; 3959 struct frv_unspec old_unspec; 3960 3961 if (!reload_in_progress 3962 && !reload_completed 3963 && !register_operand (dest, SImode) 3964 && (!reg_or_0_operand (src, SImode) 3965 /* Virtual registers will almost always be replaced by an 3966 add instruction, so expose this to CSE by copying to 3967 an intermediate register. */ 3968 || (GET_CODE (src) == REG 3969 && IN_RANGE (REGNO (src), 3970 FIRST_VIRTUAL_REGISTER, 3971 LAST_VIRTUAL_POINTER_REGISTER)))) 3972 { 3973 emit_insn (gen_rtx_SET (dest, copy_to_mode_reg (SImode, src))); 3974 return TRUE; 3975 } 3976 3977 /* Explicitly add in the PIC or small data register if needed. */ 3978 switch (GET_CODE (src)) 3979 { 3980 default: 3981 break; 3982 3983 case LABEL_REF: 3984 handle_label: 3985 if (TARGET_FDPIC) 3986 { 3987 /* Using GPREL12, we use a single GOT entry for all symbols 3988 in read-only sections, but trade sequences such as: 3989 3990 sethi #gothi(label), gr# 3991 setlo #gotlo(label), gr# 3992 ld @(gr15,gr#), gr# 3993 3994 for 3995 3996 ld @(gr15,#got12(_gp)), gr# 3997 sethi #gprelhi(label), gr## 3998 setlo #gprello(label), gr## 3999 add gr#, gr##, gr## 4000 4001 We may often be able to share gr# for multiple 4002 computations of GPREL addresses, and we may often fold 4003 the final add into the pair of registers of a load or 4004 store instruction, so it's often profitable. Even when 4005 optimizing for size, we're trading a GOT entry for an 4006 additional instruction, which trades GOT space 4007 (read-write) for code size (read-only, shareable), as 4008 long as the symbol is not used in more than two different 4009 locations. 4010 4011 With -fpie/-fpic, we'd be trading a single load for a 4012 sequence of 4 instructions, because the offset of the 4013 label can't be assumed to be addressable with 12 bits, so 4014 we don't do this. */ 4015 if (TARGET_GPREL_RO) 4016 unspec = R_FRV_GPREL12; 4017 else 4018 unspec = R_FRV_GOT12; 4019 } 4020 else if (flag_pic) 4021 base_regno = PIC_REGNO; 4022 4023 break; 4024 4025 case CONST: 4026 if (frv_const_unspec_p (src, &old_unspec)) 4027 break; 4028 4029 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0))) 4030 { 4031 handle_whatever: 4032 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0)); 4033 emit_move_insn (dest, src); 4034 return TRUE; 4035 } 4036 else 4037 { 4038 sym = XEXP (sym, 0); 4039 if (GET_CODE (sym) == PLUS 4040 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF 4041 && GET_CODE (XEXP (sym, 1)) == CONST_INT) 4042 sym = XEXP (sym, 0); 4043 if (GET_CODE (sym) == SYMBOL_REF) 4044 goto handle_sym; 4045 else if (GET_CODE (sym) == LABEL_REF) 4046 goto handle_label; 4047 else 4048 goto handle_whatever; 4049 } 4050 break; 4051 4052 case SYMBOL_REF: 4053 handle_sym: 4054 if (TARGET_FDPIC) 4055 { 4056 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym); 4057 4058 if (model != 0) 4059 { 4060 src = frv_legitimize_tls_address (src, model); 4061 emit_move_insn (dest, src); 4062 return TRUE; 4063 } 4064 4065 if (SYMBOL_REF_FUNCTION_P (sym)) 4066 { 4067 if (frv_local_funcdesc_p (sym)) 4068 unspec = R_FRV_FUNCDESC_GOTOFF12; 4069 else 4070 unspec = R_FRV_FUNCDESC_GOT12; 4071 } 4072 else 4073 { 4074 if (CONSTANT_POOL_ADDRESS_P (sym)) 4075 switch (GET_CODE (get_pool_constant (sym))) 4076 { 4077 case CONST: 4078 case SYMBOL_REF: 4079 case LABEL_REF: 4080 if (flag_pic) 4081 { 4082 unspec = R_FRV_GOTOFF12; 4083 break; 4084 } 4085 /* Fall through. */ 4086 default: 4087 if (TARGET_GPREL_RO) 4088 unspec = R_FRV_GPREL12; 4089 else 4090 unspec = R_FRV_GOT12; 4091 break; 4092 } 4093 else if (SYMBOL_REF_LOCAL_P (sym) 4094 && !SYMBOL_REF_EXTERNAL_P (sym) 4095 && SYMBOL_REF_DECL (sym) 4096 && (!DECL_P (SYMBOL_REF_DECL (sym)) 4097 || !DECL_COMMON (SYMBOL_REF_DECL (sym)))) 4098 { 4099 tree decl = SYMBOL_REF_DECL (sym); 4100 tree init = TREE_CODE (decl) == VAR_DECL 4101 ? DECL_INITIAL (decl) 4102 : TREE_CODE (decl) == CONSTRUCTOR 4103 ? decl : 0; 4104 int reloc = 0; 4105 bool named_section, readonly; 4106 4107 if (init && init != error_mark_node) 4108 reloc = compute_reloc_for_constant (init); 4109 4110 named_section = TREE_CODE (decl) == VAR_DECL 4111 && lookup_attribute ("section", DECL_ATTRIBUTES (decl)); 4112 readonly = decl_readonly_section (decl, reloc); 4113 4114 if (named_section) 4115 unspec = R_FRV_GOT12; 4116 else if (!readonly) 4117 unspec = R_FRV_GOTOFF12; 4118 else if (readonly && TARGET_GPREL_RO) 4119 unspec = R_FRV_GPREL12; 4120 else 4121 unspec = R_FRV_GOT12; 4122 } 4123 else 4124 unspec = R_FRV_GOT12; 4125 } 4126 } 4127 4128 else if (SYMBOL_REF_SMALL_P (sym)) 4129 base_regno = SDA_BASE_REG; 4130 4131 else if (flag_pic) 4132 base_regno = PIC_REGNO; 4133 4134 break; 4135 } 4136 4137 if (base_regno >= 0) 4138 { 4139 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym)) 4140 emit_insn (gen_symGOTOFF2reg (dest, src, 4141 gen_rtx_REG (Pmode, base_regno), 4142 GEN_INT (R_FRV_GPREL12))); 4143 else 4144 emit_insn (gen_symGOTOFF2reg_hilo (dest, src, 4145 gen_rtx_REG (Pmode, base_regno), 4146 GEN_INT (R_FRV_GPREL12))); 4147 if (base_regno == PIC_REGNO) 4148 crtl->uses_pic_offset_table = TRUE; 4149 return TRUE; 4150 } 4151 4152 if (unspec) 4153 { 4154 rtx x; 4155 4156 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce 4157 new uses of it once reload has begun. */ 4158 gcc_assert (!reload_in_progress && !reload_completed); 4159 4160 switch (unspec) 4161 { 4162 case R_FRV_GOTOFF12: 4163 if (!frv_small_data_reloc_p (sym, unspec)) 4164 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, 4165 GEN_INT (unspec)); 4166 else 4167 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); 4168 break; 4169 case R_FRV_GPREL12: 4170 if (!frv_small_data_reloc_p (sym, unspec)) 4171 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG, 4172 GEN_INT (unspec)); 4173 else 4174 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); 4175 break; 4176 case R_FRV_FUNCDESC_GOTOFF12: 4177 if (flag_pic != 1) 4178 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, 4179 GEN_INT (unspec)); 4180 else 4181 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); 4182 break; 4183 default: 4184 if (flag_pic != 1) 4185 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG, 4186 GEN_INT (unspec)); 4187 else 4188 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); 4189 break; 4190 } 4191 emit_insn (x); 4192 crtl->uses_pic_offset_table = TRUE; 4193 return TRUE; 4194 } 4195 4196 4197 return FALSE; 4198 } 4199 4200 4201 /* Return a string to output a single word move. */ 4202 4203 const char * 4204 output_move_single (rtx operands[], rtx insn) 4205 { 4206 rtx dest = operands[0]; 4207 rtx src = operands[1]; 4208 4209 if (GET_CODE (dest) == REG) 4210 { 4211 int dest_regno = REGNO (dest); 4212 machine_mode mode = GET_MODE (dest); 4213 4214 if (GPR_P (dest_regno)) 4215 { 4216 if (GET_CODE (src) == REG) 4217 { 4218 /* gpr <- some sort of register */ 4219 int src_regno = REGNO (src); 4220 4221 if (GPR_P (src_regno)) 4222 return "mov %1, %0"; 4223 4224 else if (FPR_P (src_regno)) 4225 return "movfg %1, %0"; 4226 4227 else if (SPR_P (src_regno)) 4228 return "movsg %1, %0"; 4229 } 4230 4231 else if (GET_CODE (src) == MEM) 4232 { 4233 /* gpr <- memory */ 4234 switch (mode) 4235 { 4236 default: 4237 break; 4238 4239 case E_QImode: 4240 return "ldsb%I1%U1 %M1,%0"; 4241 4242 case E_HImode: 4243 return "ldsh%I1%U1 %M1,%0"; 4244 4245 case E_SImode: 4246 case E_SFmode: 4247 return "ld%I1%U1 %M1, %0"; 4248 } 4249 } 4250 4251 else if (GET_CODE (src) == CONST_INT 4252 || GET_CODE (src) == CONST_DOUBLE) 4253 { 4254 /* gpr <- integer/floating constant */ 4255 HOST_WIDE_INT value; 4256 4257 if (GET_CODE (src) == CONST_INT) 4258 value = INTVAL (src); 4259 4260 else if (mode == SFmode) 4261 { 4262 long l; 4263 4264 REAL_VALUE_TO_TARGET_SINGLE 4265 (*CONST_DOUBLE_REAL_VALUE (src), l); 4266 value = l; 4267 } 4268 4269 else 4270 value = CONST_DOUBLE_LOW (src); 4271 4272 if (IN_RANGE (value, -32768, 32767)) 4273 return "setlos %1, %0"; 4274 4275 return "#"; 4276 } 4277 4278 else if (GET_CODE (src) == SYMBOL_REF 4279 || GET_CODE (src) == LABEL_REF 4280 || GET_CODE (src) == CONST) 4281 { 4282 return "#"; 4283 } 4284 } 4285 4286 else if (FPR_P (dest_regno)) 4287 { 4288 if (GET_CODE (src) == REG) 4289 { 4290 /* fpr <- some sort of register */ 4291 int src_regno = REGNO (src); 4292 4293 if (GPR_P (src_regno)) 4294 return "movgf %1, %0"; 4295 4296 else if (FPR_P (src_regno)) 4297 { 4298 if (TARGET_HARD_FLOAT) 4299 return "fmovs %1, %0"; 4300 else 4301 return "mor %1, %1, %0"; 4302 } 4303 } 4304 4305 else if (GET_CODE (src) == MEM) 4306 { 4307 /* fpr <- memory */ 4308 switch (mode) 4309 { 4310 default: 4311 break; 4312 4313 case E_QImode: 4314 return "ldbf%I1%U1 %M1,%0"; 4315 4316 case E_HImode: 4317 return "ldhf%I1%U1 %M1,%0"; 4318 4319 case E_SImode: 4320 case E_SFmode: 4321 return "ldf%I1%U1 %M1, %0"; 4322 } 4323 } 4324 4325 else if (ZERO_P (src)) 4326 return "movgf %., %0"; 4327 } 4328 4329 else if (SPR_P (dest_regno)) 4330 { 4331 if (GET_CODE (src) == REG) 4332 { 4333 /* spr <- some sort of register */ 4334 int src_regno = REGNO (src); 4335 4336 if (GPR_P (src_regno)) 4337 return "movgs %1, %0"; 4338 } 4339 else if (ZERO_P (src)) 4340 return "movgs %., %0"; 4341 } 4342 } 4343 4344 else if (GET_CODE (dest) == MEM) 4345 { 4346 if (GET_CODE (src) == REG) 4347 { 4348 int src_regno = REGNO (src); 4349 machine_mode mode = GET_MODE (dest); 4350 4351 if (GPR_P (src_regno)) 4352 { 4353 switch (mode) 4354 { 4355 default: 4356 break; 4357 4358 case E_QImode: 4359 return "stb%I0%U0 %1, %M0"; 4360 4361 case E_HImode: 4362 return "sth%I0%U0 %1, %M0"; 4363 4364 case E_SImode: 4365 case E_SFmode: 4366 return "st%I0%U0 %1, %M0"; 4367 } 4368 } 4369 4370 else if (FPR_P (src_regno)) 4371 { 4372 switch (mode) 4373 { 4374 default: 4375 break; 4376 4377 case E_QImode: 4378 return "stbf%I0%U0 %1, %M0"; 4379 4380 case E_HImode: 4381 return "sthf%I0%U0 %1, %M0"; 4382 4383 case E_SImode: 4384 case E_SFmode: 4385 return "stf%I0%U0 %1, %M0"; 4386 } 4387 } 4388 } 4389 4390 else if (ZERO_P (src)) 4391 { 4392 switch (GET_MODE (dest)) 4393 { 4394 default: 4395 break; 4396 4397 case E_QImode: 4398 return "stb%I0%U0 %., %M0"; 4399 4400 case E_HImode: 4401 return "sth%I0%U0 %., %M0"; 4402 4403 case E_SImode: 4404 case E_SFmode: 4405 return "st%I0%U0 %., %M0"; 4406 } 4407 } 4408 } 4409 4410 fatal_insn ("bad output_move_single operand", insn); 4411 return ""; 4412 } 4413 4414 4415 /* Return a string to output a double word move. */ 4416 4417 const char * 4418 output_move_double (rtx operands[], rtx insn) 4419 { 4420 rtx dest = operands[0]; 4421 rtx src = operands[1]; 4422 machine_mode mode = GET_MODE (dest); 4423 4424 if (GET_CODE (dest) == REG) 4425 { 4426 int dest_regno = REGNO (dest); 4427 4428 if (GPR_P (dest_regno)) 4429 { 4430 if (GET_CODE (src) == REG) 4431 { 4432 /* gpr <- some sort of register */ 4433 int src_regno = REGNO (src); 4434 4435 if (GPR_P (src_regno)) 4436 return "#"; 4437 4438 else if (FPR_P (src_regno)) 4439 { 4440 if (((dest_regno - GPR_FIRST) & 1) == 0 4441 && ((src_regno - FPR_FIRST) & 1) == 0) 4442 return "movfgd %1, %0"; 4443 4444 return "#"; 4445 } 4446 } 4447 4448 else if (GET_CODE (src) == MEM) 4449 { 4450 /* gpr <- memory */ 4451 if (dbl_memory_one_insn_operand (src, mode)) 4452 return "ldd%I1%U1 %M1, %0"; 4453 4454 return "#"; 4455 } 4456 4457 else if (GET_CODE (src) == CONST_INT 4458 || GET_CODE (src) == CONST_DOUBLE) 4459 return "#"; 4460 } 4461 4462 else if (FPR_P (dest_regno)) 4463 { 4464 if (GET_CODE (src) == REG) 4465 { 4466 /* fpr <- some sort of register */ 4467 int src_regno = REGNO (src); 4468 4469 if (GPR_P (src_regno)) 4470 { 4471 if (((dest_regno - FPR_FIRST) & 1) == 0 4472 && ((src_regno - GPR_FIRST) & 1) == 0) 4473 return "movgfd %1, %0"; 4474 4475 return "#"; 4476 } 4477 4478 else if (FPR_P (src_regno)) 4479 { 4480 if (TARGET_DOUBLE 4481 && ((dest_regno - FPR_FIRST) & 1) == 0 4482 && ((src_regno - FPR_FIRST) & 1) == 0) 4483 return "fmovd %1, %0"; 4484 4485 return "#"; 4486 } 4487 } 4488 4489 else if (GET_CODE (src) == MEM) 4490 { 4491 /* fpr <- memory */ 4492 if (dbl_memory_one_insn_operand (src, mode)) 4493 return "lddf%I1%U1 %M1, %0"; 4494 4495 return "#"; 4496 } 4497 4498 else if (ZERO_P (src)) 4499 return "#"; 4500 } 4501 } 4502 4503 else if (GET_CODE (dest) == MEM) 4504 { 4505 if (GET_CODE (src) == REG) 4506 { 4507 int src_regno = REGNO (src); 4508 4509 if (GPR_P (src_regno)) 4510 { 4511 if (((src_regno - GPR_FIRST) & 1) == 0 4512 && dbl_memory_one_insn_operand (dest, mode)) 4513 return "std%I0%U0 %1, %M0"; 4514 4515 return "#"; 4516 } 4517 4518 if (FPR_P (src_regno)) 4519 { 4520 if (((src_regno - FPR_FIRST) & 1) == 0 4521 && dbl_memory_one_insn_operand (dest, mode)) 4522 return "stdf%I0%U0 %1, %M0"; 4523 4524 return "#"; 4525 } 4526 } 4527 4528 else if (ZERO_P (src)) 4529 { 4530 if (dbl_memory_one_insn_operand (dest, mode)) 4531 return "std%I0%U0 %., %M0"; 4532 4533 return "#"; 4534 } 4535 } 4536 4537 fatal_insn ("bad output_move_double operand", insn); 4538 return ""; 4539 } 4540 4541 4542 /* Return a string to output a single word conditional move. 4543 Operand0 -- EQ/NE of ccr register and 0 4544 Operand1 -- CCR register 4545 Operand2 -- destination 4546 Operand3 -- source */ 4547 4548 const char * 4549 output_condmove_single (rtx operands[], rtx insn) 4550 { 4551 rtx dest = operands[2]; 4552 rtx src = operands[3]; 4553 4554 if (GET_CODE (dest) == REG) 4555 { 4556 int dest_regno = REGNO (dest); 4557 machine_mode mode = GET_MODE (dest); 4558 4559 if (GPR_P (dest_regno)) 4560 { 4561 if (GET_CODE (src) == REG) 4562 { 4563 /* gpr <- some sort of register */ 4564 int src_regno = REGNO (src); 4565 4566 if (GPR_P (src_regno)) 4567 return "cmov %z3, %2, %1, %e0"; 4568 4569 else if (FPR_P (src_regno)) 4570 return "cmovfg %3, %2, %1, %e0"; 4571 } 4572 4573 else if (GET_CODE (src) == MEM) 4574 { 4575 /* gpr <- memory */ 4576 switch (mode) 4577 { 4578 default: 4579 break; 4580 4581 case E_QImode: 4582 return "cldsb%I3%U3 %M3, %2, %1, %e0"; 4583 4584 case E_HImode: 4585 return "cldsh%I3%U3 %M3, %2, %1, %e0"; 4586 4587 case E_SImode: 4588 case E_SFmode: 4589 return "cld%I3%U3 %M3, %2, %1, %e0"; 4590 } 4591 } 4592 4593 else if (ZERO_P (src)) 4594 return "cmov %., %2, %1, %e0"; 4595 } 4596 4597 else if (FPR_P (dest_regno)) 4598 { 4599 if (GET_CODE (src) == REG) 4600 { 4601 /* fpr <- some sort of register */ 4602 int src_regno = REGNO (src); 4603 4604 if (GPR_P (src_regno)) 4605 return "cmovgf %3, %2, %1, %e0"; 4606 4607 else if (FPR_P (src_regno)) 4608 { 4609 if (TARGET_HARD_FLOAT) 4610 return "cfmovs %3,%2,%1,%e0"; 4611 else 4612 return "cmor %3, %3, %2, %1, %e0"; 4613 } 4614 } 4615 4616 else if (GET_CODE (src) == MEM) 4617 { 4618 /* fpr <- memory */ 4619 if (mode == SImode || mode == SFmode) 4620 return "cldf%I3%U3 %M3, %2, %1, %e0"; 4621 } 4622 4623 else if (ZERO_P (src)) 4624 return "cmovgf %., %2, %1, %e0"; 4625 } 4626 } 4627 4628 else if (GET_CODE (dest) == MEM) 4629 { 4630 if (GET_CODE (src) == REG) 4631 { 4632 int src_regno = REGNO (src); 4633 machine_mode mode = GET_MODE (dest); 4634 4635 if (GPR_P (src_regno)) 4636 { 4637 switch (mode) 4638 { 4639 default: 4640 break; 4641 4642 case E_QImode: 4643 return "cstb%I2%U2 %3, %M2, %1, %e0"; 4644 4645 case E_HImode: 4646 return "csth%I2%U2 %3, %M2, %1, %e0"; 4647 4648 case E_SImode: 4649 case E_SFmode: 4650 return "cst%I2%U2 %3, %M2, %1, %e0"; 4651 } 4652 } 4653 4654 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode)) 4655 return "cstf%I2%U2 %3, %M2, %1, %e0"; 4656 } 4657 4658 else if (ZERO_P (src)) 4659 { 4660 machine_mode mode = GET_MODE (dest); 4661 switch (mode) 4662 { 4663 default: 4664 break; 4665 4666 case E_QImode: 4667 return "cstb%I2%U2 %., %M2, %1, %e0"; 4668 4669 case E_HImode: 4670 return "csth%I2%U2 %., %M2, %1, %e0"; 4671 4672 case E_SImode: 4673 case E_SFmode: 4674 return "cst%I2%U2 %., %M2, %1, %e0"; 4675 } 4676 } 4677 } 4678 4679 fatal_insn ("bad output_condmove_single operand", insn); 4680 return ""; 4681 } 4682 4683 4684 /* Emit the appropriate code to do a comparison, returning the register the 4685 comparison was done it. */ 4686 4687 static rtx 4688 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1) 4689 { 4690 machine_mode cc_mode; 4691 rtx cc_reg; 4692 4693 /* Floating point doesn't have comparison against a constant. */ 4694 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG) 4695 op1 = force_reg (GET_MODE (op0), op1); 4696 4697 /* Possibly disable using anything but a fixed register in order to work 4698 around cse moving comparisons past function calls. */ 4699 cc_mode = SELECT_CC_MODE (test, op0, op1); 4700 cc_reg = ((TARGET_ALLOC_CC) 4701 ? gen_reg_rtx (cc_mode) 4702 : gen_rtx_REG (cc_mode, 4703 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST)); 4704 4705 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (cc_mode, op0, op1))); 4706 4707 return cc_reg; 4708 } 4709 4710 4711 /* Emit code for a conditional branch. 4712 XXX: I originally wanted to add a clobber of a CCR register to use in 4713 conditional execution, but that confuses the rest of the compiler. */ 4714 4715 int 4716 frv_emit_cond_branch (rtx operands[]) 4717 { 4718 rtx test_rtx; 4719 rtx label_ref; 4720 rtx if_else; 4721 enum rtx_code test = GET_CODE (operands[0]); 4722 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]); 4723 machine_mode cc_mode = GET_MODE (cc_reg); 4724 4725 /* Branches generate: 4726 (set (pc) 4727 (if_then_else (<test>, <cc_reg>, (const_int 0)) 4728 (label_ref <branch_label>) 4729 (pc))) */ 4730 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]); 4731 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); 4732 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx); 4733 emit_jump_insn (gen_rtx_SET (pc_rtx, if_else)); 4734 return TRUE; 4735 } 4736 4737 4738 /* Emit code to set a gpr to 1/0 based on a comparison. */ 4739 4740 int 4741 frv_emit_scc (rtx operands[]) 4742 { 4743 rtx set; 4744 rtx test_rtx; 4745 rtx clobber; 4746 rtx cr_reg; 4747 enum rtx_code test = GET_CODE (operands[1]); 4748 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]); 4749 4750 /* SCC instructions generate: 4751 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0)) 4752 (clobber (<ccr_reg>))]) */ 4753 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx); 4754 set = gen_rtx_SET (operands[0], test_rtx); 4755 4756 cr_reg = ((TARGET_ALLOC_CC) 4757 ? gen_reg_rtx (CC_CCRmode) 4758 : gen_rtx_REG (CC_CCRmode, 4759 ((GET_MODE (cc_reg) == CC_FPmode) 4760 ? FCR_FIRST 4761 : ICR_FIRST))); 4762 4763 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg); 4764 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); 4765 return TRUE; 4766 } 4767 4768 4769 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold 4770 the separate insns. */ 4771 4772 rtx 4773 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value) 4774 { 4775 rtx ret; 4776 4777 start_sequence (); 4778 4779 /* Set the appropriate CCR bit. */ 4780 emit_insn (gen_rtx_SET (cr_reg, 4781 gen_rtx_fmt_ee (GET_CODE (test), 4782 GET_MODE (cr_reg), 4783 cc_reg, 4784 const0_rtx))); 4785 4786 /* Move the value into the destination. */ 4787 emit_move_insn (dest, GEN_INT (value)); 4788 4789 /* Move 0 into the destination if the test failed */ 4790 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 4791 gen_rtx_EQ (GET_MODE (cr_reg), 4792 cr_reg, 4793 const0_rtx), 4794 gen_rtx_SET (dest, const0_rtx))); 4795 4796 /* Finish up, return sequence. */ 4797 ret = get_insns (); 4798 end_sequence (); 4799 return ret; 4800 } 4801 4802 4803 /* Emit the code for a conditional move, return TRUE if we could do the 4804 move. */ 4805 4806 int 4807 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2) 4808 { 4809 rtx set; 4810 rtx clobber_cc; 4811 rtx test2; 4812 rtx cr_reg; 4813 rtx if_rtx; 4814 enum rtx_code test = GET_CODE (test_rtx); 4815 rtx cc_reg = frv_emit_comparison (test, 4816 XEXP (test_rtx, 0), XEXP (test_rtx, 1)); 4817 machine_mode cc_mode = GET_MODE (cc_reg); 4818 4819 /* Conditional move instructions generate: 4820 (parallel [(set <target> 4821 (if_then_else (<test> <cc_reg> (const_int 0)) 4822 <src1> 4823 <src2>)) 4824 (clobber (<ccr_reg>))]) */ 4825 4826 /* Handle various cases of conditional move involving two constants. */ 4827 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) 4828 { 4829 HOST_WIDE_INT value1 = INTVAL (src1); 4830 HOST_WIDE_INT value2 = INTVAL (src2); 4831 4832 /* Having 0 as one of the constants can be done by loading the other 4833 constant, and optionally moving in gr0. */ 4834 if (value1 == 0 || value2 == 0) 4835 ; 4836 4837 /* If the first value is within an addi range and also the difference 4838 between the two fits in an addi's range, load up the difference, then 4839 conditionally move in 0, and then unconditionally add the first 4840 value. */ 4841 else if (IN_RANGE (value1, -2048, 2047) 4842 && IN_RANGE (value2 - value1, -2048, 2047)) 4843 ; 4844 4845 /* If neither condition holds, just force the constant into a 4846 register. */ 4847 else 4848 { 4849 src1 = force_reg (GET_MODE (dest), src1); 4850 src2 = force_reg (GET_MODE (dest), src2); 4851 } 4852 } 4853 4854 /* If one value is a register, insure the other value is either 0 or a 4855 register. */ 4856 else 4857 { 4858 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0) 4859 src1 = force_reg (GET_MODE (dest), src1); 4860 4861 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) 4862 src2 = force_reg (GET_MODE (dest), src2); 4863 } 4864 4865 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); 4866 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2); 4867 4868 set = gen_rtx_SET (dest, if_rtx); 4869 4870 cr_reg = ((TARGET_ALLOC_CC) 4871 ? gen_reg_rtx (CC_CCRmode) 4872 : gen_rtx_REG (CC_CCRmode, 4873 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST)); 4874 4875 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg); 4876 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc))); 4877 return TRUE; 4878 } 4879 4880 4881 /* Split a conditional move into constituent parts, returning a SEQUENCE 4882 containing all of the insns. */ 4883 4884 rtx 4885 frv_split_cond_move (rtx operands[]) 4886 { 4887 rtx dest = operands[0]; 4888 rtx test = operands[1]; 4889 rtx cc_reg = operands[2]; 4890 rtx src1 = operands[3]; 4891 rtx src2 = operands[4]; 4892 rtx cr_reg = operands[5]; 4893 rtx ret; 4894 machine_mode cr_mode = GET_MODE (cr_reg); 4895 4896 start_sequence (); 4897 4898 /* Set the appropriate CCR bit. */ 4899 emit_insn (gen_rtx_SET (cr_reg, 4900 gen_rtx_fmt_ee (GET_CODE (test), 4901 GET_MODE (cr_reg), 4902 cc_reg, 4903 const0_rtx))); 4904 4905 /* Handle various cases of conditional move involving two constants. */ 4906 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) 4907 { 4908 HOST_WIDE_INT value1 = INTVAL (src1); 4909 HOST_WIDE_INT value2 = INTVAL (src2); 4910 4911 /* Having 0 as one of the constants can be done by loading the other 4912 constant, and optionally moving in gr0. */ 4913 if (value1 == 0) 4914 { 4915 emit_move_insn (dest, src2); 4916 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 4917 gen_rtx_NE (cr_mode, cr_reg, 4918 const0_rtx), 4919 gen_rtx_SET (dest, src1))); 4920 } 4921 4922 else if (value2 == 0) 4923 { 4924 emit_move_insn (dest, src1); 4925 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 4926 gen_rtx_EQ (cr_mode, cr_reg, 4927 const0_rtx), 4928 gen_rtx_SET (dest, src2))); 4929 } 4930 4931 /* If the first value is within an addi range and also the difference 4932 between the two fits in an addi's range, load up the difference, then 4933 conditionally move in 0, and then unconditionally add the first 4934 value. */ 4935 else if (IN_RANGE (value1, -2048, 2047) 4936 && IN_RANGE (value2 - value1, -2048, 2047)) 4937 { 4938 rtx dest_si = ((GET_MODE (dest) == SImode) 4939 ? dest 4940 : gen_rtx_SUBREG (SImode, dest, 0)); 4941 4942 emit_move_insn (dest_si, GEN_INT (value2 - value1)); 4943 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 4944 gen_rtx_NE (cr_mode, cr_reg, 4945 const0_rtx), 4946 gen_rtx_SET (dest_si, const0_rtx))); 4947 emit_insn (gen_addsi3 (dest_si, dest_si, src1)); 4948 } 4949 4950 else 4951 gcc_unreachable (); 4952 } 4953 else 4954 { 4955 /* Emit the conditional move for the test being true if needed. */ 4956 if (! rtx_equal_p (dest, src1)) 4957 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 4958 gen_rtx_NE (cr_mode, cr_reg, const0_rtx), 4959 gen_rtx_SET (dest, src1))); 4960 4961 /* Emit the conditional move for the test being false if needed. */ 4962 if (! rtx_equal_p (dest, src2)) 4963 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 4964 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), 4965 gen_rtx_SET (dest, src2))); 4966 } 4967 4968 /* Finish up, return sequence. */ 4969 ret = get_insns (); 4970 end_sequence (); 4971 return ret; 4972 } 4973 4974 4975 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a 4976 memory location that is not known to be dword-aligned. */ 4977 void 4978 frv_split_double_load (rtx dest, rtx source) 4979 { 4980 int regno = REGNO (dest); 4981 rtx dest1 = gen_highpart (SImode, dest); 4982 rtx dest2 = gen_lowpart (SImode, dest); 4983 rtx address = XEXP (source, 0); 4984 4985 /* If the address is pre-modified, load the lower-numbered register 4986 first, then load the other register using an integer offset from 4987 the modified base register. This order should always be safe, 4988 since the pre-modification cannot affect the same registers as the 4989 load does. 4990 4991 The situation for other loads is more complicated. Loading one 4992 of the registers could affect the value of ADDRESS, so we must 4993 be careful which order we do them in. */ 4994 if (GET_CODE (address) == PRE_MODIFY 4995 || ! refers_to_regno_p (regno, address)) 4996 { 4997 /* It is safe to load the lower-numbered register first. */ 4998 emit_move_insn (dest1, change_address (source, SImode, NULL)); 4999 emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); 5000 } 5001 else 5002 { 5003 /* ADDRESS is not pre-modified and the address depends on the 5004 lower-numbered register. Load the higher-numbered register 5005 first. */ 5006 emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); 5007 emit_move_insn (dest1, change_address (source, SImode, NULL)); 5008 } 5009 } 5010 5011 /* Split (set DEST SOURCE), where DEST refers to a dword memory location 5012 and SOURCE is either a double register or the constant zero. */ 5013 void 5014 frv_split_double_store (rtx dest, rtx source) 5015 { 5016 rtx dest1 = change_address (dest, SImode, NULL); 5017 rtx dest2 = frv_index_memory (dest, SImode, 1); 5018 if (ZERO_P (source)) 5019 { 5020 emit_move_insn (dest1, CONST0_RTX (SImode)); 5021 emit_move_insn (dest2, CONST0_RTX (SImode)); 5022 } 5023 else 5024 { 5025 emit_move_insn (dest1, gen_highpart (SImode, source)); 5026 emit_move_insn (dest2, gen_lowpart (SImode, source)); 5027 } 5028 } 5029 5030 5031 /* Split a min/max operation returning a SEQUENCE containing all of the 5032 insns. */ 5033 5034 rtx 5035 frv_split_minmax (rtx operands[]) 5036 { 5037 rtx dest = operands[0]; 5038 rtx minmax = operands[1]; 5039 rtx src1 = operands[2]; 5040 rtx src2 = operands[3]; 5041 rtx cc_reg = operands[4]; 5042 rtx cr_reg = operands[5]; 5043 rtx ret; 5044 enum rtx_code test_code; 5045 machine_mode cr_mode = GET_MODE (cr_reg); 5046 5047 start_sequence (); 5048 5049 /* Figure out which test to use. */ 5050 switch (GET_CODE (minmax)) 5051 { 5052 default: 5053 gcc_unreachable (); 5054 5055 case SMIN: test_code = LT; break; 5056 case SMAX: test_code = GT; break; 5057 case UMIN: test_code = LTU; break; 5058 case UMAX: test_code = GTU; break; 5059 } 5060 5061 /* Issue the compare instruction. */ 5062 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (GET_MODE (cc_reg), 5063 src1, src2))); 5064 5065 /* Set the appropriate CCR bit. */ 5066 emit_insn (gen_rtx_SET (cr_reg, gen_rtx_fmt_ee (test_code, 5067 GET_MODE (cr_reg), 5068 cc_reg, 5069 const0_rtx))); 5070 5071 /* If are taking the min/max of a nonzero constant, load that first, and 5072 then do a conditional move of the other value. */ 5073 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) 5074 { 5075 gcc_assert (!rtx_equal_p (dest, src1)); 5076 5077 emit_move_insn (dest, src2); 5078 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5079 gen_rtx_NE (cr_mode, cr_reg, const0_rtx), 5080 gen_rtx_SET (dest, src1))); 5081 } 5082 5083 /* Otherwise, do each half of the move. */ 5084 else 5085 { 5086 /* Emit the conditional move for the test being true if needed. */ 5087 if (! rtx_equal_p (dest, src1)) 5088 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5089 gen_rtx_NE (cr_mode, cr_reg, const0_rtx), 5090 gen_rtx_SET (dest, src1))); 5091 5092 /* Emit the conditional move for the test being false if needed. */ 5093 if (! rtx_equal_p (dest, src2)) 5094 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5095 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), 5096 gen_rtx_SET (dest, src2))); 5097 } 5098 5099 /* Finish up, return sequence. */ 5100 ret = get_insns (); 5101 end_sequence (); 5102 return ret; 5103 } 5104 5105 5106 /* Split an integer abs operation returning a SEQUENCE containing all of the 5107 insns. */ 5108 5109 rtx 5110 frv_split_abs (rtx operands[]) 5111 { 5112 rtx dest = operands[0]; 5113 rtx src = operands[1]; 5114 rtx cc_reg = operands[2]; 5115 rtx cr_reg = operands[3]; 5116 rtx ret; 5117 5118 start_sequence (); 5119 5120 /* Issue the compare < 0 instruction. */ 5121 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, src, const0_rtx))); 5122 5123 /* Set the appropriate CCR bit. */ 5124 emit_insn (gen_rtx_SET (cr_reg, gen_rtx_fmt_ee (LT, CC_CCRmode, 5125 cc_reg, const0_rtx))); 5126 5127 /* Emit the conditional negate if the value is negative. */ 5128 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5129 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx), 5130 gen_negsi2 (dest, src))); 5131 5132 /* Emit the conditional move for the test being false if needed. */ 5133 if (! rtx_equal_p (dest, src)) 5134 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5135 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx), 5136 gen_rtx_SET (dest, src))); 5137 5138 /* Finish up, return sequence. */ 5139 ret = get_insns (); 5140 end_sequence (); 5141 return ret; 5142 } 5143 5144 5145 /* Initialize machine-specific if-conversion data. 5146 On the FR-V, we don't have any extra fields per se, but it is useful hook to 5147 initialize the static storage. */ 5148 void 5149 frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED) 5150 { 5151 frv_ifcvt.added_insns_list = NULL_RTX; 5152 frv_ifcvt.cur_scratch_regs = 0; 5153 frv_ifcvt.num_nested_cond_exec = 0; 5154 frv_ifcvt.cr_reg = NULL_RTX; 5155 frv_ifcvt.nested_cc_reg = NULL_RTX; 5156 frv_ifcvt.extra_int_cr = NULL_RTX; 5157 frv_ifcvt.extra_fp_cr = NULL_RTX; 5158 frv_ifcvt.last_nested_if_cr = NULL_RTX; 5159 } 5160 5161 5162 /* Internal function to add a potential insn to the list of insns to be inserted 5163 if the conditional execution conversion is successful. */ 5164 5165 static void 5166 frv_ifcvt_add_insn (rtx pattern, rtx_insn *insn, int before_p) 5167 { 5168 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn); 5169 5170 link->jump = before_p; /* Mark to add this before or after insn. */ 5171 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link, 5172 frv_ifcvt.added_insns_list); 5173 5174 if (TARGET_DEBUG_COND_EXEC) 5175 { 5176 fprintf (stderr, 5177 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n", 5178 (before_p) ? "before" : "after", 5179 (int)INSN_UID (insn)); 5180 5181 debug_rtx (pattern); 5182 } 5183 } 5184 5185 5186 /* A C expression to modify the code described by the conditional if 5187 information CE_INFO, possibly updating the tests in TRUE_EXPR, and 5188 FALSE_EXPR for converting if-then and if-then-else code to conditional 5189 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the 5190 tests cannot be converted. */ 5191 5192 void 5193 frv_ifcvt_modify_tests (ce_if_block *ce_info, rtx *p_true, rtx *p_false) 5194 { 5195 basic_block test_bb = ce_info->test_bb; /* test basic block */ 5196 basic_block then_bb = ce_info->then_bb; /* THEN */ 5197 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */ 5198 basic_block join_bb = ce_info->join_bb; /* join block or NULL */ 5199 rtx true_expr = *p_true; 5200 rtx cr; 5201 rtx cc; 5202 rtx nested_cc; 5203 machine_mode mode = GET_MODE (true_expr); 5204 int j; 5205 basic_block *bb; 5206 int num_bb; 5207 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg; 5208 rtx check_insn; 5209 rtx sub_cond_exec_reg; 5210 enum rtx_code code; 5211 enum rtx_code code_true; 5212 enum rtx_code code_false; 5213 enum reg_class cc_class; 5214 enum reg_class cr_class; 5215 int cc_first; 5216 int cc_last; 5217 reg_set_iterator rsi; 5218 5219 /* Make sure we are only dealing with hard registers. Also honor the 5220 -mno-cond-exec switch, and -mno-nested-cond-exec switches if 5221 applicable. */ 5222 if (!reload_completed || !TARGET_COND_EXEC 5223 || (!TARGET_NESTED_CE && ce_info->pass > 1)) 5224 goto fail; 5225 5226 /* Figure out which registers we can allocate for our own purposes. Only 5227 consider registers that are not preserved across function calls and are 5228 not fixed. However, allow the ICC/ICR temporary registers to be allocated 5229 if we did not need to use them in reloading other registers. */ 5230 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs)); 5231 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set); 5232 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set); 5233 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP); 5234 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP); 5235 5236 /* If this is a nested IF, we need to discover whether the CC registers that 5237 are set/used inside of the block are used anywhere else. If not, we can 5238 change them to be the CC register that is paired with the CR register that 5239 controls the outermost IF block. */ 5240 if (ce_info->pass > 1) 5241 { 5242 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite); 5243 for (j = CC_FIRST; j <= CC_LAST; j++) 5244 if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) 5245 { 5246 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j)) 5247 continue; 5248 5249 if (else_bb 5250 && REGNO_REG_SET_P (df_get_live_in (else_bb), j)) 5251 continue; 5252 5253 if (join_bb 5254 && REGNO_REG_SET_P (df_get_live_in (join_bb), j)) 5255 continue; 5256 5257 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j); 5258 } 5259 } 5260 5261 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++) 5262 frv_ifcvt.scratch_regs[j] = NULL_RTX; 5263 5264 frv_ifcvt.added_insns_list = NULL_RTX; 5265 frv_ifcvt.cur_scratch_regs = 0; 5266 5267 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks) 5268 * sizeof (basic_block)); 5269 5270 if (join_bb) 5271 { 5272 unsigned int regno; 5273 5274 /* Remove anything live at the beginning of the join block from being 5275 available for allocation. */ 5276 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi) 5277 { 5278 if (regno < FIRST_PSEUDO_REGISTER) 5279 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); 5280 } 5281 } 5282 5283 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */ 5284 num_bb = 0; 5285 if (ce_info->num_multiple_test_blocks) 5286 { 5287 basic_block multiple_test_bb = ce_info->last_test_bb; 5288 5289 while (multiple_test_bb != test_bb) 5290 { 5291 bb[num_bb++] = multiple_test_bb; 5292 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src; 5293 } 5294 } 5295 5296 /* Add in the THEN and ELSE blocks to be scanned. */ 5297 bb[num_bb++] = then_bb; 5298 if (else_bb) 5299 bb[num_bb++] = else_bb; 5300 5301 sub_cond_exec_reg = NULL_RTX; 5302 frv_ifcvt.num_nested_cond_exec = 0; 5303 5304 /* Scan all of the blocks for registers that must not be allocated. */ 5305 for (j = 0; j < num_bb; j++) 5306 { 5307 rtx_insn *last_insn = BB_END (bb[j]); 5308 rtx_insn *insn = BB_HEAD (bb[j]); 5309 unsigned int regno; 5310 5311 if (dump_file) 5312 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n", 5313 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"), 5314 (int) bb[j]->index, 5315 (int) INSN_UID (BB_HEAD (bb[j])), 5316 (int) INSN_UID (BB_END (bb[j]))); 5317 5318 /* Anything live at the beginning of the block is obviously unavailable 5319 for allocation. */ 5320 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi) 5321 { 5322 if (regno < FIRST_PSEUDO_REGISTER) 5323 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); 5324 } 5325 5326 /* Loop through the insns in the block. */ 5327 for (;;) 5328 { 5329 /* Mark any new registers that are created as being unavailable for 5330 allocation. Also see if the CC register used in nested IFs can be 5331 reallocated. */ 5332 if (INSN_P (insn)) 5333 { 5334 rtx pattern; 5335 rtx set; 5336 int skip_nested_if = FALSE; 5337 HARD_REG_SET mentioned_regs; 5338 5339 CLEAR_HARD_REG_SET (mentioned_regs); 5340 find_all_hard_regs (PATTERN (insn), &mentioned_regs); 5341 AND_COMPL_HARD_REG_SET (tmp_reg->regs, mentioned_regs); 5342 5343 pattern = PATTERN (insn); 5344 if (GET_CODE (pattern) == COND_EXEC) 5345 { 5346 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0); 5347 5348 if (reg != sub_cond_exec_reg) 5349 { 5350 sub_cond_exec_reg = reg; 5351 frv_ifcvt.num_nested_cond_exec++; 5352 } 5353 } 5354 5355 set = single_set_pattern (pattern); 5356 if (set) 5357 { 5358 rtx dest = SET_DEST (set); 5359 rtx src = SET_SRC (set); 5360 5361 if (GET_CODE (dest) == REG) 5362 { 5363 int regno = REGNO (dest); 5364 enum rtx_code src_code = GET_CODE (src); 5365 5366 if (CC_P (regno) && src_code == COMPARE) 5367 skip_nested_if = TRUE; 5368 5369 else if (CR_P (regno) 5370 && (src_code == IF_THEN_ELSE 5371 || COMPARISON_P (src))) 5372 skip_nested_if = TRUE; 5373 } 5374 } 5375 5376 if (! skip_nested_if) 5377 AND_COMPL_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite, 5378 mentioned_regs); 5379 } 5380 5381 if (insn == last_insn) 5382 break; 5383 5384 insn = NEXT_INSN (insn); 5385 } 5386 } 5387 5388 /* If this is a nested if, rewrite the CC registers that are available to 5389 include the ones that can be rewritten, to increase the chance of being 5390 able to allocate a paired CC/CR register combination. */ 5391 if (ce_info->pass > 1) 5392 { 5393 for (j = CC_FIRST; j <= CC_LAST; j++) 5394 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j)) 5395 SET_HARD_REG_BIT (tmp_reg->regs, j); 5396 else 5397 CLEAR_HARD_REG_BIT (tmp_reg->regs, j); 5398 } 5399 5400 if (dump_file) 5401 { 5402 int num_gprs = 0; 5403 fprintf (dump_file, "Available GPRs: "); 5404 5405 for (j = GPR_FIRST; j <= GPR_LAST; j++) 5406 if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) 5407 { 5408 fprintf (dump_file, " %d [%s]", j, reg_names[j]); 5409 if (++num_gprs > GPR_TEMP_NUM+2) 5410 break; 5411 } 5412 5413 fprintf (dump_file, "%s\nAvailable CRs: ", 5414 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : ""); 5415 5416 for (j = CR_FIRST; j <= CR_LAST; j++) 5417 if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) 5418 fprintf (dump_file, " %d [%s]", j, reg_names[j]); 5419 5420 fputs ("\n", dump_file); 5421 5422 if (ce_info->pass > 1) 5423 { 5424 fprintf (dump_file, "Modifiable CCs: "); 5425 for (j = CC_FIRST; j <= CC_LAST; j++) 5426 if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) 5427 fprintf (dump_file, " %d [%s]", j, reg_names[j]); 5428 5429 fprintf (dump_file, "\n%d nested COND_EXEC statements\n", 5430 frv_ifcvt.num_nested_cond_exec); 5431 } 5432 } 5433 5434 /* Allocate the appropriate temporary condition code register. Try to 5435 allocate the ICR/FCR register that corresponds to the ICC/FCC register so 5436 that conditional cmp's can be done. */ 5437 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) 5438 { 5439 cr_class = ICR_REGS; 5440 cc_class = ICC_REGS; 5441 cc_first = ICC_FIRST; 5442 cc_last = ICC_LAST; 5443 } 5444 else if (mode == CC_FPmode) 5445 { 5446 cr_class = FCR_REGS; 5447 cc_class = FCC_REGS; 5448 cc_first = FCC_FIRST; 5449 cc_last = FCC_LAST; 5450 } 5451 else 5452 { 5453 cc_first = cc_last = 0; 5454 cr_class = cc_class = NO_REGS; 5455 } 5456 5457 cc = XEXP (true_expr, 0); 5458 nested_cc = cr = NULL_RTX; 5459 if (cc_class != NO_REGS) 5460 { 5461 /* For nested IFs and &&/||, see if we can find a CC and CR register pair 5462 so we can execute a csubcc/caddcc/cfcmps instruction. */ 5463 int cc_regno; 5464 5465 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++) 5466 { 5467 int cr_regno = cc_regno - CC_FIRST + CR_FIRST; 5468 5469 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno) 5470 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno)) 5471 { 5472 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno; 5473 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE, 5474 TRUE); 5475 5476 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno; 5477 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode, 5478 TRUE, TRUE); 5479 break; 5480 } 5481 } 5482 } 5483 5484 if (! cr) 5485 { 5486 if (dump_file) 5487 fprintf (dump_file, "Could not allocate a CR temporary register\n"); 5488 5489 goto fail; 5490 } 5491 5492 if (dump_file) 5493 fprintf (dump_file, 5494 "Will use %s for conditional execution, %s for nested comparisons\n", 5495 reg_names[ REGNO (cr)], 5496 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>"); 5497 5498 /* Set the CCR bit. Note for integer tests, we reverse the condition so that 5499 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR 5500 bit being true. We don't do this for floating point, because of NaNs. */ 5501 code = GET_CODE (true_expr); 5502 if (GET_MODE (cc) != CC_FPmode) 5503 { 5504 code = reverse_condition (code); 5505 code_true = EQ; 5506 code_false = NE; 5507 } 5508 else 5509 { 5510 code_true = NE; 5511 code_false = EQ; 5512 } 5513 5514 check_insn = gen_rtx_SET (cr, gen_rtx_fmt_ee (code, CC_CCRmode, 5515 cc, const0_rtx)); 5516 5517 /* Record the check insn to be inserted later. */ 5518 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE); 5519 5520 /* Update the tests. */ 5521 frv_ifcvt.cr_reg = cr; 5522 frv_ifcvt.nested_cc_reg = nested_cc; 5523 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx); 5524 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx); 5525 return; 5526 5527 /* Fail, don't do this conditional execution. */ 5528 fail: 5529 *p_true = NULL_RTX; 5530 *p_false = NULL_RTX; 5531 if (dump_file) 5532 fprintf (dump_file, "Disabling this conditional execution.\n"); 5533 5534 return; 5535 } 5536 5537 5538 /* A C expression to modify the code described by the conditional if 5539 information CE_INFO, for the basic block BB, possibly updating the tests in 5540 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or 5541 if-then-else code to conditional instructions. Set either TRUE_EXPR or 5542 FALSE_EXPR to a null pointer if the tests cannot be converted. */ 5543 5544 /* p_true and p_false are given expressions of the form: 5545 5546 (and (eq:CC_CCR (reg:CC_CCR) 5547 (const_int 0)) 5548 (eq:CC (reg:CC) 5549 (const_int 0))) */ 5550 5551 void 5552 frv_ifcvt_modify_multiple_tests (ce_if_block *ce_info, 5553 basic_block bb, 5554 rtx *p_true, 5555 rtx *p_false) 5556 { 5557 rtx old_true = XEXP (*p_true, 0); 5558 rtx old_false = XEXP (*p_false, 0); 5559 rtx true_expr = XEXP (*p_true, 1); 5560 rtx false_expr = XEXP (*p_false, 1); 5561 rtx test_expr; 5562 rtx old_test; 5563 rtx cr = XEXP (old_true, 0); 5564 rtx check_insn; 5565 rtx new_cr = NULL_RTX; 5566 rtx *p_new_cr = (rtx *)0; 5567 rtx if_else; 5568 rtx compare; 5569 rtx cc; 5570 enum reg_class cr_class; 5571 machine_mode mode = GET_MODE (true_expr); 5572 rtx (*logical_func)(rtx, rtx, rtx); 5573 5574 if (TARGET_DEBUG_COND_EXEC) 5575 { 5576 fprintf (stderr, 5577 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n", 5578 ce_info->and_and_p ? "&&" : "||"); 5579 5580 debug_rtx (*p_true); 5581 5582 fputs ("\nfalse insn:\n", stderr); 5583 debug_rtx (*p_false); 5584 } 5585 5586 if (!TARGET_MULTI_CE) 5587 goto fail; 5588 5589 if (GET_CODE (cr) != REG) 5590 goto fail; 5591 5592 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) 5593 { 5594 cr_class = ICR_REGS; 5595 p_new_cr = &frv_ifcvt.extra_int_cr; 5596 } 5597 else if (mode == CC_FPmode) 5598 { 5599 cr_class = FCR_REGS; 5600 p_new_cr = &frv_ifcvt.extra_fp_cr; 5601 } 5602 else 5603 goto fail; 5604 5605 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or 5606 more &&/|| tests. */ 5607 new_cr = *p_new_cr; 5608 if (! new_cr) 5609 { 5610 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class, 5611 CC_CCRmode, TRUE, TRUE); 5612 if (! new_cr) 5613 goto fail; 5614 } 5615 5616 if (ce_info->and_and_p) 5617 { 5618 old_test = old_false; 5619 test_expr = true_expr; 5620 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr; 5621 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); 5622 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); 5623 } 5624 else 5625 { 5626 old_test = old_false; 5627 test_expr = false_expr; 5628 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr; 5629 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); 5630 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); 5631 } 5632 5633 /* First add the andcr/andncr/orcr/orncr, which will be added after the 5634 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO 5635 stack. */ 5636 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE); 5637 5638 /* Now add the conditional check insn. */ 5639 cc = XEXP (test_expr, 0); 5640 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx); 5641 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx); 5642 5643 check_insn = gen_rtx_SET (new_cr, if_else); 5644 5645 /* Add the new check insn to the list of check insns that need to be 5646 inserted. */ 5647 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE); 5648 5649 if (TARGET_DEBUG_COND_EXEC) 5650 { 5651 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n", 5652 stderr); 5653 5654 debug_rtx (*p_true); 5655 5656 fputs ("\nfalse insn:\n", stderr); 5657 debug_rtx (*p_false); 5658 } 5659 5660 return; 5661 5662 fail: 5663 *p_true = *p_false = NULL_RTX; 5664 5665 /* If we allocated a CR register, release it. */ 5666 if (new_cr) 5667 { 5668 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr)); 5669 *p_new_cr = NULL_RTX; 5670 } 5671 5672 if (TARGET_DEBUG_COND_EXEC) 5673 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr); 5674 5675 return; 5676 } 5677 5678 5679 /* Return a register which will be loaded with a value if an IF block is 5680 converted to conditional execution. This is used to rewrite instructions 5681 that use constants to ones that just use registers. */ 5682 5683 static rtx 5684 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED) 5685 { 5686 int num_alloc = frv_ifcvt.cur_scratch_regs; 5687 int i; 5688 rtx reg; 5689 5690 /* We know gr0 == 0, so replace any errant uses. */ 5691 if (value == const0_rtx) 5692 return gen_rtx_REG (SImode, GPR_FIRST); 5693 5694 /* First search all registers currently loaded to see if we have an 5695 applicable constant. */ 5696 if (CONSTANT_P (value) 5697 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)) 5698 { 5699 for (i = 0; i < num_alloc; i++) 5700 { 5701 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value)) 5702 return SET_DEST (frv_ifcvt.scratch_regs[i]); 5703 } 5704 } 5705 5706 /* Have we exhausted the number of registers available? */ 5707 if (num_alloc >= GPR_TEMP_NUM) 5708 { 5709 if (dump_file) 5710 fprintf (dump_file, "Too many temporary registers allocated\n"); 5711 5712 return NULL_RTX; 5713 } 5714 5715 /* Allocate the new register. */ 5716 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE); 5717 if (! reg) 5718 { 5719 if (dump_file) 5720 fputs ("Could not find a scratch register\n", dump_file); 5721 5722 return NULL_RTX; 5723 } 5724 5725 frv_ifcvt.cur_scratch_regs++; 5726 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (reg, value); 5727 5728 if (dump_file) 5729 { 5730 if (GET_CODE (value) == CONST_INT) 5731 fprintf (dump_file, "Register %s will hold %ld\n", 5732 reg_names[ REGNO (reg)], (long)INTVAL (value)); 5733 5734 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO) 5735 fprintf (dump_file, "Register %s will hold LR\n", 5736 reg_names[ REGNO (reg)]); 5737 5738 else 5739 fprintf (dump_file, "Register %s will hold a saved value\n", 5740 reg_names[ REGNO (reg)]); 5741 } 5742 5743 return reg; 5744 } 5745 5746 5747 /* Update a MEM used in conditional code that might contain an offset to put 5748 the offset into a scratch register, so that the conditional load/store 5749 operations can be used. This function returns the original pointer if the 5750 MEM is valid to use in conditional code, NULL if we can't load up the offset 5751 into a temporary register, or the new MEM if we were successful. */ 5752 5753 static rtx 5754 frv_ifcvt_rewrite_mem (rtx mem, machine_mode mode, rtx insn) 5755 { 5756 rtx addr = XEXP (mem, 0); 5757 5758 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE)) 5759 { 5760 if (GET_CODE (addr) == PLUS) 5761 { 5762 rtx addr_op0 = XEXP (addr, 0); 5763 rtx addr_op1 = XEXP (addr, 1); 5764 5765 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1)) 5766 { 5767 rtx reg = frv_ifcvt_load_value (addr_op1, insn); 5768 if (!reg) 5769 return NULL_RTX; 5770 5771 addr = gen_rtx_PLUS (Pmode, addr_op0, reg); 5772 } 5773 5774 else 5775 return NULL_RTX; 5776 } 5777 5778 else if (CONSTANT_P (addr)) 5779 addr = frv_ifcvt_load_value (addr, insn); 5780 5781 else 5782 return NULL_RTX; 5783 5784 if (addr == NULL_RTX) 5785 return NULL_RTX; 5786 5787 else if (XEXP (mem, 0) != addr) 5788 return change_address (mem, mode, addr); 5789 } 5790 5791 return mem; 5792 } 5793 5794 5795 /* Given a PATTERN, return a SET expression if this PATTERN has only a single 5796 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */ 5797 5798 static rtx 5799 single_set_pattern (rtx pattern) 5800 { 5801 rtx set; 5802 int i; 5803 5804 if (GET_CODE (pattern) == COND_EXEC) 5805 pattern = COND_EXEC_CODE (pattern); 5806 5807 if (GET_CODE (pattern) == SET) 5808 return pattern; 5809 5810 else if (GET_CODE (pattern) == PARALLEL) 5811 { 5812 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++) 5813 { 5814 rtx sub = XVECEXP (pattern, 0, i); 5815 5816 switch (GET_CODE (sub)) 5817 { 5818 case USE: 5819 case CLOBBER: 5820 break; 5821 5822 case SET: 5823 if (set) 5824 return 0; 5825 else 5826 set = sub; 5827 break; 5828 5829 default: 5830 return 0; 5831 } 5832 } 5833 return set; 5834 } 5835 5836 return 0; 5837 } 5838 5839 5840 /* A C expression to modify the code described by the conditional if 5841 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null 5842 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that 5843 insn cannot be converted to be executed conditionally. */ 5844 5845 rtx 5846 frv_ifcvt_modify_insn (ce_if_block *ce_info, 5847 rtx pattern, 5848 rtx_insn *insn) 5849 { 5850 rtx orig_ce_pattern = pattern; 5851 rtx set; 5852 rtx op0; 5853 rtx op1; 5854 rtx test; 5855 5856 gcc_assert (GET_CODE (pattern) == COND_EXEC); 5857 5858 test = COND_EXEC_TEST (pattern); 5859 if (GET_CODE (test) == AND) 5860 { 5861 rtx cr = frv_ifcvt.cr_reg; 5862 rtx test_reg; 5863 5864 op0 = XEXP (test, 0); 5865 if (! rtx_equal_p (cr, XEXP (op0, 0))) 5866 goto fail; 5867 5868 op1 = XEXP (test, 1); 5869 test_reg = XEXP (op1, 0); 5870 if (GET_CODE (test_reg) != REG) 5871 goto fail; 5872 5873 /* Is this the first nested if block in this sequence? If so, generate 5874 an andcr or andncr. */ 5875 if (! frv_ifcvt.last_nested_if_cr) 5876 { 5877 rtx and_op; 5878 5879 frv_ifcvt.last_nested_if_cr = test_reg; 5880 if (GET_CODE (op0) == NE) 5881 and_op = gen_andcr (test_reg, cr, test_reg); 5882 else 5883 and_op = gen_andncr (test_reg, cr, test_reg); 5884 5885 frv_ifcvt_add_insn (and_op, insn, TRUE); 5886 } 5887 5888 /* If this isn't the first statement in the nested if sequence, see if we 5889 are dealing with the same register. */ 5890 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr)) 5891 goto fail; 5892 5893 COND_EXEC_TEST (pattern) = test = op1; 5894 } 5895 5896 /* If this isn't a nested if, reset state variables. */ 5897 else 5898 { 5899 frv_ifcvt.last_nested_if_cr = NULL_RTX; 5900 } 5901 5902 set = single_set_pattern (pattern); 5903 if (set) 5904 { 5905 rtx dest = SET_DEST (set); 5906 rtx src = SET_SRC (set); 5907 machine_mode mode = GET_MODE (dest); 5908 5909 /* Check for normal binary operators. */ 5910 if (mode == SImode && ARITHMETIC_P (src)) 5911 { 5912 op0 = XEXP (src, 0); 5913 op1 = XEXP (src, 1); 5914 5915 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1)) 5916 { 5917 op1 = frv_ifcvt_load_value (op1, insn); 5918 if (op1) 5919 COND_EXEC_CODE (pattern) 5920 = gen_rtx_SET (dest, gen_rtx_fmt_ee (GET_CODE (src), 5921 GET_MODE (src), 5922 op0, op1)); 5923 else 5924 goto fail; 5925 } 5926 } 5927 5928 /* For multiply by a constant, we need to handle the sign extending 5929 correctly. Add a USE of the value after the multiply to prevent flow 5930 from cratering because only one register out of the two were used. */ 5931 else if (mode == DImode && GET_CODE (src) == MULT) 5932 { 5933 op0 = XEXP (src, 0); 5934 op1 = XEXP (src, 1); 5935 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT) 5936 { 5937 op1 = frv_ifcvt_load_value (op1, insn); 5938 if (op1) 5939 { 5940 op1 = gen_rtx_SIGN_EXTEND (DImode, op1); 5941 COND_EXEC_CODE (pattern) 5942 = gen_rtx_SET (dest, gen_rtx_MULT (DImode, op0, op1)); 5943 } 5944 else 5945 goto fail; 5946 } 5947 5948 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE); 5949 } 5950 5951 /* If we are just loading a constant created for a nested conditional 5952 execution statement, just load the constant without any conditional 5953 execution, since we know that the constant will not interfere with any 5954 other registers. */ 5955 else if (frv_ifcvt.scratch_insns_bitmap 5956 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap, 5957 INSN_UID (insn)) 5958 && REG_P (SET_DEST (set)) 5959 /* We must not unconditionally set a scratch reg chosen 5960 for a nested if-converted block if its incoming 5961 value from the TEST block (or the result of the THEN 5962 branch) could/should propagate to the JOIN block. 5963 It suffices to test whether the register is live at 5964 the JOIN point: if it's live there, we can infer 5965 that we set it in the former JOIN block of the 5966 nested if-converted block (otherwise it wouldn't 5967 have been available as a scratch register), and it 5968 is either propagated through or set in the other 5969 conditional block. It's probably not worth trying 5970 to catch the latter case, and it could actually 5971 limit scheduling of the combined block quite 5972 severely. */ 5973 && ce_info->join_bb 5974 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb), 5975 REGNO (SET_DEST (set)))) 5976 /* Similarly, we must not unconditionally set a reg 5977 used as scratch in the THEN branch if the same reg 5978 is live in the ELSE branch. */ 5979 && (! ce_info->else_bb 5980 || BLOCK_FOR_INSN (insn) == ce_info->else_bb 5981 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb), 5982 REGNO (SET_DEST (set)))))) 5983 pattern = set; 5984 5985 else if (mode == QImode || mode == HImode || mode == SImode 5986 || mode == SFmode) 5987 { 5988 int changed_p = FALSE; 5989 5990 /* Check for just loading up a constant */ 5991 if (CONSTANT_P (src) && integer_register_operand (dest, mode)) 5992 { 5993 src = frv_ifcvt_load_value (src, insn); 5994 if (!src) 5995 goto fail; 5996 5997 changed_p = TRUE; 5998 } 5999 6000 /* See if we need to fix up stores */ 6001 if (GET_CODE (dest) == MEM) 6002 { 6003 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn); 6004 6005 if (!new_mem) 6006 goto fail; 6007 6008 else if (new_mem != dest) 6009 { 6010 changed_p = TRUE; 6011 dest = new_mem; 6012 } 6013 } 6014 6015 /* See if we need to fix up loads */ 6016 if (GET_CODE (src) == MEM) 6017 { 6018 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn); 6019 6020 if (!new_mem) 6021 goto fail; 6022 6023 else if (new_mem != src) 6024 { 6025 changed_p = TRUE; 6026 src = new_mem; 6027 } 6028 } 6029 6030 /* If either src or destination changed, redo SET. */ 6031 if (changed_p) 6032 COND_EXEC_CODE (pattern) = gen_rtx_SET (dest, src); 6033 } 6034 6035 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with 6036 rewriting the CC register to be the same as the paired CC/CR register 6037 for nested ifs. */ 6038 else if (mode == CC_CCRmode && COMPARISON_P (src)) 6039 { 6040 int regno = REGNO (XEXP (src, 0)); 6041 rtx if_else; 6042 6043 if (ce_info->pass > 1 6044 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg) 6045 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno)) 6046 { 6047 src = gen_rtx_fmt_ee (GET_CODE (src), 6048 CC_CCRmode, 6049 frv_ifcvt.nested_cc_reg, 6050 XEXP (src, 1)); 6051 } 6052 6053 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx); 6054 pattern = gen_rtx_SET (dest, if_else); 6055 } 6056 6057 /* Remap a nested compare instruction to use the paired CC/CR reg. */ 6058 else if (ce_info->pass > 1 6059 && GET_CODE (dest) == REG 6060 && CC_P (REGNO (dest)) 6061 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg) 6062 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, 6063 REGNO (dest)) 6064 && GET_CODE (src) == COMPARE) 6065 { 6066 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest)); 6067 COND_EXEC_CODE (pattern) 6068 = gen_rtx_SET (frv_ifcvt.nested_cc_reg, copy_rtx (src)); 6069 } 6070 } 6071 6072 if (TARGET_DEBUG_COND_EXEC) 6073 { 6074 rtx orig_pattern = PATTERN (insn); 6075 6076 PATTERN (insn) = pattern; 6077 fprintf (stderr, 6078 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n", 6079 ce_info->pass); 6080 6081 debug_rtx (insn); 6082 PATTERN (insn) = orig_pattern; 6083 } 6084 6085 return pattern; 6086 6087 fail: 6088 if (TARGET_DEBUG_COND_EXEC) 6089 { 6090 rtx orig_pattern = PATTERN (insn); 6091 6092 PATTERN (insn) = orig_ce_pattern; 6093 fprintf (stderr, 6094 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n", 6095 ce_info->pass); 6096 6097 debug_rtx (insn); 6098 PATTERN (insn) = orig_pattern; 6099 } 6100 6101 return NULL_RTX; 6102 } 6103 6104 6105 /* A C expression to perform any final machine dependent modifications in 6106 converting code to conditional execution in the code described by the 6107 conditional if information CE_INFO. */ 6108 6109 void 6110 frv_ifcvt_modify_final (ce_if_block *ce_info ATTRIBUTE_UNUSED) 6111 { 6112 rtx_insn *existing_insn; 6113 rtx check_insn; 6114 rtx p = frv_ifcvt.added_insns_list; 6115 int i; 6116 6117 /* Loop inserting the check insns. The last check insn is the first test, 6118 and is the appropriate place to insert constants. */ 6119 gcc_assert (p); 6120 6121 do 6122 { 6123 rtx check_and_insert_insns = XEXP (p, 0); 6124 rtx old_p = p; 6125 6126 check_insn = XEXP (check_and_insert_insns, 0); 6127 existing_insn = as_a <rtx_insn *> (XEXP (check_and_insert_insns, 1)); 6128 p = XEXP (p, 1); 6129 6130 /* The jump bit is used to say that the new insn is to be inserted BEFORE 6131 the existing insn, otherwise it is to be inserted AFTER. */ 6132 if (check_and_insert_insns->jump) 6133 { 6134 emit_insn_before (check_insn, existing_insn); 6135 check_and_insert_insns->jump = 0; 6136 } 6137 else 6138 emit_insn_after (check_insn, existing_insn); 6139 6140 free_EXPR_LIST_node (check_and_insert_insns); 6141 free_EXPR_LIST_node (old_p); 6142 } 6143 while (p != NULL_RTX); 6144 6145 /* Load up any constants needed into temp gprs */ 6146 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) 6147 { 6148 rtx_insn *insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn); 6149 if (! frv_ifcvt.scratch_insns_bitmap) 6150 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL); 6151 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn)); 6152 frv_ifcvt.scratch_regs[i] = NULL_RTX; 6153 } 6154 6155 frv_ifcvt.added_insns_list = NULL_RTX; 6156 frv_ifcvt.cur_scratch_regs = 0; 6157 } 6158 6159 6160 /* A C expression to cancel any machine dependent modifications in converting 6161 code to conditional execution in the code described by the conditional if 6162 information CE_INFO. */ 6163 6164 void 6165 frv_ifcvt_modify_cancel (ce_if_block *ce_info ATTRIBUTE_UNUSED) 6166 { 6167 int i; 6168 rtx p = frv_ifcvt.added_insns_list; 6169 6170 /* Loop freeing up the EXPR_LIST's allocated. */ 6171 while (p != NULL_RTX) 6172 { 6173 rtx check_and_jump = XEXP (p, 0); 6174 rtx old_p = p; 6175 6176 p = XEXP (p, 1); 6177 free_EXPR_LIST_node (check_and_jump); 6178 free_EXPR_LIST_node (old_p); 6179 } 6180 6181 /* Release any temporary gprs allocated. */ 6182 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) 6183 frv_ifcvt.scratch_regs[i] = NULL_RTX; 6184 6185 frv_ifcvt.added_insns_list = NULL_RTX; 6186 frv_ifcvt.cur_scratch_regs = 0; 6187 return; 6188 } 6189 6190 /* A C expression for the size in bytes of the trampoline, as an integer. 6191 The template is: 6192 6193 setlo #0, <jmp_reg> 6194 setlo #0, <static_chain> 6195 sethi #0, <jmp_reg> 6196 sethi #0, <static_chain> 6197 jmpl @(gr0,<jmp_reg>) */ 6198 6199 int 6200 frv_trampoline_size (void) 6201 { 6202 if (TARGET_FDPIC) 6203 /* Allocate room for the function descriptor and the lddi 6204 instruction. */ 6205 return 8 + 6 * 4; 6206 return 5 /* instructions */ * 4 /* instruction size. */; 6207 } 6208 6209 6210 /* A C statement to initialize the variable parts of a trampoline. ADDR is an 6211 RTX for the address of the trampoline; FNADDR is an RTX for the address of 6212 the nested function; STATIC_CHAIN is an RTX for the static chain value that 6213 should be passed to the function when it is called. 6214 6215 The template is: 6216 6217 setlo #0, <jmp_reg> 6218 setlo #0, <static_chain> 6219 sethi #0, <jmp_reg> 6220 sethi #0, <static_chain> 6221 jmpl @(gr0,<jmp_reg>) */ 6222 6223 static void 6224 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) 6225 { 6226 rtx addr = XEXP (m_tramp, 0); 6227 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 6228 rtx sc_reg = force_reg (Pmode, static_chain); 6229 6230 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), 6231 LCT_NORMAL, VOIDmode, 6232 addr, Pmode, 6233 GEN_INT (frv_trampoline_size ()), SImode, 6234 fnaddr, Pmode, 6235 sc_reg, Pmode); 6236 } 6237 6238 6239 /* Many machines have some registers that cannot be copied directly to or from 6240 memory or even from other types of registers. An example is the `MQ' 6241 register, which on most machines, can only be copied to or from general 6242 registers, but not memory. Some machines allow copying all registers to and 6243 from memory, but require a scratch register for stores to some memory 6244 locations (e.g., those with symbolic address on the RT, and those with 6245 certain symbolic address on the SPARC when compiling PIC). In some cases, 6246 both an intermediate and a scratch register are required. 6247 6248 You should define these macros to indicate to the reload phase that it may 6249 need to allocate at least one register for a reload in addition to the 6250 register to contain the data. Specifically, if copying X to a register 6251 RCLASS in MODE requires an intermediate register, you should define 6252 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of 6253 whose registers can be used as intermediate registers or scratch registers. 6254 6255 If copying a register RCLASS in MODE to X requires an intermediate or scratch 6256 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the 6257 largest register class required. If the requirements for input and output 6258 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used 6259 instead of defining both macros identically. 6260 6261 The values returned by these macros are often `GENERAL_REGS'. Return 6262 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied 6263 to or from a register of RCLASS in MODE without requiring a scratch register. 6264 Do not define this macro if it would always return `NO_REGS'. 6265 6266 If a scratch register is required (either with or without an intermediate 6267 register), you should define patterns for `reload_inM' or `reload_outM', as 6268 required.. These patterns, which will normally be implemented with a 6269 `define_expand', should be similar to the `movM' patterns, except that 6270 operand 2 is the scratch register. 6271 6272 Define constraints for the reload register and scratch register that contain 6273 a single register class. If the original reload register (whose class is 6274 RCLASS) can meet the constraint given in the pattern, the value returned by 6275 these macros is used for the class of the scratch register. Otherwise, two 6276 additional reload registers are required. Their classes are obtained from 6277 the constraints in the insn pattern. 6278 6279 X might be a pseudo-register or a `subreg' of a pseudo-register, which could 6280 either be in a hard register or in memory. Use `true_regnum' to find out; 6281 it will return -1 if the pseudo is in memory and the hard register number if 6282 it is in a register. 6283 6284 These macros should not be used in the case where a particular class of 6285 registers can only be copied to memory and not to another class of 6286 registers. In that case, secondary reload registers are not needed and 6287 would not be helpful. Instead, a stack location must be used to perform the 6288 copy and the `movM' pattern should use memory as an intermediate storage. 6289 This case often occurs between floating-point and general registers. */ 6290 6291 enum reg_class 6292 frv_secondary_reload_class (enum reg_class rclass, 6293 machine_mode mode ATTRIBUTE_UNUSED, 6294 rtx x) 6295 { 6296 enum reg_class ret; 6297 6298 switch (rclass) 6299 { 6300 default: 6301 ret = NO_REGS; 6302 break; 6303 6304 /* Accumulators/Accumulator guard registers need to go through floating 6305 point registers. */ 6306 case QUAD_REGS: 6307 case GPR_REGS: 6308 ret = NO_REGS; 6309 if (x && GET_CODE (x) == REG) 6310 { 6311 int regno = REGNO (x); 6312 6313 if (ACC_P (regno) || ACCG_P (regno)) 6314 ret = FPR_REGS; 6315 } 6316 break; 6317 6318 /* Nonzero constants should be loaded into an FPR through a GPR. */ 6319 case QUAD_FPR_REGS: 6320 if (x && CONSTANT_P (x) && !ZERO_P (x)) 6321 ret = GPR_REGS; 6322 else 6323 ret = NO_REGS; 6324 break; 6325 6326 /* All of these types need gpr registers. */ 6327 case ICC_REGS: 6328 case FCC_REGS: 6329 case CC_REGS: 6330 case ICR_REGS: 6331 case FCR_REGS: 6332 case CR_REGS: 6333 case LCR_REG: 6334 case LR_REG: 6335 ret = GPR_REGS; 6336 break; 6337 6338 /* The accumulators need fpr registers. */ 6339 case QUAD_ACC_REGS: 6340 case ACCG_REGS: 6341 ret = FPR_REGS; 6342 break; 6343 } 6344 6345 return ret; 6346 } 6347 6348 /* This hook exists to catch the case where secondary_reload_class() is 6349 called from init_reg_autoinc() in regclass.c - before the reload optabs 6350 have been initialised. */ 6351 6352 static reg_class_t 6353 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i, 6354 machine_mode reload_mode, 6355 secondary_reload_info * sri) 6356 { 6357 enum reg_class rclass = NO_REGS; 6358 enum reg_class reload_class = (enum reg_class) reload_class_i; 6359 6360 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing) 6361 { 6362 sri->icode = sri->prev_sri->t_icode; 6363 return NO_REGS; 6364 } 6365 6366 rclass = frv_secondary_reload_class (reload_class, reload_mode, x); 6367 6368 if (rclass != NO_REGS) 6369 { 6370 enum insn_code icode 6371 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab, 6372 reload_mode); 6373 if (icode == 0) 6374 { 6375 /* This happens when then the reload_[in|out]_optabs have 6376 not been initialised. */ 6377 sri->t_icode = CODE_FOR_nothing; 6378 return rclass; 6379 } 6380 } 6381 6382 /* Fall back to the default secondary reload handler. */ 6383 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri); 6384 6385 } 6386 6387 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */ 6388 6389 static bool 6390 frv_class_likely_spilled_p (reg_class_t rclass) 6391 { 6392 switch (rclass) 6393 { 6394 default: 6395 break; 6396 6397 case GR8_REGS: 6398 case GR9_REGS: 6399 case GR89_REGS: 6400 case FDPIC_FPTR_REGS: 6401 case FDPIC_REGS: 6402 case ICC_REGS: 6403 case FCC_REGS: 6404 case CC_REGS: 6405 case ICR_REGS: 6406 case FCR_REGS: 6407 case CR_REGS: 6408 case LCR_REG: 6409 case LR_REG: 6410 case SPR_REGS: 6411 case QUAD_ACC_REGS: 6412 case ACCG_REGS: 6413 return true; 6414 } 6415 6416 return false; 6417 } 6418 6419 6420 /* An expression for the alignment of a structure field FIELD if the 6421 alignment computed in the usual way is COMPUTED. GCC uses this 6422 value instead of the value in `BIGGEST_ALIGNMENT' or 6423 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ 6424 6425 /* The definition type of the bit field data is either char, short, long or 6426 long long. The maximum bit size is the number of bits of its own type. 6427 6428 The bit field data is assigned to a storage unit that has an adequate size 6429 for bit field data retention and is located at the smallest address. 6430 6431 Consecutive bit field data are packed at consecutive bits having the same 6432 storage unit, with regard to the type, beginning with the MSB and continuing 6433 toward the LSB. 6434 6435 If a field to be assigned lies over a bit field type boundary, its 6436 assignment is completed by aligning it with a boundary suitable for the 6437 type. 6438 6439 When a bit field having a bit length of 0 is declared, it is forcibly 6440 assigned to the next storage unit. 6441 6442 e.g) 6443 struct { 6444 int a:2; 6445 int b:6; 6446 char c:4; 6447 int d:10; 6448 int :0; 6449 int f:2; 6450 } x; 6451 6452 +0 +1 +2 +3 6453 &x 00000000 00000000 00000000 00000000 6454 MLM----L 6455 a b 6456 &x+4 00000000 00000000 00000000 00000000 6457 M--L 6458 c 6459 &x+8 00000000 00000000 00000000 00000000 6460 M----------L 6461 d 6462 &x+12 00000000 00000000 00000000 00000000 6463 ML 6464 f 6465 */ 6466 6467 int 6468 frv_adjust_field_align (tree field, int computed) 6469 { 6470 /* Make sure that the bitfield is not wider than the type. */ 6471 if (field 6472 && DECL_BIT_FIELD (field) 6473 && !DECL_ARTIFICIAL (field)) 6474 { 6475 tree parent = DECL_CONTEXT (field); 6476 tree prev = NULL_TREE; 6477 tree cur; 6478 6479 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur)) 6480 { 6481 if (TREE_CODE (cur) != FIELD_DECL) 6482 continue; 6483 6484 prev = cur; 6485 } 6486 6487 gcc_assert (cur); 6488 6489 /* If this isn't a :0 field and if the previous element is a bitfield 6490 also, see if the type is different, if so, we will need to align the 6491 bit-field to the next boundary. */ 6492 if (prev 6493 && ! DECL_PACKED (field) 6494 && ! integer_zerop (DECL_SIZE (field)) 6495 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev)) 6496 { 6497 int prev_align = TYPE_ALIGN (TREE_TYPE (prev)); 6498 int cur_align = TYPE_ALIGN (TREE_TYPE (field)); 6499 computed = (prev_align > cur_align) ? prev_align : cur_align; 6500 } 6501 } 6502 6503 return computed; 6504 } 6505 6506 6507 /* Implement TARGET_HARD_REGNO_MODE_OK. */ 6508 6509 static bool 6510 frv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 6511 { 6512 int base; 6513 int mask; 6514 6515 switch (mode) 6516 { 6517 case E_CCmode: 6518 case E_CC_UNSmode: 6519 case E_CC_NZmode: 6520 return ICC_P (regno) || GPR_P (regno); 6521 6522 case E_CC_CCRmode: 6523 return CR_P (regno) || GPR_P (regno); 6524 6525 case E_CC_FPmode: 6526 return FCC_P (regno) || GPR_P (regno); 6527 6528 default: 6529 break; 6530 } 6531 6532 /* Set BASE to the first register in REGNO's class. Set MASK to the 6533 bits that must be clear in (REGNO - BASE) for the register to be 6534 well-aligned. */ 6535 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)) 6536 { 6537 if (ACCG_P (regno)) 6538 { 6539 /* ACCGs store one byte. Two-byte quantities must start in 6540 even-numbered registers, four-byte ones in registers whose 6541 numbers are divisible by four, and so on. */ 6542 base = ACCG_FIRST; 6543 mask = GET_MODE_SIZE (mode) - 1; 6544 } 6545 else 6546 { 6547 /* The other registers store one word. */ 6548 if (GPR_P (regno) || regno == AP_FIRST) 6549 base = GPR_FIRST; 6550 6551 else if (FPR_P (regno)) 6552 base = FPR_FIRST; 6553 6554 else if (ACC_P (regno)) 6555 base = ACC_FIRST; 6556 6557 else if (SPR_P (regno)) 6558 return mode == SImode; 6559 6560 /* Fill in the table. */ 6561 else 6562 return false; 6563 6564 /* Anything smaller than an SI is OK in any word-sized register. */ 6565 if (GET_MODE_SIZE (mode) < 4) 6566 return true; 6567 6568 mask = (GET_MODE_SIZE (mode) / 4) - 1; 6569 } 6570 return (((regno - base) & mask) == 0); 6571 } 6572 6573 return false; 6574 } 6575 6576 /* Implement TARGET_MODES_TIEABLE_P. */ 6577 6578 static bool 6579 frv_modes_tieable_p (machine_mode mode1, machine_mode mode2) 6580 { 6581 return mode1 == mode2; 6582 } 6583 6584 6585 /* Implement TARGET_HARD_REGNO_NREGS. 6586 6587 On the FRV, make the CC_FP mode take 3 words in the integer registers, so 6588 that we can build the appropriate instructions to properly reload the 6589 values. Also, make the byte-sized accumulator guards use one guard 6590 for each byte. */ 6591 6592 static unsigned int 6593 frv_hard_regno_nregs (unsigned int regno, machine_mode mode) 6594 { 6595 if (ACCG_P (regno)) 6596 return GET_MODE_SIZE (mode); 6597 else 6598 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 6599 } 6600 6601 6602 /* Implement CLASS_MAX_NREGS. */ 6603 6604 int 6605 frv_class_max_nregs (enum reg_class rclass, machine_mode mode) 6606 { 6607 if (rclass == ACCG_REGS) 6608 /* An N-byte value requires N accumulator guards. */ 6609 return GET_MODE_SIZE (mode); 6610 else 6611 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 6612 } 6613 6614 6615 /* A C expression that is nonzero if X is a legitimate constant for an 6616 immediate operand on the target machine. You can assume that X satisfies 6617 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable 6618 definition for this macro on machines where anything `CONSTANT_P' is valid. */ 6619 6620 static bool 6621 frv_legitimate_constant_p (machine_mode mode, rtx x) 6622 { 6623 /* frv_cannot_force_const_mem always returns true for FDPIC. This 6624 means that the move expanders will be expected to deal with most 6625 kinds of constant, regardless of what we return here. 6626 6627 However, among its other duties, frv_legitimate_constant_p decides whether 6628 a constant can be entered into reg_equiv_constant[]. If we return true, 6629 reload can create new instances of the constant whenever it likes. 6630 6631 The idea is therefore to accept as many constants as possible (to give 6632 reload more freedom) while rejecting constants that can only be created 6633 at certain times. In particular, anything with a symbolic component will 6634 require use of the pseudo FDPIC register, which is only available before 6635 reload. */ 6636 if (TARGET_FDPIC) 6637 return LEGITIMATE_PIC_OPERAND_P (x); 6638 6639 /* All of the integer constants are ok. */ 6640 if (GET_CODE (x) != CONST_DOUBLE) 6641 return TRUE; 6642 6643 /* double integer constants are ok. */ 6644 if (GET_MODE (x) == VOIDmode || mode == DImode) 6645 return TRUE; 6646 6647 /* 0 is always ok. */ 6648 if (x == CONST0_RTX (mode)) 6649 return TRUE; 6650 6651 /* If floating point is just emulated, allow any constant, since it will be 6652 constructed in the GPRs. */ 6653 if (!TARGET_HAS_FPRS) 6654 return TRUE; 6655 6656 if (mode == DFmode && !TARGET_DOUBLE) 6657 return TRUE; 6658 6659 /* Otherwise store the constant away and do a load. */ 6660 return FALSE; 6661 } 6662 6663 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons, 6664 CC_NZ for comparisons against zero in which a single Z or N flag test 6665 is enough, CC_UNS for other unsigned comparisons, and CC for other 6666 signed comparisons. */ 6667 6668 machine_mode 6669 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y) 6670 { 6671 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 6672 return CC_FPmode; 6673 6674 switch (code) 6675 { 6676 case EQ: 6677 case NE: 6678 case LT: 6679 case GE: 6680 return y == const0_rtx ? CC_NZmode : CCmode; 6681 6682 case GTU: 6683 case GEU: 6684 case LTU: 6685 case LEU: 6686 return y == const0_rtx ? CC_NZmode : CC_UNSmode; 6687 6688 default: 6689 return CCmode; 6690 } 6691 } 6692 6693 6694 /* Worker function for TARGET_REGISTER_MOVE_COST. */ 6695 6696 #define HIGH_COST 40 6697 #define MEDIUM_COST 3 6698 #define LOW_COST 1 6699 6700 static int 6701 frv_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 6702 reg_class_t from, reg_class_t to) 6703 { 6704 switch (from) 6705 { 6706 default: 6707 break; 6708 6709 case QUAD_REGS: 6710 case GPR_REGS: 6711 case GR8_REGS: 6712 case GR9_REGS: 6713 case GR89_REGS: 6714 case FDPIC_REGS: 6715 case FDPIC_FPTR_REGS: 6716 case FDPIC_CALL_REGS: 6717 6718 switch (to) 6719 { 6720 default: 6721 break; 6722 6723 case QUAD_REGS: 6724 case GPR_REGS: 6725 case GR8_REGS: 6726 case GR9_REGS: 6727 case GR89_REGS: 6728 case FDPIC_REGS: 6729 case FDPIC_FPTR_REGS: 6730 case FDPIC_CALL_REGS: 6731 6732 return LOW_COST; 6733 6734 case FPR_REGS: 6735 return LOW_COST; 6736 6737 case LCR_REG: 6738 case LR_REG: 6739 case SPR_REGS: 6740 return LOW_COST; 6741 } 6742 6743 case QUAD_FPR_REGS: 6744 switch (to) 6745 { 6746 default: 6747 break; 6748 6749 case QUAD_REGS: 6750 case GPR_REGS: 6751 case GR8_REGS: 6752 case GR9_REGS: 6753 case GR89_REGS: 6754 case FDPIC_REGS: 6755 case FDPIC_FPTR_REGS: 6756 case FDPIC_CALL_REGS: 6757 6758 case QUAD_ACC_REGS: 6759 case ACCG_REGS: 6760 return MEDIUM_COST; 6761 6762 case QUAD_FPR_REGS: 6763 return LOW_COST; 6764 } 6765 6766 case LCR_REG: 6767 case LR_REG: 6768 case SPR_REGS: 6769 switch (to) 6770 { 6771 default: 6772 break; 6773 6774 case QUAD_REGS: 6775 case GPR_REGS: 6776 case GR8_REGS: 6777 case GR9_REGS: 6778 case GR89_REGS: 6779 case FDPIC_REGS: 6780 case FDPIC_FPTR_REGS: 6781 case FDPIC_CALL_REGS: 6782 6783 return MEDIUM_COST; 6784 } 6785 6786 case QUAD_ACC_REGS: 6787 case ACCG_REGS: 6788 switch (to) 6789 { 6790 default: 6791 break; 6792 6793 case QUAD_FPR_REGS: 6794 return MEDIUM_COST; 6795 6796 } 6797 } 6798 6799 return HIGH_COST; 6800 } 6801 6802 /* Worker function for TARGET_MEMORY_MOVE_COST. */ 6803 6804 static int 6805 frv_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 6806 reg_class_t rclass ATTRIBUTE_UNUSED, 6807 bool in ATTRIBUTE_UNUSED) 6808 { 6809 return 4; 6810 } 6811 6812 6813 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to 6814 use ".picptr" to generate safe relocations for PIC code. We also 6815 need a fixup entry for aligned (non-debugging) code. */ 6816 6817 static bool 6818 frv_assemble_integer (rtx value, unsigned int size, int aligned_p) 6819 { 6820 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD) 6821 { 6822 if (GET_CODE (value) == CONST 6823 || GET_CODE (value) == SYMBOL_REF 6824 || GET_CODE (value) == LABEL_REF) 6825 { 6826 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF 6827 && SYMBOL_REF_FUNCTION_P (value)) 6828 { 6829 fputs ("\t.picptr\tfuncdesc(", asm_out_file); 6830 output_addr_const (asm_out_file, value); 6831 fputs (")\n", asm_out_file); 6832 return true; 6833 } 6834 else if (TARGET_FDPIC && GET_CODE (value) == CONST 6835 && frv_function_symbol_referenced_p (value)) 6836 return false; 6837 if (aligned_p && !TARGET_FDPIC) 6838 { 6839 static int label_num = 0; 6840 char buf[256]; 6841 const char *p; 6842 6843 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++); 6844 p = (* targetm.strip_name_encoding) (buf); 6845 6846 fprintf (asm_out_file, "%s:\n", p); 6847 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP); 6848 fprintf (asm_out_file, "\t.picptr\t%s\n", p); 6849 fprintf (asm_out_file, "\t.previous\n"); 6850 } 6851 assemble_integer_with_op ("\t.picptr\t", value); 6852 return true; 6853 } 6854 if (!aligned_p) 6855 { 6856 /* We've set the unaligned SI op to NULL, so we always have to 6857 handle the unaligned case here. */ 6858 assemble_integer_with_op ("\t.4byte\t", value); 6859 return true; 6860 } 6861 } 6862 return default_assemble_integer (value, size, aligned_p); 6863 } 6864 6865 /* Function to set up the backend function structure. */ 6866 6867 static struct machine_function * 6868 frv_init_machine_status (void) 6869 { 6870 return ggc_cleared_alloc<machine_function> (); 6871 } 6872 6873 /* Implement TARGET_SCHED_ISSUE_RATE. */ 6874 6875 int 6876 frv_issue_rate (void) 6877 { 6878 if (!TARGET_PACK) 6879 return 1; 6880 6881 switch (frv_cpu_type) 6882 { 6883 default: 6884 case FRV_CPU_FR300: 6885 case FRV_CPU_SIMPLE: 6886 return 1; 6887 6888 case FRV_CPU_FR400: 6889 case FRV_CPU_FR405: 6890 case FRV_CPU_FR450: 6891 return 2; 6892 6893 case FRV_CPU_GENERIC: 6894 case FRV_CPU_FR500: 6895 case FRV_CPU_TOMCAT: 6896 return 4; 6897 6898 case FRV_CPU_FR550: 6899 return 8; 6900 } 6901 } 6902 6903 /* Return the value of INSN's acc_group attribute. */ 6904 6905 int 6906 frv_acc_group (rtx insn) 6907 { 6908 /* This distinction only applies to the FR550 packing constraints. */ 6909 if (frv_cpu_type == FRV_CPU_FR550) 6910 { 6911 subrtx_iterator::array_type array; 6912 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) 6913 if (REG_P (*iter)) 6914 { 6915 unsigned int regno = REGNO (*iter); 6916 /* If REGNO refers to an accumulator, return ACC_GROUP_ODD if 6917 the bit 2 of the register number is set and ACC_GROUP_EVEN if 6918 it is clear. */ 6919 if (ACC_P (regno)) 6920 return (regno - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; 6921 if (ACCG_P (regno)) 6922 return (regno - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; 6923 } 6924 } 6925 return ACC_GROUP_NONE; 6926 } 6927 6928 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction 6929 INSN will try to claim first. Since this value depends only on the 6930 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */ 6931 6932 static unsigned int 6933 frv_insn_unit (rtx_insn *insn) 6934 { 6935 enum attr_type type; 6936 6937 type = get_attr_type (insn); 6938 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes)) 6939 { 6940 /* We haven't seen this type of instruction before. */ 6941 state_t state; 6942 unsigned int unit; 6943 6944 /* Issue the instruction on its own to see which unit it prefers. */ 6945 state = alloca (state_size ()); 6946 state_reset (state); 6947 state_transition (state, insn); 6948 6949 /* Find out which unit was taken. */ 6950 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++) 6951 if (cpu_unit_reservation_p (state, frv_unit_codes[unit])) 6952 break; 6953 6954 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes)); 6955 6956 frv_type_to_unit[type] = unit; 6957 } 6958 return frv_type_to_unit[type]; 6959 } 6960 6961 /* Return true if INSN issues to a branch unit. */ 6962 6963 static bool 6964 frv_issues_to_branch_unit_p (rtx_insn *insn) 6965 { 6966 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B; 6967 } 6968 6969 /* The instructions in the packet, partitioned into groups. */ 6970 struct frv_packet_group { 6971 /* How many instructions in the packet belong to this group. */ 6972 unsigned int num_insns; 6973 6974 /* A list of the instructions that belong to this group, in the order 6975 they appear in the rtl stream. */ 6976 rtx_insn *insns[ARRAY_SIZE (frv_unit_codes)]; 6977 6978 /* The contents of INSNS after they have been sorted into the correct 6979 assembly-language order. Element X issues to unit X. The list may 6980 contain extra nops. */ 6981 rtx_insn *sorted[ARRAY_SIZE (frv_unit_codes)]; 6982 6983 /* The member of frv_nops[] to use in sorted[]. */ 6984 rtx_insn *nop; 6985 }; 6986 6987 /* The current state of the packing pass, implemented by frv_pack_insns. */ 6988 static struct { 6989 /* The state of the pipeline DFA. */ 6990 state_t dfa_state; 6991 6992 /* Which hardware registers are set within the current packet, 6993 and the conditions under which they are set. */ 6994 regstate_t regstate[FIRST_PSEUDO_REGISTER]; 6995 6996 /* The memory locations that have been modified so far in this 6997 packet. MEM is the memref and COND is the regstate_t condition 6998 under which it is set. */ 6999 struct { 7000 rtx mem; 7001 regstate_t cond; 7002 } mems[2]; 7003 7004 /* The number of valid entries in MEMS. The value is larger than 7005 ARRAY_SIZE (mems) if there were too many mems to record. */ 7006 unsigned int num_mems; 7007 7008 /* The maximum number of instructions that can be packed together. */ 7009 unsigned int issue_rate; 7010 7011 /* The instructions in the packet, partitioned into groups. */ 7012 struct frv_packet_group groups[NUM_GROUPS]; 7013 7014 /* The instructions that make up the current packet. */ 7015 rtx_insn *insns[ARRAY_SIZE (frv_unit_codes)]; 7016 unsigned int num_insns; 7017 } frv_packet; 7018 7019 /* Return the regstate_t flags for the given COND_EXEC condition. 7020 Abort if the condition isn't in the right form. */ 7021 7022 static int 7023 frv_cond_flags (rtx cond) 7024 { 7025 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) 7026 && GET_CODE (XEXP (cond, 0)) == REG 7027 && CR_P (REGNO (XEXP (cond, 0))) 7028 && XEXP (cond, 1) == const0_rtx); 7029 return ((REGNO (XEXP (cond, 0)) - CR_FIRST) 7030 | (GET_CODE (cond) == NE 7031 ? REGSTATE_IF_TRUE 7032 : REGSTATE_IF_FALSE)); 7033 } 7034 7035 7036 /* Return true if something accessed under condition COND2 can 7037 conflict with something written under condition COND1. */ 7038 7039 static bool 7040 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2) 7041 { 7042 /* If either reference was unconditional, we have a conflict. */ 7043 if ((cond1 & REGSTATE_IF_EITHER) == 0 7044 || (cond2 & REGSTATE_IF_EITHER) == 0) 7045 return true; 7046 7047 /* The references might conflict if they were controlled by 7048 different CRs. */ 7049 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK)) 7050 return true; 7051 7052 /* They definitely conflict if they are controlled by the 7053 same condition. */ 7054 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0) 7055 return true; 7056 7057 return false; 7058 } 7059 7060 7061 /* Return true if an instruction with pattern PAT depends on an 7062 instruction in the current packet. COND describes the condition 7063 under which PAT might be set or used. */ 7064 7065 static bool 7066 frv_registers_conflict_p_1 (rtx pat, regstate_t cond) 7067 { 7068 subrtx_var_iterator::array_type array; 7069 FOR_EACH_SUBRTX_VAR (iter, array, pat, NONCONST) 7070 { 7071 rtx x = *iter; 7072 if (GET_CODE (x) == REG) 7073 { 7074 unsigned int regno; 7075 FOR_EACH_REGNO (regno, x) 7076 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0) 7077 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond)) 7078 return true; 7079 } 7080 else if (GET_CODE (x) == MEM) 7081 { 7082 /* If we ran out of memory slots, assume a conflict. */ 7083 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems)) 7084 return 1; 7085 7086 /* Check for output or true dependencies with earlier MEMs. */ 7087 for (unsigned int i = 0; i < frv_packet.num_mems; i++) 7088 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond)) 7089 { 7090 if (true_dependence (frv_packet.mems[i].mem, VOIDmode, x)) 7091 return true; 7092 7093 if (output_dependence (frv_packet.mems[i].mem, x)) 7094 return true; 7095 } 7096 } 7097 7098 /* The return values of calls aren't significant: they describe 7099 the effect of the call as a whole, not of the insn itself. */ 7100 else if (GET_CODE (x) == SET && GET_CODE (SET_SRC (x)) == CALL) 7101 iter.substitute (SET_SRC (x)); 7102 } 7103 return false; 7104 } 7105 7106 7107 /* Return true if something in X might depend on an instruction 7108 in the current packet. */ 7109 7110 static bool 7111 frv_registers_conflict_p (rtx x) 7112 { 7113 regstate_t flags; 7114 7115 flags = 0; 7116 if (GET_CODE (x) == COND_EXEC) 7117 { 7118 if (frv_registers_conflict_p_1 (XEXP (x, 0), flags)) 7119 return true; 7120 7121 flags |= frv_cond_flags (XEXP (x, 0)); 7122 x = XEXP (x, 1); 7123 } 7124 return frv_registers_conflict_p_1 (x, flags); 7125 } 7126 7127 7128 /* A note_stores callback. DATA points to the regstate_t condition 7129 under which X is modified. Update FRV_PACKET accordingly. */ 7130 7131 static void 7132 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) 7133 { 7134 unsigned int regno; 7135 7136 if (GET_CODE (x) == REG) 7137 FOR_EACH_REGNO (regno, x) 7138 frv_packet.regstate[regno] |= *(regstate_t *) data; 7139 7140 if (GET_CODE (x) == MEM) 7141 { 7142 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems)) 7143 { 7144 frv_packet.mems[frv_packet.num_mems].mem = x; 7145 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data; 7146 } 7147 frv_packet.num_mems++; 7148 } 7149 } 7150 7151 7152 /* Update the register state information for an instruction whose 7153 body is X. */ 7154 7155 static void 7156 frv_registers_update (rtx x) 7157 { 7158 regstate_t flags; 7159 7160 flags = REGSTATE_MODIFIED; 7161 if (GET_CODE (x) == COND_EXEC) 7162 { 7163 flags |= frv_cond_flags (XEXP (x, 0)); 7164 x = XEXP (x, 1); 7165 } 7166 note_stores (x, frv_registers_update_1, &flags); 7167 } 7168 7169 7170 /* Initialize frv_packet for the start of a new packet. */ 7171 7172 static void 7173 frv_start_packet (void) 7174 { 7175 enum frv_insn_group group; 7176 7177 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate)); 7178 frv_packet.num_mems = 0; 7179 frv_packet.num_insns = 0; 7180 for (group = GROUP_I; group < NUM_GROUPS; 7181 group = (enum frv_insn_group) (group + 1)) 7182 frv_packet.groups[group].num_insns = 0; 7183 } 7184 7185 7186 /* Likewise for the start of a new basic block. */ 7187 7188 static void 7189 frv_start_packet_block (void) 7190 { 7191 state_reset (frv_packet.dfa_state); 7192 frv_start_packet (); 7193 } 7194 7195 7196 /* Finish the current packet, if any, and start a new one. Call 7197 HANDLE_PACKET with FRV_PACKET describing the completed packet. */ 7198 7199 static void 7200 frv_finish_packet (void (*handle_packet) (void)) 7201 { 7202 if (frv_packet.num_insns > 0) 7203 { 7204 handle_packet (); 7205 state_transition (frv_packet.dfa_state, 0); 7206 frv_start_packet (); 7207 } 7208 } 7209 7210 7211 /* Return true if INSN can be added to the current packet. Update 7212 the DFA state on success. */ 7213 7214 static bool 7215 frv_pack_insn_p (rtx_insn *insn) 7216 { 7217 /* See if the packet is already as long as it can be. */ 7218 if (frv_packet.num_insns == frv_packet.issue_rate) 7219 return false; 7220 7221 /* If the scheduler thought that an instruction should start a packet, 7222 it's usually a good idea to believe it. It knows much more about 7223 the latencies than we do. 7224 7225 There are some exceptions though: 7226 7227 - Conditional instructions are scheduled on the assumption that 7228 they will be executed. This is usually a good thing, since it 7229 tends to avoid unnecessary stalls in the conditional code. 7230 But we want to pack conditional instructions as tightly as 7231 possible, in order to optimize the case where they aren't 7232 executed. 7233 7234 - The scheduler will always put branches on their own, even 7235 if there's no real dependency. 7236 7237 - There's no point putting a call in its own packet unless 7238 we have to. */ 7239 if (frv_packet.num_insns > 0 7240 && NONJUMP_INSN_P (insn) 7241 && GET_MODE (insn) == TImode 7242 && GET_CODE (PATTERN (insn)) != COND_EXEC) 7243 return false; 7244 7245 /* Check for register conflicts. Don't do this for setlo since any 7246 conflict will be with the partnering sethi, with which it can 7247 be packed. */ 7248 if (get_attr_type (insn) != TYPE_SETLO) 7249 if (frv_registers_conflict_p (PATTERN (insn))) 7250 return false; 7251 7252 return state_transition (frv_packet.dfa_state, insn) < 0; 7253 } 7254 7255 7256 /* Add instruction INSN to the current packet. */ 7257 7258 static void 7259 frv_add_insn_to_packet (rtx_insn *insn) 7260 { 7261 struct frv_packet_group *packet_group; 7262 7263 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; 7264 packet_group->insns[packet_group->num_insns++] = insn; 7265 frv_packet.insns[frv_packet.num_insns++] = insn; 7266 7267 frv_registers_update (PATTERN (insn)); 7268 } 7269 7270 7271 /* Insert INSN (a member of frv_nops[]) into the current packet. If the 7272 packet ends in a branch or call, insert the nop before it, otherwise 7273 add to the end. */ 7274 7275 static void 7276 frv_insert_nop_in_packet (rtx_insn *insn) 7277 { 7278 struct frv_packet_group *packet_group; 7279 rtx_insn *last; 7280 7281 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; 7282 last = frv_packet.insns[frv_packet.num_insns - 1]; 7283 if (! NONJUMP_INSN_P (last)) 7284 { 7285 insn = emit_insn_before (PATTERN (insn), last); 7286 frv_packet.insns[frv_packet.num_insns - 1] = insn; 7287 frv_packet.insns[frv_packet.num_insns++] = last; 7288 } 7289 else 7290 { 7291 insn = emit_insn_after (PATTERN (insn), last); 7292 frv_packet.insns[frv_packet.num_insns++] = insn; 7293 } 7294 packet_group->insns[packet_group->num_insns++] = insn; 7295 } 7296 7297 7298 /* If packing is enabled, divide the instructions into packets and 7299 return true. Call HANDLE_PACKET for each complete packet. */ 7300 7301 static bool 7302 frv_for_each_packet (void (*handle_packet) (void)) 7303 { 7304 rtx_insn *insn, *next_insn; 7305 7306 frv_packet.issue_rate = frv_issue_rate (); 7307 7308 /* Early exit if we don't want to pack insns. */ 7309 if (!optimize 7310 || !flag_schedule_insns_after_reload 7311 || !TARGET_VLIW_BRANCH 7312 || frv_packet.issue_rate == 1) 7313 return false; 7314 7315 /* Set up the initial packing state. */ 7316 dfa_start (); 7317 frv_packet.dfa_state = alloca (state_size ()); 7318 7319 frv_start_packet_block (); 7320 for (insn = get_insns (); insn != 0; insn = next_insn) 7321 { 7322 enum rtx_code code; 7323 bool eh_insn_p; 7324 7325 code = GET_CODE (insn); 7326 next_insn = NEXT_INSN (insn); 7327 7328 if (code == CODE_LABEL) 7329 { 7330 frv_finish_packet (handle_packet); 7331 frv_start_packet_block (); 7332 } 7333 7334 if (INSN_P (insn)) 7335 switch (GET_CODE (PATTERN (insn))) 7336 { 7337 case USE: 7338 case CLOBBER: 7339 break; 7340 7341 default: 7342 /* Calls mustn't be packed on a TOMCAT. */ 7343 if (CALL_P (insn) && frv_cpu_type == FRV_CPU_TOMCAT) 7344 frv_finish_packet (handle_packet); 7345 7346 /* Since the last instruction in a packet determines the EH 7347 region, any exception-throwing instruction must come at 7348 the end of reordered packet. Insns that issue to a 7349 branch unit are bound to come last; for others it's 7350 too hard to predict. */ 7351 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL); 7352 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn)) 7353 frv_finish_packet (handle_packet); 7354 7355 /* Finish the current packet if we can't add INSN to it. 7356 Simulate cycles until INSN is ready to issue. */ 7357 if (!frv_pack_insn_p (insn)) 7358 { 7359 frv_finish_packet (handle_packet); 7360 while (!frv_pack_insn_p (insn)) 7361 state_transition (frv_packet.dfa_state, 0); 7362 } 7363 7364 /* Add the instruction to the packet. */ 7365 frv_add_insn_to_packet (insn); 7366 7367 /* Calls and jumps end a packet, as do insns that throw 7368 an exception. */ 7369 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p) 7370 frv_finish_packet (handle_packet); 7371 break; 7372 } 7373 } 7374 frv_finish_packet (handle_packet); 7375 dfa_finish (); 7376 return true; 7377 } 7378 7379 /* Subroutine of frv_sort_insn_group. We are trying to sort 7380 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly 7381 language order. We have already picked a new position for 7382 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set. 7383 These instructions will occupy elements [0, LOWER_SLOT) and 7384 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is 7385 the DFA state after issuing these instructions. 7386 7387 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation 7388 of the unused instructions. Return true if one such permutation gives 7389 a valid ordering, leaving the successful permutation in sorted[]. 7390 Do not modify sorted[] until a valid permutation is found. */ 7391 7392 static bool 7393 frv_sort_insn_group_1 (enum frv_insn_group group, 7394 unsigned int lower_slot, unsigned int upper_slot, 7395 unsigned int issued, unsigned int num_insns, 7396 state_t state) 7397 { 7398 struct frv_packet_group *packet_group; 7399 unsigned int i; 7400 state_t test_state; 7401 size_t dfa_size; 7402 rtx_insn *insn; 7403 7404 /* Early success if we've filled all the slots. */ 7405 if (lower_slot == upper_slot) 7406 return true; 7407 7408 packet_group = &frv_packet.groups[group]; 7409 dfa_size = state_size (); 7410 test_state = alloca (dfa_size); 7411 7412 /* Try issuing each unused instruction. */ 7413 for (i = num_insns - 1; i + 1 != 0; i--) 7414 if (~issued & (1 << i)) 7415 { 7416 insn = packet_group->sorted[i]; 7417 memcpy (test_state, state, dfa_size); 7418 if (state_transition (test_state, insn) < 0 7419 && cpu_unit_reservation_p (test_state, 7420 NTH_UNIT (group, upper_slot - 1)) 7421 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1, 7422 issued | (1 << i), num_insns, 7423 test_state)) 7424 { 7425 packet_group->sorted[upper_slot - 1] = insn; 7426 return true; 7427 } 7428 } 7429 7430 return false; 7431 } 7432 7433 /* Compare two instructions by their frv_insn_unit. */ 7434 7435 static int 7436 frv_compare_insns (const void *first, const void *second) 7437 { 7438 rtx_insn * const *insn1 = (rtx_insn * const *) first; 7439 rtx_insn * const *insn2 = (rtx_insn * const *) second; 7440 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2); 7441 } 7442 7443 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[] 7444 and sort it into assembly language order. See frv.md for a description of 7445 the algorithm. */ 7446 7447 static void 7448 frv_sort_insn_group (enum frv_insn_group group) 7449 { 7450 struct frv_packet_group *packet_group; 7451 unsigned int first, i, nop, max_unit, num_slots; 7452 state_t state, test_state; 7453 size_t dfa_size; 7454 7455 packet_group = &frv_packet.groups[group]; 7456 7457 /* Assume no nop is needed. */ 7458 packet_group->nop = 0; 7459 7460 if (packet_group->num_insns == 0) 7461 return; 7462 7463 /* Copy insns[] to sorted[]. */ 7464 memcpy (packet_group->sorted, packet_group->insns, 7465 sizeof (rtx) * packet_group->num_insns); 7466 7467 /* Sort sorted[] by the unit that each insn tries to take first. */ 7468 if (packet_group->num_insns > 1) 7469 qsort (packet_group->sorted, packet_group->num_insns, 7470 sizeof (rtx), frv_compare_insns); 7471 7472 /* That's always enough for branch and control insns. */ 7473 if (group == GROUP_B || group == GROUP_C) 7474 return; 7475 7476 dfa_size = state_size (); 7477 state = alloca (dfa_size); 7478 test_state = alloca (dfa_size); 7479 7480 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue 7481 consecutively and such that the DFA takes unit X when sorted[X] 7482 is added. Set STATE to the new DFA state. */ 7483 state_reset (test_state); 7484 for (first = 0; first < packet_group->num_insns; first++) 7485 { 7486 memcpy (state, test_state, dfa_size); 7487 if (state_transition (test_state, packet_group->sorted[first]) >= 0 7488 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first))) 7489 break; 7490 } 7491 7492 /* If all the instructions issued in ascending order, we're done. */ 7493 if (first == packet_group->num_insns) 7494 return; 7495 7496 /* Add nops to the end of sorted[] and try each permutation until 7497 we find one that works. */ 7498 for (nop = 0; nop < frv_num_nops; nop++) 7499 { 7500 max_unit = frv_insn_unit (frv_nops[nop]); 7501 if (frv_unit_groups[max_unit] == group) 7502 { 7503 packet_group->nop = frv_nops[nop]; 7504 num_slots = UNIT_NUMBER (max_unit) + 1; 7505 for (i = packet_group->num_insns; i < num_slots; i++) 7506 packet_group->sorted[i] = frv_nops[nop]; 7507 if (frv_sort_insn_group_1 (group, first, num_slots, 7508 (1 << first) - 1, num_slots, state)) 7509 return; 7510 } 7511 } 7512 gcc_unreachable (); 7513 } 7514 7515 /* Sort the current packet into assembly-language order. Set packing 7516 flags as appropriate. */ 7517 7518 static void 7519 frv_reorder_packet (void) 7520 { 7521 unsigned int cursor[NUM_GROUPS]; 7522 rtx_insn *insns[ARRAY_SIZE (frv_unit_groups)]; 7523 unsigned int unit, to, from; 7524 enum frv_insn_group group; 7525 struct frv_packet_group *packet_group; 7526 7527 /* First sort each group individually. */ 7528 for (group = GROUP_I; group < NUM_GROUPS; 7529 group = (enum frv_insn_group) (group + 1)) 7530 { 7531 cursor[group] = 0; 7532 frv_sort_insn_group (group); 7533 } 7534 7535 /* Go through the unit template and try add an instruction from 7536 that unit's group. */ 7537 to = 0; 7538 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++) 7539 { 7540 group = frv_unit_groups[unit]; 7541 packet_group = &frv_packet.groups[group]; 7542 if (cursor[group] < packet_group->num_insns) 7543 { 7544 /* frv_reorg should have added nops for us. */ 7545 gcc_assert (packet_group->sorted[cursor[group]] 7546 != packet_group->nop); 7547 insns[to++] = packet_group->sorted[cursor[group]++]; 7548 } 7549 } 7550 7551 gcc_assert (to == frv_packet.num_insns); 7552 7553 /* Clear the last instruction's packing flag, thus marking the end of 7554 a packet. Reorder the other instructions relative to it. */ 7555 CLEAR_PACKING_FLAG (insns[to - 1]); 7556 for (from = 0; from < to - 1; from++) 7557 { 7558 remove_insn (insns[from]); 7559 add_insn_before (insns[from], insns[to - 1], NULL); 7560 SET_PACKING_FLAG (insns[from]); 7561 } 7562 } 7563 7564 7565 /* Divide instructions into packets. Reorder the contents of each 7566 packet so that they are in the correct assembly-language order. 7567 7568 Since this pass can change the raw meaning of the rtl stream, it must 7569 only be called at the last minute, just before the instructions are 7570 written out. */ 7571 7572 static void 7573 frv_pack_insns (void) 7574 { 7575 if (frv_for_each_packet (frv_reorder_packet)) 7576 frv_insn_packing_flag = 0; 7577 else 7578 frv_insn_packing_flag = -1; 7579 } 7580 7581 /* See whether we need to add nops to group GROUP in order to 7582 make a valid packet. */ 7583 7584 static void 7585 frv_fill_unused_units (enum frv_insn_group group) 7586 { 7587 unsigned int non_nops, nops, i; 7588 struct frv_packet_group *packet_group; 7589 7590 packet_group = &frv_packet.groups[group]; 7591 7592 /* Sort the instructions into assembly-language order. 7593 Use nops to fill slots that are otherwise unused. */ 7594 frv_sort_insn_group (group); 7595 7596 /* See how many nops are needed before the final useful instruction. */ 7597 i = nops = 0; 7598 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++) 7599 while (packet_group->sorted[i++] == packet_group->nop) 7600 nops++; 7601 7602 /* Insert that many nops into the instruction stream. */ 7603 while (nops-- > 0) 7604 frv_insert_nop_in_packet (packet_group->nop); 7605 } 7606 7607 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */ 7608 7609 static bool 7610 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2) 7611 { 7612 if (io1->const_address != 0 && io2->const_address != 0) 7613 return io1->const_address == io2->const_address; 7614 7615 if (io1->var_address != 0 && io2->var_address != 0) 7616 return rtx_equal_p (io1->var_address, io2->var_address); 7617 7618 return false; 7619 } 7620 7621 /* Return true if operations IO1 and IO2 are guaranteed to complete 7622 in order. */ 7623 7624 static bool 7625 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2) 7626 { 7627 /* The order of writes is always preserved. */ 7628 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE) 7629 return true; 7630 7631 /* The order of reads isn't preserved. */ 7632 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE) 7633 return false; 7634 7635 /* One operation is a write and the other is (or could be) a read. 7636 The order is only guaranteed if the accesses are to the same 7637 doubleword. */ 7638 return frv_same_doubleword_p (io1, io2); 7639 } 7640 7641 /* Generalize I/O operation X so that it covers both X and Y. */ 7642 7643 static void 7644 frv_io_union (struct frv_io *x, const struct frv_io *y) 7645 { 7646 if (x->type != y->type) 7647 x->type = FRV_IO_UNKNOWN; 7648 if (!frv_same_doubleword_p (x, y)) 7649 { 7650 x->const_address = 0; 7651 x->var_address = 0; 7652 } 7653 } 7654 7655 /* Fill IO with information about the load or store associated with 7656 membar instruction INSN. */ 7657 7658 static void 7659 frv_extract_membar (struct frv_io *io, rtx_insn *insn) 7660 { 7661 extract_insn (insn); 7662 io->type = (enum frv_io_type) INTVAL (recog_data.operand[2]); 7663 io->const_address = INTVAL (recog_data.operand[1]); 7664 io->var_address = XEXP (recog_data.operand[0], 0); 7665 } 7666 7667 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA 7668 if X is a register and *DATA depends on X. */ 7669 7670 static void 7671 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) 7672 { 7673 rtx *other = (rtx *) data; 7674 7675 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other)) 7676 *other = 0; 7677 } 7678 7679 /* A note_stores callback for which DATA points to a HARD_REG_SET. 7680 Remove every modified register from the set. */ 7681 7682 static void 7683 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) 7684 { 7685 HARD_REG_SET *set = (HARD_REG_SET *) data; 7686 unsigned int regno; 7687 7688 if (REG_P (x)) 7689 FOR_EACH_REGNO (regno, x) 7690 CLEAR_HARD_REG_BIT (*set, regno); 7691 } 7692 7693 /* A note_uses callback that adds all registers in *X to hard register 7694 set *DATA. */ 7695 7696 static void 7697 frv_io_handle_use (rtx *x, void *data) 7698 { 7699 find_all_hard_regs (*x, (HARD_REG_SET *) data); 7700 } 7701 7702 /* Go through block BB looking for membars to remove. There are two 7703 cases where intra-block analysis is enough: 7704 7705 - a membar is redundant if it occurs between two consecutive I/O 7706 operations and if those operations are guaranteed to complete 7707 in order. 7708 7709 - a membar for a __builtin_read is redundant if the result is 7710 used before the next I/O operation is issued. 7711 7712 If the last membar in the block could not be removed, and there 7713 are guaranteed to be no I/O operations between that membar and 7714 the end of the block, store the membar in *LAST_MEMBAR, otherwise 7715 store null. 7716 7717 Describe the block's first I/O operation in *NEXT_IO. Describe 7718 an unknown operation if the block doesn't do any I/O. */ 7719 7720 static void 7721 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io, 7722 rtx_insn **last_membar) 7723 { 7724 HARD_REG_SET used_regs; 7725 rtx set; 7726 rtx_insn *insn, *next_membar; 7727 bool next_is_end_p; 7728 7729 /* NEXT_IO is the next I/O operation to be performed after the current 7730 instruction. It starts off as being an unknown operation. */ 7731 memset (next_io, 0, sizeof (*next_io)); 7732 7733 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */ 7734 next_is_end_p = true; 7735 7736 /* If the current instruction is a __builtin_read or __builtin_write, 7737 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR 7738 is null if the membar has already been deleted. 7739 7740 Note that the initialization here should only be needed to 7741 suppress warnings. */ 7742 next_membar = 0; 7743 7744 /* USED_REGS is the set of registers that are used before the 7745 next I/O instruction. */ 7746 CLEAR_HARD_REG_SET (used_regs); 7747 7748 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn)) 7749 if (CALL_P (insn)) 7750 { 7751 /* We can't predict what a call will do to volatile memory. */ 7752 memset (next_io, 0, sizeof (struct frv_io)); 7753 next_is_end_p = false; 7754 CLEAR_HARD_REG_SET (used_regs); 7755 } 7756 else if (INSN_P (insn)) 7757 switch (recog_memoized (insn)) 7758 { 7759 case CODE_FOR_optional_membar_qi: 7760 case CODE_FOR_optional_membar_hi: 7761 case CODE_FOR_optional_membar_si: 7762 case CODE_FOR_optional_membar_di: 7763 next_membar = insn; 7764 if (next_is_end_p) 7765 { 7766 /* Local information isn't enough to decide whether this 7767 membar is needed. Stash it away for later. */ 7768 *last_membar = insn; 7769 frv_extract_membar (next_io, insn); 7770 next_is_end_p = false; 7771 } 7772 else 7773 { 7774 /* Check whether the I/O operation before INSN could be 7775 reordered with one described by NEXT_IO. If it can't, 7776 INSN will not be needed. */ 7777 struct frv_io prev_io; 7778 7779 frv_extract_membar (&prev_io, insn); 7780 if (frv_io_fixed_order_p (&prev_io, next_io)) 7781 { 7782 if (dump_file) 7783 fprintf (dump_file, 7784 ";; [Local] Removing membar %d since order" 7785 " of accesses is guaranteed\n", 7786 INSN_UID (next_membar)); 7787 7788 insn = NEXT_INSN (insn); 7789 delete_insn (next_membar); 7790 next_membar = 0; 7791 } 7792 *next_io = prev_io; 7793 } 7794 break; 7795 7796 default: 7797 /* Invalidate NEXT_IO's address if it depends on something that 7798 is clobbered by INSN. */ 7799 if (next_io->var_address) 7800 note_stores (PATTERN (insn), frv_io_check_address, 7801 &next_io->var_address); 7802 7803 /* If the next membar is associated with a __builtin_read, 7804 see if INSN reads from that address. If it does, and if 7805 the destination register is used before the next I/O access, 7806 there is no need for the membar. */ 7807 set = PATTERN (insn); 7808 if (next_io->type == FRV_IO_READ 7809 && next_io->var_address != 0 7810 && next_membar != 0 7811 && GET_CODE (set) == SET 7812 && GET_CODE (SET_DEST (set)) == REG 7813 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set)))) 7814 { 7815 rtx src; 7816 7817 src = SET_SRC (set); 7818 if (GET_CODE (src) == ZERO_EXTEND) 7819 src = XEXP (src, 0); 7820 7821 if (GET_CODE (src) == MEM 7822 && rtx_equal_p (XEXP (src, 0), next_io->var_address)) 7823 { 7824 if (dump_file) 7825 fprintf (dump_file, 7826 ";; [Local] Removing membar %d since the target" 7827 " of %d is used before the I/O operation\n", 7828 INSN_UID (next_membar), INSN_UID (insn)); 7829 7830 if (next_membar == *last_membar) 7831 *last_membar = 0; 7832 7833 delete_insn (next_membar); 7834 next_membar = 0; 7835 } 7836 } 7837 7838 /* If INSN has volatile references, forget about any registers 7839 that are used after it. Otherwise forget about uses that 7840 are (or might be) defined by INSN. */ 7841 if (volatile_refs_p (PATTERN (insn))) 7842 CLEAR_HARD_REG_SET (used_regs); 7843 else 7844 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs); 7845 7846 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs); 7847 break; 7848 } 7849 } 7850 7851 /* See if MEMBAR, the last membar instruction in BB, can be removed. 7852 FIRST_IO[X] describes the first operation performed by basic block X. */ 7853 7854 static void 7855 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io, 7856 rtx_insn *membar) 7857 { 7858 struct frv_io this_io, next_io; 7859 edge succ; 7860 edge_iterator ei; 7861 7862 /* We need to keep the membar if there is an edge to the exit block. */ 7863 FOR_EACH_EDGE (succ, ei, bb->succs) 7864 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */ 7865 if (succ->dest == EXIT_BLOCK_PTR_FOR_FN (cfun)) 7866 return; 7867 7868 /* Work out the union of all successor blocks. */ 7869 ei = ei_start (bb->succs); 7870 ei_cond (ei, &succ); 7871 /* next_io = first_io[bb->succ->dest->index]; */ 7872 next_io = first_io[succ->dest->index]; 7873 ei = ei_start (bb->succs); 7874 if (ei_cond (ei, &succ)) 7875 { 7876 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei)) 7877 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/ 7878 frv_io_union (&next_io, &first_io[succ->dest->index]); 7879 } 7880 else 7881 gcc_unreachable (); 7882 7883 frv_extract_membar (&this_io, membar); 7884 if (frv_io_fixed_order_p (&this_io, &next_io)) 7885 { 7886 if (dump_file) 7887 fprintf (dump_file, 7888 ";; [Global] Removing membar %d since order of accesses" 7889 " is guaranteed\n", INSN_UID (membar)); 7890 7891 delete_insn (membar); 7892 } 7893 } 7894 7895 /* Remove redundant membars from the current function. */ 7896 7897 static void 7898 frv_optimize_membar (void) 7899 { 7900 basic_block bb; 7901 struct frv_io *first_io; 7902 rtx_insn **last_membar; 7903 7904 compute_bb_for_insn (); 7905 first_io = XCNEWVEC (struct frv_io, last_basic_block_for_fn (cfun)); 7906 last_membar = XCNEWVEC (rtx_insn *, last_basic_block_for_fn (cfun)); 7907 7908 FOR_EACH_BB_FN (bb, cfun) 7909 frv_optimize_membar_local (bb, &first_io[bb->index], 7910 &last_membar[bb->index]); 7911 7912 FOR_EACH_BB_FN (bb, cfun) 7913 if (last_membar[bb->index] != 0) 7914 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]); 7915 7916 free (first_io); 7917 free (last_membar); 7918 } 7919 7920 /* Used by frv_reorg to keep track of the current packet's address. */ 7921 static unsigned int frv_packet_address; 7922 7923 /* If the current packet falls through to a label, try to pad the packet 7924 with nops in order to fit the label's alignment requirements. */ 7925 7926 static void 7927 frv_align_label (void) 7928 { 7929 unsigned int alignment, target, nop; 7930 rtx_insn *x, *last, *barrier, *label; 7931 7932 /* Walk forward to the start of the next packet. Set ALIGNMENT to the 7933 maximum alignment of that packet, LABEL to the last label between 7934 the packets, and BARRIER to the last barrier. */ 7935 last = frv_packet.insns[frv_packet.num_insns - 1]; 7936 label = barrier = 0; 7937 alignment = 4; 7938 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x)) 7939 { 7940 if (LABEL_P (x)) 7941 { 7942 unsigned int subalign = 1 << label_to_alignment (x).levels[0].log; 7943 alignment = MAX (alignment, subalign); 7944 label = x; 7945 } 7946 if (BARRIER_P (x)) 7947 barrier = x; 7948 } 7949 7950 /* If -malign-labels, and the packet falls through to an unaligned 7951 label, try introducing a nop to align that label to 8 bytes. */ 7952 if (TARGET_ALIGN_LABELS 7953 && label != 0 7954 && barrier == 0 7955 && frv_packet.num_insns < frv_packet.issue_rate) 7956 alignment = MAX (alignment, 8); 7957 7958 /* Advance the address to the end of the current packet. */ 7959 frv_packet_address += frv_packet.num_insns * 4; 7960 7961 /* Work out the target address, after alignment. */ 7962 target = (frv_packet_address + alignment - 1) & -alignment; 7963 7964 /* If the packet falls through to the label, try to find an efficient 7965 padding sequence. */ 7966 if (barrier == 0) 7967 { 7968 /* First try adding nops to the current packet. */ 7969 for (nop = 0; nop < frv_num_nops; nop++) 7970 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop])) 7971 { 7972 frv_insert_nop_in_packet (frv_nops[nop]); 7973 frv_packet_address += 4; 7974 } 7975 7976 /* If we still haven't reached the target, add some new packets that 7977 contain only nops. If there are two types of nop, insert an 7978 alternating sequence of frv_nops[0] and frv_nops[1], which will 7979 lead to packets like: 7980 7981 nop.p 7982 mnop.p/fnop.p 7983 nop.p 7984 mnop/fnop 7985 7986 etc. Just emit frv_nops[0] if that's the only nop we have. */ 7987 last = frv_packet.insns[frv_packet.num_insns - 1]; 7988 nop = 0; 7989 while (frv_packet_address < target) 7990 { 7991 last = emit_insn_after (PATTERN (frv_nops[nop]), last); 7992 frv_packet_address += 4; 7993 if (frv_num_nops > 1) 7994 nop ^= 1; 7995 } 7996 } 7997 7998 frv_packet_address = target; 7999 } 8000 8001 /* Subroutine of frv_reorg, called after each packet has been constructed 8002 in frv_packet. */ 8003 8004 static void 8005 frv_reorg_packet (void) 8006 { 8007 frv_fill_unused_units (GROUP_I); 8008 frv_fill_unused_units (GROUP_FM); 8009 frv_align_label (); 8010 } 8011 8012 /* Add an instruction with pattern NOP to frv_nops[]. */ 8013 8014 static void 8015 frv_register_nop (rtx nop) 8016 { 8017 rtx_insn *nop_insn = make_insn_raw (nop); 8018 SET_NEXT_INSN (nop_insn) = 0; 8019 SET_PREV_INSN (nop_insn) = 0; 8020 frv_nops[frv_num_nops++] = nop_insn; 8021 } 8022 8023 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions 8024 into packets and check whether we need to insert nops in order to 8025 fulfill the processor's issue requirements. Also, if the user has 8026 requested a certain alignment for a label, try to meet that alignment 8027 by inserting nops in the previous packet. */ 8028 8029 static void 8030 frv_reorg (void) 8031 { 8032 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p) 8033 frv_optimize_membar (); 8034 8035 frv_num_nops = 0; 8036 frv_register_nop (gen_nop ()); 8037 if (TARGET_MEDIA) 8038 frv_register_nop (gen_mnop ()); 8039 if (TARGET_HARD_FLOAT) 8040 frv_register_nop (gen_fnop ()); 8041 8042 /* Estimate the length of each branch. Although this may change after 8043 we've inserted nops, it will only do so in big functions. */ 8044 shorten_branches (get_insns ()); 8045 8046 frv_packet_address = 0; 8047 frv_for_each_packet (frv_reorg_packet); 8048 } 8049 8050 #define def_builtin(name, type, code) \ 8051 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL) 8052 8053 struct builtin_description 8054 { 8055 enum insn_code icode; 8056 const char *name; 8057 enum frv_builtins code; 8058 enum rtx_code comparison; 8059 unsigned int flag; 8060 }; 8061 8062 /* Media intrinsics that take a single, constant argument. */ 8063 8064 static struct builtin_description bdesc_set[] = 8065 { 8066 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, UNKNOWN, 0 } 8067 }; 8068 8069 /* Media intrinsics that take just one argument. */ 8070 8071 static struct builtin_description bdesc_1arg[] = 8072 { 8073 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, UNKNOWN, 0 }, 8074 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, UNKNOWN, 0 }, 8075 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, UNKNOWN, 0 }, 8076 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, UNKNOWN, 0}, 8077 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, UNKNOWN, 0 }, 8078 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, UNKNOWN, 0 } 8079 }; 8080 8081 /* Media intrinsics that take two arguments. */ 8082 8083 static struct builtin_description bdesc_2arg[] = 8084 { 8085 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, UNKNOWN, 0}, 8086 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, UNKNOWN, 0}, 8087 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, UNKNOWN, 0}, 8088 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, UNKNOWN, 0}, 8089 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, UNKNOWN, 0}, 8090 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, UNKNOWN, 0}, 8091 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, UNKNOWN, 0}, 8092 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, UNKNOWN, 0}, 8093 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, UNKNOWN, 0}, 8094 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, UNKNOWN, 0}, 8095 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, UNKNOWN, 0}, 8096 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, UNKNOWN, 0}, 8097 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, UNKNOWN, 0}, 8098 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, UNKNOWN, 0}, 8099 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, UNKNOWN, 0}, 8100 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, UNKNOWN, 0}, 8101 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, UNKNOWN, 0}, 8102 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, UNKNOWN, 0}, 8103 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, UNKNOWN, 0}, 8104 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, UNKNOWN, 0}, 8105 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, UNKNOWN, 0}, 8106 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, UNKNOWN, 0}, 8107 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, UNKNOWN, 0}, 8108 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, UNKNOWN, 0}, 8109 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, UNKNOWN, 0}, 8110 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, UNKNOWN, 0}, 8111 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, UNKNOWN, 0} 8112 }; 8113 8114 /* Integer intrinsics that take two arguments and have no return value. */ 8115 8116 static struct builtin_description bdesc_int_void2arg[] = 8117 { 8118 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, UNKNOWN, 0}, 8119 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, UNKNOWN, 0}, 8120 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, UNKNOWN, 0} 8121 }; 8122 8123 static struct builtin_description bdesc_prefetches[] = 8124 { 8125 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, UNKNOWN, 8126 0}, 8127 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, UNKNOWN, 0} 8128 }; 8129 8130 /* Media intrinsics that take two arguments, the first being an ACC number. */ 8131 8132 static struct builtin_description bdesc_cut[] = 8133 { 8134 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, UNKNOWN, 0}, 8135 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, UNKNOWN, 0}, 8136 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, UNKNOWN, 0} 8137 }; 8138 8139 /* Two-argument media intrinsics with an immediate second argument. */ 8140 8141 static struct builtin_description bdesc_2argimm[] = 8142 { 8143 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, UNKNOWN, 0}, 8144 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, UNKNOWN, 0}, 8145 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, UNKNOWN, 0}, 8146 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, UNKNOWN, 0}, 8147 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, UNKNOWN, 0}, 8148 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, UNKNOWN, 0}, 8149 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, UNKNOWN, 0}, 8150 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, UNKNOWN, 0}, 8151 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, UNKNOWN, 0}, 8152 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, UNKNOWN, 0}, 8153 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, UNKNOWN, 0}, 8154 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, UNKNOWN, 0}, 8155 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, UNKNOWN, 0}, 8156 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, UNKNOWN, 0}, 8157 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, UNKNOWN, 0}, 8158 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, UNKNOWN, 0}, 8159 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, UNKNOWN, 0} 8160 }; 8161 8162 /* Media intrinsics that take two arguments and return void, the first argument 8163 being a pointer to 4 words in memory. */ 8164 8165 static struct builtin_description bdesc_void2arg[] = 8166 { 8167 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, UNKNOWN, 0}, 8168 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, UNKNOWN, 0}, 8169 }; 8170 8171 /* Media intrinsics that take three arguments, the first being a const_int that 8172 denotes an accumulator, and that return void. */ 8173 8174 static struct builtin_description bdesc_void3arg[] = 8175 { 8176 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, UNKNOWN, 0}, 8177 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, UNKNOWN, 0}, 8178 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, UNKNOWN, 0}, 8179 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, UNKNOWN, 0}, 8180 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, UNKNOWN, 0}, 8181 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, UNKNOWN, 0}, 8182 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, UNKNOWN, 0}, 8183 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, UNKNOWN, 0}, 8184 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, UNKNOWN, 0}, 8185 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, UNKNOWN, 0}, 8186 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, UNKNOWN, 0}, 8187 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, UNKNOWN, 0}, 8188 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, UNKNOWN, 0}, 8189 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, UNKNOWN, 0}, 8190 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, UNKNOWN, 0}, 8191 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, UNKNOWN, 0}, 8192 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, UNKNOWN, 0}, 8193 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, UNKNOWN, 0}, 8194 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, UNKNOWN, 0}, 8195 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, UNKNOWN, 0}, 8196 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, UNKNOWN, 0}, 8197 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, UNKNOWN, 0}, 8198 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, UNKNOWN, 0}, 8199 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, UNKNOWN, 0}, 8200 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, UNKNOWN, 0} 8201 }; 8202 8203 /* Media intrinsics that take two accumulator numbers as argument and 8204 return void. */ 8205 8206 static struct builtin_description bdesc_voidacc[] = 8207 { 8208 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, UNKNOWN, 0}, 8209 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, UNKNOWN, 0}, 8210 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, UNKNOWN, 0}, 8211 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, UNKNOWN, 0}, 8212 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, UNKNOWN, 0}, 8213 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, UNKNOWN, 0} 8214 }; 8215 8216 /* Intrinsics that load a value and then issue a MEMBAR. The load is 8217 a normal move and the ICODE is for the membar. */ 8218 8219 static struct builtin_description bdesc_loads[] = 8220 { 8221 { CODE_FOR_optional_membar_qi, "__builtin_read8", 8222 FRV_BUILTIN_READ8, UNKNOWN, 0}, 8223 { CODE_FOR_optional_membar_hi, "__builtin_read16", 8224 FRV_BUILTIN_READ16, UNKNOWN, 0}, 8225 { CODE_FOR_optional_membar_si, "__builtin_read32", 8226 FRV_BUILTIN_READ32, UNKNOWN, 0}, 8227 { CODE_FOR_optional_membar_di, "__builtin_read64", 8228 FRV_BUILTIN_READ64, UNKNOWN, 0} 8229 }; 8230 8231 /* Likewise stores. */ 8232 8233 static struct builtin_description bdesc_stores[] = 8234 { 8235 { CODE_FOR_optional_membar_qi, "__builtin_write8", 8236 FRV_BUILTIN_WRITE8, UNKNOWN, 0}, 8237 { CODE_FOR_optional_membar_hi, "__builtin_write16", 8238 FRV_BUILTIN_WRITE16, UNKNOWN, 0}, 8239 { CODE_FOR_optional_membar_si, "__builtin_write32", 8240 FRV_BUILTIN_WRITE32, UNKNOWN, 0}, 8241 { CODE_FOR_optional_membar_di, "__builtin_write64", 8242 FRV_BUILTIN_WRITE64, UNKNOWN, 0}, 8243 }; 8244 8245 /* Initialize media builtins. */ 8246 8247 static void 8248 frv_init_builtins (void) 8249 { 8250 tree accumulator = integer_type_node; 8251 tree integer = integer_type_node; 8252 tree voidt = void_type_node; 8253 tree uhalf = short_unsigned_type_node; 8254 tree sword1 = long_integer_type_node; 8255 tree uword1 = long_unsigned_type_node; 8256 tree sword2 = long_long_integer_type_node; 8257 tree uword2 = long_long_unsigned_type_node; 8258 tree uword4 = build_pointer_type (uword1); 8259 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1)); 8260 tree ubyte = unsigned_char_type_node; 8261 tree iacc = integer_type_node; 8262 8263 #define UNARY(RET, T1) \ 8264 build_function_type_list (RET, T1, NULL_TREE) 8265 8266 #define BINARY(RET, T1, T2) \ 8267 build_function_type_list (RET, T1, T2, NULL_TREE) 8268 8269 #define TRINARY(RET, T1, T2, T3) \ 8270 build_function_type_list (RET, T1, T2, T3, NULL_TREE) 8271 8272 #define QUAD(RET, T1, T2, T3, T4) \ 8273 build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE) 8274 8275 tree void_ftype_void = build_function_type_list (voidt, NULL_TREE); 8276 8277 tree void_ftype_acc = UNARY (voidt, accumulator); 8278 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1); 8279 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2); 8280 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1); 8281 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator); 8282 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1); 8283 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1); 8284 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2); 8285 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2); 8286 8287 tree uw1_ftype_uw1 = UNARY (uword1, uword1); 8288 tree uw1_ftype_sw1 = UNARY (uword1, sword1); 8289 tree uw1_ftype_uw2 = UNARY (uword1, uword2); 8290 tree uw1_ftype_acc = UNARY (uword1, accumulator); 8291 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf); 8292 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1); 8293 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer); 8294 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1); 8295 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1); 8296 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1); 8297 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer); 8298 8299 tree sw1_ftype_int = UNARY (sword1, integer); 8300 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1); 8301 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer); 8302 8303 tree uw2_ftype_uw1 = UNARY (uword2, uword1); 8304 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer); 8305 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2); 8306 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer); 8307 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer); 8308 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf); 8309 8310 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2); 8311 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer); 8312 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1); 8313 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1); 8314 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1); 8315 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2); 8316 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1); 8317 tree sw1_ftype_sw1 = UNARY (sword1, sword1); 8318 tree sw2_ftype_iacc = UNARY (sword2, iacc); 8319 tree sw1_ftype_iacc = UNARY (sword1, iacc); 8320 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node); 8321 tree uw1_ftype_vptr = UNARY (uword1, vptr); 8322 tree uw2_ftype_vptr = UNARY (uword2, vptr); 8323 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte); 8324 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf); 8325 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1); 8326 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2); 8327 8328 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND); 8329 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR); 8330 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR); 8331 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT); 8332 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI); 8333 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI); 8334 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT); 8335 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH); 8336 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI); 8337 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI); 8338 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI); 8339 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS); 8340 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU); 8341 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS); 8342 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS); 8343 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS); 8344 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS); 8345 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS); 8346 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU); 8347 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS); 8348 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU); 8349 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS); 8350 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU); 8351 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS); 8352 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU); 8353 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS); 8354 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS); 8355 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS); 8356 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS); 8357 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS); 8358 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU); 8359 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS); 8360 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU); 8361 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS); 8362 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU); 8363 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS); 8364 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU); 8365 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS); 8366 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU); 8367 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS); 8368 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU); 8369 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS); 8370 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU); 8371 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT); 8372 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS); 8373 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW); 8374 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD); 8375 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH); 8376 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH); 8377 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH); 8378 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH); 8379 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH); 8380 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB); 8381 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE); 8382 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC); 8383 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA); 8384 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC); 8385 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG); 8386 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC); 8387 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG); 8388 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1); 8389 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2); 8390 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP); 8391 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS); 8392 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS); 8393 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS); 8394 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS); 8395 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS); 8396 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS); 8397 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS); 8398 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS); 8399 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS); 8400 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS); 8401 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI); 8402 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI); 8403 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI); 8404 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI); 8405 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS); 8406 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS); 8407 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS); 8408 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS); 8409 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH); 8410 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH); 8411 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH); 8412 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS); 8413 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS); 8414 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI); 8415 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI); 8416 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL); 8417 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL); 8418 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS); 8419 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS); 8420 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU); 8421 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS); 8422 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS); 8423 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS); 8424 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN); 8425 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS); 8426 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll); 8427 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl); 8428 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll); 8429 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl); 8430 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0); 8431 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH); 8432 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8); 8433 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16); 8434 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32); 8435 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64); 8436 8437 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8); 8438 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16); 8439 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32); 8440 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64); 8441 8442 #undef UNARY 8443 #undef BINARY 8444 #undef TRINARY 8445 #undef QUAD 8446 } 8447 8448 /* Set the names for various arithmetic operations according to the 8449 FRV ABI. */ 8450 static void 8451 frv_init_libfuncs (void) 8452 { 8453 set_optab_libfunc (smod_optab, SImode, "__modi"); 8454 set_optab_libfunc (umod_optab, SImode, "__umodi"); 8455 8456 set_optab_libfunc (add_optab, DImode, "__addll"); 8457 set_optab_libfunc (sub_optab, DImode, "__subll"); 8458 set_optab_libfunc (smul_optab, DImode, "__mulll"); 8459 set_optab_libfunc (sdiv_optab, DImode, "__divll"); 8460 set_optab_libfunc (smod_optab, DImode, "__modll"); 8461 set_optab_libfunc (umod_optab, DImode, "__umodll"); 8462 set_optab_libfunc (and_optab, DImode, "__andll"); 8463 set_optab_libfunc (ior_optab, DImode, "__orll"); 8464 set_optab_libfunc (xor_optab, DImode, "__xorll"); 8465 set_optab_libfunc (one_cmpl_optab, DImode, "__notll"); 8466 8467 set_optab_libfunc (add_optab, SFmode, "__addf"); 8468 set_optab_libfunc (sub_optab, SFmode, "__subf"); 8469 set_optab_libfunc (smul_optab, SFmode, "__mulf"); 8470 set_optab_libfunc (sdiv_optab, SFmode, "__divf"); 8471 8472 set_optab_libfunc (add_optab, DFmode, "__addd"); 8473 set_optab_libfunc (sub_optab, DFmode, "__subd"); 8474 set_optab_libfunc (smul_optab, DFmode, "__muld"); 8475 set_optab_libfunc (sdiv_optab, DFmode, "__divd"); 8476 8477 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod"); 8478 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof"); 8479 8480 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi"); 8481 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); 8482 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi"); 8483 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); 8484 8485 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui"); 8486 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); 8487 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui"); 8488 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); 8489 8490 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof"); 8491 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof"); 8492 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod"); 8493 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod"); 8494 } 8495 8496 /* Convert an integer constant to an accumulator register. ICODE is the 8497 code of the target instruction, OPNUM is the number of the 8498 accumulator operand and OPVAL is the constant integer. Try both 8499 ACC and ACCG registers; only report an error if neither fit the 8500 instruction. */ 8501 8502 static rtx 8503 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval) 8504 { 8505 rtx reg; 8506 int i; 8507 8508 /* ACCs and ACCGs are implicit global registers if media intrinsics 8509 are being used. We set up this lazily to avoid creating lots of 8510 unnecessary call_insn rtl in non-media code. */ 8511 for (i = 0; i <= ACC_MASK; i++) 8512 if ((i & ACC_MASK) == i) 8513 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1; 8514 8515 if (GET_CODE (opval) != CONST_INT) 8516 { 8517 error ("accumulator is not a constant integer"); 8518 return NULL_RTX; 8519 } 8520 if ((INTVAL (opval) & ~ACC_MASK) != 0) 8521 { 8522 error ("accumulator number is out of bounds"); 8523 return NULL_RTX; 8524 } 8525 8526 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode, 8527 ACC_FIRST + INTVAL (opval)); 8528 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) 8529 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval)); 8530 8531 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) 8532 { 8533 error ("inappropriate accumulator for %qs", insn_data[icode].name); 8534 return NULL_RTX; 8535 } 8536 return reg; 8537 } 8538 8539 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG 8540 should have. */ 8541 8542 static machine_mode 8543 frv_matching_accg_mode (machine_mode mode) 8544 { 8545 switch (mode) 8546 { 8547 case E_V4SImode: 8548 return V4QImode; 8549 8550 case E_DImode: 8551 return HImode; 8552 8553 case E_SImode: 8554 return QImode; 8555 8556 default: 8557 gcc_unreachable (); 8558 } 8559 } 8560 8561 /* Given that a __builtin_read or __builtin_write function is accessing 8562 address ADDRESS, return the value that should be used as operand 1 8563 of the membar. */ 8564 8565 static rtx 8566 frv_io_address_cookie (rtx address) 8567 { 8568 return (GET_CODE (address) == CONST_INT 8569 ? GEN_INT (INTVAL (address) / 8 * 8) 8570 : const0_rtx); 8571 } 8572 8573 /* Return the accumulator guard that should be paired with accumulator 8574 register ACC. The mode of the returned register is in the same 8575 class as ACC, but is four times smaller. */ 8576 8577 rtx 8578 frv_matching_accg_for_acc (rtx acc) 8579 { 8580 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)), 8581 REGNO (acc) - ACC_FIRST + ACCG_FIRST); 8582 } 8583 8584 /* Read the requested argument from the call EXP given by INDEX. 8585 Return the value as an rtx. */ 8586 8587 static rtx 8588 frv_read_argument (tree exp, unsigned int index) 8589 { 8590 return expand_normal (CALL_EXPR_ARG (exp, index)); 8591 } 8592 8593 /* Like frv_read_argument, but interpret the argument as the number 8594 of an IACC register and return a (reg:MODE ...) rtx for it. */ 8595 8596 static rtx 8597 frv_read_iacc_argument (machine_mode mode, tree call, 8598 unsigned int index) 8599 { 8600 int i, regno; 8601 rtx op; 8602 8603 op = frv_read_argument (call, index); 8604 if (GET_CODE (op) != CONST_INT 8605 || INTVAL (op) < 0 8606 || INTVAL (op) > IACC_LAST - IACC_FIRST 8607 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0) 8608 { 8609 error ("invalid IACC argument"); 8610 op = const0_rtx; 8611 } 8612 8613 /* IACCs are implicit global registers. We set up this lazily to 8614 avoid creating lots of unnecessary call_insn rtl when IACCs aren't 8615 being used. */ 8616 regno = INTVAL (op) + IACC_FIRST; 8617 for (i = 0; i < hard_regno_nregs (regno, mode); i++) 8618 global_regs[regno + i] = 1; 8619 8620 return gen_rtx_REG (mode, regno); 8621 } 8622 8623 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE. 8624 The instruction should require a constant operand of some sort. The 8625 function prints an error if OPVAL is not valid. */ 8626 8627 static int 8628 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval) 8629 { 8630 if (GET_CODE (opval) != CONST_INT) 8631 { 8632 error ("%qs expects a constant argument", insn_data[icode].name); 8633 return FALSE; 8634 } 8635 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode)) 8636 { 8637 error ("constant argument out of range for %qs", insn_data[icode].name); 8638 return FALSE; 8639 } 8640 return TRUE; 8641 } 8642 8643 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET 8644 if it's not null, has the right mode, and satisfies operand 0's 8645 predicate. */ 8646 8647 static rtx 8648 frv_legitimize_target (enum insn_code icode, rtx target) 8649 { 8650 machine_mode mode = insn_data[icode].operand[0].mode; 8651 8652 if (! target 8653 || GET_MODE (target) != mode 8654 || ! (*insn_data[icode].operand[0].predicate) (target, mode)) 8655 return gen_reg_rtx (mode); 8656 else 8657 return target; 8658 } 8659 8660 /* Given that ARG is being passed as operand OPNUM to instruction ICODE, 8661 check whether ARG satisfies the operand's constraints. If it doesn't, 8662 copy ARG to a temporary register and return that. Otherwise return ARG 8663 itself. */ 8664 8665 static rtx 8666 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg) 8667 { 8668 machine_mode mode = insn_data[icode].operand[opnum].mode; 8669 8670 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode)) 8671 return arg; 8672 else 8673 return copy_to_mode_reg (mode, arg); 8674 } 8675 8676 /* Return a volatile memory reference of mode MODE whose address is ARG. */ 8677 8678 static rtx 8679 frv_volatile_memref (machine_mode mode, rtx arg) 8680 { 8681 rtx mem; 8682 8683 mem = gen_rtx_MEM (mode, memory_address (mode, arg)); 8684 MEM_VOLATILE_P (mem) = 1; 8685 return mem; 8686 } 8687 8688 /* Expand builtins that take a single, constant argument. At the moment, 8689 only MHDSETS falls into this category. */ 8690 8691 static rtx 8692 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target) 8693 { 8694 rtx pat; 8695 rtx op0 = frv_read_argument (call, 0); 8696 8697 if (! frv_check_constant_argument (icode, 1, op0)) 8698 return NULL_RTX; 8699 8700 target = frv_legitimize_target (icode, target); 8701 pat = GEN_FCN (icode) (target, op0); 8702 if (! pat) 8703 return NULL_RTX; 8704 8705 emit_insn (pat); 8706 return target; 8707 } 8708 8709 /* Expand builtins that take one operand. */ 8710 8711 static rtx 8712 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target) 8713 { 8714 rtx pat; 8715 rtx op0 = frv_read_argument (call, 0); 8716 8717 target = frv_legitimize_target (icode, target); 8718 op0 = frv_legitimize_argument (icode, 1, op0); 8719 pat = GEN_FCN (icode) (target, op0); 8720 if (! pat) 8721 return NULL_RTX; 8722 8723 emit_insn (pat); 8724 return target; 8725 } 8726 8727 /* Expand builtins that take two operands. */ 8728 8729 static rtx 8730 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target) 8731 { 8732 rtx pat; 8733 rtx op0 = frv_read_argument (call, 0); 8734 rtx op1 = frv_read_argument (call, 1); 8735 8736 target = frv_legitimize_target (icode, target); 8737 op0 = frv_legitimize_argument (icode, 1, op0); 8738 op1 = frv_legitimize_argument (icode, 2, op1); 8739 pat = GEN_FCN (icode) (target, op0, op1); 8740 if (! pat) 8741 return NULL_RTX; 8742 8743 emit_insn (pat); 8744 return target; 8745 } 8746 8747 /* Expand cut-style builtins, which take two operands and an implicit ACCG 8748 one. */ 8749 8750 static rtx 8751 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target) 8752 { 8753 rtx pat; 8754 rtx op0 = frv_read_argument (call, 0); 8755 rtx op1 = frv_read_argument (call, 1); 8756 rtx op2; 8757 8758 target = frv_legitimize_target (icode, target); 8759 op0 = frv_int_to_acc (icode, 1, op0); 8760 if (! op0) 8761 return NULL_RTX; 8762 8763 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT) 8764 { 8765 if (! frv_check_constant_argument (icode, 2, op1)) 8766 return NULL_RTX; 8767 } 8768 else 8769 op1 = frv_legitimize_argument (icode, 2, op1); 8770 8771 op2 = frv_matching_accg_for_acc (op0); 8772 pat = GEN_FCN (icode) (target, op0, op1, op2); 8773 if (! pat) 8774 return NULL_RTX; 8775 8776 emit_insn (pat); 8777 return target; 8778 } 8779 8780 /* Expand builtins that take two operands and the second is immediate. */ 8781 8782 static rtx 8783 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target) 8784 { 8785 rtx pat; 8786 rtx op0 = frv_read_argument (call, 0); 8787 rtx op1 = frv_read_argument (call, 1); 8788 8789 if (! frv_check_constant_argument (icode, 2, op1)) 8790 return NULL_RTX; 8791 8792 target = frv_legitimize_target (icode, target); 8793 op0 = frv_legitimize_argument (icode, 1, op0); 8794 pat = GEN_FCN (icode) (target, op0, op1); 8795 if (! pat) 8796 return NULL_RTX; 8797 8798 emit_insn (pat); 8799 return target; 8800 } 8801 8802 /* Expand builtins that take two operands, the first operand being a pointer to 8803 ints and return void. */ 8804 8805 static rtx 8806 frv_expand_voidbinop_builtin (enum insn_code icode, tree call) 8807 { 8808 rtx pat; 8809 rtx op0 = frv_read_argument (call, 0); 8810 rtx op1 = frv_read_argument (call, 1); 8811 machine_mode mode0 = insn_data[icode].operand[0].mode; 8812 rtx addr; 8813 8814 if (GET_CODE (op0) != MEM) 8815 { 8816 rtx reg = op0; 8817 8818 if (! offsettable_address_p (0, mode0, op0)) 8819 { 8820 reg = gen_reg_rtx (Pmode); 8821 emit_insn (gen_rtx_SET (reg, op0)); 8822 } 8823 8824 op0 = gen_rtx_MEM (SImode, reg); 8825 } 8826 8827 addr = XEXP (op0, 0); 8828 if (! offsettable_address_p (0, mode0, addr)) 8829 addr = copy_to_mode_reg (Pmode, op0); 8830 8831 op0 = change_address (op0, V4SImode, addr); 8832 op1 = frv_legitimize_argument (icode, 1, op1); 8833 pat = GEN_FCN (icode) (op0, op1); 8834 if (! pat) 8835 return 0; 8836 8837 emit_insn (pat); 8838 return 0; 8839 } 8840 8841 /* Expand builtins that take two long operands and return void. */ 8842 8843 static rtx 8844 frv_expand_int_void2arg (enum insn_code icode, tree call) 8845 { 8846 rtx pat; 8847 rtx op0 = frv_read_argument (call, 0); 8848 rtx op1 = frv_read_argument (call, 1); 8849 8850 op0 = frv_legitimize_argument (icode, 1, op0); 8851 op1 = frv_legitimize_argument (icode, 1, op1); 8852 pat = GEN_FCN (icode) (op0, op1); 8853 if (! pat) 8854 return NULL_RTX; 8855 8856 emit_insn (pat); 8857 return NULL_RTX; 8858 } 8859 8860 /* Expand prefetch builtins. These take a single address as argument. */ 8861 8862 static rtx 8863 frv_expand_prefetches (enum insn_code icode, tree call) 8864 { 8865 rtx pat; 8866 rtx op0 = frv_read_argument (call, 0); 8867 8868 pat = GEN_FCN (icode) (force_reg (Pmode, op0)); 8869 if (! pat) 8870 return 0; 8871 8872 emit_insn (pat); 8873 return 0; 8874 } 8875 8876 /* Expand builtins that take three operands and return void. The first 8877 argument must be a constant that describes a pair or quad accumulators. A 8878 fourth argument is created that is the accumulator guard register that 8879 corresponds to the accumulator. */ 8880 8881 static rtx 8882 frv_expand_voidtriop_builtin (enum insn_code icode, tree call) 8883 { 8884 rtx pat; 8885 rtx op0 = frv_read_argument (call, 0); 8886 rtx op1 = frv_read_argument (call, 1); 8887 rtx op2 = frv_read_argument (call, 2); 8888 rtx op3; 8889 8890 op0 = frv_int_to_acc (icode, 0, op0); 8891 if (! op0) 8892 return NULL_RTX; 8893 8894 op1 = frv_legitimize_argument (icode, 1, op1); 8895 op2 = frv_legitimize_argument (icode, 2, op2); 8896 op3 = frv_matching_accg_for_acc (op0); 8897 pat = GEN_FCN (icode) (op0, op1, op2, op3); 8898 if (! pat) 8899 return NULL_RTX; 8900 8901 emit_insn (pat); 8902 return NULL_RTX; 8903 } 8904 8905 /* Expand builtins that perform accumulator-to-accumulator operations. 8906 These builtins take two accumulator numbers as argument and return 8907 void. */ 8908 8909 static rtx 8910 frv_expand_voidaccop_builtin (enum insn_code icode, tree call) 8911 { 8912 rtx pat; 8913 rtx op0 = frv_read_argument (call, 0); 8914 rtx op1 = frv_read_argument (call, 1); 8915 rtx op2; 8916 rtx op3; 8917 8918 op0 = frv_int_to_acc (icode, 0, op0); 8919 if (! op0) 8920 return NULL_RTX; 8921 8922 op1 = frv_int_to_acc (icode, 1, op1); 8923 if (! op1) 8924 return NULL_RTX; 8925 8926 op2 = frv_matching_accg_for_acc (op0); 8927 op3 = frv_matching_accg_for_acc (op1); 8928 pat = GEN_FCN (icode) (op0, op1, op2, op3); 8929 if (! pat) 8930 return NULL_RTX; 8931 8932 emit_insn (pat); 8933 return NULL_RTX; 8934 } 8935 8936 /* Expand a __builtin_read* function. ICODE is the instruction code for the 8937 membar and TARGET_MODE is the mode that the loaded value should have. */ 8938 8939 static rtx 8940 frv_expand_load_builtin (enum insn_code icode, machine_mode target_mode, 8941 tree call, rtx target) 8942 { 8943 rtx op0 = frv_read_argument (call, 0); 8944 rtx cookie = frv_io_address_cookie (op0); 8945 8946 if (target == 0 || !REG_P (target)) 8947 target = gen_reg_rtx (target_mode); 8948 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0); 8949 convert_move (target, op0, 1); 8950 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ))); 8951 cfun->machine->has_membar_p = 1; 8952 return target; 8953 } 8954 8955 /* Likewise __builtin_write* functions. */ 8956 8957 static rtx 8958 frv_expand_store_builtin (enum insn_code icode, tree call) 8959 { 8960 rtx op0 = frv_read_argument (call, 0); 8961 rtx op1 = frv_read_argument (call, 1); 8962 rtx cookie = frv_io_address_cookie (op0); 8963 8964 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0); 8965 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1); 8966 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE))); 8967 cfun->machine->has_membar_p = 1; 8968 return NULL_RTX; 8969 } 8970 8971 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and 8972 each argument forms one word of the two double-word input registers. 8973 CALL is the tree for the call and TARGET, if nonnull, suggests a good place 8974 to put the return value. */ 8975 8976 static rtx 8977 frv_expand_mdpackh_builtin (tree call, rtx target) 8978 { 8979 enum insn_code icode = CODE_FOR_mdpackh; 8980 rtx pat, op0, op1; 8981 rtx arg1 = frv_read_argument (call, 0); 8982 rtx arg2 = frv_read_argument (call, 1); 8983 rtx arg3 = frv_read_argument (call, 2); 8984 rtx arg4 = frv_read_argument (call, 3); 8985 8986 target = frv_legitimize_target (icode, target); 8987 op0 = gen_reg_rtx (DImode); 8988 op1 = gen_reg_rtx (DImode); 8989 8990 /* The high half of each word is not explicitly initialized, so indicate 8991 that the input operands are not live before this point. */ 8992 emit_clobber (op0); 8993 emit_clobber (op1); 8994 8995 /* Move each argument into the low half of its associated input word. */ 8996 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1); 8997 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2); 8998 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3); 8999 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4); 9000 9001 pat = GEN_FCN (icode) (target, op0, op1); 9002 if (! pat) 9003 return NULL_RTX; 9004 9005 emit_insn (pat); 9006 return target; 9007 } 9008 9009 /* Expand the MCLRACC builtin. This builtin takes a single accumulator 9010 number as argument. */ 9011 9012 static rtx 9013 frv_expand_mclracc_builtin (tree call) 9014 { 9015 enum insn_code icode = CODE_FOR_mclracc; 9016 rtx pat; 9017 rtx op0 = frv_read_argument (call, 0); 9018 9019 op0 = frv_int_to_acc (icode, 0, op0); 9020 if (! op0) 9021 return NULL_RTX; 9022 9023 pat = GEN_FCN (icode) (op0); 9024 if (pat) 9025 emit_insn (pat); 9026 9027 return NULL_RTX; 9028 } 9029 9030 /* Expand builtins that take no arguments. */ 9031 9032 static rtx 9033 frv_expand_noargs_builtin (enum insn_code icode) 9034 { 9035 rtx pat = GEN_FCN (icode) (const0_rtx); 9036 if (pat) 9037 emit_insn (pat); 9038 9039 return NULL_RTX; 9040 } 9041 9042 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator 9043 number or accumulator guard number as argument and return an SI integer. */ 9044 9045 static rtx 9046 frv_expand_mrdacc_builtin (enum insn_code icode, tree call) 9047 { 9048 rtx pat; 9049 rtx target = gen_reg_rtx (SImode); 9050 rtx op0 = frv_read_argument (call, 0); 9051 9052 op0 = frv_int_to_acc (icode, 1, op0); 9053 if (! op0) 9054 return NULL_RTX; 9055 9056 pat = GEN_FCN (icode) (target, op0); 9057 if (! pat) 9058 return NULL_RTX; 9059 9060 emit_insn (pat); 9061 return target; 9062 } 9063 9064 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or 9065 accumulator guard as their first argument and an SImode value as their 9066 second. */ 9067 9068 static rtx 9069 frv_expand_mwtacc_builtin (enum insn_code icode, tree call) 9070 { 9071 rtx pat; 9072 rtx op0 = frv_read_argument (call, 0); 9073 rtx op1 = frv_read_argument (call, 1); 9074 9075 op0 = frv_int_to_acc (icode, 0, op0); 9076 if (! op0) 9077 return NULL_RTX; 9078 9079 op1 = frv_legitimize_argument (icode, 1, op1); 9080 pat = GEN_FCN (icode) (op0, op1); 9081 if (pat) 9082 emit_insn (pat); 9083 9084 return NULL_RTX; 9085 } 9086 9087 /* Emit a move from SRC to DEST in SImode chunks. This can be used 9088 to move DImode values into and out of IACC0. */ 9089 9090 static void 9091 frv_split_iacc_move (rtx dest, rtx src) 9092 { 9093 machine_mode inner; 9094 int i; 9095 9096 inner = GET_MODE (dest); 9097 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode)) 9098 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i), 9099 simplify_gen_subreg (SImode, src, inner, i)); 9100 } 9101 9102 /* Expand builtins. */ 9103 9104 static rtx 9105 frv_expand_builtin (tree exp, 9106 rtx target, 9107 rtx subtarget ATTRIBUTE_UNUSED, 9108 machine_mode mode ATTRIBUTE_UNUSED, 9109 int ignore ATTRIBUTE_UNUSED) 9110 { 9111 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 9112 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl); 9113 unsigned i; 9114 struct builtin_description *d; 9115 9116 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA) 9117 { 9118 error ("media functions are not available unless %<-mmedia%> is used"); 9119 return NULL_RTX; 9120 } 9121 9122 switch (fcode) 9123 { 9124 case FRV_BUILTIN_MCOP1: 9125 case FRV_BUILTIN_MCOP2: 9126 case FRV_BUILTIN_MDUNPACKH: 9127 case FRV_BUILTIN_MBTOHE: 9128 if (! TARGET_MEDIA_REV1) 9129 { 9130 error ("this media function is only available on the fr500"); 9131 return NULL_RTX; 9132 } 9133 break; 9134 9135 case FRV_BUILTIN_MQXMACHS: 9136 case FRV_BUILTIN_MQXMACXHS: 9137 case FRV_BUILTIN_MQMACXHS: 9138 case FRV_BUILTIN_MADDACCS: 9139 case FRV_BUILTIN_MSUBACCS: 9140 case FRV_BUILTIN_MASACCS: 9141 case FRV_BUILTIN_MDADDACCS: 9142 case FRV_BUILTIN_MDSUBACCS: 9143 case FRV_BUILTIN_MDASACCS: 9144 case FRV_BUILTIN_MABSHS: 9145 case FRV_BUILTIN_MDROTLI: 9146 case FRV_BUILTIN_MCPLHI: 9147 case FRV_BUILTIN_MCPLI: 9148 case FRV_BUILTIN_MDCUTSSI: 9149 case FRV_BUILTIN_MQSATHS: 9150 case FRV_BUILTIN_MHSETLOS: 9151 case FRV_BUILTIN_MHSETLOH: 9152 case FRV_BUILTIN_MHSETHIS: 9153 case FRV_BUILTIN_MHSETHIH: 9154 case FRV_BUILTIN_MHDSETS: 9155 case FRV_BUILTIN_MHDSETH: 9156 if (! TARGET_MEDIA_REV2) 9157 { 9158 error ("this media function is only available on the fr400" 9159 " and fr550"); 9160 return NULL_RTX; 9161 } 9162 break; 9163 9164 case FRV_BUILTIN_SMASS: 9165 case FRV_BUILTIN_SMSSS: 9166 case FRV_BUILTIN_SMU: 9167 case FRV_BUILTIN_ADDSS: 9168 case FRV_BUILTIN_SUBSS: 9169 case FRV_BUILTIN_SLASS: 9170 case FRV_BUILTIN_SCUTSS: 9171 case FRV_BUILTIN_IACCreadll: 9172 case FRV_BUILTIN_IACCreadl: 9173 case FRV_BUILTIN_IACCsetll: 9174 case FRV_BUILTIN_IACCsetl: 9175 if (!TARGET_FR405_BUILTINS) 9176 { 9177 error ("this builtin function is only available" 9178 " on the fr405 and fr450"); 9179 return NULL_RTX; 9180 } 9181 break; 9182 9183 case FRV_BUILTIN_PREFETCH: 9184 if (!TARGET_FR500_FR550_BUILTINS) 9185 { 9186 error ("this builtin function is only available on the fr500" 9187 " and fr550"); 9188 return NULL_RTX; 9189 } 9190 break; 9191 9192 case FRV_BUILTIN_MQLCLRHS: 9193 case FRV_BUILTIN_MQLMTHS: 9194 case FRV_BUILTIN_MQSLLHI: 9195 case FRV_BUILTIN_MQSRAHI: 9196 if (!TARGET_MEDIA_FR450) 9197 { 9198 error ("this builtin function is only available on the fr450"); 9199 return NULL_RTX; 9200 } 9201 break; 9202 9203 default: 9204 break; 9205 } 9206 9207 /* Expand unique builtins. */ 9208 9209 switch (fcode) 9210 { 9211 case FRV_BUILTIN_MTRAP: 9212 return frv_expand_noargs_builtin (CODE_FOR_mtrap); 9213 9214 case FRV_BUILTIN_MCLRACC: 9215 return frv_expand_mclracc_builtin (exp); 9216 9217 case FRV_BUILTIN_MCLRACCA: 9218 if (TARGET_ACC_8) 9219 return frv_expand_noargs_builtin (CODE_FOR_mclracca8); 9220 else 9221 return frv_expand_noargs_builtin (CODE_FOR_mclracca4); 9222 9223 case FRV_BUILTIN_MRDACC: 9224 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp); 9225 9226 case FRV_BUILTIN_MRDACCG: 9227 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp); 9228 9229 case FRV_BUILTIN_MWTACC: 9230 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp); 9231 9232 case FRV_BUILTIN_MWTACCG: 9233 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp); 9234 9235 case FRV_BUILTIN_MDPACKH: 9236 return frv_expand_mdpackh_builtin (exp, target); 9237 9238 case FRV_BUILTIN_IACCreadll: 9239 { 9240 rtx src = frv_read_iacc_argument (DImode, exp, 0); 9241 if (target == 0 || !REG_P (target)) 9242 target = gen_reg_rtx (DImode); 9243 frv_split_iacc_move (target, src); 9244 return target; 9245 } 9246 9247 case FRV_BUILTIN_IACCreadl: 9248 return frv_read_iacc_argument (SImode, exp, 0); 9249 9250 case FRV_BUILTIN_IACCsetll: 9251 { 9252 rtx dest = frv_read_iacc_argument (DImode, exp, 0); 9253 rtx src = frv_read_argument (exp, 1); 9254 frv_split_iacc_move (dest, force_reg (DImode, src)); 9255 return 0; 9256 } 9257 9258 case FRV_BUILTIN_IACCsetl: 9259 { 9260 rtx dest = frv_read_iacc_argument (SImode, exp, 0); 9261 rtx src = frv_read_argument (exp, 1); 9262 emit_move_insn (dest, force_reg (SImode, src)); 9263 return 0; 9264 } 9265 9266 default: 9267 break; 9268 } 9269 9270 /* Expand groups of builtins. */ 9271 9272 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++) 9273 if (d->code == fcode) 9274 return frv_expand_set_builtin (d->icode, exp, target); 9275 9276 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) 9277 if (d->code == fcode) 9278 return frv_expand_unop_builtin (d->icode, exp, target); 9279 9280 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) 9281 if (d->code == fcode) 9282 return frv_expand_binop_builtin (d->icode, exp, target); 9283 9284 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++) 9285 if (d->code == fcode) 9286 return frv_expand_cut_builtin (d->icode, exp, target); 9287 9288 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++) 9289 if (d->code == fcode) 9290 return frv_expand_binopimm_builtin (d->icode, exp, target); 9291 9292 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++) 9293 if (d->code == fcode) 9294 return frv_expand_voidbinop_builtin (d->icode, exp); 9295 9296 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++) 9297 if (d->code == fcode) 9298 return frv_expand_voidtriop_builtin (d->icode, exp); 9299 9300 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++) 9301 if (d->code == fcode) 9302 return frv_expand_voidaccop_builtin (d->icode, exp); 9303 9304 for (i = 0, d = bdesc_int_void2arg; 9305 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++) 9306 if (d->code == fcode) 9307 return frv_expand_int_void2arg (d->icode, exp); 9308 9309 for (i = 0, d = bdesc_prefetches; 9310 i < ARRAY_SIZE (bdesc_prefetches); i++, d++) 9311 if (d->code == fcode) 9312 return frv_expand_prefetches (d->icode, exp); 9313 9314 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++) 9315 if (d->code == fcode) 9316 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)), 9317 exp, target); 9318 9319 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++) 9320 if (d->code == fcode) 9321 return frv_expand_store_builtin (d->icode, exp); 9322 9323 return 0; 9324 } 9325 9326 static bool 9327 frv_in_small_data_p (const_tree decl) 9328 { 9329 HOST_WIDE_INT size; 9330 const char *section_name; 9331 9332 /* Don't apply the -G flag to internal compiler structures. We 9333 should leave such structures in the main data section, partly 9334 for efficiency and partly because the size of some of them 9335 (such as C++ typeinfos) is not known until later. */ 9336 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl)) 9337 return false; 9338 9339 /* If we already know which section the decl should be in, see if 9340 it's a small data section. */ 9341 section_name = DECL_SECTION_NAME (decl); 9342 if (section_name) 9343 { 9344 if (frv_string_begins_with (section_name, ".sdata")) 9345 return true; 9346 if (frv_string_begins_with (section_name, ".sbss")) 9347 return true; 9348 return false; 9349 } 9350 9351 size = int_size_in_bytes (TREE_TYPE (decl)); 9352 if (size > 0 && size <= g_switch_value) 9353 return true; 9354 9355 return false; 9356 } 9357 9358 static bool 9359 frv_rtx_costs (rtx x, 9360 machine_mode mode, 9361 int outer_code, 9362 int opno ATTRIBUTE_UNUSED, 9363 int *total, 9364 bool speed ATTRIBUTE_UNUSED) 9365 { 9366 int code = GET_CODE (x); 9367 9368 if (outer_code == MEM) 9369 { 9370 /* Don't differentiate between memory addresses. All the ones 9371 we accept have equal cost. */ 9372 *total = COSTS_N_INSNS (0); 9373 return true; 9374 } 9375 9376 switch (code) 9377 { 9378 case CONST_INT: 9379 /* Make 12-bit integers really cheap. */ 9380 if (IN_RANGE (INTVAL (x), -2048, 2047)) 9381 { 9382 *total = 0; 9383 return true; 9384 } 9385 /* Fall through. */ 9386 9387 case CONST: 9388 case LABEL_REF: 9389 case SYMBOL_REF: 9390 case CONST_DOUBLE: 9391 *total = COSTS_N_INSNS (2); 9392 return true; 9393 9394 case PLUS: 9395 case MINUS: 9396 case AND: 9397 case IOR: 9398 case XOR: 9399 case ASHIFT: 9400 case ASHIFTRT: 9401 case LSHIFTRT: 9402 case NOT: 9403 case NEG: 9404 case COMPARE: 9405 if (mode == SImode) 9406 *total = COSTS_N_INSNS (1); 9407 else if (mode == DImode) 9408 *total = COSTS_N_INSNS (2); 9409 else 9410 *total = COSTS_N_INSNS (3); 9411 return true; 9412 9413 case MULT: 9414 if (mode == SImode) 9415 *total = COSTS_N_INSNS (2); 9416 else 9417 *total = COSTS_N_INSNS (6); /* guess */ 9418 return true; 9419 9420 case DIV: 9421 case UDIV: 9422 case MOD: 9423 case UMOD: 9424 *total = COSTS_N_INSNS (18); 9425 return true; 9426 9427 case MEM: 9428 *total = COSTS_N_INSNS (3); 9429 return true; 9430 9431 default: 9432 return false; 9433 } 9434 } 9435 9436 static void 9437 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) 9438 { 9439 switch_to_section (ctors_section); 9440 assemble_align (POINTER_SIZE); 9441 if (TARGET_FDPIC) 9442 { 9443 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); 9444 9445 gcc_assert (ok); 9446 return; 9447 } 9448 assemble_integer_with_op ("\t.picptr\t", symbol); 9449 } 9450 9451 static void 9452 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) 9453 { 9454 switch_to_section (dtors_section); 9455 assemble_align (POINTER_SIZE); 9456 if (TARGET_FDPIC) 9457 { 9458 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); 9459 9460 gcc_assert (ok); 9461 return; 9462 } 9463 assemble_integer_with_op ("\t.picptr\t", symbol); 9464 } 9465 9466 /* Worker function for TARGET_STRUCT_VALUE_RTX. */ 9467 9468 static rtx 9469 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, 9470 int incoming ATTRIBUTE_UNUSED) 9471 { 9472 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM); 9473 } 9474 9475 #define TLS_BIAS (2048 - 16) 9476 9477 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. 9478 We need to emit DTP-relative relocations. */ 9479 9480 static void 9481 frv_output_dwarf_dtprel (FILE *file, int size, rtx x) 9482 { 9483 gcc_assert (size == 4); 9484 fputs ("\t.picptr\ttlsmoff(", file); 9485 /* We want the unbiased TLS offset, so add the bias to the 9486 expression, such that the implicit biasing cancels out. */ 9487 output_addr_const (file, plus_constant (Pmode, x, TLS_BIAS)); 9488 fputs (")", file); 9489 } 9490 9491 #include "gt-frv.h" 9492