1 /* Definitions of target machine for GNU compiler, Argonaut EPIPHANY cpu. 2 Copyright (C) 1994-2017 Free Software Foundation, Inc. 3 Contributed by Embecosm on behalf of Adapteva, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #ifndef GCC_EPIPHANY_H 22 #define GCC_EPIPHANY_H 23 24 #undef LINK_SPEC 25 #undef STARTFILE_SPEC 26 #undef ENDFILE_SPEC 27 #undef SIZE_TYPE 28 #undef PTRDIFF_TYPE 29 #undef WCHAR_TYPE 30 #undef WCHAR_TYPE_SIZE 31 32 /* Names to predefine in the preprocessor for this target machine. */ 33 #define TARGET_CPU_CPP_BUILTINS() \ 34 do \ 35 { \ 36 builtin_define ("__epiphany__"); \ 37 builtin_define ("__little_endian__"); \ 38 builtin_define_with_int_value ("__EPIPHANY_STACK_OFFSET__", \ 39 epiphany_stack_offset); \ 40 builtin_assert ("cpu=epiphany"); \ 41 builtin_assert ("machine=epiphany"); \ 42 } while (0) 43 44 /* Pick up the libgloss library. One day we may do this by linker script, but 45 for now its static. 46 libgloss might use errno/__errno, which might not have been needed when we 47 saw libc the first time, so link with libc a second time. */ 48 #undef LIB_SPEC 49 #define LIB_SPEC "%{!shared:%{g*:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}} -lepiphany %{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" 50 51 #define LINK_SPEC "%{v}" 52 53 #define STARTFILE_SPEC "%{!shared:crt0.o%s} crti.o%s " \ 54 "%{mfp-mode=int:crtint.o%s} %{mfp-mode=truncate:crtrunc.o%s} " \ 55 "%{m1reg-r43:crtm1reg-r43.o%s} %{m1reg-r63:crtm1reg-r63.o%s} " \ 56 "crtbegin.o%s" 57 58 #define ENDFILE_SPEC "crtend.o%s crtn.o%s" 59 60 #define EPIPHANY_LIBRARY_EXTRA_SPEC \ 61 "-ffixed-r40 -ffixed-r41 -ffixed-r42 -ffixed-r43" 62 63 /* In the "spec:" rule,, t-epiphany changes this to epiphany_library_stub_spec 64 and epiphany_library_extra_spec, respectively. */ 65 #define EXTRA_SPECS \ 66 { "epiphany_library_extra_spec", "" }, \ 67 { "epiphany_library_build_spec", EPIPHANY_LIBRARY_EXTRA_SPEC }, \ 68 69 #define DRIVER_SELF_SPECS " %(epiphany_library_extra_spec) " 70 71 #undef USER_LABEL_PREFIX 72 #define USER_LABEL_PREFIX "_" 73 74 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 75 asm (SECTION_OP "\n\ 76 mov r0,%low(" USER_LABEL_PREFIX #FUNC")\n\ 77 movt r0,%high(" USER_LABEL_PREFIX #FUNC")\n\ 78 jalr r0\n\ 79 .text"); 80 81 #if 0 /* We would like to use Posix for profiling, but the simulator 82 interface still lacks mkdir. */ 83 #define TARGET_POSIX_IO 84 #endif 85 86 /* Target machine storage layout. */ 87 88 /* Define this if most significant bit is lowest numbered 89 in instructions that operate on numbered bit-fields. */ 90 #define BITS_BIG_ENDIAN 0 91 92 /* Define this if most significant byte of a word is the lowest numbered. */ 93 #define BYTES_BIG_ENDIAN 0 94 95 /* Define this if most significant word of a multiword number is the lowest 96 numbered. */ 97 #define WORDS_BIG_ENDIAN 0 98 99 /* Width of a word, in units (bytes). */ 100 #define UNITS_PER_WORD 4 101 102 /* Define this macro if it is advisable to hold scalars in registers 103 in a wider mode than that declared by the program. In such cases, 104 the value is constrained to be within the bounds of the declared 105 type, but kept valid in the wider mode. The signedness of the 106 extension may differ from that of the type. */ 107 /* It is far faster to zero extend chars than to sign extend them */ 108 109 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 110 if (GET_MODE_CLASS (MODE) == MODE_INT \ 111 && GET_MODE_SIZE (MODE) < 4) \ 112 { \ 113 if (MODE == QImode) \ 114 UNSIGNEDP = 1; \ 115 else if (MODE == HImode) \ 116 UNSIGNEDP = 1; \ 117 (MODE) = SImode; \ 118 } 119 120 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 121 #define PARM_BOUNDARY 32 122 123 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 124 #define STACK_BOUNDARY 64 125 126 /* ALIGN FRAMES on word boundaries */ 127 #define EPIPHANY_STACK_ALIGN(LOC) (((LOC)+7) & ~7) 128 129 /* Allocation boundary (in *bits*) for the code of a function. */ 130 #define FUNCTION_BOUNDARY 32 131 132 /* Every structure's size must be a multiple of this. */ 133 #define STRUCTURE_SIZE_BOUNDARY 8 134 135 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 136 #define PCC_BITFIELD_TYPE_MATTERS 1 137 138 /* No data type wants to be aligned rounder than this. */ 139 /* This is bigger than currently necessary for the EPIPHANY. If 8 byte floats are 140 ever added it's not clear whether they'll need such alignment or not. For 141 now we assume they will. We can always relax it if necessary but the 142 reverse isn't true. */ 143 #define BIGGEST_ALIGNMENT 64 144 145 /* The best alignment to use in cases where we have a choice. */ 146 #define FASTEST_ALIGNMENT 64 147 148 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 149 150 /* Make strings dword-aligned so strcpy from constants will be faster. */ 151 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 152 ((TREE_CODE (EXP) == STRING_CST \ 153 && (ALIGN) < FASTEST_ALIGNMENT) \ 154 ? FASTEST_ALIGNMENT : (ALIGN)) 155 156 /* Make arrays of chars dword-aligned for the same reasons. 157 Also, align arrays of SImode items. */ 158 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 159 (TREE_CODE (TYPE) == ARRAY_TYPE \ 160 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 161 && (ALIGN) < FASTEST_ALIGNMENT \ 162 ? FASTEST_ALIGNMENT \ 163 : (TREE_CODE (TYPE) == ARRAY_TYPE \ 164 && TYPE_MODE (TREE_TYPE (TYPE)) == SImode \ 165 && (ALIGN) < FASTEST_ALIGNMENT) \ 166 ? FASTEST_ALIGNMENT \ 167 : (ALIGN)) 168 169 /* Set this nonzero if move instructions will actually fail to work 170 when given unaligned data. */ 171 /* On the EPIPHANY the lower address bits are masked to 0 as necessary. The chip 172 won't croak when given an unaligned address, but the insn will still fail 173 to produce the correct result. */ 174 #define STRICT_ALIGNMENT 1 175 176 /* layout_type overrides our ADJUST_ALIGNMENT settings from epiphany-modes.def 177 for vector modes, so we have to override it back. */ 178 #define ROUND_TYPE_ALIGN(TYPE, MANGLED_ALIGN, SPECIFIED_ALIGN) \ 179 (TREE_CODE (TYPE) == VECTOR_TYPE && !TYPE_USER_ALIGN (TYPE) \ 180 && SPECIFIED_ALIGN <= GET_MODE_ALIGNMENT (TYPE_MODE (TYPE)) \ 181 ? GET_MODE_ALIGNMENT (TYPE_MODE (TYPE)) \ 182 : ((TREE_CODE (TYPE) == RECORD_TYPE \ 183 || TREE_CODE (TYPE) == UNION_TYPE \ 184 || TREE_CODE (TYPE) == QUAL_UNION_TYPE) \ 185 && !TYPE_PACKED (TYPE)) \ 186 ? epiphany_special_round_type_align ((TYPE), (MANGLED_ALIGN), \ 187 (SPECIFIED_ALIGN)) \ 188 : MAX ((MANGLED_ALIGN), (SPECIFIED_ALIGN))) 189 190 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ 191 epiphany_adjust_field_align((TYPE), (COMPUTED)) 192 193 /* Layout of source language data types. */ 194 195 #define SHORT_TYPE_SIZE 16 196 #define INT_TYPE_SIZE 32 197 #define LONG_TYPE_SIZE 32 198 #define LONG_LONG_TYPE_SIZE 64 199 #define FLOAT_TYPE_SIZE 32 200 #define DOUBLE_TYPE_SIZE 64 201 #define LONG_DOUBLE_TYPE_SIZE 64 202 203 /* Define this as 1 if `char' should by default be signed; else as 0. */ 204 #define DEFAULT_SIGNED_CHAR 0 205 206 #define SIZE_TYPE "long unsigned int" 207 #define PTRDIFF_TYPE "long int" 208 #define WCHAR_TYPE "unsigned int" 209 #define WCHAR_TYPE_SIZE BITS_PER_WORD 210 211 /* Standard register usage. */ 212 213 /* Number of actual hardware registers. 214 The hardware registers are assigned numbers for the compiler 215 from 0 to just below FIRST_PSEUDO_REGISTER. 216 All registers that the compiler knows about must be given numbers, 217 even those that are not normally considered general registers. */ 218 219 #define FIRST_PSEUDO_REGISTER 78 220 221 222 /* General purpose registers. */ 223 #define GPR_FIRST 0 /* First gpr */ 224 225 #define PIC_REGNO (GPR_FIRST + 28) /* PIC register. */ 226 #define GPR_LAST (GPR_FIRST + 63) /* Last gpr */ 227 #define CORE_CONTROL_FIRST CONFIG_REGNUM 228 #define CORE_CONTROL_LAST IRET_REGNUM 229 230 #define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST) 231 #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM) 232 233 #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) 234 #define GPR_AP_OR_PSEUDO_P(R) (GPR_OR_AP_P (R) || (R) >= FIRST_PSEUDO_REGISTER) 235 236 #define FIXED_REGISTERS \ 237 { /* Integer Registers */ \ 238 0, 0, 0, 0, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \ 239 0, 0, 0, 0, 0, 1, 0, 0, /* 008-015, gr8 - gr15 */ \ 240 0, 0, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \ 241 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ 242 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr39 */ \ 243 0, 0, 0, 0, 0, 0, 0, 0, /* 040-047, gr40 - gr47 */ \ 244 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \ 245 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \ 246 /* Other registers */ \ 247 1, /* 64 AP - fake arg ptr */ \ 248 1, /* soft frame pointer */ \ 249 1, /* CC_REGNUM - integer conditions */\ 250 1, /* CCFP_REGNUM - fp conditions */\ 251 1, 1, 1, 1, 1, 1, /* Core Control Registers. */ \ 252 1, 1, 1, /* FP_{NEAREST,...}_REGNUM */\ 253 1, /* UNKNOWN_REGNUM - placeholder. */\ 254 } 255 256 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in 257 general) by function calls as well as for fixed registers. This macro 258 therefore identifies the registers that are not available for general 259 allocation of values that must live across function calls. 260 261 If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically 262 saves it on function entry and restores it on function exit, if the register 263 is used within the function. */ 264 265 #define CALL_USED_REGISTERS \ 266 { /* Integer Registers */ \ 267 1, 1, 1, 1, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \ 268 0, 0, 0, 0, 1, 1, 1, 0, /* 008-015, gr8 - gr15 */ \ 269 1, 1, 1, 1, 1, 1, 1, 1, /* 016-023, gr16 - gr23 */ \ 270 1, 1, 1, 1, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ 271 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr38 */ \ 272 0, 0, 0, 0, 1, 1, 1, 1, /* 040-047, gr40 - gr47 */ \ 273 1, 1, 1, 1, 1, 1, 1, 1, /* 048-055, gr48 - gr55 */ \ 274 1, 1, 1, 1, 1, 1, 1, 1, /* 056-063, gr56 - gr63 */ \ 275 1, /* 64 AP - fake arg ptr */ \ 276 1, /* soft frame pointer */ \ 277 1, /* 66 CC_REGNUM */ \ 278 1, /* 67 CCFP_REGNUM */ \ 279 1, 1, 1, 1, 1, 1, /* Core Control Registers. */ \ 280 1, 1, 1, /* FP_{NEAREST,...}_REGNUM */\ 281 1, /* UNKNOWN_REGNUM - placeholder. */\ 282 } 283 284 #define REG_ALLOC_ORDER \ 285 { \ 286 0, 1, 2, 3, /* Caller-saved 'small' registers. */ \ 287 12, /* Caller-saved unpaired register. */ \ 288 /* Caller-saved registers. */ \ 289 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ 290 44, 45, 46, 47, \ 291 48, 49, 50, 51, 52, 53, 54, 55, \ 292 56, 57, 58, 59, 60, 61, 62, 63, \ 293 4, 5, 6, 7, /* Calle-saved 'small' registers. */ \ 294 15, /* Calle-saved unpaired register. */ \ 295 8, 9, 10, 11, /* Calle-saved registers. */ \ 296 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, \ 297 14, 13, /* Link register, stack pointer. */ \ 298 /* Can't allocate, but must name these... */ \ 299 28, 29, 30, 31, \ 300 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77 \ 301 } 302 303 #define HARD_REGNO_RENAME_OK(SRC, DST) epiphany_regno_rename_ok (SRC, DST) 304 305 /* Return number of consecutive hard regs needed starting at reg REGNO 306 to hold something of mode MODE. 307 This is ordinarily the length in words of a value of mode MODE 308 but can be less for certain modes in special long registers. */ 309 #define HARD_REGNO_NREGS(REGNO, MODE) \ 310 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 311 312 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 313 extern const unsigned int epiphany_hard_regno_mode_ok[]; 314 extern unsigned int epiphany_mode_class[]; 315 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) 316 317 /* A C expression that is nonzero if it is desirable to choose 318 register allocation so as to avoid move instructions between a 319 value of mode MODE1 and a value of mode MODE2. 320 321 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 322 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 323 MODE2)' must be zero. */ 324 325 #define MODES_TIEABLE_P(MODE1, MODE2) 1 326 327 /* Register classes and constants. */ 328 329 /* Define the classes of registers for register constraints in the 330 machine description. Also define ranges of constants. 331 332 One of the classes must always be named ALL_REGS and include all hard regs. 333 If there is more than one class, another class must be named NO_REGS 334 and contain no registers. 335 336 The name GENERAL_REGS must be the name of a class (or an alias for 337 another name such as ALL_REGS). This is the class of registers 338 that is allowed by "g" or "r" in a register constraint. 339 Also, registers outside this class are allocated only when 340 instructions express preferences for them. 341 342 The classes must be numbered in nondecreasing order; that is, 343 a larger-numbered class must never be contained completely 344 in a smaller-numbered class. 345 346 For any two classes, it is very desirable that there be another 347 class that represents their union. 348 349 It is important that any condition codes have class NO_REGS. 350 See `register_operand'. */ 351 352 enum reg_class { 353 NO_REGS, 354 LR_REGS, 355 SHORT_INSN_REGS, 356 SIBCALL_REGS, 357 GENERAL_REGS, 358 CORE_CONTROL_REGS, 359 ALL_REGS, 360 LIM_REG_CLASSES 361 }; 362 363 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 364 365 /* Give names of register classes as strings for dump file. */ 366 #define REG_CLASS_NAMES \ 367 { \ 368 "NO_REGS", \ 369 "LR_REGS", \ 370 "SHORT_INSN_REGS", \ 371 "SIBCALL_REGS", \ 372 "GENERAL_REGS", \ 373 "CORE_CONTROL_REGS", \ 374 "ALL_REGS" \ 375 } 376 377 /* Define which registers fit in which classes. 378 This is an initializer for a vector of HARD_REG_SET 379 of length N_REG_CLASSES. */ 380 381 #define REG_CLASS_CONTENTS \ 382 { /* r0-r31 r32-r63 ap/sfp/cc1/cc2/iret/status */ \ 383 { 0x00000000,0x00000000,0x0}, /* NO_REGS */ \ 384 { 0x00004000,0x00000000,0x0}, /* LR_REGS */ \ 385 { 0x000000ff,0x00000000,0x0}, /* SHORT_INSN_REGS */ \ 386 { 0xffff100f,0xffffff00,0x0}, /* SIBCALL_REGS */ \ 387 { 0xffffffff,0xffffffff,0x0003}, /* GENERAL_REGS */ \ 388 { 0x00000000,0x00000000,0x03f0}, /* CORE_CONTROL_REGS */ \ 389 { 0xffffffff,0xffffffff,0x3fff}, /* ALL_REGS */ \ 390 } 391 392 393 /* The same information, inverted: 394 Return the class number of the smallest class containing 395 reg number REGNO. This could be a conditional expression 396 or could index an array. */ 397 extern enum reg_class epiphany_regno_reg_class[FIRST_PSEUDO_REGISTER]; 398 #define REGNO_REG_CLASS(REGNO) \ 399 (epiphany_regno_reg_class[REGNO]) 400 401 /* The class value for index registers, and the one for base regs. */ 402 #define BASE_REG_CLASS GENERAL_REGS 403 #define INDEX_REG_CLASS GENERAL_REGS 404 405 /* These assume that REGNO is a hard or pseudo reg number. 406 They give nonzero only if REGNO is a hard reg of the suitable class 407 or a pseudo reg currently allocated to a suitable hard reg. 408 Since they use reg_renumber, they are safe only once reg_renumber 409 has been allocated, which happens in reginfo.c during register 410 allocation. */ 411 #define REGNO_OK_FOR_BASE_P(REGNO) \ 412 ((REGNO) < FIRST_PSEUDO_REGISTER || (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER) 413 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 414 ((REGNO) < FIRST_PSEUDO_REGISTER || (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER) 415 416 417 418 /* Given an rtx X being reloaded into a reg required to be 419 in class CLASS, return the class of reg to actually use. 420 In general this is just CLASS; but on some machines 421 in some cases it is preferable to use a more restrictive class. */ 422 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 423 (CLASS) 424 425 /* Return the maximum number of consecutive registers 426 needed to represent mode MODE in a register of class CLASS. */ 427 #define CLASS_MAX_NREGS(CLASS, MODE) \ 428 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 429 430 /* The letters I, J, K, L, M, N, O, P in a register constraint string 431 can be used to stand for particular ranges of immediate operands. 432 This macro defines what the ranges are. 433 C is the letter, and VALUE is a constant value. 434 Return 1 if VALUE is in the range specified by C. */ 435 436 /* 'I' is used for 16 bit unsigned. 437 'Cal' is used for long immediates (32 bits) 438 'K' is used for any constant up to 5 bits. 439 'L' is used for any 11 bit signed. 440 */ 441 442 #define IMM16(X) (IN_RANGE ((X), 0, 0xFFFF)) 443 #define SIMM16(X) (IN_RANGE ((X), -65536, 65535)) 444 #define SIMM11(X) (IN_RANGE ((X), -1024, 1023)) 445 #define IMM5(X) (IN_RANGE ((X), 0, 0x1F)) 446 447 typedef struct GTY (()) machine_function 448 { 449 unsigned args_parsed : 1; 450 unsigned pretend_args_odd : 1; 451 unsigned lr_clobbered : 1; 452 unsigned control_use_inserted : 1; 453 unsigned lr_slot_known : 1; 454 unsigned sw_entities_processed : 6; 455 long lr_slot_offset; 456 rtx and_mask; 457 rtx or_mask; 458 unsigned unknown_mode_uses; 459 unsigned unknown_mode_sets; 460 } machine_function_t; 461 462 #define MACHINE_FUNCTION(fun) (fun)->machine 463 464 #define INIT_EXPANDERS epiphany_init_expanders () 465 466 /* Stack layout and stack pointer usage. */ 467 468 /* Define this macro if pushing a word onto the stack moves the stack 469 pointer to a smaller address. */ 470 #define STACK_GROWS_DOWNWARD 1 471 472 /* Define this to nonzero if the nominal address of the stack frame 473 is at the high-address end of the local variables; 474 that is, each additional local variable allocated 475 goes at a more negative offset in the frame. */ 476 #define FRAME_GROWS_DOWNWARD 1 477 478 /* Offset within stack frame to start allocating local variables at. 479 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 480 first local allocated. Otherwise, it is the offset to the BEGINNING 481 of the first local allocated. */ 482 #define STARTING_FRAME_OFFSET epiphany_stack_offset 483 484 /* Offset from the stack pointer register to the first location at which 485 outgoing arguments are placed. */ 486 #define STACK_POINTER_OFFSET epiphany_stack_offset 487 488 /* Offset of first parameter from the argument pointer register value. */ 489 /* 4 bytes for each of previous fp, return address, and previous gp. 490 4 byte reserved area for future considerations. */ 491 #define FIRST_PARM_OFFSET(FNDECL) \ 492 (epiphany_stack_offset \ 493 + (MACHINE_FUNCTION (DECL_STRUCT_FUNCTION (FNDECL))->pretend_args_odd \ 494 ? 4 : 0)) 495 496 #define INCOMING_FRAME_SP_OFFSET epiphany_stack_offset 497 498 /* Register to use for pushing function arguments. */ 499 #define STACK_POINTER_REGNUM GPR_SP 500 501 /* Base register for access to local variables of the function. */ 502 #define HARD_FRAME_POINTER_REGNUM GPR_FP 503 504 /* Register in which static-chain is passed to a function. This must 505 not be a register used by the prologue. */ 506 #define STATIC_CHAIN_REGNUM GPR_IP 507 508 /* Define the offset between two registers, one to be eliminated, and the other 509 its replacement, at the start of a routine. */ 510 511 #define ELIMINABLE_REGS \ 512 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 513 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 514 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 515 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 516 } 517 518 /* Define the offset between two registers, one to be eliminated, and the other 519 its replacement, at the start of a routine. */ 520 521 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 522 ((OFFSET) = epiphany_initial_elimination_offset ((FROM), (TO))) 523 524 /* Function argument passing. */ 525 526 /* If defined, the maximum amount of space required for outgoing 527 arguments will be computed and placed into the variable 528 `current_function_outgoing_args_size'. No space will be pushed 529 onto the stack for each call; instead, the function prologue should 530 increase the stack frame size by this amount. */ 531 #define ACCUMULATE_OUTGOING_ARGS 1 532 533 /* Define a data type for recording info about an argument list 534 during the scan of that argument list. This data type should 535 hold all necessary information about the function itself 536 and about the args processed so far, enough to enable macros 537 such as FUNCTION_ARG to determine where the next arg should go. */ 538 #define CUMULATIVE_ARGS int 539 540 /* Initialize a variable CUM of type CUMULATIVE_ARGS 541 for a call to a function whose data type is FNTYPE. 542 For a library call, FNTYPE is 0. */ 543 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 544 ((CUM) = 0) 545 546 /* The number of registers used for parameter passing. Local to this file. */ 547 #define MAX_EPIPHANY_PARM_REGS 4 548 549 /* 1 if N is a possible register number for function argument passing. */ 550 #define FUNCTION_ARG_REGNO_P(N) \ 551 ((unsigned) (N) < MAX_EPIPHANY_PARM_REGS) 552 553 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in 554 a reg. This includes arguments that have to be passed by reference as the 555 pointer to them is passed in a reg if one is available (and that is what 556 we're given). 557 This macro is only used in this file. */ 558 /* We must use partial argument passing because of the chosen mode 559 of varargs handling. */ 560 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 561 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < MAX_EPIPHANY_PARM_REGS) 562 563 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ 564 #define DEFAULT_PCC_STRUCT_RETURN 0 565 566 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 567 the stack pointer does not matter. The value is tested only in 568 functions that have frame pointers. 569 No definition is equivalent to always zero. */ 570 #define EXIT_IGNORE_STACK 1 571 572 #define EPILOGUE_USES(REGNO) epiphany_epilogue_uses (REGNO) 573 574 /* Output assembler code to FILE to increment profiler label # LABELNO 575 for profiling a function entry. */ 576 #define FUNCTION_PROFILER(FILE, LABELNO) 577 578 /* Given an rtx for the frame pointer, 579 return an rtx for the address of the frame. */ 580 #define FRAME_ADDR_RTX(frame) \ 581 ((frame) == hard_frame_pointer_rtx ? arg_pointer_rtx : NULL) 582 583 #define EPIPHANY_RETURN_REGNO \ 584 ((current_function_decl != NULL \ 585 && epiphany_is_interrupt_p (current_function_decl)) \ 586 ? IRET_REGNUM : GPR_LR) 587 /* This is not only for dwarf unwind info, but also for the benefit of 588 df-scan.c to tell it that LR is live at the function start. */ 589 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, EPIPHANY_RETURN_REGNO) 590 591 /* However, we haven't implemented the rest needed for dwarf2 unwind info. */ 592 #define DWARF2_UNWIND_INFO 0 593 594 #define RETURN_ADDR_RTX(count, frame) \ 595 (count ? NULL_RTX \ 596 : gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), UNSPEC_RETURN_ADDR)) 597 598 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (EPIPHANY_RETURN_REGNO) 599 600 /* Trampolines. 601 An epiphany trampoline looks like this: 602 mov r16,%low(fnaddr) 603 movt r16,%high(fnaddr) 604 mov ip,%low(cxt) 605 movt ip,%high(cxt) 606 jr r16 */ 607 608 /* Length in units of the trampoline for entering a nested function. */ 609 #define TRAMPOLINE_SIZE 20 610 611 /* Addressing modes, and classification of registers for them. */ 612 613 /* Maximum number of registers that can appear in a valid memory address. */ 614 #define MAX_REGS_PER_ADDRESS 2 615 616 /* We have post_modify (load/store with update). */ 617 #define HAVE_POST_INCREMENT TARGET_POST_INC 618 #define HAVE_POST_DECREMENT TARGET_POST_INC 619 #define HAVE_POST_MODIFY_DISP TARGET_POST_MODIFY 620 #define HAVE_POST_MODIFY_REG TARGET_POST_MODIFY 621 622 /* Currently, the only users of the USE_*CREMENT macros are 623 move_by_pieces / store_by_pieces_1 . We don't want them to use 624 POST_MODIFY modes, because we got ample addressing range for the 625 reg+offset addressing mode; besides, there are short index+offset loads, 626 but the only short post-modify load uses POST_MODIFY_REG. 627 Moreover, using auto-increment in move_by_pieces from structure copying 628 in the prologue causes confused debug output. 629 If another pass starts using these macros where the use of these 630 addressing modes would make more sense, we can try checking the 631 current pass. */ 632 #define USE_LOAD_POST_INCREMENT(MODE) 0 633 #define USE_LOAD_POST_DECREMENT(MODE) 0 634 #define USE_STORE_POST_INCREMENT(MODE) 0 635 #define USE_STORE_POST_DECREMENT(MODE) 0 636 637 /* Recognize any constant value that is a valid address. */ 638 #define CONSTANT_ADDRESS_P(X) \ 639 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 640 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST) 641 642 #define RTX_OK_FOR_OFFSET_P(MODE, X) \ 643 RTX_OK_FOR_OFFSET_1 (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \ 644 && epiphany_vect_align == 4 ? SImode : (MODE), X) 645 #define RTX_OK_FOR_OFFSET_1(MODE, X) \ 646 (GET_CODE (X) == CONST_INT \ 647 && !(INTVAL (X) & (GET_MODE_SIZE (MODE) - 1)) \ 648 && INTVAL (X) >= -2047 * (int) GET_MODE_SIZE (MODE) \ 649 && INTVAL (X) <= 2047 * (int) GET_MODE_SIZE (MODE)) 650 651 /* Frame offsets cannot be evaluated till the frame pointer is eliminated. */ 652 #define RTX_FRAME_OFFSET_P(X) \ 653 ((X) == frame_pointer_rtx \ 654 || (GET_CODE (X) == PLUS && XEXP ((X), 0) == frame_pointer_rtx \ 655 && CONST_INT_P (XEXP ((X), 1)))) 656 657 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 658 return the mode to be used for the comparison. */ 659 #define SELECT_CC_MODE(OP, X, Y) \ 660 epiphany_select_cc_mode (OP, X, Y) 661 662 /* Return nonzero if SELECT_CC_MODE will never return MODE for a 663 floating point inequality comparison. */ 664 665 #define REVERSE_CONDITION(CODE, MODE) \ 666 ((MODE) == CC_FPmode || (MODE) == CC_FP_EQmode || (MODE) == CC_FP_GTEmode \ 667 || (MODE) == CC_FP_ORDmode || (MODE) == CC_FP_UNEQmode \ 668 ? reverse_condition_maybe_unordered (CODE) \ 669 : (MODE) == CCmode ? reverse_condition (CODE) \ 670 : UNKNOWN) 671 672 /* We can reverse all CCmodes with REVERSE_CONDITION. */ 673 #define REVERSIBLE_CC_MODE(MODE) \ 674 ((MODE) == CCmode || (MODE) == CC_FPmode || (MODE) == CC_FP_EQmode \ 675 || (MODE) == CC_FP_GTEmode || (MODE) == CC_FP_ORDmode \ 676 || (MODE) == CC_FP_UNEQmode) 677 678 /* Costs. */ 679 680 /* The cost of a branch insn. */ 681 /* ??? What's the right value here? Branches are certainly more 682 expensive than reg->reg moves. */ 683 #define BRANCH_COST(speed_p, predictable_p) \ 684 (speed_p ? epiphany_branch_cost : 1) 685 686 /* Nonzero if access to memory by bytes is slow and undesirable. 687 For RISC chips, it means that access to memory by bytes is no 688 better than access by words when possible, so grab a whole word 689 and maybe make use of that. */ 690 #define SLOW_BYTE_ACCESS 1 691 692 /* Define this macro if it is as good or better to call a constant 693 function address than to call an address kept in a register. */ 694 /* On the EPIPHANY, calling through registers is slow. */ 695 #define NO_FUNCTION_CSE 1 696 697 /* Section selection. */ 698 /* WARNING: These section names also appear in dwarf2out.c. */ 699 700 #define TEXT_SECTION_ASM_OP "\t.section .text" 701 #define DATA_SECTION_ASM_OP "\t.section .data" 702 703 #undef READONLY_DATA_SECTION_ASM_OP 704 #define READONLY_DATA_SECTION_ASM_OP "\t.section .rodata" 705 706 #define BSS_SECTION_ASM_OP "\t.section .bss" 707 708 /* Define this macro if jump tables (for tablejump insns) should be 709 output in the text section, along with the assembler instructions. 710 Otherwise, the readonly data section is used. 711 This macro is irrelevant if there is no separate readonly data section. */ 712 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 713 714 /* PIC */ 715 716 /* The register number of the register used to address a table of static 717 data addresses in memory. In some cases this register is defined by a 718 processor's ``application binary interface'' (ABI). When this macro 719 is defined, RTL is generated for this register once, as with the stack 720 pointer and frame pointer registers. If this macro is not defined, it 721 is up to the machine-dependent files to allocate such a register (if 722 necessary). */ 723 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REGNO : INVALID_REGNUM) 724 725 /* Control the assembler format that we output. */ 726 727 /* A C string constant describing how to begin a comment in the target 728 assembler language. The compiler assumes that the comment will 729 end at the end of the line. */ 730 #define ASM_COMMENT_START ";" 731 732 /* Output to assembler file text saying following lines 733 may contain character constants, extra white space, comments, etc. */ 734 #define ASM_APP_ON "" 735 736 /* Output to assembler file text saying following lines 737 no longer contain unusual constructs. */ 738 #define ASM_APP_OFF "" 739 740 /* Globalizing directive for a label. */ 741 #define GLOBAL_ASM_OP "\t.global\t" 742 743 /* How to refer to registers in assembler output. 744 This sequence is indexed by compiler's hard-register-number (see above). */ 745 746 #define REGISTER_NAMES \ 747 { \ 748 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 749 "r8", "r9", "r10", "fp", "ip", "sp", "lr", "r15", \ 750 "r16", "r17","r18", "r19", "r20", "r21", "r22", "r23", \ 751 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ 752 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 753 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ 754 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 755 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ 756 "ap", "sfp", "cc1", "cc2", \ 757 "config", "status", "lc", "ls", "le", "iret", \ 758 "fp_near", "fp_trunc", "fp_anyfp", "unknown" \ 759 } 760 761 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 762 epiphany_final_prescan_insn (INSN, OPVEC, NOPERANDS) 763 764 #define LOCAL_LABEL_PREFIX "." 765 766 /* A C expression which evaluates to true if CODE is a valid 767 punctuation character for use in the `PRINT_OPERAND' macro. */ 768 extern char epiphany_punct_chars[256]; 769 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 770 epiphany_punct_chars[(unsigned char) (CHAR)] 771 772 /* This is how to output an element of a case-vector that is absolute. */ 773 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 774 do { \ 775 if (CASE_VECTOR_MODE == Pmode) \ 776 asm_fprintf ((FILE), "\t.word %LL%d\n", (VALUE)); \ 777 else \ 778 asm_fprintf ((FILE), "\t.short %LL%d\n", (VALUE)); \ 779 } while (0) 780 781 /* This is how to output an element of a case-vector that is relative. */ 782 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 783 do { \ 784 if (CASE_VECTOR_MODE == Pmode) \ 785 asm_fprintf ((FILE), "\t.word"); \ 786 else \ 787 asm_fprintf ((FILE), "\t.short"); \ 788 asm_fprintf ((FILE), " %LL%d-%LL%d\n", (VALUE), (REL)); \ 789 } while (0) 790 791 /* This is how to output an assembler line 792 that says to advance the location counter 793 to a multiple of 2**LOG bytes. */ 794 #define ASM_OUTPUT_ALIGN(FILE, LOG) \ 795 do { if ((LOG) != 0) fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); } while (0) 796 797 /* Inside the text section, align with nops rather than zeros. */ 798 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE, LOG) \ 799 do \ 800 { \ 801 if ((LOG) != 0) fprintf (FILE, "\t.balignw %d,0x01a2\n", 1 << (LOG)); \ 802 } while (0) 803 804 /* This is how to declare the size of a function. */ 805 #undef ASM_DECLARE_FUNCTION_SIZE 806 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ 807 do \ 808 { \ 809 const char *__name = (FNAME); \ 810 tree attrs = DECL_ATTRIBUTES ((DECL)); \ 811 \ 812 if (!flag_inhibit_size_directive) \ 813 { \ 814 if (lookup_attribute ("forwarder_section", attrs)) \ 815 { \ 816 const char *prefix = "__forwarder_dst_"; \ 817 char *dst_name \ 818 = (char *) alloca (strlen (prefix) + strlen (__name) + 1); \ 819 \ 820 strcpy (dst_name, prefix); \ 821 strcat (dst_name, __name); \ 822 __name = dst_name; \ 823 } \ 824 ASM_OUTPUT_MEASURED_SIZE ((FILE), __name); \ 825 } \ 826 } \ 827 while (0) 828 829 /* Debugging information. */ 830 831 /* Generate DBX and DWARF debugging information. */ 832 #define DBX_DEBUGGING_INFO 1 833 834 #undef PREFERRED_DEBUGGING_TYPE 835 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 836 837 /* Turn off splitting of long stabs. */ 838 #define DBX_CONTIN_LENGTH 0 839 840 /* Miscellaneous. */ 841 842 /* Specify the machine mode that this machine uses 843 for the index in the tablejump instruction. */ 844 #define CASE_VECTOR_MODE (TARGET_SMALL16 && optimize_size ? HImode : Pmode) 845 846 /* Define if operations between registers always perform the operation 847 on the full register even if a narrower mode is specified. */ 848 #define WORD_REGISTER_OPERATIONS 1 849 850 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 851 will either zero-extend or sign-extend. The value of this macro should 852 be the code that says which one of the two operations is implicitly 853 done, UNKNOWN if none. */ 854 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 855 856 /* Max number of bytes we can move from memory to memory 857 in one reasonably fast instruction. */ 858 #define MOVE_MAX 8 859 860 /* Define this to be nonzero if shift instructions ignore all but the low-order 861 few bits. */ 862 #define SHIFT_COUNT_TRUNCATED 1 863 864 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 865 is done just by pretending it is already truncated. */ 866 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 867 868 /* Specify the machine mode that pointers have. 869 After generation of rtl, the compiler makes no further distinction 870 between pointers and any other objects of this machine mode. */ 871 872 #define Pmode SImode 873 874 /* A function address in a call instruction. */ 875 #define FUNCTION_MODE SImode 876 877 /* EPIPHANY function types. */ 878 enum epiphany_function_type 879 { 880 EPIPHANY_FUNCTION_UNKNOWN, EPIPHANY_FUNCTION_NORMAL, 881 EPIPHANY_FUNCTION_INTERRUPT 882 }; 883 884 #define EPIPHANY_INTERRUPT_P(TYPE) ((TYPE) == EPIPHANY_FUNCTION_INTERRUPT) 885 886 /* Compute the type of a function from its DECL. */ 887 888 #define IMMEDIATE_PREFIX "#" 889 890 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 891 (epiphany_optimize_mode_switching (ENTITY)) 892 893 /* We have two fake entities for lazy code motion of the mask constants, 894 one entity each for round-to-nearest / truncating 895 with a different idea what FP_MODE_ROUND_UNKNOWN will be, and 896 finally an entity that runs in a second mode switching pass to 897 resolve FP_MODE_ROUND_UNKNOWN. */ 898 #define NUM_MODES_FOR_MODE_SWITCHING \ 899 { 2, 2, 2, \ 900 FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE } 901 902 #define TARGET_INSERT_MODE_SWITCH_USE epiphany_insert_mode_switch_use 903 904 /* Mode switching entities. */ 905 enum 906 { 907 EPIPHANY_MSW_ENTITY_AND, 908 EPIPHANY_MSW_ENTITY_OR, 909 EPIPHANY_MSW_ENTITY_CONFIG, /* 1 means config is known or saved. */ 910 EPIPHANY_MSW_ENTITY_NEAREST, 911 EPIPHANY_MSW_ENTITY_TRUNC, 912 EPIPHANY_MSW_ENTITY_ROUND_UNKNOWN, 913 EPIPHANY_MSW_ENTITY_ROUND_KNOWN, 914 EPIPHANY_MSW_ENTITY_FPU_OMNIBUS, 915 EPIPHANY_MSW_ENTITY_NUM 916 }; 917 918 extern int epiphany_normal_fp_rounding; 919 #ifndef IN_LIBGCC2 920 extern rtl_opt_pass *make_pass_mode_switch_use (gcc::context *ctxt); 921 extern rtl_opt_pass *make_pass_resolve_sw_modes (gcc::context *ctxt); 922 #endif 923 924 /* This will need to be adjusted when FP_CONTRACT_ON is properly 925 implemented. */ 926 #define TARGET_FUSED_MADD (flag_fp_contract_mode == FP_CONTRACT_FAST) 927 928 #undef ASM_DECLARE_FUNCTION_NAME 929 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ 930 epiphany_start_function ((FILE), (NAME), (DECL)) 931 932 /* This is how we tell the assembler that two symbols have the same value. */ 933 #define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \ 934 do \ 935 { \ 936 assemble_name (FILE, NAME1); \ 937 fputs (" = ", FILE); \ 938 assemble_name (FILE, NAME2); \ 939 fputc ('\n', FILE); \ 940 } \ 941 while (0) 942 943 #endif /* !GCC_EPIPHANY_H */ 944