1;; GCC machine description for CRIS cpu cores. 2;; Copyright (C) 1998-2015 Free Software Foundation, Inc. 3;; Contributed by Axis Communications. 4 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; The original PO technology requires these to be ordered by speed, 22;; so that assigner will pick the fastest. 23 24;; See files "md.texi" and "rtl.def" for documentation on define_insn, 25;; match_*, et. al. 26;; 27;; The function cris_notice_update_cc in cris.c handles condition code 28;; updates for most instructions, helped by the "cc" attribute. 29 30;; There are several instructions that are orthogonal in size, and seems 31;; they could be matched by a single pattern without a specified size 32;; for the operand that is orthogonal. However, this did not work on 33;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a 34;; constant is substituted into an operand, the actual mode must be 35;; deduced from the pattern. There is reasonable hope that that has been 36;; fixed, so FIXME: try again. 37 38;; You will notice that three-operand alternatives ("=r", "r", "!To") 39;; are marked with a "!" constraint modifier to avoid being reloaded 40;; into. This is because gcc would otherwise prefer to use the constant 41;; pool and its offsettable address instead of reloading to an 42;; ("=r", "0", "i") alternative. Also, the constant-pool support was not 43;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3. 44 45;; All insns that look like (set (...) (plus (...) (reg:SI 8))) 46;; get problems when reloading r8 (frame pointer) to r14 + offs (stack 47;; pointer). Thus the instructions that get into trouble have specific 48;; checks against matching frame_pointer_rtx. 49;; ??? But it should be re-checked for gcc > 2.7.2 50;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x. 51 52;; FIXME: When PIC, all [rX=rY+S] could be enabled to match 53;; [rX=gotless_symbol]. 54;; The movsi for a gotless symbol could be split (post reload). 55 56 57(define_c_enum "" 58 [ 59 ;; PLT reference from call expansion: operand 0 is the address, 60 ;; the mode is VOIDmode. Always wrapped in CONST. 61 ;; The value is relative to the GOT. 62 CRIS_UNSPEC_PLT_GOTREL 63 64 ;; PLT reference from call expansion: operand 0 is the address, 65 ;; the mode is VOIDmode. Always wrapped in CONST. 66 ;; The value is relative to the PC. It's arch-dependent whether 67 ;; the offset counts from the start or the end of the current item. 68 CRIS_UNSPEC_PLT_PCREL 69 70 ;; The address of the global offset table as a source operand. 71 CRIS_UNSPEC_GOT 72 73 ;; The offset from the global offset table to the operand. 74 CRIS_UNSPEC_GOTREL 75 76 ;; The PC-relative offset to the operand. It's arch-dependent whether 77 ;; the offset counts from the start or the end of the current item. 78 CRIS_UNSPEC_PCREL 79 80 ;; The index into the global offset table of a symbol, while 81 ;; also generating a GOT entry for the symbol. 82 CRIS_UNSPEC_GOTREAD 83 84 ;; Similar to CRIS_UNSPEC_GOTREAD, but also generating a PLT entry. 85 CRIS_UNSPEC_PLTGOTREAD 86 87 ;; Condition for v32 casesi jump, since it needs to have if_then_else 88 ;; form with register as one branch and default label as other. 89 ;; Operand 0 is const_int 0. 90 CRIS_UNSPEC_CASESI 91 92 ;; Stack frame deallocation barrier. 93 CRIS_UNSPEC_FRAME_DEALLOC 94 95 ;; Swap all 32 bits of the operand; 31 <=> 0, 30 <=> 1... 96 CRIS_UNSPEC_SWAP_BITS 97 ]) 98 99;; Register numbers. 100(define_constants 101 [(CRIS_GOT_REGNUM 0) 102 (CRIS_STATIC_CHAIN_REGNUM 7) 103 (CRIS_FP_REGNUM 8) 104 (CRIS_SP_REGNUM 14) 105 (CRIS_ACR_REGNUM 15) 106 (CRIS_SRP_REGNUM 16) 107 (CRIS_MOF_REGNUM 17) 108 (CRIS_AP_REGNUM 18) 109 (CRIS_CC0_REGNUM 19)] 110) 111 112;; We need an attribute to define whether an instruction can be put in 113;; a branch-delay slot or not, and whether it has a delay slot. 114;; 115;; Branches and return instructions have a delay slot, and cannot 116;; themselves be put in a delay slot. This has changed *for short 117;; branches only* between architecture variants, but the possible win 118;; is presumed negligible compared to the added complexity of the machine 119;; description: one would have to add always-correct infrastructure to 120;; distinguish short branches. 121;; 122;; Whether an instruction can be put in a delay slot depends on the 123;; instruction (all short instructions except jumps and branches) 124;; and the addressing mode (must not be prefixed or referring to pc). 125;; In short, any "slottable" instruction must be 16 bit and not refer 126;; to pc, or alter it. 127;; 128;; The possible values are "yes", "no", "has_slot", "has_return_slot" 129;; and "has_call_slot". 130;; Yes/no tells whether the insn is slottable or not. Has_call_slot means 131;; that the insn is a call insn, which for CRIS v32 has a delay-slot. 132;; Of special concern is that no RTX_FRAME_RELATED insn must go in that 133;; call delay slot, as it's located in the address *after* the call insn, 134;; and the unwind machinery doesn't know about delay slots. 135;; Has_slot means that the insn is a branch insn (which are 136;; not considered slottable since that is generally true). Having the 137;; seemingly illogical value "has_slot" means we do not have to add 138;; another attribute just to say that an insn has a delay-slot, since it 139;; also infers that it is not slottable. Better names for the attribute 140;; were found to be longer and not add readability to the machine 141;; description. 142;; Has_return_slot is similar, for the return insn. 143;; 144;; The default that is defined here for this attribute is "no", not 145;; slottable, not having a delay-slot, so there's no need to worry about 146;; it being wrong for non-branch and return instructions. 147;; The default could depend on the kind of insn and the addressing 148;; mode, but that would need more attributes and hairier, more error 149;; prone code. 150;; 151;; There is an extra memory constraint, 'Q', which recognizes an indirect 152;; register. The constraints 'Q' and '>' together match all possible 153;; memory operands that are slottable. 154;; For other operands, you need to check if it has a valid "slottable" 155;; quick-immediate operand, where the particular signedness-variation 156;; may match the constraints 'I' or 'J'.), and include it in the 157;; constraint pattern for the slottable pattern. An alternative using 158;; only "r" constraints is most often slottable. 159 160(define_attr "slottable" "no,yes,has_slot,has_return_slot,has_call_slot" 161 (const_string "no")) 162 163;; We also need attributes to sanely determine the condition code 164;; state. See cris_notice_update_cc for how this is used. 165 166(define_attr "cc" "none,clobber,normal,noov32,rev" (const_string "normal")) 167 168;; At the moment, this attribute is just used to help bb-reorder do its 169;; work; the default 0 doesn't help it. Many insns have other lengths, 170;; though none are shorter. 171(define_attr "length" "" (const_int 2)) 172 173;; A branch has one delay-slot. The instruction in the 174;; delay-slot is always executed, independent of whether the branch is 175;; taken or not. Note that besides setting "slottable" to "has_slot", 176;; there also has to be a "%#" at the end of a "delayed" instruction 177;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can 178;; catch it and print a "nop" if necessary. This method was stolen from 179;; sparc.md. 180 181(define_delay (eq_attr "slottable" "has_slot") 182 [(eq_attr "slottable" "yes") (nil) (nil)]) 183 184;; We can't put prologue insns in call-insn delay-slots when 185;; DWARF2 unwind info is emitted, because the unwinder matches the 186;; address after the insn. It must see the return address of a call at 187;; a position at least *one byte after* the insn, or it'll think that 188;; the insn hasn't been executed. If the insn is in a delay-slot of a 189;; call, it's just *exactly* after the insn. 190 191(define_delay (eq_attr "slottable" "has_call_slot") 192 [(and (eq_attr "slottable" "yes") 193 (ior (not (match_test "RTX_FRAME_RELATED_P (insn)")) 194 (not (match_test "flag_exceptions")))) 195 (nil) (nil)]) 196 197;; The insn in the return insn slot must not be the 198;; return-address-register restore. FIXME: Use has_slot and express 199;; as a parallel with a use of the return-address-register (currently 200;; only SRP). However, this requires an amount of fixing tests for 201;; naked RETURN in middle-end. 202(define_delay (eq_attr "slottable" "has_return_slot") 203 [(and (eq_attr "slottable" "yes") 204 (not (match_test "dead_or_set_regno_p (insn, CRIS_SRP_REGNUM)"))) 205 (nil) (nil)]) 206 207 208;; Iterator definitions. 209 210;; For the "usual" pattern size alternatives. 211(define_mode_iterator BWD [SI HI QI]) 212(define_mode_iterator WD [SI HI]) 213(define_mode_iterator BW [HI QI]) 214(define_mode_attr S [(SI "HI") (HI "QI")]) 215(define_mode_attr s [(SI "hi") (HI "qi")]) 216(define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")]) 217(define_mode_attr mm [(SI ".w") (HI ".b")]) 218(define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")]) 219 220;; For the sign_extend+zero_extend variants. 221(define_code_iterator szext [sign_extend zero_extend]) 222(define_code_attr u [(sign_extend "") (zero_extend "u")]) 223(define_code_attr su [(sign_extend "s") (zero_extend "u")]) 224 225;; For the shift variants. 226(define_code_iterator shift [ashiftrt lshiftrt ashift]) 227(define_code_iterator shiftrt [ashiftrt lshiftrt]) 228(define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")]) 229(define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")]) 230 231(define_code_iterator ncond [eq ne gtu ltu geu leu]) 232(define_code_iterator ocond [gt le]) 233(define_code_iterator rcond [lt ge]) 234(define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt") 235 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")]) 236(define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge") 237 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")]) 238(define_code_attr oCC [(lt "mi") (ge "pl")]) 239(define_code_attr roCC [(lt "pl") (ge "mi")]) 240 241;; Operand and operator predicates. 242 243(include "predicates.md") 244(include "constraints.md") 245 246;; Test insns. 247 248;; No test insns with side-effect on the mem addressing. 249;; 250;; See note on cmp-insns with side-effects (or lack of them) 251 252;; Normal named test patterns from SI on. 253 254(define_insn "*tstsi" 255 [(set (cc0) 256 (compare (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m") 257 (const_int 0)))] 258 "" 259{ 260 if (which_alternative == 0 && TARGET_V32) 261 return "cmpq 0,%0"; 262 return "test.d %0"; 263} 264 [(set_attr "slottable" "yes,yes,no")]) 265 266(define_insn "*tst<mode>_cmp" 267 [(set (cc0) 268 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m") 269 (const_int 0)))] 270 "cris_cc0_user_requires_cmp (insn)" 271 "@ 272 cmp<m> 0,%0 273 test<m> %0 274 test<m> %0" 275 [(set_attr "slottable" "no,yes,no")]) 276 277(define_insn "*tst<mode>_non_cmp" 278 [(set (cc0) 279 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m") 280 (const_int 0)))] 281 "!cris_cc0_user_requires_cmp (insn)" 282 "@ 283 move<m> %0,%0 284 test<m> %0 285 test<m> %0" 286 [(set_attr "slottable" "yes,yes,no") 287 (set_attr "cc" "noov32,*,*")]) 288 289;; It seems that the position of the sign-bit and the fact that 0.0 is 290;; all 0-bits would make "tstsf" a straight-forward implementation; 291;; either "test.d" it for positive/negative or "btstq 30,r" it for 292;; zeroness. 293;; 294;; FIXME: Do that some time; check next_cc0_user to determine if 295;; zero or negative is tested for. 296 297;; Compare insns. 298 299;; We could optimize the sizes of the immediate operands for various 300;; cases, but that is not worth it because of the very little usage of 301;; DImode for anything else but a structure/block-mode. Just do the 302;; obvious stuff for the straight-forward constraint letters. 303 304(define_insn "*cmpdi_non_v32" 305 [(set (cc0) 306 (compare (match_operand:DI 0 "nonimmediate_operand" "rm,r,r,r,r,r,r,o") 307 (match_operand:DI 1 "general_operand" "M,Kc,I,P,n,r,o,r")))] 308 "!TARGET_V32" 309 "@ 310 test.d %M0\;ax\;test.d %H0 311 cmpq %1,%M0\;ax\;cmpq 0,%H0 312 cmpq %1,%M0\;ax\;cmpq -1,%H0 313 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0 314 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 315 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 316 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 317 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1") 318 319(define_insn "*cmpdi_v32" 320 [(set (cc0) 321 (compare (match_operand:DI 0 "register_operand" "r,r,r,r,r") 322 (match_operand:DI 1 "nonmemory_operand" "Kc,I,P,n,r")))] 323 "TARGET_V32" 324 "@ 325 cmpq %1,%M0\;ax\;cmpq 0,%H0 326 cmpq %1,%M0\;ax\;cmpq -1,%H0 327 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0 328 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 329 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0") 330 331;; Note that compare insns with side effect addressing mode (e.g.): 332;; 333;; cmp.S [rx=ry+i],rz; 334;; cmp.S [%3=%1+%2],%0 335;; 336;; are *not* usable for gcc since the reloader *does not accept* 337;; cc0-changing insns with side-effects other than setting the condition 338;; codes. The reason is that the reload stage *may* cause another insn to 339;; be output after the main instruction, in turn invalidating cc0 for the 340;; insn using the test. (This does not apply to the CRIS case, since a 341;; reload for output -- move to memory -- does not change the condition 342;; code. Unfortunately we have no way to describe that at the moment. I 343;; think code would improve being in the order of one percent faster. 344 345;; We have cmps and cmpu (compare reg w. sign/zero extended mem). 346;; These are mostly useful for compares in SImode, using 8 or 16-bit 347;; constants, but sometimes gcc will find its way to use it for other 348;; (memory) operands. Avoid side-effect patterns, though (see above). 349 350(define_insn "*cmp_ext<mode>" 351 [(set (cc0) 352 (compare 353 (match_operand:SI 0 "register_operand" "r,r") 354 (match_operator:SI 2 "cris_extend_operator" 355 [(match_operand:BW 1 "memory_operand" "Q>,m")])))] 356 "" 357 "cmp%e2<m> %1,%0" 358 [(set_attr "slottable" "yes,no")]) 359 360;; Swap operands; it seems the canonical look (if any) is not enforced. 361;; 362;; FIXME: Investigate that. 363 364(define_insn "*cmp_swapext<mode>" 365 [(set (cc0) 366 (compare 367 (match_operator:SI 2 "cris_extend_operator" 368 [(match_operand:BW 0 "memory_operand" "Q>,m")]) 369 (match_operand:SI 1 "register_operand" "r,r")))] 370 "" 371 "cmp%e2<m> %0,%1" 372 [(set_attr "slottable" "yes,no") 373 (set_attr "cc" "rev")]) 374 375;; The "normal" compare patterns, from SI on. Special-cases with zero 376;; are covered above. 377 378(define_insn "*cmpsi" 379 [(set (cc0) 380 (compare 381 (match_operand:SI 0 "nonimmediate_operand" "r,r,r, Q>,r,r,m") 382 (match_operand:SI 1 "general_operand" "I,r,Q>,r, P,g,r")))] 383 "" 384 "@ 385 cmpq %1,%0 386 cmp.d %1,%0 387 cmp.d %1,%0 388 cmp.d %0,%1 389 cmp%e1.%z1 %1,%0 390 cmp.d %1,%0 391 cmp.d %0,%1" 392 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no") 393 (set_attr "cc" "normal,normal,normal,rev,normal,normal,rev")]) 394 395(define_insn "*cmp<mode>" 396 [(set (cc0) 397 (compare (match_operand:BW 0 "nonimmediate_operand" "r,r, Q>,r,m") 398 (match_operand:BW 1 "general_operand" "r,Q>,r, g,r")))] 399 "" 400 "@ 401 cmp<m> %1,%0 402 cmp<m> %1,%0 403 cmp<m> %0,%1 404 cmp<m> %1,%0 405 cmp<m> %0,%1" 406 [(set_attr "slottable" "yes,yes,yes,no,no") 407 (set_attr "cc" "normal,normal,rev,normal,rev")]) 408 409;; Pattern matching the BTST insn. 410;; It is useful for "if (i & val)" constructs, where val is an exact 411;; power of 2, or if val + 1 is a power of two, where we check for a bunch 412;; of zeros starting at bit 0). 413 414;; SImode. This mode is the only one needed, since gcc automatically 415;; extends subregs for lower-size modes. FIXME: Add testcase. 416(define_insn "*btst" 417 [(set (cc0) 418 (compare 419 (zero_extract:SI 420 (match_operand:SI 0 "nonmemory_operand" "r, r,r, r,r, r,Kp") 421 (match_operand:SI 1 "const_int_operand" "Kc,n,Kc,n,Kc,n,n") 422 (match_operand:SI 2 "nonmemory_operand" "M, M,Kc,n,r, r,r")) 423 (const_int 0)))] 424 ;; Either it is a single bit, or consecutive ones starting at 0. 425 ;; The btst ones depend on stuff in NOTICE_UPDATE_CC. 426 "CONST_INT_P (operands[1]) 427 && (operands[1] == const1_rtx || operands[2] == const0_rtx) 428 && (REG_S_P (operands[0]) 429 || (operands[1] == const1_rtx 430 && REG_S_P (operands[2]) 431 && CONST_INT_P (operands[0]) 432 && exact_log2 (INTVAL (operands[0])) >= 0)) 433 && !TARGET_CCINIT" 434 435;; The next-to-last "&&" condition above should be caught by some kind of 436;; canonicalization in gcc, but we can easily help with it here. 437;; It results from expressions of the type 438;; "power_of_2_value & (1 << y)". 439;; 440;; Since there may be codes with tests in on bits (in constant position) 441;; beyond the size of a word, handle that by assuming those bits are 0. 442;; GCC should handle that, but it's a matter of easily-added belts while 443;; having suspenders. 444 445 "@ 446 btstq (%1-1),%0 447 cmpq 0,%0 448 btstq %2,%0 449 clearf nz 450 btst %2,%0 451 clearf nz 452 cmpq %p0,%2" 453 [(set_attr "slottable" "yes") 454 (set_attr "cc" "noov32")]) 455 456;; Move insns. 457 458;; The whole mandatory movdi family is here; expander, "anonymous" 459;; recognizer and splitter. We're forced to have a movdi pattern, 460;; although GCC should be able to split it up itself. Normally it can, 461;; but if other insns have DI operands (as is the case here), reload 462;; must be able to generate or match a movdi. many testcases fail at 463;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See 464;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>. 465;; However, a patch from Richard Kenner (similar to the cause of 466;; discussion at the URL above), indicates otherwise. See 467;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>. 468;; The truth has IMO is not been decided yet, so check from time to 469;; time by disabling the movdi patterns. 470 471;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at 472;; -O0, we need a movdi as a temporary measure. Here's how things fail: 473;; A cmpdi RTX needs reloading (global): 474;; (insn 185 326 186 (set (cc0) 475;; (compare (mem/f:DI (reg/v:SI 22) 0) 476;; (const_int 1 [0x1]))) 4 {cmpdi} (nil) 477;; (nil)) 478;; Now, reg 22 is reloaded for input address, and the mem is also moved 479;; out of the instruction (into a register), since one of the operands 480;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is 481;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok 482;; wrt. overlap). The bad things happen with the synthesis in 483;; emit_move_insn_1; the location where to substitute reg 10 is lost into 484;; two new RTX:es, both still having reg 22. Later on, the left-over reg 485;; 22 is recognized to have an equivalent in memory which is substituted 486;; straight in, and we end up with an unrecognizable insn: 487;; (insn 325 324 326 (set (reg:SI 9 r9) 488;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8) 489;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil) 490;; (nil)) 491;; which is the first part of the reloaded synthesized "movdi". 492;; The right thing would be to add equivalent replacement locations for 493;; insn with pseudos that need more reloading. The question is where. 494 495(define_expand "movdi" 496 [(set (match_operand:DI 0 "nonimmediate_operand" "") 497 (match_operand:DI 1 "general_operand" ""))] 498 "" 499{ 500 if (MEM_P (operands[0]) 501 && operands[1] != const0_rtx 502 && (!TARGET_V32 || (!REG_P (operands[1]) && can_create_pseudo_p ()))) 503 operands[1] = copy_to_mode_reg (DImode, operands[1]); 504 505 /* Some other ports (as of 2001-09-10 for example mcore and romp) also 506 prefer to split up constants early, like this. The testcase in 507 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the 508 resulting subreg sets when using the construct from mcore (as of FSF 509 CVS, version -r 1.5), and it believes that the high part (the last one 510 emitted) is the final value. */ 511 if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) 512 && ! reload_completed 513 && ! reload_in_progress) 514 { 515 rtx insns; 516 rtx op0 = operands[0]; 517 rtx op1 = operands[1]; 518 519 start_sequence (); 520 emit_move_insn (operand_subword (op0, 0, 1, DImode), 521 operand_subword (op1, 0, 1, DImode)); 522 emit_move_insn (operand_subword (op0, 1, 1, DImode), 523 operand_subword (op1, 1, 1, DImode)); 524 insns = get_insns (); 525 end_sequence (); 526 527 emit_insn (insns); 528 DONE; 529 } 530}) 531 532(define_insn_and_split "*movdi_insn_non_v32" 533 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m") 534 (match_operand:DI 1 "general_operand" "rx,g,rxM"))] 535 "(register_operand (operands[0], DImode) 536 || register_operand (operands[1], DImode) 537 || operands[1] == const0_rtx) 538 && !TARGET_V32" 539 "#" 540 "&& reload_completed" 541 [(match_dup 2)] 542 "operands[2] = cris_split_movdx (operands);") 543 544;; Overlapping (but non-identical) source memory address and destination 545;; register would be a compiler bug, so we don't have to specify that. 546(define_insn "*movdi_v32" 547 [(set 548 (match_operand:DI 0 "nonimmediate_operand" "=r,rx,&r,>, m,r,x,m") 549 (match_operand:DI 1 "general_operand" "rxi,r>,m, rx,r,m,m,x"))] 550 "TARGET_V32" 551{ 552 switch (which_alternative) 553 { 554 /* FIXME: 1) Use autoincrement where possible. 2) Have peephole2, 555 particularly for cases where the address register is dead. */ 556 case 5: 557 if (REGNO (operands[0]) == REGNO (XEXP (operands[1], 0))) 558 return "addq 4,%L1\;move.d %1,%H0\;subq 4,%L1\;move.d %1,%M0"; 559 gcc_assert (REGNO (operands[0]) + 1 == REGNO (XEXP (operands[1], 0))); 560 return "move.d [%L1+],%M0\;move.d [%L1],%H0"; 561 case 2: 562 /* We could do away with the addq if we knew the address-register 563 isn't ACR. If we knew the address-register is dead, we could do 564 away with the subq too. */ 565 return "move.d [%L1],%M0\;addq 4,%L1\;move.d [%L1],%H0\;subq 4,%L1"; 566 case 4: 567 return "move.d %M1,[%L0]\;addq 4,%L0\;move.d %H1,[%L0]\;subq 4,%L0"; 568 case 6: 569 return "move [%L1],%M0\;addq 4,%L1\;move [%L1],%H0\;subq 4,%L1"; 570 case 7: 571 return "move %M1,[%L0]\;addq 4,%L0\;move %H1,[%L0]\;subq 4,%L0"; 572 573 default: 574 return "#"; 575 } 576} 577 ;; The non-split cases clobber cc0 because of their adds and subs. 578 ;; Beware that NOTICE_UPDATE_CC is called before the forced split happens. 579 [(set_attr "cc" "*,*,clobber,*,clobber,clobber,*,*")]) 580 581;; Much like "*movdi_insn_non_v32". Overlapping registers and constants 582;; is handled so much better in cris_split_movdx. 583(define_split 584 [(set (match_operand:DI 0 "nonimmediate_operand" "") 585 (match_operand:DI 1 "general_operand" ""))] 586 "TARGET_V32 587 && reload_completed 588 && (!MEM_P (operands[0]) || !REG_P (XEXP (operands[0], 0))) 589 && (!MEM_P (operands[1]) || !REG_P (XEXP (operands[1], 0)))" 590 [(match_dup 2)] 591 "operands[2] = cris_split_movdx (operands);") 592 593;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw 594;; and move.S1 [rx=ry+i],rz 595;; Then movs.S1 and movu.S1 for both modes. 596;; 597;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx 598;; FIXME: These could have anonymous mode for operand 0. 599;; FIXME: Special registers' alternatives too. 600 601(define_insn "*mov_side<mode>_biap" 602 [(set (match_operand:BW 0 "register_operand" "=r,r") 603 (mem:BW (plus:SI 604 (mult:SI (match_operand:SI 1 "register_operand" "r,r") 605 (match_operand:SI 2 "const_int_operand" "n,n")) 606 (match_operand:SI 3 "register_operand" "r,r")))) 607 (set (match_operand:SI 4 "register_operand" "=*3,r") 608 (plus:SI (mult:SI (match_dup 1) 609 (match_dup 2)) 610 (match_dup 3)))] 611 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" 612 "@ 613 # 614 move<m> [%4=%3+%1%T2],%0") 615 616(define_insn "*mov_sidesisf_biap" 617 [(set (match_operand 0 "register_operand" "=r,r,x,x") 618 (mem (plus:SI 619 (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r") 620 (match_operand:SI 2 "const_int_operand" "n,n,n,n")) 621 (match_operand:SI 3 "register_operand" "r,r,r,r")))) 622 (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r") 623 (plus:SI (mult:SI (match_dup 1) 624 (match_dup 2)) 625 (match_dup 3)))] 626 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD 627 && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" 628 "@ 629 # 630 move.%s0 [%4=%3+%1%T2],%0 631 # 632 move [%4=%3+%1%T2],%0") 633 634;; move.S1 [rx=ry+i],rz 635;; avoiding move.S1 [ry=ry+i],rz 636;; and move.S1 [rz=ry+i],rz 637;; Note that "i" is allowed to be a register. 638 639(define_insn "*mov_side<mode>" 640 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r") 641 (mem:BW 642 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R") 643 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))) 644 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r") 645 (plus:SI (match_dup 1) 646 (match_dup 2)))] 647 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" 648{ 649 if ((which_alternative == 0 || which_alternative == 3) 650 && (!CONST_INT_P (operands[2]) 651 || INTVAL (operands[2]) > 127 652 || INTVAL (operands[2]) < -128 653 || satisfies_constraint_N (operands[2]) 654 || satisfies_constraint_J (operands[2]))) 655 return "#"; 656 if (which_alternative == 4) 657 return "move<m> [%3=%2%S1],%0"; 658 return "move<m> [%3=%1%S2],%0"; 659}) 660 661(define_insn "*mov_sidesisf" 662 [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x,r,r,x,x") 663 (mem 664 (plus:SI 665 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R") 666 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r")))) 667 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r,*2,r,*2,r") 668 (plus:SI (match_dup 1) 669 (match_dup 2)))] 670 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD 671 && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" 672{ 673 if ((which_alternative == 0 674 || which_alternative == 3 675 || which_alternative == 6 676 || which_alternative == 8) 677 && (!CONST_INT_P (operands[2]) 678 || INTVAL (operands[2]) > 127 679 || INTVAL (operands[2]) < -128 680 || satisfies_constraint_N (operands[2]) 681 || satisfies_constraint_J (operands[2]))) 682 return "#"; 683 if (which_alternative < 3) 684 return "move.%s0 [%3=%1%S2],%0"; 685 if (which_alternative == 7) 686 return "move.%s0 [%3=%2%S1],%0"; 687 if (which_alternative == 9) 688 return "move [%3=%2%S1],%0"; 689 return "move [%3=%1%S2],%0"; 690}) 691 692;; Other way around; move to memory. 693 694;; Note that the condition (which for side-effect patterns is usually a 695;; call to cris_side_effect_mode_ok), isn't consulted for register 696;; allocation preferences -- constraints is the method for that. The 697;; drawback is that we can't exclude register allocation to cause 698;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or 699;; rx==rz if we use an earlyclobber modifier for the constraint for rx. 700;; Instead of that, we recognize and split the cases where dangerous 701;; register combinations are spotted: where a register is set in the 702;; side-effect, and used in the main insn. We don't handle the case where 703;; the set in the main insn overlaps the set in the side-effect; that case 704;; must be handled in gcc. We handle just the case where the set in the 705;; side-effect overlaps the input operand of the main insn (i.e. just 706;; moves to memory). 707 708;; 709;; move.s rz,[ry=rx+rw.S] 710 711(define_insn "*mov_side<mode>_biap_mem" 712 [(set (mem:BW (plus:SI 713 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r") 714 (match_operand:SI 1 "const_int_operand" "n,n,n")) 715 (match_operand:SI 2 "register_operand" "r,r,r"))) 716 (match_operand:BW 3 "register_operand" "r,r,r")) 717 (set (match_operand:SI 4 "register_operand" "=*2,!3,r") 718 (plus:SI (mult:SI (match_dup 0) 719 (match_dup 1)) 720 (match_dup 2)))] 721 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)" 722 "@ 723 # 724 # 725 move<m> %3,[%4=%2+%0%T1]") 726 727(define_insn "*mov_sidesisf_biap_mem" 728 [(set (mem (plus:SI 729 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r") 730 (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n")) 731 (match_operand:SI 2 "register_operand" "r,r,r,r,r,r"))) 732 (match_operand 3 "register_operand" "r,r,r,x,x,x")) 733 (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r") 734 (plus:SI (mult:SI (match_dup 0) 735 (match_dup 1)) 736 (match_dup 2)))] 737 "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD 738 && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)" 739 "@ 740 # 741 # 742 move.%s3 %3,[%4=%2+%0%T1] 743 # 744 # 745 move %3,[%4=%2+%0%T1]") 746 747;; Split for the case above where we're out of luck with register 748;; allocation (again, the condition isn't checked for that), and we end up 749;; with the set in the side-effect getting the same register as the input 750;; register. 751 752(define_split 753 [(parallel 754 [(set (match_operator 755 6 "cris_mem_op" 756 [(plus:SI 757 (mult:SI (match_operand:SI 0 "register_operand" "") 758 (match_operand:SI 1 "const_int_operand" "")) 759 (match_operand:SI 2 "register_operand" ""))]) 760 (match_operand 3 "register_operand" "")) 761 (set (match_operand:SI 4 "cris_nonsp_register_operand" "") 762 (plus:SI (mult:SI (match_dup 0) 763 (match_dup 1)) 764 (match_dup 2)))])] 765 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])" 766 [(set (match_dup 5) (match_dup 3)) 767 (set (match_dup 4) (match_dup 2)) 768 (set (match_dup 4) 769 (plus:SI (mult:SI (match_dup 0) 770 (match_dup 1)) 771 (match_dup 4)))] 772 "operands[5] 773 = replace_equiv_address (operands[6], 774 gen_rtx_PLUS (SImode, 775 gen_rtx_MULT (SImode, 776 operands[0], 777 operands[1]), 778 operands[2]));") 779 780;; move.s rx,[ry=rz+i] 781;; FIXME: These could have anonymous mode for operand 2. 782 783;; QImode 784 785(define_insn "*mov_side<mode>_mem" 786 [(set (mem:BW 787 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r,R,R,R") 788 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r"))) 789 (match_operand:BW 2 "register_operand" "r,r,r,r,r,r,r")) 790 (set (match_operand:SI 3 "register_operand" "=*0,!*2,r,r,*1,!*2,r") 791 (plus:SI (match_dup 0) 792 (match_dup 1)))] 793 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)" 794{ 795 if ((which_alternative == 0 || which_alternative == 4) 796 && (!CONST_INT_P (operands[1]) 797 || INTVAL (operands[1]) > 127 798 || INTVAL (operands[1]) < -128 799 || satisfies_constraint_N (operands[1]) 800 || satisfies_constraint_J (operands[1]))) 801 return "#"; 802 if (which_alternative == 1 || which_alternative == 5) 803 return "#"; 804 if (which_alternative == 6) 805 return "move.%s2 %2,[%3=%1%S0]"; 806 return "move<m> %2,[%3=%0%S1]"; 807}) 808 809;; SImode 810 811(define_insn "*mov_sidesisf_mem" 812 [(set (mem 813 (plus:SI 814 (match_operand:SI 815 0 "cris_bdap_operand" 816 "%r, r, r,r, r, r,r, R,R, R,R, R") 817 (match_operand:SI 818 1 "cris_bdap_operand" 819 "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r, r,r, r"))) 820 (match_operand 2 "register_operand" 821 "r, r, r,r, x, x,x, r,r, r,x, x")) 822 (set (match_operand:SI 3 "register_operand" 823 "=*0,!2, r,r, *0, r,r, *1,!*2,r,*1,r") 824 (plus:SI (match_dup 0) 825 (match_dup 1)))] 826 "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD 827 && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)" 828{ 829 if ((which_alternative == 0 || which_alternative == 4) 830 && (!CONST_INT_P (operands[1]) 831 || INTVAL (operands[1]) > 127 832 || INTVAL (operands[1]) < -128 833 || satisfies_constraint_N (operands[1]) 834 || satisfies_constraint_J (operands[1]))) 835 return "#"; 836 if (which_alternative == 1 837 || which_alternative == 7 838 || which_alternative == 8 839 || which_alternative == 10) 840 return "#"; 841 if (which_alternative < 4) 842 return "move.%s2 %2,[%3=%0%S1]"; 843 if (which_alternative == 9) 844 return "move.%s2 %2,[%3=%1%S0]"; 845 if (which_alternative == 11) 846 return "move %2,[%3=%1%S0]"; 847 return "move %2,[%3=%0%S1]"; 848}) 849 850;; Like the biap case, a split where the set in the side-effect gets the 851;; same register as the input register to the main insn, since the 852;; condition isn't checked at register allocation. 853 854(define_split 855 [(parallel 856 [(set (match_operator 857 4 "cris_mem_op" 858 [(plus:SI 859 (match_operand:SI 0 "cris_bdap_operand" "") 860 (match_operand:SI 1 "cris_bdap_operand" ""))]) 861 (match_operand 2 "register_operand" "")) 862 (set (match_operand:SI 3 "cris_nonsp_register_operand" "") 863 (plus:SI (match_dup 0) (match_dup 1)))])] 864 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])" 865 [(set (match_dup 4) (match_dup 2)) 866 (set (match_dup 3) (match_dup 0)) 867 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))] 868 "") 869 870;; Clear memory side-effect patterns. It is hard to get to the mode if 871;; the MEM was anonymous, so there will be one for each mode. 872 873;; clear.[bwd] [ry=rx+rw.s2] 874 875(define_insn "*clear_side<mode>_biap" 876 [(set (mem:BWD (plus:SI 877 (mult:SI (match_operand:SI 0 "register_operand" "r,r") 878 (match_operand:SI 1 "const_int_operand" "n,n")) 879 (match_operand:SI 2 "register_operand" "r,r"))) 880 (const_int 0)) 881 (set (match_operand:SI 3 "register_operand" "=*2,r") 882 (plus:SI (mult:SI (match_dup 0) 883 (match_dup 1)) 884 (match_dup 2)))] 885 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)" 886 "@ 887 # 888 clear<m> [%3=%2+%0%T1]") 889 890;; clear.[bwd] [ry=rz+i] 891 892(define_insn "*clear_side<mode>" 893 [(set (mem:BWD 894 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,R,R") 895 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))) 896 (const_int 0)) 897 (set (match_operand:SI 2 "register_operand" "=*0,r,r,*1,r") 898 (plus:SI (match_dup 0) 899 (match_dup 1)))] 900 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)" 901{ 902 if ((which_alternative == 0 || which_alternative == 3) 903 && (!CONST_INT_P (operands[1]) 904 || INTVAL (operands[1]) > 127 905 || INTVAL (operands[1]) < -128 906 || satisfies_constraint_N (operands[1]) 907 || satisfies_constraint_J (operands[1]))) 908 return "#"; 909 if (which_alternative == 4) 910 return "clear<m> [%2=%1%S0]"; 911 return "clear<m> [%2=%0%S1]"; 912}) 913 914;; Normal move patterns from SI on. 915 916(define_expand "movsi" 917 [(set 918 (match_operand:SI 0 "nonimmediate_operand" "") 919 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))] 920 "" 921{ 922 enum cris_symbol_type t; 923 924 /* If the output goes to a MEM, make sure we have zero or a register as 925 input. */ 926 if (MEM_P (operands[0]) 927 && ! REG_S_P (operands[1]) 928 && operands[1] != const0_rtx 929 && can_create_pseudo_p ()) 930 operands[1] = force_reg (SImode, operands[1]); 931 932 /* If we're generating PIC and have an incoming symbol, validize it to a 933 general operand or something that will match a special pattern. 934 935 FIXME: Do we *have* to recognize anything that would normally be a 936 valid symbol? Can we exclude global PIC addresses with an added 937 offset? */ 938 if (flag_pic 939 && CONSTANT_P (operands[1]) 940 && !cris_valid_pic_const (operands[1], false)) 941 { 942 t = cris_symbol_type_of (operands[1]); 943 944 gcc_assert (t != cris_no_symbol && t != cris_offsettable_symbol); 945 946 if (! REG_S_P (operands[0])) 947 { 948 /* We must have a register as destination for what we're about to 949 do, and for the patterns we generate. */ 950 CRIS_ASSERT (can_create_pseudo_p ()); 951 operands[1] = force_reg (SImode, operands[1]); 952 } 953 else 954 { 955 /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the 956 destination register for the symbol. It might not be 957 worth it. Measure. */ 958 crtl->uses_pic_offset_table = 1; 959 if (t == cris_rel_symbol) 960 { 961 /* Change a "move.d sym(+offs),rN" into (allocate register rM) 962 for pre-v32: 963 "move.d (const (plus (unspec [sym] 964 CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN" 965 and for v32: 966 "move.d (const (plus (unspec [sym] 967 CRIS_UNSPEC_PCREL) offs)),rN". */ 968 rtx tem, rm, rn = operands[0]; 969 rtx sym = GET_CODE (operands[1]) != CONST 970 ? operands[1] : get_related_value (operands[1]); 971 HOST_WIDE_INT offs = get_integer_term (operands[1]); 972 973 gcc_assert (can_create_pseudo_p ()); 974 975 if (TARGET_V32) 976 { 977 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 978 CRIS_UNSPEC_PCREL); 979 if (offs != 0) 980 tem = plus_constant (Pmode, tem, offs); 981 rm = rn; 982 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); 983 } 984 else 985 { 986 /* We still uses GOT-relative addressing for 987 pre-v32. */ 988 crtl->uses_pic_offset_table = 1; 989 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 990 CRIS_UNSPEC_GOTREL); 991 if (offs != 0) 992 tem = plus_constant (Pmode, tem, offs); 993 rm = gen_reg_rtx (Pmode); 994 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); 995 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx, 996 rn, 0, OPTAB_LIB_WIDEN) != rn) 997 internal_error ("expand_binop failed in movsi gotrel"); 998 } 999 DONE; 1000 } 1001 else if (t == cris_got_symbol) 1002 { 1003 /* Change a "move.d sym,rN" into (allocate register rM, rO) 1004 "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM" 1005 "add.d rPIC,rM,rO", "move.d [rO],rN" with 1006 the memory access marked as read-only. */ 1007 rtx tem, mem, rm, ro, rn = operands[0]; 1008 gcc_assert (can_create_pseudo_p ()); 1009 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), 1010 CRIS_UNSPEC_GOTREAD); 1011 rm = gen_reg_rtx (Pmode); 1012 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); 1013 ro = gen_reg_rtx (Pmode); 1014 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx, 1015 ro, 0, OPTAB_LIB_WIDEN) != ro) 1016 internal_error ("expand_binop failed in movsi got"); 1017 mem = gen_rtx_MEM (Pmode, ro); 1018 1019 /* This MEM doesn't alias anything. Whether it 1020 aliases other same symbols is unimportant. */ 1021 set_mem_alias_set (mem, new_alias_set ()); 1022 MEM_NOTRAP_P (mem) = 1; 1023 1024 /* We can set the GOT memory read of a non-called symbol 1025 to readonly, but not that of a call symbol, as those 1026 are subject to lazy evaluation and usually have the value 1027 changed from the first call to the second (but 1028 constant thereafter). */ 1029 MEM_READONLY_P (mem) = 1; 1030 emit_move_insn (rn, mem); 1031 DONE; 1032 } 1033 else 1034 { 1035 /* We get here when we have to change something that would 1036 be recognizable if it wasn't PIC. A ``sym'' is ok for 1037 PIC symbols both with and without a GOT entry. And ``sym 1038 + offset'' is ok for local symbols, so the only thing it 1039 could be, is a global symbol with an offset. Check and 1040 abort if not. */ 1041 rtx reg = gen_reg_rtx (Pmode); 1042 rtx sym = get_related_value (operands[1]); 1043 HOST_WIDE_INT offs = get_integer_term (operands[1]); 1044 1045 gcc_assert (can_create_pseudo_p () 1046 && t == cris_got_symbol_needing_fixup 1047 && sym != NULL_RTX && offs != 0); 1048 1049 emit_move_insn (reg, sym); 1050 if (expand_binop (SImode, add_optab, reg, 1051 GEN_INT (offs), operands[0], 0, 1052 OPTAB_LIB_WIDEN) != operands[0]) 1053 internal_error ("expand_binop failed in movsi got+offs"); 1054 DONE; 1055 } 1056 } 1057 } 1058}) 1059 1060(define_insn "*movsi_got_load" 1061 [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int 0)] CRIS_UNSPEC_GOT))] 1062 "flag_pic" 1063{ 1064 return TARGET_V32 1065 ? "lapc _GLOBAL_OFFSET_TABLE_,%:" 1066 : "move.d $pc,%:\;sub.d .:GOTOFF,%:"; 1067} 1068 [(set_attr "cc" "clobber")]) 1069 1070(define_insn "*movsi_internal" 1071 [(set 1072 (match_operand:SI 0 "nonimmediate_operand" 1073 "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x") 1074 (match_operand:SI 1 "cris_general_operand_or_pic_source" 1075 "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))] 1076 ;; Note that we prefer not to use the S alternative (if for some reason 1077 ;; it competes with others) above, but g matches S. 1078 "" 1079{ 1080 /* Better to have c-switch here; it is worth it to optimize the size of 1081 move insns. The alternative would be to try to find more constraint 1082 letters. FIXME: Check again. It seems this could shrink a bit. */ 1083 switch (which_alternative) 1084 { 1085 case 9: 1086 if (TARGET_V32) 1087 { 1088 if (!flag_pic 1089 && (GET_CODE (operands[1]) == SYMBOL_REF 1090 || GET_CODE (operands[1]) == LABEL_REF 1091 || (GET_CODE (operands[1]) == CONST 1092 && (GET_CODE (XEXP (operands[1], 0)) != UNSPEC 1093 || (XINT (XEXP (operands[1], 0), 1) 1094 == CRIS_UNSPEC_PLT_PCREL) 1095 || (XINT (XEXP (operands[1], 0), 1) 1096 == CRIS_UNSPEC_PCREL))))) 1097 { 1098 /* FIXME: Express this through (set_attr cc none) instead, 1099 since we can't express the ``none'' at this point. FIXME: 1100 Use lapc for everything except const_int and when next cc0 1101 user would want the flag setting. */ 1102 CC_STATUS_INIT; 1103 return "lapc %1,%0"; 1104 } 1105 if (flag_pic == 1 1106 && GET_CODE (operands[1]) == CONST 1107 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC 1108 && XINT (XEXP (operands[1], 0), 1) == CRIS_UNSPEC_GOTREAD) 1109 return "movu.w %1,%0"; 1110 } 1111 /* FALLTHROUGH */ 1112 case 0: 1113 case 1: 1114 case 5: 1115 case 10: 1116 return "move.d %1,%0"; 1117 1118 case 11: 1119 case 12: 1120 case 13: 1121 case 14: 1122 return "move %d1,%0"; 1123 1124 case 2: 1125 case 3: 1126 case 6: 1127 return "clear.d %0"; 1128 1129 /* Constants -32..31 except 0. */ 1130 case 4: 1131 return "moveq %1,%0"; 1132 1133 /* We can win a little on constants -32768..-33, 32..65535. */ 1134 case 7: 1135 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536) 1136 { 1137 if (INTVAL (operands[1]) < 256) 1138 return "movu.b %1,%0"; 1139 return "movu.w %1,%0"; 1140 } 1141 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768) 1142 { 1143 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128) 1144 return "movs.b %1,%0"; 1145 return "movs.w %1,%0"; 1146 } 1147 return "move.d %1,%0"; 1148 1149 case 8: 1150 { 1151 rtx tem = operands[1]; 1152 gcc_assert (GET_CODE (tem) == CONST); 1153 tem = XEXP (tem, 0); 1154 if (GET_CODE (tem) == PLUS 1155 && GET_CODE (XEXP (tem, 0)) == UNSPEC 1156 && (XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL 1157 || XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_PCREL) 1158 && CONST_INT_P (XEXP (tem, 1))) 1159 tem = XEXP (tem, 0); 1160 gcc_assert (GET_CODE (tem) == UNSPEC); 1161 switch (XINT (tem, 1)) 1162 { 1163 case CRIS_UNSPEC_GOTREAD: 1164 case CRIS_UNSPEC_PLTGOTREAD: 1165 /* Using sign-extend mostly to be consistent with the 1166 indexed addressing mode. */ 1167 if (flag_pic == 1) 1168 return "movs.w %1,%0"; 1169 return "move.d %1,%0"; 1170 1171 case CRIS_UNSPEC_GOTREL: 1172 case CRIS_UNSPEC_PLT_GOTREL: 1173 gcc_assert (!TARGET_V32); 1174 return "move.d %1,%0"; 1175 1176 case CRIS_UNSPEC_PCREL: 1177 case CRIS_UNSPEC_PLT_PCREL: 1178 gcc_assert (TARGET_V32); 1179 /* LAPC doesn't set condition codes; clear them to make the 1180 (equivalence-marked) result of this insn not presumed 1181 present. This instruction can be a PIC symbol load (for 1182 a hidden symbol) which for weak symbols will be followed 1183 by a test for NULL. */ 1184 CC_STATUS_INIT; 1185 return "lapc %1,%0"; 1186 1187 default: 1188 gcc_unreachable (); 1189 } 1190 } 1191 default: 1192 return "BOGUS: %1 to %0"; 1193 } 1194} 1195 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no") 1196 (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")]) 1197 1198;; Extend operations with side-effect from mem to register, using 1199;; MOVS/MOVU. These are from mem to register only. 1200;; 1201;; [rx=ry+rz.S] 1202;; 1203;; QImode to HImode 1204;; 1205;; FIXME: Can we omit extend to HImode, since GCC should truncate for 1206;; HImode by itself? Perhaps use only anonymous modes? 1207 1208(define_insn "*ext_sideqihi_biap" 1209 [(set (match_operand:HI 0 "register_operand" "=r,r") 1210 (match_operator:HI 1211 5 "cris_extend_operator" 1212 [(mem:QI (plus:SI 1213 (mult:SI (match_operand:SI 1 "register_operand" "r,r") 1214 (match_operand:SI 2 "const_int_operand" "n,n")) 1215 (match_operand:SI 3 "register_operand" "r,r")))])) 1216 (set (match_operand:SI 4 "register_operand" "=*3,r") 1217 (plus:SI (mult:SI (match_dup 1) 1218 (match_dup 2)) 1219 (match_dup 3)))] 1220 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" 1221 "@ 1222 # 1223 mov%e5.%m5 [%4=%3+%1%T2],%0") 1224 1225(define_insn "*ext_side<mode>si_biap" 1226 [(set (match_operand:SI 0 "register_operand" "=r,r") 1227 (match_operator:SI 1228 5 "cris_extend_operator" 1229 [(mem:BW (plus:SI 1230 (mult:SI (match_operand:SI 1 "register_operand" "r,r") 1231 (match_operand:SI 2 "const_int_operand" "n,n")) 1232 (match_operand:SI 3 "register_operand" "r,r")))])) 1233 (set (match_operand:SI 4 "register_operand" "=*3,r") 1234 (plus:SI (mult:SI (match_dup 1) 1235 (match_dup 2)) 1236 (match_dup 3)))] 1237 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" 1238 "@ 1239 # 1240 mov%e5<m> [%4=%3+%1%T2],%0") 1241 1242;; Same but [rx=ry+i] 1243 1244;; QImode to HImode 1245 1246(define_insn "*ext_sideqihi" 1247 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") 1248 (match_operator:HI 1249 4 "cris_extend_operator" 1250 [(mem:QI (plus:SI 1251 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R") 1252 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])) 1253 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r") 1254 (plus:SI (match_dup 1) 1255 (match_dup 2)))] 1256 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" 1257{ 1258 if ((which_alternative == 0 || which_alternative == 3) 1259 && (!CONST_INT_P (operands[2]) 1260 || INTVAL (operands[2]) > 127 1261 || INTVAL (operands[2]) < -128 1262 || satisfies_constraint_N (operands[2]) 1263 || satisfies_constraint_J (operands[2]))) 1264 return "#"; 1265 if (which_alternative == 4) 1266 return "mov%e4.%m4 [%3=%2%S1],%0"; 1267 return "mov%e4.%m4 [%3=%1%S2],%0"; 1268}) 1269 1270(define_insn "*ext_side<mode>si" 1271 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") 1272 (match_operator:SI 1273 4 "cris_extend_operator" 1274 [(mem:BW (plus:SI 1275 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R") 1276 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])) 1277 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r") 1278 (plus:SI (match_dup 1) 1279 (match_dup 2)))] 1280 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" 1281{ 1282 if ((which_alternative == 0 || which_alternative == 3) 1283 && (!CONST_INT_P (operands[2]) 1284 || INTVAL (operands[2]) > 127 1285 || INTVAL (operands[2]) < -128 1286 || satisfies_constraint_N (operands[2]) 1287 || satisfies_constraint_J (operands[2]))) 1288 return "#"; 1289 if (which_alternative == 4) 1290 return "mov%e4<m> [%3=%2%S1],%0"; 1291 return "mov%e4<m> [%3=%1%S2],%0"; 1292}) 1293 1294;; FIXME: See movsi. 1295 1296(define_insn "movhi" 1297 [(set 1298 (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x") 1299 (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))] 1300 "" 1301{ 1302 switch (which_alternative) 1303 { 1304 case 0: 1305 case 1: 1306 case 5: 1307 case 10: 1308 case 11: 1309 return "move.w %1,%0"; 1310 case 12: 1311 case 13: 1312 return "move %1,%0"; 1313 case 2: 1314 case 3: 1315 case 9: 1316 return "clear.w %0"; 1317 case 4: 1318 return "moveq %1,%0"; 1319 case 6: 1320 case 8: 1321 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128) 1322 { 1323 if (INTVAL (operands[1]) > 0) 1324 return "movu.b %1,%0"; 1325 return "movs.b %1,%0"; 1326 } 1327 return "move.w %1,%0"; 1328 case 7: 1329 return "movEq %b1,%0"; 1330 default: 1331 return "BOGUS: %1 to %0"; 1332 } 1333} 1334 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes") 1335 (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")]) 1336 1337(define_insn "movstricthi" 1338 [(set 1339 (strict_low_part 1340 (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g")) 1341 (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))] 1342 "" 1343 "@ 1344 move.w %1,%0 1345 move.w %1,%0 1346 clear.w %0 1347 clear.w %0 1348 move.w %1,%0 1349 clear.w %0 1350 move.w %1,%0 1351 move.w %1,%0" 1352 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) 1353 1354(define_expand "reload_in<mode>" 1355 [(set (match_operand:BW 2 "register_operand" "=r") 1356 (match_operand:BW 1 "memory_operand" "m")) 1357 (set (match_operand:BW 0 "register_operand" "=x") 1358 (match_dup 2))] 1359 "" 1360 "") 1361 1362(define_expand "reload_out<mode>" 1363 [(set (match_operand:BW 2 "register_operand" "=&r") 1364 (match_operand:BW 1 "register_operand" "x")) 1365 (set (match_operand:BW 0 "memory_operand" "=m") 1366 (match_dup 2))] 1367 "" 1368 "") 1369 1370(define_insn "movqi" 1371 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x") 1372 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))] 1373 "" 1374 "@ 1375 move.b %1,%0 1376 move.b %1,%0 1377 move.b %1,%0 1378 clear.b %0 1379 clear.b %0 1380 moveq %1,%0 1381 clear.b %0 1382 move.b %1,%0 1383 moveq %b1,%0 1384 move.b %1,%0 1385 move %1,%0 1386 move %1,%0" 1387 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes") 1388 (set_attr "cc" "*,*,*,*,*,*,*,*,clobber,*,none,none")]) 1389 1390(define_insn "movstrictqi" 1391 [(set (strict_low_part 1392 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r")) 1393 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))] 1394 "" 1395 "@ 1396 move.b %1,%0 1397 move.b %1,%0 1398 move.b %1,%0 1399 clear.b %0 1400 clear.b %0 1401 clear.b %0 1402 move.b %1,%0 1403 move.b %1,%0" 1404 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) 1405 1406;; The valid "quick" bit-patterns are, except for 0.0, denormalized 1407;; values REALLY close to 0, and some NaN:s (I think; their exponent is 1408;; all ones); the worthwhile one is "0.0". 1409;; It will use clear, so we know ALL types of immediate 0 never change cc. 1410 1411(define_insn "movsf" 1412 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x") 1413 (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))] 1414 "" 1415 "@ 1416 move.d %1,%0 1417 move.d %1,%0 1418 move.d %1,%0 1419 clear.d %0 1420 clear.d %0 1421 clear.d %0 1422 move.d %1,%0 1423 move.d %1,%0 1424 move %1,%0 1425 move %1,%0 1426 move %1,%0 1427 move %1,%0 1428 move %1,%0 1429 move %1,%0" 1430 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")]) 1431 1432;; Movem patterns. Primarily for use in function prologue and epilogue. 1433;; The V32 variants have an ordering matching the expectations of the 1434;; standard names "load_multiple" and "store_multiple"; pre-v32 movem 1435;; store R0 in the highest memory location. 1436 1437(define_expand "load_multiple" 1438 [(match_operand:SI 0 "register_operand" "") 1439 (match_operand:SI 1 "memory_operand" "") 1440 (match_operand:SI 2 "const_int_operand" "")] 1441 "TARGET_V32" 1442{ 1443 rtx indreg; 1444 1445 /* Apparently the predicate isn't checked, so we need to do so 1446 manually. Once happened for libstdc++-v3 locale_facets.tcc. */ 1447 if (!MEM_P (operands[1])) 1448 FAIL; 1449 1450 indreg = XEXP (operands[1], 0); 1451 1452 if (GET_CODE (indreg) == POST_INC) 1453 indreg = XEXP (indreg, 0); 1454 if (!REG_P (indreg) 1455 || GET_CODE (operands[2]) != CONST_INT 1456 || !REG_P (operands[0]) 1457 || REGNO (operands[0]) != 0 1458 || INTVAL (operands[2]) > CRIS_SP_REGNUM 1459 || (int) REGNO (indreg) < INTVAL (operands[2])) 1460 FAIL; 1461 gcc_unreachable (); 1462 emit_insn (cris_gen_movem_load (operands[1], operands[2], 0)); 1463 DONE; 1464}) 1465 1466(define_expand "store_multiple" 1467 [(match_operand:SI 0 "memory_operand" "") 1468 (match_operand:SI 1 "register_operand" "") 1469 (match_operand:SI 2 "const_int_operand" "")] 1470 "TARGET_V32" 1471{ 1472 rtx indreg; 1473 1474 /* See load_multiple. */ 1475 if (!MEM_P (operands[0])) 1476 FAIL; 1477 1478 indreg = XEXP (operands[0], 0); 1479 1480 if (GET_CODE (indreg) == POST_INC) 1481 indreg = XEXP (indreg, 0); 1482 if (!REG_P (indreg) 1483 || GET_CODE (operands[2]) != CONST_INT 1484 || !REG_P (operands[1]) 1485 || REGNO (operands[1]) != 0 1486 || INTVAL (operands[2]) > CRIS_SP_REGNUM 1487 || (int) REGNO (indreg) < INTVAL (operands[2])) 1488 FAIL; 1489 gcc_unreachable (); 1490 cris_emit_movem_store (operands[0], operands[2], 0, false); 1491 DONE; 1492}) 1493 1494(define_insn "*cris_load_multiple" 1495 [(match_parallel 0 "cris_load_multiple_op" 1496 [(set (match_operand:SI 1 "register_operand" "=r,r") 1497 (match_operand:SI 2 "memory_operand" "Q,m"))])] 1498 "" 1499 "movem %O0,%o0" 1500 [(set_attr "cc" "none") 1501 (set_attr "slottable" "yes,no") 1502 ;; Not true, but setting the length to 0 causes return sequences (ret 1503 ;; movem) to have the cost they had when (return) included the movem 1504 ;; and reduces the performance penalty taken for needing to emit an 1505 ;; epilogue (in turn copied by bb-reorder) instead of return patterns. 1506 ;; FIXME: temporary change until all insn lengths are correctly 1507 ;; described. FIXME: have better target control over bb-reorder. 1508 (set_attr "length" "0")]) 1509 1510(define_insn "*cris_store_multiple" 1511 [(match_parallel 0 "cris_store_multiple_op" 1512 [(set (match_operand:SI 2 "memory_operand" "=Q,m") 1513 (match_operand:SI 1 "register_operand" "r,r"))])] 1514 "" 1515 "movem %o0,%O0" 1516 [(set_attr "cc" "none") 1517 (set_attr "slottable" "yes,no")]) 1518 1519 1520;; Sign- and zero-extend insns with standard names. 1521;; Those for integer source operand are ordered with the widest source 1522;; type first. 1523 1524;; Sign-extend. 1525 1526(define_insn "extendsidi2" 1527 [(set (match_operand:DI 0 "register_operand" "=r") 1528 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))] 1529 "" 1530 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0") 1531 1532(define_insn "extend<mode>di2" 1533 [(set (match_operand:DI 0 "register_operand" "=r") 1534 (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))] 1535 "" 1536 "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0") 1537 1538(define_insn "extend<mode>si2" 1539 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1540 (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))] 1541 "" 1542 "movs<m> %1,%0" 1543 [(set_attr "slottable" "yes,yes,no")]) 1544 1545;; To do a byte->word extension, extend to dword, except that the top half 1546;; of the register will be clobbered. FIXME: Perhaps this is not needed. 1547 1548(define_insn "extendqihi2" 1549 [(set (match_operand:HI 0 "register_operand" "=r,r,r") 1550 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))] 1551 "" 1552 "movs.b %1,%0" 1553 [(set_attr "slottable" "yes,yes,no")]) 1554 1555 1556;; Zero-extend. The DImode ones are synthesized by gcc, so we don't 1557;; specify them here. 1558 1559(define_insn "zero_extend<mode>si2" 1560 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1561 (zero_extend:SI 1562 (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))] 1563 "" 1564 "movu<m> %1,%0" 1565 [(set_attr "slottable" "yes,yes,no")]) 1566 1567;; Same comment as sign-extend QImode to HImode above applies. 1568 1569(define_insn "zero_extendqihi2" 1570 [(set (match_operand:HI 0 "register_operand" "=r,r,r") 1571 (zero_extend:HI 1572 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))] 1573 "" 1574 "movu.b %1,%0" 1575 [(set_attr "slottable" "yes,yes,no")]) 1576 1577;; All kinds of arithmetic and logical instructions. 1578;; 1579;; First, anonymous patterns to match addressing modes with 1580;; side-effects. 1581;; 1582;; op.S [rx=ry+I],rz; (add, sub, or, and, bound). 1583;; 1584;; [rx=ry+rz.S] 1585 1586(define_insn "*op_side<mode>_biap" 1587 [(set (match_operand:BWD 0 "register_operand" "=r,r") 1588 (match_operator:BWD 1589 6 "cris_orthogonal_operator" 1590 [(match_operand:BWD 1 "register_operand" "0,0") 1591 (mem:BWD (plus:SI 1592 (mult:SI (match_operand:SI 2 "register_operand" "r,r") 1593 (match_operand:SI 3 "const_int_operand" "n,n")) 1594 (match_operand:SI 4 "register_operand" "r,r")))])) 1595 (set (match_operand:SI 5 "register_operand" "=*4,r") 1596 (plus:SI (mult:SI (match_dup 2) 1597 (match_dup 3)) 1598 (match_dup 4)))] 1599 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" 1600 "@ 1601 # 1602 %x6<m> [%5=%4+%2%T3],%0") 1603 1604;; [rx=ry+i] ([%4=%2+%3]) 1605 1606(define_insn "*op_side<mode>" 1607 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r") 1608 (match_operator:BWD 1609 5 "cris_orthogonal_operator" 1610 [(match_operand:BWD 1 "register_operand" "0,0,0,0,0") 1611 (mem:BWD (plus:SI 1612 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") 1613 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])) 1614 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") 1615 (plus:SI (match_dup 2) 1616 (match_dup 3)))] 1617 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" 1618{ 1619 if ((which_alternative == 0 || which_alternative == 3) 1620 && (!CONST_INT_P (operands[3]) 1621 || INTVAL (operands[3]) > 127 1622 || INTVAL (operands[3]) < -128 1623 || satisfies_constraint_N (operands[3]) 1624 || satisfies_constraint_J (operands[3]))) 1625 return "#"; 1626 if (which_alternative == 4) 1627 return "%x5.%s0 [%4=%3%S2],%0"; 1628 return "%x5<m> [%4=%2%S3],%0"; 1629}) 1630 1631;; To match all cases for commutative operations we may have to have the 1632;; following pattern for add, or & and. I do not know really, but it does 1633;; not break anything. 1634;; 1635;; FIXME: This really ought to be checked. 1636;; 1637;; op.S [rx=ry+I],rz; 1638;; 1639;; [rx=ry+rz.S] 1640 1641(define_insn "*op_swap_side<mode>_biap" 1642 [(set (match_operand:BWD 0 "register_operand" "=r,r") 1643 (match_operator:BWD 1644 6 "cris_commutative_orth_op" 1645 [(mem:BWD (plus:SI 1646 (mult:SI (match_operand:SI 2 "register_operand" "r,r") 1647 (match_operand:SI 3 "const_int_operand" "n,n")) 1648 (match_operand:SI 4 "register_operand" "r,r"))) 1649 (match_operand:BWD 1 "register_operand" "0,0")])) 1650 (set (match_operand:SI 5 "register_operand" "=*4,r") 1651 (plus:SI (mult:SI (match_dup 2) 1652 (match_dup 3)) 1653 (match_dup 4)))] 1654 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" 1655 "@ 1656 # 1657 %x6<m> [%5=%4+%2%T3],%0") 1658 1659;; [rx=ry+i] ([%4=%2+%3]) 1660;; FIXME: These could have anonymous mode for operand 0. 1661 1662;; QImode 1663 1664(define_insn "*op_swap_side<mode>" 1665 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r") 1666 (match_operator:BWD 1667 5 "cris_commutative_orth_op" 1668 [(mem:BWD 1669 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") 1670 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))) 1671 (match_operand:BWD 1 "register_operand" "0,0,0,0,0")])) 1672 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") 1673 (plus:SI (match_dup 2) 1674 (match_dup 3)))] 1675 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" 1676{ 1677 if ((which_alternative == 0 || which_alternative == 3) 1678 && (!CONST_INT_P (operands[3]) 1679 || INTVAL (operands[3]) > 127 1680 || INTVAL (operands[3]) < -128 1681 || satisfies_constraint_N (operands[3]) 1682 || satisfies_constraint_J (operands[3]))) 1683 return "#"; 1684 if (which_alternative == 4) 1685 return "%x5<m> [%4=%3%S2],%0"; 1686 return "%x5<m> [%4=%2%S3],%0"; 1687}) 1688 1689;; Add operations, standard names. 1690 1691;; Note that for the 'P' constraint, the high part can be -1 or 0. We 1692;; output the insn through the 'A' output modifier as "adds.w" and "addq", 1693;; respectively. 1694(define_expand "adddi3" 1695 [(set (match_operand:DI 0 "register_operand") 1696 (plus:DI (match_operand:DI 1 "register_operand") 1697 (match_operand:DI 2 "general_operand")))] 1698 "" 1699{ 1700 if (MEM_P (operands[2]) && TARGET_V32) 1701 operands[2] = force_reg (DImode, operands[2]); 1702}) 1703 1704(define_insn "*adddi3_non_v32" 1705 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r") 1706 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r") 1707 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))] 1708 "!TARGET_V32" 1709 "@ 1710 addq %2,%M0\;ax\;addq 0,%H0 1711 subq %n2,%M0\;ax\;subq 0,%H0 1712 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0 1713 add.d %M2,%M0\;ax\;add.d %H2,%H0 1714 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0") 1715 1716; It seems no use allowing a memory operand for this one, because we'd 1717; need a scratch register for incrementing the address. 1718(define_insn "*adddi3_v32" 1719 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r") 1720 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0") 1721 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r,n")))] 1722 "TARGET_V32" 1723 "@ 1724 addq %2,%M0\;addc 0,%H0 1725 subq %n2,%M0\;ax\;subq 0,%H0 1726 add%e2.%z2 %2,%M0\;addc %H2,%H0 1727 add.d %M2,%M0\;addc %H2,%H0 1728 add.d %M2,%M0\;addc %H2,%H0") 1729 1730(define_expand "add<mode>3" 1731 [(set (match_operand:BWD 0 "register_operand") 1732 (plus:BWD 1733 (match_operand:BWD 1 "register_operand") 1734 (match_operand:BWD 2 "general_operand")))] 1735 "" 1736 "") 1737 1738(define_insn "*addsi3_non_v32" 1739 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r, r,r, r") 1740 (plus:SI 1741 (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0, 0,r, r") 1742 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,!S,g,!To,0")))] 1743 1744;; The last constraint is due to that after reload, the '%' is not 1745;; honored, and canonicalization doesn't care about keeping the same 1746;; register as in destination. This will happen after insn splitting. 1747;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x 1748 1749 "!TARGET_V32" 1750{ 1751 switch (which_alternative) 1752 { 1753 case 0: 1754 case 1: 1755 return "add.d %2,%0"; 1756 case 2: 1757 return "addq %2,%0"; 1758 case 3: 1759 return "subq %n2,%0"; 1760 case 4: 1761 /* 'Known value', but not in -63..63. 1762 Check if addu/subu may be used. */ 1763 if (INTVAL (operands[2]) > 0) 1764 { 1765 if (INTVAL (operands[2]) < 256) 1766 return "addu.b %2,%0"; 1767 if (INTVAL (operands[2]) < 65536) 1768 return "addu.w %2,%0"; 1769 } 1770 else 1771 { 1772 if (INTVAL (operands[2]) >= -255) 1773 return "subu.b %n2,%0"; 1774 if (INTVAL (operands[2]) >= -65535) 1775 return "subu.w %n2,%0"; 1776 } 1777 return "add.d %2,%0"; 1778 case 5: 1779 { 1780 rtx tem = operands[2]; 1781 gcc_assert (GET_CODE (tem) == CONST); 1782 tem = XEXP (tem, 0); 1783 if (GET_CODE (tem) == PLUS 1784 && GET_CODE (XEXP (tem, 0)) == UNSPEC 1785 /* We don't allow CRIS_UNSPEC_PCREL here; we can't have a 1786 pc-relative operand in an add insn. */ 1787 && XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL 1788 && CONST_INT_P (XEXP (tem, 1))) 1789 tem = XEXP (tem, 0); 1790 gcc_assert (GET_CODE (tem) == UNSPEC); 1791 switch (XINT (tem, 1)) 1792 { 1793 case CRIS_UNSPEC_GOTREAD: 1794 case CRIS_UNSPEC_PLTGOTREAD: 1795 /* Using sign-extend mostly to be consistent with the 1796 indexed addressing mode. */ 1797 if (flag_pic == 1) 1798 return "adds.w %2,%0"; 1799 return "add.d %2,%0"; 1800 1801 case CRIS_UNSPEC_PLT_GOTREL: 1802 case CRIS_UNSPEC_GOTREL: 1803 return "add.d %2,%0"; 1804 default: 1805 gcc_unreachable (); 1806 } 1807 } 1808 case 6: 1809 return "add%u2 %2,%0"; 1810 case 7: 1811 return "add.d %2,%1,%0"; 1812 case 8: 1813 return "add.d %1,%0"; 1814 default: 1815 return "BOGUS addsi %2+%1 to %0"; 1816 } 1817} 1818 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no,yes")]) 1819 1820; FIXME: Check what's best: having the three-operand ACR alternative 1821; before or after the corresponding-operand2 alternative. Check for 1822; *all* insns. FIXME: constant constraint letter for -128..127. 1823(define_insn "*addsi3_v32" 1824 [(set (match_operand:SI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,!a,r,r,r,!a") 1825 (plus:SI 1826 (match_operand:SI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r, 0,0,0,r") 1827 (match_operand:SI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,L,L, P,n,g,g")))] 1828 "TARGET_V32" 1829 "@ 1830 add.d %2,%0 1831 addi %2.b,%1,%0 1832 add.d %2,%0 1833 addo.d %2,%1,%0 1834 addq %2,%0 1835 subq %n2,%0 1836 addoq %2,%1,%0 1837 adds.w %2,%0 1838 addo %2,%1,%0 1839 addu.w %2,%0 1840 add.d %2,%0 1841 add%u2 %2,%0 1842 addo.%Z2 %2,%1,%0" 1843 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no,no,no,no,no") 1844 (set_attr "cc" "*,none,*,none,*,*,none,*,none,*,*,*,none")]) 1845 1846(define_insn "*addhi3_non_v32" 1847 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r") 1848 (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r") 1849 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))] 1850 "!TARGET_V32" 1851 "@ 1852 add.w %2,%0 1853 add.w %2,%0 1854 addq %2,%0 1855 subq %n2,%0 1856 add.w %2,%0 1857 add.w %2,%1,%0" 1858 [(set_attr "slottable" "yes,yes,yes,yes,no,no") 1859 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) 1860 1861(define_insn "*addhi3_v32" 1862 [(set (match_operand:HI 0 "register_operand" "=r, !a,r,!a, r,r,!a,r,!a") 1863 (plus:HI 1864 (match_operand:HI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r") 1865 (match_operand:HI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,g,g")))] 1866 "TARGET_V32" 1867 "@ 1868 add.w %2,%0 1869 addi %2.b,%1,%0 1870 add.w %2,%0 1871 addo.w %2,%1,%0 1872 addq %2,%0 1873 subq %n2,%0 1874 addoq %2,%1,%0 1875 add.w %2,%0 1876 addo.w %2,%1,%0" 1877 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no") 1878 (set_attr "cc" "*,none,*,none,clobber,clobber,none,*,none")]) 1879 1880(define_insn "*addqi3_non_v32" 1881 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r") 1882 (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r") 1883 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))] 1884 "!TARGET_V32" 1885 "@ 1886 add.b %2,%0 1887 add.b %2,%0 1888 addq %2,%0 1889 subq %n2,%0 1890 subQ -%b2,%0 1891 add.b %2,%0 1892 add.b %2,%1,%0" 1893 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no") 1894 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")]) 1895 1896(define_insn "*addqi3_v32" 1897 [(set (match_operand:QI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,r,!a") 1898 (plus:QI 1899 (match_operand:QI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,0,r") 1900 (match_operand:QI 2 "general_operand" "r,r, Q>,Q>,J,N,NJ,O,g,g")))] 1901 "TARGET_V32" 1902 "@ 1903 add.b %2,%0 1904 addi %2.b,%1,%0 1905 add.b %2,%0 1906 addo.b %2,%1,%0 1907 addq %2,%0 1908 subq %n2,%0 1909 addoq %2,%1,%0 1910 subQ -%b2,%0 1911 add.b %2,%0 1912 addo.b %2,%1,%0" 1913 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,yes,no,no") 1914 (set_attr "cc" "*,none,*,none,clobber,clobber,none,clobber,*,none")]) 1915 1916;; Subtract. 1917;; 1918;; Note that because of insn canonicalization these will *seldom* but 1919;; rarely be used with a known constant as an operand. 1920 1921;; Note that for the 'P' constraint, the high part can be -1 or 0. We 1922;; output the insn through the 'D' output modifier as "subs.w" and "subq", 1923;; respectively. 1924(define_expand "subdi3" 1925 [(set (match_operand:DI 0 "register_operand") 1926 (minus:DI (match_operand:DI 1 "register_operand") 1927 (match_operand:DI 2 "general_operand")))] 1928 "" 1929{ 1930 if (TARGET_V32 && MEM_P (operands[2])) 1931 operands[2] = force_reg (DImode, operands[2]); 1932}) 1933 1934(define_insn "*subdi3_non_v32" 1935 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r") 1936 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r") 1937 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))] 1938 "!TARGET_V32" 1939 "@ 1940 subq %2,%M0\;ax\;subq 0,%H0 1941 addq %n2,%M0\;ax\;addq 0,%H0 1942 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0 1943 sub.d %M2,%M0\;ax\;sub.d %H2,%H0 1944 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0") 1945 1946(define_insn "*subdi3_v32" 1947 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r") 1948 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0") 1949 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r")))] 1950 "TARGET_V32" 1951 "@ 1952 subq %2,%M0\;ax\;subq 0,%H0 1953 addq %n2,%M0\;ax\;addq 0,%H0 1954 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0 1955 sub.d %M2,%M0\;ax\;sub.d %H2,%H0") 1956 1957(define_expand "sub<mode>3" 1958 [(set (match_operand:BWD 0 "register_operand") 1959 (minus:BWD 1960 (match_operand:BWD 1 "register_operand") 1961 (match_operand:BWD 2 "general_operand")))] 1962 "" 1963 "") 1964 1965(define_insn "*subsi3_non_v32" 1966 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r") 1967 (minus:SI 1968 (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r") 1969 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))] 1970 "!TARGET_V32" 1971 1972;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative. 1973;; But then again, %2 should not be negative. 1974 1975 "@ 1976 sub.d %2,%0 1977 sub.d %2,%0 1978 subq %2,%0 1979 addq %n2,%0 1980 sub%e2.%z2 %2,%0 1981 sub.d %2,%0 1982 sub.d %2,%0 1983 sub.d %2,%1,%0" 1984 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")]) 1985 1986(define_insn "*subsi3_v32" 1987 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r") 1988 (minus:SI 1989 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0") 1990 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g")))] 1991 "TARGET_V32" 1992 "@ 1993 sub.d %2,%0 1994 sub.d %2,%0 1995 subq %2,%0 1996 addq %n2,%0 1997 sub%e2.%z2 %2,%0 1998 sub.d %2,%0 1999 sub.d %2,%0" 2000 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")]) 2001 2002(define_insn "*sub<mode>3_nonv32" 2003 [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r") 2004 (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r") 2005 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))] 2006 "!TARGET_V32" 2007 "@ 2008 sub<m> %2,%0 2009 sub<m> %2,%0 2010 subq %2,%0 2011 addq %n2,%0 2012 sub<m> %2,%0 2013 sub<m> %2,%1,%0" 2014 [(set_attr "slottable" "yes,yes,yes,yes,no,no") 2015 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) 2016 2017(define_insn "*sub<mode>3_v32" 2018 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r") 2019 (minus:BW (match_operand:BW 1 "register_operand" "0,0,0,0,0") 2020 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g")))] 2021 "TARGET_V32" 2022 "@ 2023 sub<m> %2,%0 2024 sub<m> %2,%0 2025 subq %2,%0 2026 addq %n2,%0 2027 sub<m> %2,%0" 2028 [(set_attr "slottable" "yes,yes,yes,yes,no") 2029 (set_attr "cc" "normal,normal,clobber,clobber,normal")]) 2030 2031;; CRIS has some add/sub-with-sign/zero-extend instructions. 2032;; Although these perform sign/zero-extension to SImode, they are 2033;; equally applicable for the HImode case. 2034;; FIXME: Check; GCC should handle the widening. 2035;; Note that these must be located after the normal add/sub patterns, 2036;; so not to get constants into any less specific operands. 2037;; 2038;; Extend with add/sub and side-effect. 2039;; 2040;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend 2041;; 2042;; adds/subs/addu/subu bound [rx=ry+rz.S] 2043 2044;; QImode to HImode 2045;; FIXME: GCC should widen. 2046 2047(define_insn "*extopqihi_side_biap" 2048 [(set (match_operand:HI 0 "register_operand" "=r,r") 2049 (match_operator:HI 2050 6 "cris_additive_operand_extend_operator" 2051 [(match_operand:HI 1 "register_operand" "0,0") 2052 (match_operator:HI 2053 7 "cris_extend_operator" 2054 [(mem:QI (plus:SI 2055 (mult:SI (match_operand:SI 2 "register_operand" "r,r") 2056 (match_operand:SI 3 "const_int_operand" "n,n")) 2057 (match_operand:SI 4 "register_operand" "r,r")))])])) 2058 (set (match_operand:SI 5 "register_operand" "=*4,r") 2059 (plus:SI (mult:SI (match_dup 2) 2060 (match_dup 3)) 2061 (match_dup 4)))] 2062 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" 2063 "@ 2064 # 2065 %x6%e7.%m7 [%5=%4+%2%T3],%0") 2066 2067(define_insn "*extop<mode>si_side_biap" 2068 [(set (match_operand:SI 0 "register_operand" "=r,r") 2069 (match_operator:SI 2070 6 "cris_operand_extend_operator" 2071 [(match_operand:SI 1 "register_operand" "0,0") 2072 (match_operator:SI 2073 7 "cris_extend_operator" 2074 [(mem:BW (plus:SI 2075 (mult:SI (match_operand:SI 2 "register_operand" "r,r") 2076 (match_operand:SI 3 "const_int_operand" "n,n")) 2077 (match_operand:SI 4 "register_operand" "r,r")))])])) 2078 (set (match_operand:SI 5 "register_operand" "=*4,r") 2079 (plus:SI (mult:SI (match_dup 2) 2080 (match_dup 3)) 2081 (match_dup 4)))] 2082 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND) 2083 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" 2084 "@ 2085 # 2086 %x6%e7<m> [%5=%4+%2%T3],%0") 2087 2088 2089;; [rx=ry+i] 2090 2091;; QImode to HImode 2092 2093(define_insn "*extopqihi_side" 2094 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") 2095 (match_operator:HI 2096 5 "cris_additive_operand_extend_operator" 2097 [(match_operand:HI 1 "register_operand" "0,0,0,0,0") 2098 (match_operator:HI 2099 6 "cris_extend_operator" 2100 [(mem:QI 2101 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") 2102 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r") 2103 ))])])) 2104 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") 2105 (plus:SI (match_dup 2) 2106 (match_dup 3)))] 2107 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" 2108{ 2109 if ((which_alternative == 0 || which_alternative == 3) 2110 && (!CONST_INT_P (operands[3]) 2111 || INTVAL (operands[3]) > 127 2112 || INTVAL (operands[3]) < -128 2113 || satisfies_constraint_N (operands[3]) 2114 || satisfies_constraint_J (operands[3]))) 2115 return "#"; 2116 if (which_alternative == 4) 2117 return "%x5%E6.%m6 [%4=%3%S2],%0"; 2118 return "%x5%E6.%m6 [%4=%2%S3],%0"; 2119}) 2120 2121(define_insn "*extop<mode>si_side" 2122 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") 2123 (match_operator:SI 2124 5 "cris_operand_extend_operator" 2125 [(match_operand:SI 1 "register_operand" "0,0,0,0,0") 2126 (match_operator:SI 2127 6 "cris_extend_operator" 2128 [(mem:BW 2129 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") 2130 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r") 2131 ))])])) 2132 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") 2133 (plus:SI (match_dup 2) 2134 (match_dup 3)))] 2135 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) 2136 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" 2137{ 2138 if ((which_alternative == 0 || which_alternative == 3) 2139 && (!CONST_INT_P (operands[3]) 2140 || INTVAL (operands[3]) > 127 2141 || INTVAL (operands[3]) < -128 2142 || satisfies_constraint_N (operands[3]) 2143 || satisfies_constraint_J (operands[3]))) 2144 return "#"; 2145 if (which_alternative == 4) 2146 return "%x5%E6<m> [%4=%3%S2],%0"; 2147 return "%x5%E6<m> [%4=%2%S3],%0"; 2148}) 2149 2150 2151;; As with op.S we may have to add special pattern to match commuted 2152;; operands to adds/addu and bound 2153;; 2154;; adds/addu/bound [rx=ry+rz.S] 2155 2156;; QImode to HImode 2157;; FIXME: GCC should widen. 2158 2159(define_insn "*extopqihi_swap_side_biap" 2160 [(set (match_operand:HI 0 "register_operand" "=r,r") 2161 (plus:HI 2162 (match_operator:HI 2163 6 "cris_extend_operator" 2164 [(mem:QI (plus:SI 2165 (mult:SI (match_operand:SI 2 "register_operand" "r,r") 2166 (match_operand:SI 3 "const_int_operand" "n,n")) 2167 (match_operand:SI 4 "register_operand" "r,r")))]) 2168 (match_operand:HI 1 "register_operand" "0,0"))) 2169 (set (match_operand:SI 5 "register_operand" "=*4,r") 2170 (plus:SI (mult:SI (match_dup 2) 2171 (match_dup 3)) 2172 (match_dup 4)))] 2173 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" 2174 "@ 2175 # 2176 add%e6.b [%5=%4+%2%T3],%0") 2177 2178(define_insn "*extop<mode>si_swap_side_biap" 2179 [(set (match_operand:SI 0 "register_operand" "=r,r") 2180 (match_operator:SI 2181 7 "cris_plus_or_bound_operator" 2182 [(match_operator:SI 2183 6 "cris_extend_operator" 2184 [(mem:BW (plus:SI 2185 (mult:SI (match_operand:SI 2 "register_operand" "r,r") 2186 (match_operand:SI 3 "const_int_operand" "n,n")) 2187 (match_operand:SI 4 "register_operand" "r,r")))]) 2188 (match_operand:SI 1 "register_operand" "0,0")])) 2189 (set (match_operand:SI 5 "register_operand" "=*4,r") 2190 (plus:SI (mult:SI (match_dup 2) 2191 (match_dup 3)) 2192 (match_dup 4)))] 2193 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) 2194 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" 2195 "@ 2196 # 2197 %x7%E6<m> [%5=%4+%2%T3],%0") 2198 2199;; [rx=ry+i] 2200;; FIXME: GCC should widen. 2201 2202;; QImode to HImode 2203 2204(define_insn "*extopqihi_swap_side" 2205 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") 2206 (plus:HI 2207 (match_operator:HI 2208 5 "cris_extend_operator" 2209 [(mem:QI (plus:SI 2210 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") 2211 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]) 2212 (match_operand:HI 1 "register_operand" "0,0,0,0,0"))) 2213 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") 2214 (plus:SI (match_dup 2) 2215 (match_dup 3)))] 2216 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" 2217{ 2218 if ((which_alternative == 0 || which_alternative == 3) 2219 && (!CONST_INT_P (operands[3]) 2220 || INTVAL (operands[3]) > 127 2221 || INTVAL (operands[3]) < -128 2222 || satisfies_constraint_N (operands[3]) 2223 || satisfies_constraint_J (operands[3]))) 2224 return "#"; 2225 if (which_alternative == 4) 2226 return "add%e5.b [%4=%3%S2],%0"; 2227 return "add%e5.b [%4=%2%S3],%0"; 2228}) 2229 2230(define_insn "*extop<mode>si_swap_side" 2231 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") 2232 (match_operator:SI 2233 6 "cris_plus_or_bound_operator" 2234 [(match_operator:SI 2235 5 "cris_extend_operator" 2236 [(mem:BW (plus:SI 2237 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") 2238 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]) 2239 (match_operand:SI 1 "register_operand" "0,0,0,0,0")])) 2240 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") 2241 (plus:SI (match_dup 2) 2242 (match_dup 3)))] 2243 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND) 2244 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" 2245{ 2246 if ((which_alternative == 0 || which_alternative == 3) 2247 && (!CONST_INT_P (operands[3]) 2248 || INTVAL (operands[3]) > 127 2249 || INTVAL (operands[3]) < -128 2250 || satisfies_constraint_N (operands[3]) 2251 || satisfies_constraint_J (operands[3]))) 2252 return "#"; 2253 if (which_alternative == 4) 2254 return \"%x6%E5.%m5 [%4=%3%S2],%0\"; 2255 return "%x6%E5<m> [%4=%2%S3],%0"; 2256}) 2257 2258;; Extend versions (zero/sign) of normal add/sub (no side-effects). 2259 2260;; QImode to HImode 2261;; FIXME: GCC should widen. 2262 2263(define_insn "*extopqihi_non_v32" 2264 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") 2265 (match_operator:HI 2266 3 "cris_additive_operand_extend_operator" 2267 [(match_operand:HI 1 "register_operand" "0,0,0,r") 2268 (match_operator:HI 2269 4 "cris_extend_operator" 2270 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] 2271 "!TARGET_V32 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 2272 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" 2273 "@ 2274 %x3%E4.%m4 %2,%0 2275 %x3%E4.%m4 %2,%0 2276 %x3%E4.%m4 %2,%0 2277 %x3%E4.%m4 %2,%1,%0" 2278 [(set_attr "slottable" "yes,yes,no,no") 2279 (set_attr "cc" "clobber")]) 2280 2281(define_insn "*extopqihi_v32" 2282 [(set (match_operand:HI 0 "register_operand" "=r,r") 2283 (match_operator:HI 2284 3 "cris_additive_operand_extend_operator" 2285 [(match_operand:HI 1 "register_operand" "0,0") 2286 (match_operator:HI 2287 4 "cris_extend_operator" 2288 [(match_operand:QI 2 "nonimmediate_operand" "r,m")])]))] 2289 "TARGET_V32" 2290 "%x3%e4.%m4 %2,%0" 2291 [(set_attr "slottable" "yes") 2292 (set_attr "cc" "clobber")]) 2293 2294;; QImode to SImode 2295 2296(define_insn "*extop<mode>si_non_v32" 2297 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 2298 (match_operator:SI 2299 3 "cris_operand_extend_operator" 2300 [(match_operand:SI 1 "register_operand" "0,0,0,r") 2301 (match_operator:SI 2302 4 "cris_extend_operator" 2303 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] 2304 "!TARGET_V32 2305 && (GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND) 2306 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 2307 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" 2308 "@ 2309 %x3%E4<m> %2,%0 2310 %x3%E4<m> %2,%0 2311 %x3%E4<m> %2,%0 2312 %x3%E4<m> %2,%1,%0" 2313 [(set_attr "slottable" "yes,yes,no,no")]) 2314 2315(define_insn "*extop<mode>si_v32" 2316 [(set (match_operand:SI 0 "register_operand" "=r,r") 2317 (match_operator:SI 2318 3 "cris_additive_operand_extend_operator" 2319 [(match_operand:SI 1 "register_operand" "0,0") 2320 (match_operator:SI 2321 4 "cris_extend_operator" 2322 [(match_operand:BW 2 "nonimmediate_operand" "r,m")])]))] 2323 "TARGET_V32" 2324 "%x3%e4.%m4 %2,%0" 2325 [(set_attr "slottable" "yes")]) 2326 2327;; As with the side-effect patterns, may have to have swapped operands for add. 2328;; For commutative operands, these are the canonical forms. 2329 2330;; QImode to HImode 2331 2332(define_insn "*addxqihi_swap_non_v32" 2333 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") 2334 (plus:HI 2335 (match_operator:HI 2336 3 "cris_extend_operator" 2337 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")]) 2338 (match_operand:HI 1 "register_operand" "0,0,0,r")))] 2339 "!TARGET_V32 && operands[1] != frame_pointer_rtx" 2340 "@ 2341 add%e3.b %2,%0 2342 add%e3.b %2,%0 2343 add%e3.b %2,%0 2344 add%e3.b %2,%1,%0" 2345 [(set_attr "slottable" "yes,yes,no,no") 2346 (set_attr "cc" "clobber")]) 2347 2348;; A case for v32, to catch the "addo" insn in addition to "adds". We 2349;; only care to match the canonical form; there should be no other. 2350 2351(define_insn "*addsbw_v32" 2352 [(set (match_operand:HI 0 "register_operand" "=r,r,!a") 2353 (plus:HI 2354 (sign_extend:HI 2355 (match_operand:QI 2 "nonimmediate_operand" "r,m,m")) 2356 (match_operand:HI 1 "register_operand" "0,0,r")))] 2357 "TARGET_V32" 2358 "@ 2359 adds.b %2,%0 2360 adds.b %2,%0 2361 addo.b %2,%1,%0" 2362 [(set_attr "slottable" "yes") 2363 (set_attr "cc" "clobber,clobber,none")]) 2364 2365(define_insn "*addubw_v32" 2366 [(set (match_operand:HI 0 "register_operand" "=r,r") 2367 (plus:HI 2368 (zero_extend:HI 2369 (match_operand:QI 2 "nonimmediate_operand" "r,m")) 2370 (match_operand:HI 1 "register_operand" "0,0")))] 2371 "TARGET_V32" 2372 "addu.b %2,%0" 2373 [(set_attr "slottable" "yes") 2374 (set_attr "cc" "clobber")]) 2375 2376(define_insn "*extop<mode>si_swap_non_v32" 2377 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 2378 (match_operator:SI 2379 4 "cris_plus_or_bound_operator" 2380 [(match_operator:SI 2381 3 "cris_extend_operator" 2382 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")]) 2383 (match_operand:SI 1 "register_operand" "0,0,0,r")]))] 2384 "!TARGET_V32 2385 && (GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND) 2386 && operands[1] != frame_pointer_rtx" 2387 "@ 2388 %x4%E3<m> %2,%0 2389 %x4%E3<m> %2,%0 2390 %x4%E3<m> %2,%0 2391 %x4%E3<m> %2,%1,%0" 2392 [(set_attr "slottable" "yes,yes,no,no")]) 2393 2394(define_insn "*adds<mode>_v32" 2395 [(set (match_operand:SI 0 "register_operand" "=r,r,!a") 2396 (plus:SI 2397 (sign_extend:SI 2398 (match_operand:BW 2 "nonimmediate_operand" "r,m,m")) 2399 (match_operand:SI 1 "register_operand" "0,0,r")))] 2400 "TARGET_V32" 2401 "@ 2402 adds<m> %2,%0 2403 adds<m> %2,%0 2404 addo<m> %2,%1,%0" 2405 [(set_attr "slottable" "yes") 2406 (set_attr "cc" "*,*,none")]) 2407 2408(define_insn "*addu<mode>_v32" 2409 [(set (match_operand:SI 0 "register_operand" "=r,r") 2410 (plus:SI 2411 (zero_extend:SI 2412 (match_operand:BW 2 "nonimmediate_operand" "r,m")) 2413 (match_operand:SI 1 "register_operand" "0,0")))] 2414 "TARGET_V32 && operands[1] != frame_pointer_rtx" 2415 "addu<m> %2,%0" 2416 [(set_attr "slottable" "yes")]) 2417 2418(define_insn "*bound<mode>_v32" 2419 [(set (match_operand:SI 0 "register_operand" "=r") 2420 (umin:SI 2421 (zero_extend:SI 2422 (match_operand:BW 2 "register_operand" "r")) 2423 (match_operand:SI 1 "register_operand" "0")))] 2424 "TARGET_V32 && operands[1] != frame_pointer_rtx" 2425 "bound<m> %2,%0" 2426 [(set_attr "slottable" "yes")]) 2427 2428;; This is the special case when we use what corresponds to the 2429;; instruction above in "casesi". Do *not* change it to use the generic 2430;; pattern and "REG 15" as pc; I did that and it led to madness and 2431;; maintenance problems: Instead of (as imagined) recognizing and removing 2432;; or replacing this pattern with something simpler, other variant 2433;; patterns were recognized or combined, including some prefix variants 2434;; where the value in pc is not that of the next instruction (which means 2435;; this instruction actually *is* special and *should* be marked as such). 2436;; When switching from the "generic pattern match" approach to this simpler 2437;; approach, there were insignificant differences in gcc, ipps and 2438;; product code, somehow due to scratching reload behind the ear or 2439;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger; 2440;; product code became .001% smaller but "looked better". The testcase 2441;; "ipps" was just different at register allocation). 2442;; 2443;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this 2444;; pattern with the default-label as the else, with the "if" being 2445;; index-is-less-than the max number of cases plus one. The default-label 2446;; is attached to the end of the case-table at time of output. 2447 2448(define_insn "*casesi_adds_w" 2449 [(set (pc) 2450 (if_then_else 2451 (ltu (match_operand:SI 0 "register_operand" "r") 2452 (match_operand:SI 1 "const_int_operand" "n")) 2453 (plus:SI (sign_extend:SI 2454 (mem:HI 2455 (plus:SI (mult:SI (match_dup 0) (const_int 2)) 2456 (pc)))) 2457 (pc)) 2458 (label_ref (match_operand 2 "" "")))) 2459 (use (label_ref (match_operand 3 "" "")))] 2460 "!TARGET_V32 && operands[0] != frame_pointer_rtx" 2461 "adds.w [$pc+%0.w],$pc" 2462 [(set_attr "cc" "clobber")]) 2463 2464;; For V32, we just have a jump, but we need to mark the table as used, 2465;; and the jump insn must have the if_then_else form expected by core 2466;; GCC. Since we don't want to prolong the lifetime of the original 2467;; index value, we compare against "unspec 0". It's a pity we have to 2468;; jump through to get the default label in place and to keep the jump 2469;; table around. FIXME: Look into it some time. 2470 2471(define_insn "*casesi_jump_v32" 2472 [(set (pc) 2473 (if_then_else 2474 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI) 2475 (match_operand:SI 0 "const_int_operand" "n")) 2476 (match_operand:SI 1 "register_operand" "r") 2477 (label_ref (match_operand 2 "" "")))) 2478 (use (label_ref (match_operand 3 "" "")))] 2479 "TARGET_V32" 2480 "jump %1%#" 2481 [(set_attr "cc" "clobber") 2482 (set_attr "slottable" "has_slot")]) 2483 2484;; Multiply instructions. 2485 2486;; Sometimes powers of 2 (which are normally canonicalized to a 2487;; left-shift) appear here, as a result of address reloading. 2488;; As a special, for values 3 and 5, we can match with an addi, so add those. 2489;; 2490;; FIXME: This may be unnecessary now. 2491;; Explicitly named for convenience of having a gen_... function. 2492 2493(define_insn "addi_mul" 2494 [(set (match_operand:SI 0 "register_operand" "=r") 2495 (mult:SI 2496 (match_operand:SI 1 "register_operand" "%0") 2497 (match_operand:SI 2 "const_int_operand" "n")))] 2498 "operands[0] != frame_pointer_rtx 2499 && operands[1] != frame_pointer_rtx 2500 && CONST_INT_P (operands[2]) 2501 && (INTVAL (operands[2]) == 2 2502 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3 2503 || INTVAL (operands[2]) == 5)" 2504{ 2505 if (INTVAL (operands[2]) == 2) 2506 return "lslq 1,%0"; 2507 else if (INTVAL (operands[2]) == 4) 2508 return "lslq 2,%0"; 2509 else if (INTVAL (operands[2]) == 3) 2510 return "addi %0.w,%0"; 2511 else if (INTVAL (operands[2]) == 5) 2512 return "addi %0.d,%0"; 2513 return "BAD: adr_mulsi: %0=%1*%2"; 2514} 2515[(set_attr "slottable" "yes") 2516 ;; No flags are changed if this insn is "addi", but it does not seem 2517 ;; worth the trouble to distinguish that to the lslq cases. 2518 (set_attr "cc" "clobber")]) 2519 2520;; The addi insn as it is normally used. 2521 2522;; Make the ACR alternative taste bad enough to not choose it as a 2523;; preference to avoid spilling problems (unwind-dw2-fde.c at build). 2524;; FIXME: Revisit for new register allocator. 2525 2526(define_insn "*addi" 2527 [(set (match_operand:SI 0 "register_operand" "=r,!a") 2528 (plus:SI 2529 (mult:SI (match_operand:SI 2 "register_operand" "r,r") 2530 (match_operand:SI 3 "const_int_operand" "n,n")) 2531 (match_operand:SI 1 "register_operand" "0,r")))] 2532 "operands[0] != frame_pointer_rtx 2533 && operands[1] != frame_pointer_rtx 2534 && CONST_INT_P (operands[3]) 2535 && (INTVAL (operands[3]) == 1 2536 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)" 2537 "@ 2538 addi %2%T3,%0 2539 addi %2%T3,%1,%0" 2540 [(set_attr "slottable" "yes") 2541 (set_attr "cc" "none")]) 2542 2543;; The mstep instruction. Probably not useful by itself; it's to 2544;; non-linear wrt. the other insns. We used to expand to it, so at least 2545;; it's correct. 2546 2547(define_insn "mstep_shift" 2548 [(set (match_operand:SI 0 "register_operand" "=r") 2549 (if_then_else:SI 2550 (lt:SI (cc0) (const_int 0)) 2551 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") 2552 (const_int 1)) 2553 (match_operand:SI 2 "register_operand" "r")) 2554 (ashift:SI (match_operand:SI 3 "register_operand" "0") 2555 (const_int 1))))] 2556 "!TARGET_V32" 2557 "mstep %2,%0" 2558 [(set_attr "slottable" "yes")]) 2559 2560;; When illegitimate addresses are legitimized, sometimes gcc forgets 2561;; to canonicalize the multiplications. 2562;; 2563;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc. 2564 2565(define_insn "mstep_mul" 2566 [(set (match_operand:SI 0 "register_operand" "=r") 2567 (if_then_else:SI 2568 (lt:SI (cc0) (const_int 0)) 2569 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0") 2570 (const_int 2)) 2571 (match_operand:SI 2 "register_operand" "r")) 2572 (mult:SI (match_operand:SI 3 "register_operand" "0") 2573 (const_int 2))))] 2574 "!TARGET_V32 2575 && operands[0] != frame_pointer_rtx 2576 && operands[1] != frame_pointer_rtx 2577 && operands[2] != frame_pointer_rtx 2578 && operands[3] != frame_pointer_rtx" 2579 "mstep %2,%0" 2580 [(set_attr "slottable" "yes")]) 2581 2582(define_insn "<u>mul<s><mode>3" 2583 [(set (match_operand:WD 0 "register_operand" "=r") 2584 (mult:WD 2585 (szext:WD (match_operand:<S> 1 "register_operand" "%0")) 2586 (szext:WD (match_operand:<S> 2 "register_operand" "r")))) 2587 (clobber (match_scratch:SI 3 "=h"))] 2588 "TARGET_HAS_MUL_INSNS" 2589 "%!mul<su><mm> %2,%0" 2590 [(set (attr "slottable") 2591 (if_then_else (match_test "TARGET_MUL_BUG") 2592 (const_string "no") 2593 (const_string "yes"))) 2594 ;; For umuls.[bwd] it's just N unusable here, but let's be safe. 2595 ;; For muls.b, this really extends to SImode, so cc should be 2596 ;; considered clobbered. 2597 ;; For muls.w, it's just N unusable here, but let's be safe. 2598 (set_attr "cc" "clobber")]) 2599 2600;; Note that gcc does not make use of such a thing as umulqisi3. It gets 2601;; confused and will erroneously use it instead of umulhisi3, failing (at 2602;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels. 2603;; Inspection of optab code shows that there must be only one widening 2604;; multiplication per mode widened to. 2605 2606(define_insn "mulsi3" 2607 [(set (match_operand:SI 0 "register_operand" "=r") 2608 (mult:SI (match_operand:SI 1 "register_operand" "%0") 2609 (match_operand:SI 2 "register_operand" "r"))) 2610 (clobber (match_scratch:SI 3 "=h"))] 2611 "TARGET_HAS_MUL_INSNS" 2612 "%!muls.d %2,%0" 2613 [(set (attr "slottable") 2614 (if_then_else (match_test "TARGET_MUL_BUG") 2615 (const_string "no") 2616 (const_string "yes"))) 2617 ;; Just N unusable here, but let's be safe. 2618 (set_attr "cc" "clobber")]) 2619 2620;; A few multiply variations. 2621 2622;; When needed, we can get the high 32 bits from the overflow 2623;; register. We don't care to split and optimize these. 2624;; 2625;; Note that cc0 is still valid after the move-from-overflow-register 2626;; insn; no special precaution need to be taken in cris_notice_update_cc. 2627 2628(define_insn "<u>mulsidi3" 2629 [(set (match_operand:DI 0 "register_operand" "=r") 2630 (mult:DI 2631 (szext:DI (match_operand:SI 1 "register_operand" "%0")) 2632 (szext:DI (match_operand:SI 2 "register_operand" "r")))) 2633 (clobber (match_scratch:SI 3 "=h"))] 2634 "TARGET_HAS_MUL_INSNS" 2635 "%!mul<su>.d %2,%M0\;move $mof,%H0") 2636 2637;; These two patterns may be expressible by other means, perhaps by making 2638;; [u]?mulsidi3 a define_expand. 2639 2640;; Due to register allocation braindamage, the clobber 1,2 alternatives 2641;; cause a move into the clobbered register *before* the insn, then 2642;; after the insn, mof is moved too, rather than the clobber assigned 2643;; the last mof target. This became apparent when making MOF and SRP 2644;; visible registers, with the necessary tweak to smulsi3_highpart. 2645;; Because these patterns are used in division by constants, that damage 2646;; is visible (ipps regression tests). Therefore the last two 2647;; alternatives, "helping" reload to avoid an unnecessary move, but 2648;; punished by force of one "?". Check code from "int d (int a) {return 2649;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit. 2650 2651(define_insn "<su>mulsi3_highpart" 2652 [(set (match_operand:SI 0 "register_operand" "=h,h,?r,?r") 2653 (truncate:SI 2654 (lshiftrt:DI 2655 (mult:DI 2656 (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r")) 2657 (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0"))) 2658 (const_int 32)))) 2659 (clobber (match_scratch:SI 3 "=1,2,h,h"))] 2660 "TARGET_HAS_MUL_INSNS" 2661 "@ 2662 %!mul<su>.d %2,%1 2663 %!mul<su>.d %1,%2 2664 %!mul<su>.d %2,%1\;move $mof,%0 2665 %!mul<su>.d %1,%2\;move $mof,%0" 2666 [(set_attr "slottable" "yes,yes,no,no") 2667 (set_attr "cc" "clobber")]) 2668 2669;; Divide and modulus instructions. CRIS only has a step instruction. 2670 2671(define_insn "dstep_shift" 2672 [(set (match_operand:SI 0 "register_operand" "=r") 2673 (if_then_else:SI 2674 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") 2675 (const_int 1)) 2676 (match_operand:SI 2 "register_operand" "r")) 2677 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0") 2678 (const_int 1)) 2679 (match_operand:SI 4 "register_operand" "2")) 2680 (ashift:SI (match_operand:SI 5 "register_operand" "0") 2681 (const_int 1))))] 2682 "" 2683 "dstep %2,%0" 2684 [(set_attr "slottable" "yes") 2685 (set_attr "cc" "noov32")]) 2686 2687;; Here's a variant with mult instead of ashift. 2688;; 2689;; FIXME: This should be investigated. Which one matches through combination? 2690 2691(define_insn "dstep_mul" 2692 [(set (match_operand:SI 0 "register_operand" "=r") 2693 (if_then_else:SI 2694 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0") 2695 (const_int 2)) 2696 (match_operand:SI 2 "register_operand" "r")) 2697 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0") 2698 (const_int 2)) 2699 (match_operand:SI 4 "register_operand" "2")) 2700 (mult:SI (match_operand:SI 5 "register_operand" "0") 2701 (const_int 2))))] 2702 "operands[0] != frame_pointer_rtx 2703 && operands[1] != frame_pointer_rtx 2704 && operands[2] != frame_pointer_rtx 2705 && operands[3] != frame_pointer_rtx" 2706 "dstep %2,%0" 2707 [(set_attr "slottable" "yes") 2708 (set_attr "cc" "noov32")]) 2709 2710;; Logical operators. 2711 2712;; Bitwise "and". 2713 2714;; There is no use in defining "anddi3", because gcc can expand this by 2715;; itself, and make reasonable code without interference. 2716 2717;; If the first operand is memory or a register and is the same as the 2718;; second operand, and the third operand is -256 or -65536, we can use 2719;; CLEAR instead. Or, if the first operand is a register, and the third 2720;; operand is 255 or 65535, we can zero_extend. 2721;; GCC isn't smart enough to recognize these cases (yet), and they seem 2722;; to be common enough to be worthwhile. 2723;; FIXME: This should be made obsolete. 2724 2725(define_expand "andsi3" 2726 [(set (match_operand:SI 0 "nonimmediate_operand" "") 2727 (and:SI (match_operand:SI 1 "nonimmediate_operand" "") 2728 (match_operand:SI 2 "general_operand" "")))] 2729 "" 2730{ 2731 if (! (CONST_INT_P (operands[2]) 2732 && (((INTVAL (operands[2]) == -256 2733 || INTVAL (operands[2]) == -65536) 2734 && rtx_equal_p (operands[1], operands[0])) 2735 || ((INTVAL (operands[2]) == 255 2736 || INTVAL (operands[2]) == 65535) 2737 && REG_P (operands[0]))))) 2738 { 2739 /* Make intermediate steps if operand0 is not a register or 2740 operand1 is not a register, and hope that the reload pass will 2741 make something useful out of it. Note that the operands are 2742 *not* canonicalized. For the moment, I chicken out on this, 2743 because all or most ports do not describe 'and' with 2744 canonicalized operands, and I seem to remember magic in reload, 2745 checking that operand1 has constraint '%0', in which case 2746 operand0 and operand1 must have similar predicates. 2747 FIXME: Investigate. */ 2748 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); 2749 rtx reg1 = operands[1]; 2750 2751 if (! REG_P (reg1)) 2752 { 2753 emit_move_insn (reg0, reg1); 2754 reg1 = reg0; 2755 } 2756 2757 emit_insn (gen_rtx_SET (SImode, reg0, 2758 gen_rtx_AND (SImode, reg1, operands[2]))); 2759 2760 /* Make sure we get the right *final* destination. */ 2761 if (! REG_P (operands[0])) 2762 emit_move_insn (operands[0], reg0); 2763 2764 DONE; 2765 } 2766}) 2767 2768;; Some special cases of andsi3. 2769 2770(define_insn "*andsi_movu" 2771 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 2772 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To") 2773 (match_operand:SI 2 "const_int_operand" "n,n,n")))] 2774 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535) 2775 && !side_effects_p (operands[1])" 2776 "movu.%z2 %1,%0" 2777 [(set_attr "slottable" "yes,yes,no")]) 2778 2779(define_insn "*andsi_clear" 2780 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To") 2781 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") 2782 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))] 2783 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256) 2784 && !side_effects_p (operands[0])" 2785 "@ 2786 cLear.b %0 2787 cLear.w %0 2788 cLear.b %0 2789 cLear.w %0 2790 cLear.b %0 2791 cLear.w %0" 2792 [(set_attr "slottable" "yes,yes,yes,yes,no,no") 2793 (set_attr "cc" "none")]) 2794 2795;; This is a catch-all pattern, taking care of everything that was not 2796;; matched in the insns above. 2797;; 2798;; Sidenote: the tightening from "nonimmediate_operand" to 2799;; "register_operand" for operand 1 actually increased the register 2800;; pressure (worse code). That will hopefully change with an 2801;; improved reload pass. 2802 2803(define_insn "*expanded_andsi_non_v32" 2804 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r") 2805 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r") 2806 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))] 2807 "!TARGET_V32" 2808 "@ 2809 andq %2,%0 2810 and.d %2,%0 2811 and.d %2,%0 2812 and.d %2,%0 2813 and.d %2,%1,%0" 2814 [(set_attr "slottable" "yes,yes,yes,no,no")]) 2815 2816(define_insn "*expanded_andsi_v32" 2817 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 2818 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0") 2819 (match_operand:SI 2 "general_operand" "I,r,Q>,g")))] 2820 "TARGET_V32" 2821 "@ 2822 andq %2,%0 2823 and.d %2,%0 2824 and.d %2,%0 2825 and.d %2,%0" 2826 [(set_attr "slottable" "yes,yes,yes,no") 2827 (set_attr "cc" "noov32")]) 2828 2829;; For both QI and HI we may use the quick patterns. This results in 2830;; useless condition codes, but that is used rarely enough for it to 2831;; normally be a win (could check ahead for use of cc0, but seems to be 2832;; more pain than win). 2833 2834;; FIXME: See note for andsi3 2835 2836(define_expand "andhi3" 2837 [(set (match_operand:HI 0 "nonimmediate_operand" "") 2838 (and:HI (match_operand:HI 1 "nonimmediate_operand" "") 2839 (match_operand:HI 2 "general_operand" "")))] 2840 "" 2841{ 2842 if (! (CONST_INT_P (operands[2]) 2843 && (((INTVAL (operands[2]) == -256 2844 || INTVAL (operands[2]) == 65280) 2845 && rtx_equal_p (operands[1], operands[0])) 2846 || (INTVAL (operands[2]) == 255 2847 && REG_P (operands[0]))))) 2848 { 2849 /* See comment for andsi3. */ 2850 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode); 2851 rtx reg1 = operands[1]; 2852 2853 if (! REG_P (reg1)) 2854 { 2855 emit_move_insn (reg0, reg1); 2856 reg1 = reg0; 2857 } 2858 2859 emit_insn (gen_rtx_SET (HImode, reg0, 2860 gen_rtx_AND (HImode, reg1, operands[2]))); 2861 2862 /* Make sure we get the right destination. */ 2863 if (! REG_P (operands[0])) 2864 emit_move_insn (operands[0], reg0); 2865 2866 DONE; 2867 } 2868}) 2869 2870;; Some fast andhi3 special cases. 2871 2872(define_insn "*andhi_movu" 2873 [(set (match_operand:HI 0 "register_operand" "=r,r,r") 2874 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To") 2875 (const_int 255)))] 2876 "!side_effects_p (operands[1])" 2877 "mOvu.b %1,%0" 2878 [(set_attr "slottable" "yes,yes,no")]) 2879 2880(define_insn "*andhi_clear" 2881 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To") 2882 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0") 2883 (const_int -256)))] 2884 "!side_effects_p (operands[0])" 2885 "cLear.b %0" 2886 [(set_attr "slottable" "yes,yes,no") 2887 (set_attr "cc" "none")]) 2888 2889;; Catch-all andhi3 pattern. 2890 2891(define_insn "*expanded_andhi_non_v32" 2892 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r") 2893 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r") 2894 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))] 2895 2896;; Sidenote: the tightening from "general_operand" to 2897;; "register_operand" for operand 1 actually increased the register 2898;; pressure (worse code). That will hopefully change with an 2899;; improved reload pass. 2900 2901 "!TARGET_V32" 2902 "@ 2903 andq %2,%0 2904 and.w %2,%0 2905 and.w %2,%0 2906 and.w %2,%0 2907 anDq %b2,%0 2908 and.w %2,%0 2909 and.w %2,%1,%0" 2910 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no") 2911 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")]) 2912 2913(define_insn "*expanded_andhi_v32" 2914 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r") 2915 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0") 2916 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))] 2917 "TARGET_V32" 2918 "@ 2919 andq %2,%0 2920 and.w %2,%0 2921 and.w %2,%0 2922 and.w %2,%0 2923 anDq %b2,%0 2924 and.w %2,%0" 2925 [(set_attr "slottable" "yes,yes,yes,no,yes,no") 2926 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")]) 2927 2928;; A strict_low_part pattern. 2929 2930;; Note the use of (match_dup 0) for the first operand of the operation 2931;; here. Reload can't handle an operand pair where one is read-write 2932;; and must match a read, like in: 2933;; (insn 80 79 81 4 2934;; (set (strict_low_part 2935;; (subreg:QI (reg/v:SI 0 r0 [orig:36 data ] [36]) 0)) 2936;; (and:QI 2937;; (subreg:QI (reg:SI 15 acr [orig:27 D.7531 ] [27]) 0) 2938;; (const_int -64 [0xf..fc0]))) x.c:126 147 {*andqi_lowpart_v32} 2939;; (nil)) 2940;; In theory, it could reload this as a movstrictqi of the register 2941;; operand at the and:QI to the destination register and change the 2942;; and:QI operand to the same as the read-write output operand and the 2943;; result would be recognized, but it doesn't recognize that's a valid 2944;; reload for a strict_low_part-destination; it just sees a "+" at the 2945;; destination constraints. Better than adding complexity to reload is 2946;; to follow the lead of m68k (see comment that begins with "These insns 2947;; must use MATCH_DUP") since prehistoric times and make it just a 2948;; match_dup. FIXME: a sanity-check in gen* to refuse an insn with 2949;; input-constraints matching input-output-constraints, e.g. "+r" <- "0". 2950 2951(define_insn "*andhi_lowpart_non_v32" 2952 [(set (strict_low_part 2953 (match_operand:HI 0 "register_operand" "+r,r,r")) 2954 (and:HI (match_dup 0) 2955 (match_operand:HI 1 "general_operand" "r,Q>,g")))] 2956 "!TARGET_V32" 2957 "@ 2958 and.w %1,%0 2959 and.w %1,%0 2960 and.w %1,%0" 2961 [(set_attr "slottable" "yes,yes,no")]) 2962 2963(define_insn "*andhi_lowpart_v32" 2964 [(set (strict_low_part 2965 (match_operand:HI 0 "register_operand" "+r,r,r")) 2966 (and:HI (match_dup 0) 2967 (match_operand:HI 1 "general_operand" "r,Q>,g")))] 2968 "TARGET_V32" 2969 "@ 2970 and.w %1,%0 2971 and.w %1,%0 2972 and.w %1,%0" 2973 [(set_attr "slottable" "yes,yes,no") 2974 (set_attr "cc" "noov32")]) 2975 2976(define_expand "andqi3" 2977 [(set (match_operand:QI 0 "register_operand") 2978 (and:QI (match_operand:QI 1 "register_operand") 2979 (match_operand:QI 2 "general_operand")))] 2980 "" 2981 "") 2982 2983(define_insn "*andqi3_non_v32" 2984 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r") 2985 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r") 2986 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))] 2987 "!TARGET_V32" 2988 "@ 2989 andq %2,%0 2990 and.b %2,%0 2991 and.b %2,%0 2992 andQ %b2,%0 2993 and.b %2,%0 2994 and.b %2,%1,%0" 2995 [(set_attr "slottable" "yes,yes,yes,yes,no,no") 2996 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")]) 2997 2998(define_insn "*andqi3_v32" 2999 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r") 3000 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0") 3001 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))] 3002 "TARGET_V32" 3003 "@ 3004 andq %2,%0 3005 and.b %2,%0 3006 and.b %2,%0 3007 andQ %b2,%0 3008 and.b %2,%0" 3009 [(set_attr "slottable" "yes,yes,yes,yes,no") 3010 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")]) 3011 3012(define_insn "*andqi_lowpart_non_v32" 3013 [(set (strict_low_part 3014 (match_operand:QI 0 "register_operand" "+r,r,r")) 3015 (and:QI (match_dup 0) 3016 (match_operand:QI 1 "general_operand" "r,Q>,g")))] 3017 "!TARGET_V32" 3018 "@ 3019 and.b %1,%0 3020 and.b %1,%0 3021 and.b %1,%0" 3022 [(set_attr "slottable" "yes,yes,no")]) 3023 3024(define_insn "*andqi_lowpart_v32" 3025 [(set (strict_low_part 3026 (match_operand:QI 0 "register_operand" "+r,r,r")) 3027 (and:QI (match_dup 0) 3028 (match_operand:QI 1 "general_operand" "r,Q>,g")))] 3029 "TARGET_V32" 3030 "@ 3031 and.b %1,%0 3032 and.b %1,%0 3033 and.b %1,%0" 3034 [(set_attr "slottable" "yes,yes,no") 3035 (set_attr "cc" "noov32")]) 3036 3037;; Bitwise or. 3038 3039;; Same comment as anddi3 applies here - no need for such a pattern. 3040 3041;; It seems there's no need to jump through hoops to get good code such as 3042;; with andsi3. 3043 3044(define_expand "ior<mode>3" 3045 [(set (match_operand:BWD 0 "register_operand") 3046 (ior:BWD (match_operand:BWD 1 "register_operand") 3047 (match_operand:BWD 2 "general_operand")))] 3048 "" 3049 "") 3050 3051(define_insn "*iorsi3_non_v32" 3052 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r") 3053 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r") 3054 (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))] 3055 "!TARGET_V32" 3056 "@ 3057 orq %2,%0 3058 or.d %2,%0 3059 or.d %2,%0 3060 oR.%s2 %2,%0 3061 or.d %2,%0 3062 or.d %2,%1,%0" 3063 [(set_attr "slottable" "yes,yes,yes,no,no,no") 3064 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")]) 3065 3066(define_insn "*iorsi3_v32" 3067 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") 3068 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0") 3069 (match_operand:SI 2 "general_operand" "I,r,Q>,n,g")))] 3070 "TARGET_V32" 3071 "@ 3072 orq %2,%0 3073 or.d %2,%0 3074 or.d %2,%0 3075 oR.%s2 %2,%0 3076 or.d %2,%0" 3077 [(set_attr "slottable" "yes,yes,yes,no,no") 3078 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")]) 3079 3080(define_insn "*iorhi3_non_v32" 3081 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r") 3082 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r") 3083 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))] 3084 "!TARGET_V32" 3085 "@ 3086 orq %2,%0 3087 or.w %2,%0 3088 or.w %2,%0 3089 or.w %2,%0 3090 oRq %b2,%0 3091 or.w %2,%0 3092 or.w %2,%1,%0" 3093 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no") 3094 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")]) 3095 3096(define_insn "*iorhi3_v32" 3097 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r") 3098 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0") 3099 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))] 3100 "TARGET_V32" 3101 "@ 3102 orq %2,%0 3103 or.w %2,%0 3104 or.w %2,%0 3105 or.w %2,%0 3106 oRq %b2,%0 3107 or.w %2,%0" 3108 [(set_attr "slottable" "yes,yes,yes,no,yes,no") 3109 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")]) 3110 3111(define_insn "*iorqi3_non_v32" 3112 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r") 3113 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r") 3114 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))] 3115 "!TARGET_V32" 3116 "@ 3117 orq %2,%0 3118 or.b %2,%0 3119 or.b %2,%0 3120 orQ %b2,%0 3121 or.b %2,%0 3122 or.b %2,%1,%0" 3123 [(set_attr "slottable" "yes,yes,yes,yes,no,no") 3124 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")]) 3125 3126(define_insn "*iorqi3_v32" 3127 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r") 3128 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0") 3129 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))] 3130 "TARGET_V32" 3131 "@ 3132 orq %2,%0 3133 or.b %2,%0 3134 or.b %2,%0 3135 orQ %b2,%0 3136 or.b %2,%0" 3137 [(set_attr "slottable" "yes,yes,yes,yes,no") 3138 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")]) 3139 3140;; Exclusive-or 3141 3142;; See comment about "anddi3" for xordi3 - no need for such a pattern. 3143;; FIXME: Do we really need the shorter variants? 3144 3145(define_insn "xorsi3" 3146 [(set (match_operand:SI 0 "register_operand" "=r") 3147 (xor:SI (match_operand:SI 1 "register_operand" "%0") 3148 (match_operand:SI 2 "register_operand" "r")))] 3149 "" 3150 "xor %2,%0" 3151 [(set_attr "slottable" "yes") 3152 (set_attr "cc" "noov32")]) 3153 3154(define_insn "xor<mode>3" 3155 [(set (match_operand:BW 0 "register_operand" "=r") 3156 (xor:BW (match_operand:BW 1 "register_operand" "%0") 3157 (match_operand:BW 2 "register_operand" "r")))] 3158 "" 3159 "xor %2,%0" 3160 [(set_attr "slottable" "yes") 3161 (set_attr "cc" "clobber")]) 3162 3163;; Negation insns. 3164 3165;; Questionable use, here mostly as a (slightly usable) define_expand 3166;; example. 3167 3168(define_expand "negsf2" 3169 [(set (match_dup 2) 3170 (match_dup 3)) 3171 (parallel [(set (match_operand:SF 0 "register_operand" "=r") 3172 (neg:SF (match_operand:SF 1 3173 "register_operand" "0"))) 3174 (use (match_dup 2))])] 3175 "" 3176{ 3177 operands[2] = gen_reg_rtx (SImode); 3178 operands[3] = GEN_INT (1 << 31); 3179}) 3180 3181(define_insn "*expanded_negsf2" 3182 [(set (match_operand:SF 0 "register_operand" "=r") 3183 (neg:SF (match_operand:SF 1 "register_operand" "0"))) 3184 (use (match_operand:SI 2 "register_operand" "r"))] 3185 "" 3186 "xor %2,%0" 3187 [(set_attr "slottable" "yes")]) 3188 3189;; No "negdi2" although we could make one up that may be faster than 3190;; the one in libgcc. 3191 3192(define_insn "neg<mode>2" 3193 [(set (match_operand:BWD 0 "register_operand" "=r") 3194 (neg:BWD (match_operand:BWD 1 "register_operand" "r")))] 3195 "" 3196 "neg<m> %1,%0" 3197 [(set_attr "slottable" "yes")]) 3198 3199;; One-complements. 3200 3201;; See comment on anddi3 - no need for a DImode pattern. 3202;; See also xor comment. 3203 3204(define_insn "one_cmplsi2" 3205 [(set (match_operand:SI 0 "register_operand" "=r") 3206 (not:SI (match_operand:SI 1 "register_operand" "0")))] 3207 "" 3208 "not %0" 3209 [(set_attr "slottable" "yes") 3210 (set_attr "cc" "noov32")]) 3211 3212(define_insn "one_cmpl<mode>2" 3213 [(set (match_operand:BW 0 "register_operand" "=r") 3214 (not:BW (match_operand:BW 1 "register_operand" "0")))] 3215 "" 3216 "not %0" 3217 [(set_attr "slottable" "yes") 3218 (set_attr "cc" "clobber")]) 3219 3220;; Arithmetic/Logical shift right (and SI left). 3221 3222(define_insn "<shlr>si3" 3223 [(set (match_operand:SI 0 "register_operand" "=r") 3224 (shift:SI (match_operand:SI 1 "register_operand" "0") 3225 (match_operand:SI 2 "nonmemory_operand" "Kcr")))] 3226 "" 3227{ 3228 if (REG_S_P (operands[2])) 3229 return "<slr>.d %2,%0"; 3230 3231 return "<slr>q %2,%0"; 3232} 3233 [(set_attr "slottable" "yes") 3234 (set_attr "cc" "noov32")]) 3235 3236;; Since gcc gets lost, and forgets to zero-extend the source (or mask 3237;; the destination) when it changes shifts of lower modes into SImode, 3238;; it is better to make these expands an anonymous patterns instead of 3239;; the more correct define_insns. This occurs when gcc thinks that is 3240;; is better to widen to SImode and use immediate shift count. 3241 3242;; FIXME: Is this legacy or still true for gcc >= 2.7.2? 3243 3244;; FIXME: Can't parametrize sign_extend and zero_extend (before 3245;; mentioning "shiftrt"), so we need two patterns. 3246(define_expand "ashr<mode>3" 3247 [(set (match_dup 3) 3248 (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" ""))) 3249 (set (match_dup 4) 3250 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" ""))) 3251 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4))) 3252 (set (match_operand:BW 0 "general_operand" "") 3253 (subreg:BW (match_dup 5) 0))] 3254 "" 3255{ 3256 int i; 3257 3258 for (i = 3; i < 6; i++) 3259 operands[i] = gen_reg_rtx (SImode); 3260}) 3261 3262(define_expand "lshr<mode>3" 3263 [(set (match_dup 3) 3264 (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" ""))) 3265 (set (match_dup 4) 3266 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" ""))) 3267 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4))) 3268 (set (match_operand:BW 0 "general_operand" "") 3269 (subreg:BW (match_dup 5) 0))] 3270 "" 3271{ 3272 int i; 3273 3274 for (i = 3; i < 6; i++) 3275 operands[i] = gen_reg_rtx (SImode); 3276}) 3277 3278(define_insn "*expanded_<shlr><mode>" 3279 [(set (match_operand:BW 0 "register_operand" "=r") 3280 (shiftrt:BW (match_operand:BW 1 "register_operand" "0") 3281 (match_operand:BW 2 "register_operand" "r")))] 3282 "" 3283 "<slr><m> %2,%0" 3284 [(set_attr "slottable" "yes") 3285 (set_attr "cc" "noov32")]) 3286 3287(define_insn "*<shlr><mode>_lowpart" 3288 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r")) 3289 (shiftrt:BW (match_dup 0) 3290 (match_operand:BW 1 "register_operand" "r")))] 3291 "" 3292 "<slr><m> %1,%0" 3293 [(set_attr "slottable" "yes") 3294 (set_attr "cc" "noov32")]) 3295 3296;; Arithmetic/logical shift left. 3297 3298;; For narrower modes than SI, we can use lslq although it makes cc 3299;; unusable. The win is that we do not have to reload the shift-count 3300;; into a register. 3301 3302(define_insn "ashl<mode>3" 3303 [(set (match_operand:BW 0 "register_operand" "=r,r") 3304 (ashift:BW (match_operand:BW 1 "register_operand" "0,0") 3305 (match_operand:BW 2 "nonmemory_operand" "r,Kc")))] 3306 "" 3307{ 3308 return 3309 (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > <nbitsm1>) 3310 ? "moveq 0,%0" 3311 : (CONSTANT_P (operands[2]) 3312 ? "lslq %2,%0" : "lsl<m> %2,%0"); 3313} 3314 [(set_attr "slottable" "yes") 3315 (set_attr "cc" "noov32,clobber")]) 3316 3317;; A strict_low_part matcher. 3318 3319(define_insn "*ashl<mode>_lowpart" 3320 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r")) 3321 (ashift:BW (match_dup 0) 3322 (match_operand:HI 1 "register_operand" "r")))] 3323 "" 3324 "lsl<m> %1,%0" 3325 [(set_attr "slottable" "yes") 3326 (set_attr "cc" "noov32")]) 3327 3328;; Various strange insns that gcc likes. 3329 3330;; Fortunately, it is simple to construct an abssf (although it may not 3331;; be very much used in practice). 3332 3333(define_insn "abssf2" 3334 [(set (match_operand:SF 0 "register_operand" "=r") 3335 (abs:SF (match_operand:SF 1 "register_operand" "0")))] 3336 "" 3337 "lslq 1,%0\;lsrq 1,%0") 3338 3339(define_insn "abssi2" 3340 [(set (match_operand:SI 0 "register_operand" "=r") 3341 (abs:SI (match_operand:SI 1 "register_operand" "r")))] 3342 "" 3343 "abs %1,%0" 3344 [(set_attr "slottable" "yes") 3345 (set_attr "cc" "noov32")]) 3346 3347;; FIXME: GCC should be able to do these expansions itself. 3348 3349(define_expand "abs<mode>2" 3350 [(set (match_dup 2) 3351 (sign_extend:SI (match_operand:BW 1 "general_operand" ""))) 3352 (set (match_dup 3) (abs:SI (match_dup 2))) 3353 (set (match_operand:BW 0 "register_operand" "") 3354 (subreg:BW (match_dup 3) 0))] 3355 "" 3356 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);") 3357 3358(define_insn "clzsi2" 3359 [(set (match_operand:SI 0 "register_operand" "=r") 3360 (clz:SI (match_operand:SI 1 "register_operand" "r")))] 3361 "TARGET_HAS_LZ" 3362 "lz %1,%0" 3363 [(set_attr "slottable" "yes") 3364 (set_attr "cc" "noov32")]) 3365 3366(define_insn "bswapsi2" 3367 [(set (match_operand:SI 0 "register_operand" "=r") 3368 (bswap:SI (match_operand:SI 1 "register_operand" "0")))] 3369 "TARGET_HAS_SWAP" 3370 "swapwb %0" 3371 [(set_attr "slottable" "yes") 3372 (set_attr "cc" "noov32")]) 3373 3374;; This instruction swaps all bits in a register. 3375;; That means that the most significant bit is put in the place 3376;; of the least significant bit, and so on. 3377 3378(define_insn "cris_swap_bits" 3379 [(set (match_operand:SI 0 "register_operand" "=r") 3380 (unspec:SI [(match_operand:SI 1 "register_operand" "0")] 3381 CRIS_UNSPEC_SWAP_BITS))] 3382 "TARGET_HAS_SWAP" 3383 "swapwbr %0" 3384 [(set_attr "slottable" "yes") 3385 (set_attr "cc" "noov32")]) 3386 3387;; Implement ctz using two instructions, one for bit swap and one for clz. 3388;; Defines a scratch register to avoid clobbering input. 3389 3390(define_expand "ctzsi2" 3391 [(set (match_dup 2) 3392 (match_operand:SI 1 "register_operand")) 3393 (set (match_dup 2) 3394 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS)) 3395 (set (match_operand:SI 0 "register_operand") 3396 (clz:SI (match_dup 2)))] 3397 "TARGET_HAS_LZ && TARGET_HAS_SWAP" 3398 "operands[2] = gen_reg_rtx (SImode);") 3399 3400;; Bound-insn. Defined to be the same as an unsigned minimum, which is an 3401;; operation supported by gcc. Used in casesi, but used now and then in 3402;; normal code too. 3403 3404(define_expand "uminsi3" 3405 [(set (match_operand:SI 0 "register_operand" "") 3406 (umin:SI (match_operand:SI 1 "register_operand" "") 3407 (match_operand:SI 2 "general_operand" "")))] 3408 "" 3409{ 3410 if (MEM_P (operands[2]) && TARGET_V32) 3411 operands[2] = force_reg (SImode, operands[2]); 3412}) 3413 3414(define_insn "*uminsi3_non_v32" 3415 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r") 3416 (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r") 3417 (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))] 3418 "!TARGET_V32" 3419{ 3420 if (CONST_INT_P (operands[2])) 3421 { 3422 /* Constant operands are zero-extended, so only 32-bit operands 3423 may be negative. */ 3424 if (INTVAL (operands[2]) >= 0) 3425 { 3426 if (INTVAL (operands[2]) < 256) 3427 return "bound.b %2,%0"; 3428 3429 if (INTVAL (operands[2]) < 65536) 3430 return "bound.w %2,%0"; 3431 } 3432 } 3433 else if (which_alternative == 3) 3434 return "bound.d %2,%1,%0"; 3435 3436 return "bound.d %2,%0"; 3437} 3438 [(set_attr "slottable" "yes,yes,no,no")]) 3439 3440(define_insn "*uminsi3_v32" 3441 [(set (match_operand:SI 0 "register_operand" "=r,r") 3442 (umin:SI (match_operand:SI 1 "register_operand" "%0,0") 3443 (match_operand:SI 2 "nonmemory_operand" "r,i")))] 3444 "TARGET_V32" 3445{ 3446 if (GET_CODE (operands[2]) == CONST_INT) 3447 { 3448 /* Constant operands are zero-extended, so only 32-bit operands 3449 may be negative. */ 3450 if (INTVAL (operands[2]) >= 0) 3451 { 3452 if (INTVAL (operands[2]) < 256) 3453 return "bound.b %2,%0"; 3454 3455 if (INTVAL (operands[2]) < 65536) 3456 return "bound.w %2,%0"; 3457 } 3458 } 3459 3460 return "bound.d %2,%0"; 3461} 3462 [(set_attr "slottable" "yes,no")]) 3463 3464;; Jump and branch insns. 3465 3466(define_insn "jump" 3467 [(set (pc) 3468 (label_ref (match_operand 0 "" "")))] 3469 "" 3470 "ba %l0%#" 3471 [(set_attr "slottable" "has_slot")]) 3472 3473;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant 3474;; here, since the insn is not recognized as an indirect jump by 3475;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to 3476;; change from general_operand to nonimmediate_operand (at least the docs 3477;; should be changed), but then again the pattern is called indirect_jump. 3478(define_expand "indirect_jump" 3479 [(set (pc) (match_operand:SI 0 "nonimmediate_operand"))] 3480 "" 3481{ 3482 if (TARGET_V32 && MEM_P (operands[0])) 3483 operands[0] = force_reg (SImode, operands[0]); 3484}) 3485 3486(define_insn "*indirect_jump_non_v32" 3487 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))] 3488 "!TARGET_V32" 3489 "jump %0") 3490 3491(define_insn "*indirect_jump_v32" 3492 [(set (pc) (match_operand:SI 0 "register_operand" "r"))] 3493 "TARGET_V32" 3494 "jump %0%#" 3495 [(set_attr "slottable" "has_slot")]) 3496 3497;; Return insn. Used whenever the epilogue is very simple; if it is only 3498;; a single ret or jump [sp+]. No allocated stack space or saved 3499;; registers are allowed. 3500;; Note that for this pattern, although named, it is ok to check the 3501;; context of the insn in the test, not only compiler switches. 3502 3503(define_expand "return" 3504 [(return)] 3505 "cris_simple_epilogue ()" 3506 "cris_expand_return (cris_return_address_on_stack ()); DONE;") 3507 3508(define_insn "*return_expanded" 3509 [(return)] 3510 "" 3511{ 3512 return cris_return_address_on_stack_for_return () 3513 ? "jump [$sp+]" : "ret%#"; 3514} 3515 [(set (attr "slottable") 3516 (if_then_else 3517 (match_test "cris_return_address_on_stack_for_return ()") 3518 (const_string "no") 3519 (const_string "has_return_slot")))]) 3520 3521(define_expand "prologue" 3522 [(const_int 0)] 3523 "TARGET_PROLOGUE_EPILOGUE" 3524 "cris_expand_prologue (); DONE;") 3525 3526;; Note that the (return) from the expander itself is always the last 3527;; insn in the epilogue. 3528(define_expand "epilogue" 3529 [(const_int 0)] 3530 "TARGET_PROLOGUE_EPILOGUE" 3531 "cris_expand_epilogue (); DONE;") 3532 3533;; Conditional branches. 3534 3535(define_expand "cbranch<mode>4" 3536 [(set (cc0) (compare 3537 (match_operand:BWD 1 "nonimmediate_operand") 3538 (match_operand:BWD 2 "general_operand"))) 3539 (set (pc) 3540 (if_then_else (match_operator 0 "ordered_comparison_operator" 3541 [(cc0) (const_int 0)]) 3542 (label_ref (match_operand 3 "" "")) 3543 (pc)))] 3544 "" 3545 "") 3546 3547(define_expand "cbranchdi4" 3548 [(set (cc0) 3549 (compare (match_operand:DI 1 "nonimmediate_operand" "") 3550 (match_operand:DI 2 "general_operand" ""))) 3551 (set (pc) 3552 (if_then_else (match_operator 0 "ordered_comparison_operator" 3553 [(cc0) (const_int 0)]) 3554 (label_ref (match_operand 3 "" "")) 3555 (pc)))] 3556 "" 3557{ 3558 if (TARGET_V32 && !REG_P (operands[1])) 3559 operands[1] = force_reg (DImode, operands[1]); 3560 if (TARGET_V32 && MEM_P (operands[2])) 3561 operands[2] = force_reg (DImode, operands[2]); 3562}) 3563 3564 3565;; We suffer from the same overflow-bit-gets-in-the-way problem as 3566;; e.g. m68k, so we have to check if overflow bit is set on all "signed" 3567;; conditions. 3568 3569(define_insn "b<ncond:code>" 3570 [(set (pc) 3571 (if_then_else (ncond (cc0) 3572 (const_int 0)) 3573 (label_ref (match_operand 0 "" "")) 3574 (pc)))] 3575 "" 3576 "b<CC> %l0%#" 3577 [(set_attr "slottable" "has_slot")]) 3578 3579(define_insn "b<ocond:code>" 3580 [(set (pc) 3581 (if_then_else (ocond (cc0) 3582 (const_int 0)) 3583 (label_ref (match_operand 0 "" "")) 3584 (pc)))] 3585 "" 3586{ 3587 return 3588 (cc_prev_status.flags & CC_NO_OVERFLOW) 3589 ? 0 : "b<CC> %l0%#"; 3590} 3591 [(set_attr "slottable" "has_slot")]) 3592 3593(define_insn "b<rcond:code>" 3594 [(set (pc) 3595 (if_then_else (rcond (cc0) 3596 (const_int 0)) 3597 (label_ref (match_operand 0 "" "")) 3598 (pc)))] 3599 "" 3600{ 3601 return 3602 (cc_prev_status.flags & CC_NO_OVERFLOW) 3603 ? "b<oCC> %l0%#" : "b<CC> %l0%#"; 3604} 3605 [(set_attr "slottable" "has_slot")]) 3606 3607;; Reversed anonymous patterns to the ones above, as mandated. 3608 3609(define_insn "*b<ncond:code>_reversed" 3610 [(set (pc) 3611 (if_then_else (ncond (cc0) 3612 (const_int 0)) 3613 (pc) 3614 (label_ref (match_operand 0 "" ""))))] 3615 "" 3616 "b<rCC> %l0%#" 3617 [(set_attr "slottable" "has_slot")]) 3618 3619(define_insn "*b<ocond:code>_reversed" 3620 [(set (pc) 3621 (if_then_else (ocond (cc0) 3622 (const_int 0)) 3623 (pc) 3624 (label_ref (match_operand 0 "" ""))))] 3625 "" 3626{ 3627 return 3628 (cc_prev_status.flags & CC_NO_OVERFLOW) 3629 ? 0 : "b<rCC> %l0%#"; 3630} 3631 [(set_attr "slottable" "has_slot")]) 3632 3633(define_insn "*b<rcond:code>_reversed" 3634 [(set (pc) 3635 (if_then_else (rcond (cc0) 3636 (const_int 0)) 3637 (pc) 3638 (label_ref (match_operand 0 "" ""))))] 3639 "" 3640{ 3641 return 3642 (cc_prev_status.flags & CC_NO_OVERFLOW) 3643 ? "b<roCC> %l0%#" : "b<rCC> %l0%#"; 3644} 3645 [(set_attr "slottable" "has_slot")]) 3646 3647;; Set on condition: sCC. 3648 3649(define_expand "cstoredi4" 3650 [(set (cc0) (compare 3651 (match_operand:DI 2 "nonimmediate_operand") 3652 (match_operand:DI 3 "general_operand"))) 3653 (set (match_operand:SI 0 "register_operand") 3654 (match_operator:SI 1 "ordered_comparison_operator" 3655 [(cc0) (const_int 0)]))] 3656 "" 3657{ 3658 if (TARGET_V32 && !REG_P (operands[2])) 3659 operands[2] = force_reg (DImode, operands[2]); 3660 if (TARGET_V32 && MEM_P (operands[3])) 3661 operands[3] = force_reg (DImode, operands[3]); 3662}) 3663 3664(define_expand "cstore<mode>4" 3665 [(set (cc0) (compare 3666 (match_operand:BWD 2 "nonimmediate_operand") 3667 (match_operand:BWD 3 "general_operand"))) 3668 (set (match_operand:SI 0 "register_operand") 3669 (match_operator:SI 1 "ordered_comparison_operator" 3670 [(cc0) (const_int 0)]))] 3671 "" 3672 "") 3673 3674;; Like bCC, we have to check the overflow bit for 3675;; signed conditions. 3676 3677(define_insn "s<ncond:code>" 3678 [(set (match_operand:SI 0 "register_operand" "=r") 3679 (ncond:SI (cc0) (const_int 0)))] 3680 "" 3681 "s<CC> %0" 3682 [(set_attr "slottable" "yes") 3683 (set_attr "cc" "none")]) 3684 3685(define_insn "s<rcond:code>" 3686 [(set (match_operand:SI 0 "register_operand" "=r") 3687 (rcond:SI (cc0) (const_int 0)))] 3688 "" 3689{ 3690 return 3691 (cc_prev_status.flags & CC_NO_OVERFLOW) 3692 ? "s<oCC> %0" : "s<CC> %0"; 3693} 3694 [(set_attr "slottable" "yes") 3695 (set_attr "cc" "none")]) 3696 3697(define_insn "s<ocond:code>" 3698 [(set (match_operand:SI 0 "register_operand" "=r") 3699 (ocond:SI (cc0) (const_int 0)))] 3700 "" 3701{ 3702 return 3703 (cc_prev_status.flags & CC_NO_OVERFLOW) 3704 ? 0 : "s<CC> %0"; 3705} 3706 [(set_attr "slottable" "yes") 3707 (set_attr "cc" "none")]) 3708 3709;; Call insns. 3710 3711;; We need to make these patterns "expand", since the real operand is 3712;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]), 3713;; and cannot be checked if it were a "normal" pattern. 3714;; Note that "call" and "call_value" are *always* called with a 3715;; mem-operand for operand 0 and 1 respective. What happens for combined 3716;; instructions is a different issue. 3717 3718(define_expand "call" 3719 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "") 3720 (match_operand 1 "general_operand" "")) 3721 (clobber (reg:SI CRIS_SRP_REGNUM))])] 3722 "" 3723{ 3724 gcc_assert (MEM_P (operands[0])); 3725 if (flag_pic) 3726 cris_expand_pic_call_address (&operands[0], &operands[1]); 3727 else 3728 operands[1] = const0_rtx; 3729}) 3730 3731;; Accept operands for operand 0 in order of preference. 3732 3733(define_insn "*expanded_call_non_v32" 3734 [(call (mem:QI (match_operand:SI 0 "general_operand" "r,Q>,g")) 3735 (match_operand:SI 1 "cris_call_type_marker" "rM,rM,rM")) 3736 (clobber (reg:SI CRIS_SRP_REGNUM))] 3737 "!TARGET_V32" 3738 "jsr %0") 3739 3740(define_insn "*expanded_call_v32" 3741 [(call 3742 (mem:QI 3743 (match_operand:SI 0 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i")) 3744 (match_operand:SI 1 "cris_call_type_marker" "rM,rM,rM,rM")) 3745 (clobber (reg:SI CRIS_SRP_REGNUM))] 3746 "TARGET_V32" 3747 "@ 3748 jsr %0%# 3749 jsr %0%# 3750 bsr %0%# 3751 bsr %0%#" 3752 [(set_attr "slottable" "has_call_slot")]) 3753 3754;; Parallel when calculating and reusing address of indirect pointer 3755;; with simple offset. (Makes most sense with PIC.) It looks a bit 3756;; wrong not to have the clobber last, but that's the way combine 3757;; generates it (except it doesn't look into the *inner* mem, so this 3758;; just matches a peephole2). FIXME: investigate that. 3759(define_insn "*expanded_call_side" 3760 [(call (mem:QI 3761 (mem:SI 3762 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r, r,r") 3763 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn")))) 3764 (match_operand:SI 2 "cris_call_type_marker" "rM,rM,rM")) 3765 (clobber (reg:SI CRIS_SRP_REGNUM)) 3766 (set (match_operand:SI 3 "register_operand" "=*0,r,r") 3767 (plus:SI (match_dup 0) 3768 (match_dup 1)))] 3769 ;; Disabled until after reload until we can avoid an output reload for 3770 ;; operand 3 (being forbidden for call insns). 3771 "reload_completed && !TARGET_AVOID_GOTPLT && !TARGET_V32" 3772 "jsr [%3=%0%S1]") 3773 3774(define_expand "call_value" 3775 [(parallel [(set (match_operand 0 "" "") 3776 (call (match_operand:QI 1 "cris_mem_call_operand" "") 3777 (match_operand 2 "" ""))) 3778 (clobber (reg:SI CRIS_SRP_REGNUM))])] 3779 "" 3780{ 3781 gcc_assert (MEM_P (operands[1])); 3782 if (flag_pic) 3783 cris_expand_pic_call_address (&operands[1], &operands[2]); 3784 else 3785 operands[2] = const0_rtx; 3786}) 3787 3788;; The validity other than "general" of 3789;; operand 0 will be checked elsewhere. Accept operands for operand 1 in 3790;; order of preference (Q includes r, but r is shorter, faster). 3791;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather 3792;; than requiring getting rPIC + sym:PLT into a register. 3793 3794(define_insn "*expanded_call_value_non_v32" 3795 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g") 3796 (call (mem:QI (match_operand:SI 1 "general_operand" "r,Q>,g")) 3797 (match_operand:SI 2 "cris_call_type_marker" "rM,rM,rM"))) 3798 (clobber (reg:SI CRIS_SRP_REGNUM))] 3799 "!TARGET_V32" 3800 "Jsr %1" 3801 [(set_attr "cc" "clobber")]) 3802 3803;; See similar call special-case. 3804(define_insn "*expanded_call_value_side" 3805 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g") 3806 (call 3807 (mem:QI 3808 (mem:SI 3809 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r, r,r") 3810 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))) 3811 (match_operand:SI 3 "cris_call_type_marker" "rM,rM,rM"))) 3812 (clobber (reg:SI CRIS_SRP_REGNUM)) 3813 (set (match_operand:SI 4 "register_operand" "=*1,r,r") 3814 (plus:SI (match_dup 1) 3815 (match_dup 2)))] 3816 ;; Disabled until after reload until we can avoid an output reload for 3817 ;; operand 4 (being forbidden for call insns). 3818 "reload_completed && !TARGET_AVOID_GOTPLT && !TARGET_V32" 3819 "Jsr [%4=%1%S2]" 3820 [(set_attr "cc" "clobber")]) 3821 3822(define_insn "*expanded_call_value_v32" 3823 [(set 3824 (match_operand 0 "nonimmediate_operand" "=g,g,g,g") 3825 (call 3826 (mem:QI 3827 (match_operand:SI 1 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i")) 3828 (match_operand:SI 2 "cris_call_type_marker" "rM,rM,rM,rM"))) 3829 (clobber (reg:SI 16))] 3830 "TARGET_V32" 3831 "@ 3832 Jsr %1%# 3833 Jsr %1%# 3834 Bsr %1%# 3835 Bsr %1%#" 3836 [(set_attr "cc" "clobber") 3837 (set_attr "slottable" "has_call_slot")]) 3838 3839;; Used in debugging. No use for the direct pattern; unfilled 3840;; delayed-branches are taken care of by other means. 3841 3842(define_insn "nop" 3843 [(const_int 0)] 3844 "" 3845 "nop" 3846 [(set_attr "cc" "none")]) 3847 3848;; Same as the gdb trap breakpoint, will cause a SIGTRAP for 3849;; cris-linux* and crisv32-linux*, as intended. Will work in 3850;; freestanding environments with sufficient framework. 3851(define_insn "trap" 3852 [(trap_if (const_int 1) (const_int 8))] 3853 "TARGET_TRAP_USING_BREAK8" 3854 "break 8") 3855 3856;; We need to stop accesses to the stack after the memory is 3857;; deallocated. Unfortunately, reorg doesn't look at naked clobbers, 3858;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't 3859;; want to use a naked (unspec_volatile) as that would stop any 3860;; scheduling in the epilogue. Hence we model it as a "real" insn that 3861;; sets the memory in an unspecified manner. FIXME: Unfortunately it 3862;; still has the effect of an unspec_volatile. 3863(define_insn "cris_frame_deallocated_barrier" 3864 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM)) 3865 (unspec:BLK [(const_int 0)] CRIS_UNSPEC_FRAME_DEALLOC))] 3866 "" 3867 "" 3868 [(set_attr "length" "0")]) 3869 3870;; We expand on casesi so we can use "bound" and "add offset fetched from 3871;; a table to pc" (adds.w [pc+%0.w],pc). 3872 3873;; Note: if you change the "parallel" (or add anything after it) in 3874;; this expansion, you must change the macro ASM_OUTPUT_CASE_END 3875;; accordingly, to add the default case at the end of the jump-table. 3876 3877(define_expand "cris_casesi_non_v32" 3878 [(set (match_dup 5) (match_operand:SI 0 "general_operand" "")) 3879 (set (match_dup 6) 3880 (minus:SI (match_dup 5) 3881 (match_operand:SI 1 "const_int_operand" "n"))) 3882 (set (match_dup 7) 3883 (umin:SI (match_dup 6) 3884 (match_operand:SI 2 "const_int_operand" "n"))) 3885 (parallel 3886 [(set (pc) 3887 (if_then_else 3888 (ltu (match_dup 7) (match_dup 2)) 3889 (plus:SI (sign_extend:SI 3890 (mem:HI 3891 (plus:SI (mult:SI (match_dup 7) (const_int 2)) 3892 (pc)))) 3893 (pc)) 3894 (label_ref (match_operand 4 "" "")))) 3895 (use (label_ref (match_operand 3 "" "")))])] 3896 "" 3897{ 3898 operands[2] = plus_constant (SImode, operands[2], 1); 3899 operands[5] = gen_reg_rtx (SImode); 3900 operands[6] = gen_reg_rtx (SImode); 3901 operands[7] = gen_reg_rtx (SImode); 3902}) 3903 3904;; FIXME: Check effect of not JUMP_TABLES_IN_TEXT_SECTION. 3905(define_expand "cris_casesi_v32" 3906 [(set (match_dup 5) (match_operand:SI 0 "general_operand")) 3907 (set (match_dup 6) 3908 (minus:SI (match_dup 5) 3909 (match_operand:SI 1 "const_int_operand"))) 3910 (set (match_dup 7) 3911 (umin:SI (match_dup 6) 3912 (match_operand:SI 2 "const_int_operand"))) 3913 (set (match_dup 8) (match_dup 11)) 3914 (set (match_dup 9) 3915 (plus:SI (mult:SI (match_dup 7) (const_int 2)) 3916 (match_dup 8))) 3917 (set (match_dup 10) 3918 (plus:SI (sign_extend:SI (mem:HI (match_dup 9))) 3919 (match_dup 9))) 3920 (parallel 3921 [(set (pc) 3922 (if_then_else 3923 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI) (match_dup 2)) 3924 (match_dup 10) 3925 (label_ref (match_operand 4 "" "")))) 3926 (use (label_ref (match_dup 3)))])] 3927 "TARGET_V32" 3928{ 3929 int i; 3930 rtx xlabel = gen_rtx_LABEL_REF (VOIDmode, operands[3]); 3931 for (i = 5; i <= 10; i++) 3932 operands[i] = gen_reg_rtx (SImode); 3933 operands[2] = plus_constant (SImode, operands[2], 1); 3934 3935 /* Don't forget to decorate labels too, for PIC. */ 3936 operands[11] = flag_pic 3937 ? gen_rtx_CONST (Pmode, 3938 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xlabel), 3939 CRIS_UNSPEC_PCREL)) 3940 : xlabel; 3941}) 3942 3943(define_expand "casesi" 3944 [(match_operand:SI 0 "general_operand") 3945 (match_operand:SI 1 "const_int_operand") 3946 (match_operand:SI 2 "const_int_operand") 3947 (match_operand 3 "" "") 3948 (match_operand 4 "" "")] 3949 "" 3950{ 3951 if (TARGET_V32) 3952 emit_insn (gen_cris_casesi_v32 (operands[0], operands[1], operands[2], 3953 operands[3], operands[4])); 3954 else 3955 emit_insn (gen_cris_casesi_non_v32 (operands[0], operands[1], operands[2], 3956 operands[3], operands[4])); 3957 DONE; 3958}) 3959 3960;; Split-patterns. Some of them have modes unspecified. This 3961;; should always be ok; if for no other reason sparc.md has it as 3962;; well. 3963;; 3964;; When register_operand is specified for an operand, we can get a 3965;; subreg as well (Axis-990331), so don't just assume that REG_P is true 3966;; for a register_operand and that REGNO can be used as is. It is best to 3967;; guard with REG_P, unless it is worth it to adjust for the subreg case. 3968 3969;; op [rx + 0],ry,rz 3970;; The index to rx is optimized into zero, and gone. 3971 3972;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended, 3973;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx]. 3974;; Split this into: 3975;; move ry,rz 3976;; op [rx],rz 3977;; Lose if rz=ry or rx=rz. 3978;; Call this op-extend-split. 3979;; Do not match for V32; the addo and addi shouldn't be split 3980;; up. 3981 3982(define_split 3983 [(set (match_operand 0 "cris_nonsp_register_operand" "") 3984 (match_operator 3985 4 "cris_operand_extend_operator" 3986 [(match_operand 1 "register_operand" "") 3987 (match_operator 3988 3 "cris_extend_operator" 3989 [(match_operand 2 "memory_operand" "")])]))] 3990 "!TARGET_V32 3991 && REG_P (operands[0]) 3992 && REG_P (operands[1]) 3993 && REGNO (operands[1]) != REGNO (operands[0]) 3994 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 3995 && REG_P (XEXP (operands[2], 0)) 3996 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" 3997 [(set (match_dup 0) 3998 (match_dup 1)) 3999 (set (match_dup 0) 4000 (match_op_dup 4001 4 [(match_dup 0) 4002 (match_op_dup 3 [(match_dup 2)])]))] 4003 "") 4004 4005;; As op-extend-split, but recognize and split op [rz],ry,rz into 4006;; ext [rz],rz 4007;; op ry,rz 4008;; Do this for plus or bound only, being commutative operations, since we 4009;; have swapped the operands. 4010;; Call this op-extend-split-rx=rz 4011 4012(define_split 4013 [(set (match_operand 0 "cris_nonsp_register_operand" "") 4014 (match_operator 4015 4 "cris_plus_or_bound_operator" 4016 [(match_operand 1 "register_operand" "") 4017 (match_operator 4018 3 "cris_extend_operator" 4019 [(match_operand 2 "memory_operand" "")])]))] 4020 "!TARGET_V32 4021 && REG_P (operands[0]) 4022 && REG_P (operands[1]) 4023 && REGNO (operands[1]) != REGNO (operands[0]) 4024 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 4025 && REG_P (XEXP (operands[2], 0)) 4026 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" 4027 [(set (match_dup 0) 4028 (match_op_dup 3 [(match_dup 2)])) 4029 (set (match_dup 0) 4030 (match_op_dup 4031 4 [(match_dup 0) 4032 (match_dup 1)]))] 4033 "") 4034 4035;; As the op-extend-split, but swapped operands, and only for 4036;; plus or bound, being the commutative extend-operators. FIXME: Why is 4037;; this needed? Is it? 4038;; Call this op-extend-split-swapped 4039 4040(define_split 4041 [(set (match_operand 0 "cris_nonsp_register_operand" "") 4042 (match_operator 4043 4 "cris_plus_or_bound_operator" 4044 [(match_operator 4045 3 "cris_extend_operator" 4046 [(match_operand 2 "memory_operand" "")]) 4047 (match_operand 1 "register_operand" "")]))] 4048 "!TARGET_V32 4049 && REG_P (operands[0]) 4050 && REG_P (operands[1]) 4051 && REGNO (operands[1]) != REGNO (operands[0]) 4052 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 4053 && REG_P (XEXP (operands[2], 0)) 4054 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" 4055 [(set (match_dup 0) 4056 (match_dup 1)) 4057 (set (match_dup 0) 4058 (match_op_dup 4059 4 [(match_dup 0) 4060 (match_op_dup 3 [(match_dup 2)])]))] 4061 "") 4062 4063;; As op-extend-split-rx=rz, but swapped operands, only for plus or 4064;; bound. Call this op-extend-split-swapped-rx=rz. 4065 4066(define_split 4067 [(set (match_operand 0 "cris_nonsp_register_operand" "") 4068 (match_operator 4069 4 "cris_plus_or_bound_operator" 4070 [(match_operator 4071 3 "cris_extend_operator" 4072 [(match_operand 2 "memory_operand" "")]) 4073 (match_operand 1 "register_operand" "")]))] 4074 "!TARGET_V32 4075 && REG_P (operands[0]) 4076 && REG_P (operands[1]) 4077 && REGNO (operands[1]) != REGNO (operands[0]) 4078 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 4079 && REG_P (XEXP (operands[2], 0)) 4080 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" 4081 [(set (match_dup 0) 4082 (match_op_dup 3 [(match_dup 2)])) 4083 (set (match_dup 0) 4084 (match_op_dup 4085 4 [(match_dup 0) 4086 (match_dup 1)]))] 4087 "") 4088 4089;; As op-extend-split, but the mem operand is not extended. 4090;; 4091;; op [rx],ry,rz changed into 4092;; move ry,rz 4093;; op [rx],rz 4094;; lose if ry=rz or rx=rz 4095;; Call this op-extend. 4096 4097(define_split 4098 [(set (match_operand 0 "cris_nonsp_register_operand" "") 4099 (match_operator 4100 3 "cris_orthogonal_operator" 4101 [(match_operand 1 "register_operand" "") 4102 (match_operand 2 "memory_operand" "")]))] 4103 "!TARGET_V32 4104 && REG_P (operands[0]) 4105 && REG_P (operands[1]) 4106 && REGNO (operands[1]) != REGNO (operands[0]) 4107 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 4108 && REG_P (XEXP (operands[2], 0)) 4109 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" 4110 [(set (match_dup 0) 4111 (match_dup 1)) 4112 (set (match_dup 0) 4113 (match_op_dup 4114 3 [(match_dup 0) 4115 (match_dup 2)]))] 4116 "") 4117 4118;; As op-extend-split-rx=rz, non-extended. 4119;; Call this op-split-rx=rz 4120 4121(define_split 4122 [(set (match_operand 0 "cris_nonsp_register_operand" "") 4123 (match_operator 4124 3 "cris_commutative_orth_op" 4125 [(match_operand 2 "memory_operand" "") 4126 (match_operand 1 "register_operand" "")]))] 4127 "!TARGET_V32 4128 && REG_P (operands[0]) 4129 && REG_P (operands[1]) 4130 && REGNO (operands[1]) != REGNO (operands[0]) 4131 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 4132 && REG_P (XEXP (operands[2], 0)) 4133 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" 4134 [(set (match_dup 0) 4135 (match_dup 1)) 4136 (set (match_dup 0) 4137 (match_op_dup 4138 3 [(match_dup 0) 4139 (match_dup 2)]))] 4140 "") 4141 4142;; As op-extend-split-swapped, nonextended. 4143;; Call this op-split-swapped. 4144 4145(define_split 4146 [(set (match_operand 0 "cris_nonsp_register_operand" "") 4147 (match_operator 4148 3 "cris_commutative_orth_op" 4149 [(match_operand 1 "register_operand" "") 4150 (match_operand 2 "memory_operand" "")]))] 4151 "!TARGET_V32 4152 && REG_P (operands[0]) && REG_P (operands[1]) 4153 && REGNO (operands[1]) != REGNO (operands[0]) 4154 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 4155 && REG_P (XEXP (operands[2], 0)) 4156 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" 4157 [(set (match_dup 0) 4158 (match_dup 2)) 4159 (set (match_dup 0) 4160 (match_op_dup 4161 3 [(match_dup 0) 4162 (match_dup 1)]))] 4163 "") 4164 4165;; As op-extend-split-swapped-rx=rz, non-extended. 4166;; Call this op-split-swapped-rx=rz. 4167 4168(define_split 4169 [(set (match_operand 0 "cris_nonsp_register_operand" "") 4170 (match_operator 4171 3 "cris_orthogonal_operator" 4172 [(match_operand 2 "memory_operand" "") 4173 (match_operand 1 "register_operand" "")]))] 4174 "!TARGET_V32 4175 && REG_P (operands[0]) && REG_P (operands[1]) 4176 && REGNO (operands[1]) != REGNO (operands[0]) 4177 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 4178 && REG_P (XEXP (operands[2], 0)) 4179 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" 4180 [(set (match_dup 0) 4181 (match_dup 2)) 4182 (set (match_dup 0) 4183 (match_op_dup 4184 3 [(match_dup 0) 4185 (match_dup 1)]))] 4186 "") 4187 4188(include "sync.md") 4189 4190;; Splits for all cases in side-effect insns where (possibly after reload 4191;; and register allocation) rx and ry in [rx=ry+i] are equal. 4192 4193;; move.S1 [rx=rx+rz.S2],ry 4194 4195(define_split 4196 [(parallel 4197 [(set (match_operand 0 "register_operand" "") 4198 (match_operator 4199 6 "cris_mem_op" 4200 [(plus:SI 4201 (mult:SI (match_operand:SI 1 "register_operand" "") 4202 (match_operand:SI 2 "const_int_operand" "")) 4203 (match_operand:SI 3 "register_operand" ""))])) 4204 (set (match_operand:SI 4 "register_operand" "") 4205 (plus:SI (mult:SI (match_dup 1) 4206 (match_dup 2)) 4207 (match_dup 3)))])] 4208 "REG_P (operands[3]) && REG_P (operands[4]) 4209 && REGNO (operands[3]) == REGNO (operands[4])" 4210 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) 4211 (match_dup 3))) 4212 (set (match_dup 0) (match_dup 5))] 4213 "operands[5] = replace_equiv_address (operands[6], operands[3]);") 4214 4215;; move.S1 [rx=rx+i],ry 4216 4217(define_split 4218 [(parallel 4219 [(set (match_operand 0 "register_operand" "") 4220 (match_operator 4221 5 "cris_mem_op" 4222 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "") 4223 (match_operand:SI 2 "cris_bdap_operand" ""))])) 4224 (set (match_operand:SI 3 "register_operand" "") 4225 (plus:SI (match_dup 1) 4226 (match_dup 2)))])] 4227 "(rtx_equal_p (operands[3], operands[1]) 4228 || rtx_equal_p (operands[3], operands[2]))" 4229 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2))) 4230 (set (match_dup 0) (match_dup 4))] 4231{ 4232 operands[4] = replace_equiv_address (operands[5], operands[3]); 4233 cris_order_for_addsi3 (operands, 1); 4234}) 4235 4236;; move.S1 ry,[rx=rx+rz.S2] 4237 4238(define_split 4239 [(parallel 4240 [(set (match_operator 4241 6 "cris_mem_op" 4242 [(plus:SI 4243 (mult:SI (match_operand:SI 0 "register_operand" "") 4244 (match_operand:SI 1 "const_int_operand" "")) 4245 (match_operand:SI 2 "register_operand" ""))]) 4246 (match_operand 3 "register_operand" "")) 4247 (set (match_operand:SI 4 "register_operand" "") 4248 (plus:SI (mult:SI (match_dup 0) 4249 (match_dup 1)) 4250 (match_dup 2)))])] 4251 "REG_P (operands[2]) && REG_P (operands[4]) 4252 && REGNO (operands[4]) == REGNO (operands[2])" 4253 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) 4254 (match_dup 2))) 4255 (set (match_dup 5) (match_dup 3))] 4256 "operands[5] = replace_equiv_address (operands[6], operands[4]);") 4257 4258;; move.S1 ry,[rx=rx+i] 4259 4260(define_split 4261 [(parallel 4262 [(set (match_operator 4263 6 "cris_mem_op" 4264 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "") 4265 (match_operand:SI 1 "cris_bdap_operand" ""))]) 4266 (match_operand 2 "register_operand" "")) 4267 (set (match_operand:SI 3 "register_operand" "") 4268 (plus:SI (match_dup 0) 4269 (match_dup 1)))])] 4270 "(rtx_equal_p (operands[3], operands[0]) 4271 || rtx_equal_p (operands[3], operands[1]))" 4272 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1))) 4273 (set (match_dup 5) (match_dup 2))] 4274{ 4275 operands[5] = replace_equiv_address (operands[6], operands[3]); 4276 cris_order_for_addsi3 (operands, 0); 4277}) 4278 4279;; clear.[bwd] [rx=rx+rz.S2] 4280 4281(define_split 4282 [(parallel 4283 [(set (mem:BWD (plus:SI 4284 (mult:SI (match_operand:SI 0 "register_operand" "") 4285 (match_operand:SI 1 "const_int_operand" "")) 4286 (match_operand:SI 2 "register_operand" ""))) 4287 (const_int 0)) 4288 (set (match_operand:SI 3 "register_operand" "") 4289 (plus:SI (mult:SI (match_dup 0) 4290 (match_dup 1)) 4291 (match_dup 2)))])] 4292 "REG_P (operands[2]) && REG_P (operands[3]) 4293 && REGNO (operands[3]) == REGNO (operands[2])" 4294 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) 4295 (match_dup 2))) 4296 (set (mem:BWD (match_dup 3)) (const_int 0))] 4297 "") 4298 4299;; clear.[bwd] [rx=rx+i] 4300 4301(define_split 4302 [(parallel 4303 [(set (mem:BWD 4304 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "") 4305 (match_operand:SI 1 "cris_bdap_operand" ""))) 4306 (const_int 0)) 4307 (set (match_operand:SI 2 "register_operand" "") 4308 (plus:SI (match_dup 0) 4309 (match_dup 1)))])] 4310 "(rtx_equal_p (operands[0], operands[2]) 4311 || rtx_equal_p (operands[2], operands[1]))" 4312 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1))) 4313 (set (mem:BWD (match_dup 2)) (const_int 0))] 4314 "cris_order_for_addsi3 (operands, 0);") 4315 4316;; mov(s|u).S1 [rx=rx+rz.S2],ry 4317 4318(define_split 4319 [(parallel 4320 [(set (match_operand 0 "register_operand" "") 4321 (match_operator 4322 5 "cris_extend_operator" 4323 [(mem (plus:SI 4324 (mult:SI (match_operand:SI 1 "register_operand" "") 4325 (match_operand:SI 2 "const_int_operand" "")) 4326 (match_operand:SI 3 "register_operand" "")))])) 4327 (set (match_operand:SI 4 "register_operand" "") 4328 (plus:SI (mult:SI (match_dup 1) 4329 (match_dup 2)) 4330 (match_dup 3)))])] 4331 "REG_P (operands[3]) 4332 && REG_P (operands[4]) 4333 && REGNO (operands[3]) == REGNO (operands[4])" 4334 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) 4335 (match_dup 3))) 4336 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))] 4337 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);") 4338 4339;; mov(s|u).S1 [rx=rx+i],ry 4340 4341(define_split 4342 [(parallel 4343 [(set (match_operand 0 "register_operand" "") 4344 (match_operator 4345 4 "cris_extend_operator" 4346 [(mem (plus:SI 4347 (match_operand:SI 1 "cris_bdap_operand" "") 4348 (match_operand:SI 2 "cris_bdap_operand" "")))])) 4349 (set (match_operand:SI 3 "register_operand" "") 4350 (plus:SI (match_dup 1) 4351 (match_dup 2)))])] 4352 "(rtx_equal_p (operands[1], operands[3]) 4353 || rtx_equal_p (operands[2], operands[3]))" 4354 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2))) 4355 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))] 4356{ 4357 operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]); 4358 cris_order_for_addsi3 (operands, 1); 4359}) 4360 4361;; op.S1 [rx=rx+i],ry 4362 4363(define_split 4364 [(parallel 4365 [(set (match_operand 0 "register_operand" "") 4366 (match_operator 4367 5 "cris_orthogonal_operator" 4368 [(match_operand 1 "register_operand" "") 4369 (mem (plus:SI 4370 (match_operand:SI 2 "cris_bdap_operand" "") 4371 (match_operand:SI 3 "cris_bdap_operand" "")))])) 4372 (set (match_operand:SI 4 "register_operand" "") 4373 (plus:SI (match_dup 2) 4374 (match_dup 3)))])] 4375 "(rtx_equal_p (operands[4], operands[2]) 4376 || rtx_equal_p (operands[4], operands[3]))" 4377 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) 4378 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))] 4379{ 4380 operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]); 4381 cris_order_for_addsi3 (operands, 2); 4382}) 4383 4384;; op.S1 [rx=rx+rz.S2],ry 4385 4386(define_split 4387 [(parallel 4388 [(set (match_operand 0 "register_operand" "") 4389 (match_operator 4390 6 "cris_orthogonal_operator" 4391 [(match_operand 1 "register_operand" "") 4392 (mem (plus:SI 4393 (mult:SI (match_operand:SI 2 "register_operand" "") 4394 (match_operand:SI 3 "const_int_operand" "")) 4395 (match_operand:SI 4 "register_operand" "")))])) 4396 (set (match_operand:SI 5 "register_operand" "") 4397 (plus:SI (mult:SI (match_dup 2) 4398 (match_dup 3)) 4399 (match_dup 4)))])] 4400 "REG_P (operands[4]) 4401 && REG_P (operands[5]) 4402 && REGNO (operands[5]) == REGNO (operands[4])" 4403 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) 4404 (match_dup 4))) 4405 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))] 4406 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);") 4407 4408;; op.S1 [rx=rx+rz.S2],ry (swapped) 4409 4410(define_split 4411 [(parallel 4412 [(set (match_operand 0 "register_operand" "") 4413 (match_operator 4414 6 "cris_commutative_orth_op" 4415 [(mem (plus:SI 4416 (mult:SI (match_operand:SI 2 "register_operand" "") 4417 (match_operand:SI 3 "const_int_operand" "")) 4418 (match_operand:SI 4 "register_operand" ""))) 4419 (match_operand 1 "register_operand" "")])) 4420 (set (match_operand:SI 5 "register_operand" "") 4421 (plus:SI (mult:SI (match_dup 2) 4422 (match_dup 3)) 4423 (match_dup 4)))])] 4424 "REG_P (operands[4]) 4425 && REG_P (operands[5]) 4426 && REGNO (operands[5]) == REGNO (operands[4])" 4427 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) 4428 (match_dup 4))) 4429 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))] 4430 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);") 4431 4432;; op.S1 [rx=rx+i],ry (swapped) 4433 4434(define_split 4435 [(parallel 4436 [(set (match_operand 0 "register_operand" "") 4437 (match_operator 4438 5 "cris_commutative_orth_op" 4439 [(mem 4440 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "") 4441 (match_operand:SI 3 "cris_bdap_operand" ""))) 4442 (match_operand 1 "register_operand" "")])) 4443 (set (match_operand:SI 4 "register_operand" "") 4444 (plus:SI (match_dup 2) 4445 (match_dup 3)))])] 4446 "(rtx_equal_p (operands[4], operands[2]) 4447 || rtx_equal_p (operands[4], operands[3]))" 4448 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) 4449 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))] 4450{ 4451 operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]); 4452 cris_order_for_addsi3 (operands, 2); 4453}) 4454 4455;; op(s|u).S1 [rx=rx+rz.S2],ry 4456 4457(define_split 4458 [(parallel 4459 [(set (match_operand 0 "register_operand" "") 4460 (match_operator 4461 6 "cris_operand_extend_operator" 4462 [(match_operand 1 "register_operand" "") 4463 (match_operator 4464 7 "cris_extend_operator" 4465 [(mem (plus:SI 4466 (mult:SI (match_operand:SI 2 "register_operand" "") 4467 (match_operand:SI 3 "const_int_operand" "")) 4468 (match_operand:SI 4 "register_operand" "")))])])) 4469 (set (match_operand:SI 5 "register_operand" "") 4470 (plus:SI (mult:SI (match_dup 2) 4471 (match_dup 3)) 4472 (match_dup 4)))])] 4473 "REG_P (operands[4]) 4474 && REG_P (operands[5]) 4475 && REGNO (operands[5]) == REGNO (operands[4])" 4476 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) 4477 (match_dup 4))) 4478 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))] 4479 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]), 4480 replace_equiv_address (XEXP (operands[7], 0), 4481 operands[5]));") 4482 4483;; op(s|u).S1 [rx=rx+i],ry 4484 4485(define_split 4486 [(parallel 4487 [(set (match_operand 0 "register_operand" "") 4488 (match_operator 4489 5 "cris_operand_extend_operator" 4490 [(match_operand 1 "register_operand" "") 4491 (match_operator 4492 6 "cris_extend_operator" 4493 [(mem 4494 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "") 4495 (match_operand:SI 3 "cris_bdap_operand" "") 4496 ))])])) 4497 (set (match_operand:SI 4 "register_operand" "") 4498 (plus:SI (match_dup 2) 4499 (match_dup 3)))])] 4500 "(rtx_equal_p (operands[4], operands[2]) 4501 || rtx_equal_p (operands[4], operands[3]))" 4502 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) 4503 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))] 4504{ 4505 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]), 4506 replace_equiv_address (XEXP (operands[6], 0), 4507 operands[4])); 4508 cris_order_for_addsi3 (operands, 2); 4509}) 4510 4511;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound) 4512 4513(define_split 4514 [(parallel 4515 [(set (match_operand 0 "register_operand" "") 4516 (match_operator 4517 7 "cris_plus_or_bound_operator" 4518 [(match_operator 4519 6 "cris_extend_operator" 4520 [(mem (plus:SI 4521 (mult:SI (match_operand:SI 2 "register_operand" "") 4522 (match_operand:SI 3 "const_int_operand" "")) 4523 (match_operand:SI 4 "register_operand" "")))]) 4524 (match_operand 1 "register_operand" "")])) 4525 (set (match_operand:SI 5 "register_operand" "") 4526 (plus:SI (mult:SI (match_dup 2) 4527 (match_dup 3)) 4528 (match_dup 4)))])] 4529 "REG_P (operands[4]) && REG_P (operands[5]) 4530 && REGNO (operands[5]) == REGNO (operands[4])" 4531 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) 4532 (match_dup 4))) 4533 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))] 4534 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]), 4535 replace_equiv_address (XEXP (operands[6], 0), 4536 operands[5]));") 4537 4538;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound) 4539 4540(define_split 4541 [(parallel 4542 [(set (match_operand 0 "register_operand" "") 4543 (match_operator 4544 6 "cris_plus_or_bound_operator" 4545 [(match_operator 4546 5 "cris_extend_operator" 4547 [(mem (plus:SI 4548 (match_operand:SI 2 "cris_bdap_operand" "") 4549 (match_operand:SI 3 "cris_bdap_operand" "")))]) 4550 (match_operand 1 "register_operand" "")])) 4551 (set (match_operand:SI 4 "register_operand" "") 4552 (plus:SI (match_dup 2) 4553 (match_dup 3)))])] 4554 "(rtx_equal_p (operands[4], operands[2]) 4555 || rtx_equal_p (operands[4], operands[3]))" 4556 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) 4557 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))] 4558{ 4559 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]), 4560 replace_equiv_address (XEXP (operands[5], 0), 4561 operands[4])); 4562 cris_order_for_addsi3 (operands, 2); 4563}) 4564 4565;; Splits for addressing prefixes that have no side-effects, so we can 4566;; fill a delay slot. Never split if we lose something, though. 4567 4568;; If we have a 4569;; move [indirect_ref],rx 4570;; where indirect ref = {const, [r+], [r]}, it costs as much as 4571;; move indirect_ref,rx 4572;; move [rx],rx 4573;; Take care not to allow indirect_ref = register. 4574 4575;; We're not allowed to generate copies of registers with different mode 4576;; until after reload; copying pseudos upsets reload. CVS as of 4577;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in 4578;; cselib_invalidate_regno. Also, don't do this for the stack-pointer, 4579;; as we don't want it set temporarily to an invalid value. 4580 4581(define_split ; indir_to_reg_split 4582 [(set (match_operand 0 "cris_nonsp_register_operand" "") 4583 (match_operand 1 "indirect_operand" ""))] 4584 "reload_completed 4585 && REG_P (operands[0]) 4586 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 4587 && (MEM_P (XEXP (operands[1], 0)) || CONSTANT_P (XEXP (operands[1], 0))) 4588 && REGNO (operands[0]) < CRIS_LAST_GENERAL_REGISTER" 4589 [(set (match_dup 2) (match_dup 4)) 4590 (set (match_dup 0) (match_dup 3))] 4591 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0])); 4592 operands[3] = replace_equiv_address (operands[1], operands[2]); 4593 operands[4] = XEXP (operands[1], 0);") 4594 4595;; As the above, but MOVS and MOVU. 4596 4597(define_split 4598 [(set (match_operand 0 "cris_nonsp_register_operand" "") 4599 (match_operator 4600 4 "cris_extend_operator" 4601 [(match_operand 1 "indirect_operand" "")]))] 4602 "reload_completed 4603 && REG_P (operands[0]) 4604 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD 4605 && (MEM_P (XEXP (operands[1], 0)) 4606 || CONSTANT_P (XEXP (operands[1], 0)))" 4607 [(set (match_dup 2) (match_dup 5)) 4608 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))] 4609 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0])); 4610 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]); 4611 operands[5] = XEXP (operands[1], 0);") 4612 4613;; Various peephole optimizations. 4614;; 4615;; Watch out: when you exchange one set of instructions for another, the 4616;; condition codes setting must be the same, or you have to CC_INIT or 4617;; whatever is appropriate, in the pattern before you emit the 4618;; assembly text. This is best done here, not in cris_notice_update_cc, 4619;; to keep changes local to their cause. 4620;; 4621;; Do not add patterns that you do not know will be matched. 4622;; Please also add a self-contained testcase. 4623 4624;; We have trouble with and:s and shifts. Maybe something is broken in 4625;; gcc? Or it could just be that bit-field insn expansion is a bit 4626;; suboptimal when not having extzv insns. 4627;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c 4628 4629(define_peephole2 ; asrandb (peephole casesi+31) 4630 [(set (match_operand:SI 0 "register_operand" "") 4631 (ashiftrt:SI (match_dup 0) 4632 (match_operand:SI 1 "const_int_operand" ""))) 4633 (set (match_dup 0) 4634 (and:SI (match_dup 0) 4635 (match_operand 2 "const_int_operand" "")))] 4636 "INTVAL (operands[2]) > 31 4637 && INTVAL (operands[2]) < 255 4638 && INTVAL (operands[1]) > 23 4639 /* Check that the and-operation enables us to use logical-shift. */ 4640 && (INTVAL (operands[2]) 4641 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0" 4642 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) 4643 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))] 4644 ;; FIXME: CC0 is valid except for the M bit. 4645{ 4646 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0])); 4647 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode)); 4648}) 4649 4650(define_peephole2 ; asrandw (peephole casesi+32) 4651 [(set (match_operand:SI 0 "register_operand" "") 4652 (ashiftrt:SI (match_dup 0) 4653 (match_operand:SI 1 "const_int_operand" ""))) 4654 (set (match_dup 0) 4655 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))] 4656 "INTVAL (operands[2]) > 31 4657 && INTVAL (operands[2]) < 65535 4658 && INTVAL (operands[2]) != 255 4659 && INTVAL (operands[1]) > 15 4660 /* Check that the and-operation enables us to use logical-shift. */ 4661 && (INTVAL (operands[2]) 4662 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0" 4663 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) 4664 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))] 4665 ;; FIXME: CC0 is valid except for the M bit. 4666{ 4667 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 4668 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode)); 4669}) 4670 4671(define_peephole2 ; lsrandb (peephole casesi+33) 4672 [(set (match_operand:SI 0 "register_operand" "") 4673 (lshiftrt:SI (match_dup 0) 4674 (match_operand:SI 1 "const_int_operand" ""))) 4675 (set (match_dup 0) 4676 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))] 4677 "INTVAL (operands[2]) > 31 4678 && INTVAL (operands[2]) < 255 4679 && INTVAL (operands[1]) > 23" 4680 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) 4681 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))] 4682 ;; FIXME: CC0 is valid except for the M bit. 4683{ 4684 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0])); 4685 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode)); 4686}) 4687 4688(define_peephole2 ; lsrandw (peephole casesi+34) 4689 [(set (match_operand:SI 0 "register_operand" "") 4690 (lshiftrt:SI (match_dup 0) 4691 (match_operand:SI 1 "const_int_operand" ""))) 4692 (set (match_dup 0) 4693 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))] 4694 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535 4695 && INTVAL (operands[2]) != 255 4696 && INTVAL (operands[1]) > 15" 4697 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) 4698 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))] 4699 ;; FIXME: CC0 is valid except for the M bit. 4700{ 4701 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 4702 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode)); 4703}) 4704 4705 4706;; Change 4707;; add.d n,rx 4708;; move [rx],ry 4709;; into 4710;; move [rx=rx+n],ry 4711;; when -128 <= n <= 127. 4712;; This will reduce the size of the assembler code for n = [-128..127], 4713;; and speed up accordingly. Don't match if the previous insn is 4714;; (set rx rz) because that combination is matched by another peephole. 4715;; No stable test-case. 4716 4717(define_peephole2 ; moversideqi (peephole casesi+35) 4718 [(set (match_operand:SI 0 "register_operand" "") 4719 (plus:SI (match_operand:SI 1 "register_operand" "") 4720 (match_operand:SI 2 "const_int_operand" ""))) 4721 (set (match_operand 3 "register_operand" "") 4722 (match_operator 4 "cris_mem_op" [(match_dup 0)]))] 4723 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD 4724 && REGNO (operands[3]) != REGNO (operands[0]) 4725 && (cris_base_p (operands[1], true) || cris_base_p (operands[2], true)) 4726 && !satisfies_constraint_J (operands[2]) 4727 && !satisfies_constraint_N (operands[2]) 4728 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128) 4729 && TARGET_SIDE_EFFECT_PREFIXES" 4730 [(parallel 4731 [(set (match_dup 3) (match_dup 5)) 4732 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])] 4733 ;; Checking the previous insn is a bit too awkward for the condition. 4734{ 4735 rtx_insn *prev = prev_nonnote_insn (curr_insn); 4736 if (prev != NULL_RTX) 4737 { 4738 rtx set = single_set (prev); 4739 if (set != NULL_RTX 4740 && REG_S_P (SET_DEST (set)) 4741 && REGNO (SET_DEST (set)) == REGNO (operands[0]) 4742 && REG_S_P (SET_SRC (set))) 4743 FAIL; 4744 } 4745 operands[5] 4746 = replace_equiv_address (operands[4], 4747 gen_rtx_PLUS (SImode, 4748 operands[1], operands[2])); 4749}) 4750 4751;; Vice versa: move ry,[rx=rx+n] 4752 4753(define_peephole2 ; movemsideqi (peephole casesi+36) 4754 [(set (match_operand:SI 0 "register_operand" "") 4755 (plus:SI (match_operand:SI 1 "register_operand" "") 4756 (match_operand:SI 2 "const_int_operand" ""))) 4757 (set (match_operator 3 "cris_mem_op" [(match_dup 0)]) 4758 (match_operand 4 "register_operand" ""))] 4759 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD 4760 && REGNO (operands[4]) != REGNO (operands[0]) 4761 && (cris_base_p (operands[1], true) || cris_base_p (operands[2], true)) 4762 && !satisfies_constraint_J (operands[2]) 4763 && !satisfies_constraint_N (operands[2]) 4764 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128) 4765 && TARGET_SIDE_EFFECT_PREFIXES" 4766 [(parallel 4767 [(set (match_dup 5) (match_dup 4)) 4768 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])] 4769 "operands[5] 4770 = replace_equiv_address (operands[3], 4771 gen_rtx_PLUS (SImode, 4772 operands[1], operands[2]));") 4773 4774;; As above, change: 4775;; add.d n,rx 4776;; op.d [rx],ry 4777;; into: 4778;; op.d [rx=rx+n],ry 4779;; Saves when n = [-128..127]. 4780;; 4781;; Splitting and joining combinations for side-effect modes are slightly 4782;; out of hand. They probably will not save the time they take typing in, 4783;; not to mention the bugs that creep in. FIXME: Get rid of as many of 4784;; the splits and peepholes as possible. 4785;; No stable test-case. 4786 4787(define_peephole2 ; mover2side (peephole casesi+37) 4788 [(set (match_operand:SI 0 "register_operand" "") 4789 (plus:SI (match_operand:SI 1 "register_operand" "") 4790 (match_operand:SI 2 "const_int_operand" ""))) 4791 (set (match_operand 3 "register_operand" "") 4792 (match_operator 4 "cris_orthogonal_operator" 4793 [(match_dup 3) 4794 (match_operator 4795 5 "cris_mem_op" [(match_dup 0)])]))] 4796 ;; FIXME: What about DFmode? 4797 ;; Change to GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD? 4798 "GET_MODE (operands[3]) != DImode 4799 && REGNO (operands[0]) != REGNO (operands[3]) 4800 && !satisfies_constraint_J (operands[2]) 4801 && !satisfies_constraint_N (operands[2]) 4802 && INTVAL (operands[2]) >= -128 4803 && INTVAL (operands[2]) <= 127 4804 && TARGET_SIDE_EFFECT_PREFIXES" 4805 [(parallel 4806 [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)])) 4807 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])] 4808 "operands[6] 4809 = replace_equiv_address (operands[5], 4810 gen_rtx_PLUS (SImode, 4811 operands[1], operands[2]));") 4812 4813;; Sometimes, for some reason the pattern 4814;; move x,rx 4815;; add y,rx 4816;; move [rx],rz 4817;; will occur. Solve this, and likewise for to-memory. 4818;; No stable test-case. 4819 4820(define_peephole2 ; moverside (peephole casesi+38) 4821 [(set (match_operand:SI 0 "register_operand" "") 4822 (match_operand:SI 1 "cris_bdap_biap_operand" "")) 4823 (set (match_dup 0) 4824 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "") 4825 (match_operand:SI 3 "cris_bdap_biap_operand" ""))) 4826 (set (match_operand 4 "register_operand" "") 4827 (match_operator 5 "cris_mem_op" [(match_dup 0)]))] 4828 "(rtx_equal_p (operands[2], operands[0]) 4829 || rtx_equal_p (operands[3], operands[0])) 4830 && cris_side_effect_mode_ok (PLUS, operands, 0, 4831 (REG_S_P (operands[1]) 4832 ? 1 4833 : (rtx_equal_p (operands[2], operands[0]) 4834 ? 3 : 2)), 4835 (! REG_S_P (operands[1]) 4836 ? 1 4837 : (rtx_equal_p (operands[2], operands[0]) 4838 ? 3 : 2)), 4839 -1, 4)" 4840 [(parallel 4841 [(set (match_dup 4) (match_dup 6)) 4842 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])] 4843{ 4844 rtx otherop 4845 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2]; 4846 4847 /* Make sure we have canonical RTX so we match the insn pattern - 4848 not a constant in the first operand. We also require the order 4849 (plus reg mem) to match the final pattern. */ 4850 if (CRIS_CONSTANT_P (otherop) || MEM_P (otherop)) 4851 { 4852 operands[7] = operands[1]; 4853 operands[8] = otherop; 4854 } 4855 else 4856 { 4857 operands[7] = otherop; 4858 operands[8] = operands[1]; 4859 } 4860 operands[6] 4861 = replace_equiv_address (operands[5], 4862 gen_rtx_PLUS (SImode, 4863 operands[7], operands[8])); 4864}) 4865 4866;; As above but to memory. 4867;; FIXME: Split movemside and moverside into variants and prune 4868;; the ones that don't trig. 4869;; No stable test-case. 4870 4871(define_peephole2 ; movemside (peephole casesi+39) 4872 [(set (match_operand:SI 0 "register_operand" "") 4873 (match_operand:SI 1 "cris_bdap_biap_operand" "")) 4874 (set (match_dup 0) 4875 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "") 4876 (match_operand:SI 3 "cris_bdap_biap_operand" ""))) 4877 (set (match_operator 4 "cris_mem_op" [(match_dup 0)]) 4878 (match_operand 5 "register_operand" ""))] 4879 "(rtx_equal_p (operands[2], operands[0]) 4880 || rtx_equal_p (operands[3], operands[0])) 4881 && cris_side_effect_mode_ok (PLUS, operands, 0, 4882 (REG_S_P (operands[1]) 4883 ? 1 4884 : (rtx_equal_p (operands[2], operands[0]) 4885 ? 3 : 2)), 4886 (! REG_S_P (operands[1]) 4887 ? 1 4888 : (rtx_equal_p (operands[2], operands[0]) 4889 ? 3 : 2)), 4890 -1, 5)" 4891 [(parallel 4892 [(set (match_dup 6) (match_dup 5)) 4893 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])] 4894{ 4895 rtx otherop 4896 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2]; 4897 4898 /* Make sure we have canonical RTX so we match the insn pattern - 4899 not a constant in the first operand. We also require the order 4900 (plus reg mem) to match the final pattern. */ 4901 if (CRIS_CONSTANT_P (otherop) || MEM_P (otherop)) 4902 { 4903 operands[7] = operands[1]; 4904 operands[8] = otherop; 4905 } 4906 else 4907 { 4908 operands[7] = otherop; 4909 operands[8] = operands[1]; 4910 } 4911 operands[6] 4912 = replace_equiv_address (operands[4], 4913 gen_rtx_PLUS (SImode, 4914 operands[7], operands[8])); 4915}) 4916 4917;; Another spotted bad code: 4918;; move rx,ry 4919;; move [ry],ry 4920;; No stable test-case. 4921 4922(define_peephole2 ; movei (peephole casesi+42) 4923 [(set (match_operand:SI 0 "register_operand" "") 4924 (match_operand:SI 1 "register_operand" "")) 4925 (set (match_operand 2 "register_operand" "") 4926 (match_operator 3 "cris_mem_op" [(match_dup 0)]))] 4927 "REGNO (operands[0]) == REGNO (operands[2]) 4928 && (REGNO_REG_CLASS (REGNO (operands[0])) 4929 == REGNO_REG_CLASS (REGNO (operands[1]))) 4930 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD" 4931 [(set (match_dup 2) (match_dup 4))] 4932 "operands[4] = replace_equiv_address (operands[3], operands[1]);") 4933 4934;; move.d [r10+16],r9 4935;; and.d r12,r9 4936;; change to 4937;; and.d [r10+16],r12,r9 4938;; With generalization of the operation, the size and the addressing mode. 4939;; This seems to be the result of a quirk in register allocation 4940;; missing the three-operand cases when having different predicates. 4941;; Maybe that it matters that it is a commutative operation. 4942;; This pattern helps that situation, but there's still the increased 4943;; register pressure. 4944;; Note that adding the noncommutative variant did not show any matches 4945;; in ipps and cc1, so it's not here. 4946;; No stable test-case. 4947 4948(define_peephole2 ; op3 (peephole casesi+44) 4949 [(set (match_operand 0 "register_operand" "") 4950 (match_operator 4951 6 "cris_mem_op" 4952 [(plus:SI 4953 (match_operand:SI 1 "cris_bdap_biap_operand" "") 4954 (match_operand:SI 2 "cris_bdap_biap_operand" ""))])) 4955 (set (match_dup 0) 4956 (match_operator 4957 5 "cris_commutative_orth_op" 4958 [(match_operand 3 "register_operand" "") 4959 (match_operand 4 "register_operand" "")]))] 4960 "(rtx_equal_p (operands[3], operands[0]) 4961 || rtx_equal_p (operands[4], operands[0])) 4962 && ! rtx_equal_p (operands[3], operands[4]) 4963 && (REG_S_P (operands[1]) || REG_S_P (operands[2])) 4964 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD" 4965 [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))] 4966 "operands[7] 4967 = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];") 4968 4969;; There seems to be no other way to make GCC (including 4.8/trunk at 4970;; r186932) optimally reload an instruction that looks like 4971;; and.d reg_or_mem,const_32__65535,other_reg 4972;; where other_reg is the destination. 4973;; It should be: 4974;; movu.[bw] reg_or_mem,reg_32 4975;; and.[bw] trunc_int_for_mode([bw], const_32__65535),reg_32 ;; or andq 4976;; but it turns into: 4977;; move.d reg_or_mem,reg_32 4978;; and.d const_32__65535,reg_32 4979;; Fix it with these two peephole2's. 4980;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c 4981 4982(define_peephole2 ; andu (casesi+45) 4983 [(set (match_operand:SI 0 "register_operand" "") 4984 (match_operand:SI 1 "nonimmediate_operand" "")) 4985 (set (match_operand:SI 2 "register_operand" "") 4986 (and:SI (match_dup 0) 4987 (match_operand:SI 3 "const_int_operand" "")))] 4988 ;; Since the size of the memory access could be made different here, 4989 ;; don't do this for a mem-volatile access. 4990 "REGNO (operands[2]) == REGNO (operands[0]) 4991 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0 4992 && !satisfies_constraint_I (operands[3]) 4993 && !side_effects_p (operands[1]) 4994 && (!REG_P (operands[1]) 4995 || REGNO (operands[1]) <= CRIS_LAST_GENERAL_REGISTER)" 4996 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE). 4997 [(set (match_dup 0) (match_dup 4)) 4998 (set (match_dup 5) (match_dup 6))] 4999{ 5000 machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode; 5001 machine_mode amode 5002 = satisfies_constraint_O (operands[3]) ? SImode : zmode; 5003 rtx op1 5004 = (REG_S_P (operands[1]) 5005 ? gen_rtx_REG (zmode, REGNO (operands[1])) 5006 : adjust_address (operands[1], zmode, 0)); 5007 operands[4] 5008 = gen_rtx_ZERO_EXTEND (SImode, op1); 5009 operands[5] = gen_rtx_REG (amode, REGNO (operands[0])); 5010 operands[6] 5011 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])), 5012 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]), 5013 amode == SImode 5014 ? QImode : amode))); 5015}) 5016 5017;; Since r186861, gcc.dg/cris-peep2-andu2.c trigs this pattern, with which 5018;; we fix up e.g.: 5019;; movu.b 254,$r9. 5020;; and.d $r10,$r9 5021;; into: 5022;; movu.b $r10,$r9 5023;; andq -2,$r9. 5024;; Only do this for values fitting the quick immediate operand. 5025(define_peephole2 ; andqu (casesi+46) 5026 [(set (match_operand:SI 0 "register_operand") 5027 (match_operand:SI 1 "const_int_operand")) 5028 (set (match_dup 0) 5029 (and:SI (match_dup 0) (match_operand:SI 2 "nonimmediate_operand")))] 5030 ;; Since the size of the memory access will be made different here, 5031 ;; don't do this for a volatile access or a post-incremented address. 5032 "satisfies_constraint_O (operands[1]) 5033 && !side_effects_p (operands[2]) 5034 && !reg_overlap_mentioned_p (operands[0], operands[2])" 5035 [(set (match_dup 0) (match_dup 3)) 5036 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] 5037{ 5038 machine_mode zmode = INTVAL (operands[2]) <= 255 ? QImode : HImode; 5039 rtx op1 5040 = (REG_S_P (operands[2]) 5041 ? gen_rtx_REG (zmode, REGNO (operands[2])) 5042 : adjust_address (operands[2], zmode, 0)); 5043 operands[3] = gen_rtx_ZERO_EXTEND (SImode, op1); 5044 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode)); 5045}) 5046 5047;; Try and avoid GOTPLT reads escaping a call: transform them into 5048;; PLT. Curiously (but thankfully), peepholes for instructions 5049;; *without side-effects* that just feed a call (or call_value) are 5050;; not matched neither in a build or test-suite, so those patterns are 5051;; omitted. 5052 5053;; A "normal" move where we don't check the consumer. 5054 5055(define_peephole2 ; gotplt-to-plt 5056 [(set 5057 (match_operand:SI 0 "register_operand" "") 5058 (match_operator:SI 5059 1 "cris_mem_op" 5060 [(plus:SI 5061 (reg:SI CRIS_GOT_REGNUM) 5062 (const:SI 5063 (unspec:SI [(match_operand:SI 2 "cris_general_operand_or_symbol" "")] 5064 CRIS_UNSPEC_PLTGOTREAD)))]))] 5065 "flag_pic 5066 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true) 5067 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)" 5068 [(set (match_dup 0) (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL))) 5069 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))] 5070 "") 5071 5072;; And one set with a side-effect getting the PLTGOT offset. 5073;; First call and call_value variants. 5074 5075(define_peephole2 ; gotplt-to-plt-side-call 5076 [(parallel 5077 [(set 5078 (match_operand:SI 0 "register_operand" "") 5079 (match_operator:SI 5080 1 "cris_mem_op" 5081 [(plus:SI 5082 (reg:SI CRIS_GOT_REGNUM) 5083 (const:SI 5084 (unspec:SI [(match_operand:SI 5085 2 "cris_general_operand_or_symbol" "")] 5086 CRIS_UNSPEC_PLTGOTREAD)))])) 5087 (set (match_operand:SI 3 "register_operand" "") 5088 (plus:SI (reg:SI CRIS_GOT_REGNUM) 5089 (const:SI 5090 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))]) 5091 (parallel [(call (mem:QI (match_dup 0)) 5092 (match_operand 4 "" "")) 5093 (clobber (reg:SI CRIS_SRP_REGNUM))])] 5094 "flag_pic 5095 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true) 5096 && peep2_reg_dead_p (2, operands[0])" 5097 [(parallel [(call (mem:QI (match_dup 1)) 5098 (match_dup 4)) 5099 (clobber (reg:SI CRIS_SRP_REGNUM)) 5100 (set (match_dup 3) 5101 (plus:SI (reg:SI CRIS_GOT_REGNUM) 5102 (const:SI 5103 (unspec:SI [(match_dup 2)] 5104 CRIS_UNSPEC_PLTGOTREAD))))])] 5105 "") 5106 5107(define_peephole2 ; gotplt-to-plt-side-call-value 5108 [(parallel 5109 [(set 5110 (match_operand:SI 0 "register_operand" "") 5111 (match_operator:SI 5112 1 "cris_mem_op" 5113 [(plus:SI 5114 (reg:SI CRIS_GOT_REGNUM) 5115 (const:SI 5116 (unspec:SI [(match_operand:SI 5117 2 "cris_general_operand_or_symbol" "")] 5118 CRIS_UNSPEC_PLTGOTREAD)))])) 5119 (set (match_operand:SI 3 "register_operand" "") 5120 (plus:SI (reg:SI CRIS_GOT_REGNUM) 5121 (const:SI 5122 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))]) 5123 (parallel [(set (match_operand 5 "" "") 5124 (call (mem:QI (match_dup 0)) 5125 (match_operand 4 "" ""))) 5126 (clobber (reg:SI CRIS_SRP_REGNUM))])] 5127 "flag_pic 5128 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true) 5129 && peep2_reg_dead_p (2, operands[0])" 5130 [(parallel [(set (match_dup 5) 5131 (call (mem:QI (match_dup 1)) 5132 (match_dup 4))) 5133 (clobber (reg:SI CRIS_SRP_REGNUM)) 5134 (set (match_dup 3) 5135 (plus:SI (reg:SI CRIS_GOT_REGNUM) 5136 (const:SI 5137 (unspec:SI [(match_dup 2)] 5138 CRIS_UNSPEC_PLTGOTREAD))))])] 5139 "") 5140 5141(define_peephole2 ; gotplt-to-plt-side 5142 [(parallel 5143 [(set 5144 (match_operand:SI 0 "register_operand" "") 5145 (match_operator:SI 5146 1 "cris_mem_op" 5147 [(plus:SI 5148 (reg:SI CRIS_GOT_REGNUM) 5149 (const:SI 5150 (unspec:SI [(match_operand:SI 5151 2 "cris_general_operand_or_symbol" "")] 5152 CRIS_UNSPEC_PLTGOTREAD)))])) 5153 (set (match_operand:SI 3 "register_operand" "") 5154 (plus:SI (reg:SI CRIS_GOT_REGNUM) 5155 (const:SI 5156 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])] 5157 "flag_pic 5158 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true) 5159 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)" 5160 [(set (match_dup 3) 5161 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))) 5162 (set (match_dup 3) (plus:SI (match_dup 3) (reg:SI CRIS_GOT_REGNUM))) 5163 (set (match_dup 0) 5164 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL))) 5165 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))] 5166 "") 5167 5168;; Local variables: 5169;; mode:emacs-lisp 5170;; comment-start: ";; " 5171;; eval: (set-syntax-table (copy-sequence (syntax-table))) 5172;; eval: (modify-syntax-entry ?[ "(]") 5173;; eval: (modify-syntax-entry ?] ")[") 5174;; eval: (modify-syntax-entry ?{ "(}") 5175;; eval: (modify-syntax-entry ?} "){") 5176;; eval: (setq indent-tabs-mode t) 5177;; End: 5178