1 /* Definitions for GCC. Part of the machine description for CRIS. 2 Copyright (C) 1998-2018 Free Software Foundation, Inc. 3 Contributed by Axis Communications. Written by Hans-Peter Nilsson. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #define IN_TARGET_CODE 1 22 23 #include "config.h" 24 #include "system.h" 25 #include "coretypes.h" 26 #include "backend.h" 27 #include "target.h" 28 #include "rtl.h" 29 #include "tree.h" 30 #include "stringpool.h" 31 #include "attribs.h" 32 #include "cfghooks.h" 33 #include "df.h" 34 #include "memmodel.h" 35 #include "tm_p.h" 36 #include "optabs.h" 37 #include "regs.h" 38 #include "emit-rtl.h" 39 #include "recog.h" 40 #include "cgraph.h" 41 #include "diagnostic-core.h" 42 #include "conditions.h" 43 #include "insn-attr.h" 44 #include "alias.h" 45 #include "varasm.h" 46 #include "stor-layout.h" 47 #include "calls.h" 48 #include "explow.h" 49 #include "expr.h" 50 #include "reload.h" 51 #include "output.h" 52 #include "tm-constrs.h" 53 #include "builtins.h" 54 55 /* This file should be included last. */ 56 #include "target-def.h" 57 58 /* Usable when we have an amount to add or subtract, and want the 59 optimal size of the insn. */ 60 #define ADDITIVE_SIZE_MODIFIER(size) \ 61 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d") 62 63 #define LOSE_AND_RETURN(msgid, x) \ 64 do \ 65 { \ 66 cris_operand_lossage (msgid, x); \ 67 return; \ 68 } while (0) 69 70 enum cris_retinsn_type 71 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP }; 72 73 /* Per-function machine data. */ 74 struct GTY(()) machine_function 75 { 76 int needs_return_address_on_stack; 77 78 /* This is the number of registers we save in the prologue due to 79 stdarg. */ 80 int stdarg_regs; 81 82 enum cris_retinsn_type return_type; 83 }; 84 85 /* This little fix suppresses the 'u' or 's' when '%e' in assembly 86 pattern. */ 87 static char cris_output_insn_is_bound = 0; 88 89 /* In code for output macros, this is how we know whether e.g. constant 90 goes in code or in a static initializer. */ 91 static int in_code = 0; 92 93 /* Fix for reg_overlap_mentioned_p. */ 94 static int cris_reg_overlap_mentioned_p (rtx, rtx); 95 96 static machine_mode cris_promote_function_mode (const_tree, machine_mode, 97 int *, const_tree, int); 98 99 static unsigned int cris_atomic_align_for_mode (machine_mode); 100 101 static void cris_print_base (rtx, FILE *); 102 103 static void cris_print_index (rtx, FILE *); 104 105 static void cris_output_addr_const (FILE *, rtx); 106 107 static struct machine_function * cris_init_machine_status (void); 108 109 static rtx cris_struct_value_rtx (tree, int); 110 111 static void cris_setup_incoming_varargs (cumulative_args_t, machine_mode, 112 tree type, int *, int); 113 114 static int cris_initial_frame_pointer_offset (void); 115 116 static void cris_operand_lossage (const char *, rtx); 117 118 static int cris_reg_saved_in_regsave_area (unsigned int, bool); 119 120 static void cris_print_operand (FILE *, rtx, int); 121 122 static void cris_print_operand_address (FILE *, machine_mode, rtx); 123 124 static bool cris_print_operand_punct_valid_p (unsigned char code); 125 126 static bool cris_output_addr_const_extra (FILE *, rtx); 127 128 static void cris_conditional_register_usage (void); 129 130 static void cris_asm_output_mi_thunk 131 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); 132 133 static void cris_file_start (void); 134 static void cris_init_libfuncs (void); 135 136 static reg_class_t cris_preferred_reload_class (rtx, reg_class_t); 137 138 static int cris_register_move_cost (machine_mode, reg_class_t, reg_class_t); 139 static int cris_memory_move_cost (machine_mode, reg_class_t, bool); 140 static bool cris_rtx_costs (rtx, machine_mode, int, int, int *, bool); 141 static int cris_address_cost (rtx, machine_mode, addr_space_t, bool); 142 static bool cris_pass_by_reference (cumulative_args_t, machine_mode, 143 const_tree, bool); 144 static int cris_arg_partial_bytes (cumulative_args_t, machine_mode, 145 tree, bool); 146 static rtx cris_function_arg (cumulative_args_t, machine_mode, 147 const_tree, bool); 148 static rtx cris_function_incoming_arg (cumulative_args_t, 149 machine_mode, const_tree, bool); 150 static void cris_function_arg_advance (cumulative_args_t, machine_mode, 151 const_tree, bool); 152 static rtx_insn *cris_md_asm_adjust (vec<rtx> &, vec<rtx> &, 153 vec<const char *> &, 154 vec<rtx> &, HARD_REG_SET &); 155 static bool cris_cannot_force_const_mem (machine_mode, rtx); 156 157 static void cris_option_override (void); 158 159 static bool cris_frame_pointer_required (void); 160 161 static void cris_asm_trampoline_template (FILE *); 162 static void cris_trampoline_init (rtx, tree, rtx); 163 164 static rtx cris_function_value(const_tree, const_tree, bool); 165 static rtx cris_libcall_value (machine_mode, const_rtx); 166 static bool cris_function_value_regno_p (const unsigned int); 167 static void cris_file_end (void); 168 static unsigned int cris_hard_regno_nregs (unsigned int, machine_mode); 169 static bool cris_hard_regno_mode_ok (unsigned int, machine_mode); 170 static HOST_WIDE_INT cris_static_rtx_alignment (machine_mode); 171 static HOST_WIDE_INT cris_constant_alignment (const_tree, HOST_WIDE_INT); 172 173 /* This is the parsed result of the "-max-stack-stackframe=" option. If 174 it (still) is zero, then there was no such option given. */ 175 int cris_max_stackframe = 0; 176 177 /* This is the parsed result of the "-march=" option, if given. */ 178 int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; 179 180 #undef TARGET_ASM_ALIGNED_HI_OP 181 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 182 #undef TARGET_ASM_ALIGNED_SI_OP 183 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t" 184 #undef TARGET_ASM_ALIGNED_DI_OP 185 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" 186 187 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only 188 available in ELF. These "normal" pseudos do not have any alignment 189 constraints or side-effects. */ 190 #undef TARGET_ASM_UNALIGNED_HI_OP 191 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP 192 193 #undef TARGET_ASM_UNALIGNED_SI_OP 194 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP 195 196 #undef TARGET_ASM_UNALIGNED_DI_OP 197 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP 198 199 #undef TARGET_PRINT_OPERAND 200 #define TARGET_PRINT_OPERAND cris_print_operand 201 #undef TARGET_PRINT_OPERAND_ADDRESS 202 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address 203 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 204 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p 205 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA 206 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra 207 208 #undef TARGET_CONDITIONAL_REGISTER_USAGE 209 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage 210 211 #undef TARGET_ASM_OUTPUT_MI_THUNK 212 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk 213 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 214 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 215 216 #undef TARGET_ASM_FILE_START 217 #define TARGET_ASM_FILE_START cris_file_start 218 #undef TARGET_ASM_FILE_END 219 #define TARGET_ASM_FILE_END cris_file_end 220 221 #undef TARGET_INIT_LIBFUNCS 222 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs 223 224 #undef TARGET_LRA_P 225 #define TARGET_LRA_P hook_bool_void_false 226 227 #undef TARGET_LEGITIMATE_ADDRESS_P 228 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p 229 230 #undef TARGET_LEGITIMATE_CONSTANT_P 231 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p 232 233 #undef TARGET_PREFERRED_RELOAD_CLASS 234 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class 235 236 #undef TARGET_REGISTER_MOVE_COST 237 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost 238 #undef TARGET_MEMORY_MOVE_COST 239 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost 240 #undef TARGET_RTX_COSTS 241 #define TARGET_RTX_COSTS cris_rtx_costs 242 #undef TARGET_ADDRESS_COST 243 #define TARGET_ADDRESS_COST cris_address_cost 244 245 #undef TARGET_PROMOTE_FUNCTION_MODE 246 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode 247 248 #undef TARGET_ATOMIC_ALIGN_FOR_MODE 249 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode 250 251 #undef TARGET_STRUCT_VALUE_RTX 252 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx 253 #undef TARGET_SETUP_INCOMING_VARARGS 254 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs 255 #undef TARGET_PASS_BY_REFERENCE 256 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference 257 #undef TARGET_ARG_PARTIAL_BYTES 258 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes 259 #undef TARGET_FUNCTION_ARG 260 #define TARGET_FUNCTION_ARG cris_function_arg 261 #undef TARGET_FUNCTION_INCOMING_ARG 262 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg 263 #undef TARGET_FUNCTION_ARG_ADVANCE 264 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance 265 #undef TARGET_MD_ASM_ADJUST 266 #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust 267 268 #undef TARGET_CANNOT_FORCE_CONST_MEM 269 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem 270 271 #undef TARGET_FRAME_POINTER_REQUIRED 272 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required 273 274 #undef TARGET_OPTION_OVERRIDE 275 #define TARGET_OPTION_OVERRIDE cris_option_override 276 277 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE 278 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template 279 #undef TARGET_TRAMPOLINE_INIT 280 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init 281 282 #undef TARGET_FUNCTION_VALUE 283 #define TARGET_FUNCTION_VALUE cris_function_value 284 #undef TARGET_LIBCALL_VALUE 285 #define TARGET_LIBCALL_VALUE cris_libcall_value 286 #undef TARGET_FUNCTION_VALUE_REGNO_P 287 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p 288 289 #undef TARGET_HARD_REGNO_NREGS 290 #define TARGET_HARD_REGNO_NREGS cris_hard_regno_nregs 291 #undef TARGET_HARD_REGNO_MODE_OK 292 #define TARGET_HARD_REGNO_MODE_OK cris_hard_regno_mode_ok 293 294 #undef TARGET_STATIC_RTX_ALIGNMENT 295 #define TARGET_STATIC_RTX_ALIGNMENT cris_static_rtx_alignment 296 #undef TARGET_CONSTANT_ALIGNMENT 297 #define TARGET_CONSTANT_ALIGNMENT cris_constant_alignment 298 299 struct gcc_target targetm = TARGET_INITIALIZER; 300 301 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */ 302 303 bool 304 cris_movem_load_rest_p (rtx op, int offs) 305 { 306 unsigned int reg_count = XVECLEN (op, 0) - offs; 307 rtx src_addr; 308 int i; 309 rtx elt; 310 int setno; 311 int regno_dir = 1; 312 unsigned int regno = 0; 313 314 /* Perform a quick check so we don't blow up below. FIXME: Adjust for 315 other than (MEM reg). */ 316 if (reg_count <= 1 317 || GET_CODE (XVECEXP (op, 0, offs)) != SET 318 || !REG_P (SET_DEST (XVECEXP (op, 0, offs))) 319 || !MEM_P (SET_SRC (XVECEXP (op, 0, offs)))) 320 return false; 321 322 /* Check a possible post-inc indicator. */ 323 if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS) 324 { 325 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0); 326 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1); 327 328 reg_count--; 329 330 if (reg_count == 1 331 || !REG_P (reg) 332 || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1))) 333 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1))) 334 || !CONST_INT_P (inc) 335 || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4) 336 return false; 337 i = offs + 2; 338 } 339 else 340 i = offs + 1; 341 342 if (!TARGET_V32) 343 { 344 regno_dir = -1; 345 regno = reg_count - 1; 346 } 347 348 elt = XVECEXP (op, 0, offs); 349 src_addr = XEXP (SET_SRC (elt), 0); 350 351 if (GET_CODE (elt) != SET 352 || !REG_P (SET_DEST (elt)) 353 || GET_MODE (SET_DEST (elt)) != SImode 354 || REGNO (SET_DEST (elt)) != regno 355 || !MEM_P (SET_SRC (elt)) 356 || GET_MODE (SET_SRC (elt)) != SImode 357 || !memory_address_p (SImode, src_addr)) 358 return false; 359 360 for (setno = 1; i < XVECLEN (op, 0); setno++, i++) 361 { 362 rtx elt = XVECEXP (op, 0, i); 363 regno += regno_dir; 364 365 if (GET_CODE (elt) != SET 366 || !REG_P (SET_DEST (elt)) 367 || GET_MODE (SET_DEST (elt)) != SImode 368 || REGNO (SET_DEST (elt)) != regno 369 || !MEM_P (SET_SRC (elt)) 370 || GET_MODE (SET_SRC (elt)) != SImode 371 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS 372 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) 373 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1)) 374 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4) 375 return false; 376 } 377 378 return true; 379 } 380 381 /* Worker function for predicate for the parallel contents in a movem 382 to-memory. */ 383 384 bool 385 cris_store_multiple_op_p (rtx op) 386 { 387 int reg_count = XVECLEN (op, 0); 388 rtx dest; 389 rtx dest_addr; 390 rtx dest_base; 391 int i; 392 rtx elt; 393 int setno; 394 int regno_dir = 1; 395 int regno = 0; 396 int offset = 0; 397 398 /* Perform a quick check so we don't blow up below. FIXME: Adjust for 399 other than (MEM reg) and (MEM (PLUS reg const)). */ 400 if (reg_count <= 1) 401 return false; 402 403 elt = XVECEXP (op, 0, 0); 404 405 if (GET_CODE (elt) != SET) 406 return false; 407 408 dest = SET_DEST (elt); 409 410 if (!REG_P (SET_SRC (elt)) || !MEM_P (dest)) 411 return false; 412 413 dest_addr = XEXP (dest, 0); 414 415 /* Check a possible post-inc indicator. */ 416 if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS) 417 { 418 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0); 419 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1); 420 421 reg_count--; 422 423 if (reg_count == 1 424 || !REG_P (reg) 425 || !REG_P (SET_DEST (XVECEXP (op, 0, 1))) 426 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1))) 427 || !CONST_INT_P (inc) 428 /* Support increment by number of registers, and by the offset 429 of the destination, if it has the form (MEM (PLUS reg 430 offset)). */ 431 || !((REG_P (dest_addr) 432 && REGNO (dest_addr) == REGNO (reg) 433 && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4) 434 || (GET_CODE (dest_addr) == PLUS 435 && REG_P (XEXP (dest_addr, 0)) 436 && REGNO (XEXP (dest_addr, 0)) == REGNO (reg) 437 && CONST_INT_P (XEXP (dest_addr, 1)) 438 && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc)))) 439 return false; 440 441 i = 2; 442 } 443 else 444 i = 1; 445 446 if (!TARGET_V32) 447 { 448 regno_dir = -1; 449 regno = reg_count - 1; 450 } 451 452 if (GET_CODE (elt) != SET 453 || !REG_P (SET_SRC (elt)) 454 || GET_MODE (SET_SRC (elt)) != SImode 455 || REGNO (SET_SRC (elt)) != (unsigned int) regno 456 || !MEM_P (SET_DEST (elt)) 457 || GET_MODE (SET_DEST (elt)) != SImode) 458 return false; 459 460 if (REG_P (dest_addr)) 461 { 462 dest_base = dest_addr; 463 offset = 0; 464 } 465 else if (GET_CODE (dest_addr) == PLUS 466 && REG_P (XEXP (dest_addr, 0)) 467 && CONST_INT_P (XEXP (dest_addr, 1))) 468 { 469 dest_base = XEXP (dest_addr, 0); 470 offset = INTVAL (XEXP (dest_addr, 1)); 471 } 472 else 473 return false; 474 475 for (setno = 1; i < XVECLEN (op, 0); setno++, i++) 476 { 477 rtx elt = XVECEXP (op, 0, i); 478 regno += regno_dir; 479 480 if (GET_CODE (elt) != SET 481 || !REG_P (SET_SRC (elt)) 482 || GET_MODE (SET_SRC (elt)) != SImode 483 || REGNO (SET_SRC (elt)) != (unsigned int) regno 484 || !MEM_P (SET_DEST (elt)) 485 || GET_MODE (SET_DEST (elt)) != SImode 486 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS 487 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base) 488 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1)) 489 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset) 490 return false; 491 } 492 493 return true; 494 } 495 496 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */ 497 498 static void 499 cris_conditional_register_usage (void) 500 { 501 /* FIXME: This isn't nice. We should be able to use that register for 502 something else if the PIC table isn't needed. */ 503 if (flag_pic) 504 fixed_regs[PIC_OFFSET_TABLE_REGNUM] 505 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; 506 507 /* Allow use of ACR (PC in pre-V32) and tweak order. */ 508 if (TARGET_V32) 509 { 510 static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32; 511 unsigned int i; 512 513 fixed_regs[CRIS_ACR_REGNUM] = 0; 514 515 for (i = 0; 516 i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]); 517 i++) 518 reg_alloc_order[i] = reg_alloc_order_v32[i]; 519 } 520 521 if (TARGET_HAS_MUL_INSNS) 522 fixed_regs[CRIS_MOF_REGNUM] = 0; 523 524 /* On early versions, we must use the 16-bit condition-code register, 525 which has another name. */ 526 if (cris_cpu_version < 8) 527 reg_names[CRIS_CC0_REGNUM] = "ccr"; 528 } 529 530 /* Return crtl->uses_pic_offset_table. For use in cris.md, 531 since some generated files do not include function.h. */ 532 533 int 534 cris_cfun_uses_pic_table (void) 535 { 536 return crtl->uses_pic_offset_table; 537 } 538 539 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM. 540 We can't put PIC addresses in the constant pool, not even the ones that 541 can be reached as pc-relative as we can't tell when or how to do that. */ 542 543 static bool 544 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 545 { 546 enum cris_symbol_type t = cris_symbol_type_of (x); 547 548 return 549 t == cris_unspec 550 || t == cris_got_symbol 551 || t == cris_rel_symbol; 552 } 553 554 /* Given an rtx, return the text string corresponding to the CODE of X. 555 Intended for use in the assembly language output section of a 556 define_insn. */ 557 558 const char * 559 cris_op_str (rtx x) 560 { 561 cris_output_insn_is_bound = 0; 562 switch (GET_CODE (x)) 563 { 564 case PLUS: 565 return "add"; 566 567 case MINUS: 568 return "sub"; 569 570 case MULT: 571 /* This function is for retrieving a part of an instruction name for 572 an operator, for immediate output. If that ever happens for 573 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure 574 we notice. */ 575 internal_error ("MULT case in cris_op_str"); 576 break; 577 578 case DIV: 579 return "div"; 580 581 case AND: 582 return "and"; 583 584 case IOR: 585 return "or"; 586 587 case XOR: 588 return "xor"; 589 590 case NOT: 591 return "not"; 592 593 case ASHIFT: 594 return "lsl"; 595 596 case LSHIFTRT: 597 return "lsr"; 598 599 case ASHIFTRT: 600 return "asr"; 601 602 case UMIN: 603 /* Used to control the sign/zero-extend character for the 'E' modifier. 604 BOUND has none. */ 605 cris_output_insn_is_bound = 1; 606 return "bound"; 607 608 default: 609 return "Unknown operator"; 610 } 611 } 612 613 /* Emit an error message when we're in an asm, and a fatal error for 614 "normal" insns. Formatted output isn't easily implemented, since we 615 use output_operand_lossage to output the actual message and handle the 616 categorization of the error. */ 617 618 static void 619 cris_operand_lossage (const char *msgid, rtx op) 620 { 621 debug_rtx (op); 622 output_operand_lossage ("%s", msgid); 623 } 624 625 /* Print an index part of an address to file. */ 626 627 static void 628 cris_print_index (rtx index, FILE *file) 629 { 630 /* Make the index "additive" unless we'll output a negative number, in 631 which case the sign character is free (as in free beer). */ 632 if (!CONST_INT_P (index) || INTVAL (index) >= 0) 633 putc ('+', file); 634 635 if (REG_P (index)) 636 fprintf (file, "$%s.b", reg_names[REGNO (index)]); 637 else if (CRIS_CONSTANT_P (index)) 638 cris_output_addr_const (file, index); 639 else if (GET_CODE (index) == MULT) 640 { 641 fprintf (file, "$%s.", 642 reg_names[REGNO (XEXP (index, 0))]); 643 644 putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file); 645 } 646 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0))) 647 { 648 rtx inner = XEXP (index, 0); 649 rtx inner_inner = XEXP (inner, 0); 650 651 if (GET_CODE (inner_inner) == POST_INC) 652 { 653 fprintf (file, "[$%s+].", 654 reg_names[REGNO (XEXP (inner_inner, 0))]); 655 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); 656 } 657 else 658 { 659 fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]); 660 661 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); 662 } 663 } 664 else if (MEM_P (index)) 665 { 666 rtx inner = XEXP (index, 0); 667 if (GET_CODE (inner) == POST_INC) 668 fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]); 669 else 670 fprintf (file, "[$%s].d", reg_names[REGNO (inner)]); 671 } 672 else 673 cris_operand_lossage ("unexpected index-type in cris_print_index", 674 index); 675 } 676 677 /* Print a base rtx of an address to file. */ 678 679 static void 680 cris_print_base (rtx base, FILE *file) 681 { 682 if (REG_P (base)) 683 fprintf (file, "$%s", reg_names[REGNO (base)]); 684 else if (GET_CODE (base) == POST_INC) 685 { 686 gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM); 687 fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]); 688 } 689 else 690 cris_operand_lossage ("unexpected base-type in cris_print_base", 691 base); 692 } 693 694 /* Usable as a guard in expressions. */ 695 696 int 697 cris_fatal (char *arg) 698 { 699 internal_error (arg); 700 701 /* We'll never get here; this is just to appease compilers. */ 702 return 0; 703 } 704 705 /* Return nonzero if REGNO is an ordinary register that *needs* to be 706 saved together with other registers, possibly by a MOVEM instruction, 707 or is saved for target-independent reasons. There may be 708 target-dependent reasons to save the register anyway; this is just a 709 wrapper for a complicated conditional. */ 710 711 static int 712 cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used) 713 { 714 return 715 (((df_regs_ever_live_p (regno) 716 && !call_used_regs[regno]) 717 || (regno == PIC_OFFSET_TABLE_REGNUM 718 && (got_really_used 719 /* It is saved anyway, if there would be a gap. */ 720 || (flag_pic 721 && df_regs_ever_live_p (regno + 1) 722 && !call_used_regs[regno + 1])))) 723 && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed) 724 && regno != CRIS_SRP_REGNUM) 725 || (crtl->calls_eh_return 726 && (regno == EH_RETURN_DATA_REGNO (0) 727 || regno == EH_RETURN_DATA_REGNO (1) 728 || regno == EH_RETURN_DATA_REGNO (2) 729 || regno == EH_RETURN_DATA_REGNO (3))); 730 } 731 732 /* The PRINT_OPERAND worker. */ 733 734 static void 735 cris_print_operand (FILE *file, rtx x, int code) 736 { 737 rtx operand = x; 738 739 /* Size-strings corresponding to MULT expressions. */ 740 static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" }; 741 742 /* New code entries should just be added to the switch below. If 743 handling is finished, just return. If handling was just a 744 modification of the operand, the modified operand should be put in 745 "operand", and then do a break to let default handling 746 (zero-modifier) output the operand. */ 747 748 switch (code) 749 { 750 case 'b': 751 /* Print the unsigned supplied integer as if it were signed 752 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */ 753 if (!satisfies_constraint_O (x)) 754 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x); 755 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 756 INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535)); 757 return; 758 759 case 'x': 760 /* Print assembler code for operator. */ 761 fprintf (file, "%s", cris_op_str (operand)); 762 return; 763 764 case 'o': 765 { 766 /* A movem modifier working on a parallel; output the register 767 name. */ 768 int regno; 769 770 if (GET_CODE (x) != PARALLEL) 771 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x); 772 773 /* The second item can be (set reg (plus reg const)) to denote a 774 postincrement. */ 775 regno 776 = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS 777 ? XVECLEN (x, 0) - 2 778 : XVECLEN (x, 0) - 1); 779 780 fprintf (file, "$%s", reg_names [regno]); 781 } 782 return; 783 784 case 'O': 785 { 786 /* A similar movem modifier; output the memory operand. */ 787 rtx addr; 788 789 if (GET_CODE (x) != PARALLEL) 790 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x); 791 792 /* The lowest mem operand is in the first item, but perhaps it 793 needs to be output as postincremented. */ 794 addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0))) 795 ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0) 796 : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0); 797 798 /* The second item can be a (set reg (plus reg const)) to denote 799 a modification. */ 800 if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS) 801 { 802 /* It's a post-increment, if the address is a naked (reg). */ 803 if (REG_P (addr)) 804 addr = gen_rtx_POST_INC (SImode, addr); 805 else 806 { 807 /* Otherwise, it's a side-effect; RN=RN+M. */ 808 fprintf (file, "[$%s=$%s%s%d]", 809 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))], 810 reg_names [REGNO (XEXP (addr, 0))], 811 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+", 812 (int) INTVAL (XEXP (addr, 1))); 813 return; 814 } 815 } 816 output_address (VOIDmode, addr); 817 } 818 return; 819 820 case 'p': 821 /* Adjust a power of two to its log2. */ 822 if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 ) 823 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x); 824 fprintf (file, "%d", exact_log2 (INTVAL (x))); 825 return; 826 827 case 's': 828 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535 829 respectively. This modifier also terminates the inhibiting 830 effects of the 'x' modifier. */ 831 cris_output_insn_is_bound = 0; 832 if (GET_MODE (x) == VOIDmode && CONST_INT_P (x)) 833 { 834 if (INTVAL (x) >= 0) 835 { 836 if (INTVAL (x) <= 255) 837 putc ('b', file); 838 else if (INTVAL (x) <= 65535) 839 putc ('w', file); 840 else 841 putc ('d', file); 842 } 843 else 844 putc ('d', file); 845 return; 846 } 847 848 /* For a non-integer, print the size of the operand. */ 849 putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode) 850 ? 'd' : GET_MODE (x) == HImode ? 'w' 851 : GET_MODE (x) == QImode ? 'b' 852 /* If none of the above, emit an erroneous size letter. */ 853 : 'X', 854 file); 855 return; 856 857 case 'z': 858 /* Const_int: print b for -127 <= x <= 255, 859 w for -32768 <= x <= 65535, else die. */ 860 if (!CONST_INT_P (x) 861 || INTVAL (x) < -32768 || INTVAL (x) > 65535) 862 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x); 863 putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file); 864 return; 865 866 case 'Z': 867 /* If this is a GOT-symbol, print the size-letter corresponding to 868 -fpic/-fPIC. For everything else, print "d". */ 869 putc ((flag_pic == 1 870 && GET_CODE (x) == CONST 871 && GET_CODE (XEXP (x, 0)) == UNSPEC 872 && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD) 873 ? 'w' : 'd', file); 874 return; 875 876 case '#': 877 /* Output a 'nop' if there's nothing for the delay slot. 878 This method stolen from the sparc files. */ 879 if (dbr_sequence_length () == 0) 880 fputs ("\n\tnop", file); 881 return; 882 883 case '!': 884 /* Output directive for alignment padded with "nop" insns. 885 Optimizing for size, it's plain 4-byte alignment, otherwise we 886 align the section to a cache-line (32 bytes) and skip at max 2 887 bytes, i.e. we skip if it's the last insn on a cache-line. The 888 latter is faster by a small amount (for two test-programs 99.6% 889 and 99.9%) and larger by a small amount (ditto 100.1% and 890 100.2%). This is supposed to be the simplest yet performance- 891 wise least intrusive way to make sure the immediately following 892 (supposed) muls/mulu insn isn't located at the end of a 893 cache-line. */ 894 if (TARGET_MUL_BUG) 895 fputs (optimize_size 896 ? ".p2alignw 2,0x050f\n\t" 897 : ".p2alignw 5,0x050f,2\n\t", file); 898 return; 899 900 case ':': 901 /* The PIC register. */ 902 if (! flag_pic) 903 internal_error ("invalid use of ':' modifier"); 904 fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]); 905 return; 906 907 case 'H': 908 /* Print high (most significant) part of something. */ 909 switch (GET_CODE (operand)) 910 { 911 case CONST_INT: 912 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode) 913 value is kept here, and so may be other than 0 or -1. */ 914 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 915 INTVAL (operand_subword (operand, 1, 0, DImode))); 916 return; 917 918 case CONST_DOUBLE: 919 /* High part of a long long constant. */ 920 if (GET_MODE (operand) == VOIDmode) 921 { 922 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x)); 923 return; 924 } 925 else 926 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); 927 928 case REG: 929 /* Print reg + 1. Check that there's not an attempt to print 930 high-parts of registers like stack-pointer or higher, except 931 for SRP (where the "high part" is MOF). */ 932 if (REGNO (operand) > STACK_POINTER_REGNUM - 2 933 && (REGNO (operand) != CRIS_SRP_REGNUM 934 || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM 935 || fixed_regs[CRIS_MOF_REGNUM] != 0)) 936 LOSE_AND_RETURN ("bad register", operand); 937 fprintf (file, "$%s", reg_names[REGNO (operand) + 1]); 938 return; 939 940 case MEM: 941 /* Adjust memory address to high part. */ 942 { 943 rtx adj_mem = operand; 944 int size 945 = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT; 946 947 /* Adjust so we can use two SImode in DImode. 948 Calling adj_offsettable_operand will make sure it is an 949 offsettable address. Don't do this for a postincrement 950 though; it should remain as it was. */ 951 if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC) 952 adj_mem 953 = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2); 954 955 output_address (VOIDmode, XEXP (adj_mem, 0)); 956 return; 957 } 958 959 default: 960 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); 961 } 962 963 case 'L': 964 /* Strip the MEM expression. */ 965 operand = XEXP (operand, 0); 966 break; 967 968 case 'e': 969 /* Like 'E', but ignore state set by 'x'. FIXME: Use code 970 iterators and attributes in cris.md to avoid the need for %x 971 and %E (and %e) and state passed between those modifiers. */ 972 cris_output_insn_is_bound = 0; 973 /* FALL THROUGH. */ 974 case 'E': 975 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless 976 cris_output_insn_is_bound is nonzero. */ 977 if (GET_CODE (operand) != SIGN_EXTEND 978 && GET_CODE (operand) != ZERO_EXTEND 979 && !CONST_INT_P (operand)) 980 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x); 981 982 if (cris_output_insn_is_bound) 983 { 984 cris_output_insn_is_bound = 0; 985 return; 986 } 987 988 putc (GET_CODE (operand) == SIGN_EXTEND 989 || (CONST_INT_P (operand) && INTVAL (operand) < 0) 990 ? 's' : 'u', file); 991 return; 992 993 case 'm': 994 /* Print the size letter of the inner element. We can do it by 995 calling ourselves with the 's' modifier. */ 996 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND) 997 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x); 998 cris_print_operand (file, XEXP (operand, 0), 's'); 999 return; 1000 1001 case 'M': 1002 /* Print the least significant part of operand. */ 1003 if (GET_CODE (operand) == CONST_DOUBLE) 1004 { 1005 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x)); 1006 return; 1007 } 1008 else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand)) 1009 { 1010 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 1011 INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1)); 1012 return; 1013 } 1014 /* Otherwise the least significant part equals the normal part, 1015 so handle it normally. */ 1016 break; 1017 1018 case 'A': 1019 /* When emitting an add for the high part of a DImode constant, we 1020 want to use addq for 0 and adds.w for -1. */ 1021 if (!CONST_INT_P (operand)) 1022 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x); 1023 fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq"); 1024 return; 1025 1026 case 'P': 1027 /* For const_int operands, print the additive mnemonic and the 1028 modified operand (byte-sized operands don't save anything): 1029 N=MIN_INT..-65536: add.d N 1030 -65535..-64: subu.w -N 1031 -63..-1: subq -N 1032 0..63: addq N 1033 64..65535: addu.w N 1034 65536..MAX_INT: add.d N. 1035 (Emitted mnemonics are capitalized to simplify testing.) 1036 For anything else (N.B: only register is valid), print "add.d". */ 1037 if (REG_P (operand)) 1038 { 1039 fprintf (file, "Add.d "); 1040 1041 /* Deal with printing the operand by dropping through to the 1042 normal path. */ 1043 break; 1044 } 1045 else 1046 { 1047 int val; 1048 gcc_assert (CONST_INT_P (operand)); 1049 1050 val = INTVAL (operand); 1051 if (!IN_RANGE (val, -65535, 65535)) 1052 fprintf (file, "Add.d %d", val); 1053 else if (val <= -64) 1054 fprintf (file, "Subu.w %d", -val); 1055 else if (val <= -1) 1056 fprintf (file, "Subq %d", -val); 1057 else if (val <= 63) 1058 fprintf (file, "Addq %d", val); 1059 else if (val <= 65535) 1060 fprintf (file, "Addu.w %d", val); 1061 return; 1062 } 1063 break; 1064 1065 case 'q': 1066 /* If the operand is an integer -31..31, print "q" else ".d". */ 1067 if (CONST_INT_P (operand) && IN_RANGE (INTVAL (operand), -31, 31)) 1068 fprintf (file, "q"); 1069 else 1070 fprintf (file, ".d"); 1071 return; 1072 1073 case 'd': 1074 /* If this is a GOT symbol, force it to be emitted as :GOT and 1075 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16). 1076 Avoid making this too much of a special case. */ 1077 if (flag_pic == 1 && CRIS_CONSTANT_P (operand)) 1078 { 1079 int flag_pic_save = flag_pic; 1080 1081 flag_pic = 2; 1082 cris_output_addr_const (file, operand); 1083 flag_pic = flag_pic_save; 1084 return; 1085 } 1086 break; 1087 1088 case 'D': 1089 /* When emitting an sub for the high part of a DImode constant, we 1090 want to use subq for 0 and subs.w for -1. */ 1091 if (!CONST_INT_P (operand)) 1092 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x); 1093 fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq"); 1094 return; 1095 1096 case 'S': 1097 /* Print the operand as the index-part of an address. 1098 Easiest way out is to use cris_print_index. */ 1099 cris_print_index (operand, file); 1100 return; 1101 1102 case 'T': 1103 /* Print the size letter for an operand to a MULT, which must be a 1104 const_int with a suitable value. */ 1105 if (!CONST_INT_P (operand) || INTVAL (operand) > 4) 1106 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x); 1107 fprintf (file, "%s", mults[INTVAL (operand)]); 1108 return; 1109 1110 case 'u': 1111 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */ 1112 if (flag_pic == 1 1113 && GET_CODE (operand) == CONST 1114 && GET_CODE (XEXP (operand, 0)) == UNSPEC 1115 && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD) 1116 fprintf (file, "u.w"); 1117 else 1118 fprintf (file, ".d"); 1119 return; 1120 1121 case 0: 1122 /* No code, print as usual. */ 1123 break; 1124 1125 default: 1126 LOSE_AND_RETURN ("invalid operand modifier letter", x); 1127 } 1128 1129 /* Print an operand as without a modifier letter. */ 1130 switch (GET_CODE (operand)) 1131 { 1132 case REG: 1133 if (REGNO (operand) > 15 1134 && REGNO (operand) != CRIS_MOF_REGNUM 1135 && REGNO (operand) != CRIS_SRP_REGNUM 1136 && REGNO (operand) != CRIS_CC0_REGNUM) 1137 internal_error ("internal error: bad register: %d", REGNO (operand)); 1138 fprintf (file, "$%s", reg_names[REGNO (operand)]); 1139 return; 1140 1141 case MEM: 1142 output_address (GET_MODE (operand), XEXP (operand, 0)); 1143 return; 1144 1145 case CONST_DOUBLE: 1146 if (GET_MODE (operand) == VOIDmode) 1147 /* A long long constant. */ 1148 output_addr_const (file, operand); 1149 else 1150 { 1151 /* Only single precision is allowed as plain operands the 1152 moment. */ 1153 long l; 1154 1155 /* FIXME: Perhaps check overflow of the "single". */ 1156 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operand), l); 1157 1158 fprintf (file, "0x%lx", l); 1159 } 1160 return; 1161 1162 case UNSPEC: 1163 /* Fall through. */ 1164 case CONST: 1165 cris_output_addr_const (file, operand); 1166 return; 1167 1168 case MULT: 1169 case ASHIFT: 1170 { 1171 /* For a (MULT (reg X) const_int) we output "rX.S". */ 1172 int i = CONST_INT_P (XEXP (operand, 1)) 1173 ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0)); 1174 rtx reg = CONST_INT_P (XEXP (operand, 1)) 1175 ? XEXP (operand, 0) : XEXP (operand, 1); 1176 1177 if (!REG_P (reg) 1178 || (!CONST_INT_P (XEXP (operand, 0)) 1179 && !CONST_INT_P (XEXP (operand, 1)))) 1180 LOSE_AND_RETURN ("unexpected multiplicative operand", x); 1181 1182 cris_print_base (reg, file); 1183 fprintf (file, ".%c", 1184 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b' 1185 : i == 4 ? 'd' 1186 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w' 1187 : 'd'); 1188 return; 1189 } 1190 1191 default: 1192 /* No need to handle all strange variants, let output_addr_const 1193 do it for us. */ 1194 if (CRIS_CONSTANT_P (operand)) 1195 { 1196 cris_output_addr_const (file, operand); 1197 return; 1198 } 1199 1200 LOSE_AND_RETURN ("unexpected operand", x); 1201 } 1202 } 1203 1204 static bool 1205 cris_print_operand_punct_valid_p (unsigned char code) 1206 { 1207 return (code == '#' || code == '!' || code == ':'); 1208 } 1209 1210 /* The PRINT_OPERAND_ADDRESS worker. */ 1211 1212 static void 1213 cris_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x) 1214 { 1215 /* All these were inside MEM:s so output indirection characters. */ 1216 putc ('[', file); 1217 1218 if (CONSTANT_ADDRESS_P (x)) 1219 cris_output_addr_const (file, x); 1220 else if (cris_base_or_autoincr_p (x, true)) 1221 cris_print_base (x, file); 1222 else if (GET_CODE (x) == PLUS) 1223 { 1224 rtx x1, x2; 1225 1226 x1 = XEXP (x, 0); 1227 x2 = XEXP (x, 1); 1228 if (cris_base_p (x1, true)) 1229 { 1230 cris_print_base (x1, file); 1231 cris_print_index (x2, file); 1232 } 1233 else if (cris_base_p (x2, true)) 1234 { 1235 cris_print_base (x2, file); 1236 cris_print_index (x1, file); 1237 } 1238 else 1239 LOSE_AND_RETURN ("unrecognized address", x); 1240 } 1241 else if (MEM_P (x)) 1242 { 1243 /* A DIP. Output more indirection characters. */ 1244 putc ('[', file); 1245 cris_print_base (XEXP (x, 0), file); 1246 putc (']', file); 1247 } 1248 else 1249 LOSE_AND_RETURN ("unrecognized address", x); 1250 1251 putc (']', file); 1252 } 1253 1254 /* The RETURN_ADDR_RTX worker. 1255 We mark that the return address is used, either by EH or 1256 __builtin_return_address, for use by the function prologue and 1257 epilogue. FIXME: This isn't optimal; we just use the mark in the 1258 prologue and epilogue to say that the return address is to be stored 1259 in the stack frame. We could return SRP for leaf-functions and use the 1260 initial-value machinery. */ 1261 1262 rtx 1263 cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED) 1264 { 1265 cfun->machine->needs_return_address_on_stack = 1; 1266 1267 /* The return-address is stored just above the saved frame-pointer (if 1268 present). Apparently we can't eliminate from the frame-pointer in 1269 that direction, so use the incoming args (maybe pretended) pointer. */ 1270 return count == 0 1271 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, virtual_incoming_args_rtx, -4)) 1272 : NULL_RTX; 1273 } 1274 1275 /* Accessor used in cris.md:return because cfun->machine isn't available 1276 there. */ 1277 1278 bool 1279 cris_return_address_on_stack (void) 1280 { 1281 return df_regs_ever_live_p (CRIS_SRP_REGNUM) 1282 || cfun->machine->needs_return_address_on_stack; 1283 } 1284 1285 /* Accessor used in cris.md:return because cfun->machine isn't available 1286 there. */ 1287 1288 bool 1289 cris_return_address_on_stack_for_return (void) 1290 { 1291 return cfun->machine->return_type == CRIS_RETINSN_RET ? false 1292 : cris_return_address_on_stack (); 1293 } 1294 1295 /* This handles FP -> SP elimination offset. */ 1296 1297 static int 1298 cris_initial_frame_pointer_offset (void) 1299 { 1300 int regno; 1301 1302 /* Initial offset is 0 if we don't have a frame pointer. */ 1303 int offs = 0; 1304 bool got_really_used = false; 1305 1306 if (crtl->uses_pic_offset_table) 1307 { 1308 push_topmost_sequence (); 1309 got_really_used 1310 = reg_used_between_p (pic_offset_table_rtx, get_insns (), 1311 NULL); 1312 pop_topmost_sequence (); 1313 } 1314 1315 /* And 4 for each register pushed. */ 1316 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 1317 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 1318 offs += 4; 1319 1320 /* And then, last, we add the locals allocated. */ 1321 offs += get_frame_size (); 1322 1323 /* And more; the accumulated args size. */ 1324 offs += crtl->outgoing_args_size; 1325 1326 /* Then round it off, in case we use aligned stack. */ 1327 if (TARGET_STACK_ALIGN) 1328 offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1; 1329 1330 return offs; 1331 } 1332 1333 /* The INITIAL_ELIMINATION_OFFSET worker. 1334 Calculate the difference between imaginary registers such as frame 1335 pointer and the stack pointer. Used to eliminate the frame pointer 1336 and imaginary arg pointer. */ 1337 1338 int 1339 cris_initial_elimination_offset (int fromreg, int toreg) 1340 { 1341 int fp_sp_offset 1342 = cris_initial_frame_pointer_offset (); 1343 1344 /* We should be able to use regs_ever_live and related prologue 1345 information here, or alpha should not as well. */ 1346 bool return_address_on_stack = cris_return_address_on_stack (); 1347 1348 /* Here we act as if the frame-pointer were needed. */ 1349 int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0); 1350 1351 if (fromreg == ARG_POINTER_REGNUM 1352 && toreg == FRAME_POINTER_REGNUM) 1353 return ap_fp_offset; 1354 1355 /* Between the frame pointer and the stack are only "normal" stack 1356 variables and saved registers. */ 1357 if (fromreg == FRAME_POINTER_REGNUM 1358 && toreg == STACK_POINTER_REGNUM) 1359 return fp_sp_offset; 1360 1361 /* We need to balance out the frame pointer here. */ 1362 if (fromreg == ARG_POINTER_REGNUM 1363 && toreg == STACK_POINTER_REGNUM) 1364 return ap_fp_offset + fp_sp_offset - 4; 1365 1366 gcc_unreachable (); 1367 } 1368 1369 /* Nonzero if X is a hard reg that can be used as an index. */ 1370 static inline bool 1371 reg_ok_for_base_p (const_rtx x, bool strict) 1372 { 1373 return ((! strict && ! HARD_REGISTER_P (x)) 1374 || REGNO_OK_FOR_BASE_P (REGNO (x))); 1375 } 1376 1377 /* Nonzero if X is a hard reg that can be used as an index. */ 1378 static inline bool 1379 reg_ok_for_index_p (const_rtx x, bool strict) 1380 { 1381 return reg_ok_for_base_p (x, strict); 1382 } 1383 1384 /* No symbol can be used as an index (or more correct, as a base) together 1385 with a register with PIC; the PIC register must be there. */ 1386 1387 bool 1388 cris_constant_index_p (const_rtx x) 1389 { 1390 return (CRIS_CONSTANT_P (x) && (!flag_pic || cris_valid_pic_const (x, true))); 1391 } 1392 1393 /* True if X is a valid base register. */ 1394 1395 bool 1396 cris_base_p (const_rtx x, bool strict) 1397 { 1398 return (REG_P (x) && reg_ok_for_base_p (x, strict)); 1399 } 1400 1401 /* True if X is a valid index register. */ 1402 1403 static inline bool 1404 cris_index_p (const_rtx x, bool strict) 1405 { 1406 return (REG_P (x) && reg_ok_for_index_p (x, strict)); 1407 } 1408 1409 /* True if X is a valid base register with or without autoincrement. */ 1410 1411 bool 1412 cris_base_or_autoincr_p (const_rtx x, bool strict) 1413 { 1414 return (cris_base_p (x, strict) 1415 || (GET_CODE (x) == POST_INC 1416 && cris_base_p (XEXP (x, 0), strict) 1417 && REGNO (XEXP (x, 0)) != CRIS_ACR_REGNUM)); 1418 } 1419 1420 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */ 1421 1422 bool 1423 cris_bdap_index_p (const_rtx x, bool strict) 1424 { 1425 return ((MEM_P (x) 1426 && GET_MODE (x) == SImode 1427 && cris_base_or_autoincr_p (XEXP (x, 0), strict)) 1428 || (GET_CODE (x) == SIGN_EXTEND 1429 && MEM_P (XEXP (x, 0)) 1430 && (GET_MODE (XEXP (x, 0)) == HImode 1431 || GET_MODE (XEXP (x, 0)) == QImode) 1432 && cris_base_or_autoincr_p (XEXP (XEXP (x, 0), 0), strict))); 1433 } 1434 1435 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */ 1436 1437 bool 1438 cris_biap_index_p (const_rtx x, bool strict) 1439 { 1440 return (cris_index_p (x, strict) 1441 || (GET_CODE (x) == MULT 1442 && cris_index_p (XEXP (x, 0), strict) 1443 && cris_scale_int_operand (XEXP (x, 1), VOIDmode))); 1444 } 1445 1446 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P. 1447 1448 A PIC operand looks like a normal symbol here. At output we dress it 1449 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local 1450 symbol) so we exclude all addressing modes where we can't replace a 1451 plain "symbol" with that. A global PIC symbol does not fit anywhere 1452 here (but is thankfully a general_operand in itself). A local PIC 1453 symbol is valid for the plain "symbol + offset" case. */ 1454 1455 bool 1456 cris_legitimate_address_p (machine_mode mode, rtx x, bool strict) 1457 { 1458 const_rtx x1, x2; 1459 1460 if (cris_base_or_autoincr_p (x, strict)) 1461 return true; 1462 else if (TARGET_V32) 1463 /* Nothing else is valid then. */ 1464 return false; 1465 else if (cris_constant_index_p (x)) 1466 return true; 1467 /* Indexed? */ 1468 else if (GET_CODE (x) == PLUS) 1469 { 1470 x1 = XEXP (x, 0); 1471 x2 = XEXP (x, 1); 1472 /* BDAP o, Rd. */ 1473 if ((cris_base_p (x1, strict) && cris_constant_index_p (x2)) 1474 || (cris_base_p (x2, strict) && cris_constant_index_p (x1)) 1475 /* BDAP Rs[+], Rd. */ 1476 || (GET_MODE_SIZE (mode) <= UNITS_PER_WORD 1477 && ((cris_base_p (x1, strict) 1478 && cris_bdap_index_p (x2, strict)) 1479 || (cris_base_p (x2, strict) 1480 && cris_bdap_index_p (x1, strict)) 1481 /* BIAP.m Rs, Rd */ 1482 || (cris_base_p (x1, strict) 1483 && cris_biap_index_p (x2, strict)) 1484 || (cris_base_p (x2, strict) 1485 && cris_biap_index_p (x1, strict))))) 1486 return true; 1487 } 1488 else if (MEM_P (x)) 1489 { 1490 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */ 1491 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD 1492 && cris_base_or_autoincr_p (XEXP (x, 0), strict)) 1493 return true; 1494 } 1495 1496 return false; 1497 } 1498 1499 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle 1500 PIC constants that aren't legitimized. FIXME: there used to be a 1501 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle 1502 PIC constants, but no more (4.7 era); testcase: glibc init-first.c. 1503 While that may be seen as a bug, that guarantee seems a wart by design, 1504 so don't bother; fix the documentation instead. */ 1505 1506 bool 1507 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 1508 { 1509 enum cris_symbol_type t; 1510 1511 if (flag_pic) 1512 return LEGITIMATE_PIC_OPERAND_P (x); 1513 1514 t = cris_symbol_type_of (x); 1515 1516 return 1517 t == cris_no_symbol 1518 || t == cris_offsettable_symbol 1519 || t == cris_unspec; 1520 } 1521 1522 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */ 1523 1524 bool 1525 cris_reload_address_legitimized (rtx x, 1526 machine_mode mode ATTRIBUTE_UNUSED, 1527 int opnum ATTRIBUTE_UNUSED, 1528 int itype, 1529 int ind_levels ATTRIBUTE_UNUSED) 1530 { 1531 enum reload_type type = (enum reload_type) itype; 1532 rtx op0, op1; 1533 rtx *op1p; 1534 1535 if (GET_CODE (x) != PLUS) 1536 return false; 1537 1538 if (TARGET_V32) 1539 return false; 1540 1541 op0 = XEXP (x, 0); 1542 op1 = XEXP (x, 1); 1543 op1p = &XEXP (x, 1); 1544 1545 if (!REG_P (op1)) 1546 return false; 1547 1548 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0))) 1549 { 1550 rtx op00 = XEXP (op0, 0); 1551 rtx op000 = XEXP (op00, 0); 1552 rtx *op000p = &XEXP (op00, 0); 1553 1554 if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode) 1555 && (REG_P (op000) 1556 || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0))))) 1557 { 1558 bool something_reloaded = false; 1559 1560 if (GET_CODE (op000) == POST_INC 1561 && REG_P (XEXP (op000, 0)) 1562 && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER) 1563 /* No, this gets too complicated and is too rare to care 1564 about trying to improve on the general code Here. 1565 As the return-value is an all-or-nothing indicator, we 1566 punt on the other register too. */ 1567 return false; 1568 1569 if ((REG_P (op000) 1570 && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER)) 1571 { 1572 /* The address of the inner mem is a pseudo or wrong 1573 reg: reload that. */ 1574 push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS, 1575 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 1576 something_reloaded = true; 1577 } 1578 1579 if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER) 1580 { 1581 /* Base register is a pseudo or wrong reg: reload it. */ 1582 push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS, 1583 GET_MODE (x), VOIDmode, 0, 0, 1584 opnum, type); 1585 something_reloaded = true; 1586 } 1587 1588 gcc_assert (something_reloaded); 1589 1590 return true; 1591 } 1592 } 1593 1594 return false; 1595 } 1596 1597 1598 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. 1599 1600 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as 1601 the class for a constant (testcase: __Mul in arit.c). To avoid forcing 1602 out a constant into the constant pool, we will trap this case and 1603 return something a bit more sane. FIXME: Check if this is a bug. 1604 Beware that we must not "override" classes that can be specified as 1605 constraint letters, or else asm operands using them will fail when 1606 they need to be reloaded. FIXME: Investigate whether that constitutes 1607 a bug. */ 1608 1609 static reg_class_t 1610 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) 1611 { 1612 if (rclass != ACR_REGS 1613 && rclass != MOF_REGS 1614 && rclass != MOF_SRP_REGS 1615 && rclass != SRP_REGS 1616 && rclass != CC0_REGS 1617 && rclass != SPECIAL_REGS) 1618 return GENNONACR_REGS; 1619 1620 return rclass; 1621 } 1622 1623 /* Worker function for TARGET_REGISTER_MOVE_COST. */ 1624 1625 static int 1626 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 1627 reg_class_t from, reg_class_t to) 1628 { 1629 /* Can't move to and from a SPECIAL_REGS register, so we have to say 1630 their move cost within that class is higher. How about 7? That's 3 1631 for a move to a GENERAL_REGS register, 3 for the move from the 1632 GENERAL_REGS register, and 1 for the increased register pressure. 1633 Also, it's higher than the memory move cost, as it should. 1634 We also do this for ALL_REGS, since we don't want that class to be 1635 preferred (even to memory) at all where GENERAL_REGS doesn't fit. 1636 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't 1637 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be 1638 used when a GENERAL_REGS should be used, even if there are call-saved 1639 GENERAL_REGS left to allocate. This is because the fall-back when 1640 the most preferred register class isn't available, isn't the next 1641 (or next good) wider register class, but the *most widest* register 1642 class. FIXME: pre-IRA comment, perhaps obsolete now. */ 1643 1644 if ((reg_classes_intersect_p (from, SPECIAL_REGS) 1645 && reg_classes_intersect_p (to, SPECIAL_REGS)) 1646 || from == ALL_REGS || to == ALL_REGS) 1647 return 7; 1648 1649 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we 1650 generally prefer GENERAL_REGS. */ 1651 if (reg_classes_intersect_p (from, SPECIAL_REGS) 1652 || reg_classes_intersect_p (to, SPECIAL_REGS)) 1653 return 3; 1654 1655 return 2; 1656 } 1657 1658 /* Worker function for TARGET_MEMORY_MOVE_COST. 1659 1660 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should 1661 suffice. */ 1662 1663 static int 1664 cris_memory_move_cost (machine_mode mode, 1665 reg_class_t rclass ATTRIBUTE_UNUSED, 1666 bool in ATTRIBUTE_UNUSED) 1667 { 1668 if (mode == QImode 1669 || mode == HImode) 1670 return 4; 1671 else 1672 return 6; 1673 } 1674 1675 /* Worker for cris_notice_update_cc; handles the "normal" cases. 1676 FIXME: this code is historical; its functionality should be 1677 refactored to look at insn attributes and moved to 1678 cris_notice_update_cc. Except, we better lose cc0 entirely. */ 1679 1680 static void 1681 cris_normal_notice_update_cc (rtx exp, rtx insn) 1682 { 1683 /* "Normal" means, for: 1684 (set (cc0) (...)): 1685 CC is (...). 1686 1687 (set (reg) (...)): 1688 CC is (reg) and (...) - unless (...) is 0 or reg is a special 1689 register or (v32 and (...) is -32..-1), then CC does not change. 1690 CC_NO_OVERFLOW unless (...) is reg or mem. 1691 1692 (set (mem) (...)): 1693 CC does not change. 1694 1695 (set (pc) (...)): 1696 CC does not change. 1697 1698 (parallel 1699 (set (reg1) (mem (bdap/biap))) 1700 (set (reg2) (bdap/biap))): 1701 CC is (reg1) and (mem (reg2)) 1702 1703 (parallel 1704 (set (mem (bdap/biap)) (reg1)) [or 0] 1705 (set (reg2) (bdap/biap))): 1706 CC does not change. 1707 1708 (where reg and mem includes strict_low_parts variants thereof) 1709 1710 For all others, assume CC is clobbered. 1711 Note that we do not have to care about setting CC_NO_OVERFLOW, 1712 since the overflow flag is set to 0 (i.e. right) for 1713 instructions where it does not have any sane sense, but where 1714 other flags have meanings. (This includes shifts; the carry is 1715 not set by them). 1716 1717 Note that there are other parallel constructs we could match, 1718 but we don't do that yet. */ 1719 1720 if (GET_CODE (exp) == SET) 1721 { 1722 /* FIXME: Check when this happens. It looks like we should 1723 actually do a CC_STATUS_INIT here to be safe. */ 1724 if (SET_DEST (exp) == pc_rtx) 1725 return; 1726 1727 /* Record CC0 changes, so we do not have to output multiple 1728 test insns. */ 1729 if (SET_DEST (exp) == cc0_rtx) 1730 { 1731 CC_STATUS_INIT; 1732 1733 if (GET_CODE (SET_SRC (exp)) == COMPARE 1734 && XEXP (SET_SRC (exp), 1) == const0_rtx) 1735 cc_status.value1 = XEXP (SET_SRC (exp), 0); 1736 else 1737 cc_status.value1 = SET_SRC (exp); 1738 1739 /* Handle flags for the special btstq on one bit. */ 1740 if (GET_CODE (cc_status.value1) == ZERO_EXTRACT 1741 && XEXP (cc_status.value1, 1) == const1_rtx) 1742 { 1743 if (CONST_INT_P (XEXP (cc_status.value1, 0))) 1744 /* Using cmpq. */ 1745 cc_status.flags = CC_INVERTED; 1746 else 1747 /* A one-bit btstq. */ 1748 cc_status.flags = CC_Z_IN_NOT_N; 1749 } 1750 1751 else if (GET_CODE (SET_SRC (exp)) == COMPARE) 1752 { 1753 if (!REG_P (XEXP (SET_SRC (exp), 0)) 1754 && XEXP (SET_SRC (exp), 1) != const0_rtx) 1755 /* For some reason gcc will not canonicalize compare 1756 operations, reversing the sign by itself if 1757 operands are in wrong order. */ 1758 /* (But NOT inverted; eq is still eq.) */ 1759 cc_status.flags = CC_REVERSED; 1760 1761 /* This seems to be overlooked by gcc. FIXME: Check again. 1762 FIXME: Is it really safe? */ 1763 cc_status.value2 1764 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)), 1765 XEXP (SET_SRC (exp), 0), 1766 XEXP (SET_SRC (exp), 1)); 1767 } 1768 return; 1769 } 1770 else if (REG_P (SET_DEST (exp)) 1771 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART 1772 && REG_P (XEXP (SET_DEST (exp), 0)))) 1773 { 1774 /* A register is set; normally CC is set to show that no 1775 test insn is needed. Catch the exceptions. */ 1776 1777 /* If not to cc0, then no "set"s in non-natural mode give 1778 ok cc0... */ 1779 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD 1780 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT) 1781 { 1782 /* ... except add:s and sub:s in DImode. */ 1783 if (GET_MODE (SET_DEST (exp)) == DImode 1784 && (GET_CODE (SET_SRC (exp)) == PLUS 1785 || GET_CODE (SET_SRC (exp)) == MINUS)) 1786 { 1787 CC_STATUS_INIT; 1788 cc_status.value1 = SET_DEST (exp); 1789 cc_status.value2 = SET_SRC (exp); 1790 1791 if (cris_reg_overlap_mentioned_p (cc_status.value1, 1792 cc_status.value2)) 1793 cc_status.value2 = 0; 1794 1795 /* Add and sub may set V, which gets us 1796 unoptimizable results in "gt" and "le" condition 1797 codes. */ 1798 cc_status.flags |= CC_NO_OVERFLOW; 1799 1800 return; 1801 } 1802 } 1803 else if (SET_SRC (exp) == const0_rtx 1804 || (REG_P (SET_SRC (exp)) 1805 && (REGNO (SET_SRC (exp)) 1806 > CRIS_LAST_GENERAL_REGISTER)) 1807 || (TARGET_V32 1808 && REG_P (SET_DEST (exp)) 1809 && satisfies_constraint_I (SET_SRC (exp)))) 1810 { 1811 /* There's no CC0 change for this case. Just check 1812 for overlap. */ 1813 if (cc_status.value1 1814 && modified_in_p (cc_status.value1, insn)) 1815 cc_status.value1 = 0; 1816 1817 if (cc_status.value2 1818 && modified_in_p (cc_status.value2, insn)) 1819 cc_status.value2 = 0; 1820 1821 return; 1822 } 1823 else 1824 { 1825 CC_STATUS_INIT; 1826 cc_status.value1 = SET_DEST (exp); 1827 cc_status.value2 = SET_SRC (exp); 1828 1829 if (cris_reg_overlap_mentioned_p (cc_status.value1, 1830 cc_status.value2)) 1831 cc_status.value2 = 0; 1832 1833 /* Some operations may set V, which gets us 1834 unoptimizable results in "gt" and "le" condition 1835 codes. */ 1836 if (GET_CODE (SET_SRC (exp)) == PLUS 1837 || GET_CODE (SET_SRC (exp)) == MINUS 1838 || GET_CODE (SET_SRC (exp)) == NEG) 1839 cc_status.flags |= CC_NO_OVERFLOW; 1840 1841 /* For V32, nothing with a register destination sets 1842 C and V usefully. */ 1843 if (TARGET_V32) 1844 cc_status.flags |= CC_NO_OVERFLOW; 1845 1846 return; 1847 } 1848 } 1849 else if (MEM_P (SET_DEST (exp)) 1850 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART 1851 && MEM_P (XEXP (SET_DEST (exp), 0)))) 1852 { 1853 /* When SET to MEM, then CC is not changed (except for 1854 overlap). */ 1855 if (cc_status.value1 1856 && modified_in_p (cc_status.value1, insn)) 1857 cc_status.value1 = 0; 1858 1859 if (cc_status.value2 1860 && modified_in_p (cc_status.value2, insn)) 1861 cc_status.value2 = 0; 1862 1863 return; 1864 } 1865 } 1866 else if (GET_CODE (exp) == PARALLEL) 1867 { 1868 if (GET_CODE (XVECEXP (exp, 0, 0)) == SET 1869 && GET_CODE (XVECEXP (exp, 0, 1)) == SET 1870 && REG_P (XEXP (XVECEXP (exp, 0, 1), 0))) 1871 { 1872 if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0)) 1873 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1))) 1874 { 1875 CC_STATUS_INIT; 1876 1877 /* For "move.S [rx=ry+o],rz", say CC reflects 1878 value1=rz and value2=[rx] */ 1879 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); 1880 cc_status.value2 1881 = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1), 1882 XEXP (XVECEXP (exp, 0, 1), 0)); 1883 1884 /* Huh? A side-effect cannot change the destination 1885 register. */ 1886 if (cris_reg_overlap_mentioned_p (cc_status.value1, 1887 cc_status.value2)) 1888 internal_error ("internal error: sideeffect-insn affecting main effect"); 1889 1890 /* For V32, moves to registers don't set C and V. */ 1891 if (TARGET_V32) 1892 cc_status.flags |= CC_NO_OVERFLOW; 1893 return; 1894 } 1895 else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1)) 1896 || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx) 1897 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0))) 1898 { 1899 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]", 1900 say flags are not changed, except for overlap. */ 1901 if (cc_status.value1 1902 && modified_in_p (cc_status.value1, insn)) 1903 cc_status.value1 = 0; 1904 1905 if (cc_status.value2 1906 && modified_in_p (cc_status.value2, insn)) 1907 cc_status.value2 = 0; 1908 1909 return; 1910 } 1911 } 1912 } 1913 1914 /* If we got here, the case wasn't covered by the code above. */ 1915 CC_STATUS_INIT; 1916 } 1917 1918 /* This function looks into the pattern to see how this insn affects 1919 condition codes. 1920 1921 Used when to eliminate test insns before a condition-code user, 1922 such as a "scc" insn or a conditional branch. This includes 1923 checking if the entities that cc was updated by, are changed by the 1924 operation. 1925 1926 Currently a jumble of the old peek-inside-the-insn and the newer 1927 check-cc-attribute methods. */ 1928 1929 void 1930 cris_notice_update_cc (rtx exp, rtx_insn *insn) 1931 { 1932 enum attr_cc attrval = get_attr_cc (insn); 1933 1934 /* Check if user specified "-mcc-init" as a bug-workaround. Remember 1935 to still set CC_REVERSED as below, since that's required by some 1936 compare insn alternatives. (FIXME: GCC should do this virtual 1937 operand swap by itself.) A test-case that may otherwise fail is 1938 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */ 1939 if (TARGET_CCINIT) 1940 { 1941 CC_STATUS_INIT; 1942 1943 if (attrval == CC_REV) 1944 cc_status.flags = CC_REVERSED; 1945 return; 1946 } 1947 1948 /* Slowly, we're converting to using attributes to control the setting 1949 of condition-code status. */ 1950 switch (attrval) 1951 { 1952 case CC_NONE: 1953 /* Even if it is "none", a setting may clobber a previous 1954 cc-value, so check. */ 1955 if (GET_CODE (exp) == SET) 1956 { 1957 if (cc_status.value1 1958 && modified_in_p (cc_status.value1, insn)) 1959 cc_status.value1 = 0; 1960 1961 if (cc_status.value2 1962 && modified_in_p (cc_status.value2, insn)) 1963 cc_status.value2 = 0; 1964 } 1965 return; 1966 1967 case CC_CLOBBER: 1968 CC_STATUS_INIT; 1969 return; 1970 1971 case CC_REV: 1972 case CC_NOOV32: 1973 case CC_NORMAL: 1974 cris_normal_notice_update_cc (exp, insn); 1975 1976 /* The "test" insn doesn't clear (carry and) overflow on V32. We 1977 can change bge => bpl and blt => bmi by passing on to the cc0 1978 user that V should not be considered; bgt and ble are taken 1979 care of by other methods (see {tst,cmp}{si,hi,qi}). */ 1980 if (attrval == CC_NOOV32 && TARGET_V32) 1981 cc_status.flags |= CC_NO_OVERFLOW; 1982 return; 1983 1984 default: 1985 internal_error ("unknown cc_attr value"); 1986 } 1987 1988 CC_STATUS_INIT; 1989 } 1990 1991 /* Return != 0 if the return sequence for the current function is short, 1992 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if 1993 registers must be saved, so return 0 then. */ 1994 1995 bool 1996 cris_simple_epilogue (void) 1997 { 1998 unsigned int regno; 1999 unsigned int reglimit = STACK_POINTER_REGNUM; 2000 bool got_really_used = false; 2001 2002 if (! reload_completed 2003 || frame_pointer_needed 2004 || get_frame_size () != 0 2005 || crtl->args.pretend_args_size 2006 || crtl->args.size 2007 || crtl->outgoing_args_size 2008 || crtl->calls_eh_return 2009 2010 /* If we're not supposed to emit prologue and epilogue, we must 2011 not emit return-type instructions. */ 2012 || !TARGET_PROLOGUE_EPILOGUE) 2013 return false; 2014 2015 /* Can't return from stacked return address with v32. */ 2016 if (TARGET_V32 && cris_return_address_on_stack ()) 2017 return false; 2018 2019 if (crtl->uses_pic_offset_table) 2020 { 2021 push_topmost_sequence (); 2022 got_really_used 2023 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); 2024 pop_topmost_sequence (); 2025 } 2026 2027 /* No simple epilogue if there are saved registers. */ 2028 for (regno = 0; regno < reglimit; regno++) 2029 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 2030 return false; 2031 2032 return true; 2033 } 2034 2035 /* Emit checking that MEM is aligned for an access in MODE, failing 2036 that, executing a "break 8" (or call to abort, if "break 8" is 2037 disabled). */ 2038 2039 void 2040 cris_emit_trap_for_misalignment (rtx mem) 2041 { 2042 rtx addr, reg, ok_label, andop; 2043 rtx_insn *jmp; 2044 int natural_alignment; 2045 gcc_assert (MEM_P (mem)); 2046 2047 natural_alignment = GET_MODE_SIZE (GET_MODE (mem)); 2048 addr = XEXP (mem, 0); 2049 reg = force_reg (Pmode, addr); 2050 ok_label = gen_label_rtx (); 2051 2052 /* This will yield a btstq without a separate register used, usually - 2053 with the exception for PRE hoisting the "and" but not the branch 2054 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */ 2055 andop = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1)); 2056 emit_cmp_and_jump_insns (force_reg (SImode, andop), const0_rtx, EQ, 2057 NULL_RTX, Pmode, 1, ok_label); 2058 jmp = get_last_insn (); 2059 gcc_assert (JUMP_P (jmp)); 2060 2061 predict_insn_def (jmp, PRED_NORETURN, TAKEN); 2062 expand_builtin_trap (); 2063 emit_label (ok_label); 2064 } 2065 2066 /* Expand a return insn (just one insn) marked as using SRP or stack 2067 slot depending on parameter ON_STACK. */ 2068 2069 void 2070 cris_expand_return (bool on_stack) 2071 { 2072 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to 2073 tell "ret" from "jump [sp+]". Some, but not all, other parts of 2074 GCC expect just (return) to do the right thing when optimizing, so 2075 we do that until they're fixed. Currently, all return insns in a 2076 function must be the same (not really a limiting factor) so we need 2077 to check that it doesn't change half-way through. */ 2078 emit_jump_insn (ret_rtx); 2079 2080 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack); 2081 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack); 2082 2083 cfun->machine->return_type 2084 = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET; 2085 } 2086 2087 /* Compute a (partial) cost for rtx X. Return true if the complete 2088 cost has been computed, and false if subexpressions should be 2089 scanned. In either case, *TOTAL contains the cost result. */ 2090 2091 static bool 2092 cris_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, 2093 int *total, bool speed) 2094 { 2095 int code = GET_CODE (x); 2096 2097 switch (code) 2098 { 2099 case CONST_INT: 2100 { 2101 HOST_WIDE_INT val = INTVAL (x); 2102 if (val == 0) 2103 *total = 0; 2104 else if (val < 32 && val >= -32) 2105 *total = 1; 2106 /* Eight or 16 bits are a word and cycle more expensive. */ 2107 else if (val <= 32767 && val >= -32768) 2108 *total = 2; 2109 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs 2110 another word. FIXME: This isn't linear to 16 bits. */ 2111 else 2112 *total = 4; 2113 return true; 2114 } 2115 2116 case LABEL_REF: 2117 *total = 6; 2118 return true; 2119 2120 case CONST: 2121 case SYMBOL_REF: 2122 *total = 6; 2123 return true; 2124 2125 case CONST_DOUBLE: 2126 if (x != CONST0_RTX (mode == VOIDmode ? DImode : mode)) 2127 *total = 12; 2128 else 2129 /* Make 0.0 cheap, else test-insns will not be used. */ 2130 *total = 0; 2131 return true; 2132 2133 case MULT: 2134 /* If we have one arm of an ADDI, make sure it gets the cost of 2135 one insn, i.e. zero cost for this operand, and just the cost 2136 of the PLUS, as the insn is created by combine from a PLUS 2137 and an ASHIFT, and the MULT cost below would make the 2138 combined value be larger than the separate insns. The insn 2139 validity is checked elsewhere by combine. 2140 2141 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole 2142 function should be rewritten. */ 2143 if (outer_code == PLUS && cris_biap_index_p (x, false)) 2144 { 2145 *total = 0; 2146 return true; 2147 } 2148 2149 /* Identify values that are no powers of two. Powers of 2 are 2150 taken care of already and those values should not be changed. */ 2151 if (!CONST_INT_P (XEXP (x, 1)) 2152 || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) 2153 { 2154 /* If we have a multiply insn, then the cost is between 2155 1 and 2 "fast" instructions. */ 2156 if (TARGET_HAS_MUL_INSNS) 2157 { 2158 *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2; 2159 return true; 2160 } 2161 2162 /* Estimate as 4 + 4 * #ofbits. */ 2163 *total = COSTS_N_INSNS (132); 2164 return true; 2165 } 2166 return false; 2167 2168 case UDIV: 2169 case MOD: 2170 case UMOD: 2171 case DIV: 2172 if (!CONST_INT_P (XEXP (x, 1)) 2173 || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) 2174 { 2175 /* Estimate this as 4 + 8 * #of bits. */ 2176 *total = COSTS_N_INSNS (260); 2177 return true; 2178 } 2179 return false; 2180 2181 case AND: 2182 if (CONST_INT_P (XEXP (x, 1)) 2183 /* Two constants may actually happen before optimization. */ 2184 && !CONST_INT_P (XEXP (x, 0)) 2185 && !satisfies_constraint_I (XEXP (x, 1))) 2186 { 2187 *total 2188 = (rtx_cost (XEXP (x, 0), mode, (enum rtx_code) outer_code, 2189 opno, speed) + 2 2190 + 2 * GET_MODE_NUNITS (mode)); 2191 return true; 2192 } 2193 return false; 2194 2195 case ZERO_EXTRACT: 2196 if (outer_code != COMPARE) 2197 return false; 2198 /* fall through */ 2199 2200 case ZERO_EXTEND: case SIGN_EXTEND: 2201 *total = rtx_cost (XEXP (x, 0), VOIDmode, (enum rtx_code) outer_code, 2202 opno, speed); 2203 return true; 2204 2205 default: 2206 return false; 2207 } 2208 } 2209 2210 /* The ADDRESS_COST worker. */ 2211 2212 static int 2213 cris_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED, 2214 addr_space_t as ATTRIBUTE_UNUSED, 2215 bool speed ATTRIBUTE_UNUSED) 2216 { 2217 /* The metric to use for the cost-macros is unclear. 2218 The metric used here is (the number of cycles needed) / 2, 2219 where we consider equal a cycle for a word of code and a cycle to 2220 read memory. FIXME: Adding "+ 1" to all values would avoid 2221 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes" 2222 0 to 1, thereby giving equal costs to [rN + rM] and [rN]. 2223 Unfortunately(?) such a hack would expose other pessimizations, 2224 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the 2225 loop there, without apparent reason. */ 2226 2227 /* The cheapest addressing modes get 0, since nothing extra is needed. */ 2228 if (cris_base_or_autoincr_p (x, false)) 2229 return 0; 2230 2231 /* An indirect mem must be a DIP. This means two bytes extra for code, 2232 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */ 2233 if (MEM_P (x)) 2234 return (2 + 4) / 2; 2235 2236 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs 2237 an extra DIP prefix and 4 bytes of constant in most cases. */ 2238 if (CONSTANT_P (x)) 2239 return (2 + 4) / 2; 2240 2241 /* Handle BIAP and BDAP prefixes. */ 2242 if (GET_CODE (x) == PLUS) 2243 { 2244 rtx tem1 = XEXP (x, 0); 2245 rtx tem2 = XEXP (x, 1); 2246 2247 /* Local extended canonicalization rule: the first operand must 2248 be REG, unless it's an operation (MULT). */ 2249 if (!REG_P (tem1) && GET_CODE (tem1) != MULT) 2250 tem1 = tem2, tem2 = XEXP (x, 0); 2251 2252 /* We'll "assume" we have canonical RTX now. */ 2253 gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT); 2254 2255 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We 2256 recognize the typical MULT which is always in tem1 because of 2257 insn canonicalization. */ 2258 if ((GET_CODE (tem1) == MULT && cris_biap_index_p (tem1, false)) 2259 || REG_P (tem2)) 2260 return 2 / 2; 2261 2262 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the 2263 PLUS is always found in tem2. */ 2264 if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128) 2265 return 2 / 2; 2266 2267 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra 2268 bytes. */ 2269 if (satisfies_constraint_L (tem2)) 2270 return (2 + 2) / 2; 2271 2272 /* A BDAP with some other constant is 2 bytes extra. */ 2273 if (CRIS_CONSTANT_P (tem2)) 2274 return (2 + 2 + 2) / 2; 2275 2276 /* BDAP with something indirect should have a higher cost than 2277 BIAP with register. FIXME: Should it cost like a MEM or more? */ 2278 return (2 + 2 + 2) / 2; 2279 } 2280 2281 /* What else? Return a high cost. It matters only for valid 2282 addressing modes. */ 2283 return 10; 2284 } 2285 2286 /* Check various objections to the side-effect. Used in the test-part 2287 of an anonymous insn describing an insn with a possible side-effect. 2288 Returns nonzero if the implied side-effect is ok. 2289 2290 code : PLUS or MULT 2291 ops : An array of rtx:es. lreg, rreg, rval, 2292 The variables multop and other_op are indexes into this, 2293 or -1 if they are not applicable. 2294 lreg : The register that gets assigned in the side-effect. 2295 rreg : One register in the side-effect expression 2296 rval : The other register, or an int. 2297 multop : An integer to multiply rval with. 2298 other_op : One of the entities of the main effect, 2299 whose mode we must consider. */ 2300 2301 int 2302 cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, 2303 int lreg, int rreg, int rval, 2304 int multop, int other_op) 2305 { 2306 /* Find what value to multiply with, for rx =ry + rz * n. */ 2307 int mult = multop < 0 ? 1 : INTVAL (ops[multop]); 2308 2309 rtx reg_rtx = ops[rreg]; 2310 rtx val_rtx = ops[rval]; 2311 2312 /* The operands may be swapped. Canonicalize them in reg_rtx and 2313 val_rtx, where reg_rtx always is a reg (for this constraint to 2314 match). */ 2315 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) 2316 reg_rtx = val_rtx, val_rtx = ops[rreg]; 2317 2318 /* Don't forget to check that reg_rtx really is a reg. If it isn't, 2319 we have no business. */ 2320 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) 2321 return 0; 2322 2323 /* Don't do this when -mno-split. */ 2324 if (!TARGET_SIDE_EFFECT_PREFIXES) 2325 return 0; 2326 2327 /* The mult expression may be hidden in lreg. FIXME: Add more 2328 commentary about that. */ 2329 if (GET_CODE (val_rtx) == MULT) 2330 { 2331 mult = INTVAL (XEXP (val_rtx, 1)); 2332 val_rtx = XEXP (val_rtx, 0); 2333 code = MULT; 2334 } 2335 2336 /* First check the "other operand". */ 2337 if (other_op >= 0) 2338 { 2339 if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD) 2340 return 0; 2341 2342 /* Check if the lvalue register is the same as the "other 2343 operand". If so, the result is undefined and we shouldn't do 2344 this. FIXME: Check again. */ 2345 if ((cris_base_p (ops[lreg], reload_in_progress || reload_completed) 2346 && cris_base_p (ops[other_op], 2347 reload_in_progress || reload_completed) 2348 && REGNO (ops[lreg]) == REGNO (ops[other_op])) 2349 || rtx_equal_p (ops[other_op], ops[lreg])) 2350 return 0; 2351 } 2352 2353 /* Do not accept frame_pointer_rtx as any operand. */ 2354 if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx 2355 || ops[rval] == frame_pointer_rtx 2356 || (other_op >= 0 && ops[other_op] == frame_pointer_rtx)) 2357 return 0; 2358 2359 if (code == PLUS 2360 && ! cris_base_p (val_rtx, reload_in_progress || reload_completed)) 2361 { 2362 2363 /* Do not allow rx = rx + n if a normal add or sub with same size 2364 would do. */ 2365 if (rtx_equal_p (ops[lreg], reg_rtx) 2366 && CONST_INT_P (val_rtx) 2367 && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63)) 2368 return 0; 2369 2370 /* Check allowed cases, like [r(+)?].[bwd] and const. */ 2371 if (CRIS_CONSTANT_P (val_rtx)) 2372 return 1; 2373 2374 if (MEM_P (val_rtx) 2375 && cris_base_or_autoincr_p (XEXP (val_rtx, 0), 2376 reload_in_progress || reload_completed)) 2377 return 1; 2378 2379 if (GET_CODE (val_rtx) == SIGN_EXTEND 2380 && MEM_P (XEXP (val_rtx, 0)) 2381 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx, 0), 0), 2382 reload_in_progress || reload_completed)) 2383 return 1; 2384 2385 /* If we got here, it's not a valid addressing mode. */ 2386 return 0; 2387 } 2388 else if (code == MULT 2389 || (code == PLUS 2390 && cris_base_p (val_rtx, 2391 reload_in_progress || reload_completed))) 2392 { 2393 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */ 2394 if (rtx_equal_p (ops[lreg], reg_rtx) 2395 || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx))) 2396 return 0; 2397 2398 /* Do not allow bad multiply-values. */ 2399 if (mult != 1 && mult != 2 && mult != 4) 2400 return 0; 2401 2402 /* Only allow r + ... */ 2403 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) 2404 return 0; 2405 2406 /* If we got here, all seems ok. 2407 (All checks need to be done above). */ 2408 return 1; 2409 } 2410 2411 /* If we get here, the caller got its initial tests wrong. */ 2412 internal_error ("internal error: cris_side_effect_mode_ok with bad operands"); 2413 } 2414 2415 /* Whether next_cc0_user of insn is LE or GT or requires a real compare 2416 insn for other reasons. */ 2417 2418 bool 2419 cris_cc0_user_requires_cmp (rtx_insn *insn) 2420 { 2421 rtx_insn *cc0_user = NULL; 2422 rtx body; 2423 rtx set; 2424 2425 gcc_assert (insn != NULL); 2426 2427 if (!TARGET_V32) 2428 return false; 2429 2430 cc0_user = next_cc0_user (insn); 2431 if (cc0_user == NULL) 2432 return false; 2433 2434 body = PATTERN (cc0_user); 2435 set = single_set (cc0_user); 2436 2437 /* Users can be sCC and bCC. */ 2438 if (JUMP_P (cc0_user) 2439 && GET_CODE (body) == SET 2440 && SET_DEST (body) == pc_rtx 2441 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE 2442 && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx) 2443 { 2444 return 2445 GET_CODE (XEXP (SET_SRC (body), 0)) == GT 2446 || GET_CODE (XEXP (SET_SRC (body), 0)) == LE; 2447 } 2448 else if (set) 2449 { 2450 return 2451 GET_CODE (SET_SRC (body)) == GT 2452 || GET_CODE (SET_SRC (body)) == LE; 2453 } 2454 2455 gcc_unreachable (); 2456 } 2457 2458 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16) 2459 does not handle the case where the IN operand is strict_low_part; it 2460 does handle it for X. Test-case in Axis-20010516. This function takes 2461 care of that for THIS port. FIXME: strict_low_part is going away 2462 anyway. */ 2463 2464 static int 2465 cris_reg_overlap_mentioned_p (rtx x, rtx in) 2466 { 2467 /* The function reg_overlap_mentioned now handles when X is 2468 strict_low_part, but not when IN is a STRICT_LOW_PART. */ 2469 if (GET_CODE (in) == STRICT_LOW_PART) 2470 in = XEXP (in, 0); 2471 2472 return reg_overlap_mentioned_p (x, in); 2473 } 2474 2475 /* Return TRUE iff X is a CONST valid for e.g. indexing. 2476 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1 2477 elsewhere. */ 2478 2479 bool 2480 cris_valid_pic_const (const_rtx x, bool any_operand) 2481 { 2482 gcc_assert (flag_pic); 2483 2484 switch (GET_CODE (x)) 2485 { 2486 case CONST_INT: 2487 case CONST_DOUBLE: 2488 return true; 2489 default: 2490 ; 2491 } 2492 2493 if (GET_CODE (x) != CONST) 2494 return false; 2495 2496 x = XEXP (x, 0); 2497 2498 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */ 2499 if (GET_CODE (x) == PLUS 2500 && GET_CODE (XEXP (x, 0)) == UNSPEC 2501 && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL 2502 || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL) 2503 && CONST_INT_P (XEXP (x, 1))) 2504 x = XEXP (x, 0); 2505 2506 if (GET_CODE (x) == UNSPEC) 2507 switch (XINT (x, 1)) 2508 { 2509 /* A PCREL operand is only valid for call and movsi. */ 2510 case CRIS_UNSPEC_PLT_PCREL: 2511 case CRIS_UNSPEC_PCREL: 2512 return !any_operand; 2513 2514 case CRIS_UNSPEC_PLT_GOTREL: 2515 case CRIS_UNSPEC_PLTGOTREAD: 2516 case CRIS_UNSPEC_GOTREAD: 2517 case CRIS_UNSPEC_GOTREL: 2518 return true; 2519 default: 2520 gcc_unreachable (); 2521 } 2522 2523 return cris_symbol_type_of (x) == cris_no_symbol; 2524 } 2525 2526 /* Helper function to find the right symbol-type to generate, 2527 given the original (non-PIC) representation. */ 2528 2529 enum cris_symbol_type 2530 cris_symbol_type_of (const_rtx x) 2531 { 2532 switch (GET_CODE (x)) 2533 { 2534 case SYMBOL_REF: 2535 return flag_pic 2536 ? (SYMBOL_REF_LOCAL_P (x) 2537 ? cris_rel_symbol : cris_got_symbol) 2538 : cris_offsettable_symbol; 2539 2540 case LABEL_REF: 2541 return flag_pic ? cris_rel_symbol : cris_offsettable_symbol; 2542 2543 case CONST: 2544 return cris_symbol_type_of (XEXP (x, 0)); 2545 2546 case PLUS: 2547 case MINUS: 2548 { 2549 enum cris_symbol_type t1 = cris_symbol_type_of (XEXP (x, 0)); 2550 enum cris_symbol_type t2 = cris_symbol_type_of (XEXP (x, 1)); 2551 2552 gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol); 2553 2554 if (t1 == cris_got_symbol || t2 == cris_got_symbol) 2555 return cris_got_symbol_needing_fixup; 2556 2557 return t1 != cris_no_symbol ? t1 : t2; 2558 } 2559 2560 case CONST_INT: 2561 case CONST_DOUBLE: 2562 return cris_no_symbol; 2563 2564 case UNSPEC: 2565 return cris_unspec; 2566 2567 default: 2568 fatal_insn ("unrecognized supposed constant", x); 2569 } 2570 2571 gcc_unreachable (); 2572 } 2573 2574 /* The LEGITIMATE_PIC_OPERAND_P worker. */ 2575 2576 int 2577 cris_legitimate_pic_operand (rtx x) 2578 { 2579 /* Symbols are not valid PIC operands as-is; just constants. */ 2580 return cris_valid_pic_const (x, true); 2581 } 2582 2583 /* Queue an .ident string in the queue of top-level asm statements. 2584 If the front-end is done, we must be being called from toplev.c. 2585 In that case, do nothing. */ 2586 void 2587 cris_asm_output_ident (const char *string) 2588 { 2589 if (symtab->state != PARSING) 2590 return; 2591 2592 default_asm_output_ident_directive (string); 2593 } 2594 2595 /* The ASM_OUTPUT_CASE_END worker. */ 2596 2597 void 2598 cris_asm_output_case_end (FILE *stream, int num, rtx_insn *table) 2599 { 2600 /* Step back, over the label for the table, to the actual casejump and 2601 assert that we find only what's expected. */ 2602 rtx_insn *whole_jump_insn = prev_nonnote_nondebug_insn (table); 2603 gcc_assert (whole_jump_insn != NULL_RTX && LABEL_P (whole_jump_insn)); 2604 whole_jump_insn = prev_nonnote_nondebug_insn (whole_jump_insn); 2605 gcc_assert (whole_jump_insn != NULL_RTX 2606 && (JUMP_P (whole_jump_insn) 2607 || (TARGET_V32 && INSN_P (whole_jump_insn) 2608 && GET_CODE (PATTERN (whole_jump_insn)) == SEQUENCE))); 2609 /* Get the pattern of the casejump, so we can extract the default label. */ 2610 rtx whole_jump_pat = PATTERN (whole_jump_insn); 2611 2612 if (TARGET_V32) 2613 { 2614 /* This can be a SEQUENCE, meaning the delay-slot of the jump is 2615 filled. We also output the offset word a little differently. */ 2616 rtx parallel_jump 2617 = (GET_CODE (whole_jump_pat) == SEQUENCE 2618 ? PATTERN (XVECEXP (whole_jump_pat, 0, 0)) : whole_jump_pat); 2619 2620 asm_fprintf (stream, 2621 "\t.word %LL%d-.%s\n", 2622 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP 2623 (parallel_jump, 0, 0), 2624 1), 2), 0)), 2625 (TARGET_PDEBUG ? "; default" : "")); 2626 return; 2627 } 2628 2629 asm_fprintf (stream, 2630 "\t.word %LL%d-%LL%d%s\n", 2631 CODE_LABEL_NUMBER (XEXP 2632 (XEXP 2633 (XEXP (XVECEXP (whole_jump_pat, 0, 0), 1), 2634 2), 0)), 2635 num, 2636 (TARGET_PDEBUG ? "; default" : "")); 2637 } 2638 2639 /* The TARGET_OPTION_OVERRIDE worker. 2640 As is the norm, this also parses -mfoo=bar type parameters. */ 2641 2642 static void 2643 cris_option_override (void) 2644 { 2645 if (cris_max_stackframe_str) 2646 { 2647 cris_max_stackframe = atoi (cris_max_stackframe_str); 2648 2649 /* Do some sanity checking. */ 2650 if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000) 2651 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d", 2652 cris_max_stackframe, 0x20000000); 2653 } 2654 2655 /* Let "-metrax4" and "-metrax100" change the cpu version. */ 2656 if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO) 2657 cris_cpu_version = CRIS_CPU_SVINTO; 2658 else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4) 2659 cris_cpu_version = CRIS_CPU_ETRAX4; 2660 2661 /* Parse -march=... and its synonym, the deprecated -mcpu=... */ 2662 if (cris_cpu_str) 2663 { 2664 cris_cpu_version 2665 = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1); 2666 2667 if (strcmp ("etrax4", cris_cpu_str) == 0) 2668 cris_cpu_version = 3; 2669 2670 if (strcmp ("svinto", cris_cpu_str) == 0 2671 || strcmp ("etrax100", cris_cpu_str) == 0) 2672 cris_cpu_version = 8; 2673 2674 if (strcmp ("ng", cris_cpu_str) == 0 2675 || strcmp ("etrax100lx", cris_cpu_str) == 0) 2676 cris_cpu_version = 10; 2677 2678 if (cris_cpu_version < 0 || cris_cpu_version > 32) 2679 error ("unknown CRIS version specification in -march= or -mcpu= : %s", 2680 cris_cpu_str); 2681 2682 /* Set the target flags. */ 2683 if (cris_cpu_version >= CRIS_CPU_ETRAX4) 2684 target_flags |= MASK_ETRAX4_ADD; 2685 2686 /* If this is Svinto or higher, align for 32 bit accesses. */ 2687 if (cris_cpu_version >= CRIS_CPU_SVINTO) 2688 target_flags 2689 |= (MASK_SVINTO | MASK_ALIGN_BY_32 2690 | MASK_STACK_ALIGN | MASK_CONST_ALIGN 2691 | MASK_DATA_ALIGN); 2692 2693 /* Note that we do not add new flags when it can be completely 2694 described with a macro that uses -mcpu=X. So 2695 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */ 2696 } 2697 2698 if (cris_tune_str) 2699 { 2700 int cris_tune 2701 = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1); 2702 2703 if (strcmp ("etrax4", cris_tune_str) == 0) 2704 cris_tune = 3; 2705 2706 if (strcmp ("svinto", cris_tune_str) == 0 2707 || strcmp ("etrax100", cris_tune_str) == 0) 2708 cris_tune = 8; 2709 2710 if (strcmp ("ng", cris_tune_str) == 0 2711 || strcmp ("etrax100lx", cris_tune_str) == 0) 2712 cris_tune = 10; 2713 2714 if (cris_tune < 0 || cris_tune > 32) 2715 error ("unknown CRIS cpu version specification in -mtune= : %s", 2716 cris_tune_str); 2717 2718 if (cris_tune >= CRIS_CPU_SVINTO) 2719 /* We have currently nothing more to tune than alignment for 2720 memory accesses. */ 2721 target_flags 2722 |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN 2723 | MASK_DATA_ALIGN | MASK_ALIGN_BY_32); 2724 } 2725 2726 if (cris_cpu_version >= CRIS_CPU_V32) 2727 target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG); 2728 2729 if (flag_pic) 2730 { 2731 /* Use error rather than warning, so invalid use is easily 2732 detectable. Still change to the values we expect, to avoid 2733 further errors. */ 2734 if (! TARGET_LINUX) 2735 { 2736 error ("-fPIC and -fpic are not supported in this configuration"); 2737 flag_pic = 0; 2738 } 2739 2740 /* Turn off function CSE. We need to have the addresses reach the 2741 call expanders to get PLT-marked, as they could otherwise be 2742 compared against zero directly or indirectly. After visiting the 2743 call expanders they will then be cse:ed, as the call expanders 2744 force_reg the addresses, effectively forcing flag_no_function_cse 2745 to 0. */ 2746 flag_no_function_cse = 1; 2747 } 2748 2749 /* Set the per-function-data initializer. */ 2750 init_machine_status = cris_init_machine_status; 2751 } 2752 2753 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */ 2754 2755 static void 2756 cris_asm_output_mi_thunk (FILE *stream, 2757 tree thunkdecl ATTRIBUTE_UNUSED, 2758 HOST_WIDE_INT delta, 2759 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, 2760 tree funcdecl) 2761 { 2762 /* Make sure unwind info is emitted for the thunk if needed. */ 2763 final_start_function (emit_barrier (), stream, 1); 2764 2765 if (delta > 0) 2766 fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", 2767 ADDITIVE_SIZE_MODIFIER (delta), delta, 2768 reg_names[CRIS_FIRST_ARG_REG]); 2769 else if (delta < 0) 2770 fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", 2771 ADDITIVE_SIZE_MODIFIER (-delta), -delta, 2772 reg_names[CRIS_FIRST_ARG_REG]); 2773 2774 if (flag_pic) 2775 { 2776 const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0); 2777 2778 name = (* targetm.strip_name_encoding) (name); 2779 2780 if (TARGET_V32) 2781 { 2782 fprintf (stream, "\tba "); 2783 assemble_name (stream, name); 2784 fprintf (stream, "%s\n\tnop\n", CRIS_PLT_PCOFFSET_SUFFIX); 2785 } 2786 else 2787 { 2788 fprintf (stream, "\tadd.d "); 2789 assemble_name (stream, name); 2790 fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX); 2791 } 2792 } 2793 else 2794 { 2795 fprintf (stream, "\tjump "); 2796 assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0)); 2797 fprintf (stream, "\n"); 2798 2799 if (TARGET_V32) 2800 fprintf (stream, "\tnop\n"); 2801 } 2802 2803 final_end_function (); 2804 } 2805 2806 /* Boilerplate emitted at start of file. 2807 2808 NO_APP *only at file start* means faster assembly. It also means 2809 comments are not allowed. In some cases comments will be output 2810 for debugging purposes. Make sure they are allowed then. */ 2811 static void 2812 cris_file_start (void) 2813 { 2814 /* These expressions can vary at run time, so we cannot put 2815 them into TARGET_INITIALIZER. */ 2816 targetm.asm_file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name); 2817 2818 default_file_start (); 2819 } 2820 2821 /* Output that goes at the end of the file, similarly. */ 2822 2823 static void 2824 cris_file_end (void) 2825 { 2826 /* For CRIS, the default is to assume *no* executable stack, so output 2827 an executable-stack-note only when needed. */ 2828 if (TARGET_LINUX && trampolines_created) 2829 file_end_indicate_exec_stack (); 2830 } 2831 2832 /* Rename the function calls for integer multiply and divide. */ 2833 static void 2834 cris_init_libfuncs (void) 2835 { 2836 set_optab_libfunc (smul_optab, SImode, "__Mul"); 2837 set_optab_libfunc (sdiv_optab, SImode, "__Div"); 2838 set_optab_libfunc (udiv_optab, SImode, "__Udiv"); 2839 set_optab_libfunc (smod_optab, SImode, "__Mod"); 2840 set_optab_libfunc (umod_optab, SImode, "__Umod"); 2841 2842 /* Atomic data being unaligned is unfortunately a reality. 2843 Deal with it. */ 2844 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS) 2845 { 2846 set_optab_libfunc (sync_compare_and_swap_optab, SImode, 2847 "__cris_atcmpxchgr32"); 2848 set_optab_libfunc (sync_compare_and_swap_optab, HImode, 2849 "__cris_atcmpxchgr16"); 2850 } 2851 } 2852 2853 /* The INIT_EXPANDERS worker sets the per-function-data initializer and 2854 mark functions. */ 2855 2856 void 2857 cris_init_expanders (void) 2858 { 2859 /* Nothing here at the moment. */ 2860 } 2861 2862 /* Zero initialization is OK for all current fields. */ 2863 2864 static struct machine_function * 2865 cris_init_machine_status (void) 2866 { 2867 return ggc_cleared_alloc<machine_function> (); 2868 } 2869 2870 /* Split a 2 word move (DI or presumably DF) into component parts. 2871 Originally a copy of gen_split_move_double in m32r.c. */ 2872 2873 rtx 2874 cris_split_movdx (rtx *operands) 2875 { 2876 machine_mode mode = GET_MODE (operands[0]); 2877 rtx dest = operands[0]; 2878 rtx src = operands[1]; 2879 rtx val; 2880 2881 /* We used to have to handle (SUBREG (MEM)) here, but that should no 2882 longer happen; after reload there are no SUBREGs any more, and we're 2883 only called after reload. */ 2884 CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG); 2885 2886 start_sequence (); 2887 if (REG_P (dest)) 2888 { 2889 int dregno = REGNO (dest); 2890 2891 /* Reg-to-reg copy. */ 2892 if (REG_P (src)) 2893 { 2894 int sregno = REGNO (src); 2895 2896 int reverse = (dregno == sregno + 1); 2897 2898 /* We normally copy the low-numbered register first. However, if 2899 the first register operand 0 is the same as the second register of 2900 operand 1, we must copy in the opposite order. */ 2901 emit_insn (gen_rtx_SET (operand_subword (dest, reverse, TRUE, mode), 2902 operand_subword (src, reverse, TRUE, mode))); 2903 2904 emit_insn (gen_rtx_SET (operand_subword (dest, !reverse, TRUE, mode), 2905 operand_subword (src, !reverse, TRUE, mode))); 2906 } 2907 /* Constant-to-reg copy. */ 2908 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE) 2909 { 2910 rtx words[2]; 2911 split_double (src, &words[0], &words[1]); 2912 emit_insn (gen_rtx_SET (operand_subword (dest, 0, TRUE, mode), 2913 words[0])); 2914 2915 emit_insn (gen_rtx_SET (operand_subword (dest, 1, TRUE, mode), 2916 words[1])); 2917 } 2918 /* Mem-to-reg copy. */ 2919 else if (MEM_P (src)) 2920 { 2921 /* If the high-address word is used in the address, we must load it 2922 last. Otherwise, load it first. */ 2923 rtx addr = XEXP (src, 0); 2924 int reverse = (refers_to_regno_p (dregno, addr) != 0); 2925 2926 /* The original code implies that we can't do 2927 move.x [rN+],rM move.x [rN],rM+1 2928 when rN is dead, because of REG_NOTES damage. That is 2929 consistent with what I've seen, so don't try it. 2930 2931 We have two different cases here; if the addr is POST_INC, 2932 just pass it through, otherwise add constants. */ 2933 2934 if (GET_CODE (addr) == POST_INC) 2935 { 2936 rtx mem; 2937 rtx insn; 2938 2939 /* Whenever we emit insns with post-incremented 2940 addresses ourselves, we must add a post-inc note 2941 manually. */ 2942 mem = change_address (src, SImode, addr); 2943 insn 2944 = gen_rtx_SET (operand_subword (dest, 0, TRUE, mode), mem); 2945 insn = emit_insn (insn); 2946 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 2947 REG_NOTES (insn) 2948 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 2949 REG_NOTES (insn)); 2950 2951 mem = copy_rtx (mem); 2952 insn 2953 = gen_rtx_SET (operand_subword (dest, 1, TRUE, mode), mem); 2954 insn = emit_insn (insn); 2955 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 2956 REG_NOTES (insn) 2957 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 2958 REG_NOTES (insn)); 2959 } 2960 else 2961 { 2962 /* Make sure we don't get any other addresses with 2963 embedded postincrements. They should be stopped in 2964 GO_IF_LEGITIMATE_ADDRESS, but we're here for your 2965 safety. */ 2966 if (side_effects_p (addr)) 2967 fatal_insn ("unexpected side-effects in address", addr); 2968 2969 emit_insn (gen_rtx_SET 2970 (operand_subword (dest, reverse, TRUE, mode), 2971 change_address 2972 (src, SImode, 2973 plus_constant (Pmode, addr, 2974 reverse * UNITS_PER_WORD)))); 2975 emit_insn (gen_rtx_SET 2976 (operand_subword (dest, ! reverse, TRUE, mode), 2977 change_address 2978 (src, SImode, 2979 plus_constant (Pmode, addr, 2980 (! reverse) * 2981 UNITS_PER_WORD)))); 2982 } 2983 } 2984 else 2985 internal_error ("unknown src"); 2986 } 2987 /* Reg-to-mem copy or clear mem. */ 2988 else if (MEM_P (dest) 2989 && (REG_P (src) 2990 || src == const0_rtx 2991 || src == CONST0_RTX (DFmode))) 2992 { 2993 rtx addr = XEXP (dest, 0); 2994 2995 if (GET_CODE (addr) == POST_INC) 2996 { 2997 rtx mem; 2998 rtx insn; 2999 3000 /* Whenever we emit insns with post-incremented addresses 3001 ourselves, we must add a post-inc note manually. */ 3002 mem = change_address (dest, SImode, addr); 3003 insn 3004 = gen_rtx_SET (mem, operand_subword (src, 0, TRUE, mode)); 3005 insn = emit_insn (insn); 3006 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 3007 REG_NOTES (insn) 3008 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 3009 REG_NOTES (insn)); 3010 3011 mem = copy_rtx (mem); 3012 insn = gen_rtx_SET (mem, operand_subword (src, 1, TRUE, mode)); 3013 insn = emit_insn (insn); 3014 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 3015 REG_NOTES (insn) 3016 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 3017 REG_NOTES (insn)); 3018 } 3019 else 3020 { 3021 /* Make sure we don't get any other addresses with embedded 3022 postincrements. They should be stopped in 3023 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */ 3024 if (side_effects_p (addr)) 3025 fatal_insn ("unexpected side-effects in address", addr); 3026 3027 emit_insn (gen_rtx_SET 3028 (change_address (dest, SImode, addr), 3029 operand_subword (src, 0, TRUE, mode))); 3030 3031 emit_insn (gen_rtx_SET 3032 (change_address (dest, SImode, 3033 plus_constant (Pmode, addr, 3034 UNITS_PER_WORD)), 3035 operand_subword (src, 1, TRUE, mode))); 3036 } 3037 } 3038 3039 else 3040 internal_error ("unknown dest"); 3041 3042 val = get_insns (); 3043 end_sequence (); 3044 return val; 3045 } 3046 3047 /* The expander for the prologue pattern name. */ 3048 3049 void 3050 cris_expand_prologue (void) 3051 { 3052 int regno; 3053 int size = get_frame_size (); 3054 /* Shorten the used name for readability. */ 3055 int cfoa_size = crtl->outgoing_args_size; 3056 int last_movem_reg = -1; 3057 int framesize = 0; 3058 rtx mem, insn; 3059 int return_address_on_stack = cris_return_address_on_stack (); 3060 int got_really_used = false; 3061 int n_movem_regs = 0; 3062 int pretend = crtl->args.pretend_args_size; 3063 3064 /* Don't do anything if no prologues or epilogues are wanted. */ 3065 if (!TARGET_PROLOGUE_EPILOGUE) 3066 return; 3067 3068 CRIS_ASSERT (size >= 0); 3069 3070 if (crtl->uses_pic_offset_table) 3071 { 3072 /* A reference may have been optimized out (like the abort () in 3073 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that 3074 it's still used. */ 3075 push_topmost_sequence (); 3076 got_really_used 3077 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); 3078 pop_topmost_sequence (); 3079 } 3080 3081 /* Align the size to what's best for the CPU model. */ 3082 if (TARGET_STACK_ALIGN) 3083 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; 3084 3085 if (pretend) 3086 { 3087 /* See also cris_setup_incoming_varargs where 3088 cfun->machine->stdarg_regs is set. There are other setters of 3089 crtl->args.pretend_args_size than stdarg handling, like 3090 for an argument passed with parts in R13 and stack. We must 3091 not store R13 into the pretend-area for that case, as GCC does 3092 that itself. "Our" store would be marked as redundant and GCC 3093 will attempt to remove it, which will then be flagged as an 3094 internal error; trying to remove a frame-related insn. */ 3095 int stdarg_regs = cfun->machine->stdarg_regs; 3096 3097 framesize += pretend; 3098 3099 for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1; 3100 stdarg_regs > 0; 3101 regno--, pretend -= 4, stdarg_regs--) 3102 { 3103 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3104 plus_constant (Pmode, 3105 stack_pointer_rtx, 3106 -4))); 3107 /* FIXME: When dwarf2 frame output and unless asynchronous 3108 exceptions, make dwarf2 bundle together all stack 3109 adjustments like it does for registers between stack 3110 adjustments. */ 3111 RTX_FRAME_RELATED_P (insn) = 1; 3112 3113 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3114 set_mem_alias_set (mem, get_varargs_alias_set ()); 3115 insn = emit_move_insn (mem, gen_raw_REG (SImode, regno)); 3116 3117 /* Note the absence of RTX_FRAME_RELATED_P on the above insn: 3118 the value isn't restored, so we don't want to tell dwarf2 3119 that it's been stored to stack, else EH handling info would 3120 get confused. */ 3121 } 3122 3123 /* For other setters of crtl->args.pretend_args_size, we 3124 just adjust the stack by leaving the remaining size in 3125 "pretend", handled below. */ 3126 } 3127 3128 /* Save SRP if not a leaf function. */ 3129 if (return_address_on_stack) 3130 { 3131 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3132 plus_constant (Pmode, stack_pointer_rtx, 3133 -4 - pretend))); 3134 pretend = 0; 3135 RTX_FRAME_RELATED_P (insn) = 1; 3136 3137 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3138 set_mem_alias_set (mem, get_frame_alias_set ()); 3139 insn = emit_move_insn (mem, gen_raw_REG (SImode, CRIS_SRP_REGNUM)); 3140 RTX_FRAME_RELATED_P (insn) = 1; 3141 framesize += 4; 3142 } 3143 3144 /* Set up the frame pointer, if needed. */ 3145 if (frame_pointer_needed) 3146 { 3147 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3148 plus_constant (Pmode, stack_pointer_rtx, 3149 -4 - pretend))); 3150 pretend = 0; 3151 RTX_FRAME_RELATED_P (insn) = 1; 3152 3153 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3154 set_mem_alias_set (mem, get_frame_alias_set ()); 3155 insn = emit_move_insn (mem, frame_pointer_rtx); 3156 RTX_FRAME_RELATED_P (insn) = 1; 3157 3158 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); 3159 RTX_FRAME_RELATED_P (insn) = 1; 3160 3161 framesize += 4; 3162 } 3163 3164 /* Between frame-pointer and saved registers lie the area for local 3165 variables. If we get here with "pretended" size remaining, count 3166 it into the general stack size. */ 3167 size += pretend; 3168 3169 /* Get a contiguous sequence of registers, starting with R0, that need 3170 to be saved. */ 3171 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 3172 { 3173 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 3174 { 3175 n_movem_regs++; 3176 3177 /* Check if movem may be used for registers so far. */ 3178 if (regno == last_movem_reg + 1) 3179 /* Yes, update next expected register. */ 3180 last_movem_reg = regno; 3181 else 3182 { 3183 /* We cannot use movem for all registers. We have to flush 3184 any movem:ed registers we got so far. */ 3185 if (last_movem_reg != -1) 3186 { 3187 int n_saved 3188 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; 3189 3190 /* It is a win to use a side-effect assignment for 3191 64 <= size <= 128. But side-effect on movem was 3192 not usable for CRIS v0..3. Also only do it if 3193 side-effects insns are allowed. */ 3194 if ((last_movem_reg + 1) * 4 + size >= 64 3195 && (last_movem_reg + 1) * 4 + size <= 128 3196 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) 3197 && TARGET_SIDE_EFFECT_PREFIXES) 3198 { 3199 mem 3200 = gen_rtx_MEM (SImode, 3201 plus_constant (Pmode, stack_pointer_rtx, 3202 -(n_saved * 4 + size))); 3203 set_mem_alias_set (mem, get_frame_alias_set ()); 3204 insn 3205 = cris_emit_movem_store (mem, GEN_INT (n_saved), 3206 -(n_saved * 4 + size), 3207 true); 3208 } 3209 else 3210 { 3211 insn 3212 = gen_rtx_SET (stack_pointer_rtx, 3213 plus_constant (Pmode, stack_pointer_rtx, 3214 -(n_saved * 4 + size))); 3215 insn = emit_insn (insn); 3216 RTX_FRAME_RELATED_P (insn) = 1; 3217 3218 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3219 set_mem_alias_set (mem, get_frame_alias_set ()); 3220 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 3221 0, true); 3222 } 3223 3224 framesize += n_saved * 4 + size; 3225 last_movem_reg = -1; 3226 size = 0; 3227 } 3228 3229 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3230 plus_constant (Pmode, 3231 stack_pointer_rtx, 3232 -4 - size))); 3233 RTX_FRAME_RELATED_P (insn) = 1; 3234 3235 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3236 set_mem_alias_set (mem, get_frame_alias_set ()); 3237 insn = emit_move_insn (mem, gen_raw_REG (SImode, regno)); 3238 RTX_FRAME_RELATED_P (insn) = 1; 3239 3240 framesize += 4 + size; 3241 size = 0; 3242 } 3243 } 3244 } 3245 3246 /* Check after, if we could movem all registers. This is the normal case. */ 3247 if (last_movem_reg != -1) 3248 { 3249 int n_saved 3250 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; 3251 3252 /* Side-effect on movem was not usable for CRIS v0..3. Also only 3253 do it if side-effects insns are allowed. */ 3254 if ((last_movem_reg + 1) * 4 + size >= 64 3255 && (last_movem_reg + 1) * 4 + size <= 128 3256 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) 3257 && TARGET_SIDE_EFFECT_PREFIXES) 3258 { 3259 mem 3260 = gen_rtx_MEM (SImode, 3261 plus_constant (Pmode, stack_pointer_rtx, 3262 -(n_saved * 4 + size))); 3263 set_mem_alias_set (mem, get_frame_alias_set ()); 3264 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 3265 -(n_saved * 4 + size), true); 3266 } 3267 else 3268 { 3269 insn 3270 = gen_rtx_SET (stack_pointer_rtx, 3271 plus_constant (Pmode, stack_pointer_rtx, 3272 -(n_saved * 4 + size))); 3273 insn = emit_insn (insn); 3274 RTX_FRAME_RELATED_P (insn) = 1; 3275 3276 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3277 set_mem_alias_set (mem, get_frame_alias_set ()); 3278 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true); 3279 } 3280 3281 framesize += n_saved * 4 + size; 3282 /* We have to put outgoing argument space after regs. */ 3283 if (cfoa_size) 3284 { 3285 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3286 plus_constant (Pmode, 3287 stack_pointer_rtx, 3288 -cfoa_size))); 3289 RTX_FRAME_RELATED_P (insn) = 1; 3290 framesize += cfoa_size; 3291 } 3292 } 3293 else if ((size + cfoa_size) > 0) 3294 { 3295 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3296 plus_constant (Pmode, 3297 stack_pointer_rtx, 3298 -(cfoa_size + size)))); 3299 RTX_FRAME_RELATED_P (insn) = 1; 3300 framesize += size + cfoa_size; 3301 } 3302 3303 /* Set up the PIC register, if it is used. */ 3304 if (got_really_used) 3305 { 3306 rtx got 3307 = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT); 3308 emit_move_insn (pic_offset_table_rtx, got); 3309 3310 /* FIXME: This is a cover-up for flow2 messing up; it doesn't 3311 follow exceptional paths and tries to delete the GOT load as 3312 unused, if it isn't used on the non-exceptional paths. Other 3313 ports have similar or other cover-ups, or plain bugs marking 3314 the GOT register load as maybe-dead. To see this, remove the 3315 line below and try libsupc++/vec.cc or a trivial 3316 "static void y (); void x () {try {y ();} catch (...) {}}". */ 3317 emit_use (pic_offset_table_rtx); 3318 } 3319 3320 if (cris_max_stackframe && framesize > cris_max_stackframe) 3321 warning (0, "stackframe too big: %d bytes", framesize); 3322 } 3323 3324 /* The expander for the epilogue pattern. */ 3325 3326 void 3327 cris_expand_epilogue (void) 3328 { 3329 int regno; 3330 int size = get_frame_size (); 3331 int last_movem_reg = -1; 3332 int argspace_offset = crtl->outgoing_args_size; 3333 int pretend = crtl->args.pretend_args_size; 3334 rtx mem; 3335 bool return_address_on_stack = cris_return_address_on_stack (); 3336 /* A reference may have been optimized out 3337 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1) 3338 so check that it's still used. */ 3339 int got_really_used = false; 3340 int n_movem_regs = 0; 3341 3342 if (!TARGET_PROLOGUE_EPILOGUE) 3343 return; 3344 3345 if (crtl->uses_pic_offset_table) 3346 { 3347 /* A reference may have been optimized out (like the abort () in 3348 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that 3349 it's still used. */ 3350 push_topmost_sequence (); 3351 got_really_used 3352 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); 3353 pop_topmost_sequence (); 3354 } 3355 3356 /* Align byte count of stack frame. */ 3357 if (TARGET_STACK_ALIGN) 3358 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; 3359 3360 /* Check how many saved regs we can movem. They start at r0 and must 3361 be contiguous. */ 3362 for (regno = 0; 3363 regno < FIRST_PSEUDO_REGISTER; 3364 regno++) 3365 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 3366 { 3367 n_movem_regs++; 3368 3369 if (regno == last_movem_reg + 1) 3370 last_movem_reg = regno; 3371 else 3372 break; 3373 } 3374 3375 /* If there was only one register that really needed to be saved 3376 through movem, don't use movem. */ 3377 if (n_movem_regs == 1) 3378 last_movem_reg = -1; 3379 3380 /* Now emit "normal" move insns for all regs higher than the movem 3381 regs. */ 3382 for (regno = FIRST_PSEUDO_REGISTER - 1; 3383 regno > last_movem_reg; 3384 regno--) 3385 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 3386 { 3387 rtx insn; 3388 3389 if (argspace_offset) 3390 { 3391 /* There is an area for outgoing parameters located before 3392 the saved registers. We have to adjust for that. */ 3393 emit_insn (gen_rtx_SET (stack_pointer_rtx, 3394 plus_constant (Pmode, stack_pointer_rtx, 3395 argspace_offset))); 3396 /* Make sure we only do this once. */ 3397 argspace_offset = 0; 3398 } 3399 3400 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, 3401 stack_pointer_rtx)); 3402 set_mem_alias_set (mem, get_frame_alias_set ()); 3403 insn = emit_move_insn (gen_raw_REG (SImode, regno), mem); 3404 3405 /* Whenever we emit insns with post-incremented addresses 3406 ourselves, we must add a post-inc note manually. */ 3407 REG_NOTES (insn) 3408 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3409 } 3410 3411 /* If we have any movem-restore, do it now. */ 3412 if (last_movem_reg != -1) 3413 { 3414 rtx insn; 3415 3416 if (argspace_offset) 3417 { 3418 emit_insn (gen_rtx_SET (stack_pointer_rtx, 3419 plus_constant (Pmode, stack_pointer_rtx, 3420 argspace_offset))); 3421 argspace_offset = 0; 3422 } 3423 3424 mem = gen_rtx_MEM (SImode, 3425 gen_rtx_POST_INC (SImode, stack_pointer_rtx)); 3426 set_mem_alias_set (mem, get_frame_alias_set ()); 3427 insn 3428 = emit_insn (cris_gen_movem_load (mem, 3429 GEN_INT (last_movem_reg + 1), 0)); 3430 /* Whenever we emit insns with post-incremented addresses 3431 ourselves, we must add a post-inc note manually. */ 3432 if (side_effects_p (PATTERN (insn))) 3433 REG_NOTES (insn) 3434 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3435 } 3436 3437 /* If we don't clobber all of the allocated stack area (we've already 3438 deallocated saved registers), GCC might want to schedule loads from 3439 the stack to *after* the stack-pointer restore, which introduces an 3440 interrupt race condition. This happened for the initial-value 3441 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of 3442 other failure for that test). It also happened for the stack slot 3443 for the return value in (one version of) 3444 linux/fs/dcache.c:__d_lookup, at least with "-O2 3445 -fno-omit-frame-pointer". */ 3446 3447 /* Restore frame pointer if necessary. */ 3448 if (frame_pointer_needed) 3449 { 3450 rtx insn; 3451 3452 emit_insn (gen_cris_frame_deallocated_barrier ()); 3453 3454 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); 3455 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, 3456 stack_pointer_rtx)); 3457 set_mem_alias_set (mem, get_frame_alias_set ()); 3458 insn = emit_move_insn (frame_pointer_rtx, mem); 3459 3460 /* Whenever we emit insns with post-incremented addresses 3461 ourselves, we must add a post-inc note manually. */ 3462 REG_NOTES (insn) 3463 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3464 } 3465 else if ((size + argspace_offset) != 0) 3466 { 3467 emit_insn (gen_cris_frame_deallocated_barrier ()); 3468 3469 /* If there was no frame-pointer to restore sp from, we must 3470 explicitly deallocate local variables. */ 3471 3472 /* Handle space for outgoing parameters that hasn't been handled 3473 yet. */ 3474 size += argspace_offset; 3475 3476 emit_insn (gen_rtx_SET (stack_pointer_rtx, 3477 plus_constant (Pmode, stack_pointer_rtx, size))); 3478 } 3479 3480 /* If this function has no pushed register parameters 3481 (stdargs/varargs), and if it is not a leaf function, then we have 3482 the return address on the stack. */ 3483 if (return_address_on_stack && pretend == 0) 3484 { 3485 if (TARGET_V32 || crtl->calls_eh_return) 3486 { 3487 rtx mem; 3488 rtx insn; 3489 rtx srpreg = gen_raw_REG (SImode, CRIS_SRP_REGNUM); 3490 mem = gen_rtx_MEM (SImode, 3491 gen_rtx_POST_INC (SImode, 3492 stack_pointer_rtx)); 3493 set_mem_alias_set (mem, get_frame_alias_set ()); 3494 insn = emit_move_insn (srpreg, mem); 3495 3496 /* Whenever we emit insns with post-incremented addresses 3497 ourselves, we must add a post-inc note manually. */ 3498 REG_NOTES (insn) 3499 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3500 3501 if (crtl->calls_eh_return) 3502 emit_insn (gen_addsi3 (stack_pointer_rtx, 3503 stack_pointer_rtx, 3504 gen_raw_REG (SImode, CRIS_STACKADJ_REG))); 3505 cris_expand_return (false); 3506 } 3507 else 3508 cris_expand_return (true); 3509 3510 return; 3511 } 3512 3513 /* If we pushed some register parameters, then adjust the stack for 3514 them. */ 3515 if (pretend != 0) 3516 { 3517 /* If SRP is stored on the way, we need to restore it first. */ 3518 if (return_address_on_stack) 3519 { 3520 rtx mem; 3521 rtx srpreg = gen_raw_REG (SImode, CRIS_SRP_REGNUM); 3522 rtx insn; 3523 3524 mem = gen_rtx_MEM (SImode, 3525 gen_rtx_POST_INC (SImode, 3526 stack_pointer_rtx)); 3527 set_mem_alias_set (mem, get_frame_alias_set ()); 3528 insn = emit_move_insn (srpreg, mem); 3529 3530 /* Whenever we emit insns with post-incremented addresses 3531 ourselves, we must add a post-inc note manually. */ 3532 REG_NOTES (insn) 3533 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3534 } 3535 3536 emit_insn (gen_rtx_SET (stack_pointer_rtx, 3537 plus_constant (Pmode, stack_pointer_rtx, 3538 pretend))); 3539 } 3540 3541 /* Perform the "physical" unwinding that the EH machinery calculated. */ 3542 if (crtl->calls_eh_return) 3543 emit_insn (gen_addsi3 (stack_pointer_rtx, 3544 stack_pointer_rtx, 3545 gen_raw_REG (SImode, CRIS_STACKADJ_REG))); 3546 cris_expand_return (false); 3547 } 3548 3549 /* Worker function for generating movem from mem for load_multiple. */ 3550 3551 rtx 3552 cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) 3553 { 3554 int nregs = INTVAL (nregs_rtx); 3555 rtvec vec; 3556 int eltno = 1; 3557 int i; 3558 rtx srcreg = XEXP (src, 0); 3559 unsigned int regno = nregs - 1; 3560 int regno_inc = -1; 3561 3562 if (TARGET_V32) 3563 { 3564 regno = 0; 3565 regno_inc = 1; 3566 } 3567 3568 if (GET_CODE (srcreg) == POST_INC) 3569 srcreg = XEXP (srcreg, 0); 3570 3571 CRIS_ASSERT (REG_P (srcreg)); 3572 3573 /* Don't use movem for just one insn. The insns are equivalent except 3574 for the pipeline hazard (on v32); movem does not forward the loaded 3575 registers so there's a three cycles penalty for their use. */ 3576 if (nregs == 1) 3577 return gen_movsi (gen_rtx_REG (SImode, 0), src); 3578 3579 vec = rtvec_alloc (nprefix + nregs 3580 + (GET_CODE (XEXP (src, 0)) == POST_INC)); 3581 3582 if (GET_CODE (XEXP (src, 0)) == POST_INC) 3583 { 3584 RTVEC_ELT (vec, nprefix + 1) 3585 = gen_rtx_SET (srcreg, plus_constant (Pmode, srcreg, nregs * 4)); 3586 eltno++; 3587 } 3588 3589 src = replace_equiv_address (src, srcreg); 3590 RTVEC_ELT (vec, nprefix) 3591 = gen_rtx_SET (gen_rtx_REG (SImode, regno), src); 3592 regno += regno_inc; 3593 3594 for (i = 1; i < nregs; i++, eltno++) 3595 { 3596 RTVEC_ELT (vec, nprefix + eltno) 3597 = gen_rtx_SET (gen_rtx_REG (SImode, regno), 3598 adjust_address_nv (src, SImode, i * 4)); 3599 regno += regno_inc; 3600 } 3601 3602 return gen_rtx_PARALLEL (VOIDmode, vec); 3603 } 3604 3605 /* Worker function for generating movem to mem. If FRAME_RELATED, notes 3606 are added that the dwarf2 machinery understands. */ 3607 3608 rtx 3609 cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, 3610 bool frame_related) 3611 { 3612 int nregs = INTVAL (nregs_rtx); 3613 rtvec vec; 3614 int eltno = 1; 3615 int i; 3616 rtx insn; 3617 rtx destreg = XEXP (dest, 0); 3618 unsigned int regno = nregs - 1; 3619 int regno_inc = -1; 3620 3621 if (TARGET_V32) 3622 { 3623 regno = 0; 3624 regno_inc = 1; 3625 } 3626 3627 if (GET_CODE (destreg) == POST_INC) 3628 increment += nregs * 4; 3629 3630 if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS) 3631 destreg = XEXP (destreg, 0); 3632 3633 CRIS_ASSERT (REG_P (destreg)); 3634 3635 /* Don't use movem for just one insn. The insns are equivalent except 3636 for the pipeline hazard (on v32); movem does not forward the loaded 3637 registers so there's a three cycles penalty for use. */ 3638 if (nregs == 1) 3639 { 3640 rtx mov = gen_rtx_SET (dest, gen_rtx_REG (SImode, 0)); 3641 3642 if (increment == 0) 3643 { 3644 insn = emit_insn (mov); 3645 if (frame_related) 3646 RTX_FRAME_RELATED_P (insn) = 1; 3647 return insn; 3648 } 3649 3650 /* If there was a request for a side-effect, create the ordinary 3651 parallel. */ 3652 vec = rtvec_alloc (2); 3653 3654 RTVEC_ELT (vec, 0) = mov; 3655 RTVEC_ELT (vec, 1) = gen_rtx_SET (destreg, plus_constant (Pmode, destreg, 3656 increment)); 3657 if (frame_related) 3658 { 3659 RTX_FRAME_RELATED_P (mov) = 1; 3660 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; 3661 } 3662 } 3663 else 3664 { 3665 vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0)); 3666 RTVEC_ELT (vec, 0) 3667 = gen_rtx_SET (replace_equiv_address (dest, 3668 plus_constant (Pmode, destreg, 3669 increment)), 3670 gen_rtx_REG (SImode, regno)); 3671 regno += regno_inc; 3672 3673 /* The dwarf2 info wants this mark on each component in a parallel 3674 that's part of the prologue (though it's optional on the first 3675 component). */ 3676 if (frame_related) 3677 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1; 3678 3679 if (increment != 0) 3680 { 3681 RTVEC_ELT (vec, 1) 3682 = gen_rtx_SET (destreg, plus_constant (Pmode, destreg, 3683 increment != 0 3684 ? increment : nregs * 4)); 3685 eltno++; 3686 3687 if (frame_related) 3688 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; 3689 3690 /* Don't call adjust_address_nv on a post-incremented address if 3691 we can help it. */ 3692 if (GET_CODE (XEXP (dest, 0)) == POST_INC) 3693 dest = replace_equiv_address (dest, destreg); 3694 } 3695 3696 for (i = 1; i < nregs; i++, eltno++) 3697 { 3698 RTVEC_ELT (vec, eltno) 3699 = gen_rtx_SET (adjust_address_nv (dest, SImode, i * 4), 3700 gen_rtx_REG (SImode, regno)); 3701 if (frame_related) 3702 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1; 3703 regno += regno_inc; 3704 } 3705 } 3706 3707 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); 3708 3709 /* Because dwarf2out.c handles the insns in a parallel as a sequence, 3710 we need to keep the stack adjustment separate, after the 3711 MEM-setters. Else the stack-adjustment in the second component of 3712 the parallel would be mishandled; the offsets for the SETs that 3713 follow it would be wrong. We prepare for this by adding a 3714 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE 3715 followed by the increment. Note that we have FRAME_RELATED_P on 3716 all the SETs, including the original stack adjustment SET in the 3717 parallel. */ 3718 if (frame_related) 3719 { 3720 if (increment != 0) 3721 { 3722 rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1)); 3723 XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0)); 3724 for (i = 1; i < nregs; i++) 3725 XVECEXP (seq, 0, i) 3726 = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1)); 3727 XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1)); 3728 add_reg_note (insn, REG_FRAME_RELATED_EXPR, seq); 3729 } 3730 3731 RTX_FRAME_RELATED_P (insn) = 1; 3732 } 3733 3734 return insn; 3735 } 3736 3737 /* Worker function for expanding the address for PIC function calls. */ 3738 3739 void 3740 cris_expand_pic_call_address (rtx *opp, rtx *markerp) 3741 { 3742 rtx op = *opp; 3743 3744 gcc_assert (flag_pic && MEM_P (op)); 3745 op = XEXP (op, 0); 3746 3747 /* It might be that code can be generated that jumps to 0 (or to a 3748 specific address). Don't die on that. (There is a 3749 testcase.) */ 3750 if (CONSTANT_P (op) && !CONST_INT_P (op)) 3751 { 3752 enum cris_symbol_type t = cris_symbol_type_of (op); 3753 3754 CRIS_ASSERT (can_create_pseudo_p ()); 3755 3756 /* For local symbols (non-PLT), just get the plain symbol 3757 reference into a register. For symbols that can be PLT, make 3758 them PLT. */ 3759 if (t == cris_rel_symbol) 3760 { 3761 /* For v32, we're fine as-is; just PICify the symbol. Forcing 3762 into a register caused performance regression for 3.2.1, 3763 observable in __floatdidf and elsewhere in libgcc. */ 3764 if (TARGET_V32) 3765 { 3766 rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op); 3767 HOST_WIDE_INT offs = get_integer_term (op); 3768 3769 /* We can't get calls to sym+N, N integer, can we? */ 3770 gcc_assert (offs == 0); 3771 3772 op = gen_rtx_CONST (Pmode, 3773 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 3774 CRIS_UNSPEC_PCREL)); 3775 } 3776 else 3777 op = force_reg (Pmode, op); 3778 3779 /* A local call. */ 3780 *markerp = const0_rtx; 3781 } 3782 else if (t == cris_got_symbol) 3783 { 3784 if (TARGET_AVOID_GOTPLT) 3785 { 3786 /* Change a "jsr sym" into (allocate register rM, rO) 3787 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM" 3788 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and 3789 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))" 3790 for v32. */ 3791 rtx tem, rm, ro; 3792 3793 crtl->uses_pic_offset_table = 1; 3794 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), 3795 TARGET_V32 3796 ? CRIS_UNSPEC_PLT_PCREL 3797 : CRIS_UNSPEC_PLT_GOTREL); 3798 tem = gen_rtx_CONST (Pmode, tem); 3799 if (TARGET_V32) 3800 op = tem; 3801 else 3802 { 3803 rm = gen_reg_rtx (Pmode); 3804 emit_move_insn (rm, tem); 3805 ro = gen_reg_rtx (Pmode); 3806 if (expand_binop (Pmode, add_optab, rm, 3807 pic_offset_table_rtx, 3808 ro, 0, OPTAB_LIB_WIDEN) != ro) 3809 internal_error ("expand_binop failed in movsi got"); 3810 op = ro; 3811 } 3812 } 3813 else 3814 { 3815 /* Change a "jsr sym" into (allocate register rM, rO) 3816 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM" 3817 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access 3818 marked as not trapping and not aliasing. No "move.d 3819 [rO],rP" as that would invite to re-use of a value 3820 that should not be reused. FIXME: Need a peephole2 3821 for cases when this is cse:d from the call, to change 3822 back to just get the PLT entry address, so we don't 3823 resolve the same symbol over and over (the memory 3824 access of the PLTGOT isn't constant). */ 3825 rtx tem, mem, rm, ro; 3826 3827 gcc_assert (can_create_pseudo_p ()); 3828 crtl->uses_pic_offset_table = 1; 3829 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), 3830 CRIS_UNSPEC_PLTGOTREAD); 3831 rm = gen_reg_rtx (Pmode); 3832 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); 3833 ro = gen_reg_rtx (Pmode); 3834 if (expand_binop (Pmode, add_optab, rm, 3835 pic_offset_table_rtx, 3836 ro, 0, OPTAB_LIB_WIDEN) != ro) 3837 internal_error ("expand_binop failed in movsi got"); 3838 mem = gen_rtx_MEM (Pmode, ro); 3839 3840 /* This MEM doesn't alias anything. Whether it aliases 3841 other same symbols is unimportant. */ 3842 set_mem_alias_set (mem, new_alias_set ()); 3843 MEM_NOTRAP_P (mem) = 1; 3844 op = mem; 3845 } 3846 3847 /* We need to prepare this call to go through the PLT; we 3848 need to make GOT available. */ 3849 *markerp = pic_offset_table_rtx; 3850 } 3851 else 3852 /* Can't possibly get anything else for a function-call, right? */ 3853 fatal_insn ("unidentifiable call op", op); 3854 3855 /* If the validizing variant is called, it will try to validize 3856 the address as a valid any-operand constant, but as it's only 3857 valid for calls and moves, it will fail and always be forced 3858 into a register. */ 3859 *opp = replace_equiv_address_nv (*opp, op); 3860 } 3861 else 3862 /* Can't tell what locality a call to a non-constant address has; 3863 better make the GOT register alive at it. 3864 FIXME: Can we see whether the register has known constant 3865 contents? */ 3866 *markerp = pic_offset_table_rtx; 3867 } 3868 3869 /* Make sure operands are in the right order for an addsi3 insn as 3870 generated by a define_split. Nothing but REG_P as the first 3871 operand is recognized by addsi3 after reload. OPERANDS contains 3872 the operands, with the first at OPERANDS[N] and the second at 3873 OPERANDS[N+1]. */ 3874 3875 void 3876 cris_order_for_addsi3 (rtx *operands, int n) 3877 { 3878 if (!REG_P (operands[n])) 3879 { 3880 rtx tem = operands[n]; 3881 operands[n] = operands[n + 1]; 3882 operands[n + 1] = tem; 3883 } 3884 } 3885 3886 /* Use from within code, from e.g. PRINT_OPERAND and 3887 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit 3888 different things depending on whether code operand or constant is 3889 emitted. */ 3890 3891 static void 3892 cris_output_addr_const (FILE *file, rtx x) 3893 { 3894 in_code++; 3895 output_addr_const (file, x); 3896 in_code--; 3897 } 3898 3899 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */ 3900 3901 void 3902 cris_asm_output_symbol_ref (FILE *file, rtx x) 3903 { 3904 gcc_assert (GET_CODE (x) == SYMBOL_REF); 3905 3906 if (flag_pic && in_code > 0) 3907 { 3908 const char *origstr = XSTR (x, 0); 3909 const char *str; 3910 str = (* targetm.strip_name_encoding) (origstr); 3911 assemble_name (file, str); 3912 3913 /* Sanity check. */ 3914 if (!TARGET_V32 && !crtl->uses_pic_offset_table) 3915 output_operand_lossage ("PIC register isn't set up"); 3916 } 3917 else 3918 assemble_name (file, XSTR (x, 0)); 3919 } 3920 3921 /* Worker function for ASM_OUTPUT_LABEL_REF. */ 3922 3923 void 3924 cris_asm_output_label_ref (FILE *file, char *buf) 3925 { 3926 if (flag_pic && in_code > 0) 3927 { 3928 assemble_name (file, buf); 3929 3930 /* Sanity check. */ 3931 if (!TARGET_V32 && !crtl->uses_pic_offset_table) 3932 internal_error ("emitting PIC operand, but PIC register " 3933 "isn%'t set up"); 3934 } 3935 else 3936 assemble_name (file, buf); 3937 } 3938 3939 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ 3940 3941 static bool 3942 cris_output_addr_const_extra (FILE *file, rtx xconst) 3943 { 3944 switch (GET_CODE (xconst)) 3945 { 3946 rtx x; 3947 3948 case UNSPEC: 3949 x = XVECEXP (xconst, 0, 0); 3950 CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF 3951 || GET_CODE (x) == LABEL_REF 3952 || GET_CODE (x) == CONST); 3953 output_addr_const (file, x); 3954 switch (XINT (xconst, 1)) 3955 { 3956 case CRIS_UNSPEC_PCREL: 3957 /* We only get this with -fpic/PIC to tell it apart from an 3958 invalid symbol. We can't tell here, but it should only 3959 be the operand of a call or movsi. */ 3960 gcc_assert (TARGET_V32 && flag_pic); 3961 break; 3962 3963 case CRIS_UNSPEC_PLT_PCREL: 3964 gcc_assert (TARGET_V32); 3965 fprintf (file, ":PLT"); 3966 break; 3967 3968 case CRIS_UNSPEC_PLT_GOTREL: 3969 gcc_assert (!TARGET_V32); 3970 fprintf (file, ":PLTG"); 3971 break; 3972 3973 case CRIS_UNSPEC_GOTREL: 3974 gcc_assert (!TARGET_V32); 3975 fprintf (file, ":GOTOFF"); 3976 break; 3977 3978 case CRIS_UNSPEC_GOTREAD: 3979 if (flag_pic == 1) 3980 fprintf (file, ":GOT16"); 3981 else 3982 fprintf (file, ":GOT"); 3983 break; 3984 3985 case CRIS_UNSPEC_PLTGOTREAD: 3986 if (flag_pic == 1) 3987 fprintf (file, CRIS_GOTPLT_SUFFIX "16"); 3988 else 3989 fprintf (file, CRIS_GOTPLT_SUFFIX); 3990 break; 3991 3992 default: 3993 gcc_unreachable (); 3994 } 3995 return true; 3996 3997 default: 3998 return false; 3999 } 4000 } 4001 4002 /* Worker function for TARGET_STRUCT_VALUE_RTX. */ 4003 4004 static rtx 4005 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, 4006 int incoming ATTRIBUTE_UNUSED) 4007 { 4008 return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM); 4009 } 4010 4011 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ 4012 4013 static void 4014 cris_setup_incoming_varargs (cumulative_args_t ca_v, 4015 machine_mode mode ATTRIBUTE_UNUSED, 4016 tree type ATTRIBUTE_UNUSED, 4017 int *pretend_arg_size, 4018 int second_time) 4019 { 4020 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); 4021 4022 if (ca->regs < CRIS_MAX_ARGS_IN_REGS) 4023 { 4024 int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs; 4025 cfun->machine->stdarg_regs = stdarg_regs; 4026 *pretend_arg_size = stdarg_regs * 4; 4027 } 4028 4029 if (TARGET_PDEBUG) 4030 fprintf (asm_out_file, 4031 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n", 4032 ca->regs, *pretend_arg_size, second_time); 4033 } 4034 4035 /* Return true if TYPE must be passed by invisible reference. 4036 For cris, we pass <= 8 bytes by value, others by reference. */ 4037 4038 static bool 4039 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, 4040 machine_mode mode, const_tree type, 4041 bool named ATTRIBUTE_UNUSED) 4042 { 4043 return (targetm.calls.must_pass_in_stack (mode, type) 4044 || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8); 4045 } 4046 4047 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments 4048 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the 4049 best code size and speed for gcc, ipps and products in gcc-2.7.2. */ 4050 4051 machine_mode 4052 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, 4053 machine_mode mode, 4054 int *punsignedp ATTRIBUTE_UNUSED, 4055 const_tree fntype ATTRIBUTE_UNUSED, 4056 int for_return) 4057 { 4058 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even 4059 when modifying TARGET_FUNCTION_VALUE to return the promoted mode). 4060 Maybe pointless as of now, but let's keep the old behavior. */ 4061 if (for_return == 1) 4062 return mode; 4063 return CRIS_PROMOTED_MODE (mode, *punsignedp, type); 4064 } 4065 4066 /* Atomic types require alignment to be at least their "natural" size. */ 4067 4068 static unsigned int 4069 cris_atomic_align_for_mode (machine_mode mode) 4070 { 4071 return GET_MODE_BITSIZE (mode); 4072 } 4073 4074 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the 4075 time being. */ 4076 4077 static rtx 4078 cris_function_value(const_tree type, 4079 const_tree func ATTRIBUTE_UNUSED, 4080 bool outgoing ATTRIBUTE_UNUSED) 4081 { 4082 return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG); 4083 } 4084 4085 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the 4086 time being. */ 4087 4088 static rtx 4089 cris_libcall_value (machine_mode mode, 4090 const_rtx fun ATTRIBUTE_UNUSED) 4091 { 4092 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG); 4093 } 4094 4095 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the 4096 time being. */ 4097 4098 static bool 4099 cris_function_value_regno_p (const unsigned int regno) 4100 { 4101 return (regno == CRIS_FIRST_ARG_REG); 4102 } 4103 4104 static int 4105 cris_arg_partial_bytes (cumulative_args_t ca, machine_mode mode, 4106 tree type, bool named ATTRIBUTE_UNUSED) 4107 { 4108 if (get_cumulative_args (ca)->regs == CRIS_MAX_ARGS_IN_REGS - 1 4109 && !targetm.calls.must_pass_in_stack (mode, type) 4110 && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4 4111 && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8) 4112 return UNITS_PER_WORD; 4113 else 4114 return 0; 4115 } 4116 4117 static rtx 4118 cris_function_arg_1 (cumulative_args_t ca_v, 4119 machine_mode mode ATTRIBUTE_UNUSED, 4120 const_tree type ATTRIBUTE_UNUSED, 4121 bool named, bool incoming) 4122 { 4123 const CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); 4124 4125 if ((!incoming || named) && ca->regs < CRIS_MAX_ARGS_IN_REGS) 4126 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG + ca->regs); 4127 else 4128 return NULL_RTX; 4129 } 4130 4131 /* Worker function for TARGET_FUNCTION_ARG. 4132 The void_type_node is sent as a "closing" call. */ 4133 4134 static rtx 4135 cris_function_arg (cumulative_args_t ca, machine_mode mode, 4136 const_tree type, bool named) 4137 { 4138 return cris_function_arg_1 (ca, mode, type, named, false); 4139 } 4140 4141 /* Worker function for TARGET_FUNCTION_INCOMING_ARG. 4142 4143 The differences between this and the previous, is that this one checks 4144 that an argument is named, since incoming stdarg/varargs arguments are 4145 pushed onto the stack, and we don't have to check against the "closing" 4146 void_type_node TYPE parameter. */ 4147 4148 static rtx 4149 cris_function_incoming_arg (cumulative_args_t ca, machine_mode mode, 4150 const_tree type, bool named) 4151 { 4152 return cris_function_arg_1 (ca, mode, type, named, true); 4153 } 4154 4155 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */ 4156 4157 static void 4158 cris_function_arg_advance (cumulative_args_t ca_v, machine_mode mode, 4159 const_tree type, bool named ATTRIBUTE_UNUSED) 4160 { 4161 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); 4162 4163 ca->regs += (3 + CRIS_FUNCTION_ARG_SIZE (mode, type)) / 4; 4164 } 4165 4166 /* Worker function for TARGET_MD_ASM_ADJUST. */ 4167 4168 static rtx_insn * 4169 cris_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &inputs, 4170 vec<const char *> &constraints, 4171 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs) 4172 { 4173 /* For the time being, all asms clobber condition codes. 4174 Revisit when there's a reasonable use for inputs/outputs 4175 that mention condition codes. */ 4176 clobbers.safe_push (gen_rtx_REG (CCmode, CRIS_CC0_REGNUM)); 4177 SET_HARD_REG_BIT (clobbered_regs, CRIS_CC0_REGNUM); 4178 4179 /* Determine if the source using MOF. If it is, automatically 4180 clobbering MOF would cause it to have impossible constraints. */ 4181 4182 /* Look for a use of the MOF constraint letter: h. */ 4183 for (unsigned i = 0, n = constraints.length(); i < n; ++i) 4184 if (strchr (constraints[i], 'h') != NULL) 4185 return NULL; 4186 4187 /* Look for an output or an input that touches MOF. */ 4188 rtx mof_reg = gen_rtx_REG (SImode, CRIS_MOF_REGNUM); 4189 for (unsigned i = 0, n = outputs.length(); i < n; ++i) 4190 if (reg_overlap_mentioned_p (mof_reg, outputs[i])) 4191 return NULL; 4192 for (unsigned i = 0, n = inputs.length(); i < n; ++i) 4193 if (reg_overlap_mentioned_p (mof_reg, inputs[i])) 4194 return NULL; 4195 4196 /* No direct reference to MOF or its constraint. 4197 Clobber it for backward compatibility. */ 4198 clobbers.safe_push (mof_reg); 4199 SET_HARD_REG_BIT (clobbered_regs, CRIS_MOF_REGNUM); 4200 return NULL; 4201 } 4202 4203 /* Implement TARGET_FRAME_POINTER_REQUIRED. 4204 4205 Really only needed if the stack frame has variable length (alloca 4206 or variable sized local arguments (GNU C extension). See PR39499 and 4207 PR38609 for the reason this isn't just 0. */ 4208 4209 bool 4210 cris_frame_pointer_required (void) 4211 { 4212 return !crtl->sp_is_unchanging; 4213 } 4214 4215 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE. 4216 4217 This looks too complicated, and it is. I assigned r7 to be the 4218 static chain register, but it is call-saved, so we have to save it, 4219 and come back to restore it after the call, so we have to save srp... 4220 Anyway, trampolines are rare enough that we can cope with this 4221 somewhat lack of elegance. 4222 (Do not be tempted to "straighten up" whitespace in the asms; the 4223 assembler #NO_APP state mandates strict spacing). */ 4224 /* ??? See the i386 regparm=3 implementation that pushes the static 4225 chain value to the stack in the trampoline, and uses a call-saved 4226 register when called directly. */ 4227 4228 static void 4229 cris_asm_trampoline_template (FILE *f) 4230 { 4231 if (TARGET_V32) 4232 { 4233 /* This normally-unused nop insn acts as an instruction to 4234 the simulator to flush its instruction cache. None of 4235 the other instructions in the trampoline template suits 4236 as a trigger for V32. The pc-relative addressing mode 4237 works nicely as a trigger for V10. 4238 FIXME: Have specific V32 template (possibly avoiding the 4239 use of a special instruction). */ 4240 fprintf (f, "\tclearf x\n"); 4241 /* We have to use a register as an intermediate, choosing 4242 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM), 4243 so we can use it for address indirection and jsr target. */ 4244 fprintf (f, "\tmove $r1,$mof\n"); 4245 /* +4 */ 4246 fprintf (f, "\tmove.d 0,$r1\n"); 4247 fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]); 4248 fprintf (f, "\taddq 6,$r1\n"); 4249 fprintf (f, "\tmove $mof,[$r1]\n"); 4250 fprintf (f, "\taddq 6,$r1\n"); 4251 fprintf (f, "\tmove $srp,[$r1]\n"); 4252 /* +20 */ 4253 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4254 /* +26 */ 4255 fprintf (f, "\tmove.d 0,$r1\n"); 4256 fprintf (f, "\tjsr $r1\n"); 4257 fprintf (f, "\tsetf\n"); 4258 /* +36 */ 4259 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4260 /* +42 */ 4261 fprintf (f, "\tmove.d 0,$r1\n"); 4262 /* +48 */ 4263 fprintf (f, "\tmove.d 0,$r9\n"); 4264 fprintf (f, "\tjump $r9\n"); 4265 fprintf (f, "\tsetf\n"); 4266 } 4267 else 4268 { 4269 fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]); 4270 fprintf (f, "\tmove $srp,[$pc+22]\n"); 4271 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4272 fprintf (f, "\tjsr 0\n"); 4273 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4274 fprintf (f, "\tjump 0\n"); 4275 } 4276 } 4277 4278 /* Implement TARGET_TRAMPOLINE_INIT. */ 4279 4280 static void 4281 cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 4282 { 4283 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 4284 rtx tramp = XEXP (m_tramp, 0); 4285 rtx mem; 4286 4287 emit_block_move (m_tramp, assemble_trampoline_template (), 4288 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); 4289 4290 if (TARGET_V32) 4291 { 4292 mem = adjust_address (m_tramp, SImode, 6); 4293 emit_move_insn (mem, plus_constant (Pmode, tramp, 38)); 4294 mem = adjust_address (m_tramp, SImode, 22); 4295 emit_move_insn (mem, chain_value); 4296 mem = adjust_address (m_tramp, SImode, 28); 4297 emit_move_insn (mem, fnaddr); 4298 } 4299 else 4300 { 4301 mem = adjust_address (m_tramp, SImode, 10); 4302 emit_move_insn (mem, chain_value); 4303 mem = adjust_address (m_tramp, SImode, 16); 4304 emit_move_insn (mem, fnaddr); 4305 } 4306 4307 /* Note that there is no need to do anything with the cache for 4308 sake of a trampoline. */ 4309 } 4310 4311 /* Implement TARGET_HARD_REGNO_NREGS. 4312 4313 The VOIDmode test is so we can omit mode on anonymous insns. FIXME: 4314 Still needed in 2.9x, at least for Axis-20000319. */ 4315 4316 static unsigned int 4317 cris_hard_regno_nregs (unsigned int, machine_mode mode) 4318 { 4319 if (mode == VOIDmode) 4320 return 1; 4321 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); 4322 } 4323 4324 /* Implement TARGET_HARD_REGNO_MODE_OK. 4325 4326 CRIS permits all registers to hold all modes. Well, except for the 4327 condition-code register. And we can't hold larger-than-register size 4328 modes in the last special register that can hold a full 32 bits. */ 4329 static bool 4330 cris_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 4331 { 4332 return ((mode == CCmode || regno != CRIS_CC0_REGNUM) 4333 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD 4334 || (regno != CRIS_MOF_REGNUM && regno != CRIS_ACR_REGNUM))); 4335 } 4336 4337 /* Return the preferred minimum alignment for a static object. */ 4338 4339 static HOST_WIDE_INT 4340 cris_preferred_mininum_alignment (void) 4341 { 4342 if (!TARGET_CONST_ALIGN) 4343 return 8; 4344 if (TARGET_ALIGN_BY_32) 4345 return 32; 4346 return 16; 4347 } 4348 4349 /* Implement TARGET_STATIC_RTX_ALIGNMENT. */ 4350 4351 static HOST_WIDE_INT 4352 cris_static_rtx_alignment (machine_mode mode) 4353 { 4354 return MAX (cris_preferred_mininum_alignment (), GET_MODE_ALIGNMENT (mode)); 4355 } 4356 4357 /* Implement TARGET_CONSTANT_ALIGNMENT. Note that this hook has the 4358 effect of making gcc believe that ALL references to constant stuff 4359 (in code segment, like strings) have this alignment. That is a rather 4360 rushed assumption. Luckily we do not care about the "alignment" 4361 operand to builtin memcpy (only place where it counts), so it doesn't 4362 affect any bad spots. */ 4363 4364 static HOST_WIDE_INT 4365 cris_constant_alignment (const_tree, HOST_WIDE_INT basic_align) 4366 { 4367 return MAX (cris_preferred_mininum_alignment (), basic_align); 4368 } 4369 4370 #if 0 4371 /* Various small functions to replace macros. Only called from a 4372 debugger. They might collide with gcc functions or system functions, 4373 so only emit them when '#if 1' above. */ 4374 4375 enum rtx_code Get_code (rtx); 4376 4377 enum rtx_code 4378 Get_code (rtx x) 4379 { 4380 return GET_CODE (x); 4381 } 4382 4383 const char *Get_mode (rtx); 4384 4385 const char * 4386 Get_mode (rtx x) 4387 { 4388 return GET_MODE_NAME (GET_MODE (x)); 4389 } 4390 4391 rtx Xexp (rtx, int); 4392 4393 rtx 4394 Xexp (rtx x, int n) 4395 { 4396 return XEXP (x, n); 4397 } 4398 4399 rtx Xvecexp (rtx, int, int); 4400 4401 rtx 4402 Xvecexp (rtx x, int n, int m) 4403 { 4404 return XVECEXP (x, n, m); 4405 } 4406 4407 int Get_rtx_len (rtx); 4408 4409 int 4410 Get_rtx_len (rtx x) 4411 { 4412 return GET_RTX_LENGTH (GET_CODE (x)); 4413 } 4414 4415 /* Use upper-case to distinguish from local variables that are sometimes 4416 called next_insn and prev_insn. */ 4417 4418 rtx Next_insn (rtx); 4419 4420 rtx 4421 Next_insn (rtx insn) 4422 { 4423 return NEXT_INSN (insn); 4424 } 4425 4426 rtx Prev_insn (rtx); 4427 4428 rtx 4429 Prev_insn (rtx insn) 4430 { 4431 return PREV_INSN (insn); 4432 } 4433 #endif 4434 4435 #include "gt-cris.h" 4436 4437 /* 4438 * Local variables: 4439 * eval: (c-set-style "gnu") 4440 * indent-tabs-mode: t 4441 * End: 4442 */ 4443