1 /* Definitions for GCC. Part of the machine description for CRIS. 2 Copyright (C) 1998-2020 Free Software Foundation, Inc. 3 Contributed by Axis Communications. Written by Hans-Peter Nilsson. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #define IN_TARGET_CODE 1 22 23 #include "config.h" 24 #include "system.h" 25 #include "coretypes.h" 26 #include "backend.h" 27 #include "target.h" 28 #include "rtl.h" 29 #include "tree.h" 30 #include "stringpool.h" 31 #include "attribs.h" 32 #include "cfghooks.h" 33 #include "df.h" 34 #include "memmodel.h" 35 #include "tm_p.h" 36 #include "optabs.h" 37 #include "regs.h" 38 #include "emit-rtl.h" 39 #include "recog.h" 40 #include "cgraph.h" 41 #include "diagnostic-core.h" 42 #include "conditions.h" 43 #include "insn-attr.h" 44 #include "alias.h" 45 #include "varasm.h" 46 #include "stor-layout.h" 47 #include "calls.h" 48 #include "explow.h" 49 #include "expr.h" 50 #include "reload.h" 51 #include "output.h" 52 #include "tm-constrs.h" 53 #include "builtins.h" 54 55 /* This file should be included last. */ 56 #include "target-def.h" 57 58 /* Usable when we have an amount to add or subtract, and want the 59 optimal size of the insn. */ 60 #define ADDITIVE_SIZE_MODIFIER(size) \ 61 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d") 62 63 #define LOSE_AND_RETURN(msgid, x) \ 64 do \ 65 { \ 66 cris_operand_lossage (msgid, x); \ 67 return; \ 68 } while (0) 69 70 enum cris_retinsn_type 71 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP }; 72 73 /* Per-function machine data. */ 74 struct GTY(()) machine_function 75 { 76 int needs_return_address_on_stack; 77 78 /* This is the number of registers we save in the prologue due to 79 stdarg. */ 80 int stdarg_regs; 81 82 enum cris_retinsn_type return_type; 83 }; 84 85 /* This little fix suppresses the 'u' or 's' when '%e' in assembly 86 pattern. */ 87 static char cris_output_insn_is_bound = 0; 88 89 /* In code for output macros, this is how we know whether e.g. constant 90 goes in code or in a static initializer. */ 91 static int in_code = 0; 92 93 /* Fix for reg_overlap_mentioned_p. */ 94 static int cris_reg_overlap_mentioned_p (rtx, rtx); 95 96 static machine_mode cris_promote_function_mode (const_tree, machine_mode, 97 int *, const_tree, int); 98 99 static unsigned int cris_atomic_align_for_mode (machine_mode); 100 101 static void cris_print_base (rtx, FILE *); 102 103 static void cris_print_index (rtx, FILE *); 104 105 static void cris_output_addr_const (FILE *, rtx); 106 107 static struct machine_function * cris_init_machine_status (void); 108 109 static rtx cris_struct_value_rtx (tree, int); 110 111 static void cris_setup_incoming_varargs (cumulative_args_t, 112 const function_arg_info &, 113 int *, int); 114 115 static int cris_initial_frame_pointer_offset (void); 116 117 static void cris_operand_lossage (const char *, rtx); 118 119 static int cris_reg_saved_in_regsave_area (unsigned int, bool); 120 121 static void cris_print_operand (FILE *, rtx, int); 122 123 static void cris_print_operand_address (FILE *, machine_mode, rtx); 124 125 static bool cris_print_operand_punct_valid_p (unsigned char code); 126 127 static bool cris_output_addr_const_extra (FILE *, rtx); 128 129 static void cris_conditional_register_usage (void); 130 131 static void cris_asm_output_mi_thunk 132 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); 133 134 static void cris_file_start (void); 135 static void cris_init_libfuncs (void); 136 137 static reg_class_t cris_preferred_reload_class (rtx, reg_class_t); 138 139 static int cris_register_move_cost (machine_mode, reg_class_t, reg_class_t); 140 static int cris_memory_move_cost (machine_mode, reg_class_t, bool); 141 static bool cris_rtx_costs (rtx, machine_mode, int, int, int *, bool); 142 static int cris_address_cost (rtx, machine_mode, addr_space_t, bool); 143 static bool cris_pass_by_reference (cumulative_args_t, 144 const function_arg_info &); 145 static int cris_arg_partial_bytes (cumulative_args_t, 146 const function_arg_info &); 147 static rtx cris_function_arg (cumulative_args_t, const function_arg_info &); 148 static rtx cris_function_incoming_arg (cumulative_args_t, 149 const function_arg_info &); 150 static void cris_function_arg_advance (cumulative_args_t, 151 const function_arg_info &); 152 static rtx_insn *cris_md_asm_adjust (vec<rtx> &, vec<rtx> &, 153 vec<const char *> &, 154 vec<rtx> &, HARD_REG_SET &); 155 static bool cris_cannot_force_const_mem (machine_mode, rtx); 156 157 static void cris_option_override (void); 158 159 static bool cris_frame_pointer_required (void); 160 161 static void cris_asm_trampoline_template (FILE *); 162 static void cris_trampoline_init (rtx, tree, rtx); 163 164 static rtx cris_function_value(const_tree, const_tree, bool); 165 static rtx cris_libcall_value (machine_mode, const_rtx); 166 static bool cris_function_value_regno_p (const unsigned int); 167 static void cris_file_end (void); 168 static unsigned int cris_hard_regno_nregs (unsigned int, machine_mode); 169 static bool cris_hard_regno_mode_ok (unsigned int, machine_mode); 170 static HOST_WIDE_INT cris_static_rtx_alignment (machine_mode); 171 static HOST_WIDE_INT cris_constant_alignment (const_tree, HOST_WIDE_INT); 172 173 /* This is the parsed result of the "-max-stack-stackframe=" option. If 174 it (still) is zero, then there was no such option given. */ 175 int cris_max_stackframe = 0; 176 177 /* This is the parsed result of the "-march=" option, if given. */ 178 int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; 179 180 #undef TARGET_ASM_ALIGNED_HI_OP 181 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 182 #undef TARGET_ASM_ALIGNED_SI_OP 183 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t" 184 #undef TARGET_ASM_ALIGNED_DI_OP 185 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" 186 187 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only 188 available in ELF. These "normal" pseudos do not have any alignment 189 constraints or side-effects. */ 190 #undef TARGET_ASM_UNALIGNED_HI_OP 191 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP 192 193 #undef TARGET_ASM_UNALIGNED_SI_OP 194 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP 195 196 #undef TARGET_ASM_UNALIGNED_DI_OP 197 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP 198 199 #undef TARGET_PRINT_OPERAND 200 #define TARGET_PRINT_OPERAND cris_print_operand 201 #undef TARGET_PRINT_OPERAND_ADDRESS 202 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address 203 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 204 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p 205 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA 206 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra 207 208 #undef TARGET_CONDITIONAL_REGISTER_USAGE 209 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage 210 211 #undef TARGET_ASM_OUTPUT_MI_THUNK 212 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk 213 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 214 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 215 216 #undef TARGET_ASM_FILE_START 217 #define TARGET_ASM_FILE_START cris_file_start 218 #undef TARGET_ASM_FILE_END 219 #define TARGET_ASM_FILE_END cris_file_end 220 221 #undef TARGET_INIT_LIBFUNCS 222 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs 223 224 #undef TARGET_LRA_P 225 #define TARGET_LRA_P hook_bool_void_false 226 227 #undef TARGET_LEGITIMATE_ADDRESS_P 228 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p 229 230 #undef TARGET_LEGITIMATE_CONSTANT_P 231 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p 232 233 #undef TARGET_PREFERRED_RELOAD_CLASS 234 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class 235 236 #undef TARGET_REGISTER_MOVE_COST 237 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost 238 #undef TARGET_MEMORY_MOVE_COST 239 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost 240 #undef TARGET_RTX_COSTS 241 #define TARGET_RTX_COSTS cris_rtx_costs 242 #undef TARGET_ADDRESS_COST 243 #define TARGET_ADDRESS_COST cris_address_cost 244 245 #undef TARGET_PROMOTE_FUNCTION_MODE 246 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode 247 248 #undef TARGET_ATOMIC_ALIGN_FOR_MODE 249 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode 250 251 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE 252 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed 253 254 #undef TARGET_STRUCT_VALUE_RTX 255 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx 256 #undef TARGET_SETUP_INCOMING_VARARGS 257 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs 258 #undef TARGET_PASS_BY_REFERENCE 259 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference 260 #undef TARGET_ARG_PARTIAL_BYTES 261 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes 262 #undef TARGET_FUNCTION_ARG 263 #define TARGET_FUNCTION_ARG cris_function_arg 264 #undef TARGET_FUNCTION_INCOMING_ARG 265 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg 266 #undef TARGET_FUNCTION_ARG_ADVANCE 267 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance 268 #undef TARGET_MD_ASM_ADJUST 269 #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust 270 271 #undef TARGET_CANNOT_FORCE_CONST_MEM 272 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem 273 274 #undef TARGET_FRAME_POINTER_REQUIRED 275 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required 276 277 #undef TARGET_OPTION_OVERRIDE 278 #define TARGET_OPTION_OVERRIDE cris_option_override 279 280 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE 281 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template 282 #undef TARGET_TRAMPOLINE_INIT 283 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init 284 285 #undef TARGET_FUNCTION_VALUE 286 #define TARGET_FUNCTION_VALUE cris_function_value 287 #undef TARGET_LIBCALL_VALUE 288 #define TARGET_LIBCALL_VALUE cris_libcall_value 289 #undef TARGET_FUNCTION_VALUE_REGNO_P 290 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p 291 292 #undef TARGET_HARD_REGNO_NREGS 293 #define TARGET_HARD_REGNO_NREGS cris_hard_regno_nregs 294 #undef TARGET_HARD_REGNO_MODE_OK 295 #define TARGET_HARD_REGNO_MODE_OK cris_hard_regno_mode_ok 296 297 #undef TARGET_STATIC_RTX_ALIGNMENT 298 #define TARGET_STATIC_RTX_ALIGNMENT cris_static_rtx_alignment 299 #undef TARGET_CONSTANT_ALIGNMENT 300 #define TARGET_CONSTANT_ALIGNMENT cris_constant_alignment 301 302 struct gcc_target targetm = TARGET_INITIALIZER; 303 304 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */ 305 306 bool 307 cris_movem_load_rest_p (rtx op, int offs) 308 { 309 unsigned int reg_count = XVECLEN (op, 0) - offs; 310 rtx src_addr; 311 int i; 312 rtx elt; 313 int setno; 314 int regno_dir = 1; 315 unsigned int regno = 0; 316 317 /* Perform a quick check so we don't blow up below. FIXME: Adjust for 318 other than (MEM reg). */ 319 if (reg_count <= 1 320 || GET_CODE (XVECEXP (op, 0, offs)) != SET 321 || !REG_P (SET_DEST (XVECEXP (op, 0, offs))) 322 || !MEM_P (SET_SRC (XVECEXP (op, 0, offs)))) 323 return false; 324 325 /* Check a possible post-inc indicator. */ 326 if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS) 327 { 328 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0); 329 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1); 330 331 reg_count--; 332 333 if (reg_count == 1 334 || !REG_P (reg) 335 || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1))) 336 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1))) 337 || !CONST_INT_P (inc) 338 || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4) 339 return false; 340 i = offs + 2; 341 } 342 else 343 i = offs + 1; 344 345 if (!TARGET_V32) 346 { 347 regno_dir = -1; 348 regno = reg_count - 1; 349 } 350 351 elt = XVECEXP (op, 0, offs); 352 src_addr = XEXP (SET_SRC (elt), 0); 353 354 if (GET_CODE (elt) != SET 355 || !REG_P (SET_DEST (elt)) 356 || GET_MODE (SET_DEST (elt)) != SImode 357 || REGNO (SET_DEST (elt)) != regno 358 || !MEM_P (SET_SRC (elt)) 359 || GET_MODE (SET_SRC (elt)) != SImode 360 || !memory_address_p (SImode, src_addr)) 361 return false; 362 363 for (setno = 1; i < XVECLEN (op, 0); setno++, i++) 364 { 365 rtx elt = XVECEXP (op, 0, i); 366 regno += regno_dir; 367 368 if (GET_CODE (elt) != SET 369 || !REG_P (SET_DEST (elt)) 370 || GET_MODE (SET_DEST (elt)) != SImode 371 || REGNO (SET_DEST (elt)) != regno 372 || !MEM_P (SET_SRC (elt)) 373 || GET_MODE (SET_SRC (elt)) != SImode 374 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS 375 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) 376 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1)) 377 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4) 378 return false; 379 } 380 381 return true; 382 } 383 384 /* Worker function for predicate for the parallel contents in a movem 385 to-memory. */ 386 387 bool 388 cris_store_multiple_op_p (rtx op) 389 { 390 int reg_count = XVECLEN (op, 0); 391 rtx dest; 392 rtx dest_addr; 393 rtx dest_base; 394 int i; 395 rtx elt; 396 int setno; 397 int regno_dir = 1; 398 int regno = 0; 399 int offset = 0; 400 401 /* Perform a quick check so we don't blow up below. FIXME: Adjust for 402 other than (MEM reg) and (MEM (PLUS reg const)). */ 403 if (reg_count <= 1) 404 return false; 405 406 elt = XVECEXP (op, 0, 0); 407 408 if (GET_CODE (elt) != SET) 409 return false; 410 411 dest = SET_DEST (elt); 412 413 if (!REG_P (SET_SRC (elt)) || !MEM_P (dest)) 414 return false; 415 416 dest_addr = XEXP (dest, 0); 417 418 /* Check a possible post-inc indicator. */ 419 if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS) 420 { 421 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0); 422 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1); 423 424 reg_count--; 425 426 if (reg_count == 1 427 || !REG_P (reg) 428 || !REG_P (SET_DEST (XVECEXP (op, 0, 1))) 429 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1))) 430 || !CONST_INT_P (inc) 431 /* Support increment by number of registers, and by the offset 432 of the destination, if it has the form (MEM (PLUS reg 433 offset)). */ 434 || !((REG_P (dest_addr) 435 && REGNO (dest_addr) == REGNO (reg) 436 && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4) 437 || (GET_CODE (dest_addr) == PLUS 438 && REG_P (XEXP (dest_addr, 0)) 439 && REGNO (XEXP (dest_addr, 0)) == REGNO (reg) 440 && CONST_INT_P (XEXP (dest_addr, 1)) 441 && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc)))) 442 return false; 443 444 i = 2; 445 } 446 else 447 i = 1; 448 449 if (!TARGET_V32) 450 { 451 regno_dir = -1; 452 regno = reg_count - 1; 453 } 454 455 if (GET_CODE (elt) != SET 456 || !REG_P (SET_SRC (elt)) 457 || GET_MODE (SET_SRC (elt)) != SImode 458 || REGNO (SET_SRC (elt)) != (unsigned int) regno 459 || !MEM_P (SET_DEST (elt)) 460 || GET_MODE (SET_DEST (elt)) != SImode) 461 return false; 462 463 if (REG_P (dest_addr)) 464 { 465 dest_base = dest_addr; 466 offset = 0; 467 } 468 else if (GET_CODE (dest_addr) == PLUS 469 && REG_P (XEXP (dest_addr, 0)) 470 && CONST_INT_P (XEXP (dest_addr, 1))) 471 { 472 dest_base = XEXP (dest_addr, 0); 473 offset = INTVAL (XEXP (dest_addr, 1)); 474 } 475 else 476 return false; 477 478 for (setno = 1; i < XVECLEN (op, 0); setno++, i++) 479 { 480 rtx elt = XVECEXP (op, 0, i); 481 regno += regno_dir; 482 483 if (GET_CODE (elt) != SET 484 || !REG_P (SET_SRC (elt)) 485 || GET_MODE (SET_SRC (elt)) != SImode 486 || REGNO (SET_SRC (elt)) != (unsigned int) regno 487 || !MEM_P (SET_DEST (elt)) 488 || GET_MODE (SET_DEST (elt)) != SImode 489 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS 490 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base) 491 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1)) 492 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset) 493 return false; 494 } 495 496 return true; 497 } 498 499 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */ 500 501 static void 502 cris_conditional_register_usage (void) 503 { 504 /* FIXME: This isn't nice. We should be able to use that register for 505 something else if the PIC table isn't needed. */ 506 if (flag_pic) 507 fixed_regs[PIC_OFFSET_TABLE_REGNUM] 508 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; 509 510 /* Allow use of ACR (PC in pre-V32) and tweak order. */ 511 if (TARGET_V32) 512 { 513 static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32; 514 unsigned int i; 515 516 fixed_regs[CRIS_ACR_REGNUM] = 0; 517 518 for (i = 0; 519 i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]); 520 i++) 521 reg_alloc_order[i] = reg_alloc_order_v32[i]; 522 } 523 524 if (TARGET_HAS_MUL_INSNS) 525 fixed_regs[CRIS_MOF_REGNUM] = 0; 526 527 /* On early versions, we must use the 16-bit condition-code register, 528 which has another name. */ 529 if (cris_cpu_version < 8) 530 reg_names[CRIS_CC0_REGNUM] = "ccr"; 531 } 532 533 /* Return crtl->uses_pic_offset_table. For use in cris.md, 534 since some generated files do not include function.h. */ 535 536 int 537 cris_cfun_uses_pic_table (void) 538 { 539 return crtl->uses_pic_offset_table; 540 } 541 542 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM. 543 We can't put PIC addresses in the constant pool, not even the ones that 544 can be reached as pc-relative as we can't tell when or how to do that. */ 545 546 static bool 547 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 548 { 549 enum cris_symbol_type t = cris_symbol_type_of (x); 550 551 return 552 t == cris_unspec 553 || t == cris_got_symbol 554 || t == cris_rel_symbol; 555 } 556 557 /* Given an rtx, return the text string corresponding to the CODE of X. 558 Intended for use in the assembly language output section of a 559 define_insn. */ 560 561 const char * 562 cris_op_str (rtx x) 563 { 564 cris_output_insn_is_bound = 0; 565 switch (GET_CODE (x)) 566 { 567 case PLUS: 568 return "add"; 569 570 case MINUS: 571 return "sub"; 572 573 case MULT: 574 /* This function is for retrieving a part of an instruction name for 575 an operator, for immediate output. If that ever happens for 576 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure 577 we notice. */ 578 internal_error ("MULT case in cris_op_str"); 579 break; 580 581 case DIV: 582 return "div"; 583 584 case AND: 585 return "and"; 586 587 case IOR: 588 return "or"; 589 590 case XOR: 591 return "xor"; 592 593 case NOT: 594 return "not"; 595 596 case ASHIFT: 597 return "lsl"; 598 599 case LSHIFTRT: 600 return "lsr"; 601 602 case ASHIFTRT: 603 return "asr"; 604 605 case UMIN: 606 /* Used to control the sign/zero-extend character for the 'E' modifier. 607 BOUND has none. */ 608 cris_output_insn_is_bound = 1; 609 return "bound"; 610 611 default: 612 return "Unknown operator"; 613 } 614 } 615 616 /* Emit an error message when we're in an asm, and a fatal error for 617 "normal" insns. Formatted output isn't easily implemented, since we 618 use output_operand_lossage to output the actual message and handle the 619 categorization of the error. */ 620 621 static void 622 cris_operand_lossage (const char *msgid, rtx op) 623 { 624 debug_rtx (op); 625 output_operand_lossage ("%s", msgid); 626 } 627 628 /* Print an index part of an address to file. */ 629 630 static void 631 cris_print_index (rtx index, FILE *file) 632 { 633 /* Make the index "additive" unless we'll output a negative number, in 634 which case the sign character is free (as in free beer). */ 635 if (!CONST_INT_P (index) || INTVAL (index) >= 0) 636 putc ('+', file); 637 638 if (REG_P (index)) 639 fprintf (file, "$%s.b", reg_names[REGNO (index)]); 640 else if (CRIS_CONSTANT_P (index)) 641 cris_output_addr_const (file, index); 642 else if (GET_CODE (index) == MULT) 643 { 644 fprintf (file, "$%s.", 645 reg_names[REGNO (XEXP (index, 0))]); 646 647 putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file); 648 } 649 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0))) 650 { 651 rtx inner = XEXP (index, 0); 652 rtx inner_inner = XEXP (inner, 0); 653 654 if (GET_CODE (inner_inner) == POST_INC) 655 { 656 fprintf (file, "[$%s+].", 657 reg_names[REGNO (XEXP (inner_inner, 0))]); 658 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); 659 } 660 else 661 { 662 fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]); 663 664 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file); 665 } 666 } 667 else if (MEM_P (index)) 668 { 669 rtx inner = XEXP (index, 0); 670 if (GET_CODE (inner) == POST_INC) 671 fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]); 672 else 673 fprintf (file, "[$%s].d", reg_names[REGNO (inner)]); 674 } 675 else 676 cris_operand_lossage ("unexpected index-type in cris_print_index", 677 index); 678 } 679 680 /* Print a base rtx of an address to file. */ 681 682 static void 683 cris_print_base (rtx base, FILE *file) 684 { 685 if (REG_P (base)) 686 fprintf (file, "$%s", reg_names[REGNO (base)]); 687 else if (GET_CODE (base) == POST_INC) 688 { 689 gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM); 690 fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]); 691 } 692 else 693 cris_operand_lossage ("unexpected base-type in cris_print_base", 694 base); 695 } 696 697 /* Usable as a guard in expressions. */ 698 699 int 700 cris_fatal (char *arg) 701 { 702 internal_error (arg); 703 704 /* We'll never get here; this is just to appease compilers. */ 705 return 0; 706 } 707 708 /* Return nonzero if REGNO is an ordinary register that *needs* to be 709 saved together with other registers, possibly by a MOVEM instruction, 710 or is saved for target-independent reasons. There may be 711 target-dependent reasons to save the register anyway; this is just a 712 wrapper for a complicated conditional. */ 713 714 static int 715 cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used) 716 { 717 return 718 (((df_regs_ever_live_p (regno) 719 && !call_used_or_fixed_reg_p (regno)) 720 || (regno == PIC_OFFSET_TABLE_REGNUM 721 && (got_really_used 722 /* It is saved anyway, if there would be a gap. */ 723 || (flag_pic 724 && df_regs_ever_live_p (regno + 1) 725 && !call_used_or_fixed_reg_p (regno + 1))))) 726 && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed) 727 && regno != CRIS_SRP_REGNUM) 728 || (crtl->calls_eh_return 729 && (regno == EH_RETURN_DATA_REGNO (0) 730 || regno == EH_RETURN_DATA_REGNO (1) 731 || regno == EH_RETURN_DATA_REGNO (2) 732 || regno == EH_RETURN_DATA_REGNO (3))); 733 } 734 735 /* The PRINT_OPERAND worker. */ 736 737 static void 738 cris_print_operand (FILE *file, rtx x, int code) 739 { 740 rtx operand = x; 741 742 /* Size-strings corresponding to MULT expressions. */ 743 static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" }; 744 745 /* New code entries should just be added to the switch below. If 746 handling is finished, just return. If handling was just a 747 modification of the operand, the modified operand should be put in 748 "operand", and then do a break to let default handling 749 (zero-modifier) output the operand. */ 750 751 switch (code) 752 { 753 case 'b': 754 /* Print the unsigned supplied integer as if it were signed 755 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */ 756 if (!satisfies_constraint_O (x)) 757 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x); 758 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 759 INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535)); 760 return; 761 762 case 'x': 763 /* Print assembler code for operator. */ 764 fprintf (file, "%s", cris_op_str (operand)); 765 return; 766 767 case 'o': 768 { 769 /* A movem modifier working on a parallel; output the register 770 name. */ 771 int regno; 772 773 if (GET_CODE (x) != PARALLEL) 774 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x); 775 776 /* The second item can be (set reg (plus reg const)) to denote a 777 postincrement. */ 778 regno 779 = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS 780 ? XVECLEN (x, 0) - 2 781 : XVECLEN (x, 0) - 1); 782 783 fprintf (file, "$%s", reg_names [regno]); 784 } 785 return; 786 787 case 'O': 788 { 789 /* A similar movem modifier; output the memory operand. */ 790 rtx addr; 791 792 if (GET_CODE (x) != PARALLEL) 793 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x); 794 795 /* The lowest mem operand is in the first item, but perhaps it 796 needs to be output as postincremented. */ 797 addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0))) 798 ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0) 799 : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0); 800 801 /* The second item can be a (set reg (plus reg const)) to denote 802 a modification. */ 803 if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS) 804 { 805 /* It's a post-increment, if the address is a naked (reg). */ 806 if (REG_P (addr)) 807 addr = gen_rtx_POST_INC (SImode, addr); 808 else 809 { 810 /* Otherwise, it's a side-effect; RN=RN+M. */ 811 fprintf (file, "[$%s=$%s%s%d]", 812 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))], 813 reg_names [REGNO (XEXP (addr, 0))], 814 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+", 815 (int) INTVAL (XEXP (addr, 1))); 816 return; 817 } 818 } 819 output_address (VOIDmode, addr); 820 } 821 return; 822 823 case 'p': 824 /* Adjust a power of two to its log2. */ 825 if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 ) 826 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x); 827 fprintf (file, "%d", exact_log2 (INTVAL (x))); 828 return; 829 830 case 's': 831 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535 832 respectively. This modifier also terminates the inhibiting 833 effects of the 'x' modifier. */ 834 cris_output_insn_is_bound = 0; 835 if (GET_MODE (x) == VOIDmode && CONST_INT_P (x)) 836 { 837 if (INTVAL (x) >= 0) 838 { 839 if (INTVAL (x) <= 255) 840 putc ('b', file); 841 else if (INTVAL (x) <= 65535) 842 putc ('w', file); 843 else 844 putc ('d', file); 845 } 846 else 847 putc ('d', file); 848 return; 849 } 850 851 /* For a non-integer, print the size of the operand. */ 852 putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode) 853 ? 'd' : GET_MODE (x) == HImode ? 'w' 854 : GET_MODE (x) == QImode ? 'b' 855 /* If none of the above, emit an erroneous size letter. */ 856 : 'X', 857 file); 858 return; 859 860 case 'z': 861 /* Const_int: print b for -127 <= x <= 255, 862 w for -32768 <= x <= 65535, else die. */ 863 if (!CONST_INT_P (x) 864 || INTVAL (x) < -32768 || INTVAL (x) > 65535) 865 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x); 866 putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file); 867 return; 868 869 case 'Z': 870 /* If this is a GOT-symbol, print the size-letter corresponding to 871 -fpic/-fPIC. For everything else, print "d". */ 872 putc ((flag_pic == 1 873 && GET_CODE (x) == CONST 874 && GET_CODE (XEXP (x, 0)) == UNSPEC 875 && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD) 876 ? 'w' : 'd', file); 877 return; 878 879 case '#': 880 /* Output a 'nop' if there's nothing for the delay slot. 881 This method stolen from the sparc files. */ 882 if (dbr_sequence_length () == 0) 883 fputs ("\n\tnop", file); 884 return; 885 886 case '!': 887 /* Output directive for alignment padded with "nop" insns. 888 Optimizing for size, it's plain 4-byte alignment, otherwise we 889 align the section to a cache-line (32 bytes) and skip at max 2 890 bytes, i.e. we skip if it's the last insn on a cache-line. The 891 latter is faster by a small amount (for two test-programs 99.6% 892 and 99.9%) and larger by a small amount (ditto 100.1% and 893 100.2%). This is supposed to be the simplest yet performance- 894 wise least intrusive way to make sure the immediately following 895 (supposed) muls/mulu insn isn't located at the end of a 896 cache-line. */ 897 if (TARGET_MUL_BUG) 898 fputs (optimize_size 899 ? ".p2alignw 2,0x050f\n\t" 900 : ".p2alignw 5,0x050f,2\n\t", file); 901 return; 902 903 case ':': 904 /* The PIC register. */ 905 if (! flag_pic) 906 internal_error ("invalid use of %<:%> modifier"); 907 fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]); 908 return; 909 910 case 'H': 911 /* Print high (most significant) part of something. */ 912 switch (GET_CODE (operand)) 913 { 914 case CONST_INT: 915 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode) 916 value is kept here, and so may be other than 0 or -1. */ 917 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 918 INTVAL (operand_subword (operand, 1, 0, DImode))); 919 return; 920 921 case CONST_DOUBLE: 922 /* High part of a long long constant. */ 923 if (GET_MODE (operand) == VOIDmode) 924 { 925 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x)); 926 return; 927 } 928 else 929 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); 930 931 case REG: 932 /* Print reg + 1. Check that there's not an attempt to print 933 high-parts of registers like stack-pointer or higher, except 934 for SRP (where the "high part" is MOF). */ 935 if (REGNO (operand) > STACK_POINTER_REGNUM - 2 936 && (REGNO (operand) != CRIS_SRP_REGNUM 937 || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM 938 || fixed_regs[CRIS_MOF_REGNUM] != 0)) 939 LOSE_AND_RETURN ("bad register", operand); 940 fprintf (file, "$%s", reg_names[REGNO (operand) + 1]); 941 return; 942 943 case MEM: 944 /* Adjust memory address to high part. */ 945 { 946 rtx adj_mem = operand; 947 int size 948 = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT; 949 950 /* Adjust so we can use two SImode in DImode. 951 Calling adj_offsettable_operand will make sure it is an 952 offsettable address. Don't do this for a postincrement 953 though; it should remain as it was. */ 954 if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC) 955 adj_mem 956 = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2); 957 958 output_address (VOIDmode, XEXP (adj_mem, 0)); 959 return; 960 } 961 962 default: 963 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x); 964 } 965 966 case 'L': 967 /* Strip the MEM expression. */ 968 operand = XEXP (operand, 0); 969 break; 970 971 case 'e': 972 /* Like 'E', but ignore state set by 'x'. FIXME: Use code 973 iterators and attributes in cris.md to avoid the need for %x 974 and %E (and %e) and state passed between those modifiers. */ 975 cris_output_insn_is_bound = 0; 976 /* FALL THROUGH. */ 977 case 'E': 978 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless 979 cris_output_insn_is_bound is nonzero. */ 980 if (GET_CODE (operand) != SIGN_EXTEND 981 && GET_CODE (operand) != ZERO_EXTEND 982 && !CONST_INT_P (operand)) 983 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x); 984 985 if (cris_output_insn_is_bound) 986 { 987 cris_output_insn_is_bound = 0; 988 return; 989 } 990 991 putc (GET_CODE (operand) == SIGN_EXTEND 992 || (CONST_INT_P (operand) && INTVAL (operand) < 0) 993 ? 's' : 'u', file); 994 return; 995 996 case 'm': 997 /* Print the size letter of the inner element. We can do it by 998 calling ourselves with the 's' modifier. */ 999 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND) 1000 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x); 1001 cris_print_operand (file, XEXP (operand, 0), 's'); 1002 return; 1003 1004 case 'M': 1005 /* Print the least significant part of operand. */ 1006 if (GET_CODE (operand) == CONST_DOUBLE) 1007 { 1008 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x)); 1009 return; 1010 } 1011 else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand)) 1012 { 1013 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 1014 INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1)); 1015 return; 1016 } 1017 /* Otherwise the least significant part equals the normal part, 1018 so handle it normally. */ 1019 break; 1020 1021 case 'A': 1022 /* When emitting an add for the high part of a DImode constant, we 1023 want to use addq for 0 and adds.w for -1. */ 1024 if (!CONST_INT_P (operand)) 1025 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x); 1026 fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq"); 1027 return; 1028 1029 case 'P': 1030 /* For const_int operands, print the additive mnemonic and the 1031 modified operand (byte-sized operands don't save anything): 1032 N=MIN_INT..-65536: add.d N 1033 -65535..-64: subu.w -N 1034 -63..-1: subq -N 1035 0..63: addq N 1036 64..65535: addu.w N 1037 65536..MAX_INT: add.d N. 1038 (Emitted mnemonics are capitalized to simplify testing.) 1039 For anything else (N.B: only register is valid), print "add.d". */ 1040 if (REG_P (operand)) 1041 { 1042 fprintf (file, "Add.d "); 1043 1044 /* Deal with printing the operand by dropping through to the 1045 normal path. */ 1046 break; 1047 } 1048 else 1049 { 1050 int val; 1051 gcc_assert (CONST_INT_P (operand)); 1052 1053 val = INTVAL (operand); 1054 if (!IN_RANGE (val, -65535, 65535)) 1055 fprintf (file, "Add.d %d", val); 1056 else if (val <= -64) 1057 fprintf (file, "Subu.w %d", -val); 1058 else if (val <= -1) 1059 fprintf (file, "Subq %d", -val); 1060 else if (val <= 63) 1061 fprintf (file, "Addq %d", val); 1062 else if (val <= 65535) 1063 fprintf (file, "Addu.w %d", val); 1064 return; 1065 } 1066 break; 1067 1068 case 'q': 1069 /* If the operand is an integer -31..31, print "q" else ".d". */ 1070 if (CONST_INT_P (operand) && IN_RANGE (INTVAL (operand), -31, 31)) 1071 fprintf (file, "q"); 1072 else 1073 fprintf (file, ".d"); 1074 return; 1075 1076 case 'd': 1077 /* If this is a GOT symbol, force it to be emitted as :GOT and 1078 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16). 1079 Avoid making this too much of a special case. */ 1080 if (flag_pic == 1 && CRIS_CONSTANT_P (operand)) 1081 { 1082 int flag_pic_save = flag_pic; 1083 1084 flag_pic = 2; 1085 cris_output_addr_const (file, operand); 1086 flag_pic = flag_pic_save; 1087 return; 1088 } 1089 break; 1090 1091 case 'D': 1092 /* When emitting an sub for the high part of a DImode constant, we 1093 want to use subq for 0 and subs.w for -1. */ 1094 if (!CONST_INT_P (operand)) 1095 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x); 1096 fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq"); 1097 return; 1098 1099 case 'S': 1100 /* Print the operand as the index-part of an address. 1101 Easiest way out is to use cris_print_index. */ 1102 cris_print_index (operand, file); 1103 return; 1104 1105 case 'T': 1106 /* Print the size letter for an operand to a MULT, which must be a 1107 const_int with a suitable value. */ 1108 if (!CONST_INT_P (operand) || INTVAL (operand) > 4) 1109 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x); 1110 fprintf (file, "%s", mults[INTVAL (operand)]); 1111 return; 1112 1113 case 'u': 1114 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */ 1115 if (flag_pic == 1 1116 && GET_CODE (operand) == CONST 1117 && GET_CODE (XEXP (operand, 0)) == UNSPEC 1118 && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD) 1119 fprintf (file, "u.w"); 1120 else 1121 fprintf (file, ".d"); 1122 return; 1123 1124 case 0: 1125 /* No code, print as usual. */ 1126 break; 1127 1128 default: 1129 LOSE_AND_RETURN ("invalid operand modifier letter", x); 1130 } 1131 1132 /* Print an operand as without a modifier letter. */ 1133 switch (GET_CODE (operand)) 1134 { 1135 case REG: 1136 if (REGNO (operand) > 15 1137 && REGNO (operand) != CRIS_MOF_REGNUM 1138 && REGNO (operand) != CRIS_SRP_REGNUM 1139 && REGNO (operand) != CRIS_CC0_REGNUM) 1140 internal_error ("internal error: bad register: %d", REGNO (operand)); 1141 fprintf (file, "$%s", reg_names[REGNO (operand)]); 1142 return; 1143 1144 case MEM: 1145 output_address (GET_MODE (operand), XEXP (operand, 0)); 1146 return; 1147 1148 case CONST_DOUBLE: 1149 if (GET_MODE (operand) == VOIDmode) 1150 /* A long long constant. */ 1151 output_addr_const (file, operand); 1152 else 1153 { 1154 /* Only single precision is allowed as plain operands the 1155 moment. */ 1156 long l; 1157 1158 /* FIXME: Perhaps check overflow of the "single". */ 1159 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operand), l); 1160 1161 fprintf (file, "0x%lx", l); 1162 } 1163 return; 1164 1165 case UNSPEC: 1166 /* Fall through. */ 1167 case CONST: 1168 cris_output_addr_const (file, operand); 1169 return; 1170 1171 case MULT: 1172 case ASHIFT: 1173 { 1174 /* For a (MULT (reg X) const_int) we output "rX.S". */ 1175 int i = CONST_INT_P (XEXP (operand, 1)) 1176 ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0)); 1177 rtx reg = CONST_INT_P (XEXP (operand, 1)) 1178 ? XEXP (operand, 0) : XEXP (operand, 1); 1179 1180 if (!REG_P (reg) 1181 || (!CONST_INT_P (XEXP (operand, 0)) 1182 && !CONST_INT_P (XEXP (operand, 1)))) 1183 LOSE_AND_RETURN ("unexpected multiplicative operand", x); 1184 1185 cris_print_base (reg, file); 1186 fprintf (file, ".%c", 1187 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b' 1188 : i == 4 ? 'd' 1189 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w' 1190 : 'd'); 1191 return; 1192 } 1193 1194 default: 1195 /* No need to handle all strange variants, let output_addr_const 1196 do it for us. */ 1197 if (CRIS_CONSTANT_P (operand)) 1198 { 1199 cris_output_addr_const (file, operand); 1200 return; 1201 } 1202 1203 LOSE_AND_RETURN ("unexpected operand", x); 1204 } 1205 } 1206 1207 static bool 1208 cris_print_operand_punct_valid_p (unsigned char code) 1209 { 1210 return (code == '#' || code == '!' || code == ':'); 1211 } 1212 1213 /* The PRINT_OPERAND_ADDRESS worker. */ 1214 1215 static void 1216 cris_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x) 1217 { 1218 /* All these were inside MEM:s so output indirection characters. */ 1219 putc ('[', file); 1220 1221 if (CONSTANT_ADDRESS_P (x)) 1222 cris_output_addr_const (file, x); 1223 else if (cris_base_or_autoincr_p (x, true)) 1224 cris_print_base (x, file); 1225 else if (GET_CODE (x) == PLUS) 1226 { 1227 rtx x1, x2; 1228 1229 x1 = XEXP (x, 0); 1230 x2 = XEXP (x, 1); 1231 if (cris_base_p (x1, true)) 1232 { 1233 cris_print_base (x1, file); 1234 cris_print_index (x2, file); 1235 } 1236 else if (cris_base_p (x2, true)) 1237 { 1238 cris_print_base (x2, file); 1239 cris_print_index (x1, file); 1240 } 1241 else 1242 LOSE_AND_RETURN ("unrecognized address", x); 1243 } 1244 else if (MEM_P (x)) 1245 { 1246 /* A DIP. Output more indirection characters. */ 1247 putc ('[', file); 1248 cris_print_base (XEXP (x, 0), file); 1249 putc (']', file); 1250 } 1251 else 1252 LOSE_AND_RETURN ("unrecognized address", x); 1253 1254 putc (']', file); 1255 } 1256 1257 /* The RETURN_ADDR_RTX worker. 1258 We mark that the return address is used, either by EH or 1259 __builtin_return_address, for use by the function prologue and 1260 epilogue. FIXME: This isn't optimal; we just use the mark in the 1261 prologue and epilogue to say that the return address is to be stored 1262 in the stack frame. We could return SRP for leaf-functions and use the 1263 initial-value machinery. */ 1264 1265 rtx 1266 cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED) 1267 { 1268 cfun->machine->needs_return_address_on_stack = 1; 1269 1270 /* The return-address is stored just above the saved frame-pointer (if 1271 present). Apparently we can't eliminate from the frame-pointer in 1272 that direction, so use the incoming args (maybe pretended) pointer. */ 1273 return count == 0 1274 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, virtual_incoming_args_rtx, -4)) 1275 : NULL_RTX; 1276 } 1277 1278 /* Accessor used in cris.md:return because cfun->machine isn't available 1279 there. */ 1280 1281 bool 1282 cris_return_address_on_stack (void) 1283 { 1284 return df_regs_ever_live_p (CRIS_SRP_REGNUM) 1285 || cfun->machine->needs_return_address_on_stack; 1286 } 1287 1288 /* Accessor used in cris.md:return because cfun->machine isn't available 1289 there. */ 1290 1291 bool 1292 cris_return_address_on_stack_for_return (void) 1293 { 1294 return cfun->machine->return_type == CRIS_RETINSN_RET ? false 1295 : cris_return_address_on_stack (); 1296 } 1297 1298 /* This handles FP -> SP elimination offset. */ 1299 1300 static int 1301 cris_initial_frame_pointer_offset (void) 1302 { 1303 int regno; 1304 1305 /* Initial offset is 0 if we don't have a frame pointer. */ 1306 int offs = 0; 1307 bool got_really_used = false; 1308 1309 if (crtl->uses_pic_offset_table) 1310 { 1311 push_topmost_sequence (); 1312 got_really_used 1313 = reg_used_between_p (pic_offset_table_rtx, get_insns (), 1314 NULL); 1315 pop_topmost_sequence (); 1316 } 1317 1318 /* And 4 for each register pushed. */ 1319 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 1320 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 1321 offs += 4; 1322 1323 /* And then, last, we add the locals allocated. */ 1324 offs += get_frame_size (); 1325 1326 /* And more; the accumulated args size. */ 1327 offs += crtl->outgoing_args_size; 1328 1329 /* Then round it off, in case we use aligned stack. */ 1330 if (TARGET_STACK_ALIGN) 1331 offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1; 1332 1333 return offs; 1334 } 1335 1336 /* The INITIAL_ELIMINATION_OFFSET worker. 1337 Calculate the difference between imaginary registers such as frame 1338 pointer and the stack pointer. Used to eliminate the frame pointer 1339 and imaginary arg pointer. */ 1340 1341 int 1342 cris_initial_elimination_offset (int fromreg, int toreg) 1343 { 1344 int fp_sp_offset 1345 = cris_initial_frame_pointer_offset (); 1346 1347 /* We should be able to use regs_ever_live and related prologue 1348 information here, or alpha should not as well. */ 1349 bool return_address_on_stack = cris_return_address_on_stack (); 1350 1351 /* Here we act as if the frame-pointer were needed. */ 1352 int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0); 1353 1354 if (fromreg == ARG_POINTER_REGNUM 1355 && toreg == FRAME_POINTER_REGNUM) 1356 return ap_fp_offset; 1357 1358 /* Between the frame pointer and the stack are only "normal" stack 1359 variables and saved registers. */ 1360 if (fromreg == FRAME_POINTER_REGNUM 1361 && toreg == STACK_POINTER_REGNUM) 1362 return fp_sp_offset; 1363 1364 /* We need to balance out the frame pointer here. */ 1365 if (fromreg == ARG_POINTER_REGNUM 1366 && toreg == STACK_POINTER_REGNUM) 1367 return ap_fp_offset + fp_sp_offset - 4; 1368 1369 gcc_unreachable (); 1370 } 1371 1372 /* Nonzero if X is a hard reg that can be used as an index. */ 1373 static inline bool 1374 reg_ok_for_base_p (const_rtx x, bool strict) 1375 { 1376 return ((! strict && ! HARD_REGISTER_P (x)) 1377 || REGNO_OK_FOR_BASE_P (REGNO (x))); 1378 } 1379 1380 /* Nonzero if X is a hard reg that can be used as an index. */ 1381 static inline bool 1382 reg_ok_for_index_p (const_rtx x, bool strict) 1383 { 1384 return reg_ok_for_base_p (x, strict); 1385 } 1386 1387 /* No symbol can be used as an index (or more correct, as a base) together 1388 with a register with PIC; the PIC register must be there. */ 1389 1390 bool 1391 cris_constant_index_p (const_rtx x) 1392 { 1393 return (CRIS_CONSTANT_P (x) && (!flag_pic || cris_valid_pic_const (x, true))); 1394 } 1395 1396 /* True if X is a valid base register. */ 1397 1398 bool 1399 cris_base_p (const_rtx x, bool strict) 1400 { 1401 return (REG_P (x) && reg_ok_for_base_p (x, strict)); 1402 } 1403 1404 /* True if X is a valid index register. */ 1405 1406 static inline bool 1407 cris_index_p (const_rtx x, bool strict) 1408 { 1409 return (REG_P (x) && reg_ok_for_index_p (x, strict)); 1410 } 1411 1412 /* True if X is a valid base register with or without autoincrement. */ 1413 1414 bool 1415 cris_base_or_autoincr_p (const_rtx x, bool strict) 1416 { 1417 return (cris_base_p (x, strict) 1418 || (GET_CODE (x) == POST_INC 1419 && cris_base_p (XEXP (x, 0), strict) 1420 && REGNO (XEXP (x, 0)) != CRIS_ACR_REGNUM)); 1421 } 1422 1423 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */ 1424 1425 bool 1426 cris_bdap_index_p (const_rtx x, bool strict) 1427 { 1428 return ((MEM_P (x) 1429 && GET_MODE (x) == SImode 1430 && cris_base_or_autoincr_p (XEXP (x, 0), strict)) 1431 || (GET_CODE (x) == SIGN_EXTEND 1432 && MEM_P (XEXP (x, 0)) 1433 && (GET_MODE (XEXP (x, 0)) == HImode 1434 || GET_MODE (XEXP (x, 0)) == QImode) 1435 && cris_base_or_autoincr_p (XEXP (XEXP (x, 0), 0), strict))); 1436 } 1437 1438 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */ 1439 1440 bool 1441 cris_biap_index_p (const_rtx x, bool strict) 1442 { 1443 return (cris_index_p (x, strict) 1444 || (GET_CODE (x) == MULT 1445 && cris_index_p (XEXP (x, 0), strict) 1446 && cris_scale_int_operand (XEXP (x, 1), VOIDmode))); 1447 } 1448 1449 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P. 1450 1451 A PIC operand looks like a normal symbol here. At output we dress it 1452 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local 1453 symbol) so we exclude all addressing modes where we can't replace a 1454 plain "symbol" with that. A global PIC symbol does not fit anywhere 1455 here (but is thankfully a general_operand in itself). A local PIC 1456 symbol is valid for the plain "symbol + offset" case. */ 1457 1458 bool 1459 cris_legitimate_address_p (machine_mode mode, rtx x, bool strict) 1460 { 1461 const_rtx x1, x2; 1462 1463 if (cris_base_or_autoincr_p (x, strict)) 1464 return true; 1465 else if (TARGET_V32) 1466 /* Nothing else is valid then. */ 1467 return false; 1468 else if (cris_constant_index_p (x)) 1469 return true; 1470 /* Indexed? */ 1471 else if (GET_CODE (x) == PLUS) 1472 { 1473 x1 = XEXP (x, 0); 1474 x2 = XEXP (x, 1); 1475 /* BDAP o, Rd. */ 1476 if ((cris_base_p (x1, strict) && cris_constant_index_p (x2)) 1477 || (cris_base_p (x2, strict) && cris_constant_index_p (x1)) 1478 /* BDAP Rs[+], Rd. */ 1479 || (GET_MODE_SIZE (mode) <= UNITS_PER_WORD 1480 && ((cris_base_p (x1, strict) 1481 && cris_bdap_index_p (x2, strict)) 1482 || (cris_base_p (x2, strict) 1483 && cris_bdap_index_p (x1, strict)) 1484 /* BIAP.m Rs, Rd */ 1485 || (cris_base_p (x1, strict) 1486 && cris_biap_index_p (x2, strict)) 1487 || (cris_base_p (x2, strict) 1488 && cris_biap_index_p (x1, strict))))) 1489 return true; 1490 } 1491 else if (MEM_P (x)) 1492 { 1493 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */ 1494 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD 1495 && cris_base_or_autoincr_p (XEXP (x, 0), strict)) 1496 return true; 1497 } 1498 1499 return false; 1500 } 1501 1502 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle 1503 PIC constants that aren't legitimized. FIXME: there used to be a 1504 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle 1505 PIC constants, but no more (4.7 era); testcase: glibc init-first.c. 1506 While that may be seen as a bug, that guarantee seems a wart by design, 1507 so don't bother; fix the documentation instead. */ 1508 1509 bool 1510 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 1511 { 1512 enum cris_symbol_type t; 1513 1514 if (flag_pic) 1515 return LEGITIMATE_PIC_OPERAND_P (x); 1516 1517 t = cris_symbol_type_of (x); 1518 1519 return 1520 t == cris_no_symbol 1521 || t == cris_offsettable_symbol 1522 || t == cris_unspec; 1523 } 1524 1525 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */ 1526 1527 bool 1528 cris_reload_address_legitimized (rtx x, 1529 machine_mode mode ATTRIBUTE_UNUSED, 1530 int opnum ATTRIBUTE_UNUSED, 1531 int itype, 1532 int ind_levels ATTRIBUTE_UNUSED) 1533 { 1534 enum reload_type type = (enum reload_type) itype; 1535 rtx op0, op1; 1536 rtx *op1p; 1537 1538 if (GET_CODE (x) != PLUS) 1539 return false; 1540 1541 if (TARGET_V32) 1542 return false; 1543 1544 op0 = XEXP (x, 0); 1545 op1 = XEXP (x, 1); 1546 op1p = &XEXP (x, 1); 1547 1548 if (!REG_P (op1)) 1549 return false; 1550 1551 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0))) 1552 { 1553 rtx op00 = XEXP (op0, 0); 1554 rtx op000 = XEXP (op00, 0); 1555 rtx *op000p = &XEXP (op00, 0); 1556 1557 if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode) 1558 && (REG_P (op000) 1559 || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0))))) 1560 { 1561 bool something_reloaded = false; 1562 1563 if (GET_CODE (op000) == POST_INC 1564 && REG_P (XEXP (op000, 0)) 1565 && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER) 1566 /* No, this gets too complicated and is too rare to care 1567 about trying to improve on the general code Here. 1568 As the return-value is an all-or-nothing indicator, we 1569 punt on the other register too. */ 1570 return false; 1571 1572 if ((REG_P (op000) 1573 && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER)) 1574 { 1575 /* The address of the inner mem is a pseudo or wrong 1576 reg: reload that. */ 1577 push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS, 1578 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 1579 something_reloaded = true; 1580 } 1581 1582 if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER) 1583 { 1584 /* Base register is a pseudo or wrong reg: reload it. */ 1585 push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS, 1586 GET_MODE (x), VOIDmode, 0, 0, 1587 opnum, type); 1588 something_reloaded = true; 1589 } 1590 1591 gcc_assert (something_reloaded); 1592 1593 return true; 1594 } 1595 } 1596 1597 return false; 1598 } 1599 1600 1601 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. 1602 1603 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as 1604 the class for a constant (testcase: __Mul in arit.c). To avoid forcing 1605 out a constant into the constant pool, we will trap this case and 1606 return something a bit more sane. FIXME: Check if this is a bug. 1607 Beware that we must not "override" classes that can be specified as 1608 constraint letters, or else asm operands using them will fail when 1609 they need to be reloaded. FIXME: Investigate whether that constitutes 1610 a bug. */ 1611 1612 static reg_class_t 1613 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) 1614 { 1615 if (rclass != ACR_REGS 1616 && rclass != MOF_REGS 1617 && rclass != MOF_SRP_REGS 1618 && rclass != SRP_REGS 1619 && rclass != CC0_REGS 1620 && rclass != SPECIAL_REGS) 1621 return GENNONACR_REGS; 1622 1623 return rclass; 1624 } 1625 1626 /* Worker function for TARGET_REGISTER_MOVE_COST. */ 1627 1628 static int 1629 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 1630 reg_class_t from, reg_class_t to) 1631 { 1632 /* Can't move to and from a SPECIAL_REGS register, so we have to say 1633 their move cost within that class is higher. How about 7? That's 3 1634 for a move to a GENERAL_REGS register, 3 for the move from the 1635 GENERAL_REGS register, and 1 for the increased register pressure. 1636 Also, it's higher than the memory move cost, as it should. 1637 We also do this for ALL_REGS, since we don't want that class to be 1638 preferred (even to memory) at all where GENERAL_REGS doesn't fit. 1639 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't 1640 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be 1641 used when a GENERAL_REGS should be used, even if there are call-saved 1642 GENERAL_REGS left to allocate. This is because the fall-back when 1643 the most preferred register class isn't available, isn't the next 1644 (or next good) wider register class, but the *most widest* register 1645 class. FIXME: pre-IRA comment, perhaps obsolete now. */ 1646 1647 if ((reg_classes_intersect_p (from, SPECIAL_REGS) 1648 && reg_classes_intersect_p (to, SPECIAL_REGS)) 1649 || from == ALL_REGS || to == ALL_REGS) 1650 return 7; 1651 1652 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we 1653 generally prefer GENERAL_REGS. */ 1654 if (reg_classes_intersect_p (from, SPECIAL_REGS) 1655 || reg_classes_intersect_p (to, SPECIAL_REGS)) 1656 return 3; 1657 1658 return 2; 1659 } 1660 1661 /* Worker function for TARGET_MEMORY_MOVE_COST. 1662 1663 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should 1664 suffice. */ 1665 1666 static int 1667 cris_memory_move_cost (machine_mode mode, 1668 reg_class_t rclass ATTRIBUTE_UNUSED, 1669 bool in ATTRIBUTE_UNUSED) 1670 { 1671 if (mode == QImode 1672 || mode == HImode) 1673 return 4; 1674 else 1675 return 6; 1676 } 1677 1678 /* Worker for cris_notice_update_cc; handles the "normal" cases. 1679 FIXME: this code is historical; its functionality should be 1680 refactored to look at insn attributes and moved to 1681 cris_notice_update_cc. Except, we better lose cc0 entirely. */ 1682 1683 static void 1684 cris_normal_notice_update_cc (rtx exp, rtx insn) 1685 { 1686 /* "Normal" means, for: 1687 (set (cc0) (...)): 1688 CC is (...). 1689 1690 (set (reg) (...)): 1691 CC is (reg) and (...) - unless (...) is 0 or reg is a special 1692 register or (v32 and (...) is -32..-1), then CC does not change. 1693 CC_NO_OVERFLOW unless (...) is reg or mem. 1694 1695 (set (mem) (...)): 1696 CC does not change. 1697 1698 (set (pc) (...)): 1699 CC does not change. 1700 1701 (parallel 1702 (set (reg1) (mem (bdap/biap))) 1703 (set (reg2) (bdap/biap))): 1704 CC is (reg1) and (mem (reg2)) 1705 1706 (parallel 1707 (set (mem (bdap/biap)) (reg1)) [or 0] 1708 (set (reg2) (bdap/biap))): 1709 CC does not change. 1710 1711 (where reg and mem includes strict_low_parts variants thereof) 1712 1713 For all others, assume CC is clobbered. 1714 Note that we do not have to care about setting CC_NO_OVERFLOW, 1715 since the overflow flag is set to 0 (i.e. right) for 1716 instructions where it does not have any sane sense, but where 1717 other flags have meanings. (This includes shifts; the carry is 1718 not set by them). 1719 1720 Note that there are other parallel constructs we could match, 1721 but we don't do that yet. */ 1722 1723 if (GET_CODE (exp) == SET) 1724 { 1725 /* FIXME: Check when this happens. It looks like we should 1726 actually do a CC_STATUS_INIT here to be safe. */ 1727 if (SET_DEST (exp) == pc_rtx) 1728 return; 1729 1730 /* Record CC0 changes, so we do not have to output multiple 1731 test insns. */ 1732 if (SET_DEST (exp) == cc0_rtx) 1733 { 1734 CC_STATUS_INIT; 1735 1736 if (GET_CODE (SET_SRC (exp)) == COMPARE 1737 && XEXP (SET_SRC (exp), 1) == const0_rtx) 1738 cc_status.value1 = XEXP (SET_SRC (exp), 0); 1739 else 1740 cc_status.value1 = SET_SRC (exp); 1741 1742 /* Handle flags for the special btstq on one bit. */ 1743 if (GET_CODE (cc_status.value1) == ZERO_EXTRACT 1744 && XEXP (cc_status.value1, 1) == const1_rtx) 1745 { 1746 if (CONST_INT_P (XEXP (cc_status.value1, 0))) 1747 /* Using cmpq. */ 1748 cc_status.flags = CC_INVERTED; 1749 else 1750 /* A one-bit btstq. */ 1751 cc_status.flags = CC_Z_IN_NOT_N; 1752 } 1753 1754 else if (GET_CODE (SET_SRC (exp)) == COMPARE) 1755 { 1756 if (!REG_P (XEXP (SET_SRC (exp), 0)) 1757 && XEXP (SET_SRC (exp), 1) != const0_rtx) 1758 /* For some reason gcc will not canonicalize compare 1759 operations, reversing the sign by itself if 1760 operands are in wrong order. */ 1761 /* (But NOT inverted; eq is still eq.) */ 1762 cc_status.flags = CC_REVERSED; 1763 1764 /* This seems to be overlooked by gcc. FIXME: Check again. 1765 FIXME: Is it really safe? */ 1766 cc_status.value2 1767 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)), 1768 XEXP (SET_SRC (exp), 0), 1769 XEXP (SET_SRC (exp), 1)); 1770 } 1771 return; 1772 } 1773 else if (REG_P (SET_DEST (exp)) 1774 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART 1775 && REG_P (XEXP (SET_DEST (exp), 0)))) 1776 { 1777 /* A register is set; normally CC is set to show that no 1778 test insn is needed. Catch the exceptions. */ 1779 1780 /* If not to cc0, then no "set"s in non-natural mode give 1781 ok cc0... */ 1782 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD 1783 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT) 1784 { 1785 /* ... except add:s and sub:s in DImode. */ 1786 if (GET_MODE (SET_DEST (exp)) == DImode 1787 && (GET_CODE (SET_SRC (exp)) == PLUS 1788 || GET_CODE (SET_SRC (exp)) == MINUS)) 1789 { 1790 CC_STATUS_INIT; 1791 cc_status.value1 = SET_DEST (exp); 1792 cc_status.value2 = SET_SRC (exp); 1793 1794 if (cris_reg_overlap_mentioned_p (cc_status.value1, 1795 cc_status.value2)) 1796 cc_status.value2 = 0; 1797 1798 /* Add and sub may set V, which gets us 1799 unoptimizable results in "gt" and "le" condition 1800 codes. */ 1801 cc_status.flags |= CC_NO_OVERFLOW; 1802 1803 return; 1804 } 1805 } 1806 else if (SET_SRC (exp) == const0_rtx 1807 || (REG_P (SET_SRC (exp)) 1808 && (REGNO (SET_SRC (exp)) 1809 > CRIS_LAST_GENERAL_REGISTER)) 1810 || (TARGET_V32 1811 && REG_P (SET_DEST (exp)) 1812 && satisfies_constraint_I (SET_SRC (exp)))) 1813 { 1814 /* There's no CC0 change for this case. Just check 1815 for overlap. */ 1816 if (cc_status.value1 1817 && modified_in_p (cc_status.value1, insn)) 1818 cc_status.value1 = 0; 1819 1820 if (cc_status.value2 1821 && modified_in_p (cc_status.value2, insn)) 1822 cc_status.value2 = 0; 1823 1824 return; 1825 } 1826 else 1827 { 1828 CC_STATUS_INIT; 1829 cc_status.value1 = SET_DEST (exp); 1830 cc_status.value2 = SET_SRC (exp); 1831 1832 if (cris_reg_overlap_mentioned_p (cc_status.value1, 1833 cc_status.value2)) 1834 cc_status.value2 = 0; 1835 1836 /* Some operations may set V, which gets us 1837 unoptimizable results in "gt" and "le" condition 1838 codes. */ 1839 if (GET_CODE (SET_SRC (exp)) == PLUS 1840 || GET_CODE (SET_SRC (exp)) == MINUS 1841 || GET_CODE (SET_SRC (exp)) == NEG) 1842 cc_status.flags |= CC_NO_OVERFLOW; 1843 1844 /* For V32, nothing with a register destination sets 1845 C and V usefully. */ 1846 if (TARGET_V32) 1847 cc_status.flags |= CC_NO_OVERFLOW; 1848 1849 return; 1850 } 1851 } 1852 else if (MEM_P (SET_DEST (exp)) 1853 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART 1854 && MEM_P (XEXP (SET_DEST (exp), 0)))) 1855 { 1856 /* When SET to MEM, then CC is not changed (except for 1857 overlap). */ 1858 if (cc_status.value1 1859 && modified_in_p (cc_status.value1, insn)) 1860 cc_status.value1 = 0; 1861 1862 if (cc_status.value2 1863 && modified_in_p (cc_status.value2, insn)) 1864 cc_status.value2 = 0; 1865 1866 return; 1867 } 1868 } 1869 else if (GET_CODE (exp) == PARALLEL) 1870 { 1871 if (GET_CODE (XVECEXP (exp, 0, 0)) == SET 1872 && GET_CODE (XVECEXP (exp, 0, 1)) == SET 1873 && REG_P (XEXP (XVECEXP (exp, 0, 1), 0))) 1874 { 1875 if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0)) 1876 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1))) 1877 { 1878 CC_STATUS_INIT; 1879 1880 /* For "move.S [rx=ry+o],rz", say CC reflects 1881 value1=rz and value2=[rx] */ 1882 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); 1883 cc_status.value2 1884 = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1), 1885 XEXP (XVECEXP (exp, 0, 1), 0)); 1886 1887 /* Huh? A side-effect cannot change the destination 1888 register. */ 1889 if (cris_reg_overlap_mentioned_p (cc_status.value1, 1890 cc_status.value2)) 1891 internal_error ("internal error: sideeffect-insn affecting main effect"); 1892 1893 /* For V32, moves to registers don't set C and V. */ 1894 if (TARGET_V32) 1895 cc_status.flags |= CC_NO_OVERFLOW; 1896 return; 1897 } 1898 else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1)) 1899 || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx) 1900 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0))) 1901 { 1902 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]", 1903 say flags are not changed, except for overlap. */ 1904 if (cc_status.value1 1905 && modified_in_p (cc_status.value1, insn)) 1906 cc_status.value1 = 0; 1907 1908 if (cc_status.value2 1909 && modified_in_p (cc_status.value2, insn)) 1910 cc_status.value2 = 0; 1911 1912 return; 1913 } 1914 } 1915 } 1916 1917 /* If we got here, the case wasn't covered by the code above. */ 1918 CC_STATUS_INIT; 1919 } 1920 1921 /* This function looks into the pattern to see how this insn affects 1922 condition codes. 1923 1924 Used when to eliminate test insns before a condition-code user, 1925 such as a "scc" insn or a conditional branch. This includes 1926 checking if the entities that cc was updated by, are changed by the 1927 operation. 1928 1929 Currently a jumble of the old peek-inside-the-insn and the newer 1930 check-cc-attribute methods. */ 1931 1932 void 1933 cris_notice_update_cc (rtx exp, rtx_insn *insn) 1934 { 1935 enum attr_cc attrval = get_attr_cc (insn); 1936 1937 /* Check if user specified "-mcc-init" as a bug-workaround. Remember 1938 to still set CC_REVERSED as below, since that's required by some 1939 compare insn alternatives. (FIXME: GCC should do this virtual 1940 operand swap by itself.) A test-case that may otherwise fail is 1941 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */ 1942 if (TARGET_CCINIT) 1943 { 1944 CC_STATUS_INIT; 1945 1946 if (attrval == CC_REV) 1947 cc_status.flags = CC_REVERSED; 1948 return; 1949 } 1950 1951 /* Slowly, we're converting to using attributes to control the setting 1952 of condition-code status. */ 1953 switch (attrval) 1954 { 1955 case CC_NONE: 1956 /* Even if it is "none", a setting may clobber a previous 1957 cc-value, so check. */ 1958 if (GET_CODE (exp) == SET) 1959 { 1960 if (cc_status.value1 1961 && modified_in_p (cc_status.value1, insn)) 1962 cc_status.value1 = 0; 1963 1964 if (cc_status.value2 1965 && modified_in_p (cc_status.value2, insn)) 1966 cc_status.value2 = 0; 1967 } 1968 return; 1969 1970 case CC_CLOBBER: 1971 CC_STATUS_INIT; 1972 return; 1973 1974 case CC_REV: 1975 case CC_NOOV32: 1976 case CC_NORMAL: 1977 cris_normal_notice_update_cc (exp, insn); 1978 1979 /* The "test" insn doesn't clear (carry and) overflow on V32. We 1980 can change bge => bpl and blt => bmi by passing on to the cc0 1981 user that V should not be considered; bgt and ble are taken 1982 care of by other methods (see {tst,cmp}{si,hi,qi}). */ 1983 if (attrval == CC_NOOV32 && TARGET_V32) 1984 cc_status.flags |= CC_NO_OVERFLOW; 1985 return; 1986 1987 default: 1988 internal_error ("unknown cc_attr value"); 1989 } 1990 1991 CC_STATUS_INIT; 1992 } 1993 1994 /* Return != 0 if the return sequence for the current function is short, 1995 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if 1996 registers must be saved, so return 0 then. */ 1997 1998 bool 1999 cris_simple_epilogue (void) 2000 { 2001 unsigned int regno; 2002 unsigned int reglimit = STACK_POINTER_REGNUM; 2003 bool got_really_used = false; 2004 2005 if (! reload_completed 2006 || frame_pointer_needed 2007 || get_frame_size () != 0 2008 || crtl->args.pretend_args_size 2009 || crtl->args.size 2010 || crtl->outgoing_args_size 2011 || crtl->calls_eh_return 2012 2013 /* If we're not supposed to emit prologue and epilogue, we must 2014 not emit return-type instructions. */ 2015 || !TARGET_PROLOGUE_EPILOGUE) 2016 return false; 2017 2018 /* Can't return from stacked return address with v32. */ 2019 if (TARGET_V32 && cris_return_address_on_stack ()) 2020 return false; 2021 2022 if (crtl->uses_pic_offset_table) 2023 { 2024 push_topmost_sequence (); 2025 got_really_used 2026 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); 2027 pop_topmost_sequence (); 2028 } 2029 2030 /* No simple epilogue if there are saved registers. */ 2031 for (regno = 0; regno < reglimit; regno++) 2032 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 2033 return false; 2034 2035 return true; 2036 } 2037 2038 /* Emit checking that MEM is aligned for an access in MODE, failing 2039 that, executing a "break 8" (or call to abort, if "break 8" is 2040 disabled). */ 2041 2042 void 2043 cris_emit_trap_for_misalignment (rtx mem) 2044 { 2045 rtx addr, reg, ok_label, andop; 2046 rtx_insn *jmp; 2047 int natural_alignment; 2048 gcc_assert (MEM_P (mem)); 2049 2050 natural_alignment = GET_MODE_SIZE (GET_MODE (mem)); 2051 addr = XEXP (mem, 0); 2052 reg = force_reg (Pmode, addr); 2053 ok_label = gen_label_rtx (); 2054 2055 /* This will yield a btstq without a separate register used, usually - 2056 with the exception for PRE hoisting the "and" but not the branch 2057 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */ 2058 andop = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1)); 2059 emit_cmp_and_jump_insns (force_reg (SImode, andop), const0_rtx, EQ, 2060 NULL_RTX, Pmode, 1, ok_label); 2061 jmp = get_last_insn (); 2062 gcc_assert (JUMP_P (jmp)); 2063 2064 predict_insn_def (jmp, PRED_NORETURN, TAKEN); 2065 expand_builtin_trap (); 2066 emit_label (ok_label); 2067 } 2068 2069 /* Expand a return insn (just one insn) marked as using SRP or stack 2070 slot depending on parameter ON_STACK. */ 2071 2072 void 2073 cris_expand_return (bool on_stack) 2074 { 2075 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to 2076 tell "ret" from "jump [sp+]". Some, but not all, other parts of 2077 GCC expect just (return) to do the right thing when optimizing, so 2078 we do that until they're fixed. Currently, all return insns in a 2079 function must be the same (not really a limiting factor) so we need 2080 to check that it doesn't change half-way through. */ 2081 emit_jump_insn (ret_rtx); 2082 2083 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack); 2084 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack); 2085 2086 cfun->machine->return_type 2087 = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET; 2088 } 2089 2090 /* Compute a (partial) cost for rtx X. Return true if the complete 2091 cost has been computed, and false if subexpressions should be 2092 scanned. In either case, *TOTAL contains the cost result. */ 2093 2094 static bool 2095 cris_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, 2096 int *total, bool speed) 2097 { 2098 int code = GET_CODE (x); 2099 2100 switch (code) 2101 { 2102 case CONST_INT: 2103 { 2104 HOST_WIDE_INT val = INTVAL (x); 2105 if (val == 0) 2106 *total = 0; 2107 else if (val < 32 && val >= -32) 2108 *total = 1; 2109 /* Eight or 16 bits are a word and cycle more expensive. */ 2110 else if (val <= 32767 && val >= -32768) 2111 *total = 2; 2112 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs 2113 another word. FIXME: This isn't linear to 16 bits. */ 2114 else 2115 *total = 4; 2116 return true; 2117 } 2118 2119 case LABEL_REF: 2120 *total = 6; 2121 return true; 2122 2123 case CONST: 2124 case SYMBOL_REF: 2125 *total = 6; 2126 return true; 2127 2128 case CONST_DOUBLE: 2129 if (x != CONST0_RTX (mode == VOIDmode ? DImode : mode)) 2130 *total = 12; 2131 else 2132 /* Make 0.0 cheap, else test-insns will not be used. */ 2133 *total = 0; 2134 return true; 2135 2136 case MULT: 2137 /* If we have one arm of an ADDI, make sure it gets the cost of 2138 one insn, i.e. zero cost for this operand, and just the cost 2139 of the PLUS, as the insn is created by combine from a PLUS 2140 and an ASHIFT, and the MULT cost below would make the 2141 combined value be larger than the separate insns. The insn 2142 validity is checked elsewhere by combine. 2143 2144 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole 2145 function should be rewritten. */ 2146 if (outer_code == PLUS && cris_biap_index_p (x, false)) 2147 { 2148 *total = 0; 2149 return true; 2150 } 2151 2152 /* Identify values that are no powers of two. Powers of 2 are 2153 taken care of already and those values should not be changed. */ 2154 if (!CONST_INT_P (XEXP (x, 1)) 2155 || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) 2156 { 2157 /* If we have a multiply insn, then the cost is between 2158 1 and 2 "fast" instructions. */ 2159 if (TARGET_HAS_MUL_INSNS) 2160 { 2161 *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2; 2162 return true; 2163 } 2164 2165 /* Estimate as 4 + 4 * #ofbits. */ 2166 *total = COSTS_N_INSNS (132); 2167 return true; 2168 } 2169 return false; 2170 2171 case UDIV: 2172 case MOD: 2173 case UMOD: 2174 case DIV: 2175 if (!CONST_INT_P (XEXP (x, 1)) 2176 || exact_log2 (INTVAL (XEXP (x, 1)) < 0)) 2177 { 2178 /* Estimate this as 4 + 8 * #of bits. */ 2179 *total = COSTS_N_INSNS (260); 2180 return true; 2181 } 2182 return false; 2183 2184 case AND: 2185 if (CONST_INT_P (XEXP (x, 1)) 2186 /* Two constants may actually happen before optimization. */ 2187 && !CONST_INT_P (XEXP (x, 0)) 2188 && !satisfies_constraint_I (XEXP (x, 1))) 2189 { 2190 *total 2191 = (rtx_cost (XEXP (x, 0), mode, (enum rtx_code) outer_code, 2192 opno, speed) + 2 2193 + 2 * GET_MODE_NUNITS (mode)); 2194 return true; 2195 } 2196 return false; 2197 2198 case ZERO_EXTRACT: 2199 if (outer_code != COMPARE) 2200 return false; 2201 /* fall through */ 2202 2203 case ZERO_EXTEND: case SIGN_EXTEND: 2204 *total = rtx_cost (XEXP (x, 0), VOIDmode, (enum rtx_code) outer_code, 2205 opno, speed); 2206 return true; 2207 2208 default: 2209 return false; 2210 } 2211 } 2212 2213 /* The ADDRESS_COST worker. */ 2214 2215 static int 2216 cris_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED, 2217 addr_space_t as ATTRIBUTE_UNUSED, 2218 bool speed ATTRIBUTE_UNUSED) 2219 { 2220 /* The metric to use for the cost-macros is unclear. 2221 The metric used here is (the number of cycles needed) / 2, 2222 where we consider equal a cycle for a word of code and a cycle to 2223 read memory. FIXME: Adding "+ 1" to all values would avoid 2224 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes" 2225 0 to 1, thereby giving equal costs to [rN + rM] and [rN]. 2226 Unfortunately(?) such a hack would expose other pessimizations, 2227 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the 2228 loop there, without apparent reason. */ 2229 2230 /* The cheapest addressing modes get 0, since nothing extra is needed. */ 2231 if (cris_base_or_autoincr_p (x, false)) 2232 return 0; 2233 2234 /* An indirect mem must be a DIP. This means two bytes extra for code, 2235 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */ 2236 if (MEM_P (x)) 2237 return (2 + 4) / 2; 2238 2239 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs 2240 an extra DIP prefix and 4 bytes of constant in most cases. */ 2241 if (CONSTANT_P (x)) 2242 return (2 + 4) / 2; 2243 2244 /* Handle BIAP and BDAP prefixes. */ 2245 if (GET_CODE (x) == PLUS) 2246 { 2247 rtx tem1 = XEXP (x, 0); 2248 rtx tem2 = XEXP (x, 1); 2249 2250 /* Local extended canonicalization rule: the first operand must 2251 be REG, unless it's an operation (MULT). */ 2252 if (!REG_P (tem1) && GET_CODE (tem1) != MULT) 2253 tem1 = tem2, tem2 = XEXP (x, 0); 2254 2255 /* We'll "assume" we have canonical RTX now. */ 2256 gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT); 2257 2258 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We 2259 recognize the typical MULT which is always in tem1 because of 2260 insn canonicalization. */ 2261 if ((GET_CODE (tem1) == MULT && cris_biap_index_p (tem1, false)) 2262 || REG_P (tem2)) 2263 return 2 / 2; 2264 2265 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the 2266 PLUS is always found in tem2. */ 2267 if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128) 2268 return 2 / 2; 2269 2270 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra 2271 bytes. */ 2272 if (satisfies_constraint_L (tem2)) 2273 return (2 + 2) / 2; 2274 2275 /* A BDAP with some other constant is 2 bytes extra. */ 2276 if (CRIS_CONSTANT_P (tem2)) 2277 return (2 + 2 + 2) / 2; 2278 2279 /* BDAP with something indirect should have a higher cost than 2280 BIAP with register. FIXME: Should it cost like a MEM or more? */ 2281 return (2 + 2 + 2) / 2; 2282 } 2283 2284 /* What else? Return a high cost. It matters only for valid 2285 addressing modes. */ 2286 return 10; 2287 } 2288 2289 /* Check various objections to the side-effect. Used in the test-part 2290 of an anonymous insn describing an insn with a possible side-effect. 2291 Returns nonzero if the implied side-effect is ok. 2292 2293 code : PLUS or MULT 2294 ops : An array of rtx:es. lreg, rreg, rval, 2295 The variables multop and other_op are indexes into this, 2296 or -1 if they are not applicable. 2297 lreg : The register that gets assigned in the side-effect. 2298 rreg : One register in the side-effect expression 2299 rval : The other register, or an int. 2300 multop : An integer to multiply rval with. 2301 other_op : One of the entities of the main effect, 2302 whose mode we must consider. */ 2303 2304 int 2305 cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, 2306 int lreg, int rreg, int rval, 2307 int multop, int other_op) 2308 { 2309 /* Find what value to multiply with, for rx =ry + rz * n. */ 2310 int mult = multop < 0 ? 1 : INTVAL (ops[multop]); 2311 2312 rtx reg_rtx = ops[rreg]; 2313 rtx val_rtx = ops[rval]; 2314 2315 /* The operands may be swapped. Canonicalize them in reg_rtx and 2316 val_rtx, where reg_rtx always is a reg (for this constraint to 2317 match). */ 2318 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) 2319 reg_rtx = val_rtx, val_rtx = ops[rreg]; 2320 2321 /* Don't forget to check that reg_rtx really is a reg. If it isn't, 2322 we have no business. */ 2323 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) 2324 return 0; 2325 2326 /* Don't do this when -mno-split. */ 2327 if (!TARGET_SIDE_EFFECT_PREFIXES) 2328 return 0; 2329 2330 /* The mult expression may be hidden in lreg. FIXME: Add more 2331 commentary about that. */ 2332 if (GET_CODE (val_rtx) == MULT) 2333 { 2334 mult = INTVAL (XEXP (val_rtx, 1)); 2335 val_rtx = XEXP (val_rtx, 0); 2336 code = MULT; 2337 } 2338 2339 /* First check the "other operand". */ 2340 if (other_op >= 0) 2341 { 2342 if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD) 2343 return 0; 2344 2345 /* Check if the lvalue register is the same as the "other 2346 operand". If so, the result is undefined and we shouldn't do 2347 this. FIXME: Check again. */ 2348 if ((cris_base_p (ops[lreg], reload_in_progress || reload_completed) 2349 && cris_base_p (ops[other_op], 2350 reload_in_progress || reload_completed) 2351 && REGNO (ops[lreg]) == REGNO (ops[other_op])) 2352 || rtx_equal_p (ops[other_op], ops[lreg])) 2353 return 0; 2354 } 2355 2356 /* Do not accept frame_pointer_rtx as any operand. */ 2357 if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx 2358 || ops[rval] == frame_pointer_rtx 2359 || (other_op >= 0 && ops[other_op] == frame_pointer_rtx)) 2360 return 0; 2361 2362 if (code == PLUS 2363 && ! cris_base_p (val_rtx, reload_in_progress || reload_completed)) 2364 { 2365 2366 /* Do not allow rx = rx + n if a normal add or sub with same size 2367 would do. */ 2368 if (rtx_equal_p (ops[lreg], reg_rtx) 2369 && CONST_INT_P (val_rtx) 2370 && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63)) 2371 return 0; 2372 2373 /* Check allowed cases, like [r(+)?].[bwd] and const. */ 2374 if (CRIS_CONSTANT_P (val_rtx)) 2375 return 1; 2376 2377 if (MEM_P (val_rtx) 2378 && cris_base_or_autoincr_p (XEXP (val_rtx, 0), 2379 reload_in_progress || reload_completed)) 2380 return 1; 2381 2382 if (GET_CODE (val_rtx) == SIGN_EXTEND 2383 && MEM_P (XEXP (val_rtx, 0)) 2384 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx, 0), 0), 2385 reload_in_progress || reload_completed)) 2386 return 1; 2387 2388 /* If we got here, it's not a valid addressing mode. */ 2389 return 0; 2390 } 2391 else if (code == MULT 2392 || (code == PLUS 2393 && cris_base_p (val_rtx, 2394 reload_in_progress || reload_completed))) 2395 { 2396 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */ 2397 if (rtx_equal_p (ops[lreg], reg_rtx) 2398 || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx))) 2399 return 0; 2400 2401 /* Do not allow bad multiply-values. */ 2402 if (mult != 1 && mult != 2 && mult != 4) 2403 return 0; 2404 2405 /* Only allow r + ... */ 2406 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) 2407 return 0; 2408 2409 /* If we got here, all seems ok. 2410 (All checks need to be done above). */ 2411 return 1; 2412 } 2413 2414 /* If we get here, the caller got its initial tests wrong. */ 2415 internal_error ("internal error: cris_side_effect_mode_ok with bad operands"); 2416 } 2417 2418 /* Whether next_cc0_user of insn is LE or GT or requires a real compare 2419 insn for other reasons. */ 2420 2421 bool 2422 cris_cc0_user_requires_cmp (rtx_insn *insn) 2423 { 2424 rtx_insn *cc0_user = NULL; 2425 rtx body; 2426 rtx set; 2427 2428 gcc_assert (insn != NULL); 2429 2430 if (!TARGET_V32) 2431 return false; 2432 2433 cc0_user = next_cc0_user (insn); 2434 if (cc0_user == NULL) 2435 return false; 2436 2437 body = PATTERN (cc0_user); 2438 set = single_set (cc0_user); 2439 2440 /* Users can be sCC and bCC. */ 2441 if (JUMP_P (cc0_user) 2442 && GET_CODE (body) == SET 2443 && SET_DEST (body) == pc_rtx 2444 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE 2445 && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx) 2446 { 2447 return 2448 GET_CODE (XEXP (SET_SRC (body), 0)) == GT 2449 || GET_CODE (XEXP (SET_SRC (body), 0)) == LE; 2450 } 2451 else if (set) 2452 { 2453 return 2454 GET_CODE (SET_SRC (body)) == GT 2455 || GET_CODE (SET_SRC (body)) == LE; 2456 } 2457 2458 gcc_unreachable (); 2459 } 2460 2461 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16) 2462 does not handle the case where the IN operand is strict_low_part; it 2463 does handle it for X. Test-case in Axis-20010516. This function takes 2464 care of that for THIS port. FIXME: strict_low_part is going away 2465 anyway. */ 2466 2467 static int 2468 cris_reg_overlap_mentioned_p (rtx x, rtx in) 2469 { 2470 /* The function reg_overlap_mentioned now handles when X is 2471 strict_low_part, but not when IN is a STRICT_LOW_PART. */ 2472 if (GET_CODE (in) == STRICT_LOW_PART) 2473 in = XEXP (in, 0); 2474 2475 return reg_overlap_mentioned_p (x, in); 2476 } 2477 2478 /* Return TRUE iff X is a CONST valid for e.g. indexing. 2479 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1 2480 elsewhere. */ 2481 2482 bool 2483 cris_valid_pic_const (const_rtx x, bool any_operand) 2484 { 2485 gcc_assert (flag_pic); 2486 2487 switch (GET_CODE (x)) 2488 { 2489 case CONST_INT: 2490 case CONST_DOUBLE: 2491 return true; 2492 default: 2493 ; 2494 } 2495 2496 if (GET_CODE (x) != CONST) 2497 return false; 2498 2499 x = XEXP (x, 0); 2500 2501 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */ 2502 if (GET_CODE (x) == PLUS 2503 && GET_CODE (XEXP (x, 0)) == UNSPEC 2504 && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL 2505 || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL) 2506 && CONST_INT_P (XEXP (x, 1))) 2507 x = XEXP (x, 0); 2508 2509 if (GET_CODE (x) == UNSPEC) 2510 switch (XINT (x, 1)) 2511 { 2512 /* A PCREL operand is only valid for call and movsi. */ 2513 case CRIS_UNSPEC_PLT_PCREL: 2514 case CRIS_UNSPEC_PCREL: 2515 return !any_operand; 2516 2517 case CRIS_UNSPEC_PLT_GOTREL: 2518 case CRIS_UNSPEC_PLTGOTREAD: 2519 case CRIS_UNSPEC_GOTREAD: 2520 case CRIS_UNSPEC_GOTREL: 2521 return true; 2522 default: 2523 gcc_unreachable (); 2524 } 2525 2526 return cris_symbol_type_of (x) == cris_no_symbol; 2527 } 2528 2529 /* Helper function to find the right symbol-type to generate, 2530 given the original (non-PIC) representation. */ 2531 2532 enum cris_symbol_type 2533 cris_symbol_type_of (const_rtx x) 2534 { 2535 switch (GET_CODE (x)) 2536 { 2537 case SYMBOL_REF: 2538 return flag_pic 2539 ? (SYMBOL_REF_LOCAL_P (x) 2540 ? cris_rel_symbol : cris_got_symbol) 2541 : cris_offsettable_symbol; 2542 2543 case LABEL_REF: 2544 return flag_pic ? cris_rel_symbol : cris_offsettable_symbol; 2545 2546 case CONST: 2547 return cris_symbol_type_of (XEXP (x, 0)); 2548 2549 case PLUS: 2550 case MINUS: 2551 { 2552 enum cris_symbol_type t1 = cris_symbol_type_of (XEXP (x, 0)); 2553 enum cris_symbol_type t2 = cris_symbol_type_of (XEXP (x, 1)); 2554 2555 gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol); 2556 2557 if (t1 == cris_got_symbol || t2 == cris_got_symbol) 2558 return cris_got_symbol_needing_fixup; 2559 2560 return t1 != cris_no_symbol ? t1 : t2; 2561 } 2562 2563 case CONST_INT: 2564 case CONST_DOUBLE: 2565 return cris_no_symbol; 2566 2567 case UNSPEC: 2568 return cris_unspec; 2569 2570 default: 2571 fatal_insn ("unrecognized supposed constant", x); 2572 } 2573 2574 gcc_unreachable (); 2575 } 2576 2577 /* The LEGITIMATE_PIC_OPERAND_P worker. */ 2578 2579 int 2580 cris_legitimate_pic_operand (rtx x) 2581 { 2582 /* Symbols are not valid PIC operands as-is; just constants. */ 2583 return cris_valid_pic_const (x, true); 2584 } 2585 2586 /* Queue an .ident string in the queue of top-level asm statements. 2587 If the front-end is done, we must be being called from toplev.c. 2588 In that case, do nothing. */ 2589 void 2590 cris_asm_output_ident (const char *string) 2591 { 2592 if (symtab->state != PARSING) 2593 return; 2594 2595 default_asm_output_ident_directive (string); 2596 } 2597 2598 /* The ASM_OUTPUT_CASE_END worker. */ 2599 2600 void 2601 cris_asm_output_case_end (FILE *stream, int num, rtx_insn *table) 2602 { 2603 /* Step back, over the label for the table, to the actual casejump and 2604 assert that we find only what's expected. */ 2605 rtx_insn *whole_jump_insn = prev_nonnote_nondebug_insn (table); 2606 gcc_assert (whole_jump_insn != NULL_RTX && LABEL_P (whole_jump_insn)); 2607 whole_jump_insn = prev_nonnote_nondebug_insn (whole_jump_insn); 2608 gcc_assert (whole_jump_insn != NULL_RTX 2609 && (JUMP_P (whole_jump_insn) 2610 || (TARGET_V32 && INSN_P (whole_jump_insn) 2611 && GET_CODE (PATTERN (whole_jump_insn)) == SEQUENCE))); 2612 /* Get the pattern of the casejump, so we can extract the default label. */ 2613 rtx whole_jump_pat = PATTERN (whole_jump_insn); 2614 2615 if (TARGET_V32) 2616 { 2617 /* This can be a SEQUENCE, meaning the delay-slot of the jump is 2618 filled. We also output the offset word a little differently. */ 2619 rtx parallel_jump 2620 = (GET_CODE (whole_jump_pat) == SEQUENCE 2621 ? PATTERN (XVECEXP (whole_jump_pat, 0, 0)) : whole_jump_pat); 2622 2623 asm_fprintf (stream, 2624 "\t.word %LL%d-.%s\n", 2625 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP 2626 (parallel_jump, 0, 0), 2627 1), 2), 0)), 2628 (TARGET_PDEBUG ? "; default" : "")); 2629 return; 2630 } 2631 2632 asm_fprintf (stream, 2633 "\t.word %LL%d-%LL%d%s\n", 2634 CODE_LABEL_NUMBER (XEXP 2635 (XEXP 2636 (XEXP (XVECEXP (whole_jump_pat, 0, 0), 1), 2637 2), 0)), 2638 num, 2639 (TARGET_PDEBUG ? "; default" : "")); 2640 } 2641 2642 /* The TARGET_OPTION_OVERRIDE worker. 2643 As is the norm, this also parses -mfoo=bar type parameters. */ 2644 2645 static void 2646 cris_option_override (void) 2647 { 2648 if (cris_max_stackframe_str) 2649 { 2650 cris_max_stackframe = atoi (cris_max_stackframe_str); 2651 2652 /* Do some sanity checking. */ 2653 if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000) 2654 internal_error ("%<-max-stackframe=%d%> is not usable, " 2655 "not between 0 and %d", 2656 cris_max_stackframe, 0x20000000); 2657 } 2658 2659 /* Let "-metrax4" and "-metrax100" change the cpu version. */ 2660 if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO) 2661 cris_cpu_version = CRIS_CPU_SVINTO; 2662 else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4) 2663 cris_cpu_version = CRIS_CPU_ETRAX4; 2664 2665 /* Parse -march=... and its synonym, the deprecated -mcpu=... */ 2666 if (cris_cpu_str) 2667 { 2668 cris_cpu_version 2669 = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1); 2670 2671 if (strcmp ("etrax4", cris_cpu_str) == 0) 2672 cris_cpu_version = 3; 2673 2674 if (strcmp ("svinto", cris_cpu_str) == 0 2675 || strcmp ("etrax100", cris_cpu_str) == 0) 2676 cris_cpu_version = 8; 2677 2678 if (strcmp ("ng", cris_cpu_str) == 0 2679 || strcmp ("etrax100lx", cris_cpu_str) == 0) 2680 cris_cpu_version = 10; 2681 2682 if (cris_cpu_version < 0 || cris_cpu_version > 32) 2683 error ("unknown CRIS version specification in %<-march=%> or " 2684 "%<-mcpu=%> : %s", cris_cpu_str); 2685 2686 /* Set the target flags. */ 2687 if (cris_cpu_version >= CRIS_CPU_ETRAX4) 2688 target_flags |= MASK_ETRAX4_ADD; 2689 2690 /* If this is Svinto or higher, align for 32 bit accesses. */ 2691 if (cris_cpu_version >= CRIS_CPU_SVINTO) 2692 target_flags 2693 |= (MASK_SVINTO | MASK_ALIGN_BY_32 2694 | MASK_STACK_ALIGN | MASK_CONST_ALIGN 2695 | MASK_DATA_ALIGN); 2696 2697 /* Note that we do not add new flags when it can be completely 2698 described with a macro that uses -mcpu=X. So 2699 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */ 2700 } 2701 2702 if (cris_tune_str) 2703 { 2704 int cris_tune 2705 = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1); 2706 2707 if (strcmp ("etrax4", cris_tune_str) == 0) 2708 cris_tune = 3; 2709 2710 if (strcmp ("svinto", cris_tune_str) == 0 2711 || strcmp ("etrax100", cris_tune_str) == 0) 2712 cris_tune = 8; 2713 2714 if (strcmp ("ng", cris_tune_str) == 0 2715 || strcmp ("etrax100lx", cris_tune_str) == 0) 2716 cris_tune = 10; 2717 2718 if (cris_tune < 0 || cris_tune > 32) 2719 error ("unknown CRIS cpu version specification in %<-mtune=%> : %s", 2720 cris_tune_str); 2721 2722 if (cris_tune >= CRIS_CPU_SVINTO) 2723 /* We have currently nothing more to tune than alignment for 2724 memory accesses. */ 2725 target_flags 2726 |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN 2727 | MASK_DATA_ALIGN | MASK_ALIGN_BY_32); 2728 } 2729 2730 if (cris_cpu_version >= CRIS_CPU_V32) 2731 target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG); 2732 2733 if (flag_pic) 2734 { 2735 /* Use error rather than warning, so invalid use is easily 2736 detectable. Still change to the values we expect, to avoid 2737 further errors. */ 2738 if (! TARGET_LINUX) 2739 { 2740 error ("%<-fPIC%> and %<-fpic%> are not supported " 2741 "in this configuration"); 2742 flag_pic = 0; 2743 } 2744 2745 /* Turn off function CSE. We need to have the addresses reach the 2746 call expanders to get PLT-marked, as they could otherwise be 2747 compared against zero directly or indirectly. After visiting the 2748 call expanders they will then be cse:ed, as the call expanders 2749 force_reg the addresses, effectively forcing flag_no_function_cse 2750 to 0. */ 2751 flag_no_function_cse = 1; 2752 } 2753 2754 /* Set the per-function-data initializer. */ 2755 init_machine_status = cris_init_machine_status; 2756 } 2757 2758 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */ 2759 2760 static void 2761 cris_asm_output_mi_thunk (FILE *stream, 2762 tree thunkdecl ATTRIBUTE_UNUSED, 2763 HOST_WIDE_INT delta, 2764 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, 2765 tree funcdecl) 2766 { 2767 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunkdecl)); 2768 2769 assemble_start_function (thunkdecl, fnname); 2770 /* Make sure unwind info is emitted for the thunk if needed. */ 2771 final_start_function (emit_barrier (), stream, 1); 2772 2773 if (delta > 0) 2774 fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", 2775 ADDITIVE_SIZE_MODIFIER (delta), delta, 2776 reg_names[CRIS_FIRST_ARG_REG]); 2777 else if (delta < 0) 2778 fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n", 2779 ADDITIVE_SIZE_MODIFIER (-delta), -delta, 2780 reg_names[CRIS_FIRST_ARG_REG]); 2781 2782 if (flag_pic) 2783 { 2784 const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0); 2785 2786 name = (* targetm.strip_name_encoding) (name); 2787 2788 if (TARGET_V32) 2789 { 2790 fprintf (stream, "\tba "); 2791 assemble_name (stream, name); 2792 fprintf (stream, "%s\n\tnop\n", CRIS_PLT_PCOFFSET_SUFFIX); 2793 } 2794 else 2795 { 2796 fprintf (stream, "\tadd.d "); 2797 assemble_name (stream, name); 2798 fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX); 2799 } 2800 } 2801 else 2802 { 2803 fprintf (stream, "\tjump "); 2804 assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0)); 2805 fprintf (stream, "\n"); 2806 2807 if (TARGET_V32) 2808 fprintf (stream, "\tnop\n"); 2809 } 2810 2811 final_end_function (); 2812 assemble_end_function (thunkdecl, fnname); 2813 } 2814 2815 /* Boilerplate emitted at start of file. 2816 2817 NO_APP *only at file start* means faster assembly. It also means 2818 comments are not allowed. In some cases comments will be output 2819 for debugging purposes. Make sure they are allowed then. */ 2820 static void 2821 cris_file_start (void) 2822 { 2823 /* These expressions can vary at run time, so we cannot put 2824 them into TARGET_INITIALIZER. */ 2825 targetm.asm_file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name); 2826 2827 default_file_start (); 2828 } 2829 2830 /* Output that goes at the end of the file, similarly. */ 2831 2832 static void 2833 cris_file_end (void) 2834 { 2835 /* For CRIS, the default is to assume *no* executable stack, so output 2836 an executable-stack-note only when needed. */ 2837 if (TARGET_LINUX && trampolines_created) 2838 file_end_indicate_exec_stack (); 2839 } 2840 2841 /* Rename the function calls for integer multiply and divide. */ 2842 static void 2843 cris_init_libfuncs (void) 2844 { 2845 set_optab_libfunc (smul_optab, SImode, "__Mul"); 2846 set_optab_libfunc (sdiv_optab, SImode, "__Div"); 2847 set_optab_libfunc (udiv_optab, SImode, "__Udiv"); 2848 set_optab_libfunc (smod_optab, SImode, "__Mod"); 2849 set_optab_libfunc (umod_optab, SImode, "__Umod"); 2850 2851 /* Atomic data being unaligned is unfortunately a reality. 2852 Deal with it. */ 2853 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS) 2854 { 2855 set_optab_libfunc (sync_compare_and_swap_optab, SImode, 2856 "__cris_atcmpxchgr32"); 2857 set_optab_libfunc (sync_compare_and_swap_optab, HImode, 2858 "__cris_atcmpxchgr16"); 2859 } 2860 } 2861 2862 /* The INIT_EXPANDERS worker sets the per-function-data initializer and 2863 mark functions. */ 2864 2865 void 2866 cris_init_expanders (void) 2867 { 2868 /* Nothing here at the moment. */ 2869 } 2870 2871 /* Zero initialization is OK for all current fields. */ 2872 2873 static struct machine_function * 2874 cris_init_machine_status (void) 2875 { 2876 return ggc_cleared_alloc<machine_function> (); 2877 } 2878 2879 /* Split a 2 word move (DI or presumably DF) into component parts. 2880 Originally a copy of gen_split_move_double in m32r.c. */ 2881 2882 rtx 2883 cris_split_movdx (rtx *operands) 2884 { 2885 machine_mode mode = GET_MODE (operands[0]); 2886 rtx dest = operands[0]; 2887 rtx src = operands[1]; 2888 rtx val; 2889 2890 /* We used to have to handle (SUBREG (MEM)) here, but that should no 2891 longer happen; after reload there are no SUBREGs any more, and we're 2892 only called after reload. */ 2893 CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG); 2894 2895 start_sequence (); 2896 if (REG_P (dest)) 2897 { 2898 int dregno = REGNO (dest); 2899 2900 /* Reg-to-reg copy. */ 2901 if (REG_P (src)) 2902 { 2903 int sregno = REGNO (src); 2904 2905 int reverse = (dregno == sregno + 1); 2906 2907 /* We normally copy the low-numbered register first. However, if 2908 the first register operand 0 is the same as the second register of 2909 operand 1, we must copy in the opposite order. */ 2910 emit_insn (gen_rtx_SET (operand_subword (dest, reverse, TRUE, mode), 2911 operand_subword (src, reverse, TRUE, mode))); 2912 2913 emit_insn (gen_rtx_SET (operand_subword (dest, !reverse, TRUE, mode), 2914 operand_subword (src, !reverse, TRUE, mode))); 2915 } 2916 /* Constant-to-reg copy. */ 2917 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE) 2918 { 2919 rtx words[2]; 2920 split_double (src, &words[0], &words[1]); 2921 emit_insn (gen_rtx_SET (operand_subword (dest, 0, TRUE, mode), 2922 words[0])); 2923 2924 emit_insn (gen_rtx_SET (operand_subword (dest, 1, TRUE, mode), 2925 words[1])); 2926 } 2927 /* Mem-to-reg copy. */ 2928 else if (MEM_P (src)) 2929 { 2930 /* If the high-address word is used in the address, we must load it 2931 last. Otherwise, load it first. */ 2932 rtx addr = XEXP (src, 0); 2933 int reverse = (refers_to_regno_p (dregno, addr) != 0); 2934 2935 /* The original code implies that we can't do 2936 move.x [rN+],rM move.x [rN],rM+1 2937 when rN is dead, because of REG_NOTES damage. That is 2938 consistent with what I've seen, so don't try it. 2939 2940 We have two different cases here; if the addr is POST_INC, 2941 just pass it through, otherwise add constants. */ 2942 2943 if (GET_CODE (addr) == POST_INC) 2944 { 2945 rtx mem; 2946 rtx insn; 2947 2948 /* Whenever we emit insns with post-incremented 2949 addresses ourselves, we must add a post-inc note 2950 manually. */ 2951 mem = change_address (src, SImode, addr); 2952 insn 2953 = gen_rtx_SET (operand_subword (dest, 0, TRUE, mode), mem); 2954 insn = emit_insn (insn); 2955 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 2956 REG_NOTES (insn) 2957 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 2958 REG_NOTES (insn)); 2959 2960 mem = copy_rtx (mem); 2961 insn 2962 = gen_rtx_SET (operand_subword (dest, 1, TRUE, mode), mem); 2963 insn = emit_insn (insn); 2964 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 2965 REG_NOTES (insn) 2966 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 2967 REG_NOTES (insn)); 2968 } 2969 else 2970 { 2971 /* Make sure we don't get any other addresses with 2972 embedded postincrements. They should be stopped in 2973 GO_IF_LEGITIMATE_ADDRESS, but we're here for your 2974 safety. */ 2975 if (side_effects_p (addr)) 2976 fatal_insn ("unexpected side-effects in address", addr); 2977 2978 emit_insn (gen_rtx_SET 2979 (operand_subword (dest, reverse, TRUE, mode), 2980 change_address 2981 (src, SImode, 2982 plus_constant (Pmode, addr, 2983 reverse * UNITS_PER_WORD)))); 2984 emit_insn (gen_rtx_SET 2985 (operand_subword (dest, ! reverse, TRUE, mode), 2986 change_address 2987 (src, SImode, 2988 plus_constant (Pmode, addr, 2989 (! reverse) * 2990 UNITS_PER_WORD)))); 2991 } 2992 } 2993 else 2994 internal_error ("unknown src"); 2995 } 2996 /* Reg-to-mem copy or clear mem. */ 2997 else if (MEM_P (dest) 2998 && (REG_P (src) 2999 || src == const0_rtx 3000 || src == CONST0_RTX (DFmode))) 3001 { 3002 rtx addr = XEXP (dest, 0); 3003 3004 if (GET_CODE (addr) == POST_INC) 3005 { 3006 rtx mem; 3007 rtx insn; 3008 3009 /* Whenever we emit insns with post-incremented addresses 3010 ourselves, we must add a post-inc note manually. */ 3011 mem = change_address (dest, SImode, addr); 3012 insn 3013 = gen_rtx_SET (mem, operand_subword (src, 0, TRUE, mode)); 3014 insn = emit_insn (insn); 3015 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 3016 REG_NOTES (insn) 3017 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 3018 REG_NOTES (insn)); 3019 3020 mem = copy_rtx (mem); 3021 insn = gen_rtx_SET (mem, operand_subword (src, 1, TRUE, mode)); 3022 insn = emit_insn (insn); 3023 if (GET_CODE (XEXP (mem, 0)) == POST_INC) 3024 REG_NOTES (insn) 3025 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), 3026 REG_NOTES (insn)); 3027 } 3028 else 3029 { 3030 /* Make sure we don't get any other addresses with embedded 3031 postincrements. They should be stopped in 3032 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */ 3033 if (side_effects_p (addr)) 3034 fatal_insn ("unexpected side-effects in address", addr); 3035 3036 emit_insn (gen_rtx_SET 3037 (change_address (dest, SImode, addr), 3038 operand_subword (src, 0, TRUE, mode))); 3039 3040 emit_insn (gen_rtx_SET 3041 (change_address (dest, SImode, 3042 plus_constant (Pmode, addr, 3043 UNITS_PER_WORD)), 3044 operand_subword (src, 1, TRUE, mode))); 3045 } 3046 } 3047 3048 else 3049 internal_error ("unknown dest"); 3050 3051 val = get_insns (); 3052 end_sequence (); 3053 return val; 3054 } 3055 3056 /* Try to change a comparison against a constant to be against zero, and 3057 an unsigned compare against zero to be an equality test. Beware: 3058 only valid for compares of integer-type operands. Also, note that we 3059 don't use operand 0 at the moment. */ 3060 3061 void 3062 cris_reduce_compare (rtx *relp, rtx *, rtx *op1p) 3063 { 3064 rtx op1 = *op1p; 3065 rtx_code code = GET_CODE (*relp); 3066 3067 /* Code lifted mostly from emit_store_flag_1. */ 3068 switch (code) 3069 { 3070 case LT: 3071 if (op1 == const1_rtx) 3072 code = LE; 3073 break; 3074 case LE: 3075 if (op1 == constm1_rtx) 3076 code = LT; 3077 break; 3078 case GE: 3079 if (op1 == const1_rtx) 3080 code = GT; 3081 break; 3082 case GT: 3083 if (op1 == constm1_rtx) 3084 code = GE; 3085 break; 3086 case GEU: 3087 if (op1 == const1_rtx) 3088 code = NE; 3089 break; 3090 case LTU: 3091 if (op1 == const1_rtx) 3092 code = EQ; 3093 break; 3094 case GTU: 3095 if (op1 == const0_rtx) 3096 code = NE; 3097 break; 3098 case LEU: 3099 if (op1 == const0_rtx) 3100 code = EQ; 3101 break; 3102 default: 3103 break; 3104 } 3105 3106 if (code != GET_CODE (*relp)) 3107 { 3108 *op1p = const0_rtx; 3109 PUT_CODE (*relp, code); 3110 } 3111 } 3112 3113 /* The expander for the prologue pattern name. */ 3114 3115 void 3116 cris_expand_prologue (void) 3117 { 3118 int regno; 3119 int size = get_frame_size (); 3120 /* Shorten the used name for readability. */ 3121 int cfoa_size = crtl->outgoing_args_size; 3122 int last_movem_reg = -1; 3123 int framesize = 0; 3124 rtx mem, insn; 3125 int return_address_on_stack = cris_return_address_on_stack (); 3126 int got_really_used = false; 3127 int n_movem_regs = 0; 3128 int pretend = crtl->args.pretend_args_size; 3129 3130 /* Don't do anything if no prologues or epilogues are wanted. */ 3131 if (!TARGET_PROLOGUE_EPILOGUE) 3132 return; 3133 3134 CRIS_ASSERT (size >= 0); 3135 3136 if (crtl->uses_pic_offset_table) 3137 { 3138 /* A reference may have been optimized out (like the abort () in 3139 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that 3140 it's still used. */ 3141 push_topmost_sequence (); 3142 got_really_used 3143 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); 3144 pop_topmost_sequence (); 3145 } 3146 3147 /* Align the size to what's best for the CPU model. */ 3148 if (TARGET_STACK_ALIGN) 3149 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; 3150 3151 if (pretend) 3152 { 3153 /* See also cris_setup_incoming_varargs where 3154 cfun->machine->stdarg_regs is set. There are other setters of 3155 crtl->args.pretend_args_size than stdarg handling, like 3156 for an argument passed with parts in R13 and stack. We must 3157 not store R13 into the pretend-area for that case, as GCC does 3158 that itself. "Our" store would be marked as redundant and GCC 3159 will attempt to remove it, which will then be flagged as an 3160 internal error; trying to remove a frame-related insn. */ 3161 int stdarg_regs = cfun->machine->stdarg_regs; 3162 3163 framesize += pretend; 3164 3165 for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1; 3166 stdarg_regs > 0; 3167 regno--, pretend -= 4, stdarg_regs--) 3168 { 3169 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3170 plus_constant (Pmode, 3171 stack_pointer_rtx, 3172 -4))); 3173 /* FIXME: When dwarf2 frame output and unless asynchronous 3174 exceptions, make dwarf2 bundle together all stack 3175 adjustments like it does for registers between stack 3176 adjustments. */ 3177 RTX_FRAME_RELATED_P (insn) = 1; 3178 3179 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3180 set_mem_alias_set (mem, get_varargs_alias_set ()); 3181 insn = emit_move_insn (mem, gen_raw_REG (SImode, regno)); 3182 3183 /* Note the absence of RTX_FRAME_RELATED_P on the above insn: 3184 the value isn't restored, so we don't want to tell dwarf2 3185 that it's been stored to stack, else EH handling info would 3186 get confused. */ 3187 } 3188 3189 /* For other setters of crtl->args.pretend_args_size, we 3190 just adjust the stack by leaving the remaining size in 3191 "pretend", handled below. */ 3192 } 3193 3194 /* Save SRP if not a leaf function. */ 3195 if (return_address_on_stack) 3196 { 3197 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3198 plus_constant (Pmode, stack_pointer_rtx, 3199 -4 - pretend))); 3200 pretend = 0; 3201 RTX_FRAME_RELATED_P (insn) = 1; 3202 3203 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3204 set_mem_alias_set (mem, get_frame_alias_set ()); 3205 insn = emit_move_insn (mem, gen_raw_REG (SImode, CRIS_SRP_REGNUM)); 3206 RTX_FRAME_RELATED_P (insn) = 1; 3207 framesize += 4; 3208 } 3209 3210 /* Set up the frame pointer, if needed. */ 3211 if (frame_pointer_needed) 3212 { 3213 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3214 plus_constant (Pmode, stack_pointer_rtx, 3215 -4 - pretend))); 3216 pretend = 0; 3217 RTX_FRAME_RELATED_P (insn) = 1; 3218 3219 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3220 set_mem_alias_set (mem, get_frame_alias_set ()); 3221 insn = emit_move_insn (mem, frame_pointer_rtx); 3222 RTX_FRAME_RELATED_P (insn) = 1; 3223 3224 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); 3225 RTX_FRAME_RELATED_P (insn) = 1; 3226 3227 framesize += 4; 3228 } 3229 3230 /* Between frame-pointer and saved registers lie the area for local 3231 variables. If we get here with "pretended" size remaining, count 3232 it into the general stack size. */ 3233 size += pretend; 3234 3235 /* Get a contiguous sequence of registers, starting with R0, that need 3236 to be saved. */ 3237 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 3238 { 3239 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 3240 { 3241 n_movem_regs++; 3242 3243 /* Check if movem may be used for registers so far. */ 3244 if (regno == last_movem_reg + 1) 3245 /* Yes, update next expected register. */ 3246 last_movem_reg = regno; 3247 else 3248 { 3249 /* We cannot use movem for all registers. We have to flush 3250 any movem:ed registers we got so far. */ 3251 if (last_movem_reg != -1) 3252 { 3253 int n_saved 3254 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; 3255 3256 /* It is a win to use a side-effect assignment for 3257 64 <= size <= 128. But side-effect on movem was 3258 not usable for CRIS v0..3. Also only do it if 3259 side-effects insns are allowed. */ 3260 if ((last_movem_reg + 1) * 4 + size >= 64 3261 && (last_movem_reg + 1) * 4 + size <= 128 3262 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) 3263 && TARGET_SIDE_EFFECT_PREFIXES) 3264 { 3265 mem 3266 = gen_rtx_MEM (SImode, 3267 plus_constant (Pmode, stack_pointer_rtx, 3268 -(n_saved * 4 + size))); 3269 set_mem_alias_set (mem, get_frame_alias_set ()); 3270 insn 3271 = cris_emit_movem_store (mem, GEN_INT (n_saved), 3272 -(n_saved * 4 + size), 3273 true); 3274 } 3275 else 3276 { 3277 insn 3278 = gen_rtx_SET (stack_pointer_rtx, 3279 plus_constant (Pmode, stack_pointer_rtx, 3280 -(n_saved * 4 + size))); 3281 insn = emit_insn (insn); 3282 RTX_FRAME_RELATED_P (insn) = 1; 3283 3284 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3285 set_mem_alias_set (mem, get_frame_alias_set ()); 3286 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 3287 0, true); 3288 } 3289 3290 framesize += n_saved * 4 + size; 3291 last_movem_reg = -1; 3292 size = 0; 3293 } 3294 3295 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3296 plus_constant (Pmode, 3297 stack_pointer_rtx, 3298 -4 - size))); 3299 RTX_FRAME_RELATED_P (insn) = 1; 3300 3301 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3302 set_mem_alias_set (mem, get_frame_alias_set ()); 3303 insn = emit_move_insn (mem, gen_raw_REG (SImode, regno)); 3304 RTX_FRAME_RELATED_P (insn) = 1; 3305 3306 framesize += 4 + size; 3307 size = 0; 3308 } 3309 } 3310 } 3311 3312 /* Check after, if we could movem all registers. This is the normal case. */ 3313 if (last_movem_reg != -1) 3314 { 3315 int n_saved 3316 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1; 3317 3318 /* Side-effect on movem was not usable for CRIS v0..3. Also only 3319 do it if side-effects insns are allowed. */ 3320 if ((last_movem_reg + 1) * 4 + size >= 64 3321 && (last_movem_reg + 1) * 4 + size <= 128 3322 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) 3323 && TARGET_SIDE_EFFECT_PREFIXES) 3324 { 3325 mem 3326 = gen_rtx_MEM (SImode, 3327 plus_constant (Pmode, stack_pointer_rtx, 3328 -(n_saved * 4 + size))); 3329 set_mem_alias_set (mem, get_frame_alias_set ()); 3330 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 3331 -(n_saved * 4 + size), true); 3332 } 3333 else 3334 { 3335 insn 3336 = gen_rtx_SET (stack_pointer_rtx, 3337 plus_constant (Pmode, stack_pointer_rtx, 3338 -(n_saved * 4 + size))); 3339 insn = emit_insn (insn); 3340 RTX_FRAME_RELATED_P (insn) = 1; 3341 3342 mem = gen_rtx_MEM (SImode, stack_pointer_rtx); 3343 set_mem_alias_set (mem, get_frame_alias_set ()); 3344 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true); 3345 } 3346 3347 framesize += n_saved * 4 + size; 3348 /* We have to put outgoing argument space after regs. */ 3349 if (cfoa_size) 3350 { 3351 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3352 plus_constant (Pmode, 3353 stack_pointer_rtx, 3354 -cfoa_size))); 3355 RTX_FRAME_RELATED_P (insn) = 1; 3356 framesize += cfoa_size; 3357 } 3358 } 3359 else if ((size + cfoa_size) > 0) 3360 { 3361 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, 3362 plus_constant (Pmode, 3363 stack_pointer_rtx, 3364 -(cfoa_size + size)))); 3365 RTX_FRAME_RELATED_P (insn) = 1; 3366 framesize += size + cfoa_size; 3367 } 3368 3369 /* Set up the PIC register, if it is used. */ 3370 if (got_really_used) 3371 { 3372 rtx got 3373 = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT); 3374 emit_move_insn (pic_offset_table_rtx, got); 3375 3376 /* FIXME: This is a cover-up for flow2 messing up; it doesn't 3377 follow exceptional paths and tries to delete the GOT load as 3378 unused, if it isn't used on the non-exceptional paths. Other 3379 ports have similar or other cover-ups, or plain bugs marking 3380 the GOT register load as maybe-dead. To see this, remove the 3381 line below and try libsupc++/vec.cc or a trivial 3382 "static void y (); void x () {try {y ();} catch (...) {}}". */ 3383 emit_use (pic_offset_table_rtx); 3384 } 3385 3386 if (cris_max_stackframe && framesize > cris_max_stackframe) 3387 warning (0, "stackframe too big: %d bytes", framesize); 3388 } 3389 3390 /* The expander for the epilogue pattern. */ 3391 3392 void 3393 cris_expand_epilogue (void) 3394 { 3395 int regno; 3396 int size = get_frame_size (); 3397 int last_movem_reg = -1; 3398 int argspace_offset = crtl->outgoing_args_size; 3399 int pretend = crtl->args.pretend_args_size; 3400 rtx mem; 3401 bool return_address_on_stack = cris_return_address_on_stack (); 3402 /* A reference may have been optimized out 3403 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1) 3404 so check that it's still used. */ 3405 int got_really_used = false; 3406 int n_movem_regs = 0; 3407 3408 if (!TARGET_PROLOGUE_EPILOGUE) 3409 return; 3410 3411 if (crtl->uses_pic_offset_table) 3412 { 3413 /* A reference may have been optimized out (like the abort () in 3414 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that 3415 it's still used. */ 3416 push_topmost_sequence (); 3417 got_really_used 3418 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); 3419 pop_topmost_sequence (); 3420 } 3421 3422 /* Align byte count of stack frame. */ 3423 if (TARGET_STACK_ALIGN) 3424 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; 3425 3426 /* Check how many saved regs we can movem. They start at r0 and must 3427 be contiguous. */ 3428 for (regno = 0; 3429 regno < FIRST_PSEUDO_REGISTER; 3430 regno++) 3431 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 3432 { 3433 n_movem_regs++; 3434 3435 if (regno == last_movem_reg + 1) 3436 last_movem_reg = regno; 3437 else 3438 break; 3439 } 3440 3441 /* If there was only one register that really needed to be saved 3442 through movem, don't use movem. */ 3443 if (n_movem_regs == 1) 3444 last_movem_reg = -1; 3445 3446 /* Now emit "normal" move insns for all regs higher than the movem 3447 regs. */ 3448 for (regno = FIRST_PSEUDO_REGISTER - 1; 3449 regno > last_movem_reg; 3450 regno--) 3451 if (cris_reg_saved_in_regsave_area (regno, got_really_used)) 3452 { 3453 rtx insn; 3454 3455 if (argspace_offset) 3456 { 3457 /* There is an area for outgoing parameters located before 3458 the saved registers. We have to adjust for that. */ 3459 emit_insn (gen_rtx_SET (stack_pointer_rtx, 3460 plus_constant (Pmode, stack_pointer_rtx, 3461 argspace_offset))); 3462 /* Make sure we only do this once. */ 3463 argspace_offset = 0; 3464 } 3465 3466 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, 3467 stack_pointer_rtx)); 3468 set_mem_alias_set (mem, get_frame_alias_set ()); 3469 insn = emit_move_insn (gen_raw_REG (SImode, regno), mem); 3470 3471 /* Whenever we emit insns with post-incremented addresses 3472 ourselves, we must add a post-inc note manually. */ 3473 REG_NOTES (insn) 3474 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3475 } 3476 3477 /* If we have any movem-restore, do it now. */ 3478 if (last_movem_reg != -1) 3479 { 3480 rtx insn; 3481 3482 if (argspace_offset) 3483 { 3484 emit_insn (gen_rtx_SET (stack_pointer_rtx, 3485 plus_constant (Pmode, stack_pointer_rtx, 3486 argspace_offset))); 3487 argspace_offset = 0; 3488 } 3489 3490 mem = gen_rtx_MEM (SImode, 3491 gen_rtx_POST_INC (SImode, stack_pointer_rtx)); 3492 set_mem_alias_set (mem, get_frame_alias_set ()); 3493 insn 3494 = emit_insn (cris_gen_movem_load (mem, 3495 GEN_INT (last_movem_reg + 1), 0)); 3496 /* Whenever we emit insns with post-incremented addresses 3497 ourselves, we must add a post-inc note manually. */ 3498 if (side_effects_p (PATTERN (insn))) 3499 REG_NOTES (insn) 3500 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3501 } 3502 3503 /* If we don't clobber all of the allocated stack area (we've already 3504 deallocated saved registers), GCC might want to schedule loads from 3505 the stack to *after* the stack-pointer restore, which introduces an 3506 interrupt race condition. This happened for the initial-value 3507 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of 3508 other failure for that test). It also happened for the stack slot 3509 for the return value in (one version of) 3510 linux/fs/dcache.c:__d_lookup, at least with "-O2 3511 -fno-omit-frame-pointer". */ 3512 3513 /* Restore frame pointer if necessary. */ 3514 if (frame_pointer_needed) 3515 { 3516 rtx insn; 3517 3518 emit_insn (gen_cris_frame_deallocated_barrier ()); 3519 3520 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); 3521 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, 3522 stack_pointer_rtx)); 3523 set_mem_alias_set (mem, get_frame_alias_set ()); 3524 insn = emit_move_insn (frame_pointer_rtx, mem); 3525 3526 /* Whenever we emit insns with post-incremented addresses 3527 ourselves, we must add a post-inc note manually. */ 3528 REG_NOTES (insn) 3529 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3530 } 3531 else if ((size + argspace_offset) != 0) 3532 { 3533 emit_insn (gen_cris_frame_deallocated_barrier ()); 3534 3535 /* If there was no frame-pointer to restore sp from, we must 3536 explicitly deallocate local variables. */ 3537 3538 /* Handle space for outgoing parameters that hasn't been handled 3539 yet. */ 3540 size += argspace_offset; 3541 3542 emit_insn (gen_rtx_SET (stack_pointer_rtx, 3543 plus_constant (Pmode, stack_pointer_rtx, size))); 3544 } 3545 3546 /* If this function has no pushed register parameters 3547 (stdargs/varargs), and if it is not a leaf function, then we have 3548 the return address on the stack. */ 3549 if (return_address_on_stack && pretend == 0) 3550 { 3551 if (TARGET_V32 || crtl->calls_eh_return) 3552 { 3553 rtx mem; 3554 rtx insn; 3555 rtx srpreg = gen_raw_REG (SImode, CRIS_SRP_REGNUM); 3556 mem = gen_rtx_MEM (SImode, 3557 gen_rtx_POST_INC (SImode, 3558 stack_pointer_rtx)); 3559 set_mem_alias_set (mem, get_frame_alias_set ()); 3560 insn = emit_move_insn (srpreg, mem); 3561 3562 /* Whenever we emit insns with post-incremented addresses 3563 ourselves, we must add a post-inc note manually. */ 3564 REG_NOTES (insn) 3565 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3566 3567 if (crtl->calls_eh_return) 3568 emit_insn (gen_addsi3 (stack_pointer_rtx, 3569 stack_pointer_rtx, 3570 gen_raw_REG (SImode, CRIS_STACKADJ_REG))); 3571 cris_expand_return (false); 3572 } 3573 else 3574 cris_expand_return (true); 3575 3576 return; 3577 } 3578 3579 /* If we pushed some register parameters, then adjust the stack for 3580 them. */ 3581 if (pretend != 0) 3582 { 3583 /* If SRP is stored on the way, we need to restore it first. */ 3584 if (return_address_on_stack) 3585 { 3586 rtx mem; 3587 rtx srpreg = gen_raw_REG (SImode, CRIS_SRP_REGNUM); 3588 rtx insn; 3589 3590 mem = gen_rtx_MEM (SImode, 3591 gen_rtx_POST_INC (SImode, 3592 stack_pointer_rtx)); 3593 set_mem_alias_set (mem, get_frame_alias_set ()); 3594 insn = emit_move_insn (srpreg, mem); 3595 3596 /* Whenever we emit insns with post-incremented addresses 3597 ourselves, we must add a post-inc note manually. */ 3598 REG_NOTES (insn) 3599 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); 3600 } 3601 3602 emit_insn (gen_rtx_SET (stack_pointer_rtx, 3603 plus_constant (Pmode, stack_pointer_rtx, 3604 pretend))); 3605 } 3606 3607 /* Perform the "physical" unwinding that the EH machinery calculated. */ 3608 if (crtl->calls_eh_return) 3609 emit_insn (gen_addsi3 (stack_pointer_rtx, 3610 stack_pointer_rtx, 3611 gen_raw_REG (SImode, CRIS_STACKADJ_REG))); 3612 cris_expand_return (false); 3613 } 3614 3615 /* Worker function for generating movem from mem for load_multiple. */ 3616 3617 rtx 3618 cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) 3619 { 3620 int nregs = INTVAL (nregs_rtx); 3621 rtvec vec; 3622 int eltno = 1; 3623 int i; 3624 rtx srcreg = XEXP (src, 0); 3625 unsigned int regno = nregs - 1; 3626 int regno_inc = -1; 3627 3628 if (TARGET_V32) 3629 { 3630 regno = 0; 3631 regno_inc = 1; 3632 } 3633 3634 if (GET_CODE (srcreg) == POST_INC) 3635 srcreg = XEXP (srcreg, 0); 3636 3637 CRIS_ASSERT (REG_P (srcreg)); 3638 3639 /* Don't use movem for just one insn. The insns are equivalent except 3640 for the pipeline hazard (on v32); movem does not forward the loaded 3641 registers so there's a three cycles penalty for their use. */ 3642 if (nregs == 1) 3643 return gen_movsi (gen_rtx_REG (SImode, 0), src); 3644 3645 vec = rtvec_alloc (nprefix + nregs 3646 + (GET_CODE (XEXP (src, 0)) == POST_INC)); 3647 3648 if (GET_CODE (XEXP (src, 0)) == POST_INC) 3649 { 3650 RTVEC_ELT (vec, nprefix + 1) 3651 = gen_rtx_SET (srcreg, plus_constant (Pmode, srcreg, nregs * 4)); 3652 eltno++; 3653 } 3654 3655 src = replace_equiv_address (src, srcreg); 3656 RTVEC_ELT (vec, nprefix) 3657 = gen_rtx_SET (gen_rtx_REG (SImode, regno), src); 3658 regno += regno_inc; 3659 3660 for (i = 1; i < nregs; i++, eltno++) 3661 { 3662 RTVEC_ELT (vec, nprefix + eltno) 3663 = gen_rtx_SET (gen_rtx_REG (SImode, regno), 3664 adjust_address_nv (src, SImode, i * 4)); 3665 regno += regno_inc; 3666 } 3667 3668 return gen_rtx_PARALLEL (VOIDmode, vec); 3669 } 3670 3671 /* Worker function for generating movem to mem. If FRAME_RELATED, notes 3672 are added that the dwarf2 machinery understands. */ 3673 3674 rtx 3675 cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, 3676 bool frame_related) 3677 { 3678 int nregs = INTVAL (nregs_rtx); 3679 rtvec vec; 3680 int eltno = 1; 3681 int i; 3682 rtx insn; 3683 rtx destreg = XEXP (dest, 0); 3684 unsigned int regno = nregs - 1; 3685 int regno_inc = -1; 3686 3687 if (TARGET_V32) 3688 { 3689 regno = 0; 3690 regno_inc = 1; 3691 } 3692 3693 if (GET_CODE (destreg) == POST_INC) 3694 increment += nregs * 4; 3695 3696 if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS) 3697 destreg = XEXP (destreg, 0); 3698 3699 CRIS_ASSERT (REG_P (destreg)); 3700 3701 /* Don't use movem for just one insn. The insns are equivalent except 3702 for the pipeline hazard (on v32); movem does not forward the loaded 3703 registers so there's a three cycles penalty for use. */ 3704 if (nregs == 1) 3705 { 3706 rtx mov = gen_rtx_SET (dest, gen_rtx_REG (SImode, 0)); 3707 3708 if (increment == 0) 3709 { 3710 insn = emit_insn (mov); 3711 if (frame_related) 3712 RTX_FRAME_RELATED_P (insn) = 1; 3713 return insn; 3714 } 3715 3716 /* If there was a request for a side-effect, create the ordinary 3717 parallel. */ 3718 vec = rtvec_alloc (2); 3719 3720 RTVEC_ELT (vec, 0) = mov; 3721 RTVEC_ELT (vec, 1) = gen_rtx_SET (destreg, plus_constant (Pmode, destreg, 3722 increment)); 3723 if (frame_related) 3724 { 3725 RTX_FRAME_RELATED_P (mov) = 1; 3726 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; 3727 } 3728 } 3729 else 3730 { 3731 vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0)); 3732 RTVEC_ELT (vec, 0) 3733 = gen_rtx_SET (replace_equiv_address (dest, 3734 plus_constant (Pmode, destreg, 3735 increment)), 3736 gen_rtx_REG (SImode, regno)); 3737 regno += regno_inc; 3738 3739 /* The dwarf2 info wants this mark on each component in a parallel 3740 that's part of the prologue (though it's optional on the first 3741 component). */ 3742 if (frame_related) 3743 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1; 3744 3745 if (increment != 0) 3746 { 3747 RTVEC_ELT (vec, 1) 3748 = gen_rtx_SET (destreg, plus_constant (Pmode, destreg, 3749 increment != 0 3750 ? increment : nregs * 4)); 3751 eltno++; 3752 3753 if (frame_related) 3754 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1; 3755 3756 /* Don't call adjust_address_nv on a post-incremented address if 3757 we can help it. */ 3758 if (GET_CODE (XEXP (dest, 0)) == POST_INC) 3759 dest = replace_equiv_address (dest, destreg); 3760 } 3761 3762 for (i = 1; i < nregs; i++, eltno++) 3763 { 3764 RTVEC_ELT (vec, eltno) 3765 = gen_rtx_SET (adjust_address_nv (dest, SImode, i * 4), 3766 gen_rtx_REG (SImode, regno)); 3767 if (frame_related) 3768 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1; 3769 regno += regno_inc; 3770 } 3771 } 3772 3773 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); 3774 3775 /* Because dwarf2out.c handles the insns in a parallel as a sequence, 3776 we need to keep the stack adjustment separate, after the 3777 MEM-setters. Else the stack-adjustment in the second component of 3778 the parallel would be mishandled; the offsets for the SETs that 3779 follow it would be wrong. We prepare for this by adding a 3780 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE 3781 followed by the increment. Note that we have FRAME_RELATED_P on 3782 all the SETs, including the original stack adjustment SET in the 3783 parallel. */ 3784 if (frame_related) 3785 { 3786 if (increment != 0) 3787 { 3788 rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1)); 3789 XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0)); 3790 for (i = 1; i < nregs; i++) 3791 XVECEXP (seq, 0, i) 3792 = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1)); 3793 XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1)); 3794 add_reg_note (insn, REG_FRAME_RELATED_EXPR, seq); 3795 } 3796 3797 RTX_FRAME_RELATED_P (insn) = 1; 3798 } 3799 3800 return insn; 3801 } 3802 3803 /* Worker function for expanding the address for PIC function calls. */ 3804 3805 void 3806 cris_expand_pic_call_address (rtx *opp, rtx *markerp) 3807 { 3808 rtx op = *opp; 3809 3810 gcc_assert (flag_pic && MEM_P (op)); 3811 op = XEXP (op, 0); 3812 3813 /* It might be that code can be generated that jumps to 0 (or to a 3814 specific address). Don't die on that. (There is a 3815 testcase.) */ 3816 if (CONSTANT_P (op) && !CONST_INT_P (op)) 3817 { 3818 enum cris_symbol_type t = cris_symbol_type_of (op); 3819 3820 CRIS_ASSERT (can_create_pseudo_p ()); 3821 3822 /* For local symbols (non-PLT), just get the plain symbol 3823 reference into a register. For symbols that can be PLT, make 3824 them PLT. */ 3825 if (t == cris_rel_symbol) 3826 { 3827 /* For v32, we're fine as-is; just PICify the symbol. Forcing 3828 into a register caused performance regression for 3.2.1, 3829 observable in __floatdidf and elsewhere in libgcc. */ 3830 if (TARGET_V32) 3831 { 3832 rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op); 3833 HOST_WIDE_INT offs = get_integer_term (op); 3834 3835 /* We can't get calls to sym+N, N integer, can we? */ 3836 gcc_assert (offs == 0); 3837 3838 op = gen_rtx_CONST (Pmode, 3839 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 3840 CRIS_UNSPEC_PCREL)); 3841 } 3842 else 3843 op = force_reg (Pmode, op); 3844 3845 /* A local call. */ 3846 *markerp = const0_rtx; 3847 } 3848 else if (t == cris_got_symbol) 3849 { 3850 if (TARGET_AVOID_GOTPLT) 3851 { 3852 /* Change a "jsr sym" into (allocate register rM, rO) 3853 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM" 3854 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and 3855 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))" 3856 for v32. */ 3857 rtx tem, rm, ro; 3858 3859 crtl->uses_pic_offset_table = 1; 3860 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), 3861 TARGET_V32 3862 ? CRIS_UNSPEC_PLT_PCREL 3863 : CRIS_UNSPEC_PLT_GOTREL); 3864 tem = gen_rtx_CONST (Pmode, tem); 3865 if (TARGET_V32) 3866 op = tem; 3867 else 3868 { 3869 rm = gen_reg_rtx (Pmode); 3870 emit_move_insn (rm, tem); 3871 ro = gen_reg_rtx (Pmode); 3872 if (expand_binop (Pmode, add_optab, rm, 3873 pic_offset_table_rtx, 3874 ro, 0, OPTAB_LIB_WIDEN) != ro) 3875 internal_error ("expand_binop failed in movsi got"); 3876 op = ro; 3877 } 3878 } 3879 else 3880 { 3881 /* Change a "jsr sym" into (allocate register rM, rO) 3882 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM" 3883 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access 3884 marked as not trapping and not aliasing. No "move.d 3885 [rO],rP" as that would invite to re-use of a value 3886 that should not be reused. FIXME: Need a peephole2 3887 for cases when this is cse:d from the call, to change 3888 back to just get the PLT entry address, so we don't 3889 resolve the same symbol over and over (the memory 3890 access of the PLTGOT isn't constant). */ 3891 rtx tem, mem, rm, ro; 3892 3893 gcc_assert (can_create_pseudo_p ()); 3894 crtl->uses_pic_offset_table = 1; 3895 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), 3896 CRIS_UNSPEC_PLTGOTREAD); 3897 rm = gen_reg_rtx (Pmode); 3898 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); 3899 ro = gen_reg_rtx (Pmode); 3900 if (expand_binop (Pmode, add_optab, rm, 3901 pic_offset_table_rtx, 3902 ro, 0, OPTAB_LIB_WIDEN) != ro) 3903 internal_error ("expand_binop failed in movsi got"); 3904 mem = gen_rtx_MEM (Pmode, ro); 3905 3906 /* This MEM doesn't alias anything. Whether it aliases 3907 other same symbols is unimportant. */ 3908 set_mem_alias_set (mem, new_alias_set ()); 3909 MEM_NOTRAP_P (mem) = 1; 3910 op = mem; 3911 } 3912 3913 /* We need to prepare this call to go through the PLT; we 3914 need to make GOT available. */ 3915 *markerp = pic_offset_table_rtx; 3916 } 3917 else 3918 /* Can't possibly get anything else for a function-call, right? */ 3919 fatal_insn ("unidentifiable call op", op); 3920 3921 /* If the validizing variant is called, it will try to validize 3922 the address as a valid any-operand constant, but as it's only 3923 valid for calls and moves, it will fail and always be forced 3924 into a register. */ 3925 *opp = replace_equiv_address_nv (*opp, op); 3926 } 3927 else 3928 /* Can't tell what locality a call to a non-constant address has; 3929 better make the GOT register alive at it. 3930 FIXME: Can we see whether the register has known constant 3931 contents? */ 3932 *markerp = pic_offset_table_rtx; 3933 } 3934 3935 /* Make sure operands are in the right order for an addsi3 insn as 3936 generated by a define_split. Nothing but REG_P as the first 3937 operand is recognized by addsi3 after reload. OPERANDS contains 3938 the operands, with the first at OPERANDS[N] and the second at 3939 OPERANDS[N+1]. */ 3940 3941 void 3942 cris_order_for_addsi3 (rtx *operands, int n) 3943 { 3944 if (!REG_P (operands[n])) 3945 { 3946 rtx tem = operands[n]; 3947 operands[n] = operands[n + 1]; 3948 operands[n + 1] = tem; 3949 } 3950 } 3951 3952 /* Use from within code, from e.g. PRINT_OPERAND and 3953 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit 3954 different things depending on whether code operand or constant is 3955 emitted. */ 3956 3957 static void 3958 cris_output_addr_const (FILE *file, rtx x) 3959 { 3960 in_code++; 3961 output_addr_const (file, x); 3962 in_code--; 3963 } 3964 3965 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */ 3966 3967 void 3968 cris_asm_output_symbol_ref (FILE *file, rtx x) 3969 { 3970 gcc_assert (GET_CODE (x) == SYMBOL_REF); 3971 3972 if (flag_pic && in_code > 0) 3973 { 3974 const char *origstr = XSTR (x, 0); 3975 const char *str; 3976 str = (* targetm.strip_name_encoding) (origstr); 3977 assemble_name (file, str); 3978 3979 /* Sanity check. */ 3980 if (!TARGET_V32 && !crtl->uses_pic_offset_table) 3981 output_operand_lossage ("PIC register isn't set up"); 3982 } 3983 else 3984 assemble_name (file, XSTR (x, 0)); 3985 } 3986 3987 /* Worker function for ASM_OUTPUT_LABEL_REF. */ 3988 3989 void 3990 cris_asm_output_label_ref (FILE *file, char *buf) 3991 { 3992 if (flag_pic && in_code > 0) 3993 { 3994 assemble_name (file, buf); 3995 3996 /* Sanity check. */ 3997 if (!TARGET_V32 && !crtl->uses_pic_offset_table) 3998 internal_error ("emitting PIC operand, but PIC register " 3999 "isn%'t set up"); 4000 } 4001 else 4002 assemble_name (file, buf); 4003 } 4004 4005 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ 4006 4007 static bool 4008 cris_output_addr_const_extra (FILE *file, rtx xconst) 4009 { 4010 switch (GET_CODE (xconst)) 4011 { 4012 rtx x; 4013 4014 case UNSPEC: 4015 x = XVECEXP (xconst, 0, 0); 4016 CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF 4017 || GET_CODE (x) == LABEL_REF 4018 || GET_CODE (x) == CONST); 4019 output_addr_const (file, x); 4020 switch (XINT (xconst, 1)) 4021 { 4022 case CRIS_UNSPEC_PCREL: 4023 /* We only get this with -fpic/PIC to tell it apart from an 4024 invalid symbol. We can't tell here, but it should only 4025 be the operand of a call or movsi. */ 4026 gcc_assert (TARGET_V32 && flag_pic); 4027 break; 4028 4029 case CRIS_UNSPEC_PLT_PCREL: 4030 gcc_assert (TARGET_V32); 4031 fprintf (file, ":PLT"); 4032 break; 4033 4034 case CRIS_UNSPEC_PLT_GOTREL: 4035 gcc_assert (!TARGET_V32); 4036 fprintf (file, ":PLTG"); 4037 break; 4038 4039 case CRIS_UNSPEC_GOTREL: 4040 gcc_assert (!TARGET_V32); 4041 fprintf (file, ":GOTOFF"); 4042 break; 4043 4044 case CRIS_UNSPEC_GOTREAD: 4045 if (flag_pic == 1) 4046 fprintf (file, ":GOT16"); 4047 else 4048 fprintf (file, ":GOT"); 4049 break; 4050 4051 case CRIS_UNSPEC_PLTGOTREAD: 4052 if (flag_pic == 1) 4053 fprintf (file, CRIS_GOTPLT_SUFFIX "16"); 4054 else 4055 fprintf (file, CRIS_GOTPLT_SUFFIX); 4056 break; 4057 4058 default: 4059 gcc_unreachable (); 4060 } 4061 return true; 4062 4063 default: 4064 return false; 4065 } 4066 } 4067 4068 /* Worker function for TARGET_STRUCT_VALUE_RTX. */ 4069 4070 static rtx 4071 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, 4072 int incoming ATTRIBUTE_UNUSED) 4073 { 4074 return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM); 4075 } 4076 4077 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ 4078 4079 static void 4080 cris_setup_incoming_varargs (cumulative_args_t ca_v, 4081 const function_arg_info &, 4082 int *pretend_arg_size, 4083 int second_time) 4084 { 4085 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); 4086 4087 if (ca->regs < CRIS_MAX_ARGS_IN_REGS) 4088 { 4089 int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs; 4090 cfun->machine->stdarg_regs = stdarg_regs; 4091 *pretend_arg_size = stdarg_regs * 4; 4092 } 4093 4094 if (TARGET_PDEBUG) 4095 fprintf (asm_out_file, 4096 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n", 4097 ca->regs, *pretend_arg_size, second_time); 4098 } 4099 4100 /* Return true if ARG must be passed by invisible reference. 4101 For cris, we pass <= 8 bytes by value, others by reference. */ 4102 4103 static bool 4104 cris_pass_by_reference (cumulative_args_t, const function_arg_info &arg) 4105 { 4106 return (targetm.calls.must_pass_in_stack (arg) 4107 || CRIS_FUNCTION_ARG_SIZE (arg.mode, arg.type) > 8); 4108 } 4109 4110 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments 4111 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the 4112 best code size and speed for gcc, ipps and products in gcc-2.7.2. */ 4113 4114 machine_mode 4115 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, 4116 machine_mode mode, 4117 int *punsignedp ATTRIBUTE_UNUSED, 4118 const_tree fntype ATTRIBUTE_UNUSED, 4119 int for_return) 4120 { 4121 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even 4122 when modifying TARGET_FUNCTION_VALUE to return the promoted mode). 4123 Maybe pointless as of now, but let's keep the old behavior. */ 4124 if (for_return == 1) 4125 return mode; 4126 return CRIS_PROMOTED_MODE (mode, *punsignedp, type); 4127 } 4128 4129 /* Atomic types require alignment to be at least their "natural" size. */ 4130 4131 static unsigned int 4132 cris_atomic_align_for_mode (machine_mode mode) 4133 { 4134 return GET_MODE_BITSIZE (mode); 4135 } 4136 4137 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the 4138 time being. */ 4139 4140 static rtx 4141 cris_function_value(const_tree type, 4142 const_tree func ATTRIBUTE_UNUSED, 4143 bool outgoing ATTRIBUTE_UNUSED) 4144 { 4145 return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG); 4146 } 4147 4148 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the 4149 time being. */ 4150 4151 static rtx 4152 cris_libcall_value (machine_mode mode, 4153 const_rtx fun ATTRIBUTE_UNUSED) 4154 { 4155 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG); 4156 } 4157 4158 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the 4159 time being. */ 4160 4161 static bool 4162 cris_function_value_regno_p (const unsigned int regno) 4163 { 4164 return (regno == CRIS_FIRST_ARG_REG); 4165 } 4166 4167 static int 4168 cris_arg_partial_bytes (cumulative_args_t ca, const function_arg_info &arg) 4169 { 4170 if (get_cumulative_args (ca)->regs == CRIS_MAX_ARGS_IN_REGS - 1 4171 && !targetm.calls.must_pass_in_stack (arg) 4172 && CRIS_FUNCTION_ARG_SIZE (arg.mode, arg.type) > 4 4173 && CRIS_FUNCTION_ARG_SIZE (arg.mode, arg.type) <= 8) 4174 return UNITS_PER_WORD; 4175 else 4176 return 0; 4177 } 4178 4179 static rtx 4180 cris_function_arg_1 (cumulative_args_t ca_v, const function_arg_info &arg, 4181 bool incoming) 4182 { 4183 const CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); 4184 4185 if ((!incoming || arg.named) && ca->regs < CRIS_MAX_ARGS_IN_REGS) 4186 return gen_rtx_REG (arg.mode, CRIS_FIRST_ARG_REG + ca->regs); 4187 else 4188 return NULL_RTX; 4189 } 4190 4191 /* Worker function for TARGET_FUNCTION_ARG. 4192 The void_type_node is sent as a "closing" call. */ 4193 4194 static rtx 4195 cris_function_arg (cumulative_args_t ca, const function_arg_info &arg) 4196 { 4197 return cris_function_arg_1 (ca, arg, false); 4198 } 4199 4200 /* Worker function for TARGET_FUNCTION_INCOMING_ARG. 4201 4202 The differences between this and the previous, is that this one checks 4203 that an argument is named, since incoming stdarg/varargs arguments are 4204 pushed onto the stack, and we don't have to check against the "closing" 4205 function_arg_info::end_marker parameter. */ 4206 4207 static rtx 4208 cris_function_incoming_arg (cumulative_args_t ca, const function_arg_info &arg) 4209 { 4210 return cris_function_arg_1 (ca, arg, true); 4211 } 4212 4213 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */ 4214 4215 static void 4216 cris_function_arg_advance (cumulative_args_t ca_v, 4217 const function_arg_info &arg) 4218 { 4219 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); 4220 4221 ca->regs += (3 + CRIS_FUNCTION_ARG_SIZE (arg.mode, arg.type)) / 4; 4222 } 4223 4224 /* Worker function for TARGET_MD_ASM_ADJUST. */ 4225 4226 static rtx_insn * 4227 cris_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &inputs, 4228 vec<const char *> &constraints, 4229 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs) 4230 { 4231 /* For the time being, all asms clobber condition codes. 4232 Revisit when there's a reasonable use for inputs/outputs 4233 that mention condition codes. */ 4234 clobbers.safe_push (gen_rtx_REG (CCmode, CRIS_CC0_REGNUM)); 4235 SET_HARD_REG_BIT (clobbered_regs, CRIS_CC0_REGNUM); 4236 4237 /* Determine if the source using MOF. If it is, automatically 4238 clobbering MOF would cause it to have impossible constraints. */ 4239 4240 /* Look for a use of the MOF constraint letter: h. */ 4241 for (unsigned i = 0, n = constraints.length(); i < n; ++i) 4242 if (strchr (constraints[i], 'h') != NULL) 4243 return NULL; 4244 4245 /* Look for an output or an input that touches MOF. */ 4246 rtx mof_reg = gen_rtx_REG (SImode, CRIS_MOF_REGNUM); 4247 for (unsigned i = 0, n = outputs.length(); i < n; ++i) 4248 if (reg_overlap_mentioned_p (mof_reg, outputs[i])) 4249 return NULL; 4250 for (unsigned i = 0, n = inputs.length(); i < n; ++i) 4251 if (reg_overlap_mentioned_p (mof_reg, inputs[i])) 4252 return NULL; 4253 4254 /* No direct reference to MOF or its constraint. 4255 Clobber it for backward compatibility. */ 4256 clobbers.safe_push (mof_reg); 4257 SET_HARD_REG_BIT (clobbered_regs, CRIS_MOF_REGNUM); 4258 return NULL; 4259 } 4260 4261 /* Implement TARGET_FRAME_POINTER_REQUIRED. 4262 4263 Really only needed if the stack frame has variable length (alloca 4264 or variable sized local arguments (GNU C extension). See PR39499 and 4265 PR38609 for the reason this isn't just 0. */ 4266 4267 bool 4268 cris_frame_pointer_required (void) 4269 { 4270 return !crtl->sp_is_unchanging; 4271 } 4272 4273 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE. 4274 4275 This looks too complicated, and it is. I assigned r7 to be the 4276 static chain register, but it is call-saved, so we have to save it, 4277 and come back to restore it after the call, so we have to save srp... 4278 Anyway, trampolines are rare enough that we can cope with this 4279 somewhat lack of elegance. 4280 (Do not be tempted to "straighten up" whitespace in the asms; the 4281 assembler #NO_APP state mandates strict spacing). */ 4282 /* ??? See the i386 regparm=3 implementation that pushes the static 4283 chain value to the stack in the trampoline, and uses a call-saved 4284 register when called directly. */ 4285 4286 static void 4287 cris_asm_trampoline_template (FILE *f) 4288 { 4289 if (TARGET_V32) 4290 { 4291 /* This normally-unused nop insn acts as an instruction to 4292 the simulator to flush its instruction cache. None of 4293 the other instructions in the trampoline template suits 4294 as a trigger for V32. The pc-relative addressing mode 4295 works nicely as a trigger for V10. 4296 FIXME: Have specific V32 template (possibly avoiding the 4297 use of a special instruction). */ 4298 fprintf (f, "\tclearf x\n"); 4299 /* We have to use a register as an intermediate, choosing 4300 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM), 4301 so we can use it for address indirection and jsr target. */ 4302 fprintf (f, "\tmove $r1,$mof\n"); 4303 /* +4 */ 4304 fprintf (f, "\tmove.d 0,$r1\n"); 4305 fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]); 4306 fprintf (f, "\taddq 6,$r1\n"); 4307 fprintf (f, "\tmove $mof,[$r1]\n"); 4308 fprintf (f, "\taddq 6,$r1\n"); 4309 fprintf (f, "\tmove $srp,[$r1]\n"); 4310 /* +20 */ 4311 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4312 /* +26 */ 4313 fprintf (f, "\tmove.d 0,$r1\n"); 4314 fprintf (f, "\tjsr $r1\n"); 4315 fprintf (f, "\tsetf\n"); 4316 /* +36 */ 4317 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4318 /* +42 */ 4319 fprintf (f, "\tmove.d 0,$r1\n"); 4320 /* +48 */ 4321 fprintf (f, "\tmove.d 0,$r9\n"); 4322 fprintf (f, "\tjump $r9\n"); 4323 fprintf (f, "\tsetf\n"); 4324 } 4325 else 4326 { 4327 fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]); 4328 fprintf (f, "\tmove $srp,[$pc+22]\n"); 4329 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4330 fprintf (f, "\tjsr 0\n"); 4331 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); 4332 fprintf (f, "\tjump 0\n"); 4333 } 4334 } 4335 4336 /* Implement TARGET_TRAMPOLINE_INIT. */ 4337 4338 static void 4339 cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 4340 { 4341 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 4342 rtx tramp = XEXP (m_tramp, 0); 4343 rtx mem; 4344 4345 emit_block_move (m_tramp, assemble_trampoline_template (), 4346 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); 4347 4348 if (TARGET_V32) 4349 { 4350 mem = adjust_address (m_tramp, SImode, 6); 4351 emit_move_insn (mem, plus_constant (Pmode, tramp, 38)); 4352 mem = adjust_address (m_tramp, SImode, 22); 4353 emit_move_insn (mem, chain_value); 4354 mem = adjust_address (m_tramp, SImode, 28); 4355 emit_move_insn (mem, fnaddr); 4356 } 4357 else 4358 { 4359 mem = adjust_address (m_tramp, SImode, 10); 4360 emit_move_insn (mem, chain_value); 4361 mem = adjust_address (m_tramp, SImode, 16); 4362 emit_move_insn (mem, fnaddr); 4363 } 4364 4365 /* Note that there is no need to do anything with the cache for 4366 sake of a trampoline. */ 4367 } 4368 4369 /* Implement TARGET_HARD_REGNO_NREGS. 4370 4371 The VOIDmode test is so we can omit mode on anonymous insns. FIXME: 4372 Still needed in 2.9x, at least for Axis-20000319. */ 4373 4374 static unsigned int 4375 cris_hard_regno_nregs (unsigned int, machine_mode mode) 4376 { 4377 if (mode == VOIDmode) 4378 return 1; 4379 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); 4380 } 4381 4382 /* Implement TARGET_HARD_REGNO_MODE_OK. 4383 4384 CRIS permits all registers to hold all modes. Well, except for the 4385 condition-code register. And we can't hold larger-than-register size 4386 modes in the last special register that can hold a full 32 bits. */ 4387 static bool 4388 cris_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 4389 { 4390 return ((mode == CCmode || regno != CRIS_CC0_REGNUM) 4391 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD 4392 || (regno != CRIS_MOF_REGNUM && regno != CRIS_ACR_REGNUM))); 4393 } 4394 4395 /* Return the preferred minimum alignment for a static object. */ 4396 4397 static HOST_WIDE_INT 4398 cris_preferred_minimum_alignment (void) 4399 { 4400 if (!TARGET_CONST_ALIGN) 4401 return 8; 4402 if (TARGET_ALIGN_BY_32) 4403 return 32; 4404 return 16; 4405 } 4406 4407 /* Implement TARGET_STATIC_RTX_ALIGNMENT. */ 4408 4409 static HOST_WIDE_INT 4410 cris_static_rtx_alignment (machine_mode mode) 4411 { 4412 return MAX (cris_preferred_minimum_alignment (), GET_MODE_ALIGNMENT (mode)); 4413 } 4414 4415 /* Implement TARGET_CONSTANT_ALIGNMENT. Note that this hook has the 4416 effect of making gcc believe that ALL references to constant stuff 4417 (in code segment, like strings) have this alignment. That is a rather 4418 rushed assumption. Luckily we do not care about the "alignment" 4419 operand to builtin memcpy (only place where it counts), so it doesn't 4420 affect any bad spots. */ 4421 4422 static HOST_WIDE_INT 4423 cris_constant_alignment (const_tree, HOST_WIDE_INT basic_align) 4424 { 4425 return MAX (cris_preferred_minimum_alignment (), basic_align); 4426 } 4427 4428 #if 0 4429 /* Various small functions to replace macros. Only called from a 4430 debugger. They might collide with gcc functions or system functions, 4431 so only emit them when '#if 1' above. */ 4432 4433 enum rtx_code Get_code (rtx); 4434 4435 enum rtx_code 4436 Get_code (rtx x) 4437 { 4438 return GET_CODE (x); 4439 } 4440 4441 const char *Get_mode (rtx); 4442 4443 const char * 4444 Get_mode (rtx x) 4445 { 4446 return GET_MODE_NAME (GET_MODE (x)); 4447 } 4448 4449 rtx Xexp (rtx, int); 4450 4451 rtx 4452 Xexp (rtx x, int n) 4453 { 4454 return XEXP (x, n); 4455 } 4456 4457 rtx Xvecexp (rtx, int, int); 4458 4459 rtx 4460 Xvecexp (rtx x, int n, int m) 4461 { 4462 return XVECEXP (x, n, m); 4463 } 4464 4465 int Get_rtx_len (rtx); 4466 4467 int 4468 Get_rtx_len (rtx x) 4469 { 4470 return GET_RTX_LENGTH (GET_CODE (x)); 4471 } 4472 4473 /* Use upper-case to distinguish from local variables that are sometimes 4474 called next_insn and prev_insn. */ 4475 4476 rtx Next_insn (rtx); 4477 4478 rtx 4479 Next_insn (rtx insn) 4480 { 4481 return NEXT_INSN (insn); 4482 } 4483 4484 rtx Prev_insn (rtx); 4485 4486 rtx 4487 Prev_insn (rtx insn) 4488 { 4489 return PREV_INSN (insn); 4490 } 4491 #endif 4492 4493 #include "gt-cris.h" 4494 4495 /* 4496 * Local variables: 4497 * eval: (c-set-style "gnu") 4498 * indent-tabs-mode: t 4499 * End: 4500 */ 4501