1 /* Target Definitions for TI C6X. 2 Copyright (C) 2010-2013 Free Software Foundation, Inc. 3 Contributed by Andrew Jenner <andrew@codesourcery.com> 4 Contributed by Bernd Schmidt <bernds@codesourcery.com> 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 3, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #ifndef GCC_C6X_H 23 #define GCC_C6X_H 24 25 /* Feature bit definitions that enable specific insns. */ 26 #define C6X_INSNS_C62X 1 27 #define C6X_INSNS_C64X 2 28 #define C6X_INSNS_C64XP 4 29 #define C6X_INSNS_C67X 8 30 #define C6X_INSNS_C67XP 16 31 #define C6X_INSNS_C674X 32 32 #define C6X_INSNS_ATOMIC 64 33 #define C6X_INSNS_ALL_CPU_BITS 127 34 35 #define C6X_DEFAULT_INSN_MASK \ 36 (C6X_INSNS_C62X | C6X_INSNS_C64X | C6X_INSNS_C64XP) 37 38 /* A mask of allowed insn types, as defined above. */ 39 extern unsigned long c6x_insn_mask; 40 41 /* Value of -march= */ 42 extern c6x_cpu_t c6x_arch; 43 #define C6X_DEFAULT_ARCH C6X_CPU_C64XP 44 45 /* True if the target has C64x instructions. */ 46 #define TARGET_INSNS_64 ((c6x_insn_mask & C6X_INSNS_C64X) != 0) 47 /* True if the target has C64x+ instructions. */ 48 #define TARGET_INSNS_64PLUS ((c6x_insn_mask & C6X_INSNS_C64XP) != 0) 49 /* True if the target has C67x instructions. */ 50 #define TARGET_INSNS_67 ((c6x_insn_mask & C6X_INSNS_C67X) != 0) 51 /* True if the target has C67x+ instructions. */ 52 #define TARGET_INSNS_67PLUS ((c6x_insn_mask & C6X_INSNS_C67XP) != 0) 53 54 /* True if the target supports doubleword loads. */ 55 #define TARGET_LDDW (TARGET_INSNS_64 || TARGET_INSNS_67) 56 /* True if the target supports doubleword loads. */ 57 #define TARGET_STDW TARGET_INSNS_64 58 /* True if the target supports the MPY32 family of instructions. */ 59 #define TARGET_MPY32 TARGET_INSNS_64PLUS 60 /* True if the target has floating point hardware. */ 61 #define TARGET_FP TARGET_INSNS_67 62 /* True if the target has C67x+ floating point extensions. */ 63 #define TARGET_FP_EXT TARGET_INSNS_67PLUS 64 65 #define TARGET_DEFAULT 0 66 67 /* Run-time Target. */ 68 69 #define TARGET_CPU_CPP_BUILTINS() \ 70 do \ 71 { \ 72 builtin_assert ("machine=tic6x"); \ 73 builtin_assert ("cpu=tic6x"); \ 74 builtin_define ("__TMS320C6X__"); \ 75 builtin_define ("_TMS320C6X"); \ 76 \ 77 if (TARGET_DSBT) \ 78 builtin_define ("__DSBT__"); \ 79 \ 80 if (TARGET_BIG_ENDIAN) \ 81 builtin_define ("_BIG_ENDIAN"); \ 82 else \ 83 builtin_define ("_LITTLE_ENDIAN"); \ 84 \ 85 switch (c6x_arch) \ 86 { \ 87 case C6X_CPU_C62X: \ 88 builtin_define ("_TMS320C6200"); \ 89 break; \ 90 \ 91 case C6X_CPU_C64XP: \ 92 builtin_define ("_TMS320C6400_PLUS"); \ 93 /* ... fall through ... */ \ 94 case C6X_CPU_C64X: \ 95 builtin_define ("_TMS320C6400"); \ 96 break; \ 97 \ 98 case C6X_CPU_C67XP: \ 99 builtin_define ("_TMS320C6700_PLUS"); \ 100 /* ... fall through ... */ \ 101 case C6X_CPU_C67X: \ 102 builtin_define ("_TMS320C6700"); \ 103 break; \ 104 \ 105 case C6X_CPU_C674X: \ 106 builtin_define ("_TMS320C6740"); \ 107 builtin_define ("_TMS320C6700_PLUS"); \ 108 builtin_define ("_TMS320C6700"); \ 109 builtin_define ("_TMS320C6400_PLUS"); \ 110 builtin_define ("_TMS320C6400"); \ 111 break; \ 112 } \ 113 } while (0) 114 115 #define OPTION_DEFAULT_SPECS \ 116 {"arch", "%{!march=*:-march=%(VALUE)}" } 117 118 /* Storage Layout. */ 119 120 #define BITS_BIG_ENDIAN 0 121 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 122 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 123 124 #define REG_WORDS_BIG_ENDIAN 0 125 126 #define UNITS_PER_WORD 4 127 #define PARM_BOUNDARY 8 128 #define STACK_BOUNDARY 64 129 #define FUNCTION_BOUNDARY 32 130 #define BIGGEST_ALIGNMENT 64 131 #define STRICT_ALIGNMENT 1 132 133 /* The ABI requires static arrays must be at least 8 byte aligned. 134 Really only externally visible arrays must be aligned this way, as 135 only those are directly visible from another compilation unit. But 136 we don't have that information available here. */ 137 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 138 (((ALIGN) < BITS_PER_UNIT * 8 && TREE_CODE (TYPE) == ARRAY_TYPE) \ 139 ? BITS_PER_UNIT * 8 : (ALIGN)) 140 141 /* Type Layout. */ 142 143 #define DEFAULT_SIGNED_CHAR 1 144 145 #undef SIZE_TYPE 146 #define SIZE_TYPE "unsigned int" 147 #undef PTRDIFF_TYPE 148 #define PTRDIFF_TYPE "int" 149 150 /* Registers. */ 151 152 #define FIRST_PSEUDO_REGISTER 67 153 #define FIXED_REGISTERS \ 154 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 156 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ 157 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 158 1, 1, 1} 159 #define CALL_USED_REGISTERS \ 160 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ 161 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 162 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, \ 163 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 164 1, 1, 1} 165 166 /* This lists call-used non-predicate registers first, followed by call-used 167 registers, followed by predicate registers. We want to avoid allocating 168 the predicate registers for other uses as much as possible. */ 169 #define REG_ALLOC_ORDER \ 170 { \ 171 REG_A0, REG_A3, REG_A4, REG_A5, REG_A6, REG_A7, REG_A8, REG_A9, \ 172 REG_A16, REG_A17, REG_A18, REG_A19, REG_A20, REG_A21, REG_A22, REG_A23, \ 173 REG_A24, REG_A25, REG_A26, REG_A27, REG_A28, REG_A29, REG_A30, REG_A31, \ 174 REG_B4, REG_B5, REG_B6, REG_B7, REG_B8, REG_B9, REG_B16, \ 175 REG_B17, REG_B18, REG_B19, REG_B20, REG_B21, REG_B22, REG_B23, REG_B24, \ 176 REG_B25, REG_B26, REG_B27, REG_B28, REG_B29, REG_B30, REG_B31, \ 177 REG_A10, REG_A11, REG_A12, REG_A13, REG_A14, REG_A15, \ 178 REG_B3, REG_B10, REG_B11, REG_B12, REG_B13, REG_B14, REG_B15, \ 179 REG_A1, REG_A2, REG_B0, REG_B1, REG_B2, REG_ILC \ 180 } 181 182 #define HARD_REGNO_NREGS(regno, mode) \ 183 ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) \ 184 / UNITS_PER_WORD) 185 186 #define HARD_REGNO_MODE_OK(reg, mode) (GET_MODE_SIZE (mode) <= UNITS_PER_WORD \ 187 ? 1 : ((reg) & 1) == 0) 188 189 #define MODES_TIEABLE_P(mode1, mode2) \ 190 ((mode1) == (mode2) || \ 191 (GET_MODE_SIZE (mode1) <= UNITS_PER_WORD && \ 192 GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)) 193 194 195 /* Register Classes. */ 196 197 enum reg_class 198 { 199 NO_REGS, 200 PREDICATE_A_REGS, 201 PREDICATE_B_REGS, 202 PREDICATE_REGS, 203 PICREG, 204 SPREG, 205 CALL_USED_B_REGS, 206 NONPREDICATE_A_REGS, 207 NONPREDICATE_B_REGS, 208 NONPREDICATE_REGS, 209 A_REGS, 210 B_REGS, 211 GENERAL_REGS, 212 ALL_REGS, 213 LIM_REG_CLASSES 214 }; 215 216 #define N_REG_CLASSES (int) LIM_REG_CLASSES 217 218 #define REG_CLASS_NAMES { \ 219 "NO_REGS", \ 220 "PREDICATE_A_REGS", \ 221 "PREDICATE_B_REGS", \ 222 "PREDICATE_REGS", \ 223 "PICREG", \ 224 "SPREG", \ 225 "CALL_USED_B_REGS", \ 226 "NONPREDICATE_A_REGS", \ 227 "NONPREDICATE_B_REGS", \ 228 "NONPREDICATE_REGS", \ 229 "A_REGS", \ 230 "B_REGS", \ 231 "GENERAL_REGS", \ 232 "ALL_REGS" } 233 234 #define REG_CLASS_CONTENTS \ 235 { \ 236 /* NO_REGS. */ \ 237 { 0x00000000, 0x00000000, 0 }, \ 238 /* PREDICATE_A_REGS. */ \ 239 { 0x00000006, 0x00000000, 0 }, \ 240 /* PREDICATE_B_REGS. */ \ 241 { 0x00000000, 0x00000007, 0 }, \ 242 /* PREDICATE_REGS. */ \ 243 { 0x00000006, 0x00000007, 0 }, \ 244 /* PICREG. */ \ 245 { 0x00000000, 0x00004000, 0 }, \ 246 /* SPREG. */ \ 247 { 0x00000000, 0x00008000, 0 }, \ 248 /* CALL_USED_B_REGS. */ \ 249 { 0x00000000, 0xFFFF03FF, 0 }, \ 250 /* NONPREDICATE_A_REGS. */ \ 251 { 0xFFFFFFF9, 0x00000000, 0 }, \ 252 /* NONPREDICATE_B_REGS. */ \ 253 { 0x00000000, 0xFFFFFFF8, 0 }, \ 254 /* NONPREDICATE_REGS. */ \ 255 { 0xFFFFFFF9, 0xFFFFFFF8, 0 }, \ 256 /* A_REGS. */ \ 257 { 0xFFFFFFFF, 0x00000000, 3 }, \ 258 /* B_REGS. */ \ 259 { 0x00000000, 0xFFFFFFFF, 3 }, \ 260 /* GENERAL_REGS. */ \ 261 { 0xFFFFFFFF, 0xFFFFFFFF, 3 }, \ 262 /* ALL_REGS. */ \ 263 { 0xFFFFFFFF, 0xFFFFFFFF, 7 }, \ 264 } 265 266 #define A_REGNO_P(N) ((N) <= REG_A31) 267 #define B_REGNO_P(N) ((N) >= REG_B0 && (N) <= REG_B31) 268 269 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X))) 270 #define CROSS_OPERANDS(X0,X1) \ 271 (A_REG_P (X0) == A_REG_P (X1) ? CROSS_N : CROSS_Y) 272 273 #define REGNO_REG_CLASS(reg) \ 274 ((reg) >= REG_A1 && (reg) <= REG_A2 ? PREDICATE_A_REGS \ 275 : (reg) == REG_A0 && TARGET_INSNS_64 ? PREDICATE_A_REGS \ 276 : (reg) >= REG_B0 && (reg) <= REG_B2 ? PREDICATE_B_REGS \ 277 : A_REGNO_P (reg) ? NONPREDICATE_A_REGS \ 278 : call_used_regs[reg] ? CALL_USED_B_REGS : B_REGS) 279 280 #define BASE_REG_CLASS ALL_REGS 281 #define INDEX_REG_CLASS ALL_REGS 282 283 #define REGNO_OK_FOR_BASE_STRICT_P(X) \ 284 ((X) < FIRST_PSEUDO_REGISTER \ 285 || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER)) 286 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X) 1 287 288 #define REGNO_OK_FOR_INDEX_STRICT_P(X) \ 289 ((X) < FIRST_PSEUDO_REGISTER \ 290 || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER)) 291 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(X) 1 292 293 #ifdef REG_OK_STRICT 294 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_STRICT_P (X) 295 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_STRICT_P (X) 296 #else 297 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (X) 298 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (X) 299 #endif 300 301 #define CLASS_MAX_NREGS(class, mode) \ 302 ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 303 304 #define REGNO_OK_FOR_INDIRECT_JUMP_P(REGNO, MODE) B_REGNO_P (REGNO) 305 306 /* Stack and Calling. */ 307 308 /* SP points to 4 bytes below the first word of the frame. */ 309 #define STACK_POINTER_OFFSET 4 310 /* Likewise for AP (which is the incoming stack pointer). */ 311 #define FIRST_PARM_OFFSET(fundecl) 4 312 #define STARTING_FRAME_OFFSET 0 313 #define FRAME_GROWS_DOWNWARD 1 314 #define STACK_GROWS_DOWNWARD 315 316 #define STACK_POINTER_REGNUM REG_B15 317 #define HARD_FRAME_POINTER_REGNUM REG_A15 318 /* These two always get eliminated in favour of the stack pointer 319 or the hard frame pointer. */ 320 #define FRAME_POINTER_REGNUM REG_FRAME 321 #define ARG_POINTER_REGNUM REG_ARGP 322 323 #define PIC_OFFSET_TABLE_REGNUM REG_B14 324 325 /* We keep the stack pointer constant rather than using push/pop 326 instructions. */ 327 #define ACCUMULATE_OUTGOING_ARGS 1 328 329 /* Before the prologue, the return address is in the B3 register. */ 330 #define RETURN_ADDR_REGNO REG_B3 331 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNO) 332 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (RETURN_ADDR_REGNO) 333 334 #define RETURN_ADDR_RTX(COUNT, FRAME) c6x_return_addr_rtx (COUNT) 335 336 #define INCOMING_FRAME_SP_OFFSET 0 337 #define ARG_POINTER_CFA_OFFSET(fundecl) 0 338 339 #define STATIC_CHAIN_REGNUM REG_A2 340 341 struct c6x_args { 342 /* Number of arguments to pass in registers. */ 343 int nregs; 344 /* Number of arguments passed in registers so far. */ 345 int count; 346 }; 347 348 #define CUMULATIVE_ARGS struct c6x_args 349 350 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \ 351 c6x_init_cumulative_args (&cum, fntype, libname, n_named_args) 352 353 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 354 (c6x_block_reg_pad_upward (MODE, TYPE, FIRST) ? upward : downward) 355 356 #define FUNCTION_ARG_REGNO_P(r) \ 357 (((r) >= REG_A4 && (r) <= REG_A13) || ((r) >= REG_B4 && (r) <= REG_B13)) 358 359 #define DEFAULT_PCC_STRUCT_RETURN 0 360 361 #define FUNCTION_PROFILER(file, labelno) \ 362 fatal_error ("profiling is not yet implemented for this architecture") 363 364 365 /* Trampolines. */ 366 #define TRAMPOLINE_SIZE 32 367 #define TRAMPOLINE_ALIGNMENT 256 368 369 #define ELIMINABLE_REGS \ 370 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 371 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 372 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 373 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 374 375 /* Define the offset between two registers, one to be eliminated, and the other 376 its replacement, at the start of a routine. */ 377 378 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 379 ((OFFSET) = c6x_initial_elimination_offset ((FROM), (TO))) 380 381 /* Addressing Modes. */ 382 383 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P(x) && GET_CODE(x) != CONST_DOUBLE) 384 #define MAX_REGS_PER_ADDRESS 2 385 386 #define HAVE_PRE_DECREMENT 1 387 #define HAVE_POST_DECREMENT 1 388 #define HAVE_PRE_INCREMENT 1 389 #define HAVE_POST_INCREMENT 1 390 391 /* Register forms are available, but due to scaling we currently don't 392 support them. */ 393 #define HAVE_PRE_MODIFY_DISP 1 394 #define HAVE_POST_MODIFY_DISP 1 395 396 #define LEGITIMATE_PIC_OPERAND_P(X) \ 397 (!symbolic_operand (X, SImode)) 398 399 struct GTY(()) machine_function 400 { 401 /* True if we expanded a sibling call. */ 402 int contains_sibcall; 403 }; 404 405 /* Costs. */ 406 #define NO_FUNCTION_CSE 1 407 408 #define SLOW_BYTE_ACCESS 0 409 410 #define BRANCH_COST(speed_p, predictable_p) 6 411 412 413 /* Model costs for the vectorizer. */ 414 415 /* Cost of conditional branch. */ 416 #ifndef TARG_COND_BRANCH_COST 417 #define TARG_COND_BRANCH_COST 6 418 #endif 419 420 /* Cost of any scalar operation, excluding load and store. */ 421 #ifndef TARG_SCALAR_STMT_COST 422 #define TARG_SCALAR_STMT_COST 1 423 #endif 424 425 /* Cost of scalar load. */ 426 #undef TARG_SCALAR_LOAD_COST 427 #define TARG_SCALAR_LOAD_COST 2 /* load + rotate */ 428 429 /* Cost of scalar store. */ 430 #undef TARG_SCALAR_STORE_COST 431 #define TARG_SCALAR_STORE_COST 10 432 433 /* Cost of any vector operation, excluding load, store, 434 or vector to scalar operation. */ 435 #undef TARG_VEC_STMT_COST 436 #define TARG_VEC_STMT_COST 1 437 438 /* Cost of vector to scalar operation. */ 439 #undef TARG_VEC_TO_SCALAR_COST 440 #define TARG_VEC_TO_SCALAR_COST 1 441 442 /* Cost of scalar to vector operation. */ 443 #undef TARG_SCALAR_TO_VEC_COST 444 #define TARG_SCALAR_TO_VEC_COST 1 445 446 /* Cost of aligned vector load. */ 447 #undef TARG_VEC_LOAD_COST 448 #define TARG_VEC_LOAD_COST 1 449 450 /* Cost of misaligned vector load. */ 451 #undef TARG_VEC_UNALIGNED_LOAD_COST 452 #define TARG_VEC_UNALIGNED_LOAD_COST 2 453 454 /* Cost of vector store. */ 455 #undef TARG_VEC_STORE_COST 456 #define TARG_VEC_STORE_COST 1 457 458 /* Cost of vector permutation. */ 459 #ifndef TARG_VEC_PERMUTE_COST 460 #define TARG_VEC_PERMUTE_COST 1 461 #endif 462 463 /* ttype entries (the only interesting data references used) are 464 sb-relative got-indirect (aka .ehtype). */ 465 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 466 (((code) == 0 && (data) == 1) ? (DW_EH_PE_datarel | DW_EH_PE_indirect) \ 467 : DW_EH_PE_absptr) 468 469 /* This should be the same as the definition in elfos.h, plus the call 470 to output special unwinding directives. */ 471 #undef ASM_DECLARE_FUNCTION_NAME 472 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ 473 do \ 474 { \ 475 c6x_output_file_unwind (FILE); \ 476 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ 477 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ 478 ASM_OUTPUT_LABEL (FILE, NAME); \ 479 } \ 480 while (0) 481 482 /* This should be the same as the definition in elfos.h, plus the call 483 to output special unwinding directives. */ 484 #undef ASM_DECLARE_FUNCTION_SIZE 485 #define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ 486 c6x_function_end (STREAM, NAME) 487 488 /* Arbitrarily choose A4/A5. */ 489 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) + 4 : INVALID_REGNUM) 490 491 /* The register that holds the return address in exception handlers. */ 492 #define C6X_EH_STACKADJ_REGNUM 3 493 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, C6X_EH_STACKADJ_REGNUM) 494 495 496 /* Assembler Format. */ 497 498 #define DWARF2_ASM_LINE_DEBUG_INFO 1 499 500 #undef ASM_APP_ON 501 #define ASM_APP_ON "\t; #APP \n" 502 #undef ASM_APP_OFF 503 #define ASM_APP_OFF "\t; #NO_APP \n" 504 505 #define ASM_OUTPUT_COMMON(stream, name, size, rounded) 506 #define ASM_OUTPUT_LOCAL(stream, name, size, rounded) 507 508 #define GLOBAL_ASM_OP "\t.global\t" 509 510 #define REGISTER_NAMES \ 511 { \ 512 "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", \ 513 "A8", "A9", "A10", "A11", "A12", "A13", "A14", "A15", \ 514 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23", \ 515 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31", \ 516 "B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7", \ 517 "B8", "B9", "B10", "B11", "B12", "B13", "B14", "B15", \ 518 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23", \ 519 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31", \ 520 "FP", "ARGP", "ILC" } 521 522 #define DBX_REGISTER_NUMBER(N) (dbx_register_map[(N)]) 523 524 extern unsigned const dbx_register_map[FIRST_PSEUDO_REGISTER]; 525 526 #define FINAL_PRESCAN_INSN c6x_final_prescan_insn 527 528 #define TEXT_SECTION_ASM_OP ".text;" 529 #define DATA_SECTION_ASM_OP ".data;" 530 531 #define ASM_OUTPUT_ALIGN(stream, power) \ 532 do \ 533 { \ 534 if (power) \ 535 fprintf ((stream), "\t.align\t%d\n", power); \ 536 } \ 537 while (0) 538 539 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 540 do { char __buf[256]; \ 541 fprintf (FILE, "\t.long\t"); \ 542 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 543 assemble_name (FILE, __buf); \ 544 fputc ('\n', FILE); \ 545 } while (0) 546 547 /* Determine whether to place EXP (an expression or a decl) should be 548 placed into one of the small data sections. */ 549 #define PLACE_IN_SDATA_P(EXP) \ 550 (c6x_sdata_mode == C6X_SDATA_NONE ? false \ 551 : c6x_sdata_mode == C6X_SDATA_ALL ? true \ 552 : !AGGREGATE_TYPE_P (TREE_TYPE (EXP))) 553 554 #define SCOMMON_ASM_OP "\t.scomm\t" 555 556 #undef ASM_OUTPUT_ALIGNED_DECL_COMMON 557 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN) \ 558 do \ 559 { \ 560 if (DECL != NULL && PLACE_IN_SDATA_P (DECL)) \ 561 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \ 562 else \ 563 fprintf ((FILE), "%s", COMMON_ASM_OP); \ 564 assemble_name ((FILE), (NAME)); \ 565 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ 566 } \ 567 while (0) 568 569 /* This says how to output assembler code to declare an 570 uninitialized internal linkage data object. */ 571 572 #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL 573 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \ 574 do { \ 575 if (PLACE_IN_SDATA_P (DECL)) \ 576 switch_to_section (sbss_section); \ 577 else \ 578 switch_to_section (bss_section); \ 579 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ 580 if (!flag_inhibit_size_directive) \ 581 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 582 ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT)); \ 583 ASM_OUTPUT_LABEL(FILE, NAME); \ 584 ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1); \ 585 } while (0) 586 587 #define CASE_VECTOR_PC_RELATIVE flag_pic 588 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic 589 590 #define ADDR_VEC_ALIGN(VEC) (JUMP_TABLES_IN_TEXT_SECTION ? 5 : 2) 591 592 /* This is how to output an element of a case-vector that is relative. */ 593 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 594 do { char buf[100]; \ 595 fputs ("\t.long ", FILE); \ 596 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 597 assemble_name (FILE, buf); \ 598 putc ('-', FILE); \ 599 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 600 assemble_name (FILE, buf); \ 601 putc ('\n', FILE); \ 602 } while (0) 603 604 /* Misc. */ 605 606 #define CASE_VECTOR_MODE SImode 607 #define MOVE_MAX 4 608 #define MOVE_RATIO(SPEED) 4 609 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1 610 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 611 #define Pmode SImode 612 #define FUNCTION_MODE QImode 613 614 #define CPU_UNITS_QUERY 1 615 616 extern int c6x_initial_flag_pic; 617 618 #endif /* GCC_C6X_H */ 619