xref: /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/avr/avr-devices.c (revision 8feb0f0b7eaff0608f8350bbfa3098827b4bb91b)
1*8feb0f0bSmrg /* Copyright (C) 2009-2020 Free Software Foundation, Inc.
21debfc3dSmrg    Contributed by Anatoly Sokolov (aesok@post.ru)
31debfc3dSmrg 
41debfc3dSmrg    This file is part of GCC.
51debfc3dSmrg 
61debfc3dSmrg    GCC is free software; you can redistribute it and/or modify
71debfc3dSmrg    it under the terms of the GNU General Public License as published by
81debfc3dSmrg    the Free Software Foundation; either version 3, or (at your option)
91debfc3dSmrg    any later version.
101debfc3dSmrg 
111debfc3dSmrg    GCC is distributed in the hope that it will be useful,
121debfc3dSmrg    but WITHOUT ANY WARRANTY; without even the implied warranty of
131debfc3dSmrg    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
141debfc3dSmrg    GNU General Public License for more details.
151debfc3dSmrg 
161debfc3dSmrg    You should have received a copy of the GNU General Public License
171debfc3dSmrg    along with GCC; see the file COPYING3.  If not see
181debfc3dSmrg    <http://www.gnu.org/licenses/>.  */
191debfc3dSmrg 
201debfc3dSmrg #ifndef IN_GEN_AVR_MMCU_TEXI
21a2dc1f3fSmrg #define IN_TARGET_CODE 1
22a2dc1f3fSmrg 
231debfc3dSmrg #include "config.h"
241debfc3dSmrg #include "system.h"
251debfc3dSmrg #include "coretypes.h"
261debfc3dSmrg #include "tm.h"
271debfc3dSmrg #include "diagnostic.h"
281debfc3dSmrg #endif /* IN_GEN_AVR_MMCU_TEXI */
291debfc3dSmrg 
301debfc3dSmrg #include "avr-arch.h"
311debfc3dSmrg 
321debfc3dSmrg /* List of all known AVR MCU architectures.
331debfc3dSmrg    Order as of enum avr_arch from avr.h.  */
341debfc3dSmrg 
351debfc3dSmrg const avr_arch_t
361debfc3dSmrg avr_arch_types[] =
371debfc3dSmrg {
381debfc3dSmrg   /* unknown device specified */
39a2dc1f3fSmrg   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, NULL, AVR_MMCU_DEFAULT },
401debfc3dSmrg   /*
41a2dc1f3fSmrg     A  M  J  LM E  E  E  X  R  T  d S     FPO     S O   A
42a2dc1f3fSmrg     S  U  M  PO L  L  I  M  A  I  a t     lMff    F ff  r
43a2dc1f3fSmrg     M  L  P  MV P  P  J  E  M  N  t a     a s     R s   c
44a2dc1f3fSmrg              XW M  M  M  G  P  Y  a r     s e       e   h
45a2dc1f3fSmrg                    X  P  A  D       t     h t       t   ID   */
46a2dc1f3fSmrg   { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "1",   "avr1"  },
47a2dc1f3fSmrg   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "2",   "avr2"  },
48a2dc1f3fSmrg   { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "25",  "avr25" },
49a2dc1f3fSmrg   { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "3",   "avr3"  },
50a2dc1f3fSmrg   { 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0x0060, 0,      32, "31",  "avr31" },
51a2dc1f3fSmrg   { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "35",  "avr35" },
52a2dc1f3fSmrg   { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "4",   "avr4"  },
53a2dc1f3fSmrg   { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0x0060, 0,      32, "5",   "avr5"  },
54a2dc1f3fSmrg   { 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0x0060, 0,      32, "51",  "avr51" },
55a2dc1f3fSmrg   { 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0x0060, 0,      32, "6",   "avr6"  },
561debfc3dSmrg 
57a2dc1f3fSmrg   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0x0040, 0x4000, 0, "100", "avrtiny" },
58a2dc1f3fSmrg   { 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0x2000, 0,      0, "102", "avrxmega2" },
59a2dc1f3fSmrg   { 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0x2000, 0x8000, 0, "103", "avrxmega3" },
60a2dc1f3fSmrg   { 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0x2000, 0,      0, "104", "avrxmega4" },
61a2dc1f3fSmrg   { 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0x2000, 0,      0, "105", "avrxmega5" },
62a2dc1f3fSmrg   { 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0x2000, 0,      0, "106", "avrxmega6" },
63a2dc1f3fSmrg   { 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0x2000, 0,      0, "107", "avrxmega7" }
641debfc3dSmrg };
651debfc3dSmrg 
661debfc3dSmrg const avr_arch_info_t
671debfc3dSmrg avr_texinfo[] =
681debfc3dSmrg {
691debfc3dSmrg   { ARCH_AVR1,
701debfc3dSmrg     "This ISA is implemented by the minimal AVR core and supported "
711debfc3dSmrg     "for assembler only." },
721debfc3dSmrg   { ARCH_AVR2,
731debfc3dSmrg     "``Classic'' devices with up to 8@tie{}KiB of program memory." },
741debfc3dSmrg   { ARCH_AVR25,
751debfc3dSmrg     "``Classic'' devices with up to 8@tie{}KiB of program memory and with "
761debfc3dSmrg     "the @code{MOVW} instruction." },
771debfc3dSmrg   { ARCH_AVR3,
781debfc3dSmrg     "``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of "
791debfc3dSmrg     "program memory." },
801debfc3dSmrg   { ARCH_AVR31,
811debfc3dSmrg     "``Classic'' devices with 128@tie{}KiB of program memory." },
821debfc3dSmrg   { ARCH_AVR35,
831debfc3dSmrg     "``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of "
841debfc3dSmrg     "program memory and with the @code{MOVW} instruction." },
851debfc3dSmrg   { ARCH_AVR4,
861debfc3dSmrg     "``Enhanced'' devices with up to 8@tie{}KiB of program memory." },
871debfc3dSmrg   { ARCH_AVR5,
881debfc3dSmrg     "``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of "
891debfc3dSmrg     "program memory." },
901debfc3dSmrg   { ARCH_AVR51,
911debfc3dSmrg     "``Enhanced'' devices with 128@tie{}KiB of program memory." },
921debfc3dSmrg   { ARCH_AVR6,
931debfc3dSmrg     "``Enhanced'' devices with 3-byte PC, i.e.@: with more than 128@tie{}KiB "
941debfc3dSmrg     "of program memory." },
951debfc3dSmrg   { ARCH_AVRTINY,
961debfc3dSmrg     "``TINY'' Tiny core devices with 512@tie{}B up to 4@tie{}KiB of "
971debfc3dSmrg     "program memory." },
981debfc3dSmrg   { ARCH_AVRXMEGA2,
991debfc3dSmrg     "``XMEGA'' devices with more than 8@tie{}KiB and up to 64@tie{}KiB "
1001debfc3dSmrg     "of program memory." },
101a2dc1f3fSmrg   { ARCH_AVRXMEGA3,
102a2dc1f3fSmrg     "``XMEGA'' devices with up to 64@tie{}KiB of combined program memory "
103a2dc1f3fSmrg     "and RAM, and with program memory visible in the RAM address space." },
1041debfc3dSmrg   { ARCH_AVRXMEGA4,
1051debfc3dSmrg     "``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB "
1061debfc3dSmrg     "of program memory." },
1071debfc3dSmrg   { ARCH_AVRXMEGA5,
1081debfc3dSmrg     "``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB "
1091debfc3dSmrg     "of program memory and more than 64@tie{}KiB of RAM." },
1101debfc3dSmrg   { ARCH_AVRXMEGA6,
1111debfc3dSmrg     "``XMEGA'' devices with more than 128@tie{}KiB of program memory." },
1121debfc3dSmrg   { ARCH_AVRXMEGA7,
1131debfc3dSmrg     "``XMEGA'' devices with more than 128@tie{}KiB of program memory "
1141debfc3dSmrg     "and more than 64@tie{}KiB of RAM." }
1151debfc3dSmrg };
1161debfc3dSmrg 
1171debfc3dSmrg const avr_mcu_t
1181debfc3dSmrg avr_mcu_types[] =
1191debfc3dSmrg {
120a2dc1f3fSmrg #define AVR_MCU(NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, TEXT_SEC, FLASH_SIZE, PMOFF) \
121a2dc1f3fSmrg   { NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, TEXT_SEC, FLASH_SIZE, PMOFF },
1221debfc3dSmrg #include "avr-mcus.def"
1231debfc3dSmrg #undef AVR_MCU
1241debfc3dSmrg     /* End of list.  */
125a2dc1f3fSmrg   { NULL, ARCH_UNKNOWN, AVR_ISA_NONE, NULL, 0, 0, 0, 0 }
1261debfc3dSmrg };
1271debfc3dSmrg 
1281debfc3dSmrg 
1291debfc3dSmrg 
1301debfc3dSmrg 
1311debfc3dSmrg #ifndef IN_GEN_AVR_MMCU_TEXI
1321debfc3dSmrg 
1331debfc3dSmrg static char*
avr_archs_str(void)1341debfc3dSmrg avr_archs_str (void)
1351debfc3dSmrg {
1361debfc3dSmrg   char *archs = concat ("", NULL);
1371debfc3dSmrg 
1381debfc3dSmrg   // Build of core architectures' names.
1391debfc3dSmrg 
1401debfc3dSmrg   for (const avr_mcu_t *mcu = avr_mcu_types; mcu->name; mcu++)
1411debfc3dSmrg     if (!mcu->macro)
1421debfc3dSmrg       archs = concat (archs, " ", avr_arch_types[mcu->arch_id].name, NULL);
1431debfc3dSmrg 
1441debfc3dSmrg   return archs;
1451debfc3dSmrg }
1461debfc3dSmrg 
1471debfc3dSmrg 
1481debfc3dSmrg void
avr_inform_core_architectures(void)1491debfc3dSmrg avr_inform_core_architectures (void)
1501debfc3dSmrg {
1511debfc3dSmrg   char *archs = avr_archs_str ();
1521debfc3dSmrg   inform (input_location, "supported core architectures:%s", archs);
1531debfc3dSmrg   free (archs);
1541debfc3dSmrg }
1551debfc3dSmrg 
1561debfc3dSmrg #endif // IN_GEN_AVR_MMCU_TEXI
157