1 /* Definitions of types that are used to store AVR architecture and 2 device information. 3 Copyright (C) 2012-2015 Free Software Foundation, Inc. 4 Contributed by Georg-Johann Lay (avr@gjlay.de) 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #ifndef AVR_ARCH_H 23 #define AVR_ARCH_H 24 25 #define AVR_MMCU_DEFAULT "avr2" 26 27 /* This enum supplies indices into the avr_arch_types[] table below. */ 28 29 enum avr_arch_id 30 { 31 ARCH_UNKNOWN, 32 ARCH_AVR1, 33 ARCH_AVR2, 34 ARCH_AVR25, 35 ARCH_AVR3, 36 ARCH_AVR31, 37 ARCH_AVR35, 38 ARCH_AVR4, 39 ARCH_AVR5, 40 ARCH_AVR51, 41 ARCH_AVR6, 42 ARCH_AVRTINY, 43 ARCH_AVRXMEGA2, 44 ARCH_AVRXMEGA4, 45 ARCH_AVRXMEGA5, 46 ARCH_AVRXMEGA6, 47 ARCH_AVRXMEGA7 48 }; 49 50 51 /* Architecture-specific properties. */ 52 53 typedef struct 54 { 55 /* Assembler only. */ 56 int asm_only; 57 58 /* Core have 'MUL*' instructions. */ 59 int have_mul; 60 61 /* Core have 'CALL' and 'JMP' instructions. */ 62 int have_jmp_call; 63 64 /* Core have 'MOVW' and 'LPM Rx,Z' instructions. */ 65 int have_movw_lpmx; 66 67 /* Core have 'ELPM' instructions. */ 68 int have_elpm; 69 70 /* Core have 'ELPM Rx,Z' instructions. */ 71 int have_elpmx; 72 73 /* Core have 'EICALL' and 'EIJMP' instructions. */ 74 int have_eijmp_eicall; 75 76 /* This is an XMEGA core. */ 77 int xmega_p; 78 79 /* This core has the RAMPD special function register 80 and thus also the RAMPX, RAMPY and RAMPZ registers. */ 81 int have_rampd; 82 83 /* This is a TINY core. */ 84 int tiny_p; 85 86 /* Default start of data section address for architecture. */ 87 int default_data_section_start; 88 89 /* Offset between SFR address and RAM address: 90 SFR-address = RAM-address - sfr_offset */ 91 int sfr_offset; 92 93 /* Architecture id to built-in define __AVR_ARCH__ (NULL -> no macro) */ 94 const char *const macro; 95 96 /* Architecture name. */ 97 const char *const name; 98 } avr_arch_t; 99 100 101 /* Device-specific properties. */ 102 103 typedef struct 104 { 105 /* Device name. */ 106 const char *const name; 107 108 /* Index in avr_arch_types[]. */ 109 enum avr_arch_id arch_id; 110 111 /* device specific feature */ 112 int dev_attribute; 113 114 /* Must lie outside user's namespace. NULL == no macro. */ 115 const char *const macro; 116 117 /* Start of data section. */ 118 int data_section_start; 119 120 /* Start of text section. */ 121 int text_section_start; 122 123 /* Number of 64k segments in the flash. */ 124 int n_flash; 125 } avr_mcu_t; 126 127 /* AVR device specific features. 128 129 AVR_ISA_RMW 130 Only few avr devices have Read-Modify-Write (RMW) instructions 131 (XCH, LAC, LAS and LAT) 132 133 AVR_SHORT_SP 134 Stack Pointer has only 8 bit width. 135 The device / multilib has an 8-bit stack pointer (no SPH). 136 137 AVR_ERRATA_SKIP 138 Some AVR devices have a core erratum when skipping a 2-word instruction. 139 Skip instructions are: SBRC, SBRS, SBIC, SBIS, CPSE. 140 Problems will occur with return address is IRQ executes during the 141 skip sequence. 142 143 A support ticket from Atmel returned the following information: 144 145 Subject: (ATTicket:644469) On AVR skip-bug core Erratum 146 From: avr@atmel.com Date: 2011-07-27 147 (Please keep the subject when replying to this mail) 148 149 This errata exists only in AT90S8515 and ATmega103 devices. 150 151 For information please refer the following respective errata links 152 http://www.atmel.com/dyn/resources/prod_documents/doc2494.pdf 153 http://www.atmel.com/dyn/resources/prod_documents/doc1436.pdf */ 154 155 enum avr_device_specific_features 156 { 157 AVR_ISA_NONE, 158 AVR_ISA_RMW = 0x1, /* device has RMW instructions. */ 159 AVR_SHORT_SP = 0x2, /* Stack Pointer has 8 bits width. */ 160 AVR_ERRATA_SKIP = 0x4 /* device has a core erratum. */ 161 }; 162 163 /* Map architecture to its texinfo string. */ 164 165 typedef struct 166 { 167 /* Architecture ID. */ 168 enum avr_arch_id arch_id; 169 170 /* textinfo source to describe the archtiecture. */ 171 const char *texinfo; 172 } avr_arch_info_t; 173 174 /* Preprocessor macros to define depending on MCU type. */ 175 176 extern const avr_arch_t avr_arch_types[]; 177 extern const avr_arch_t *avr_arch; 178 179 extern const avr_mcu_t avr_mcu_types[]; 180 181 extern void avr_inform_devices (void); 182 extern void avr_inform_core_architectures (void); 183 184 #endif /* AVR_ARCH_H */ 185