1;; Unspec defintions. 2;; Copyright (C) 2012-2015 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; UNSPEC Usage: 22;; Note: sin and cos are no-longer used. 23;; Unspec enumerators for Neon are defined in neon.md. 24;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md 25 26(define_c_enum "unspec" [ 27 UNSPEC_PUSH_MULT ; `push multiple' operation: 28 ; operand 0 is the first register, 29 ; subsequent registers are in parallel (use ...) 30 ; expressions. 31 UNSPEC_PIC_SYM ; A symbol that has been treated properly for pic 32 ; usage, that is, we will add the pic_register 33 ; value to it before trying to dereference it. 34 UNSPEC_PIC_BASE ; Add PC and all but the last operand together, 35 ; The last operand is the number of a PIC_LABEL 36 ; that points at the containing instruction. 37 UNSPEC_PRLG_STK ; A special barrier that prevents frame accesses 38 ; being scheduled before the stack adjustment insn. 39 UNSPEC_REGISTER_USE ; As USE insns are not meaningful after reload, 40 ; this unspec is used to prevent the deletion of 41 ; instructions setting registers for EH handling 42 ; and stack frame generation. Operand 0 is the 43 ; register to "use". 44 UNSPEC_CHECK_ARCH ; Set CCs to indicate 26-bit or 32-bit mode. 45 UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction. 46 UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction. 47 UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction. 48 UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction. 49 UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction. 50 UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction. 51 UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction. 52 UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction. 53 UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction. 54 UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction. 55 UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN instruction. 56 UNSPEC_TLS ; A symbol that has been treated properly for TLS usage. 57 UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the 58 ; instruction stream. 59 UNSPEC_PIC_OFFSET ; A symbolic 12-bit OFFSET that has been treated 60 ; correctly for PIC usage. 61 UNSPEC_GOTSYM_OFF ; The offset of the start of the GOT from a 62 ; a given symbolic address. 63 UNSPEC_THUMB1_CASESI ; A Thumb1 compressed dispatch-table call. 64 UNSPEC_RBIT ; rbit operation. 65 UNSPEC_SYMBOL_OFFSET ; The offset of the start of the symbol from 66 ; another symbolic address. 67 UNSPEC_MEMORY_BARRIER ; Represent a memory barrier. 68 UNSPEC_UNALIGNED_LOAD ; Used to represent ldr/ldrh instructions that access 69 ; unaligned locations, on architectures which support 70 ; that. 71 UNSPEC_UNALIGNED_STORE ; Same for str/strh. 72 UNSPEC_PIC_UNIFIED ; Create a common pic addressing form. 73 UNSPEC_LL ; Represent an unpaired load-register-exclusive. 74 UNSPEC_VRINTZ ; Represent a float to integral float rounding 75 ; towards zero. 76 UNSPEC_VRINTP ; Represent a float to integral float rounding 77 ; towards +Inf. 78 UNSPEC_VRINTM ; Represent a float to integral float rounding 79 ; towards -Inf. 80 UNSPEC_VRINTR ; Represent a float to integral float rounding 81 ; FPSCR rounding mode. 82 UNSPEC_VRINTX ; Represent a float to integral float rounding 83 ; FPSCR rounding mode and signal inexactness. 84 UNSPEC_VRINTA ; Represent a float to integral float rounding 85 ; towards nearest, ties away from zero. 86]) 87 88(define_c_enum "unspec" [ 89 UNSPEC_WADDC ; Used by the intrinsic form of the iWMMXt WADDC instruction. 90 UNSPEC_WABS ; Used by the intrinsic form of the iWMMXt WABS instruction. 91 UNSPEC_WQMULWMR ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction. 92 UNSPEC_WQMULMR ; Used by the intrinsic form of the iWMMXt WQMULMR instruction. 93 UNSPEC_WQMULWM ; Used by the intrinsic form of the iWMMXt WQMULWM instruction. 94 UNSPEC_WQMULM ; Used by the intrinsic form of the iWMMXt WQMULM instruction. 95 UNSPEC_WQMIAxyn ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction. 96 UNSPEC_WQMIAxy ; Used by the intrinsic form of the iWMMXt WMIAxy instruction. 97 UNSPEC_TANDC ; Used by the intrinsic form of the iWMMXt TANDC instruction. 98 UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. 99 UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. 100 UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. 101]) 102 103 104;; UNSPEC_VOLATILE Usage: 105 106(define_c_enum "unspecv" [ 107 VUNSPEC_BLOCKAGE ; `blockage' insn to prevent scheduling across an 108 ; insn in the code. 109 VUNSPEC_EPILOGUE ; `epilogue' insn, used to represent any part of the 110 ; instruction epilogue sequence that isn't expanded 111 ; into normal RTL. Used for both normal and sibcall 112 ; epilogues. 113 VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap 114 ; modes from arm to thumb. 115 VUNSPEC_ALIGN ; `align' insn. Used at the head of a minipool table 116 ; for inlined constants. 117 VUNSPEC_POOL_END ; `end-of-table'. Used to mark the end of a minipool 118 ; table. 119 VUNSPEC_POOL_1 ; `pool-entry(1)'. An entry in the constant pool for 120 ; an 8-bit object. 121 VUNSPEC_POOL_2 ; `pool-entry(2)'. An entry in the constant pool for 122 ; a 16-bit object. 123 VUNSPEC_POOL_4 ; `pool-entry(4)'. An entry in the constant pool for 124 ; a 32-bit object. 125 VUNSPEC_POOL_8 ; `pool-entry(8)'. An entry in the constant pool for 126 ; a 64-bit object. 127 VUNSPEC_POOL_16 ; `pool-entry(16)'. An entry in the constant pool for 128 ; a 128-bit object. 129 VUNSPEC_TMRC ; Used by the iWMMXt TMRC instruction. 130 VUNSPEC_TMCR ; Used by the iWMMXt TMCR instruction. 131 VUNSPEC_ALIGN8 ; 8-byte alignment version of VUNSPEC_ALIGN 132 VUNSPEC_WCMP_EQ ; Used by the iWMMXt WCMPEQ instructions 133 VUNSPEC_WCMP_GTU ; Used by the iWMMXt WCMPGTU instructions 134 VUNSPEC_WCMP_GT ; Used by the iwMMXT WCMPGT instructions 135 VUNSPEC_EH_RETURN ; Use to override the return address for exception 136 ; handling. 137 VUNSPEC_ATOMIC_CAS ; Represent an atomic compare swap. 138 VUNSPEC_ATOMIC_XCHG ; Represent an atomic exchange. 139 VUNSPEC_ATOMIC_OP ; Represent an atomic operation. 140 VUNSPEC_LL ; Represent a load-register-exclusive. 141 VUNSPEC_LDRD_ATOMIC ; Represent an LDRD used as an atomic DImode load. 142 VUNSPEC_SC ; Represent a store-register-exclusive. 143 VUNSPEC_LAX ; Represent a load-register-acquire-exclusive. 144 VUNSPEC_SLX ; Represent a store-register-release-exclusive. 145 VUNSPEC_LDA ; Represent a store-register-acquire. 146 VUNSPEC_STL ; Represent a store-register-release. 147 VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. 148 VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content. 149]) 150 151;; Enumerators for NEON unspecs. 152(define_c_enum "unspec" [ 153 UNSPEC_ASHIFT_SIGNED 154 UNSPEC_ASHIFT_UNSIGNED 155 UNSPEC_CRC32B 156 UNSPEC_CRC32H 157 UNSPEC_CRC32W 158 UNSPEC_CRC32CB 159 UNSPEC_CRC32CH 160 UNSPEC_CRC32CW 161 UNSPEC_AESD 162 UNSPEC_AESE 163 UNSPEC_AESIMC 164 UNSPEC_AESMC 165 UNSPEC_SHA1C 166 UNSPEC_SHA1M 167 UNSPEC_SHA1P 168 UNSPEC_SHA1H 169 UNSPEC_SHA1SU0 170 UNSPEC_SHA1SU1 171 UNSPEC_SHA256H 172 UNSPEC_SHA256H2 173 UNSPEC_SHA256SU0 174 UNSPEC_SHA256SU1 175 UNSPEC_VMULLP64 176 UNSPEC_LOAD_COUNT 177 UNSPEC_VABD_F 178 UNSPEC_VABD_S 179 UNSPEC_VABD_U 180 UNSPEC_VABDL_S 181 UNSPEC_VABDL_U 182 UNSPEC_VADD 183 UNSPEC_VADDHN 184 UNSPEC_VRADDHN 185 UNSPEC_VADDL_S 186 UNSPEC_VADDL_U 187 UNSPEC_VADDW_S 188 UNSPEC_VADDW_U 189 UNSPEC_VBSL 190 UNSPEC_VCAGE 191 UNSPEC_VCAGT 192 UNSPEC_VCEQ 193 UNSPEC_VCGE 194 UNSPEC_VCGEU 195 UNSPEC_VCGT 196 UNSPEC_VCGTU 197 UNSPEC_VCLS 198 UNSPEC_VCONCAT 199 UNSPEC_VCVT 200 UNSPEC_VCVT_S 201 UNSPEC_VCVT_U 202 UNSPEC_VCVT_S_N 203 UNSPEC_VCVT_U_N 204 UNSPEC_VEXT 205 UNSPEC_VHADD_S 206 UNSPEC_VHADD_U 207 UNSPEC_VRHADD_S 208 UNSPEC_VRHADD_U 209 UNSPEC_VHSUB_S 210 UNSPEC_VHSUB_U 211 UNSPEC_VLD1 212 UNSPEC_VLD1_LANE 213 UNSPEC_VLD2 214 UNSPEC_VLD2_DUP 215 UNSPEC_VLD2_LANE 216 UNSPEC_VLD3 217 UNSPEC_VLD3A 218 UNSPEC_VLD3B 219 UNSPEC_VLD3_DUP 220 UNSPEC_VLD3_LANE 221 UNSPEC_VLD4 222 UNSPEC_VLD4A 223 UNSPEC_VLD4B 224 UNSPEC_VLD4_DUP 225 UNSPEC_VLD4_LANE 226 UNSPEC_VMAX 227 UNSPEC_VMAX_U 228 UNSPEC_VMIN 229 UNSPEC_VMIN_U 230 UNSPEC_VMLA 231 UNSPEC_VMLA_LANE 232 UNSPEC_VMLAL_S 233 UNSPEC_VMLAL_U 234 UNSPEC_VMLAL_S_LANE 235 UNSPEC_VMLAL_U_LANE 236 UNSPEC_VMLS 237 UNSPEC_VMLS_LANE 238 UNSPEC_VMLSL_S 239 UNSPEC_VMLSL_U 240 UNSPEC_VMLSL_S_LANE 241 UNSPEC_VMLSL_U_LANE 242 UNSPEC_VMLSL_LANE 243 UNSPEC_VMOVL_S 244 UNSPEC_VMOVL_U 245 UNSPEC_VMOVN 246 UNSPEC_VMUL 247 UNSPEC_VMULL_P 248 UNSPEC_VMULL_S 249 UNSPEC_VMULL_U 250 UNSPEC_VMUL_LANE 251 UNSPEC_VMULL_S_LANE 252 UNSPEC_VMULL_U_LANE 253 UNSPEC_VPADAL_S 254 UNSPEC_VPADAL_U 255 UNSPEC_VPADD 256 UNSPEC_VPADDL_S 257 UNSPEC_VPADDL_U 258 UNSPEC_VPMAX 259 UNSPEC_VPMAX_U 260 UNSPEC_VPMIN 261 UNSPEC_VPMIN_U 262 UNSPEC_VPSMAX 263 UNSPEC_VPSMIN 264 UNSPEC_VPUMAX 265 UNSPEC_VPUMIN 266 UNSPEC_VQABS 267 UNSPEC_VQADD_S 268 UNSPEC_VQADD_U 269 UNSPEC_VQDMLAL 270 UNSPEC_VQDMLAL_LANE 271 UNSPEC_VQDMLSL 272 UNSPEC_VQDMLSL_LANE 273 UNSPEC_VQDMULH 274 UNSPEC_VQDMULH_LANE 275 UNSPEC_VQRDMULH 276 UNSPEC_VQRDMULH_LANE 277 UNSPEC_VQDMULL 278 UNSPEC_VQDMULL_LANE 279 UNSPEC_VQMOVN_S 280 UNSPEC_VQMOVN_U 281 UNSPEC_VQMOVUN 282 UNSPEC_VQNEG 283 UNSPEC_VQSHL_S 284 UNSPEC_VQSHL_U 285 UNSPEC_VQRSHL_S 286 UNSPEC_VQRSHL_U 287 UNSPEC_VQSHL_S_N 288 UNSPEC_VQSHL_U_N 289 UNSPEC_VQSHLU_N 290 UNSPEC_VQSHRN_S_N 291 UNSPEC_VQSHRN_U_N 292 UNSPEC_VQRSHRN_S_N 293 UNSPEC_VQRSHRN_U_N 294 UNSPEC_VQSHRUN_N 295 UNSPEC_VQRSHRUN_N 296 UNSPEC_VQSUB_S 297 UNSPEC_VQSUB_U 298 UNSPEC_VRECPE 299 UNSPEC_VRECPS 300 UNSPEC_VREV16 301 UNSPEC_VREV32 302 UNSPEC_VREV64 303 UNSPEC_VRSQRTE 304 UNSPEC_VRSQRTS 305 UNSPEC_VSHL_S 306 UNSPEC_VSHL_U 307 UNSPEC_VRSHL_S 308 UNSPEC_VRSHL_U 309 UNSPEC_VSHLL_S_N 310 UNSPEC_VSHLL_U_N 311 UNSPEC_VSHL_N 312 UNSPEC_VSHR_S_N 313 UNSPEC_VSHR_U_N 314 UNSPEC_VRSHR_S_N 315 UNSPEC_VRSHR_U_N 316 UNSPEC_VSHRN_N 317 UNSPEC_VRSHRN_N 318 UNSPEC_VSLI 319 UNSPEC_VSRA_S_N 320 UNSPEC_VSRA_U_N 321 UNSPEC_VRSRA_S_N 322 UNSPEC_VRSRA_U_N 323 UNSPEC_VSRI 324 UNSPEC_VST1 325 UNSPEC_VST1_LANE 326 UNSPEC_VST2 327 UNSPEC_VST2_LANE 328 UNSPEC_VST3 329 UNSPEC_VST3A 330 UNSPEC_VST3B 331 UNSPEC_VST3_LANE 332 UNSPEC_VST4 333 UNSPEC_VST4A 334 UNSPEC_VST4B 335 UNSPEC_VST4_LANE 336 UNSPEC_VSTRUCTDUMMY 337 UNSPEC_VSUB 338 UNSPEC_VSUBHN 339 UNSPEC_VRSUBHN 340 UNSPEC_VSUBL_S 341 UNSPEC_VSUBL_U 342 UNSPEC_VSUBW_S 343 UNSPEC_VSUBW_U 344 UNSPEC_VTBL 345 UNSPEC_VTBX 346 UNSPEC_VTRN1 347 UNSPEC_VTRN2 348 UNSPEC_VTST 349 UNSPEC_VUZP1 350 UNSPEC_VUZP2 351 UNSPEC_VZIP1 352 UNSPEC_VZIP2 353 UNSPEC_MISALIGNED_ACCESS 354 UNSPEC_VCLE 355 UNSPEC_VCLT 356 UNSPEC_NVRINTZ 357 UNSPEC_NVRINTP 358 UNSPEC_NVRINTM 359 UNSPEC_NVRINTX 360 UNSPEC_NVRINTA 361 UNSPEC_NVRINTN 362]) 363 364