1;; Predicate definitions for ARM and Thumb 2;; Copyright (C) 2004-2020 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_predicate "s_register_operand" 22 (match_code "reg,subreg") 23{ 24 if (GET_CODE (op) == SUBREG) 25 op = SUBREG_REG (op); 26 /* We don't consider registers whose class is NO_REGS 27 to be a register operand. */ 28 /* XXX might have to check for lo regs only for thumb ??? */ 29 return (REG_P (op) 30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); 32}) 33 34(define_predicate "mve_memory_operand" 35 (and (match_code "mem") 36 (match_test "TARGET_32BIT 37 && mve_vector_mem_operand (GET_MODE (op), XEXP (op, 0), 38 false)"))) 39 40(define_predicate "mve_scatter_memory" 41 (and (match_code "mem") 42 (match_test "TARGET_HAVE_MVE && REG_P (XEXP (op, 0)) 43 && mve_vector_mem_operand (GET_MODE (op), XEXP (op, 0), 44 false)"))) 45 46;; True for immediates in the range of 1 to 16 for MVE. 47(define_predicate "mve_imm_16" 48 (match_test "satisfies_constraint_Rd (op)")) 49 50;; True for immediates in the range of 0 to 7 for MVE. 51(define_predicate "mve_imm_7" 52 (match_test "satisfies_constraint_Ra (op)")) 53 54;; True for immediates in the range of 1 to 8 for MVE. 55(define_predicate "mve_imm_8" 56 (match_test "satisfies_constraint_Rb (op)")) 57 58;; True for immediates in the range of 0 to 15 for MVE. 59(define_predicate "mve_imm_15" 60 (match_test "satisfies_constraint_Rc (op)")) 61 62;; True for immediates in the range of 0 to 31 for MVE. 63(define_predicate "mve_imm_31" 64 (match_test "satisfies_constraint_Re (op)")) 65 66;; True for immediates in the range of 1 to 32 for MVE. 67(define_predicate "mve_imm_32" 68 (match_test "satisfies_constraint_Rf (op)")) 69 70;; True if the immediate is one among 1, 2, 4 or 8 for MVE. 71(define_predicate "mve_imm_selective_upto_8" 72 (match_test "satisfies_constraint_Rg (op)")) 73 74;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. 75(define_constraint "Ri" 76 "@internal In Thumb-2 state a constant is multiple of 8 and in range 77 of -/+ 1016 for MVE" 78 (and (match_code "const_int") 79 (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) 80 && ((ival % 8) == 0)"))) 81 82; Predicate for stack protector guard's address in 83; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns 84(define_predicate "guard_addr_operand" 85 (match_test "true") 86{ 87 return (CONSTANT_ADDRESS_P (op) 88 || !targetm.cannot_force_const_mem (mode, op)); 89}) 90 91; Predicate for stack protector guard in stack_protect_combined_set and 92; stack_protect_combined_test patterns 93(define_predicate "guard_operand" 94 (match_code "mem") 95{ 96 return guard_addr_operand (XEXP (op, 0), mode); 97}) 98 99(define_predicate "vpr_register_operand" 100 (match_code "reg") 101{ 102 return REG_P (op) 103 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 104 || IS_VPR_REGNUM (REGNO (op))); 105}) 106 107(define_predicate "imm_for_neon_inv_logic_operand" 108 (match_code "const_vector") 109{ 110 return (TARGET_NEON 111 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); 112}) 113 114(define_predicate "neon_inv_logic_op2" 115 (ior (match_operand 0 "imm_for_neon_inv_logic_operand") 116 (match_operand 0 "s_register_operand"))) 117 118(define_predicate "imm_for_neon_logic_operand" 119 (match_code "const_vector") 120{ 121 return (TARGET_NEON 122 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); 123}) 124 125(define_predicate "neon_logic_op2" 126 (ior (match_operand 0 "imm_for_neon_logic_operand") 127 (match_operand 0 "s_register_operand"))) 128 129;; Any general register. 130(define_predicate "arm_hard_general_register_operand" 131 (match_code "reg") 132{ 133 return REGNO (op) <= LAST_ARM_REGNUM; 134}) 135 136;; A low register. 137(define_predicate "low_register_operand" 138 (and (match_code "reg") 139 (match_test "REGNO (op) <= LAST_LO_REGNUM"))) 140 141;; A low register or const_int. 142(define_predicate "low_reg_or_int_operand" 143 (ior (match_code "const_int") 144 (match_operand 0 "low_register_operand"))) 145 146;; Any core register, or any pseudo. */ 147(define_predicate "arm_general_register_operand" 148 (match_code "reg,subreg") 149{ 150 if (GET_CODE (op) == SUBREG) 151 op = SUBREG_REG (op); 152 153 return (REG_P (op) 154 && (REGNO (op) <= LAST_ARM_REGNUM 155 || REGNO (op) >= FIRST_PSEUDO_REGISTER)); 156}) 157 158;; Low core register, or any pseudo. 159(define_predicate "arm_low_register_operand" 160 (match_code "reg,subreg") 161{ 162 if (GET_CODE (op) == SUBREG) 163 op = SUBREG_REG (op); 164 165 return (REG_P (op) 166 && (REGNO (op) <= LAST_LO_REGNUM 167 || REGNO (op) >= FIRST_PSEUDO_REGISTER)); 168}) 169 170(define_predicate "arm_general_adddi_operand" 171 (ior (match_operand 0 "arm_general_register_operand") 172 (and (match_code "const_int") 173 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) 174 175(define_predicate "vfp_register_operand" 176 (match_code "reg,subreg") 177{ 178 if (GET_CODE (op) == SUBREG) 179 op = SUBREG_REG (op); 180 181 /* We don't consider registers whose class is NO_REGS 182 to be a register operand. */ 183 return (REG_P (op) 184 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 185 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS 186 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS 187 || (TARGET_VFPD32 188 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); 189}) 190 191(define_predicate "vfp_hard_register_operand" 192 (match_code "reg") 193{ 194 return (IS_VFP_REGNUM (REGNO (op))); 195}) 196 197(define_predicate "zero_operand" 198 (and (match_code "const_int,const_double,const_vector") 199 (match_test "op == CONST0_RTX (mode)"))) 200 201;; Match a register, or zero in the appropriate mode. 202(define_predicate "reg_or_zero_operand" 203 (ior (match_operand 0 "s_register_operand") 204 (match_operand 0 "zero_operand"))) 205 206(define_special_predicate "subreg_lowpart_operator" 207 (and (match_code "subreg") 208 (match_test "subreg_lowpart_p (op)"))) 209 210;; Reg, subreg(reg) or const_int. 211(define_predicate "reg_or_int_operand" 212 (ior (match_code "const_int") 213 (match_operand 0 "s_register_operand"))) 214 215(define_predicate "arm_immediate_operand" 216 (and (match_code "const_int") 217 (match_test "const_ok_for_arm (INTVAL (op))"))) 218 219;; A constant value which fits into two instructions, each taking 220;; an arithmetic constant operand for one of the words. 221(define_predicate "arm_immediate_di_operand" 222 (and (match_code "const_int,const_double") 223 (match_test "arm_const_double_by_immediates (op)"))) 224 225(define_predicate "arm_neg_immediate_operand" 226 (and (match_code "const_int") 227 (match_test "const_ok_for_arm (-INTVAL (op))"))) 228 229(define_predicate "arm_not_immediate_operand" 230 (and (match_code "const_int") 231 (match_test "const_ok_for_arm (~INTVAL (op))"))) 232 233(define_predicate "const0_operand" 234 (match_test "op == CONST0_RTX (mode)")) 235 236;; Something valid on the RHS of an ARM data-processing instruction 237(define_predicate "arm_rhs_operand" 238 (ior (match_operand 0 "s_register_operand") 239 (match_operand 0 "arm_immediate_operand"))) 240 241(define_predicate "arm_rhsm_operand" 242 (ior (match_operand 0 "arm_rhs_operand") 243 (match_operand 0 "memory_operand"))) 244 245(define_predicate "const_int_I_operand" 246 (and (match_operand 0 "const_int_operand") 247 (match_test "satisfies_constraint_I (op)"))) 248 249(define_predicate "const_int_M_operand" 250 (and (match_operand 0 "const_int_operand") 251 (match_test "satisfies_constraint_M (op)"))) 252 253(define_predicate "const_int_coproc_operand" 254 (and (match_operand 0 "const_int_operand") 255 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_CDE_CONST_COPROC)") 256 (match_test "arm_arch_cde_coproc_bits[UINTVAL (op)] & arm_arch_cde_coproc"))) 257 258(define_predicate "const_int_ccde1_operand" 259 (and (match_operand 0 "const_int_operand") 260 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_CCDE_CONST_1)"))) 261 262(define_predicate "const_int_ccde2_operand" 263 (and (match_operand 0 "const_int_operand") 264 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_CCDE_CONST_2)"))) 265 266(define_predicate "const_int_ccde3_operand" 267 (and (match_operand 0 "const_int_operand") 268 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_CCDE_CONST_3)"))) 269 270(define_predicate "const_int_vcde1_operand" 271 (and (match_operand 0 "const_int_operand") 272 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_VCDE_CONST_1)"))) 273 274(define_predicate "const_int_vcde2_operand" 275 (and (match_operand 0 "const_int_operand") 276 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_VCDE_CONST_2)"))) 277 278(define_predicate "const_int_vcde3_operand" 279 (and (match_operand 0 "const_int_operand") 280 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_VCDE_CONST_3)"))) 281 282(define_predicate "const_int_mve_cde1_operand" 283 (and (match_operand 0 "const_int_operand") 284 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_MVE_CDE_CONST_1)"))) 285 286(define_predicate "const_int_mve_cde2_operand" 287 (and (match_operand 0 "const_int_operand") 288 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_MVE_CDE_CONST_2)"))) 289 290(define_predicate "const_int_mve_cde3_operand" 291 (and (match_operand 0 "const_int_operand") 292 (match_test "IN_RANGE (UINTVAL (op), 0, ARM_MVE_CDE_CONST_3)"))) 293 294;; This doesn't have to do much because the constant is already checked 295;; in the shift_operator predicate. 296(define_predicate "shift_amount_operand" 297 (ior (and (match_test "TARGET_ARM") 298 (match_operand 0 "s_register_operand")) 299 (match_operand 0 "const_int_operand"))) 300 301(define_predicate "const_neon_scalar_shift_amount_operand" 302 (and (match_code "const_int") 303 (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))"))) 304 305(define_predicate "ssat16_imm" 306 (and (match_code "const_int") 307 (match_test "IN_RANGE (INTVAL (op), 1, 16)"))) 308 309(define_predicate "usat16_imm" 310 (and (match_code "const_int") 311 (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) 312 313(define_predicate "ldrd_strd_offset_operand" 314 (and (match_operand 0 "const_int_operand") 315 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))"))) 316 317(define_predicate "arm_add_operand" 318 (ior (match_operand 0 "arm_rhs_operand") 319 (match_operand 0 "arm_neg_immediate_operand"))) 320 321(define_predicate "arm_adddi_operand" 322 (ior (match_operand 0 "s_register_operand") 323 (and (match_code "const_int") 324 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) 325 326(define_predicate "arm_anddi_operand" 327 (ior (match_operand 0 "s_register_operand") 328 (and (match_code "const_int") 329 (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")))) 330 331(define_predicate "arm_iordi_operand" 332 (ior (match_operand 0 "s_register_operand") 333 (and (match_code "const_int") 334 (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)")))) 335 336(define_predicate "arm_xordi_operand" 337 (ior (match_operand 0 "s_register_operand") 338 (and (match_code "const_int") 339 (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)")))) 340 341(define_predicate "arm_addimm_operand" 342 (ior (match_operand 0 "arm_immediate_operand") 343 (match_operand 0 "arm_neg_immediate_operand"))) 344 345(define_predicate "arm_not_operand" 346 (ior (match_operand 0 "arm_rhs_operand") 347 (match_operand 0 "arm_not_immediate_operand"))) 348 349;; A constant that can be used with ADC(SBC) or SBC(ADC) when bit-wise 350;; inverted. Similar to arm_not_operand, but excludes registers. 351(define_predicate "arm_adcimm_operand" 352 (ior (match_operand 0 "arm_immediate_operand") 353 (match_operand 0 "arm_not_immediate_operand"))) 354 355(define_predicate "arm_di_operand" 356 (ior (match_operand 0 "s_register_operand") 357 (match_operand 0 "arm_immediate_di_operand"))) 358 359;; True if the operand is a memory reference which contains an 360;; offsettable address. 361(define_predicate "offsettable_memory_operand" 362 (and (match_code "mem") 363 (match_test 364 "offsettable_address_p (reload_completed | reload_in_progress, 365 mode, XEXP (op, 0))"))) 366 367;; True if the operand is a memory operand that does not have an 368;; automodified base register (and thus will not generate output reloads). 369(define_predicate "call_memory_operand" 370 (and (match_code "mem") 371 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) 372 != RTX_AUTOINC") 373 (match_operand 0 "memory_operand")))) 374 375(define_predicate "arm_reload_memory_operand" 376 (and (match_code "mem,reg,subreg") 377 (match_test "(!CONSTANT_P (op) 378 && (true_regnum(op) == -1 379 || (REG_P (op) 380 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) 381 382(define_predicate "vfp_compare_operand" 383 (ior (match_operand 0 "s_register_operand") 384 (and (match_code "const_double") 385 (match_test "arm_const_double_rtx (op)")))) 386 387;; True for valid index operands. 388(define_predicate "index_operand" 389 (ior (match_operand 0 "s_register_operand") 390 (and (match_operand 0 "immediate_operand") 391 (match_test "(!CONST_INT_P (op) 392 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) 393 394;; True for operators that can be combined with a shift in ARM state. 395(define_special_predicate "shiftable_operator" 396 (and (match_code "plus,minus,ior,xor,and") 397 (match_test "mode == GET_MODE (op)"))) 398 399(define_special_predicate "shiftable_operator_strict_it" 400 (and (match_code "plus,and") 401 (match_test "mode == GET_MODE (op)"))) 402 403;; True for logical binary operators. 404(define_special_predicate "logical_binary_operator" 405 (and (match_code "ior,xor,and") 406 (match_test "mode == GET_MODE (op)"))) 407 408;; True for commutative operators 409(define_special_predicate "commutative_binary_operator" 410 (and (match_code "ior,xor,and,plus") 411 (match_test "mode == GET_MODE (op)"))) 412 413;; True for shift operators. 414;; Notes: 415;; * mult is only permitted with a constant shift amount 416;; * patterns that permit register shift amounts only in ARM mode use 417;; shift_amount_operand, patterns that always allow registers do not, 418;; so we don't have to worry about that sort of thing here. 419(define_special_predicate "shift_operator" 420 (and (ior (ior (and (match_code "mult") 421 (match_test "power_of_two_operand (XEXP (op, 1), mode)")) 422 (and (match_code "rotate") 423 (match_test "CONST_INT_P (XEXP (op, 1)) 424 && (UINTVAL (XEXP (op, 1))) < 32"))) 425 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") 426 (match_test "!CONST_INT_P (XEXP (op, 1)) 427 || (UINTVAL (XEXP (op, 1))) < 32"))) 428 (match_test "mode == GET_MODE (op)"))) 429 430(define_special_predicate "shift_nomul_operator" 431 (and (ior (and (match_code "rotate") 432 (match_test "CONST_INT_P (XEXP (op, 1)) 433 && (UINTVAL (XEXP (op, 1))) < 32")) 434 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") 435 (match_test "!CONST_INT_P (XEXP (op, 1)) 436 || (UINTVAL (XEXP (op, 1))) < 32"))) 437 (match_test "mode == GET_MODE (op)"))) 438 439;; True for shift operators which can be used with saturation instructions. 440(define_special_predicate "sat_shift_operator" 441 (and (ior (and (match_code "mult") 442 (match_test "power_of_two_operand (XEXP (op, 1), mode)")) 443 (and (match_code "ashift,ashiftrt") 444 (match_test "CONST_INT_P (XEXP (op, 1)) 445 && (UINTVAL (XEXP (op, 1)) < 32)"))) 446 (match_test "mode == GET_MODE (op)"))) 447 448;; True for Armv8.1-M Mainline long shift instructions. 449(define_predicate "long_shift_imm" 450 (match_test "satisfies_constraint_Pg (op)")) 451 452(define_predicate "arm_reg_or_long_shift_imm" 453 (ior (match_test "TARGET_THUMB2 454 && arm_general_register_operand (op, GET_MODE (op))") 455 (match_test "satisfies_constraint_Pg (op)"))) 456 457;; True for MULT, to identify which variant of shift_operator is in use. 458(define_special_predicate "mult_operator" 459 (match_code "mult")) 460 461;; True for operators that have 16-bit thumb variants. */ 462(define_special_predicate "thumb_16bit_operator" 463 (match_code "plus,minus,and,ior,xor")) 464 465;; True for EQ & NE 466(define_special_predicate "equality_operator" 467 (match_code "eq,ne")) 468 469;; True for integer comparisons and, if FP is active, for comparisons 470;; other than LTGT or UNEQ. 471(define_special_predicate "expandable_comparison_operator" 472 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, 473 unordered,ordered,unlt,unle,unge,ungt")) 474 475;; Likewise, but only accept comparisons that are directly supported 476;; by ARM condition codes. 477(define_special_predicate "arm_comparison_operator" 478 (and (match_operand 0 "expandable_comparison_operator") 479 (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) 480 481;; Likewise, but don't ignore the mode. 482;; RTL SET operations require their operands source and destination have 483;; the same modes, so we can't ignore the modes there. See PR target/69161. 484(define_predicate "arm_comparison_operator_mode" 485 (and (match_operand 0 "expandable_comparison_operator") 486 (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) 487 488(define_special_predicate "lt_ge_comparison_operator" 489 (match_code "lt,ge")) 490 491(define_special_predicate "arm_carry_operation" 492 (match_code "geu,ltu") 493 { 494 if (XEXP (op, 1) != const0_rtx) 495 return false; 496 497 rtx op0 = XEXP (op, 0); 498 499 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) 500 return false; 501 502 machine_mode ccmode = GET_MODE (op0); 503 if (ccmode == CC_Cmode) 504 return GET_CODE (op) == LTU; 505 else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode) 506 return GET_CODE (op) == GEU; 507 508 return false; 509 } 510) 511 512;; Match a "borrow" operation for use with SBC. The precise code will 513;; depend on the form of the comparison. This is generally the inverse of 514;; a carry operation, since the logic of SBC uses "not borrow" in it's 515;; calculation. 516(define_special_predicate "arm_borrow_operation" 517 (match_code "geu,ltu") 518 { 519 if (XEXP (op, 1) != const0_rtx) 520 return false; 521 rtx op0 = XEXP (op, 0); 522 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) 523 return false; 524 machine_mode ccmode = GET_MODE (op0); 525 if (ccmode == CC_Cmode) 526 return GET_CODE (op) == GEU; 527 else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode) 528 return GET_CODE (op) == LTU; 529 return false; 530 } 531) 532 533;; The vsel instruction only accepts the ARM condition codes listed below. 534(define_special_predicate "arm_vsel_comparison_operator" 535 (and (match_operand 0 "expandable_comparison_operator") 536 (match_test "maybe_get_arm_condition_code (op) == ARM_GE 537 || maybe_get_arm_condition_code (op) == ARM_GT 538 || maybe_get_arm_condition_code (op) == ARM_EQ 539 || maybe_get_arm_condition_code (op) == ARM_VS 540 || maybe_get_arm_condition_code (op) == ARM_LT 541 || maybe_get_arm_condition_code (op) == ARM_LE 542 || maybe_get_arm_condition_code (op) == ARM_NE 543 || maybe_get_arm_condition_code (op) == ARM_VC"))) 544 545(define_special_predicate "arm_cond_move_operator" 546 (if_then_else (match_test "arm_restrict_it") 547 (and (match_test "TARGET_VFP5") 548 (match_operand 0 "arm_vsel_comparison_operator")) 549 (match_operand 0 "expandable_comparison_operator"))) 550 551(define_special_predicate "nz_comparison_operator" 552 (match_code "lt,ge,eq,ne")) 553 554(define_special_predicate "minmax_operator" 555 (and (match_code "smin,smax,umin,umax") 556 (match_test "mode == GET_MODE (op)"))) 557 558(define_special_predicate "cc_register" 559 (and (match_code "reg") 560 (and (match_test "REGNO (op) == CC_REGNUM") 561 (ior (match_test "mode == GET_MODE (op)") 562 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) 563 564(define_special_predicate "dominant_cc_register" 565 (match_code "reg") 566{ 567 if (mode == VOIDmode) 568 { 569 mode = GET_MODE (op); 570 571 if (GET_MODE_CLASS (mode) != MODE_CC) 572 return false; 573 } 574 575 return (cc_register (op, mode) 576 && (mode == CC_DNEmode 577 || mode == CC_DEQmode 578 || mode == CC_DLEmode 579 || mode == CC_DLTmode 580 || mode == CC_DGEmode 581 || mode == CC_DGTmode 582 || mode == CC_DLEUmode 583 || mode == CC_DLTUmode 584 || mode == CC_DGEUmode 585 || mode == CC_DGTUmode)); 586}) 587 588;; Any register, including CC 589(define_predicate "cc_register_operand" 590 (and (match_code "reg") 591 (ior (match_operand 0 "s_register_operand") 592 (match_operand 0 "cc_register")))) 593 594(define_special_predicate "arm_extendqisi_mem_op" 595 (and (match_operand 0 "memory_operand") 596 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, 597 XEXP (op, 0), 598 SIGN_EXTEND, 599 0) 600 : memory_address_p (QImode, XEXP (op, 0))"))) 601 602(define_special_predicate "arm_reg_or_extendqisi_mem_op" 603 (ior (match_operand 0 "arm_extendqisi_mem_op") 604 (match_operand 0 "s_register_operand"))) 605 606(define_predicate "power_of_two_operand" 607 (match_code "const_int") 608{ 609 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; 610 611 return value != 0 && (value & (value - 1)) == 0; 612}) 613 614(define_predicate "nonimmediate_di_operand" 615 (match_code "reg,subreg,mem") 616{ 617 if (s_register_operand (op, mode)) 618 return true; 619 620 if (GET_CODE (op) == SUBREG) 621 op = SUBREG_REG (op); 622 623 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0)); 624}) 625 626(define_predicate "di_operand" 627 (ior (match_code "const_int,const_double") 628 (and (match_code "reg,subreg,mem") 629 (match_operand 0 "nonimmediate_di_operand")))) 630 631(define_predicate "nonimmediate_soft_df_operand" 632 (match_code "reg,subreg,mem") 633{ 634 if (s_register_operand (op, mode)) 635 return true; 636 637 if (GET_CODE (op) == SUBREG) 638 op = SUBREG_REG (op); 639 640 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0)); 641}) 642 643(define_predicate "soft_df_operand" 644 (ior (match_code "const_double") 645 (and (match_code "reg,subreg,mem") 646 (match_operand 0 "nonimmediate_soft_df_operand")))) 647 648;; Predicate for thumb2_movsf_vfp. Compared to general_operand, this 649;; forbids constant loaded via literal pool iff literal pools are disabled. 650(define_predicate "hard_sf_operand" 651 (and (match_operand 0 "general_operand") 652 (ior (not (match_code "const_double")) 653 (not (match_test "arm_disable_literal_pool")) 654 (match_test "satisfies_constraint_Dv (op)")))) 655 656;; Predicate for thumb2_movdf_vfp. Compared to soft_df_operand used in 657;; movdf_soft_insn, this forbids constant loaded via literal pool iff 658;; literal pools are disabled. 659(define_predicate "hard_df_operand" 660 (and (match_operand 0 "soft_df_operand") 661 (ior (not (match_code "const_double")) 662 (not (match_test "arm_disable_literal_pool")) 663 (match_test "satisfies_constraint_Dy (op)") 664 (match_test "satisfies_constraint_G (op)")))) 665 666(define_special_predicate "clear_multiple_operation" 667 (match_code "parallel") 668{ 669 return clear_operation_p (op, /*vfp*/false); 670}) 671 672(define_special_predicate "clear_vfp_multiple_operation" 673 (match_code "parallel") 674{ 675 return clear_operation_p (op, /*vfp*/true); 676}) 677 678(define_special_predicate "load_multiple_operation" 679 (match_code "parallel") 680{ 681 return ldm_stm_operation_p (op, /*load=*/true, SImode, 682 /*consecutive=*/false, 683 /*return_pc=*/false); 684}) 685 686(define_special_predicate "store_multiple_operation" 687 (match_code "parallel") 688{ 689 return ldm_stm_operation_p (op, /*load=*/false, SImode, 690 /*consecutive=*/false, 691 /*return_pc=*/false); 692}) 693 694(define_special_predicate "pop_multiple_return" 695 (match_code "parallel") 696{ 697 return ldm_stm_operation_p (op, /*load=*/true, SImode, 698 /*consecutive=*/false, 699 /*return_pc=*/true); 700}) 701 702(define_special_predicate "pop_multiple_fp" 703 (match_code "parallel") 704{ 705 return ldm_stm_operation_p (op, /*load=*/true, DFmode, 706 /*consecutive=*/true, 707 /*return_pc=*/false); 708}) 709 710(define_special_predicate "multi_register_push" 711 (match_code "parallel") 712{ 713 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) 714 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) 715 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) 716 return false; 717 718 return true; 719}) 720 721(define_predicate "push_mult_memory_operand" 722 (match_code "mem") 723{ 724 /* ??? Given how PUSH_MULT is generated in the prologues, is there 725 any point in testing for thumb1 specially? All of the variants 726 use the same form. */ 727 if (TARGET_THUMB1) 728 { 729 /* ??? No attempt is made to represent STMIA, or validate that 730 the stack adjustment matches the register count. This is 731 true of the ARM/Thumb2 path as well. */ 732 rtx x = XEXP (op, 0); 733 if (GET_CODE (x) != PRE_MODIFY) 734 return false; 735 if (XEXP (x, 0) != stack_pointer_rtx) 736 return false; 737 x = XEXP (x, 1); 738 if (GET_CODE (x) != PLUS) 739 return false; 740 if (XEXP (x, 0) != stack_pointer_rtx) 741 return false; 742 return CONST_INT_P (XEXP (x, 1)); 743 } 744 745 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ 746 return memory_operand (op, mode); 747}) 748 749;;------------------------------------------------------------------------- 750;; 751;; Thumb predicates 752;; 753 754(define_predicate "thumb1_cmp_operand" 755 (ior (and (match_code "reg,subreg") 756 (match_operand 0 "s_register_operand")) 757 (and (match_code "const_int") 758 (match_test "(UINTVAL (op)) < 256")))) 759 760(define_predicate "thumb1_cmpneg_operand" 761 (and (match_code "const_int") 762 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) 763 764;; Return TRUE if a result can be stored in OP without clobbering the 765;; condition code register. Prior to reload we only accept a 766;; register. After reload we have to be able to handle memory as 767;; well, since a pseudo may not get a hard reg and reload cannot 768;; handle output-reloads on jump insns. 769 770;; We could possibly handle mem before reload as well, but that might 771;; complicate things with the need to handle increment 772;; side-effects. 773(define_predicate "thumb_cbrch_target_operand" 774 (and (match_code "reg,subreg,mem") 775 (ior (match_operand 0 "s_register_operand") 776 (and (match_test "reload_in_progress || reload_completed") 777 (match_operand 0 "memory_operand"))))) 778 779;;------------------------------------------------------------------------- 780;; 781;; iWMMXt predicates 782;; 783 784(define_predicate "imm_or_reg_operand" 785 (ior (match_operand 0 "immediate_operand") 786 (match_operand 0 "register_operand"))) 787 788;; Neon predicates 789 790(define_predicate "const_multiple_of_8_operand" 791 (match_code "const_int") 792{ 793 unsigned HOST_WIDE_INT val = INTVAL (op); 794 return (val & 7) == 0; 795}) 796 797(define_predicate "imm_for_neon_mov_operand" 798 (match_code "const_vector,const_int") 799{ 800 return simd_immediate_valid_for_move (op, mode, NULL, NULL); 801}) 802 803(define_predicate "imm_for_neon_lshift_operand" 804 (match_code "const_vector") 805{ 806 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); 807}) 808 809(define_predicate "imm_for_neon_rshift_operand" 810 (match_code "const_vector") 811{ 812 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); 813}) 814 815(define_predicate "imm_lshift_or_reg_neon" 816 (ior (match_operand 0 "s_register_operand") 817 (match_operand 0 "imm_for_neon_lshift_operand"))) 818 819(define_predicate "imm_rshift_or_reg_neon" 820 (ior (match_operand 0 "s_register_operand") 821 (match_operand 0 "imm_for_neon_rshift_operand"))) 822 823;; Predicates for named expanders that overlap multiple ISAs. 824 825(define_predicate "cmpdi_operand" 826 (and (match_test "TARGET_32BIT") 827 (match_operand 0 "arm_di_operand"))) 828 829;; True if the operand is memory reference suitable for a ldrex/strex. 830(define_predicate "arm_sync_memory_operand" 831 (and (match_operand 0 "memory_operand") 832 (match_code "reg" "0"))) 833 834;; Predicates for parallel expanders based on mode. 835(define_special_predicate "vect_par_constant_high" 836 (match_code "parallel") 837{ 838 return arm_simd_check_vect_par_cnst_half_p (op, mode, true); 839}) 840 841(define_special_predicate "vect_par_constant_low" 842 (match_code "parallel") 843{ 844 return arm_simd_check_vect_par_cnst_half_p (op, mode, false); 845}) 846 847(define_predicate "const_double_vcvt_power_of_two_reciprocal" 848 (and (match_code "const_double") 849 (match_test "TARGET_32BIT 850 && vfp3_const_double_for_fract_bits (op)"))) 851 852(define_predicate "const_double_vcvt_power_of_two" 853 (and (match_code "const_double") 854 (match_test "TARGET_32BIT 855 && vfp3_const_double_for_bits (op) > 0"))) 856 857(define_predicate "neon_struct_operand" 858 (and (match_code "mem") 859 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)"))) 860 861(define_predicate "neon_permissive_struct_operand" 862 (and (match_code "mem") 863 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)"))) 864 865(define_predicate "neon_perm_struct_or_reg_operand" 866 (ior (match_operand 0 "neon_permissive_struct_operand") 867 (match_operand 0 "s_register_operand"))) 868 869(define_special_predicate "add_operator" 870 (match_code "plus")) 871 872(define_predicate "mem_noofs_operand" 873 (and (match_code "mem") 874 (match_code "reg" "0"))) 875 876(define_predicate "call_insn_operand" 877 (ior (and (match_code "symbol_ref") 878 (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))")) 879 (match_operand 0 "s_register_operand"))) 880 881(define_special_predicate "aligned_operand" 882 (ior (not (match_code "mem")) 883 (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))) 884