1;; Predicate definitions for ARM and Thumb 2;; Copyright (C) 2004-2019 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_predicate "s_register_operand" 22 (match_code "reg,subreg") 23{ 24 if (GET_CODE (op) == SUBREG) 25 op = SUBREG_REG (op); 26 /* We don't consider registers whose class is NO_REGS 27 to be a register operand. */ 28 /* XXX might have to check for lo regs only for thumb ??? */ 29 return (REG_P (op) 30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); 32}) 33 34; Predicate for stack protector guard's address in 35; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns 36(define_predicate "guard_addr_operand" 37 (match_test "true") 38{ 39 return (CONSTANT_ADDRESS_P (op) 40 || !targetm.cannot_force_const_mem (mode, op)); 41}) 42 43; Predicate for stack protector guard in stack_protect_combined_set and 44; stack_protect_combined_test patterns 45(define_predicate "guard_operand" 46 (match_code "mem") 47{ 48 return guard_addr_operand (XEXP (op, 0), mode); 49}) 50 51(define_predicate "imm_for_neon_inv_logic_operand" 52 (match_code "const_vector") 53{ 54 return (TARGET_NEON 55 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); 56}) 57 58(define_predicate "neon_inv_logic_op2" 59 (ior (match_operand 0 "imm_for_neon_inv_logic_operand") 60 (match_operand 0 "s_register_operand"))) 61 62(define_predicate "imm_for_neon_logic_operand" 63 (match_code "const_vector") 64{ 65 return (TARGET_NEON 66 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); 67}) 68 69(define_predicate "neon_logic_op2" 70 (ior (match_operand 0 "imm_for_neon_logic_operand") 71 (match_operand 0 "s_register_operand"))) 72 73;; Any general register. 74(define_predicate "arm_hard_general_register_operand" 75 (match_code "reg") 76{ 77 return REGNO (op) <= LAST_ARM_REGNUM; 78}) 79 80;; A low register. 81(define_predicate "low_register_operand" 82 (and (match_code "reg") 83 (match_test "REGNO (op) <= LAST_LO_REGNUM"))) 84 85;; A low register or const_int. 86(define_predicate "low_reg_or_int_operand" 87 (ior (match_code "const_int") 88 (match_operand 0 "low_register_operand"))) 89 90;; Any core register, or any pseudo. */ 91(define_predicate "arm_general_register_operand" 92 (match_code "reg,subreg") 93{ 94 if (GET_CODE (op) == SUBREG) 95 op = SUBREG_REG (op); 96 97 return (REG_P (op) 98 && (REGNO (op) <= LAST_ARM_REGNUM 99 || REGNO (op) >= FIRST_PSEUDO_REGISTER)); 100}) 101 102(define_predicate "arm_general_adddi_operand" 103 (ior (match_operand 0 "arm_general_register_operand") 104 (and (match_code "const_int") 105 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) 106 107(define_predicate "vfp_register_operand" 108 (match_code "reg,subreg") 109{ 110 if (GET_CODE (op) == SUBREG) 111 op = SUBREG_REG (op); 112 113 /* We don't consider registers whose class is NO_REGS 114 to be a register operand. */ 115 return (REG_P (op) 116 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 117 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS 118 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS 119 || (TARGET_VFPD32 120 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); 121}) 122 123(define_predicate "vfp_hard_register_operand" 124 (match_code "reg") 125{ 126 return (IS_VFP_REGNUM (REGNO (op))); 127}) 128 129(define_predicate "zero_operand" 130 (and (match_code "const_int,const_double,const_vector") 131 (match_test "op == CONST0_RTX (mode)"))) 132 133;; Match a register, or zero in the appropriate mode. 134(define_predicate "reg_or_zero_operand" 135 (ior (match_operand 0 "s_register_operand") 136 (match_operand 0 "zero_operand"))) 137 138(define_special_predicate "subreg_lowpart_operator" 139 (and (match_code "subreg") 140 (match_test "subreg_lowpart_p (op)"))) 141 142;; Reg, subreg(reg) or const_int. 143(define_predicate "reg_or_int_operand" 144 (ior (match_code "const_int") 145 (match_operand 0 "s_register_operand"))) 146 147(define_predicate "arm_immediate_operand" 148 (and (match_code "const_int") 149 (match_test "const_ok_for_arm (INTVAL (op))"))) 150 151;; A constant value which fits into two instructions, each taking 152;; an arithmetic constant operand for one of the words. 153(define_predicate "arm_immediate_di_operand" 154 (and (match_code "const_int,const_double") 155 (match_test "arm_const_double_by_immediates (op)"))) 156 157(define_predicate "arm_neg_immediate_operand" 158 (and (match_code "const_int") 159 (match_test "const_ok_for_arm (-INTVAL (op))"))) 160 161(define_predicate "arm_not_immediate_operand" 162 (and (match_code "const_int") 163 (match_test "const_ok_for_arm (~INTVAL (op))"))) 164 165(define_predicate "const0_operand" 166 (match_test "op == CONST0_RTX (mode)")) 167 168;; Something valid on the RHS of an ARM data-processing instruction 169(define_predicate "arm_rhs_operand" 170 (ior (match_operand 0 "s_register_operand") 171 (match_operand 0 "arm_immediate_operand"))) 172 173(define_predicate "arm_rhsm_operand" 174 (ior (match_operand 0 "arm_rhs_operand") 175 (match_operand 0 "memory_operand"))) 176 177(define_predicate "const_int_I_operand" 178 (and (match_operand 0 "const_int_operand") 179 (match_test "satisfies_constraint_I (op)"))) 180 181(define_predicate "const_int_M_operand" 182 (and (match_operand 0 "const_int_operand") 183 (match_test "satisfies_constraint_M (op)"))) 184 185;; This doesn't have to do much because the constant is already checked 186;; in the shift_operator predicate. 187(define_predicate "shift_amount_operand" 188 (ior (and (match_test "TARGET_ARM") 189 (match_operand 0 "s_register_operand")) 190 (match_operand 0 "const_int_operand"))) 191 192(define_predicate "const_neon_scalar_shift_amount_operand" 193 (and (match_code "const_int") 194 (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))"))) 195 196(define_predicate "ldrd_strd_offset_operand" 197 (and (match_operand 0 "const_int_operand") 198 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))"))) 199 200(define_predicate "arm_add_operand" 201 (ior (match_operand 0 "arm_rhs_operand") 202 (match_operand 0 "arm_neg_immediate_operand"))) 203 204(define_predicate "arm_anddi_operand_neon" 205 (ior (match_operand 0 "s_register_operand") 206 (and (match_code "const_int") 207 (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")) 208 (match_operand 0 "neon_inv_logic_op2"))) 209 210(define_predicate "arm_iordi_operand_neon" 211 (ior (match_operand 0 "s_register_operand") 212 (and (match_code "const_int") 213 (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)")) 214 (match_operand 0 "neon_logic_op2"))) 215 216(define_predicate "arm_xordi_operand" 217 (ior (match_operand 0 "s_register_operand") 218 (and (match_code "const_int") 219 (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)")))) 220 221(define_predicate "arm_adddi_operand" 222 (ior (match_operand 0 "s_register_operand") 223 (and (match_code "const_int") 224 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) 225 226(define_predicate "arm_addimm_operand" 227 (ior (match_operand 0 "arm_immediate_operand") 228 (match_operand 0 "arm_neg_immediate_operand"))) 229 230(define_predicate "arm_not_operand" 231 (ior (match_operand 0 "arm_rhs_operand") 232 (match_operand 0 "arm_not_immediate_operand"))) 233 234(define_predicate "arm_di_operand" 235 (ior (match_operand 0 "s_register_operand") 236 (match_operand 0 "arm_immediate_di_operand"))) 237 238;; True if the operand is a memory reference which contains an 239;; offsettable address. 240(define_predicate "offsettable_memory_operand" 241 (and (match_code "mem") 242 (match_test 243 "offsettable_address_p (reload_completed | reload_in_progress, 244 mode, XEXP (op, 0))"))) 245 246;; True if the operand is a memory operand that does not have an 247;; automodified base register (and thus will not generate output reloads). 248(define_predicate "call_memory_operand" 249 (and (match_code "mem") 250 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) 251 != RTX_AUTOINC") 252 (match_operand 0 "memory_operand")))) 253 254(define_predicate "arm_reload_memory_operand" 255 (and (match_code "mem,reg,subreg") 256 (match_test "(!CONSTANT_P (op) 257 && (true_regnum(op) == -1 258 || (REG_P (op) 259 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) 260 261(define_predicate "vfp_compare_operand" 262 (ior (match_operand 0 "s_register_operand") 263 (and (match_code "const_double") 264 (match_test "arm_const_double_rtx (op)")))) 265 266;; True for valid index operands. 267(define_predicate "index_operand" 268 (ior (match_operand 0 "s_register_operand") 269 (and (match_operand 0 "immediate_operand") 270 (match_test "(!CONST_INT_P (op) 271 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) 272 273;; True for operators that can be combined with a shift in ARM state. 274(define_special_predicate "shiftable_operator" 275 (and (match_code "plus,minus,ior,xor,and") 276 (match_test "mode == GET_MODE (op)"))) 277 278(define_special_predicate "shiftable_operator_strict_it" 279 (and (match_code "plus,and") 280 (match_test "mode == GET_MODE (op)"))) 281 282;; True for logical binary operators. 283(define_special_predicate "logical_binary_operator" 284 (and (match_code "ior,xor,and") 285 (match_test "mode == GET_MODE (op)"))) 286 287;; True for commutative operators 288(define_special_predicate "commutative_binary_operator" 289 (and (match_code "ior,xor,and,plus") 290 (match_test "mode == GET_MODE (op)"))) 291 292;; True for shift operators. 293;; Notes: 294;; * mult is only permitted with a constant shift amount 295;; * patterns that permit register shift amounts only in ARM mode use 296;; shift_amount_operand, patterns that always allow registers do not, 297;; so we don't have to worry about that sort of thing here. 298(define_special_predicate "shift_operator" 299 (and (ior (ior (and (match_code "mult") 300 (match_test "power_of_two_operand (XEXP (op, 1), mode)")) 301 (and (match_code "rotate") 302 (match_test "CONST_INT_P (XEXP (op, 1)) 303 && (UINTVAL (XEXP (op, 1))) < 32"))) 304 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") 305 (match_test "!CONST_INT_P (XEXP (op, 1)) 306 || (UINTVAL (XEXP (op, 1))) < 32"))) 307 (match_test "mode == GET_MODE (op)"))) 308 309(define_special_predicate "shift_nomul_operator" 310 (and (ior (and (match_code "rotate") 311 (match_test "CONST_INT_P (XEXP (op, 1)) 312 && (UINTVAL (XEXP (op, 1))) < 32")) 313 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") 314 (match_test "!CONST_INT_P (XEXP (op, 1)) 315 || (UINTVAL (XEXP (op, 1))) < 32"))) 316 (match_test "mode == GET_MODE (op)"))) 317 318;; True for shift operators which can be used with saturation instructions. 319(define_special_predicate "sat_shift_operator" 320 (and (ior (and (match_code "mult") 321 (match_test "power_of_two_operand (XEXP (op, 1), mode)")) 322 (and (match_code "ashift,ashiftrt") 323 (match_test "CONST_INT_P (XEXP (op, 1)) 324 && (UINTVAL (XEXP (op, 1)) < 32)"))) 325 (match_test "mode == GET_MODE (op)"))) 326 327;; True for MULT, to identify which variant of shift_operator is in use. 328(define_special_predicate "mult_operator" 329 (match_code "mult")) 330 331;; True for operators that have 16-bit thumb variants. */ 332(define_special_predicate "thumb_16bit_operator" 333 (match_code "plus,minus,and,ior,xor")) 334 335;; True for EQ & NE 336(define_special_predicate "equality_operator" 337 (match_code "eq,ne")) 338 339;; True for integer comparisons and, if FP is active, for comparisons 340;; other than LTGT or UNEQ. 341(define_special_predicate "expandable_comparison_operator" 342 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, 343 unordered,ordered,unlt,unle,unge,ungt")) 344 345;; Likewise, but only accept comparisons that are directly supported 346;; by ARM condition codes. 347(define_special_predicate "arm_comparison_operator" 348 (and (match_operand 0 "expandable_comparison_operator") 349 (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) 350 351;; Likewise, but don't ignore the mode. 352;; RTL SET operations require their operands source and destination have 353;; the same modes, so we can't ignore the modes there. See PR target/69161. 354(define_predicate "arm_comparison_operator_mode" 355 (and (match_operand 0 "expandable_comparison_operator") 356 (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) 357 358(define_special_predicate "lt_ge_comparison_operator" 359 (match_code "lt,ge")) 360 361;; Match a "borrow" operation for use with SBC. The precise code will 362;; depend on the form of the comparison. This is generally the inverse of 363;; a carry operation, since the logic of SBC uses "not borrow" in it's 364;; calculation. 365(define_special_predicate "arm_borrow_operation" 366 (match_code "geu,ltu") 367 { 368 if (XEXP (op, 1) != const0_rtx) 369 return false; 370 rtx op0 = XEXP (op, 0); 371 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) 372 return false; 373 machine_mode ccmode = GET_MODE (op0); 374 if (ccmode == CC_Cmode) 375 return GET_CODE (op) == GEU; 376 else if (ccmode == CCmode) 377 return GET_CODE (op) == LTU; 378 return false; 379 } 380) 381 382;; The vsel instruction only accepts the ARM condition codes listed below. 383(define_special_predicate "arm_vsel_comparison_operator" 384 (and (match_operand 0 "expandable_comparison_operator") 385 (match_test "maybe_get_arm_condition_code (op) == ARM_GE 386 || maybe_get_arm_condition_code (op) == ARM_GT 387 || maybe_get_arm_condition_code (op) == ARM_EQ 388 || maybe_get_arm_condition_code (op) == ARM_VS 389 || maybe_get_arm_condition_code (op) == ARM_LT 390 || maybe_get_arm_condition_code (op) == ARM_LE 391 || maybe_get_arm_condition_code (op) == ARM_NE 392 || maybe_get_arm_condition_code (op) == ARM_VC"))) 393 394(define_special_predicate "arm_cond_move_operator" 395 (if_then_else (match_test "arm_restrict_it") 396 (and (match_test "TARGET_VFP5") 397 (match_operand 0 "arm_vsel_comparison_operator")) 398 (match_operand 0 "expandable_comparison_operator"))) 399 400(define_special_predicate "noov_comparison_operator" 401 (match_code "lt,ge,eq,ne")) 402 403(define_special_predicate "minmax_operator" 404 (and (match_code "smin,smax,umin,umax") 405 (match_test "mode == GET_MODE (op)"))) 406 407(define_special_predicate "cc_register" 408 (and (match_code "reg") 409 (and (match_test "REGNO (op) == CC_REGNUM") 410 (ior (match_test "mode == GET_MODE (op)") 411 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))) 412 413(define_special_predicate "dominant_cc_register" 414 (match_code "reg") 415{ 416 if (mode == VOIDmode) 417 { 418 mode = GET_MODE (op); 419 420 if (GET_MODE_CLASS (mode) != MODE_CC) 421 return false; 422 } 423 424 return (cc_register (op, mode) 425 && (mode == CC_DNEmode 426 || mode == CC_DEQmode 427 || mode == CC_DLEmode 428 || mode == CC_DLTmode 429 || mode == CC_DGEmode 430 || mode == CC_DGTmode 431 || mode == CC_DLEUmode 432 || mode == CC_DLTUmode 433 || mode == CC_DGEUmode 434 || mode == CC_DGTUmode)); 435}) 436 437;; Any register, including CC 438(define_predicate "cc_register_operand" 439 (and (match_code "reg") 440 (ior (match_operand 0 "s_register_operand") 441 (match_operand 0 "cc_register")))) 442 443(define_special_predicate "arm_extendqisi_mem_op" 444 (and (match_operand 0 "memory_operand") 445 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, 446 XEXP (op, 0), 447 SIGN_EXTEND, 448 0) 449 : memory_address_p (QImode, XEXP (op, 0))"))) 450 451(define_special_predicate "arm_reg_or_extendqisi_mem_op" 452 (ior (match_operand 0 "arm_extendqisi_mem_op") 453 (match_operand 0 "s_register_operand"))) 454 455(define_predicate "power_of_two_operand" 456 (match_code "const_int") 457{ 458 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff; 459 460 return value != 0 && (value & (value - 1)) == 0; 461}) 462 463(define_predicate "nonimmediate_di_operand" 464 (match_code "reg,subreg,mem") 465{ 466 if (s_register_operand (op, mode)) 467 return true; 468 469 if (GET_CODE (op) == SUBREG) 470 op = SUBREG_REG (op); 471 472 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0)); 473}) 474 475(define_predicate "di_operand" 476 (ior (match_code "const_int,const_double") 477 (and (match_code "reg,subreg,mem") 478 (match_operand 0 "nonimmediate_di_operand")))) 479 480(define_predicate "nonimmediate_soft_df_operand" 481 (match_code "reg,subreg,mem") 482{ 483 if (s_register_operand (op, mode)) 484 return true; 485 486 if (GET_CODE (op) == SUBREG) 487 op = SUBREG_REG (op); 488 489 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0)); 490}) 491 492(define_predicate "soft_df_operand" 493 (ior (match_code "const_double") 494 (and (match_code "reg,subreg,mem") 495 (match_operand 0 "nonimmediate_soft_df_operand")))) 496 497;; Predicate for thumb2_movsf_vfp. Compared to general_operand, this 498;; forbids constant loaded via literal pool iff literal pools are disabled. 499(define_predicate "hard_sf_operand" 500 (and (match_operand 0 "general_operand") 501 (ior (not (match_code "const_double")) 502 (not (match_test "arm_disable_literal_pool")) 503 (match_test "satisfies_constraint_Dv (op)")))) 504 505;; Predicate for thumb2_movdf_vfp. Compared to soft_df_operand used in 506;; movdf_soft_insn, this forbids constant loaded via literal pool iff 507;; literal pools are disabled. 508(define_predicate "hard_df_operand" 509 (and (match_operand 0 "soft_df_operand") 510 (ior (not (match_code "const_double")) 511 (not (match_test "arm_disable_literal_pool")) 512 (match_test "satisfies_constraint_Dy (op)") 513 (match_test "satisfies_constraint_G (op)")))) 514 515(define_special_predicate "load_multiple_operation" 516 (match_code "parallel") 517{ 518 return ldm_stm_operation_p (op, /*load=*/true, SImode, 519 /*consecutive=*/false, 520 /*return_pc=*/false); 521}) 522 523(define_special_predicate "store_multiple_operation" 524 (match_code "parallel") 525{ 526 return ldm_stm_operation_p (op, /*load=*/false, SImode, 527 /*consecutive=*/false, 528 /*return_pc=*/false); 529}) 530 531(define_special_predicate "pop_multiple_return" 532 (match_code "parallel") 533{ 534 return ldm_stm_operation_p (op, /*load=*/true, SImode, 535 /*consecutive=*/false, 536 /*return_pc=*/true); 537}) 538 539(define_special_predicate "pop_multiple_fp" 540 (match_code "parallel") 541{ 542 return ldm_stm_operation_p (op, /*load=*/true, DFmode, 543 /*consecutive=*/true, 544 /*return_pc=*/false); 545}) 546 547(define_special_predicate "multi_register_push" 548 (match_code "parallel") 549{ 550 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET) 551 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) 552 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) 553 return false; 554 555 return true; 556}) 557 558(define_predicate "push_mult_memory_operand" 559 (match_code "mem") 560{ 561 /* ??? Given how PUSH_MULT is generated in the prologues, is there 562 any point in testing for thumb1 specially? All of the variants 563 use the same form. */ 564 if (TARGET_THUMB1) 565 { 566 /* ??? No attempt is made to represent STMIA, or validate that 567 the stack adjustment matches the register count. This is 568 true of the ARM/Thumb2 path as well. */ 569 rtx x = XEXP (op, 0); 570 if (GET_CODE (x) != PRE_MODIFY) 571 return false; 572 if (XEXP (x, 0) != stack_pointer_rtx) 573 return false; 574 x = XEXP (x, 1); 575 if (GET_CODE (x) != PLUS) 576 return false; 577 if (XEXP (x, 0) != stack_pointer_rtx) 578 return false; 579 return CONST_INT_P (XEXP (x, 1)); 580 } 581 582 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */ 583 return memory_operand (op, mode); 584}) 585 586;;------------------------------------------------------------------------- 587;; 588;; Thumb predicates 589;; 590 591(define_predicate "thumb1_cmp_operand" 592 (ior (and (match_code "reg,subreg") 593 (match_operand 0 "s_register_operand")) 594 (and (match_code "const_int") 595 (match_test "(UINTVAL (op)) < 256")))) 596 597(define_predicate "thumb1_cmpneg_operand" 598 (and (match_code "const_int") 599 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256"))) 600 601;; Return TRUE if a result can be stored in OP without clobbering the 602;; condition code register. Prior to reload we only accept a 603;; register. After reload we have to be able to handle memory as 604;; well, since a pseudo may not get a hard reg and reload cannot 605;; handle output-reloads on jump insns. 606 607;; We could possibly handle mem before reload as well, but that might 608;; complicate things with the need to handle increment 609;; side-effects. 610(define_predicate "thumb_cbrch_target_operand" 611 (and (match_code "reg,subreg,mem") 612 (ior (match_operand 0 "s_register_operand") 613 (and (match_test "reload_in_progress || reload_completed") 614 (match_operand 0 "memory_operand"))))) 615 616;;------------------------------------------------------------------------- 617;; 618;; iWMMXt predicates 619;; 620 621(define_predicate "imm_or_reg_operand" 622 (ior (match_operand 0 "immediate_operand") 623 (match_operand 0 "register_operand"))) 624 625;; Neon predicates 626 627(define_predicate "const_multiple_of_8_operand" 628 (match_code "const_int") 629{ 630 unsigned HOST_WIDE_INT val = INTVAL (op); 631 return (val & 7) == 0; 632}) 633 634(define_predicate "imm_for_neon_mov_operand" 635 (match_code "const_vector,const_int") 636{ 637 return neon_immediate_valid_for_move (op, mode, NULL, NULL); 638}) 639 640(define_predicate "imm_for_neon_lshift_operand" 641 (match_code "const_vector") 642{ 643 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true); 644}) 645 646(define_predicate "imm_for_neon_rshift_operand" 647 (match_code "const_vector") 648{ 649 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false); 650}) 651 652(define_predicate "imm_lshift_or_reg_neon" 653 (ior (match_operand 0 "s_register_operand") 654 (match_operand 0 "imm_for_neon_lshift_operand"))) 655 656(define_predicate "imm_rshift_or_reg_neon" 657 (ior (match_operand 0 "s_register_operand") 658 (match_operand 0 "imm_for_neon_rshift_operand"))) 659 660;; Predicates for named expanders that overlap multiple ISAs. 661 662(define_predicate "cmpdi_operand" 663 (and (match_test "TARGET_32BIT") 664 (match_operand 0 "arm_di_operand"))) 665 666;; True if the operand is memory reference suitable for a ldrex/strex. 667(define_predicate "arm_sync_memory_operand" 668 (and (match_operand 0 "memory_operand") 669 (match_code "reg" "0"))) 670 671;; Predicates for parallel expanders based on mode. 672(define_special_predicate "vect_par_constant_high" 673 (match_code "parallel") 674{ 675 return arm_simd_check_vect_par_cnst_half_p (op, mode, true); 676}) 677 678(define_special_predicate "vect_par_constant_low" 679 (match_code "parallel") 680{ 681 return arm_simd_check_vect_par_cnst_half_p (op, mode, false); 682}) 683 684(define_predicate "const_double_vcvt_power_of_two_reciprocal" 685 (and (match_code "const_double") 686 (match_test "TARGET_32BIT 687 && vfp3_const_double_for_fract_bits (op)"))) 688 689(define_predicate "const_double_vcvt_power_of_two" 690 (and (match_code "const_double") 691 (match_test "TARGET_32BIT 692 && vfp3_const_double_for_bits (op) > 0"))) 693 694(define_predicate "neon_struct_operand" 695 (and (match_code "mem") 696 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)"))) 697 698(define_predicate "neon_permissive_struct_operand" 699 (and (match_code "mem") 700 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)"))) 701 702(define_predicate "neon_perm_struct_or_reg_operand" 703 (ior (match_operand 0 "neon_permissive_struct_operand") 704 (match_operand 0 "s_register_operand"))) 705 706(define_special_predicate "add_operator" 707 (match_code "plus")) 708 709(define_predicate "mem_noofs_operand" 710 (and (match_code "mem") 711 (match_code "reg" "0"))) 712 713(define_predicate "call_insn_operand" 714 (ior (and (match_code "symbol_ref") 715 (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))")) 716 (match_operand 0 "s_register_operand"))) 717