1;; Constraint definitions for ARM and Thumb 2;; Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; The following register constraints have been used: 22;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z 23;; - in Thumb state: h, b 24;; - in both states: l, c, k 25;; In ARM state, 'l' is an alias for 'r' 26 27;; The following normal constraints have been used: 28;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M 29;; in Thumb-1 state: I, J, K, L, M, N, O 30 31;; The following multi-letter normal constraints have been used: 32;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy 33;; in Thumb-1 state: Pa, Pb 34;; in Thumb-2 state: Ps, Pt 35 36;; The following memory constraints have been used: 37;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us 38;; in ARM state: Uq 39 40 41(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS" 42 "Legacy FPA registers @code{f0}-@code{f7}.") 43 44(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" 45 "The VFP registers @code{s0}-@code{s31}.") 46 47(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS" 48 "The Cirrus Maverick co-processor registers.") 49 50(define_register_constraint "w" 51 "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS" 52 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.") 53 54(define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS" 55 "The VFP registers @code{d0}-@code{d7}.") 56 57(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS" 58 "The Intel iWMMX co-processor registers.") 59 60(define_register_constraint "z" 61 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS" 62 "The Intel iWMMX GR registers.") 63 64(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS" 65 "In Thumb state the core registers @code{r0}-@code{r7}.") 66 67(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS" 68 "In Thumb state the core registers @code{r8}-@code{r15}.") 69 70(define_constraint "j" 71 "A constant suitable for a MOVW instruction. (ARM/Thumb-2)" 72 (and (match_test "TARGET_32BIT && arm_arch_thumb2") 73 (ior (match_code "high") 74 (and (match_code "const_int") 75 (match_test "(ival & 0xffff0000) == 0"))))) 76 77(define_register_constraint "k" "STACK_REG" 78 "@internal The stack register.") 79 80(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS" 81 "@internal 82 Thumb only. The union of the low registers and the stack register.") 83 84(define_register_constraint "c" "CC_REG" 85 "@internal The condition code register.") 86 87(define_constraint "I" 88 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a 89 Data Processing instruction. In Thumb-1 state a constant in the range 90 0-255." 91 (and (match_code "const_int") 92 (match_test "TARGET_32BIT ? const_ok_for_arm (ival) 93 : ival >= 0 && ival <= 255"))) 94 95(define_constraint "J" 96 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1 97 state a constant in the range @minus{}255-@minus{}1." 98 (and (match_code "const_int") 99 (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095) 100 : (ival >= -255 && ival <= -1)"))) 101 102(define_constraint "K" 103 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if 104 inverted. In Thumb-1 state a constant that satisfies the @code{I} 105 constraint multiplied by any power of 2." 106 (and (match_code "const_int") 107 (match_test "TARGET_32BIT ? const_ok_for_arm (~ival) 108 : thumb_shiftable_const (ival)"))) 109 110(define_constraint "L" 111 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if 112 negated. In Thumb-1 state a constant in the range @minus{}7-7." 113 (and (match_code "const_int") 114 (match_test "TARGET_32BIT ? const_ok_for_arm (-ival) 115 : (ival >= -7 && ival <= 7)"))) 116 117;; The ARM state version is internal... 118;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any 119;; power of 2. 120(define_constraint "M" 121 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020." 122 (and (match_code "const_int") 123 (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32) 124 || ((ival & (ival - 1)) == 0)) 125 : ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))"))) 126 127(define_constraint "N" 128 "Thumb-1 state a constant in the range 0-31." 129 (and (match_code "const_int") 130 (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)"))) 131 132(define_constraint "O" 133 "In Thumb-1 state a constant that is a multiple of 4 in the range 134 @minus{}508-508." 135 (and (match_code "const_int") 136 (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508 137 && ((ival & 3) == 0)"))) 138 139(define_constraint "Pa" 140 "@internal In Thumb-1 state a constant in the range -510 to +510" 141 (and (match_code "const_int") 142 (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510 143 && (ival > 255 || ival < -255)"))) 144 145(define_constraint "Pb" 146 "@internal In Thumb-1 state a constant in the range -262 to +262" 147 (and (match_code "const_int") 148 (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262 149 && (ival > 255 || ival < -255)"))) 150 151(define_constraint "Ps" 152 "@internal In Thumb-2 state a constant in the range -255 to +255" 153 (and (match_code "const_int") 154 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255"))) 155 156(define_constraint "Pt" 157 "@internal In Thumb-2 state a constant in the range -7 to +7" 158 (and (match_code "const_int") 159 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7"))) 160 161(define_constraint "G" 162 "In ARM/Thumb-2 state a valid FPA immediate constant." 163 (and (match_code "const_double") 164 (match_test "TARGET_32BIT && arm_const_double_rtx (op)"))) 165 166(define_constraint "H" 167 "In ARM/Thumb-2 state a valid FPA immediate constant when negated." 168 (and (match_code "const_double") 169 (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)"))) 170 171(define_constraint "Da" 172 "@internal 173 In ARM/Thumb-2 state a const_int, const_double or const_vector that can 174 be generated with two Data Processing insns." 175 (and (match_code "const_double,const_int,const_vector") 176 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2"))) 177 178(define_constraint "Db" 179 "@internal 180 In ARM/Thumb-2 state a const_int, const_double or const_vector that can 181 be generated with three Data Processing insns." 182 (and (match_code "const_double,const_int,const_vector") 183 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3"))) 184 185(define_constraint "Dc" 186 "@internal 187 In ARM/Thumb-2 state a const_int, const_double or const_vector that can 188 be generated with four Data Processing insns. This pattern is disabled 189 if optimizing for space or when we have load-delay slots to fill." 190 (and (match_code "const_double,const_int,const_vector") 191 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4 192 && !(optimize_size || arm_ld_sched)"))) 193 194(define_constraint "Dn" 195 "@internal 196 In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov 197 immediate instruction." 198 (and (match_code "const_vector") 199 (match_test "TARGET_32BIT 200 && imm_for_neon_mov_operand (op, GET_MODE (op))"))) 201 202(define_constraint "Dl" 203 "@internal 204 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or 205 vbic instruction." 206 (and (match_code "const_vector") 207 (match_test "TARGET_32BIT 208 && imm_for_neon_logic_operand (op, GET_MODE (op))"))) 209 210(define_constraint "DL" 211 "@internal 212 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or 213 vand instruction." 214 (and (match_code "const_vector") 215 (match_test "TARGET_32BIT 216 && imm_for_neon_inv_logic_operand (op, GET_MODE (op))"))) 217 218(define_constraint "Dv" 219 "@internal 220 In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts 221 instruction." 222 (and (match_code "const_double") 223 (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)"))) 224 225(define_constraint "Dy" 226 "@internal 227 In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd 228 instruction." 229 (and (match_code "const_double") 230 (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)"))) 231 232(define_memory_constraint "Ut" 233 "@internal 234 In ARM/Thumb-2 state an address valid for loading/storing opaque structure 235 types wider than TImode." 236 (and (match_code "mem") 237 (match_test "TARGET_32BIT && neon_struct_mem_operand (op)"))) 238 239(define_memory_constraint "Uv" 240 "@internal 241 In ARM/Thumb-2 state a valid VFP load/store address." 242 (and (match_code "mem") 243 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)"))) 244 245(define_memory_constraint "Uy" 246 "@internal 247 In ARM/Thumb-2 state a valid iWMMX load/store address." 248 (and (match_code "mem") 249 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)"))) 250 251(define_memory_constraint "Un" 252 "@internal 253 In ARM/Thumb-2 state a valid address for Neon doubleword vector 254 load/store instructions." 255 (and (match_code "mem") 256 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)"))) 257 258(define_memory_constraint "Um" 259 "@internal 260 In ARM/Thumb-2 state a valid address for Neon element and structure 261 load/store instructions." 262 (and (match_code "mem") 263 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)"))) 264 265(define_memory_constraint "Us" 266 "@internal 267 In ARM/Thumb-2 state a valid address for non-offset loads/stores of 268 quad-word values in four ARM registers." 269 (and (match_code "mem") 270 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)"))) 271 272(define_memory_constraint "Uq" 273 "@internal 274 In ARM state an address valid in ldrsb instructions." 275 (and (match_code "mem") 276 (match_test "TARGET_ARM 277 && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0), 278 SIGN_EXTEND, 0)"))) 279 280(define_memory_constraint "Q" 281 "@internal 282 In ARM/Thumb-2 state an address that is a single base register." 283 (and (match_code "mem") 284 (match_test "REG_P (XEXP (op, 0))"))) 285 286;; We used to have constraint letters for S and R in ARM state, but 287;; all uses of these now appear to have been removed. 288 289;; Additionally, we used to have a Q constraint in Thumb state, but 290;; this wasn't really a valid memory constraint. Again, all uses of 291;; this now seem to have been removed. 292