1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2015 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha@arm.com) 6 Minor hacks by Nick Clifton (nickc@cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() \ 49 do \ 50 { \ 51 if (TARGET_DSP_MULTIPLY) \ 52 builtin_define ("__ARM_FEATURE_DSP"); \ 53 if (TARGET_ARM_QBIT) \ 54 builtin_define ("__ARM_FEATURE_QBIT"); \ 55 if (TARGET_ARM_SAT) \ 56 builtin_define ("__ARM_FEATURE_SAT"); \ 57 if (TARGET_CRYPTO) \ 58 builtin_define ("__ARM_FEATURE_CRYPTO"); \ 59 if (unaligned_access) \ 60 builtin_define ("__ARM_FEATURE_UNALIGNED"); \ 61 if (TARGET_CRC32) \ 62 builtin_define ("__ARM_FEATURE_CRC32"); \ 63 if (TARGET_32BIT) \ 64 builtin_define ("__ARM_32BIT_STATE"); \ 65 if (TARGET_ARM_FEATURE_LDREX) \ 66 builtin_define_with_int_value ( \ 67 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \ 68 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \ 69 || TARGET_ARM_ARCH_ISA_THUMB >=2) \ 70 builtin_define ("__ARM_FEATURE_CLZ"); \ 71 if (TARGET_INT_SIMD) \ 72 builtin_define ("__ARM_FEATURE_SIMD32"); \ 73 \ 74 builtin_define_with_int_value ( \ 75 "__ARM_SIZEOF_MINIMAL_ENUM", \ 76 flag_short_enums ? 1 : 4); \ 77 builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T", \ 78 wchar_type_node); \ 79 if (TARGET_ARM_ARCH_PROFILE) \ 80 builtin_define_with_int_value ( \ 81 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \ 82 \ 83 /* Define __arm__ even when in thumb mode, for \ 84 consistency with armcc. */ \ 85 builtin_define ("__arm__"); \ 86 if (TARGET_ARM_ARCH) \ 87 builtin_define_with_int_value ( \ 88 "__ARM_ARCH", TARGET_ARM_ARCH); \ 89 if (arm_arch_notm) \ 90 builtin_define ("__ARM_ARCH_ISA_ARM"); \ 91 builtin_define ("__APCS_32__"); \ 92 if (TARGET_THUMB) \ 93 builtin_define ("__thumb__"); \ 94 if (TARGET_THUMB2) \ 95 builtin_define ("__thumb2__"); \ 96 if (TARGET_ARM_ARCH_ISA_THUMB) \ 97 builtin_define_with_int_value ( \ 98 "__ARM_ARCH_ISA_THUMB", \ 99 TARGET_ARM_ARCH_ISA_THUMB); \ 100 \ 101 if (TARGET_BIG_END) \ 102 { \ 103 builtin_define ("__ARMEB__"); \ 104 builtin_define ("__ARM_BIG_ENDIAN"); \ 105 if (TARGET_THUMB) \ 106 builtin_define ("__THUMBEB__"); \ 107 } \ 108 else \ 109 { \ 110 builtin_define ("__ARMEL__"); \ 111 if (TARGET_THUMB) \ 112 builtin_define ("__THUMBEL__"); \ 113 } \ 114 \ 115 if (TARGET_SOFT_FLOAT) \ 116 builtin_define ("__SOFTFP__"); \ 117 \ 118 if (TARGET_VFP) \ 119 builtin_define ("__VFP_FP__"); \ 120 \ 121 if (TARGET_ARM_FP) \ 122 builtin_define_with_int_value ( \ 123 "__ARM_FP", TARGET_ARM_FP); \ 124 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \ 125 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \ 126 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \ 127 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \ 128 if (TARGET_FMA) \ 129 builtin_define ("__ARM_FEATURE_FMA"); \ 130 \ 131 if (TARGET_NEON) \ 132 { \ 133 builtin_define ("__ARM_NEON__"); \ 134 builtin_define ("__ARM_NEON"); \ 135 } \ 136 if (TARGET_NEON_FP) \ 137 builtin_define_with_int_value ( \ 138 "__ARM_NEON_FP", TARGET_NEON_FP); \ 139 \ 140 /* Add a define for interworking. \ 141 Needed when building libgcc.a. */ \ 142 if (arm_cpp_interwork) \ 143 builtin_define ("__THUMB_INTERWORK__"); \ 144 \ 145 builtin_assert ("cpu=arm"); \ 146 builtin_assert ("machine=arm"); \ 147 \ 148 builtin_define (arm_arch_name); \ 149 if (arm_arch_xscale) \ 150 builtin_define ("__XSCALE__"); \ 151 if (arm_arch_iwmmxt) \ 152 { \ 153 builtin_define ("__IWMMXT__"); \ 154 builtin_define ("__ARM_WMMX"); \ 155 } \ 156 if (arm_arch_iwmmxt2) \ 157 builtin_define ("__IWMMXT2__"); \ 158 if (TARGET_AAPCS_BASED) \ 159 { \ 160 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ 161 builtin_define ("__ARM_PCS_VFP"); \ 162 else if (arm_pcs_default == ARM_PCS_AAPCS) \ 163 builtin_define ("__ARM_PCS"); \ 164 builtin_define ("__ARM_EABI__"); \ 165 } \ 166 if (TARGET_IDIV) \ 167 { \ 168 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ 169 builtin_define ("__ARM_FEATURE_IDIV"); \ 170 } \ 171 if (inline_asm_unified) \ 172 builtin_define ("__ARM_ASM_SYNTAX_UNIFIED__");\ 173 } while (0) 174 175 #include "config/arm/arm-opts.h" 176 177 enum target_cpus 178 { 179 #define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ 180 TARGET_CPU_##INTERNAL_IDENT, 181 #include "arm-cores.def" 182 #undef ARM_CORE 183 TARGET_CPU_generic 184 }; 185 186 /* The processor for which instructions should be scheduled. */ 187 extern enum processor_type arm_tune; 188 189 typedef enum arm_cond_code 190 { 191 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 192 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 193 } 194 arm_cc; 195 196 extern arm_cc arm_current_cc; 197 198 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 199 200 /* The maximum number of instructions that is beneficial to 201 conditionally execute. */ 202 #undef MAX_CONDITIONAL_EXECUTE 203 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 204 205 extern int arm_target_label; 206 extern int arm_ccfsm_state; 207 extern GTY(()) rtx arm_target_insn; 208 /* The label of the current constant pool. */ 209 extern rtx pool_vector_label; 210 /* Set to 1 when a return insn is output, this means that the epilogue 211 is not needed. */ 212 extern int return_used_this_function; 213 /* Callback to output language specific object attributes. */ 214 extern void (*arm_lang_output_object_attributes_hook)(void); 215 216 /* Just in case configure has failed to define anything. */ 217 #ifndef TARGET_CPU_DEFAULT 218 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 219 #endif 220 221 222 #undef CPP_SPEC 223 #define CPP_SPEC "%(subtarget_cpp_spec) \ 224 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 225 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 226 %{mbig-endian:%{mlittle-endian: \ 227 %e-mbig-endian and -mlittle-endian may not be used together}}" 228 229 #ifndef CC1_SPEC 230 #define CC1_SPEC "" 231 #endif 232 233 /* This macro defines names of additional specifications to put in the specs 234 that can be used in various specifications like CC1_SPEC. Its definition 235 is an initializer with a subgrouping for each command option. 236 237 Each subgrouping contains a string constant, that defines the 238 specification name, and a string constant that used by the GCC driver 239 program. 240 241 Do not define this macro if it does not need to do anything. */ 242 #define EXTRA_SPECS \ 243 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 244 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 245 SUBTARGET_EXTRA_SPECS 246 247 #ifndef SUBTARGET_EXTRA_SPECS 248 #define SUBTARGET_EXTRA_SPECS 249 #endif 250 251 #ifndef SUBTARGET_CPP_SPEC 252 #define SUBTARGET_CPP_SPEC "" 253 #endif 254 255 /* Run-time Target Specification. */ 256 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 257 /* Use hardware floating point instructions. */ 258 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 259 /* Use hardware floating point calling convention. */ 260 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 261 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 262 #define TARGET_IWMMXT (arm_arch_iwmmxt) 263 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 264 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 265 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) 266 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 267 #define TARGET_ARM (! TARGET_THUMB) 268 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 269 #define TARGET_BACKTRACE (leaf_function_p () \ 270 ? TARGET_TPCS_LEAF_FRAME \ 271 : TARGET_TPCS_FRAME) 272 #define TARGET_AAPCS_BASED \ 273 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 274 275 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 276 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 277 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 278 279 /* Only 16-bit thumb code. */ 280 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 281 /* Arm or Thumb-2 32-bit code. */ 282 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 283 /* 32-bit Thumb-2 code. */ 284 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 285 /* Thumb-1 only. */ 286 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 287 288 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ 289 && !TARGET_THUMB1) 290 291 #define TARGET_CRC32 (arm_arch_crc) 292 293 /* The following two macros concern the ability to execute coprocessor 294 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 295 only ever tested when we know we are generating for VFP hardware; we need 296 to be more careful with TARGET_NEON as noted below. */ 297 298 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 299 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 300 301 /* FPU supports VFPv3 instructions. */ 302 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 303 304 /* FPU supports FPv5 instructions. */ 305 #define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5) 306 307 /* FPU only supports VFP single-precision instructions. */ 308 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 309 310 /* FPU supports VFP double-precision instructions. */ 311 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 312 313 /* FPU supports half-precision floating-point with NEON element load/store. */ 314 #define TARGET_NEON_FP16 \ 315 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 316 317 /* FPU supports VFP half-precision floating-point. */ 318 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 319 320 /* FPU supports fused-multiply-add operations. */ 321 #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) 322 323 /* FPU is ARMv8 compatible. */ 324 #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8) 325 326 /* FPU supports Crypto extensions. */ 327 #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto) 328 329 /* FPU supports Neon instructions. The setting of this macro gets 330 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 331 and TARGET_HARD_FLOAT to ensure that NEON instructions are 332 available. */ 333 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 334 && TARGET_VFP && arm_fpu_desc->neon) 335 336 /* Q-bit is present. */ 337 #define TARGET_ARM_QBIT \ 338 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) 339 /* Saturation operation, e.g. SSAT. */ 340 #define TARGET_ARM_SAT \ 341 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 342 /* "DSP" multiply instructions, eg. SMULxy. */ 343 #define TARGET_DSP_MULTIPLY \ 344 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 345 /* Integer SIMD instructions, and extend-accumulate instructions. */ 346 #define TARGET_INT_SIMD \ 347 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 348 349 /* Should MOVW/MOVT be used in preference to a constant pool. */ 350 #define TARGET_USE_MOVT \ 351 (arm_arch_thumb2 \ 352 && (arm_disable_literal_pool \ 353 || (!optimize_size && !current_tune->prefer_constant_pool))) 354 355 /* We could use unified syntax for arm mode, but for now we just use it 356 for thumb mode. */ 357 #define TARGET_UNIFIED_ASM (TARGET_THUMB) 358 359 /* Nonzero if this chip provides the DMB instruction. */ 360 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 361 362 /* Nonzero if this chip implements a memory barrier via CP15. */ 363 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 364 && ! TARGET_THUMB1) 365 366 /* Nonzero if this chip implements a memory barrier instruction. */ 367 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 368 369 /* Nonzero if this chip supports ldrex and strex */ 370 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) 371 372 /* Nonzero if this chip supports LPAE. */ 373 #define TARGET_HAVE_LPAE (arm_arch_lpae) 374 375 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 376 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) 377 378 /* Nonzero if this chip supports ldrexd and strexd. */ 379 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ 380 && arm_arch_notm) 381 382 /* Nonzero if this chip supports load-acquire and store-release. */ 383 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 384 385 /* Nonzero if integer division instructions supported. */ 386 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 387 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) 388 389 /* Nonzero if disallow volatile memory access in IT block. */ 390 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 391 392 /* Should NEON be used for 64-bits bitops. */ 393 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 394 395 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 396 then TARGET_AAPCS_BASED must be true -- but the converse does not 397 hold. TARGET_BPABI implies the use of the BPABI runtime library, 398 etc., in addition to just the AAPCS calling conventions. */ 399 #ifndef TARGET_BPABI 400 #define TARGET_BPABI false 401 #endif 402 403 /* Support for a compile-time default CPU, et cetera. The rules are: 404 --with-arch is ignored if -march or -mcpu are specified. 405 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 406 by --with-arch. 407 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 408 by -march). 409 --with-float is ignored if -mfloat-abi is specified. 410 --with-fpu is ignored if -mfpu is specified. 411 --with-abi is ignored if -mabi is specified. 412 --with-tls is ignored if -mtls-dialect is specified. */ 413 #define OPTION_DEFAULT_SPECS \ 414 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 415 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 416 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 417 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 418 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 419 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 420 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 421 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 422 423 /* Which floating point model to use. */ 424 enum arm_fp_model 425 { 426 ARM_FP_MODEL_UNKNOWN, 427 /* VFP floating point model. */ 428 ARM_FP_MODEL_VFP 429 }; 430 431 enum vfp_reg_type 432 { 433 VFP_NONE = 0, 434 VFP_REG_D16, 435 VFP_REG_D32, 436 VFP_REG_SINGLE 437 }; 438 439 extern const struct arm_fpu_desc 440 { 441 const char *name; 442 enum arm_fp_model model; 443 int rev; 444 enum vfp_reg_type regs; 445 int neon; 446 int fp16; 447 int crypto; 448 } *arm_fpu_desc; 449 450 /* Which floating point hardware to schedule for. */ 451 extern int arm_fpu_attr; 452 453 #ifndef TARGET_DEFAULT_FLOAT_ABI 454 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 455 #endif 456 457 #ifndef ARM_DEFAULT_ABI 458 #define ARM_DEFAULT_ABI ARM_ABI_APCS 459 #endif 460 461 /* Map each of the micro-architecture variants to their corresponding 462 major architecture revision. */ 463 464 enum base_architecture 465 { 466 BASE_ARCH_0 = 0, 467 BASE_ARCH_2 = 2, 468 BASE_ARCH_3 = 3, 469 BASE_ARCH_3M = 3, 470 BASE_ARCH_4 = 4, 471 BASE_ARCH_4T = 4, 472 BASE_ARCH_5 = 5, 473 BASE_ARCH_5E = 5, 474 BASE_ARCH_5T = 5, 475 BASE_ARCH_5TE = 5, 476 BASE_ARCH_5TEJ = 5, 477 BASE_ARCH_6 = 6, 478 BASE_ARCH_6J = 6, 479 BASE_ARCH_6ZK = 6, 480 BASE_ARCH_6K = 6, 481 BASE_ARCH_6T2 = 6, 482 BASE_ARCH_6M = 6, 483 BASE_ARCH_6Z = 6, 484 BASE_ARCH_7 = 7, 485 BASE_ARCH_7A = 7, 486 BASE_ARCH_7R = 7, 487 BASE_ARCH_7M = 7, 488 BASE_ARCH_7EM = 7, 489 BASE_ARCH_8A = 8 490 }; 491 492 /* The major revision number of the ARM Architecture implemented by the target. */ 493 extern enum base_architecture arm_base_arch; 494 495 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 496 extern int arm_arch3m; 497 498 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 499 extern int arm_arch4; 500 501 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 502 extern int arm_arch4t; 503 504 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 505 extern int arm_arch5; 506 507 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 508 extern int arm_arch5e; 509 510 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 511 extern int arm_arch6; 512 513 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 514 extern int arm_arch6k; 515 516 /* Nonzero if instructions present in ARMv6-M can be used. */ 517 extern int arm_arch6m; 518 519 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 520 extern int arm_arch7; 521 522 /* Nonzero if instructions not present in the 'M' profile can be used. */ 523 extern int arm_arch_notm; 524 525 /* Nonzero if instructions present in ARMv7E-M can be used. */ 526 extern int arm_arch7em; 527 528 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 529 extern int arm_arch8; 530 531 /* Nonzero if this chip can benefit from load scheduling. */ 532 extern int arm_ld_sched; 533 534 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ 535 extern int thumb_code; 536 537 /* Nonzero if generating Thumb-1 code. */ 538 extern int thumb1_code; 539 540 /* Nonzero if this chip is a StrongARM. */ 541 extern int arm_tune_strongarm; 542 543 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 544 extern int arm_arch_iwmmxt; 545 546 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 547 extern int arm_arch_iwmmxt2; 548 549 /* Nonzero if this chip is an XScale. */ 550 extern int arm_arch_xscale; 551 552 /* Nonzero if tuning for XScale. */ 553 extern int arm_tune_xscale; 554 555 /* Nonzero if tuning for stores via the write buffer. */ 556 extern int arm_tune_wbuf; 557 558 /* Nonzero if tuning for Cortex-A9. */ 559 extern int arm_tune_cortex_a9; 560 561 /* Nonzero if we should define __THUMB_INTERWORK__ in the 562 preprocessor. 563 XXX This is a bit of a hack, it's intended to help work around 564 problems in GLD which doesn't understand that armv5t code is 565 interworking clean. */ 566 extern int arm_cpp_interwork; 567 568 /* Nonzero if chip supports Thumb 2. */ 569 extern int arm_arch_thumb2; 570 571 /* Nonzero if chip supports integer division instruction in ARM mode. */ 572 extern int arm_arch_arm_hwdiv; 573 574 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 575 extern int arm_arch_thumb_hwdiv; 576 577 /* Nonzero if chip disallows volatile memory access in IT block. */ 578 extern int arm_arch_no_volatile_ce; 579 580 /* Nonzero if we should use Neon to handle 64-bits operations rather 581 than core registers. */ 582 extern int prefer_neon_for_64bits; 583 584 /* Nonzero if we shouldn't use literal pools. */ 585 #ifndef USED_FOR_TARGET 586 extern bool arm_disable_literal_pool; 587 #endif 588 589 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 590 extern int arm_arch_crc; 591 592 #ifndef TARGET_DEFAULT 593 #define TARGET_DEFAULT (MASK_APCS_FRAME) 594 #endif 595 596 /* Nonzero if PIC code requires explicit qualifiers to generate 597 PLT and GOT relocs rather than the assembler doing so implicitly. 598 Subtargets can override these if required. */ 599 #ifndef NEED_GOT_RELOC 600 #define NEED_GOT_RELOC 0 601 #endif 602 #ifndef NEED_PLT_RELOC 603 #define NEED_PLT_RELOC 0 604 #endif 605 606 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 607 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 608 #endif 609 610 /* Nonzero if we need to refer to the GOT with a PC-relative 611 offset. In other words, generate 612 613 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 614 615 rather than 616 617 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 618 619 The default is true, which matches NetBSD. Subtargets can 620 override this if required. */ 621 #ifndef GOT_PCREL 622 #define GOT_PCREL 1 623 #endif 624 625 /* Target machine storage Layout. */ 626 627 628 /* Define this macro if it is advisable to hold scalars in registers 629 in a wider mode than that declared by the program. In such cases, 630 the value is constrained to be within the bounds of the declared 631 type, but kept valid in the wider mode. The signedness of the 632 extension may differ from that of the type. */ 633 634 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 635 if (GET_MODE_CLASS (MODE) == MODE_INT \ 636 && GET_MODE_SIZE (MODE) < 4) \ 637 { \ 638 (MODE) = SImode; \ 639 } 640 641 /* Define this if most significant bit is lowest numbered 642 in instructions that operate on numbered bit-fields. */ 643 #define BITS_BIG_ENDIAN 0 644 645 /* Define this if most significant byte of a word is the lowest numbered. 646 Most ARM processors are run in little endian mode, so that is the default. 647 If you want to have it run-time selectable, change the definition in a 648 cover file to be TARGET_BIG_ENDIAN. */ 649 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 650 651 /* Define this if most significant word of a multiword number is the lowest 652 numbered. */ 653 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 654 655 #define UNITS_PER_WORD 4 656 657 /* True if natural alignment is used for doubleword types. */ 658 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 659 660 #define DOUBLEWORD_ALIGNMENT 64 661 662 #define PARM_BOUNDARY 32 663 664 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 665 666 #define PREFERRED_STACK_BOUNDARY \ 667 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 668 669 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 670 671 /* The lowest bit is used to indicate Thumb-mode functions, so the 672 vbit must go into the delta field of pointers to member 673 functions. */ 674 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 675 676 #define EMPTY_FIELD_BOUNDARY 32 677 678 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 679 680 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 681 682 /* XXX Blah -- this macro is used directly by libobjc. Since it 683 supports no vector modes, cut out the complexity and fall back 684 on BIGGEST_FIELD_ALIGNMENT. */ 685 #ifdef IN_TARGET_LIBS 686 #define BIGGEST_FIELD_ALIGNMENT 64 687 #endif 688 689 /* Make strings word-aligned so strcpy from constants will be faster. */ 690 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 691 692 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 693 ((TREE_CODE (EXP) == STRING_CST \ 694 && !optimize_size \ 695 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 696 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 697 698 /* Align definitions of arrays, unions and structures so that 699 initializations and copies can be made more efficient. This is not 700 ABI-changing, so it only affects places where we can see the 701 definition. Increasing the alignment tends to introduce padding, 702 so don't do this when optimizing for size/conserving stack space. */ 703 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 704 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 705 && (TREE_CODE (EXP) == ARRAY_TYPE \ 706 || TREE_CODE (EXP) == UNION_TYPE \ 707 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 708 709 /* Align global data. */ 710 #define DATA_ALIGNMENT(EXP, ALIGN) \ 711 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 712 713 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 714 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 715 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 716 717 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 718 value set in previous versions of this toolchain was 8, which produces more 719 compact structures. The command line option -mstructure_size_boundary=<n> 720 can be used to change this value. For compatibility with the ARM SDK 721 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 722 0020D) page 2-20 says "Structures are aligned on word boundaries". 723 The AAPCS specifies a value of 8. */ 724 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 725 726 /* This is the value used to initialize arm_structure_size_boundary. If a 727 particular arm target wants to change the default value it should change 728 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 729 for an example of this. */ 730 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 731 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 732 #endif 733 734 /* Nonzero if move instructions will actually fail to work 735 when given unaligned data. */ 736 #define STRICT_ALIGNMENT 1 737 738 /* wchar_t is unsigned under the AAPCS. */ 739 #ifndef WCHAR_TYPE 740 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 741 742 #define WCHAR_TYPE_SIZE BITS_PER_WORD 743 #endif 744 745 /* Sized for fixed-point types. */ 746 747 #define SHORT_FRACT_TYPE_SIZE 8 748 #define FRACT_TYPE_SIZE 16 749 #define LONG_FRACT_TYPE_SIZE 32 750 #define LONG_LONG_FRACT_TYPE_SIZE 64 751 752 #define SHORT_ACCUM_TYPE_SIZE 16 753 #define ACCUM_TYPE_SIZE 32 754 #define LONG_ACCUM_TYPE_SIZE 64 755 #define LONG_LONG_ACCUM_TYPE_SIZE 64 756 757 #define MAX_FIXED_MODE_SIZE 64 758 759 #ifndef SIZE_TYPE 760 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 761 #endif 762 763 #ifndef PTRDIFF_TYPE 764 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 765 #endif 766 767 /* AAPCS requires that structure alignment is affected by bitfields. */ 768 #ifndef PCC_BITFIELD_TYPE_MATTERS 769 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 770 #endif 771 772 /* The maximum size of the sync library functions supported. */ 773 #ifndef MAX_SYNC_LIBFUNC_SIZE 774 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 775 #endif 776 777 778 /* Standard register usage. */ 779 780 /* Register allocation in ARM Procedure Call Standard 781 (S - saved over call). 782 783 r0 * argument word/integer result 784 r1-r3 argument word 785 786 r4-r8 S register variable 787 r9 S (rfp) register variable (real frame pointer) 788 789 r10 F S (sl) stack limit (used by -mapcs-stack-check) 790 r11 F S (fp) argument pointer 791 r12 (ip) temp workspace 792 r13 F S (sp) lower end of current stack frame 793 r14 (lr) link address/workspace 794 r15 F (pc) program counter 795 796 cc This is NOT a real register, but is used internally 797 to represent things that use or set the condition 798 codes. 799 sfp This isn't either. It is used during rtl generation 800 since the offset between the frame pointer and the 801 auto's isn't known until after register allocation. 802 afp Nor this, we only need this because of non-local 803 goto. Without it fp appears to be used and the 804 elimination code won't get rid of sfp. It tracks 805 fp exactly at all times. 806 807 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 808 809 /* s0-s15 VFP scratch (aka d0-d7). 810 s16-s31 S VFP variable (aka d8-d15). 811 vfpcc Not a real register. Represents the VFP condition 812 code flags. */ 813 814 /* The stack backtrace structure is as follows: 815 fp points to here: | save code pointer | [fp] 816 | return link value | [fp, #-4] 817 | return sp value | [fp, #-8] 818 | return fp value | [fp, #-12] 819 [| saved r10 value |] 820 [| saved r9 value |] 821 [| saved r8 value |] 822 [| saved r7 value |] 823 [| saved r6 value |] 824 [| saved r5 value |] 825 [| saved r4 value |] 826 [| saved r3 value |] 827 [| saved r2 value |] 828 [| saved r1 value |] 829 [| saved r0 value |] 830 r0-r3 are not normally saved in a C function. */ 831 832 /* 1 for registers that have pervasive standard uses 833 and are not available for the register allocator. */ 834 #define FIXED_REGISTERS \ 835 { \ 836 /* Core regs. */ \ 837 0,0,0,0,0,0,0,0, \ 838 0,0,0,0,0,1,0,1, \ 839 /* VFP regs. */ \ 840 1,1,1,1,1,1,1,1, \ 841 1,1,1,1,1,1,1,1, \ 842 1,1,1,1,1,1,1,1, \ 843 1,1,1,1,1,1,1,1, \ 844 1,1,1,1,1,1,1,1, \ 845 1,1,1,1,1,1,1,1, \ 846 1,1,1,1,1,1,1,1, \ 847 1,1,1,1,1,1,1,1, \ 848 /* IWMMXT regs. */ \ 849 1,1,1,1,1,1,1,1, \ 850 1,1,1,1,1,1,1,1, \ 851 1,1,1,1, \ 852 /* Specials. */ \ 853 1,1,1,1 \ 854 } 855 856 /* 1 for registers not available across function calls. 857 These must include the FIXED_REGISTERS and also any 858 registers that can be used without being saved. 859 The latter must include the registers where values are returned 860 and the register where structure-value addresses are passed. 861 Aside from that, you can include as many other registers as you like. 862 The CC is not preserved over function calls on the ARM 6, so it is 863 easier to assume this for all. SFP is preserved, since FP is. */ 864 #define CALL_USED_REGISTERS \ 865 { \ 866 /* Core regs. */ \ 867 1,1,1,1,0,0,0,0, \ 868 0,0,0,0,1,1,1,1, \ 869 /* VFP Regs. */ \ 870 1,1,1,1,1,1,1,1, \ 871 1,1,1,1,1,1,1,1, \ 872 1,1,1,1,1,1,1,1, \ 873 1,1,1,1,1,1,1,1, \ 874 1,1,1,1,1,1,1,1, \ 875 1,1,1,1,1,1,1,1, \ 876 1,1,1,1,1,1,1,1, \ 877 1,1,1,1,1,1,1,1, \ 878 /* IWMMXT regs. */ \ 879 1,1,1,1,1,1,1,1, \ 880 1,1,1,1,1,1,1,1, \ 881 1,1,1,1, \ 882 /* Specials. */ \ 883 1,1,1,1 \ 884 } 885 886 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 887 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 888 #endif 889 890 /* These are a couple of extensions to the formats accepted 891 by asm_fprintf: 892 %@ prints out ASM_COMMENT_START 893 %r prints out REGISTER_PREFIX reg_names[arg] */ 894 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 895 case '@': \ 896 fputs (ASM_COMMENT_START, FILE); \ 897 break; \ 898 \ 899 case 'r': \ 900 fputs (REGISTER_PREFIX, FILE); \ 901 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 902 break; 903 904 /* Round X up to the nearest word. */ 905 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 906 907 /* Convert fron bytes to ints. */ 908 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 909 910 /* The number of (integer) registers required to hold a quantity of type MODE. 911 Also used for VFP registers. */ 912 #define ARM_NUM_REGS(MODE) \ 913 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 914 915 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 916 #define ARM_NUM_REGS2(MODE, TYPE) \ 917 ARM_NUM_INTS ((MODE) == BLKmode ? \ 918 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 919 920 /* The number of (integer) argument register available. */ 921 #define NUM_ARG_REGS 4 922 923 /* And similarly for the VFP. */ 924 #define NUM_VFP_ARG_REGS 16 925 926 /* Return the register number of the N'th (integer) argument. */ 927 #define ARG_REGISTER(N) (N - 1) 928 929 /* Specify the registers used for certain standard purposes. 930 The values of these macros are register numbers. */ 931 932 /* The number of the last argument register. */ 933 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 934 935 /* The numbers of the Thumb register ranges. */ 936 #define FIRST_LO_REGNUM 0 937 #define LAST_LO_REGNUM 7 938 #define FIRST_HI_REGNUM 8 939 #define LAST_HI_REGNUM 11 940 941 /* Overridden by config/arm/bpabi.h. */ 942 #ifndef ARM_UNWIND_INFO 943 #define ARM_UNWIND_INFO 0 944 #endif 945 946 /* Overriden by config/arm/netbsd-eabi.h. */ 947 #ifndef ARM_DWARF_UNWIND_TABLES 948 #define ARM_DWARF_UNWIND_TABLES 0 949 #endif 950 951 /* Use r0 and r1 to pass exception handling information. */ 952 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 953 954 /* The register that holds the return address in exception handlers. */ 955 #define ARM_EH_STACKADJ_REGNUM 2 956 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 957 958 #ifndef ARM_TARGET2_DWARF_FORMAT 959 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 960 #endif 961 962 #if ARM_DWARF_UNWIND_TABLES 963 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 964 for 32bit platforms. */ 965 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 966 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 967 : DW_EH_PE_absptr) 968 #else 969 /* ttype entries (the only interesting data references used) 970 use TARGET2 relocations. */ 971 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 972 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 973 : DW_EH_PE_absptr) 974 #endif 975 976 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 977 as an invisible last argument (possible since varargs don't exist in 978 Pascal), so the following is not true. */ 979 #define STATIC_CHAIN_REGNUM 12 980 981 /* Define this to be where the real frame pointer is if it is not possible to 982 work out the offset between the frame pointer and the automatic variables 983 until after register allocation has taken place. FRAME_POINTER_REGNUM 984 should point to a special register that we will make sure is eliminated. 985 986 For the Thumb we have another problem. The TPCS defines the frame pointer 987 as r11, and GCC believes that it is always possible to use the frame pointer 988 as base register for addressing purposes. (See comments in 989 find_reloads_address()). But - the Thumb does not allow high registers, 990 including r11, to be used as base address registers. Hence our problem. 991 992 The solution used here, and in the old thumb port is to use r7 instead of 993 r11 as the hard frame pointer and to have special code to generate 994 backtrace structures on the stack (if required to do so via a command line 995 option) using r11. This is the only 'user visible' use of r11 as a frame 996 pointer. */ 997 #define ARM_HARD_FRAME_POINTER_REGNUM 11 998 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 999 1000 #define HARD_FRAME_POINTER_REGNUM \ 1001 (TARGET_ARM \ 1002 ? ARM_HARD_FRAME_POINTER_REGNUM \ 1003 : THUMB_HARD_FRAME_POINTER_REGNUM) 1004 1005 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 1006 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 1007 1008 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 1009 1010 /* Register to use for pushing function arguments. */ 1011 #define STACK_POINTER_REGNUM SP_REGNUM 1012 1013 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 1014 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 1015 1016 /* Need to sync with WCGR in iwmmxt.md. */ 1017 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 1018 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 1019 1020 #define IS_IWMMXT_REGNUM(REGNUM) \ 1021 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1022 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1023 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1024 1025 /* Base register for access to local variables of the function. */ 1026 #define FRAME_POINTER_REGNUM 102 1027 1028 /* Base register for access to arguments of the function. */ 1029 #define ARG_POINTER_REGNUM 103 1030 1031 #define FIRST_VFP_REGNUM 16 1032 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1033 #define LAST_VFP_REGNUM \ 1034 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1035 1036 #define IS_VFP_REGNUM(REGNUM) \ 1037 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1038 1039 /* VFP registers are split into two types: those defined by VFP versions < 3 1040 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1041 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1042 in various parts of the backend, we implement as "fake" single-precision 1043 registers (which would be S32-S63, but cannot be used in that way). The 1044 following macros define these ranges of registers. */ 1045 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1046 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1047 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1048 1049 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1050 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1051 1052 /* DFmode values are only valid in even register pairs. */ 1053 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1054 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1055 1056 /* Neon Quad values must start at a multiple of four registers. */ 1057 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1058 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1059 1060 /* Neon structures of vectors must be in even register pairs and there 1061 must be enough registers available. Because of various patterns 1062 requiring quad registers, we require them to start at a multiple of 1063 four. */ 1064 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1065 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1066 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1067 1068 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 1069 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1070 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1071 #define FIRST_PSEUDO_REGISTER 104 1072 1073 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1074 1075 /* Value should be nonzero if functions must have frame pointers. 1076 Zero means the frame pointer need not be set up (and parms may be accessed 1077 via the stack pointer) in functions that seem suitable. 1078 If we have to have a frame pointer we might as well make use of it. 1079 APCS says that the frame pointer does not need to be pushed in leaf 1080 functions, or simple tail call functions. */ 1081 1082 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1083 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1084 #endif 1085 1086 /* Return number of consecutive hard regs needed starting at reg REGNO 1087 to hold something of mode MODE. 1088 This is ordinarily the length in words of a value of mode MODE 1089 but can be less for certain modes in special long registers. 1090 1091 On the ARM core regs are UNITS_PER_WORD bits wide. */ 1092 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1093 ((TARGET_32BIT \ 1094 && REGNO > PC_REGNUM \ 1095 && REGNO != FRAME_POINTER_REGNUM \ 1096 && REGNO != ARG_POINTER_REGNUM) \ 1097 && !IS_VFP_REGNUM (REGNO) \ 1098 ? 1 : ARM_NUM_REGS (MODE)) 1099 1100 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1101 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1102 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1103 1104 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) 1105 1106 #define VALID_IWMMXT_REG_MODE(MODE) \ 1107 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1108 1109 /* Modes valid for Neon D registers. */ 1110 #define VALID_NEON_DREG_MODE(MODE) \ 1111 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1112 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1113 1114 /* Modes valid for Neon Q registers. */ 1115 #define VALID_NEON_QREG_MODE(MODE) \ 1116 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1117 || (MODE) == V4SFmode || (MODE) == V2DImode) 1118 1119 /* Structure modes valid for Neon registers. */ 1120 #define VALID_NEON_STRUCT_MODE(MODE) \ 1121 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1122 || (MODE) == CImode || (MODE) == XImode) 1123 1124 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1125 extern int arm_regs_in_sequence[]; 1126 1127 /* The order in which register should be allocated. It is good to use ip 1128 since no saving is required (though calls clobber it) and it never contains 1129 function parameters. It is quite good to use lr since other calls may 1130 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1131 least likely to contain a function parameter; in addition results are 1132 returned in r0. 1133 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1134 then D8-D15. The reason for doing this is to attempt to reduce register 1135 pressure when both single- and double-precision registers are used in a 1136 function. */ 1137 1138 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1139 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1140 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1141 1142 #define REG_ALLOC_ORDER \ 1143 { \ 1144 /* General registers. */ \ 1145 3, 2, 1, 0, 12, 14, 4, 5, \ 1146 6, 7, 8, 9, 10, 11, \ 1147 /* High VFP registers. */ \ 1148 VREG(32), VREG(33), VREG(34), VREG(35), \ 1149 VREG(36), VREG(37), VREG(38), VREG(39), \ 1150 VREG(40), VREG(41), VREG(42), VREG(43), \ 1151 VREG(44), VREG(45), VREG(46), VREG(47), \ 1152 VREG(48), VREG(49), VREG(50), VREG(51), \ 1153 VREG(52), VREG(53), VREG(54), VREG(55), \ 1154 VREG(56), VREG(57), VREG(58), VREG(59), \ 1155 VREG(60), VREG(61), VREG(62), VREG(63), \ 1156 /* VFP argument registers. */ \ 1157 VREG(15), VREG(14), VREG(13), VREG(12), \ 1158 VREG(11), VREG(10), VREG(9), VREG(8), \ 1159 VREG(7), VREG(6), VREG(5), VREG(4), \ 1160 VREG(3), VREG(2), VREG(1), VREG(0), \ 1161 /* VFP call-saved registers. */ \ 1162 VREG(16), VREG(17), VREG(18), VREG(19), \ 1163 VREG(20), VREG(21), VREG(22), VREG(23), \ 1164 VREG(24), VREG(25), VREG(26), VREG(27), \ 1165 VREG(28), VREG(29), VREG(30), VREG(31), \ 1166 /* IWMMX registers. */ \ 1167 WREG(0), WREG(1), WREG(2), WREG(3), \ 1168 WREG(4), WREG(5), WREG(6), WREG(7), \ 1169 WREG(8), WREG(9), WREG(10), WREG(11), \ 1170 WREG(12), WREG(13), WREG(14), WREG(15), \ 1171 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1172 /* Registers not for general use. */ \ 1173 CC_REGNUM, VFPCC_REGNUM, \ 1174 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1175 SP_REGNUM, PC_REGNUM \ 1176 } 1177 1178 /* Use different register alloc ordering for Thumb. */ 1179 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1180 1181 /* Tell IRA to use the order we define rather than messing it up with its 1182 own cost calculations. */ 1183 #define HONOR_REG_ALLOC_ORDER 1 1184 1185 /* Interrupt functions can only use registers that have already been 1186 saved by the prologue, even if they would normally be 1187 call-clobbered. */ 1188 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1189 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1190 df_regs_ever_live_p (DST)) 1191 1192 /* Register and constant classes. */ 1193 1194 /* Register classes. */ 1195 enum reg_class 1196 { 1197 NO_REGS, 1198 LO_REGS, 1199 STACK_REG, 1200 BASE_REGS, 1201 HI_REGS, 1202 CALLER_SAVE_REGS, 1203 GENERAL_REGS, 1204 CORE_REGS, 1205 VFP_D0_D7_REGS, 1206 VFP_LO_REGS, 1207 VFP_HI_REGS, 1208 VFP_REGS, 1209 IWMMXT_REGS, 1210 IWMMXT_GR_REGS, 1211 CC_REG, 1212 VFPCC_REG, 1213 SFP_REG, 1214 AFP_REG, 1215 ALL_REGS, 1216 LIM_REG_CLASSES 1217 }; 1218 1219 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1220 1221 /* Give names of register classes as strings for dump file. */ 1222 #define REG_CLASS_NAMES \ 1223 { \ 1224 "NO_REGS", \ 1225 "LO_REGS", \ 1226 "STACK_REG", \ 1227 "BASE_REGS", \ 1228 "HI_REGS", \ 1229 "CALLER_SAVE_REGS", \ 1230 "GENERAL_REGS", \ 1231 "CORE_REGS", \ 1232 "VFP_D0_D7_REGS", \ 1233 "VFP_LO_REGS", \ 1234 "VFP_HI_REGS", \ 1235 "VFP_REGS", \ 1236 "IWMMXT_REGS", \ 1237 "IWMMXT_GR_REGS", \ 1238 "CC_REG", \ 1239 "VFPCC_REG", \ 1240 "SFP_REG", \ 1241 "AFP_REG", \ 1242 "ALL_REGS" \ 1243 } 1244 1245 /* Define which registers fit in which classes. 1246 This is an initializer for a vector of HARD_REG_SET 1247 of length N_REG_CLASSES. */ 1248 #define REG_CLASS_CONTENTS \ 1249 { \ 1250 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1251 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1252 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1253 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1254 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1255 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1256 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1257 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1258 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1259 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1260 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1261 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1262 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1263 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1264 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1265 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1266 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1267 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1268 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1269 } 1270 1271 /* Any of the VFP register classes. */ 1272 #define IS_VFP_CLASS(X) \ 1273 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1274 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1275 1276 /* The same information, inverted: 1277 Return the class number of the smallest class containing 1278 reg number REGNO. This could be a conditional expression 1279 or could index an array. */ 1280 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1281 1282 /* In VFPv1, VFP registers could only be accessed in the mode they 1283 were set, so subregs would be invalid there. However, we don't 1284 support VFPv1 at the moment, and the restriction was lifted in 1285 VFPv2. 1286 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in 1287 VFP registers in little-endian order. We can't describe that accurately to 1288 GCC, so avoid taking subregs of such values. 1289 The only exception is going from a 128-bit to a 64-bit type. In that case 1290 the data layout happens to be consistent for big-endian, so we explicitly allow 1291 that case. */ 1292 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1293 (TARGET_VFP && TARGET_BIG_END \ 1294 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ 1295 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ 1296 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ 1297 && reg_classes_intersect_p (VFP_REGS, (CLASS))) 1298 1299 /* The class value for index registers, and the one for base regs. */ 1300 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1301 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1302 1303 /* For the Thumb the high registers cannot be used as base registers 1304 when addressing quantities in QI or HI mode; if we don't know the 1305 mode, then we must be conservative. */ 1306 #define MODE_BASE_REG_CLASS(MODE) \ 1307 (TARGET_32BIT ? CORE_REGS \ 1308 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1309 : LO_REGS) 1310 1311 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1312 instead of BASE_REGS. */ 1313 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1314 1315 /* When this hook returns true for MODE, the compiler allows 1316 registers explicitly used in the rtl to be used as spill registers 1317 but prevents the compiler from extending the lifetime of these 1318 registers. */ 1319 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1320 arm_small_register_classes_for_mode_p 1321 1322 /* Must leave BASE_REGS reloads alone */ 1323 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1324 (lra_in_progress ? NO_REGS \ 1325 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1326 ? ((true_regnum (X) == -1 ? LO_REGS \ 1327 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1328 : NO_REGS)) \ 1329 : NO_REGS)) 1330 1331 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1332 (lra_in_progress ? NO_REGS \ 1333 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1334 ? ((true_regnum (X) == -1 ? LO_REGS \ 1335 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1336 : NO_REGS)) \ 1337 : NO_REGS) 1338 1339 /* Return the register class of a scratch register needed to copy IN into 1340 or out of a register in CLASS in MODE. If it can be done directly, 1341 NO_REGS is returned. */ 1342 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1343 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1344 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1345 && IS_VFP_CLASS (CLASS)) \ 1346 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1347 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1348 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1349 : TARGET_32BIT \ 1350 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1351 ? GENERAL_REGS : NO_REGS) \ 1352 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1353 1354 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1355 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1356 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1357 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1358 && IS_VFP_CLASS (CLASS)) \ 1359 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1360 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1361 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1362 (TARGET_32BIT ? \ 1363 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1364 && CONSTANT_P (X)) \ 1365 ? GENERAL_REGS : \ 1366 (((MODE) == HImode && ! arm_arch4 \ 1367 && (MEM_P (X) \ 1368 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1369 && true_regnum (X) == -1))) \ 1370 ? GENERAL_REGS : NO_REGS) \ 1371 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1372 1373 /* Try a machine-dependent way of reloading an illegitimate address 1374 operand. If we find one, push the reload and jump to WIN. This 1375 macro is used in only one place: `find_reloads_address' in reload.c. 1376 1377 For the ARM, we wish to handle large displacements off a base 1378 register by splitting the addend across a MOV and the mem insn. 1379 This can cut the number of reloads needed. */ 1380 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1381 do \ 1382 { \ 1383 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ 1384 goto WIN; \ 1385 } \ 1386 while (0) 1387 1388 /* XXX If an HImode FP+large_offset address is converted to an HImode 1389 SP+large_offset address, then reload won't know how to fix it. It sees 1390 only that SP isn't valid for HImode, and so reloads the SP into an index 1391 register, but the resulting address is still invalid because the offset 1392 is too big. We fix it here instead by reloading the entire address. */ 1393 /* We could probably achieve better results by defining PROMOTE_MODE to help 1394 cope with the variances between the Thumb's signed and unsigned byte and 1395 halfword load instructions. */ 1396 /* ??? This should be safe for thumb2, but we may be able to do better. */ 1397 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1398 do { \ 1399 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1400 if (new_x) \ 1401 { \ 1402 X = new_x; \ 1403 goto WIN; \ 1404 } \ 1405 } while (0) 1406 1407 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1408 if (TARGET_ARM) \ 1409 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1410 else \ 1411 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1412 1413 /* Return the maximum number of consecutive registers 1414 needed to represent mode MODE in a register of class CLASS. 1415 ARM regs are UNITS_PER_WORD bits. 1416 FIXME: Is this true for iWMMX? */ 1417 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1418 (ARM_NUM_REGS (MODE)) 1419 1420 /* If defined, gives a class of registers that cannot be used as the 1421 operand of a SUBREG that changes the mode of the object illegally. */ 1422 1423 /* Stack layout; function entry, exit and calling. */ 1424 1425 /* Define this if pushing a word on the stack 1426 makes the stack pointer a smaller address. */ 1427 #define STACK_GROWS_DOWNWARD 1 1428 1429 /* Define this to nonzero if the nominal address of the stack frame 1430 is at the high-address end of the local variables; 1431 that is, each additional local variable allocated 1432 goes at a more negative offset in the frame. */ 1433 #define FRAME_GROWS_DOWNWARD 1 1434 1435 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1436 When present, it is one word in size, and sits at the top of the frame, 1437 between the soft frame pointer and either r7 or r11. 1438 1439 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1440 and only then if some outgoing arguments are passed on the stack. It would 1441 be tempting to also check whether the stack arguments are passed by indirect 1442 calls, but there seems to be no reason in principle why a post-reload pass 1443 couldn't convert a direct call into an indirect one. */ 1444 #define CALLER_INTERWORKING_SLOT_SIZE \ 1445 (TARGET_CALLER_INTERWORKING \ 1446 && crtl->outgoing_args_size != 0 \ 1447 ? UNITS_PER_WORD : 0) 1448 1449 /* Offset within stack frame to start allocating local variables at. 1450 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1451 first local allocated. Otherwise, it is the offset to the BEGINNING 1452 of the first local allocated. */ 1453 #define STARTING_FRAME_OFFSET 0 1454 1455 /* If we generate an insn to push BYTES bytes, 1456 this says how many the stack pointer really advances by. */ 1457 /* The push insns do not do this rounding implicitly. 1458 So don't define this. */ 1459 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1460 1461 /* Define this if the maximum size of all the outgoing args is to be 1462 accumulated and pushed during the prologue. The amount can be 1463 found in the variable crtl->outgoing_args_size. */ 1464 #define ACCUMULATE_OUTGOING_ARGS 1 1465 1466 /* Offset of first parameter from the argument pointer register value. */ 1467 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1468 1469 /* Amount of memory needed for an untyped call to save all possible return 1470 registers. */ 1471 #define APPLY_RESULT_SIZE arm_apply_result_size() 1472 1473 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1474 values must be in memory. On the ARM, they need only do so if larger 1475 than a word, or if they contain elements offset from zero in the struct. */ 1476 #define DEFAULT_PCC_STRUCT_RETURN 0 1477 1478 /* These bits describe the different types of function supported 1479 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1480 normal function and an interworked function, for example. Knowing the 1481 type of a function is important for determining its prologue and 1482 epilogue sequences. 1483 Note value 7 is currently unassigned. Also note that the interrupt 1484 function types all have bit 2 set, so that they can be tested for easily. 1485 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1486 machine_function structure is initialized (to zero) func_type will 1487 default to unknown. This will force the first use of arm_current_func_type 1488 to call arm_compute_func_type. */ 1489 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1490 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1491 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1492 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1493 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1494 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1495 1496 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1497 1498 /* In addition functions can have several type modifiers, 1499 outlined by these bit masks: */ 1500 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1501 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1502 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1503 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1504 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1505 1506 /* Some macros to test these flags. */ 1507 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1508 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1509 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1510 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1511 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1512 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1513 1514 1515 /* Structure used to hold the function stack frame layout. Offsets are 1516 relative to the stack pointer on function entry. Positive offsets are 1517 in the direction of stack growth. 1518 Only soft_frame is used in thumb mode. */ 1519 1520 typedef struct GTY(()) arm_stack_offsets 1521 { 1522 int saved_args; /* ARG_POINTER_REGNUM. */ 1523 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1524 int saved_regs; 1525 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1526 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1527 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1528 unsigned int saved_regs_mask; 1529 } 1530 arm_stack_offsets; 1531 1532 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1533 /* A C structure for machine-specific, per-function data. 1534 This is added to the cfun structure. */ 1535 typedef struct GTY(()) machine_function 1536 { 1537 /* Additional stack adjustment in __builtin_eh_throw. */ 1538 rtx eh_epilogue_sp_ofs; 1539 /* Records if LR has to be saved for far jumps. */ 1540 int far_jump_used; 1541 /* Records if ARG_POINTER was ever live. */ 1542 int arg_pointer_live; 1543 /* Records if the save of LR has been eliminated. */ 1544 int lr_save_eliminated; 1545 /* The size of the stack frame. Only valid after reload. */ 1546 arm_stack_offsets stack_offsets; 1547 /* Records the type of the current function. */ 1548 unsigned long func_type; 1549 /* Record if the function has a variable argument list. */ 1550 int uses_anonymous_args; 1551 /* Records if sibcalls are blocked because an argument 1552 register is needed to preserve stack alignment. */ 1553 int sibcall_blocked; 1554 /* The PIC register for this function. This might be a pseudo. */ 1555 rtx pic_reg; 1556 /* Labels for per-function Thumb call-via stubs. One per potential calling 1557 register. We can never call via LR or PC. We can call via SP if a 1558 trampoline happens to be on the top of the stack. */ 1559 rtx call_via[14]; 1560 /* Set to 1 when a return insn is output, this means that the epilogue 1561 is not needed. */ 1562 int return_used_this_function; 1563 /* When outputting Thumb-1 code, record the last insn that provides 1564 information about condition codes, and the comparison operands. */ 1565 rtx thumb1_cc_insn; 1566 rtx thumb1_cc_op0; 1567 rtx thumb1_cc_op1; 1568 /* Also record the CC mode that is supported. */ 1569 machine_mode thumb1_cc_mode; 1570 /* Set to 1 after arm_reorg has started. */ 1571 int after_arm_reorg; 1572 } 1573 machine_function; 1574 #endif 1575 1576 /* As in the machine_function, a global set of call-via labels, for code 1577 that is in text_section. */ 1578 extern GTY(()) rtx thumb_call_via_label[14]; 1579 1580 /* The number of potential ways of assigning to a co-processor. */ 1581 #define ARM_NUM_COPROC_SLOTS 1 1582 1583 /* Enumeration of procedure calling standard variants. We don't really 1584 support all of these yet. */ 1585 enum arm_pcs 1586 { 1587 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1588 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1589 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1590 /* This must be the last AAPCS variant. */ 1591 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1592 ARM_PCS_ATPCS, /* ATPCS. */ 1593 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1594 ARM_PCS_UNKNOWN 1595 }; 1596 1597 /* Default procedure calling standard of current compilation unit. */ 1598 extern enum arm_pcs arm_pcs_default; 1599 1600 #if !defined (USED_FOR_TARGET) 1601 /* A C type for declaring a variable that is used as the first argument of 1602 `FUNCTION_ARG' and other related values. */ 1603 typedef struct 1604 { 1605 /* This is the number of registers of arguments scanned so far. */ 1606 int nregs; 1607 /* This is the number of iWMMXt register arguments scanned so far. */ 1608 int iwmmxt_nregs; 1609 int named_count; 1610 int nargs; 1611 /* Which procedure call variant to use for this call. */ 1612 enum arm_pcs pcs_variant; 1613 1614 /* AAPCS related state tracking. */ 1615 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1616 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1617 this argument, or -1 if using core 1618 registers. */ 1619 int aapcs_ncrn; 1620 int aapcs_next_ncrn; 1621 rtx aapcs_reg; /* Register assigned to this argument. */ 1622 int aapcs_partial; /* How many bytes are passed in regs (if 1623 split between core regs and stack. 1624 Zero otherwise. */ 1625 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1626 int can_split; /* Argument can be split between core regs 1627 and the stack. */ 1628 /* Private data for tracking VFP register allocation */ 1629 unsigned aapcs_vfp_regs_free; 1630 unsigned aapcs_vfp_reg_alloc; 1631 int aapcs_vfp_rcount; 1632 MACHMODE aapcs_vfp_rmode; 1633 } CUMULATIVE_ARGS; 1634 #endif 1635 1636 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1637 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1638 1639 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1640 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1641 1642 /* For AAPCS, padding should never be below the argument. For other ABIs, 1643 * mimic the default. */ 1644 #define PAD_VARARGS_DOWN \ 1645 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1646 1647 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1648 for a call to a function whose data type is FNTYPE. 1649 For a library call, FNTYPE is 0. 1650 On the ARM, the offset starts at 0. */ 1651 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1652 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1653 1654 /* 1 if N is a possible register number for function argument passing. 1655 On the ARM, r0-r3 are used to pass args. */ 1656 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1657 (IN_RANGE ((REGNO), 0, 3) \ 1658 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1659 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1660 || (TARGET_IWMMXT_ABI \ 1661 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1662 1663 1664 /* If your target environment doesn't prefix user functions with an 1665 underscore, you may wish to re-define this to prevent any conflicts. */ 1666 #ifndef ARM_MCOUNT_NAME 1667 #define ARM_MCOUNT_NAME "*mcount" 1668 #endif 1669 1670 /* Call the function profiler with a given profile label. The Acorn 1671 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1672 On the ARM the full profile code will look like: 1673 .data 1674 LP1 1675 .word 0 1676 .text 1677 mov ip, lr 1678 bl mcount 1679 .word LP1 1680 1681 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1682 will output the .text section. 1683 1684 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1685 ``prof'' doesn't seem to mind about this! 1686 1687 Note - this version of the code is designed to work in both ARM and 1688 Thumb modes. */ 1689 #ifndef ARM_FUNCTION_PROFILER 1690 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1691 { \ 1692 char temp[20]; \ 1693 rtx sym; \ 1694 \ 1695 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1696 IP_REGNUM, LR_REGNUM); \ 1697 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1698 fputc ('\n', STREAM); \ 1699 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1700 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1701 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1702 } 1703 #endif 1704 1705 #ifdef THUMB_FUNCTION_PROFILER 1706 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1707 if (TARGET_ARM) \ 1708 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1709 else \ 1710 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1711 #else 1712 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1713 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1714 #endif 1715 1716 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1717 the stack pointer does not matter. The value is tested only in 1718 functions that have frame pointers. 1719 No definition is equivalent to always zero. 1720 1721 On the ARM, the function epilogue recovers the stack pointer from the 1722 frame. */ 1723 #define EXIT_IGNORE_STACK 1 1724 1725 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1726 1727 /* Determine if the epilogue should be output as RTL. 1728 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1729 #define USE_RETURN_INSN(ISCOND) \ 1730 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1731 1732 /* Definitions for register eliminations. 1733 1734 This is an array of structures. Each structure initializes one pair 1735 of eliminable registers. The "from" register number is given first, 1736 followed by "to". Eliminations of the same "from" register are listed 1737 in order of preference. 1738 1739 We have two registers that can be eliminated on the ARM. First, the 1740 arg pointer register can often be eliminated in favor of the stack 1741 pointer register. Secondly, the pseudo frame pointer register can always 1742 be eliminated; it is replaced with either the stack or the real frame 1743 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1744 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1745 1746 #define ELIMINABLE_REGS \ 1747 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1748 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1749 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1750 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1751 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1752 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1753 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1754 1755 /* Define the offset between two registers, one to be eliminated, and the 1756 other its replacement, at the start of a routine. */ 1757 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1758 if (TARGET_ARM) \ 1759 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1760 else \ 1761 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1762 1763 /* Special case handling of the location of arguments passed on the stack. */ 1764 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1765 1766 /* Initialize data used by insn expanders. This is called from insn_emit, 1767 once for every function before code is generated. */ 1768 #define INIT_EXPANDERS arm_init_expanders () 1769 1770 /* Length in units of the trampoline for entering a nested function. */ 1771 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1772 1773 /* Alignment required for a trampoline in bits. */ 1774 #define TRAMPOLINE_ALIGNMENT 32 1775 1776 /* Addressing modes, and classification of registers for them. */ 1777 #define HAVE_POST_INCREMENT 1 1778 #define HAVE_PRE_INCREMENT TARGET_32BIT 1779 #define HAVE_POST_DECREMENT TARGET_32BIT 1780 #define HAVE_PRE_DECREMENT TARGET_32BIT 1781 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1782 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1783 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1784 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1785 1786 enum arm_auto_incmodes 1787 { 1788 ARM_POST_INC, 1789 ARM_PRE_INC, 1790 ARM_POST_DEC, 1791 ARM_PRE_DEC 1792 }; 1793 1794 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1795 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1796 #define USE_LOAD_POST_INCREMENT(mode) \ 1797 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1798 #define USE_LOAD_PRE_INCREMENT(mode) \ 1799 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1800 #define USE_LOAD_POST_DECREMENT(mode) \ 1801 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1802 #define USE_LOAD_PRE_DECREMENT(mode) \ 1803 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1804 1805 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1806 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1807 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1808 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1809 1810 /* Macros to check register numbers against specific register classes. */ 1811 1812 /* These assume that REGNO is a hard or pseudo reg number. 1813 They give nonzero only if REGNO is a hard reg of the suitable class 1814 or a pseudo reg currently allocated to a suitable hard reg. 1815 Since they use reg_renumber, they are safe only once reg_renumber 1816 has been allocated, which happens in reginfo.c during register 1817 allocation. */ 1818 #define TEST_REGNO(R, TEST, VALUE) \ 1819 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1820 1821 /* Don't allow the pc to be used. */ 1822 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1823 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1824 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1825 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1826 1827 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1828 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1829 || (GET_MODE_SIZE (MODE) >= 4 \ 1830 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1831 1832 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1833 (TARGET_THUMB1 \ 1834 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1835 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1836 1837 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1838 For Thumb, we can not use SP + reg, so reject SP. */ 1839 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1840 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1841 1842 /* For ARM code, we don't care about the mode, but for Thumb, the index 1843 must be suitable for use in a QImode load. */ 1844 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1845 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1846 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1847 1848 /* Maximum number of registers that can appear in a valid memory address. 1849 Shifts in addresses can't be by a register. */ 1850 #define MAX_REGS_PER_ADDRESS 2 1851 1852 /* Recognize any constant value that is a valid address. */ 1853 /* XXX We can address any constant, eventually... */ 1854 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1855 #define CONSTANT_ADDRESS_P(X) \ 1856 (GET_CODE (X) == SYMBOL_REF \ 1857 && (CONSTANT_POOL_ADDRESS_P (X) \ 1858 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1859 1860 /* True if SYMBOL + OFFSET constants must refer to something within 1861 SYMBOL's section. */ 1862 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1863 1864 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1865 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1866 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1867 #endif 1868 1869 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1870 #define SUBTARGET_NAME_ENCODING_LENGTHS 1871 #endif 1872 1873 /* This is a C fragment for the inside of a switch statement. 1874 Each case label should return the number of characters to 1875 be stripped from the start of a function's name, if that 1876 name starts with the indicated character. */ 1877 #define ARM_NAME_ENCODING_LENGTHS \ 1878 case '*': return 1; \ 1879 SUBTARGET_NAME_ENCODING_LENGTHS 1880 1881 /* This is how to output a reference to a user-level label named NAME. 1882 `assemble_name' uses this. */ 1883 #undef ASM_OUTPUT_LABELREF 1884 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1885 arm_asm_output_labelref (FILE, NAME) 1886 1887 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1888 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1889 if (TARGET_THUMB2) \ 1890 thumb2_asm_output_opcode (STREAM); 1891 1892 /* The EABI specifies that constructors should go in .init_array. 1893 Other targets use .ctors for compatibility. */ 1894 #ifndef ARM_EABI_CTORS_SECTION_OP 1895 #define ARM_EABI_CTORS_SECTION_OP \ 1896 "\t.section\t.init_array,\"aw\",%init_array" 1897 #endif 1898 #ifndef ARM_EABI_DTORS_SECTION_OP 1899 #define ARM_EABI_DTORS_SECTION_OP \ 1900 "\t.section\t.fini_array,\"aw\",%fini_array" 1901 #endif 1902 #define ARM_CTORS_SECTION_OP \ 1903 "\t.section\t.ctors,\"aw\",%progbits" 1904 #define ARM_DTORS_SECTION_OP \ 1905 "\t.section\t.dtors,\"aw\",%progbits" 1906 1907 /* Define CTORS_SECTION_ASM_OP. */ 1908 #undef CTORS_SECTION_ASM_OP 1909 #undef DTORS_SECTION_ASM_OP 1910 #ifndef IN_LIBGCC2 1911 # define CTORS_SECTION_ASM_OP \ 1912 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1913 # define DTORS_SECTION_ASM_OP \ 1914 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1915 #else /* !defined (IN_LIBGCC2) */ 1916 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1917 so we cannot use the definition above. */ 1918 # ifdef __ARM_EABI__ 1919 /* The .ctors section is not part of the EABI, so we do not define 1920 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1921 from trying to use it. We do define it when doing normal 1922 compilation, as .init_array can be used instead of .ctors. */ 1923 /* There is no need to emit begin or end markers when using 1924 init_array; the dynamic linker will compute the size of the 1925 array itself based on special symbols created by the static 1926 linker. However, we do need to arrange to set up 1927 exception-handling here. */ 1928 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1929 # define CTOR_LIST_END /* empty */ 1930 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1931 # define DTOR_LIST_END /* empty */ 1932 # else /* !defined (__ARM_EABI__) */ 1933 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1934 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1935 # endif /* !defined (__ARM_EABI__) */ 1936 #endif /* !defined (IN_LIBCC2) */ 1937 1938 /* True if the operating system can merge entities with vague linkage 1939 (e.g., symbols in COMDAT group) during dynamic linking. */ 1940 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1941 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1942 #endif 1943 1944 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1945 1946 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1947 and check its validity for a certain class. 1948 We have two alternate definitions for each of them. 1949 The usual definition accepts all pseudo regs; the other rejects 1950 them unless they have been allocated suitable hard regs. 1951 The symbol REG_OK_STRICT causes the latter definition to be used. 1952 Thumb-2 has the same restrictions as arm. */ 1953 #ifndef REG_OK_STRICT 1954 1955 #define ARM_REG_OK_FOR_BASE_P(X) \ 1956 (REGNO (X) <= LAST_ARM_REGNUM \ 1957 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1958 || REGNO (X) == FRAME_POINTER_REGNUM \ 1959 || REGNO (X) == ARG_POINTER_REGNUM) 1960 1961 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1962 ((REGNO (X) <= LAST_ARM_REGNUM \ 1963 && REGNO (X) != STACK_POINTER_REGNUM) \ 1964 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1965 || REGNO (X) == FRAME_POINTER_REGNUM \ 1966 || REGNO (X) == ARG_POINTER_REGNUM) 1967 1968 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1969 (REGNO (X) <= LAST_LO_REGNUM \ 1970 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1971 || (GET_MODE_SIZE (MODE) >= 4 \ 1972 && (REGNO (X) == STACK_POINTER_REGNUM \ 1973 || (X) == hard_frame_pointer_rtx \ 1974 || (X) == arg_pointer_rtx))) 1975 1976 #define REG_STRICT_P 0 1977 1978 #else /* REG_OK_STRICT */ 1979 1980 #define ARM_REG_OK_FOR_BASE_P(X) \ 1981 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1982 1983 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1984 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1985 1986 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1987 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1988 1989 #define REG_STRICT_P 1 1990 1991 #endif /* REG_OK_STRICT */ 1992 1993 /* Now define some helpers in terms of the above. */ 1994 1995 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1996 (TARGET_THUMB1 \ 1997 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1998 : ARM_REG_OK_FOR_BASE_P (X)) 1999 2000 /* For 16-bit Thumb, a valid index register is anything that can be used in 2001 a byte load instruction. */ 2002 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2003 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2004 2005 /* Nonzero if X is a hard reg that can be used as an index 2006 or if it is a pseudo reg. On the Thumb, the stack pointer 2007 is not suitable. */ 2008 #define REG_OK_FOR_INDEX_P(X) \ 2009 (TARGET_THUMB1 \ 2010 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2011 : ARM_REG_OK_FOR_INDEX_P (X)) 2012 2013 /* Nonzero if X can be the base register in a reg+reg addressing mode. 2014 For Thumb, we can not use SP + reg, so reject SP. */ 2015 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2016 REG_OK_FOR_INDEX_P (X) 2017 2018 #define ARM_BASE_REGISTER_RTX_P(X) \ 2019 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 2020 2021 #define ARM_INDEX_REGISTER_RTX_P(X) \ 2022 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 2023 2024 /* Specify the machine mode that this machine uses 2025 for the index in the tablejump instruction. */ 2026 #define CASE_VECTOR_MODE Pmode 2027 2028 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 2029 || (TARGET_THUMB1 \ 2030 && (optimize_size || flag_pic))) 2031 2032 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2033 (TARGET_THUMB1 \ 2034 ? (min >= 0 && max < 512 \ 2035 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2036 : min >= -256 && max < 256 \ 2037 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2038 : min >= 0 && max < 8192 \ 2039 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2040 : min >= -4096 && max < 4096 \ 2041 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2042 : SImode) \ 2043 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 2044 : (max >= 0x200) ? HImode \ 2045 : QImode)) 2046 2047 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2048 unsigned is probably best, but may break some code. */ 2049 #ifndef DEFAULT_SIGNED_CHAR 2050 #define DEFAULT_SIGNED_CHAR 0 2051 #endif 2052 2053 /* Max number of bytes we can move from memory to memory 2054 in one reasonably fast instruction. */ 2055 #define MOVE_MAX 4 2056 2057 #undef MOVE_RATIO 2058 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2059 2060 /* Define if operations between registers always perform the operation 2061 on the full register even if a narrower mode is specified. */ 2062 #define WORD_REGISTER_OPERATIONS 2063 2064 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2065 will either zero-extend or sign-extend. The value of this macro should 2066 be the code that says which one of the two operations is implicitly 2067 done, UNKNOWN if none. */ 2068 #define LOAD_EXTEND_OP(MODE) \ 2069 (TARGET_THUMB ? ZERO_EXTEND : \ 2070 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2071 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2072 2073 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2074 #define SLOW_BYTE_ACCESS 0 2075 2076 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2077 2078 /* Immediate shift counts are truncated by the output routines (or was it 2079 the assembler?). Shift counts in a register are truncated by ARM. Note 2080 that the native compiler puts too large (> 32) immediate shift counts 2081 into a register and shifts by the register, letting the ARM decide what 2082 to do instead of doing that itself. */ 2083 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2084 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2085 On the arm, Y in a register is used modulo 256 for the shift. Only for 2086 rotates is modulo 32 used. */ 2087 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2088 2089 /* All integers have the same format so truncation is easy. */ 2090 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2091 2092 /* Calling from registers is a massive pain. */ 2093 #define NO_FUNCTION_CSE 1 2094 2095 /* The machine modes of pointers and functions */ 2096 #define Pmode SImode 2097 #define FUNCTION_MODE Pmode 2098 2099 #define ARM_FRAME_RTX(X) \ 2100 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2101 || (X) == arg_pointer_rtx) 2102 2103 /* Try to generate sequences that don't involve branches, we can then use 2104 conditional instructions. */ 2105 #define BRANCH_COST(speed_p, predictable_p) \ 2106 (current_tune->branch_cost (speed_p, predictable_p)) 2107 2108 /* False if short circuit operation is preferred. */ 2109 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2110 ((optimize_size) \ 2111 ? (TARGET_THUMB ? false : true) \ 2112 : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) 2113 2114 2115 /* Position Independent Code. */ 2116 /* We decide which register to use based on the compilation options and 2117 the assembler in use; this is more general than the APCS restriction of 2118 using sb (r9) all the time. */ 2119 extern unsigned arm_pic_register; 2120 2121 /* The register number of the register used to address a table of static 2122 data addresses in memory. */ 2123 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2124 2125 /* We can't directly access anything that contains a symbol, 2126 nor can we indirect via the constant pool. One exception is 2127 UNSPEC_TLS, which is always PIC. */ 2128 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2129 (!(symbol_mentioned_p (X) \ 2130 || label_mentioned_p (X) \ 2131 || (GET_CODE (X) == SYMBOL_REF \ 2132 && CONSTANT_POOL_ADDRESS_P (X) \ 2133 && (symbol_mentioned_p (get_pool_constant (X)) \ 2134 || label_mentioned_p (get_pool_constant (X))))) \ 2135 || tls_mentioned_p (X)) 2136 2137 /* We need to know when we are making a constant pool; this determines 2138 whether data needs to be in the GOT or can be referenced via a GOT 2139 offset. */ 2140 extern int making_const_table; 2141 2142 /* Handle pragmas for compatibility with Intel's compilers. */ 2143 /* Also abuse this to register additional C specific EABI attributes. */ 2144 #define REGISTER_TARGET_PRAGMAS() do { \ 2145 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2146 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2147 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2148 arm_lang_object_attributes_init(); \ 2149 } while (0) 2150 2151 /* Condition code information. */ 2152 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2153 return the mode to be used for the comparison. */ 2154 2155 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2156 2157 #define REVERSIBLE_CC_MODE(MODE) 1 2158 2159 #define REVERSE_CONDITION(CODE,MODE) \ 2160 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2161 ? reverse_condition_maybe_unordered (code) \ 2162 : reverse_condition (code)) 2163 2164 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2165 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2166 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2167 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2168 2169 #define CC_STATUS_INIT \ 2170 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2171 2172 #undef ASM_APP_ON 2173 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2174 "\t.syntax divided\n") 2175 2176 #undef ASM_APP_OFF 2177 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax divided\n" : \ 2178 "\t.thumb\n\t.syntax unified\n") 2179 2180 /* Output a push or a pop instruction (only used when profiling). 2181 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2182 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2183 that r7 isn't used by the function profiler, so we can use it as a 2184 scratch reg. WARNING: This isn't safe in the general case! It may be 2185 sensitive to future changes in final.c:profile_function. */ 2186 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2187 do \ 2188 { \ 2189 if (TARGET_ARM) \ 2190 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2191 STACK_POINTER_REGNUM, REGNO); \ 2192 else if (TARGET_THUMB1 \ 2193 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2194 { \ 2195 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2196 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2197 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2198 } \ 2199 else \ 2200 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2201 } while (0) 2202 2203 2204 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2205 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2206 do \ 2207 { \ 2208 if (TARGET_ARM) \ 2209 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2210 STACK_POINTER_REGNUM, REGNO); \ 2211 else if (TARGET_THUMB1 \ 2212 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2213 { \ 2214 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2215 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2216 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2217 } \ 2218 else \ 2219 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2220 } while (0) 2221 2222 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2223 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2224 2225 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2226 default alignment from elfos.h. */ 2227 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2228 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2229 2230 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2231 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2232 ? 1 : 0) 2233 2234 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2235 do \ 2236 { \ 2237 if (TARGET_THUMB) \ 2238 { \ 2239 if (is_called_in_ARM_mode (DECL) \ 2240 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2241 && cfun->is_thunk)) \ 2242 fprintf (STREAM, "\t.code 32\n") ; \ 2243 else if (TARGET_THUMB1) \ 2244 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2245 else \ 2246 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2247 } \ 2248 if (TARGET_POKE_FUNCTION_NAME) \ 2249 arm_poke_function_name (STREAM, (const char *) NAME); \ 2250 } \ 2251 while (0) 2252 2253 /* For aliases of functions we use .thumb_set instead. */ 2254 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2255 do \ 2256 { \ 2257 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2258 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2259 \ 2260 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2261 { \ 2262 fprintf (FILE, "\t.thumb_set "); \ 2263 assemble_name (FILE, LABEL1); \ 2264 fprintf (FILE, ","); \ 2265 assemble_name (FILE, LABEL2); \ 2266 fprintf (FILE, "\n"); \ 2267 } \ 2268 else \ 2269 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2270 } \ 2271 while (0) 2272 2273 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2274 /* To support -falign-* switches we need to use .p2align so 2275 that alignment directives in code sections will be padded 2276 with no-op instructions, rather than zeroes. */ 2277 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2278 if ((LOG) != 0) \ 2279 { \ 2280 if ((MAX_SKIP) == 0) \ 2281 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2282 else \ 2283 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2284 (int) (LOG), (int) (MAX_SKIP)); \ 2285 } 2286 #endif 2287 2288 /* Add two bytes to the length of conditionally executed Thumb-2 2289 instructions for the IT instruction. */ 2290 #define ADJUST_INSN_LENGTH(insn, length) \ 2291 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2292 length += 2; 2293 2294 /* Only perform branch elimination (by making instructions conditional) if 2295 we're optimizing. For Thumb-2 check if any IT instructions need 2296 outputting. */ 2297 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2298 if (TARGET_ARM && optimize) \ 2299 arm_final_prescan_insn (INSN); \ 2300 else if (TARGET_THUMB2) \ 2301 thumb2_final_prescan_insn (INSN); \ 2302 else if (TARGET_THUMB1) \ 2303 thumb1_final_prescan_insn (INSN) 2304 2305 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2306 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2307 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2308 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2309 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2310 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2311 : 0)))) 2312 2313 /* A C expression whose value is RTL representing the value of the return 2314 address for the frame COUNT steps up from the current frame. */ 2315 2316 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2317 arm_return_addr (COUNT, FRAME) 2318 2319 /* Mask of the bits in the PC that contain the real return address 2320 when running in 26-bit mode. */ 2321 #define RETURN_ADDR_MASK26 (0x03fffffc) 2322 2323 /* Pick up the return address upon entry to a procedure. Used for 2324 dwarf2 unwind information. This also enables the table driven 2325 mechanism. */ 2326 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2327 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2328 2329 /* Used to mask out junk bits from the return address, such as 2330 processor state, interrupt status, condition codes and the like. */ 2331 #define MASK_RETURN_ADDR \ 2332 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2333 in 26 bit mode, the condition codes must be masked out of the \ 2334 return address. This does not apply to ARM6 and later processors \ 2335 when running in 32 bit mode. */ \ 2336 ((arm_arch4 || TARGET_THUMB) \ 2337 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2338 : arm_gen_return_addr_mask ()) 2339 2340 2341 /* Do not emit .note.GNU-stack by default. */ 2342 #ifndef NEED_INDICATE_EXEC_STACK 2343 #define NEED_INDICATE_EXEC_STACK 0 2344 #endif 2345 2346 #define TARGET_ARM_ARCH \ 2347 (arm_base_arch) \ 2348 2349 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) 2350 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) 2351 2352 /* The highest Thumb instruction set version supported by the chip. */ 2353 #define TARGET_ARM_ARCH_ISA_THUMB \ 2354 (arm_arch_thumb2 ? 2 \ 2355 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0)) 2356 2357 /* Expands to an upper-case char of the target's architectural 2358 profile. */ 2359 #define TARGET_ARM_ARCH_PROFILE \ 2360 (!arm_arch_notm \ 2361 ? 'M' \ 2362 : (arm_arch7 \ 2363 ? (strlen (arm_arch_name) >=3 \ 2364 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ 2365 : 0) \ 2366 : 0)) 2367 2368 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2369 Bit 0 for bytes, up to bit 3 for double-words. */ 2370 #define TARGET_ARM_FEATURE_LDREX \ 2371 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2372 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2373 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2374 2375 /* Set as a bit mask indicating the available widths of hardware floating 2376 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2377 32-bit support, bit 3 indicates 64-bit support. */ 2378 #define TARGET_ARM_FP \ 2379 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2380 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2381 : 0) 2382 2383 2384 /* Set as a bit mask indicating the available widths of floating point 2385 types for hardware NEON floating point. This is the same as 2386 TARGET_ARM_FP without the 64-bit bit set. */ 2387 #define TARGET_NEON_FP \ 2388 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2389 : 0) 2390 2391 /* The maximum number of parallel loads or stores we support in an ldm/stm 2392 instruction. */ 2393 #define MAX_LDM_STM_OPS 4 2394 2395 #define BIG_LITTLE_SPEC \ 2396 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" 2397 2398 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2399 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 2400 { "rewrite_mcpu", arm_rewrite_mcpu }, 2401 2402 #define ASM_CPU_SPEC \ 2403 " %{mcpu=generic-*:-march=%*;" \ 2404 " :%{march=*:-march=%*}}" \ 2405 BIG_LITTLE_SPEC 2406 2407 /* -mcpu=native handling only makes sense with compiler running on 2408 an ARM chip. */ 2409 #if defined(__arm__) && defined(__linux__) 2410 extern const char *host_detect_local_cpu (int argc, const char **argv); 2411 # define EXTRA_SPEC_FUNCTIONS \ 2412 { "local_cpu_detect", host_detect_local_cpu }, \ 2413 BIG_LITTLE_CPU_SPEC_FUNCTIONS 2414 2415 # define MCPU_MTUNE_NATIVE_SPECS \ 2416 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2417 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2418 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2419 #else 2420 # define MCPU_MTUNE_NATIVE_SPECS "" 2421 # define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS 2422 #endif 2423 2424 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS 2425 #define TARGET_SUPPORTS_WIDE_INT 1 2426 #endif /* ! GCC_ARM_H */ 2427