1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2019 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha@arm.com) 6 Minor hacks by Nick Clifton (nickc@cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 /* Target CPU versions for D. */ 51 #define TARGET_D_CPU_VERSIONS arm_d_target_versions 52 53 #include "config/arm/arm-opts.h" 54 55 /* The processor for which instructions should be scheduled. */ 56 extern enum processor_type arm_tune; 57 58 typedef enum arm_cond_code 59 { 60 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 61 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 62 } 63 arm_cc; 64 65 extern arm_cc arm_current_cc; 66 67 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 68 69 /* The maximum number of instructions that is beneficial to 70 conditionally execute. */ 71 #undef MAX_CONDITIONAL_EXECUTE 72 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 73 74 extern int arm_target_label; 75 extern int arm_ccfsm_state; 76 extern GTY(()) rtx arm_target_insn; 77 /* Callback to output language specific object attributes. */ 78 extern void (*arm_lang_output_object_attributes_hook)(void); 79 80 /* This type is the user-visible __fp16. We need it in a few places in 81 the backend. Defined in arm-builtins.c. */ 82 extern tree arm_fp16_type_node; 83 84 85 #undef CPP_SPEC 86 #define CPP_SPEC "%(subtarget_cpp_spec) \ 87 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 88 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 89 %{mbig-endian:%{mlittle-endian: \ 90 %e-mbig-endian and -mlittle-endian may not be used together}}" 91 92 #ifndef CC1_SPEC 93 #define CC1_SPEC "" 94 #endif 95 96 /* This macro defines names of additional specifications to put in the specs 97 that can be used in various specifications like CC1_SPEC. Its definition 98 is an initializer with a subgrouping for each command option. 99 100 Each subgrouping contains a string constant, that defines the 101 specification name, and a string constant that used by the GCC driver 102 program. 103 104 Do not define this macro if it does not need to do anything. */ 105 #define EXTRA_SPECS \ 106 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 107 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 108 SUBTARGET_EXTRA_SPECS 109 110 #ifndef SUBTARGET_EXTRA_SPECS 111 #define SUBTARGET_EXTRA_SPECS 112 #endif 113 114 #ifndef SUBTARGET_CPP_SPEC 115 #define SUBTARGET_CPP_SPEC "" 116 #endif 117 118 /* Tree Target Specification. */ 119 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 120 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 121 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 122 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 123 124 /* Run-time Target Specification. */ 125 /* Use hardware floating point instructions. -mgeneral-regs-only prevents 126 the use of floating point instructions and registers but does not prevent 127 emission of floating point pcs attributes. */ 128 #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 129 && bitmap_bit_p (arm_active_target.isa, \ 130 isa_bit_vfpv2) \ 131 && TARGET_32BIT) 132 133 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \ 134 && !TARGET_GENERAL_REGS_ONLY) 135 136 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB) 137 /* User has permitted use of FP instructions, if they exist for this 138 target. */ 139 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 140 /* Use hardware floating point calling convention. */ 141 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 142 #define TARGET_IWMMXT (arm_arch_iwmmxt) 143 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 144 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ 145 && !TARGET_GENERAL_REGS_ONLY) 146 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ 147 && !TARGET_GENERAL_REGS_ONLY) 148 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 149 #define TARGET_ARM (! TARGET_THUMB) 150 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 151 #define TARGET_BACKTRACE (crtl->is_leaf \ 152 ? TARGET_TPCS_LEAF_FRAME \ 153 : TARGET_TPCS_FRAME) 154 #define TARGET_AAPCS_BASED \ 155 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 156 157 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 158 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 159 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 160 161 /* Only 16-bit thumb code. */ 162 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 163 /* Arm or Thumb-2 32-bit code. */ 164 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 165 /* 32-bit Thumb-2 code. */ 166 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 167 /* Thumb-1 only. */ 168 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 169 170 #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ 171 && !TARGET_THUMB1) 172 173 #define TARGET_CRC32 (arm_arch_crc) 174 175 /* The following two macros concern the ability to execute coprocessor 176 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 177 only ever tested when we know we are generating for VFP hardware; we need 178 to be more careful with TARGET_NEON as noted below. */ 179 180 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 181 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) 182 183 /* FPU supports VFPv3 instructions. */ 184 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) 185 186 /* FPU supports FPv5 instructions. */ 187 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) 188 189 /* FPU only supports VFP single-precision instructions. */ 190 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) 191 192 /* FPU supports VFP double-precision instructions. */ 193 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) 194 195 /* FPU supports half-precision floating-point with NEON element load/store. */ 196 #define TARGET_NEON_FP16 \ 197 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ 198 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 199 200 /* FPU supports VFP half-precision floating-point conversions. */ 201 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 202 203 /* FPU supports converting between HFmode and DFmode in a single hardware 204 step. */ 205 #define TARGET_FP16_TO_DOUBLE \ 206 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) 207 208 /* FPU supports fused-multiply-add operations. */ 209 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) 210 211 /* FPU supports Crypto extensions. */ 212 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) 213 214 /* FPU supports Neon instructions. The setting of this macro gets 215 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 216 and TARGET_HARD_FLOAT to ensure that NEON instructions are 217 available. */ 218 #define TARGET_NEON \ 219 (TARGET_32BIT && TARGET_HARD_FLOAT \ 220 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) 221 222 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 223 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 224 225 /* Supports the Dot Product AdvSIMD extensions. */ 226 #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \ 227 && bitmap_bit_p (arm_active_target.isa, \ 228 isa_bit_dotprod) \ 229 && arm_arch8_2) 230 231 /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */ 232 #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3) 233 234 /* FPU supports the floating point FP16 instructions for ARMv8.2-A 235 and later. */ 236 #define TARGET_VFP_FP16INST \ 237 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) 238 239 /* Target supports the floating point FP16 instructions from ARMv8.2-A 240 and later. */ 241 #define TARGET_FP16FML (TARGET_NEON \ 242 && bitmap_bit_p (arm_active_target.isa, \ 243 isa_bit_fp16fml) \ 244 && arm_arch8_2) 245 246 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ 247 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) 248 249 /* Q-bit is present. */ 250 #define TARGET_ARM_QBIT \ 251 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) 252 /* Saturation operation, e.g. SSAT. */ 253 #define TARGET_ARM_SAT \ 254 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 255 /* "DSP" multiply instructions, eg. SMULxy. */ 256 #define TARGET_DSP_MULTIPLY \ 257 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) 258 /* Integer SIMD instructions, and extend-accumulate instructions. */ 259 #define TARGET_INT_SIMD \ 260 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 261 262 /* Should MOVW/MOVT be used in preference to a constant pool. */ 263 #define TARGET_USE_MOVT \ 264 (TARGET_HAVE_MOVT \ 265 && (arm_disable_literal_pool \ 266 || (!optimize_size && !current_tune->prefer_constant_pool))) 267 268 /* Nonzero if this chip provides the DMB instruction. */ 269 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 270 271 /* Nonzero if this chip implements a memory barrier via CP15. */ 272 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 273 && ! TARGET_THUMB1) 274 275 /* Nonzero if this chip implements a memory barrier instruction. */ 276 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 277 278 /* Nonzero if this chip supports ldrex and strex */ 279 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ 280 || arm_arch7 \ 281 || (arm_arch8 && !arm_arch_notm)) 282 283 /* Nonzero if this chip supports LPAE. */ 284 #define TARGET_HAVE_LPAE (arm_arch_lpae) 285 286 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 287 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ 288 || arm_arch7 \ 289 || (arm_arch8 && !arm_arch_notm)) 290 291 /* Nonzero if this chip supports ldrexd and strexd. */ 292 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 293 || arm_arch7) && arm_arch_notm) 294 295 /* Nonzero if this chip supports load-acquire and store-release. */ 296 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 297 298 /* Nonzero if this chip supports LDAEXD and STLEXD. */ 299 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ 300 && TARGET_32BIT \ 301 && arm_arch_notm) 302 303 /* Nonzero if this chip provides the MOVW and MOVT instructions. */ 304 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) 305 306 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ 307 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) 308 309 /* Nonzero if integer division instructions supported. */ 310 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 311 || (TARGET_THUMB && arm_arch_thumb_hwdiv)) 312 313 /* Nonzero if disallow volatile memory access in IT block. */ 314 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 315 316 /* Should NEON be used for 64-bits bitops. */ 317 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 318 319 /* Should constant I be slplit for OP. */ 320 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 321 ((optimize >= 2) \ 322 && can_create_pseudo_p () \ 323 && !const_ok_for_op (i, op)) 324 325 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 326 then TARGET_AAPCS_BASED must be true -- but the converse does not 327 hold. TARGET_BPABI implies the use of the BPABI runtime library, 328 etc., in addition to just the AAPCS calling conventions. */ 329 #ifndef TARGET_BPABI 330 #define TARGET_BPABI false 331 #endif 332 333 /* Transform lane numbers on big endian targets. This is used to allow for the 334 endianness difference between NEON architectural lane numbers and those 335 used in RTL */ 336 #define NEON_ENDIAN_LANE_N(mode, n) \ 337 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 338 339 /* Support for a compile-time default CPU, et cetera. The rules are: 340 --with-arch is ignored if -march or -mcpu are specified. 341 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 342 by --with-arch. 343 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 344 by -march). 345 --with-float is ignored if -mfloat-abi is specified. 346 --with-fpu is ignored if -mfpu is specified. 347 --with-abi is ignored if -mabi is specified. 348 --with-tls is ignored if -mtls-dialect is specified. */ 349 #define OPTION_DEFAULT_SPECS \ 350 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 351 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 352 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 353 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 354 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 355 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 356 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 357 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 358 359 extern const struct arm_fpu_desc 360 { 361 const char *name; 362 enum isa_feature isa_bits[isa_num_bits]; 363 } all_fpus[]; 364 365 /* Which floating point hardware to schedule for. */ 366 extern int arm_fpu_attr; 367 368 #ifndef TARGET_DEFAULT_FLOAT_ABI 369 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 370 #endif 371 372 #ifndef ARM_DEFAULT_ABI 373 #define ARM_DEFAULT_ABI ARM_ABI_APCS 374 #endif 375 376 /* AAPCS based ABIs use short enums by default. */ 377 #ifndef ARM_DEFAULT_SHORT_ENUMS 378 #define ARM_DEFAULT_SHORT_ENUMS \ 379 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 380 #endif 381 382 /* Map each of the micro-architecture variants to their corresponding 383 major architecture revision. */ 384 385 enum base_architecture 386 { 387 BASE_ARCH_0 = 0, 388 BASE_ARCH_2 = 2, 389 BASE_ARCH_3 = 3, 390 BASE_ARCH_3M = 3, 391 BASE_ARCH_4 = 4, 392 BASE_ARCH_4T = 4, 393 BASE_ARCH_5T = 5, 394 BASE_ARCH_5TE = 5, 395 BASE_ARCH_5TEJ = 5, 396 BASE_ARCH_6 = 6, 397 BASE_ARCH_6J = 6, 398 BASE_ARCH_6KZ = 6, 399 BASE_ARCH_6K = 6, 400 BASE_ARCH_6T2 = 6, 401 BASE_ARCH_6M = 6, 402 BASE_ARCH_6Z = 6, 403 BASE_ARCH_7 = 7, 404 BASE_ARCH_7A = 7, 405 BASE_ARCH_7R = 7, 406 BASE_ARCH_7M = 7, 407 BASE_ARCH_7EM = 7, 408 BASE_ARCH_8A = 8, 409 BASE_ARCH_8M_BASE = 8, 410 BASE_ARCH_8M_MAIN = 8, 411 BASE_ARCH_8R = 8 412 }; 413 414 /* The major revision number of the ARM Architecture implemented by the target. */ 415 extern enum base_architecture arm_base_arch; 416 417 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 418 extern int arm_arch4; 419 420 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 421 extern int arm_arch4t; 422 423 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */ 424 extern int arm_arch5t; 425 426 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ 427 extern int arm_arch5te; 428 429 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 430 extern int arm_arch6; 431 432 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 433 extern int arm_arch6k; 434 435 /* Nonzero if instructions present in ARMv6-M can be used. */ 436 extern int arm_arch6m; 437 438 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 439 extern int arm_arch7; 440 441 /* Nonzero if instructions not present in the 'M' profile can be used. */ 442 extern int arm_arch_notm; 443 444 /* Nonzero if instructions present in ARMv7E-M can be used. */ 445 extern int arm_arch7em; 446 447 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 448 extern int arm_arch8; 449 450 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 451 extern int arm_arch8_1; 452 453 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ 454 extern int arm_arch8_2; 455 456 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */ 457 extern int arm_arch8_3; 458 459 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ 460 extern int arm_arch8_4; 461 462 /* Nonzero if this chip supports the FP16 instructions extension of ARM 463 Architecture 8.2. */ 464 extern int arm_fp16_inst; 465 466 /* Nonzero if this chip can benefit from load scheduling. */ 467 extern int arm_ld_sched; 468 469 /* Nonzero if this chip is a StrongARM. */ 470 extern int arm_tune_strongarm; 471 472 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 473 extern int arm_arch_iwmmxt; 474 475 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 476 extern int arm_arch_iwmmxt2; 477 478 /* Nonzero if this chip is an XScale. */ 479 extern int arm_arch_xscale; 480 481 /* Nonzero if tuning for XScale. */ 482 extern int arm_tune_xscale; 483 484 /* Nonzero if tuning for stores via the write buffer. */ 485 extern int arm_tune_wbuf; 486 487 /* Nonzero if tuning for Cortex-A9. */ 488 extern int arm_tune_cortex_a9; 489 490 /* Nonzero if we should define __THUMB_INTERWORK__ in the 491 preprocessor. 492 XXX This is a bit of a hack, it's intended to help work around 493 problems in GLD which doesn't understand that armv5t code is 494 interworking clean. */ 495 extern int arm_cpp_interwork; 496 497 /* Nonzero if chip supports Thumb 1. */ 498 extern int arm_arch_thumb1; 499 500 /* Nonzero if chip supports Thumb 2. */ 501 extern int arm_arch_thumb2; 502 503 /* Nonzero if chip supports integer division instruction in ARM mode. */ 504 extern int arm_arch_arm_hwdiv; 505 506 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 507 extern int arm_arch_thumb_hwdiv; 508 509 /* Nonzero if chip disallows volatile memory access in IT block. */ 510 extern int arm_arch_no_volatile_ce; 511 512 /* Nonzero if we should use Neon to handle 64-bits operations rather 513 than core registers. */ 514 extern int prefer_neon_for_64bits; 515 516 /* Nonzero if we shouldn't use literal pools. */ 517 #ifndef USED_FOR_TARGET 518 extern bool arm_disable_literal_pool; 519 #endif 520 521 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 522 extern int arm_arch_crc; 523 524 /* Nonzero if chip supports the ARMv8-M Security Extensions. */ 525 extern int arm_arch_cmse; 526 527 #ifndef TARGET_DEFAULT 528 #define TARGET_DEFAULT (MASK_APCS_FRAME) 529 #endif 530 531 /* Nonzero if PIC code requires explicit qualifiers to generate 532 PLT and GOT relocs rather than the assembler doing so implicitly. 533 Subtargets can override these if required. */ 534 #ifndef NEED_GOT_RELOC 535 #define NEED_GOT_RELOC 0 536 #endif 537 #ifndef NEED_PLT_RELOC 538 #define NEED_PLT_RELOC 0 539 #endif 540 541 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 542 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 543 #endif 544 545 /* Nonzero if we need to refer to the GOT with a PC-relative 546 offset. In other words, generate 547 548 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 549 550 rather than 551 552 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 553 554 The default is true, which matches NetBSD. Subtargets can 555 override this if required. */ 556 #ifndef GOT_PCREL 557 #define GOT_PCREL 1 558 #endif 559 560 /* Target machine storage Layout. */ 561 562 563 /* Define this macro if it is advisable to hold scalars in registers 564 in a wider mode than that declared by the program. In such cases, 565 the value is constrained to be within the bounds of the declared 566 type, but kept valid in the wider mode. The signedness of the 567 extension may differ from that of the type. */ 568 569 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 570 if (GET_MODE_CLASS (MODE) == MODE_INT \ 571 && GET_MODE_SIZE (MODE) < 4) \ 572 { \ 573 (MODE) = SImode; \ 574 } 575 576 /* Define this if most significant bit is lowest numbered 577 in instructions that operate on numbered bit-fields. */ 578 #define BITS_BIG_ENDIAN 0 579 580 /* Define this if most significant byte of a word is the lowest numbered. 581 Most ARM processors are run in little endian mode, so that is the default. 582 If you want to have it run-time selectable, change the definition in a 583 cover file to be TARGET_BIG_ENDIAN. */ 584 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 585 586 /* Define this if most significant word of a multiword number is the lowest 587 numbered. */ 588 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 589 590 #define UNITS_PER_WORD 4 591 592 /* True if natural alignment is used for doubleword types. */ 593 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 594 595 #define DOUBLEWORD_ALIGNMENT 64 596 597 #define PARM_BOUNDARY 32 598 599 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 600 601 #define PREFERRED_STACK_BOUNDARY \ 602 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 603 604 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 605 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 606 607 /* The lowest bit is used to indicate Thumb-mode functions, so the 608 vbit must go into the delta field of pointers to member 609 functions. */ 610 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 611 612 #define EMPTY_FIELD_BOUNDARY 32 613 614 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 615 616 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 617 618 /* XXX Blah -- this macro is used directly by libobjc. Since it 619 supports no vector modes, cut out the complexity and fall back 620 on BIGGEST_FIELD_ALIGNMENT. */ 621 #ifdef IN_TARGET_LIBS 622 #define BIGGEST_FIELD_ALIGNMENT 64 623 #endif 624 625 /* Align definitions of arrays, unions and structures so that 626 initializations and copies can be made more efficient. This is not 627 ABI-changing, so it only affects places where we can see the 628 definition. Increasing the alignment tends to introduce padding, 629 so don't do this when optimizing for size/conserving stack space. */ 630 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 631 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 632 && (TREE_CODE (EXP) == ARRAY_TYPE \ 633 || TREE_CODE (EXP) == UNION_TYPE \ 634 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 635 636 /* Align global data. */ 637 #define DATA_ALIGNMENT(EXP, ALIGN) \ 638 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 639 640 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 641 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 642 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 643 644 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 645 value set in previous versions of this toolchain was 8, which produces more 646 compact structures. The command line option -mstructure_size_boundary=<n> 647 can be used to change this value. For compatibility with the ARM SDK 648 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 649 0020D) page 2-20 says "Structures are aligned on word boundaries". 650 The AAPCS specifies a value of 8. */ 651 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 652 653 /* This is the value used to initialize arm_structure_size_boundary. If a 654 particular arm target wants to change the default value it should change 655 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 656 for an example of this. */ 657 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 658 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 659 #endif 660 661 /* Nonzero if move instructions will actually fail to work 662 when given unaligned data. */ 663 #define STRICT_ALIGNMENT 1 664 665 /* wchar_t is unsigned under the AAPCS. */ 666 #ifndef WCHAR_TYPE 667 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 668 669 #define WCHAR_TYPE_SIZE BITS_PER_WORD 670 #endif 671 672 /* Sized for fixed-point types. */ 673 674 #define SHORT_FRACT_TYPE_SIZE 8 675 #define FRACT_TYPE_SIZE 16 676 #define LONG_FRACT_TYPE_SIZE 32 677 #define LONG_LONG_FRACT_TYPE_SIZE 64 678 679 #define SHORT_ACCUM_TYPE_SIZE 16 680 #define ACCUM_TYPE_SIZE 32 681 #define LONG_ACCUM_TYPE_SIZE 64 682 #define LONG_LONG_ACCUM_TYPE_SIZE 64 683 684 #define MAX_FIXED_MODE_SIZE 64 685 686 #ifndef SIZE_TYPE 687 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 688 #endif 689 690 #ifndef PTRDIFF_TYPE 691 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 692 #endif 693 694 /* AAPCS requires that structure alignment is affected by bitfields. */ 695 #ifndef PCC_BITFIELD_TYPE_MATTERS 696 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 697 #endif 698 699 /* The maximum size of the sync library functions supported. */ 700 #ifndef MAX_SYNC_LIBFUNC_SIZE 701 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 702 #endif 703 704 705 /* Standard register usage. */ 706 707 /* Register allocation in ARM Procedure Call Standard 708 (S - saved over call, F - Frame-related). 709 710 r0 * argument word/integer result 711 r1-r3 argument word 712 713 r4-r8 S register variable 714 r9 S (rfp) register variable (real frame pointer) 715 716 r10 F S (sl) stack limit (used by -mapcs-stack-check) 717 r11 F S (fp) argument pointer 718 r12 (ip) temp workspace 719 r13 F S (sp) lower end of current stack frame 720 r14 (lr) link address/workspace 721 r15 F (pc) program counter 722 723 cc This is NOT a real register, but is used internally 724 to represent things that use or set the condition 725 codes. 726 sfp This isn't either. It is used during rtl generation 727 since the offset between the frame pointer and the 728 auto's isn't known until after register allocation. 729 afp Nor this, we only need this because of non-local 730 goto. Without it fp appears to be used and the 731 elimination code won't get rid of sfp. It tracks 732 fp exactly at all times. 733 734 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 735 736 /* s0-s15 VFP scratch (aka d0-d7). 737 s16-s31 S VFP variable (aka d8-d15). 738 vfpcc Not a real register. Represents the VFP condition 739 code flags. */ 740 741 /* The stack backtrace structure is as follows: 742 fp points to here: | save code pointer | [fp] 743 | return link value | [fp, #-4] 744 | return sp value | [fp, #-8] 745 | return fp value | [fp, #-12] 746 [| saved r10 value |] 747 [| saved r9 value |] 748 [| saved r8 value |] 749 [| saved r7 value |] 750 [| saved r6 value |] 751 [| saved r5 value |] 752 [| saved r4 value |] 753 [| saved r3 value |] 754 [| saved r2 value |] 755 [| saved r1 value |] 756 [| saved r0 value |] 757 r0-r3 are not normally saved in a C function. */ 758 759 /* 1 for registers that have pervasive standard uses 760 and are not available for the register allocator. */ 761 #define FIXED_REGISTERS \ 762 { \ 763 /* Core regs. */ \ 764 0,0,0,0,0,0,0,0, \ 765 0,0,0,0,0,1,0,1, \ 766 /* VFP regs. */ \ 767 1,1,1,1,1,1,1,1, \ 768 1,1,1,1,1,1,1,1, \ 769 1,1,1,1,1,1,1,1, \ 770 1,1,1,1,1,1,1,1, \ 771 1,1,1,1,1,1,1,1, \ 772 1,1,1,1,1,1,1,1, \ 773 1,1,1,1,1,1,1,1, \ 774 1,1,1,1,1,1,1,1, \ 775 /* IWMMXT regs. */ \ 776 1,1,1,1,1,1,1,1, \ 777 1,1,1,1,1,1,1,1, \ 778 1,1,1,1, \ 779 /* Specials. */ \ 780 1,1,1,1 \ 781 } 782 783 /* 1 for registers not available across function calls. 784 These must include the FIXED_REGISTERS and also any 785 registers that can be used without being saved. 786 The latter must include the registers where values are returned 787 and the register where structure-value addresses are passed. 788 Aside from that, you can include as many other registers as you like. 789 The CC is not preserved over function calls on the ARM 6, so it is 790 easier to assume this for all. SFP is preserved, since FP is. */ 791 #define CALL_USED_REGISTERS \ 792 { \ 793 /* Core regs. */ \ 794 1,1,1,1,0,0,0,0, \ 795 0,0,0,0,1,1,1,1, \ 796 /* VFP Regs. */ \ 797 1,1,1,1,1,1,1,1, \ 798 1,1,1,1,1,1,1,1, \ 799 1,1,1,1,1,1,1,1, \ 800 1,1,1,1,1,1,1,1, \ 801 1,1,1,1,1,1,1,1, \ 802 1,1,1,1,1,1,1,1, \ 803 1,1,1,1,1,1,1,1, \ 804 1,1,1,1,1,1,1,1, \ 805 /* IWMMXT regs. */ \ 806 1,1,1,1,1,1,1,1, \ 807 1,1,1,1,1,1,1,1, \ 808 1,1,1,1, \ 809 /* Specials. */ \ 810 1,1,1,1 \ 811 } 812 813 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 814 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 815 #endif 816 817 /* These are a couple of extensions to the formats accepted 818 by asm_fprintf: 819 %@ prints out ASM_COMMENT_START 820 %r prints out REGISTER_PREFIX reg_names[arg] */ 821 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 822 case '@': \ 823 fputs (ASM_COMMENT_START, FILE); \ 824 break; \ 825 \ 826 case 'r': \ 827 fputs (REGISTER_PREFIX, FILE); \ 828 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 829 break; 830 831 /* Round X up to the nearest word. */ 832 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 833 834 /* Convert fron bytes to ints. */ 835 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 836 837 /* The number of (integer) registers required to hold a quantity of type MODE. 838 Also used for VFP registers. */ 839 #define ARM_NUM_REGS(MODE) \ 840 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 841 842 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 843 #define ARM_NUM_REGS2(MODE, TYPE) \ 844 ARM_NUM_INTS ((MODE) == BLKmode ? \ 845 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 846 847 /* The number of (integer) argument register available. */ 848 #define NUM_ARG_REGS 4 849 850 /* And similarly for the VFP. */ 851 #define NUM_VFP_ARG_REGS 16 852 853 /* Return the register number of the N'th (integer) argument. */ 854 #define ARG_REGISTER(N) (N - 1) 855 856 /* Specify the registers used for certain standard purposes. 857 The values of these macros are register numbers. */ 858 859 /* The number of the last argument register. */ 860 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 861 862 /* The numbers of the Thumb register ranges. */ 863 #define FIRST_LO_REGNUM 0 864 #define LAST_LO_REGNUM 7 865 #define FIRST_HI_REGNUM 8 866 #define LAST_HI_REGNUM 11 867 868 /* Overridden by config/arm/bpabi.h. */ 869 #ifndef ARM_UNWIND_INFO 870 #define ARM_UNWIND_INFO 0 871 #endif 872 873 /* Overriden by config/arm/netbsd-eabi.h. */ 874 #ifndef ARM_DWARF_UNWIND_TABLES 875 #define ARM_DWARF_UNWIND_TABLES 0 876 #endif 877 878 /* Use r0 and r1 to pass exception handling information. */ 879 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 880 881 /* The register that holds the return address in exception handlers. */ 882 #define ARM_EH_STACKADJ_REGNUM 2 883 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 884 885 #ifndef ARM_TARGET2_DWARF_FORMAT 886 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 887 #endif 888 889 #if ARM_DWARF_UNWIND_TABLES 890 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 891 for 32bit platforms. */ 892 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 893 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 894 : DW_EH_PE_absptr) 895 #else 896 /* ttype entries (the only interesting data references used) 897 use TARGET2 relocations. */ 898 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 899 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 900 : DW_EH_PE_absptr) 901 #endif 902 903 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 904 as an invisible last argument (possible since varargs don't exist in 905 Pascal), so the following is not true. */ 906 #define STATIC_CHAIN_REGNUM 12 907 908 /* Define this to be where the real frame pointer is if it is not possible to 909 work out the offset between the frame pointer and the automatic variables 910 until after register allocation has taken place. FRAME_POINTER_REGNUM 911 should point to a special register that we will make sure is eliminated. 912 913 For the Thumb we have another problem. The TPCS defines the frame pointer 914 as r11, and GCC believes that it is always possible to use the frame pointer 915 as base register for addressing purposes. (See comments in 916 find_reloads_address()). But - the Thumb does not allow high registers, 917 including r11, to be used as base address registers. Hence our problem. 918 919 The solution used here, and in the old thumb port is to use r7 instead of 920 r11 as the hard frame pointer and to have special code to generate 921 backtrace structures on the stack (if required to do so via a command line 922 option) using r11. This is the only 'user visible' use of r11 as a frame 923 pointer. */ 924 #define ARM_HARD_FRAME_POINTER_REGNUM 11 925 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 926 927 #define HARD_FRAME_POINTER_REGNUM \ 928 (TARGET_ARM \ 929 ? ARM_HARD_FRAME_POINTER_REGNUM \ 930 : THUMB_HARD_FRAME_POINTER_REGNUM) 931 932 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 933 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 934 935 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 936 937 /* Register to use for pushing function arguments. */ 938 #define STACK_POINTER_REGNUM SP_REGNUM 939 940 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 941 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 942 943 /* Need to sync with WCGR in iwmmxt.md. */ 944 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 945 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 946 947 #define IS_IWMMXT_REGNUM(REGNUM) \ 948 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 949 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 950 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 951 952 /* Base register for access to local variables of the function. */ 953 #define FRAME_POINTER_REGNUM 102 954 955 /* Base register for access to arguments of the function. */ 956 #define ARG_POINTER_REGNUM 103 957 958 #define FIRST_VFP_REGNUM 16 959 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 960 #define LAST_VFP_REGNUM \ 961 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 962 963 #define IS_VFP_REGNUM(REGNUM) \ 964 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 965 966 /* VFP registers are split into two types: those defined by VFP versions < 3 967 have D registers overlaid on consecutive pairs of S registers. VFP version 3 968 defines 16 new D registers (d16-d31) which, for simplicity and correctness 969 in various parts of the backend, we implement as "fake" single-precision 970 registers (which would be S32-S63, but cannot be used in that way). The 971 following macros define these ranges of registers. */ 972 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 973 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 974 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 975 976 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 977 ((REGNUM) <= LAST_LO_VFP_REGNUM) 978 979 /* DFmode values are only valid in even register pairs. */ 980 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 981 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 982 983 /* Neon Quad values must start at a multiple of four registers. */ 984 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 985 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 986 987 /* Neon structures of vectors must be in even register pairs and there 988 must be enough registers available. Because of various patterns 989 requiring quad registers, we require them to start at a multiple of 990 four. */ 991 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 992 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 993 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 994 995 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 996 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 997 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 998 #define FIRST_PSEUDO_REGISTER 104 999 1000 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1001 1002 /* Value should be nonzero if functions must have frame pointers. 1003 Zero means the frame pointer need not be set up (and parms may be accessed 1004 via the stack pointer) in functions that seem suitable. 1005 If we have to have a frame pointer we might as well make use of it. 1006 APCS says that the frame pointer does not need to be pushed in leaf 1007 functions, or simple tail call functions. */ 1008 1009 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1010 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1011 #endif 1012 1013 #define VALID_IWMMXT_REG_MODE(MODE) \ 1014 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1015 1016 /* Modes valid for Neon D registers. */ 1017 #define VALID_NEON_DREG_MODE(MODE) \ 1018 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1019 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1020 1021 /* Modes valid for Neon Q registers. */ 1022 #define VALID_NEON_QREG_MODE(MODE) \ 1023 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1024 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode) 1025 1026 /* Structure modes valid for Neon registers. */ 1027 #define VALID_NEON_STRUCT_MODE(MODE) \ 1028 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1029 || (MODE) == CImode || (MODE) == XImode) 1030 1031 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1032 extern int arm_regs_in_sequence[]; 1033 1034 /* The order in which register should be allocated. It is good to use ip 1035 since no saving is required (though calls clobber it) and it never contains 1036 function parameters. It is quite good to use lr since other calls may 1037 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1038 least likely to contain a function parameter; in addition results are 1039 returned in r0. 1040 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1041 then D8-D15. The reason for doing this is to attempt to reduce register 1042 pressure when both single- and double-precision registers are used in a 1043 function. */ 1044 1045 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1046 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1047 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1048 1049 #define REG_ALLOC_ORDER \ 1050 { \ 1051 /* General registers. */ \ 1052 3, 2, 1, 0, 12, 14, 4, 5, \ 1053 6, 7, 8, 9, 10, 11, \ 1054 /* High VFP registers. */ \ 1055 VREG(32), VREG(33), VREG(34), VREG(35), \ 1056 VREG(36), VREG(37), VREG(38), VREG(39), \ 1057 VREG(40), VREG(41), VREG(42), VREG(43), \ 1058 VREG(44), VREG(45), VREG(46), VREG(47), \ 1059 VREG(48), VREG(49), VREG(50), VREG(51), \ 1060 VREG(52), VREG(53), VREG(54), VREG(55), \ 1061 VREG(56), VREG(57), VREG(58), VREG(59), \ 1062 VREG(60), VREG(61), VREG(62), VREG(63), \ 1063 /* VFP argument registers. */ \ 1064 VREG(15), VREG(14), VREG(13), VREG(12), \ 1065 VREG(11), VREG(10), VREG(9), VREG(8), \ 1066 VREG(7), VREG(6), VREG(5), VREG(4), \ 1067 VREG(3), VREG(2), VREG(1), VREG(0), \ 1068 /* VFP call-saved registers. */ \ 1069 VREG(16), VREG(17), VREG(18), VREG(19), \ 1070 VREG(20), VREG(21), VREG(22), VREG(23), \ 1071 VREG(24), VREG(25), VREG(26), VREG(27), \ 1072 VREG(28), VREG(29), VREG(30), VREG(31), \ 1073 /* IWMMX registers. */ \ 1074 WREG(0), WREG(1), WREG(2), WREG(3), \ 1075 WREG(4), WREG(5), WREG(6), WREG(7), \ 1076 WREG(8), WREG(9), WREG(10), WREG(11), \ 1077 WREG(12), WREG(13), WREG(14), WREG(15), \ 1078 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1079 /* Registers not for general use. */ \ 1080 CC_REGNUM, VFPCC_REGNUM, \ 1081 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1082 SP_REGNUM, PC_REGNUM \ 1083 } 1084 1085 /* Use different register alloc ordering for Thumb. */ 1086 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1087 1088 /* Tell IRA to use the order we define rather than messing it up with its 1089 own cost calculations. */ 1090 #define HONOR_REG_ALLOC_ORDER 1 1091 1092 /* Interrupt functions can only use registers that have already been 1093 saved by the prologue, even if they would normally be 1094 call-clobbered. */ 1095 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1096 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1097 df_regs_ever_live_p (DST)) 1098 1099 /* Register and constant classes. */ 1100 1101 /* Register classes. */ 1102 enum reg_class 1103 { 1104 NO_REGS, 1105 LO_REGS, 1106 STACK_REG, 1107 BASE_REGS, 1108 HI_REGS, 1109 CALLER_SAVE_REGS, 1110 GENERAL_REGS, 1111 CORE_REGS, 1112 VFP_D0_D7_REGS, 1113 VFP_LO_REGS, 1114 VFP_HI_REGS, 1115 VFP_REGS, 1116 IWMMXT_REGS, 1117 IWMMXT_GR_REGS, 1118 CC_REG, 1119 VFPCC_REG, 1120 SFP_REG, 1121 AFP_REG, 1122 ALL_REGS, 1123 LIM_REG_CLASSES 1124 }; 1125 1126 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1127 1128 /* Give names of register classes as strings for dump file. */ 1129 #define REG_CLASS_NAMES \ 1130 { \ 1131 "NO_REGS", \ 1132 "LO_REGS", \ 1133 "STACK_REG", \ 1134 "BASE_REGS", \ 1135 "HI_REGS", \ 1136 "CALLER_SAVE_REGS", \ 1137 "GENERAL_REGS", \ 1138 "CORE_REGS", \ 1139 "VFP_D0_D7_REGS", \ 1140 "VFP_LO_REGS", \ 1141 "VFP_HI_REGS", \ 1142 "VFP_REGS", \ 1143 "IWMMXT_REGS", \ 1144 "IWMMXT_GR_REGS", \ 1145 "CC_REG", \ 1146 "VFPCC_REG", \ 1147 "SFP_REG", \ 1148 "AFP_REG", \ 1149 "ALL_REGS" \ 1150 } 1151 1152 /* Define which registers fit in which classes. 1153 This is an initializer for a vector of HARD_REG_SET 1154 of length N_REG_CLASSES. */ 1155 #define REG_CLASS_CONTENTS \ 1156 { \ 1157 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1158 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1159 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1160 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1161 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1162 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1163 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1164 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1165 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1166 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1167 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1168 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1169 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1170 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1171 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1172 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1173 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1174 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1175 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1176 } 1177 1178 /* Any of the VFP register classes. */ 1179 #define IS_VFP_CLASS(X) \ 1180 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1181 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1182 1183 /* The same information, inverted: 1184 Return the class number of the smallest class containing 1185 reg number REGNO. This could be a conditional expression 1186 or could index an array. */ 1187 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1188 1189 /* The class value for index registers, and the one for base regs. */ 1190 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1191 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1192 1193 /* For the Thumb the high registers cannot be used as base registers 1194 when addressing quantities in QI or HI mode; if we don't know the 1195 mode, then we must be conservative. */ 1196 #define MODE_BASE_REG_CLASS(MODE) \ 1197 (TARGET_32BIT ? CORE_REGS \ 1198 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1199 : LO_REGS) 1200 1201 /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS 1202 instead of BASE_REGS. */ 1203 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1204 1205 /* When this hook returns true for MODE, the compiler allows 1206 registers explicitly used in the rtl to be used as spill registers 1207 but prevents the compiler from extending the lifetime of these 1208 registers. */ 1209 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1210 arm_small_register_classes_for_mode_p 1211 1212 /* Must leave BASE_REGS reloads alone */ 1213 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1214 (lra_in_progress ? NO_REGS \ 1215 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1216 ? ((true_regnum (X) == -1 ? LO_REGS \ 1217 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1218 : NO_REGS)) \ 1219 : NO_REGS)) 1220 1221 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1222 (lra_in_progress ? NO_REGS \ 1223 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1224 ? ((true_regnum (X) == -1 ? LO_REGS \ 1225 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1226 : NO_REGS)) \ 1227 : NO_REGS) 1228 1229 /* Return the register class of a scratch register needed to copy IN into 1230 or out of a register in CLASS in MODE. If it can be done directly, 1231 NO_REGS is returned. */ 1232 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1233 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1234 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1235 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1236 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1237 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1238 : TARGET_32BIT \ 1239 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1240 ? GENERAL_REGS : NO_REGS) \ 1241 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1242 1243 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1244 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1245 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1246 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1247 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1248 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1249 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1250 (TARGET_32BIT ? \ 1251 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1252 && CONSTANT_P (X)) \ 1253 ? GENERAL_REGS : \ 1254 (((MODE) == HImode && ! arm_arch4 \ 1255 && (MEM_P (X) \ 1256 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1257 && true_regnum (X) == -1))) \ 1258 ? GENERAL_REGS : NO_REGS) \ 1259 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1260 1261 /* Return the maximum number of consecutive registers 1262 needed to represent mode MODE in a register of class CLASS. 1263 ARM regs are UNITS_PER_WORD bits. 1264 FIXME: Is this true for iWMMX? */ 1265 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1266 (ARM_NUM_REGS (MODE)) 1267 1268 /* If defined, gives a class of registers that cannot be used as the 1269 operand of a SUBREG that changes the mode of the object illegally. */ 1270 1271 /* Stack layout; function entry, exit and calling. */ 1272 1273 /* Define this if pushing a word on the stack 1274 makes the stack pointer a smaller address. */ 1275 #define STACK_GROWS_DOWNWARD 1 1276 1277 /* Define this to nonzero if the nominal address of the stack frame 1278 is at the high-address end of the local variables; 1279 that is, each additional local variable allocated 1280 goes at a more negative offset in the frame. */ 1281 #define FRAME_GROWS_DOWNWARD 1 1282 1283 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1284 When present, it is one word in size, and sits at the top of the frame, 1285 between the soft frame pointer and either r7 or r11. 1286 1287 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1288 and only then if some outgoing arguments are passed on the stack. It would 1289 be tempting to also check whether the stack arguments are passed by indirect 1290 calls, but there seems to be no reason in principle why a post-reload pass 1291 couldn't convert a direct call into an indirect one. */ 1292 #define CALLER_INTERWORKING_SLOT_SIZE \ 1293 (TARGET_CALLER_INTERWORKING \ 1294 && maybe_ne (crtl->outgoing_args_size, 0) \ 1295 ? UNITS_PER_WORD : 0) 1296 1297 /* If we generate an insn to push BYTES bytes, 1298 this says how many the stack pointer really advances by. */ 1299 /* The push insns do not do this rounding implicitly. 1300 So don't define this. */ 1301 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1302 1303 /* Define this if the maximum size of all the outgoing args is to be 1304 accumulated and pushed during the prologue. The amount can be 1305 found in the variable crtl->outgoing_args_size. */ 1306 #define ACCUMULATE_OUTGOING_ARGS 1 1307 1308 /* Offset of first parameter from the argument pointer register value. */ 1309 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1310 1311 /* Amount of memory needed for an untyped call to save all possible return 1312 registers. */ 1313 #define APPLY_RESULT_SIZE arm_apply_result_size() 1314 1315 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1316 values must be in memory. On the ARM, they need only do so if larger 1317 than a word, or if they contain elements offset from zero in the struct. */ 1318 #define DEFAULT_PCC_STRUCT_RETURN 0 1319 1320 /* These bits describe the different types of function supported 1321 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1322 normal function and an interworked function, for example. Knowing the 1323 type of a function is important for determining its prologue and 1324 epilogue sequences. 1325 Note value 7 is currently unassigned. Also note that the interrupt 1326 function types all have bit 2 set, so that they can be tested for easily. 1327 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1328 machine_function structure is initialized (to zero) func_type will 1329 default to unknown. This will force the first use of arm_current_func_type 1330 to call arm_compute_func_type. */ 1331 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1332 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1333 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1334 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1335 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1336 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1337 1338 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1339 1340 /* In addition functions can have several type modifiers, 1341 outlined by these bit masks: */ 1342 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1343 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1344 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1345 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1346 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1347 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ 1348 1349 /* Some macros to test these flags. */ 1350 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1351 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1352 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1353 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1354 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1355 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1356 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) 1357 1358 1359 /* Structure used to hold the function stack frame layout. Offsets are 1360 relative to the stack pointer on function entry. Positive offsets are 1361 in the direction of stack growth. 1362 Only soft_frame is used in thumb mode. */ 1363 1364 typedef struct GTY(()) arm_stack_offsets 1365 { 1366 int saved_args; /* ARG_POINTER_REGNUM. */ 1367 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1368 int saved_regs; 1369 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1370 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1371 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1372 unsigned int saved_regs_mask; 1373 } 1374 arm_stack_offsets; 1375 1376 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1377 /* A C structure for machine-specific, per-function data. 1378 This is added to the cfun structure. */ 1379 typedef struct GTY(()) machine_function 1380 { 1381 /* Additional stack adjustment in __builtin_eh_throw. */ 1382 rtx eh_epilogue_sp_ofs; 1383 /* Records if LR has to be saved for far jumps. */ 1384 int far_jump_used; 1385 /* Records if ARG_POINTER was ever live. */ 1386 int arg_pointer_live; 1387 /* Records if the save of LR has been eliminated. */ 1388 int lr_save_eliminated; 1389 /* The size of the stack frame. Only valid after reload. */ 1390 arm_stack_offsets stack_offsets; 1391 /* Records the type of the current function. */ 1392 unsigned long func_type; 1393 /* Record if the function has a variable argument list. */ 1394 int uses_anonymous_args; 1395 /* Records if sibcalls are blocked because an argument 1396 register is needed to preserve stack alignment. */ 1397 int sibcall_blocked; 1398 /* The PIC register for this function. This might be a pseudo. */ 1399 rtx pic_reg; 1400 /* Labels for per-function Thumb call-via stubs. One per potential calling 1401 register. We can never call via LR or PC. We can call via SP if a 1402 trampoline happens to be on the top of the stack. */ 1403 rtx call_via[14]; 1404 /* Set to 1 when a return insn is output, this means that the epilogue 1405 is not needed. */ 1406 int return_used_this_function; 1407 /* When outputting Thumb-1 code, record the last insn that provides 1408 information about condition codes, and the comparison operands. */ 1409 rtx thumb1_cc_insn; 1410 rtx thumb1_cc_op0; 1411 rtx thumb1_cc_op1; 1412 /* Also record the CC mode that is supported. */ 1413 machine_mode thumb1_cc_mode; 1414 /* Set to 1 after arm_reorg has started. */ 1415 int after_arm_reorg; 1416 /* The number of bytes used to store the static chain register on the 1417 stack, above the stack frame. */ 1418 int static_chain_stack_bytes; 1419 } 1420 machine_function; 1421 #endif 1422 1423 /* As in the machine_function, a global set of call-via labels, for code 1424 that is in text_section. */ 1425 extern GTY(()) rtx thumb_call_via_label[14]; 1426 1427 /* The number of potential ways of assigning to a co-processor. */ 1428 #define ARM_NUM_COPROC_SLOTS 1 1429 1430 /* Enumeration of procedure calling standard variants. We don't really 1431 support all of these yet. */ 1432 enum arm_pcs 1433 { 1434 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1435 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1436 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1437 /* This must be the last AAPCS variant. */ 1438 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1439 ARM_PCS_ATPCS, /* ATPCS. */ 1440 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1441 ARM_PCS_UNKNOWN 1442 }; 1443 1444 /* Default procedure calling standard of current compilation unit. */ 1445 extern enum arm_pcs arm_pcs_default; 1446 1447 #if !defined (USED_FOR_TARGET) 1448 /* A C type for declaring a variable that is used as the first argument of 1449 `FUNCTION_ARG' and other related values. */ 1450 typedef struct 1451 { 1452 /* This is the number of registers of arguments scanned so far. */ 1453 int nregs; 1454 /* This is the number of iWMMXt register arguments scanned so far. */ 1455 int iwmmxt_nregs; 1456 int named_count; 1457 int nargs; 1458 /* Which procedure call variant to use for this call. */ 1459 enum arm_pcs pcs_variant; 1460 1461 /* AAPCS related state tracking. */ 1462 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1463 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1464 this argument, or -1 if using core 1465 registers. */ 1466 int aapcs_ncrn; 1467 int aapcs_next_ncrn; 1468 rtx aapcs_reg; /* Register assigned to this argument. */ 1469 int aapcs_partial; /* How many bytes are passed in regs (if 1470 split between core regs and stack. 1471 Zero otherwise. */ 1472 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1473 int can_split; /* Argument can be split between core regs 1474 and the stack. */ 1475 /* Private data for tracking VFP register allocation */ 1476 unsigned aapcs_vfp_regs_free; 1477 unsigned aapcs_vfp_reg_alloc; 1478 int aapcs_vfp_rcount; 1479 MACHMODE aapcs_vfp_rmode; 1480 } CUMULATIVE_ARGS; 1481 #endif 1482 1483 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1484 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1485 1486 /* For AAPCS, padding should never be below the argument. For other ABIs, 1487 * mimic the default. */ 1488 #define PAD_VARARGS_DOWN \ 1489 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1490 1491 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1492 for a call to a function whose data type is FNTYPE. 1493 For a library call, FNTYPE is 0. 1494 On the ARM, the offset starts at 0. */ 1495 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1496 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1497 1498 /* 1 if N is a possible register number for function argument passing. 1499 On the ARM, r0-r3 are used to pass args. */ 1500 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1501 (IN_RANGE ((REGNO), 0, 3) \ 1502 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ 1503 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1504 || (TARGET_IWMMXT_ABI \ 1505 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1506 1507 1508 /* If your target environment doesn't prefix user functions with an 1509 underscore, you may wish to re-define this to prevent any conflicts. */ 1510 #ifndef ARM_MCOUNT_NAME 1511 #define ARM_MCOUNT_NAME "*mcount" 1512 #endif 1513 1514 /* Call the function profiler with a given profile label. The Acorn 1515 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1516 On the ARM the full profile code will look like: 1517 .data 1518 LP1 1519 .word 0 1520 .text 1521 mov ip, lr 1522 bl mcount 1523 .word LP1 1524 1525 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1526 will output the .text section. 1527 1528 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1529 ``prof'' doesn't seem to mind about this! 1530 1531 Note - this version of the code is designed to work in both ARM and 1532 Thumb modes. */ 1533 #ifndef ARM_FUNCTION_PROFILER 1534 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1535 { \ 1536 char temp[20]; \ 1537 rtx sym; \ 1538 \ 1539 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1540 IP_REGNUM, LR_REGNUM); \ 1541 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1542 fputc ('\n', STREAM); \ 1543 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1544 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1545 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1546 } 1547 #endif 1548 1549 #ifdef THUMB_FUNCTION_PROFILER 1550 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1551 if (TARGET_ARM) \ 1552 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1553 else \ 1554 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1555 #else 1556 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1557 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1558 #endif 1559 1560 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1561 the stack pointer does not matter. The value is tested only in 1562 functions that have frame pointers. 1563 No definition is equivalent to always zero. 1564 1565 On the ARM, the function epilogue recovers the stack pointer from the 1566 frame. */ 1567 #define EXIT_IGNORE_STACK 1 1568 1569 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1570 1571 /* Determine if the epilogue should be output as RTL. 1572 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1573 #define USE_RETURN_INSN(ISCOND) \ 1574 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1575 1576 /* Definitions for register eliminations. 1577 1578 This is an array of structures. Each structure initializes one pair 1579 of eliminable registers. The "from" register number is given first, 1580 followed by "to". Eliminations of the same "from" register are listed 1581 in order of preference. 1582 1583 We have two registers that can be eliminated on the ARM. First, the 1584 arg pointer register can often be eliminated in favor of the stack 1585 pointer register. Secondly, the pseudo frame pointer register can always 1586 be eliminated; it is replaced with either the stack or the real frame 1587 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1588 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1589 1590 #define ELIMINABLE_REGS \ 1591 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1592 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1593 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1594 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1595 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1596 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1597 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1598 1599 /* Define the offset between two registers, one to be eliminated, and the 1600 other its replacement, at the start of a routine. */ 1601 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1602 if (TARGET_ARM) \ 1603 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1604 else \ 1605 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1606 1607 /* Special case handling of the location of arguments passed on the stack. */ 1608 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1609 1610 /* Initialize data used by insn expanders. This is called from insn_emit, 1611 once for every function before code is generated. */ 1612 #define INIT_EXPANDERS arm_init_expanders () 1613 1614 /* Length in units of the trampoline for entering a nested function. */ 1615 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1616 1617 /* Alignment required for a trampoline in bits. */ 1618 #define TRAMPOLINE_ALIGNMENT 32 1619 1620 /* Addressing modes, and classification of registers for them. */ 1621 #define HAVE_POST_INCREMENT 1 1622 #define HAVE_PRE_INCREMENT TARGET_32BIT 1623 #define HAVE_POST_DECREMENT TARGET_32BIT 1624 #define HAVE_PRE_DECREMENT TARGET_32BIT 1625 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1626 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1627 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1628 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1629 1630 enum arm_auto_incmodes 1631 { 1632 ARM_POST_INC, 1633 ARM_PRE_INC, 1634 ARM_POST_DEC, 1635 ARM_PRE_DEC 1636 }; 1637 1638 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1639 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1640 #define USE_LOAD_POST_INCREMENT(mode) \ 1641 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1642 #define USE_LOAD_PRE_INCREMENT(mode) \ 1643 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1644 #define USE_LOAD_POST_DECREMENT(mode) \ 1645 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1646 #define USE_LOAD_PRE_DECREMENT(mode) \ 1647 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1648 1649 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1650 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1651 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1652 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1653 1654 /* Macros to check register numbers against specific register classes. */ 1655 1656 /* These assume that REGNO is a hard or pseudo reg number. 1657 They give nonzero only if REGNO is a hard reg of the suitable class 1658 or a pseudo reg currently allocated to a suitable hard reg. */ 1659 #define TEST_REGNO(R, TEST, VALUE) \ 1660 ((R TEST VALUE) \ 1661 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1662 1663 /* Don't allow the pc to be used. */ 1664 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1665 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1666 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1667 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1668 1669 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1670 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1671 || (GET_MODE_SIZE (MODE) >= 4 \ 1672 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1673 1674 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1675 (TARGET_THUMB1 \ 1676 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1677 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1678 1679 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1680 For Thumb, we cannot use SP + reg, so reject SP. */ 1681 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1682 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1683 1684 /* For ARM code, we don't care about the mode, but for Thumb, the index 1685 must be suitable for use in a QImode load. */ 1686 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1687 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1688 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1689 1690 /* Maximum number of registers that can appear in a valid memory address. 1691 Shifts in addresses can't be by a register. */ 1692 #define MAX_REGS_PER_ADDRESS 2 1693 1694 /* Recognize any constant value that is a valid address. */ 1695 /* XXX We can address any constant, eventually... */ 1696 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1697 #define CONSTANT_ADDRESS_P(X) \ 1698 (GET_CODE (X) == SYMBOL_REF \ 1699 && (CONSTANT_POOL_ADDRESS_P (X) \ 1700 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1701 1702 /* True if SYMBOL + OFFSET constants must refer to something within 1703 SYMBOL's section. */ 1704 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1705 1706 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1707 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1708 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1709 #endif 1710 1711 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1712 #define SUBTARGET_NAME_ENCODING_LENGTHS 1713 #endif 1714 1715 /* This is a C fragment for the inside of a switch statement. 1716 Each case label should return the number of characters to 1717 be stripped from the start of a function's name, if that 1718 name starts with the indicated character. */ 1719 #define ARM_NAME_ENCODING_LENGTHS \ 1720 case '*': return 1; \ 1721 SUBTARGET_NAME_ENCODING_LENGTHS 1722 1723 /* This is how to output a reference to a user-level label named NAME. 1724 `assemble_name' uses this. */ 1725 #undef ASM_OUTPUT_LABELREF 1726 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1727 arm_asm_output_labelref (FILE, NAME) 1728 1729 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1730 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1731 if (TARGET_THUMB2) \ 1732 thumb2_asm_output_opcode (STREAM); 1733 1734 /* The EABI specifies that constructors should go in .init_array. 1735 Other targets use .ctors for compatibility. */ 1736 #ifndef ARM_EABI_CTORS_SECTION_OP 1737 #define ARM_EABI_CTORS_SECTION_OP \ 1738 "\t.section\t.init_array,\"aw\",%init_array" 1739 #endif 1740 #ifndef ARM_EABI_DTORS_SECTION_OP 1741 #define ARM_EABI_DTORS_SECTION_OP \ 1742 "\t.section\t.fini_array,\"aw\",%fini_array" 1743 #endif 1744 #define ARM_CTORS_SECTION_OP \ 1745 "\t.section\t.ctors,\"aw\",%progbits" 1746 #define ARM_DTORS_SECTION_OP \ 1747 "\t.section\t.dtors,\"aw\",%progbits" 1748 1749 /* Define CTORS_SECTION_ASM_OP. */ 1750 #undef CTORS_SECTION_ASM_OP 1751 #undef DTORS_SECTION_ASM_OP 1752 #ifndef IN_LIBGCC2 1753 # define CTORS_SECTION_ASM_OP \ 1754 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1755 # define DTORS_SECTION_ASM_OP \ 1756 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1757 #else /* !defined (IN_LIBGCC2) */ 1758 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1759 so we cannot use the definition above. */ 1760 # ifdef __ARM_EABI__ 1761 /* The .ctors section is not part of the EABI, so we do not define 1762 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1763 from trying to use it. We do define it when doing normal 1764 compilation, as .init_array can be used instead of .ctors. */ 1765 /* There is no need to emit begin or end markers when using 1766 init_array; the dynamic linker will compute the size of the 1767 array itself based on special symbols created by the static 1768 linker. However, we do need to arrange to set up 1769 exception-handling here. */ 1770 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1771 # define CTOR_LIST_END /* empty */ 1772 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1773 # define DTOR_LIST_END /* empty */ 1774 # else /* !defined (__ARM_EABI__) */ 1775 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1776 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1777 # endif /* !defined (__ARM_EABI__) */ 1778 #endif /* !defined (IN_LIBCC2) */ 1779 1780 /* True if the operating system can merge entities with vague linkage 1781 (e.g., symbols in COMDAT group) during dynamic linking. */ 1782 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1783 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1784 #endif 1785 1786 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1787 1788 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1789 and check its validity for a certain class. 1790 We have two alternate definitions for each of them. 1791 The usual definition accepts all pseudo regs; the other rejects 1792 them unless they have been allocated suitable hard regs. 1793 The symbol REG_OK_STRICT causes the latter definition to be used. 1794 Thumb-2 has the same restrictions as arm. */ 1795 #ifndef REG_OK_STRICT 1796 1797 #define ARM_REG_OK_FOR_BASE_P(X) \ 1798 (REGNO (X) <= LAST_ARM_REGNUM \ 1799 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1800 || REGNO (X) == FRAME_POINTER_REGNUM \ 1801 || REGNO (X) == ARG_POINTER_REGNUM) 1802 1803 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1804 ((REGNO (X) <= LAST_ARM_REGNUM \ 1805 && REGNO (X) != STACK_POINTER_REGNUM) \ 1806 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1807 || REGNO (X) == FRAME_POINTER_REGNUM \ 1808 || REGNO (X) == ARG_POINTER_REGNUM) 1809 1810 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1811 (REGNO (X) <= LAST_LO_REGNUM \ 1812 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1813 || (GET_MODE_SIZE (MODE) >= 4 \ 1814 && (REGNO (X) == STACK_POINTER_REGNUM \ 1815 || (X) == hard_frame_pointer_rtx \ 1816 || (X) == arg_pointer_rtx))) 1817 1818 #define REG_STRICT_P 0 1819 1820 #else /* REG_OK_STRICT */ 1821 1822 #define ARM_REG_OK_FOR_BASE_P(X) \ 1823 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1824 1825 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1826 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1827 1828 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1829 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1830 1831 #define REG_STRICT_P 1 1832 1833 #endif /* REG_OK_STRICT */ 1834 1835 /* Now define some helpers in terms of the above. */ 1836 1837 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1838 (TARGET_THUMB1 \ 1839 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1840 : ARM_REG_OK_FOR_BASE_P (X)) 1841 1842 /* For 16-bit Thumb, a valid index register is anything that can be used in 1843 a byte load instruction. */ 1844 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1845 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1846 1847 /* Nonzero if X is a hard reg that can be used as an index 1848 or if it is a pseudo reg. On the Thumb, the stack pointer 1849 is not suitable. */ 1850 #define REG_OK_FOR_INDEX_P(X) \ 1851 (TARGET_THUMB1 \ 1852 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1853 : ARM_REG_OK_FOR_INDEX_P (X)) 1854 1855 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1856 For Thumb, we cannot use SP + reg, so reject SP. */ 1857 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1858 REG_OK_FOR_INDEX_P (X) 1859 1860 #define ARM_BASE_REGISTER_RTX_P(X) \ 1861 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 1862 1863 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1864 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 1865 1866 /* Specify the machine mode that this machine uses 1867 for the index in the tablejump instruction. */ 1868 #define CASE_VECTOR_MODE Pmode 1869 1870 #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ 1871 || (TARGET_THUMB1 \ 1872 && (optimize_size || flag_pic))) \ 1873 && (!target_pure_code)) 1874 1875 1876 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1877 (TARGET_THUMB1 \ 1878 ? (min >= 0 && max < 512 \ 1879 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 1880 : min >= -256 && max < 256 \ 1881 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 1882 : min >= 0 && max < 8192 \ 1883 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 1884 : min >= -4096 && max < 4096 \ 1885 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 1886 : SImode) \ 1887 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 1888 : (max >= 0x200) ? HImode \ 1889 : QImode)) 1890 1891 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 1892 unsigned is probably best, but may break some code. */ 1893 #ifndef DEFAULT_SIGNED_CHAR 1894 #define DEFAULT_SIGNED_CHAR 0 1895 #endif 1896 1897 /* Max number of bytes we can move from memory to memory 1898 in one reasonably fast instruction. */ 1899 #define MOVE_MAX 4 1900 1901 #undef MOVE_RATIO 1902 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 1903 1904 /* Define if operations between registers always perform the operation 1905 on the full register even if a narrower mode is specified. */ 1906 #define WORD_REGISTER_OPERATIONS 1 1907 1908 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1909 will either zero-extend or sign-extend. The value of this macro should 1910 be the code that says which one of the two operations is implicitly 1911 done, UNKNOWN if none. */ 1912 #define LOAD_EXTEND_OP(MODE) \ 1913 (TARGET_THUMB ? ZERO_EXTEND : \ 1914 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 1915 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 1916 1917 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1918 #define SLOW_BYTE_ACCESS 0 1919 1920 /* Immediate shift counts are truncated by the output routines (or was it 1921 the assembler?). Shift counts in a register are truncated by ARM. Note 1922 that the native compiler puts too large (> 32) immediate shift counts 1923 into a register and shifts by the register, letting the ARM decide what 1924 to do instead of doing that itself. */ 1925 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 1926 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1927 On the arm, Y in a register is used modulo 256 for the shift. Only for 1928 rotates is modulo 32 used. */ 1929 /* #define SHIFT_COUNT_TRUNCATED 1 */ 1930 1931 /* Calling from registers is a massive pain. */ 1932 #define NO_FUNCTION_CSE 1 1933 1934 /* The machine modes of pointers and functions */ 1935 #define Pmode SImode 1936 #define FUNCTION_MODE Pmode 1937 1938 #define ARM_FRAME_RTX(X) \ 1939 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 1940 || (X) == arg_pointer_rtx) 1941 1942 /* Try to generate sequences that don't involve branches, we can then use 1943 conditional instructions. */ 1944 #define BRANCH_COST(speed_p, predictable_p) \ 1945 ((arm_branch_cost != -1) ? arm_branch_cost : \ 1946 (current_tune->branch_cost (speed_p, predictable_p))) 1947 1948 /* False if short circuit operation is preferred. */ 1949 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 1950 ((optimize_size) \ 1951 ? (TARGET_THUMB ? false : true) \ 1952 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 1953 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 1954 1955 1956 /* Position Independent Code. */ 1957 /* We decide which register to use based on the compilation options and 1958 the assembler in use; this is more general than the APCS restriction of 1959 using sb (r9) all the time. */ 1960 extern unsigned arm_pic_register; 1961 1962 /* The register number of the register used to address a table of static 1963 data addresses in memory. */ 1964 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 1965 1966 /* We can't directly access anything that contains a symbol, 1967 nor can we indirect via the constant pool. One exception is 1968 UNSPEC_TLS, which is always PIC. */ 1969 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1970 (!(symbol_mentioned_p (X) \ 1971 || label_mentioned_p (X) \ 1972 || (GET_CODE (X) == SYMBOL_REF \ 1973 && CONSTANT_POOL_ADDRESS_P (X) \ 1974 && (symbol_mentioned_p (get_pool_constant (X)) \ 1975 || label_mentioned_p (get_pool_constant (X))))) \ 1976 || tls_mentioned_p (X)) 1977 1978 /* We need to know when we are making a constant pool; this determines 1979 whether data needs to be in the GOT or can be referenced via a GOT 1980 offset. */ 1981 extern int making_const_table; 1982 1983 /* Handle pragmas for compatibility with Intel's compilers. */ 1984 /* Also abuse this to register additional C specific EABI attributes. */ 1985 #define REGISTER_TARGET_PRAGMAS() do { \ 1986 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 1987 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 1988 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 1989 arm_lang_object_attributes_init(); \ 1990 arm_register_target_pragmas(); \ 1991 } while (0) 1992 1993 /* Condition code information. */ 1994 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1995 return the mode to be used for the comparison. */ 1996 1997 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 1998 1999 #define REVERSIBLE_CC_MODE(MODE) 1 2000 2001 #define REVERSE_CONDITION(CODE,MODE) \ 2002 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2003 ? reverse_condition_maybe_unordered (code) \ 2004 : reverse_condition (code)) 2005 2006 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2007 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2008 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2009 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2010 2011 #define CC_STATUS_INIT \ 2012 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2013 2014 #undef ASM_APP_ON 2015 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2016 "\t.syntax divided\n") 2017 2018 #undef ASM_APP_OFF 2019 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2020 "\t.thumb\n\t.syntax unified\n") 2021 2022 /* Output a push or a pop instruction (only used when profiling). 2023 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2024 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2025 that r7 isn't used by the function profiler, so we can use it as a 2026 scratch reg. WARNING: This isn't safe in the general case! It may be 2027 sensitive to future changes in final.c:profile_function. */ 2028 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2029 do \ 2030 { \ 2031 if (TARGET_THUMB1 \ 2032 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2033 { \ 2034 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2035 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2036 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2037 } \ 2038 else \ 2039 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2040 } while (0) 2041 2042 2043 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2044 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2045 do \ 2046 { \ 2047 if (TARGET_THUMB1 \ 2048 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2049 { \ 2050 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2051 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2052 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2053 } \ 2054 else \ 2055 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2056 } while (0) 2057 2058 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2059 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2060 2061 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2062 default alignment from elfos.h. */ 2063 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2064 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2065 2066 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2067 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2068 ? 1 : 0) 2069 2070 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2071 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2072 2073 /* For aliases of functions we use .thumb_set instead. */ 2074 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2075 do \ 2076 { \ 2077 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2078 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2079 \ 2080 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2081 { \ 2082 fprintf (FILE, "\t.thumb_set "); \ 2083 assemble_name (FILE, LABEL1); \ 2084 fprintf (FILE, ","); \ 2085 assemble_name (FILE, LABEL2); \ 2086 fprintf (FILE, "\n"); \ 2087 } \ 2088 else \ 2089 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2090 } \ 2091 while (0) 2092 2093 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2094 /* To support -falign-* switches we need to use .p2align so 2095 that alignment directives in code sections will be padded 2096 with no-op instructions, rather than zeroes. */ 2097 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2098 if ((LOG) != 0) \ 2099 { \ 2100 if ((MAX_SKIP) == 0) \ 2101 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2102 else \ 2103 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2104 (int) (LOG), (int) (MAX_SKIP)); \ 2105 } 2106 #endif 2107 2108 /* Add two bytes to the length of conditionally executed Thumb-2 2109 instructions for the IT instruction. */ 2110 #define ADJUST_INSN_LENGTH(insn, length) \ 2111 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2112 length += 2; 2113 2114 /* Only perform branch elimination (by making instructions conditional) if 2115 we're optimizing. For Thumb-2 check if any IT instructions need 2116 outputting. */ 2117 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2118 if (TARGET_ARM && optimize) \ 2119 arm_final_prescan_insn (INSN); \ 2120 else if (TARGET_THUMB2) \ 2121 thumb2_final_prescan_insn (INSN); \ 2122 else if (TARGET_THUMB1) \ 2123 thumb1_final_prescan_insn (INSN) 2124 2125 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2126 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2127 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2128 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2129 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2130 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2131 : 0)))) 2132 2133 /* A C expression whose value is RTL representing the value of the return 2134 address for the frame COUNT steps up from the current frame. */ 2135 2136 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2137 arm_return_addr (COUNT, FRAME) 2138 2139 /* Mask of the bits in the PC that contain the real return address 2140 when running in 26-bit mode. */ 2141 #define RETURN_ADDR_MASK26 (0x03fffffc) 2142 2143 /* Pick up the return address upon entry to a procedure. Used for 2144 dwarf2 unwind information. This also enables the table driven 2145 mechanism. */ 2146 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2147 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2148 2149 /* Used to mask out junk bits from the return address, such as 2150 processor state, interrupt status, condition codes and the like. */ 2151 #define MASK_RETURN_ADDR \ 2152 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2153 in 26 bit mode, the condition codes must be masked out of the \ 2154 return address. This does not apply to ARM6 and later processors \ 2155 when running in 32 bit mode. */ \ 2156 ((arm_arch4 || TARGET_THUMB) \ 2157 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2158 : arm_gen_return_addr_mask ()) 2159 2160 2161 /* Do not emit .note.GNU-stack by default. */ 2162 #ifndef NEED_INDICATE_EXEC_STACK 2163 #define NEED_INDICATE_EXEC_STACK 0 2164 #endif 2165 2166 #define TARGET_ARM_ARCH \ 2167 (arm_base_arch) \ 2168 2169 /* The highest Thumb instruction set version supported by the chip. */ 2170 #define TARGET_ARM_ARCH_ISA_THUMB \ 2171 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) 2172 2173 /* Expands to an upper-case char of the target's architectural 2174 profile. */ 2175 #define TARGET_ARM_ARCH_PROFILE \ 2176 (arm_active_target.profile) 2177 2178 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2179 Bit 0 for bytes, up to bit 3 for double-words. */ 2180 #define TARGET_ARM_FEATURE_LDREX \ 2181 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2182 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2183 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2184 2185 /* Set as a bit mask indicating the available widths of hardware floating 2186 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2187 32-bit support, bit 3 indicates 64-bit support. */ 2188 #define TARGET_ARM_FP \ 2189 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2190 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2191 : 0) 2192 2193 2194 /* Set as a bit mask indicating the available widths of floating point 2195 types for hardware NEON floating point. This is the same as 2196 TARGET_ARM_FP without the 64-bit bit set. */ 2197 #define TARGET_NEON_FP \ 2198 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2199 : 0) 2200 2201 /* Name of the automatic fpu-selection option. */ 2202 #define FPUTYPE_AUTO "auto" 2203 2204 /* The maximum number of parallel loads or stores we support in an ldm/stm 2205 instruction. */ 2206 #define MAX_LDM_STM_OPS 4 2207 2208 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2209 extern const char *arm_rewrite_march (int argc, const char **argv); 2210 extern const char *arm_asm_auto_mfpu (int argc, const char **argv); 2211 #define ASM_CPU_SPEC_FUNCTIONS \ 2212 { "rewrite_mcpu", arm_rewrite_mcpu }, \ 2213 { "rewrite_march", arm_rewrite_march }, \ 2214 { "asm_auto_mfpu", arm_asm_auto_mfpu }, 2215 2216 #define ASM_CPU_SPEC \ 2217 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ 2218 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ 2219 " march=*:-march=%:rewrite_march(%{march=*:%*});" \ 2220 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ 2221 " }" 2222 2223 extern const char *arm_target_thumb_only (int argc, const char **argv); 2224 #define TARGET_MODE_SPEC_FUNCTIONS \ 2225 { "target_mode_check", arm_target_thumb_only }, 2226 2227 /* -mcpu=native handling only makes sense with compiler running on 2228 an ARM chip. */ 2229 #if defined(__arm__) && defined(__linux__) 2230 extern const char *host_detect_local_cpu (int argc, const char **argv); 2231 #define HAVE_LOCAL_CPU_DETECT 2232 # define MCPU_MTUNE_NATIVE_FUNCTIONS \ 2233 { "local_cpu_detect", host_detect_local_cpu }, 2234 # define MCPU_MTUNE_NATIVE_SPECS \ 2235 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2236 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2237 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2238 #else 2239 # define MCPU_MTUNE_NATIVE_FUNCTIONS 2240 # define MCPU_MTUNE_NATIVE_SPECS "" 2241 #endif 2242 2243 const char *arm_canon_arch_option (int argc, const char **argv); 2244 2245 #define CANON_ARCH_SPEC_FUNCTION \ 2246 { "canon_arch", arm_canon_arch_option }, 2247 2248 const char *arm_be8_option (int argc, const char **argv); 2249 #define BE8_SPEC_FUNCTION \ 2250 { "be8_linkopt", arm_be8_option }, 2251 2252 # define EXTRA_SPEC_FUNCTIONS \ 2253 MCPU_MTUNE_NATIVE_FUNCTIONS \ 2254 ASM_CPU_SPEC_FUNCTIONS \ 2255 CANON_ARCH_SPEC_FUNCTION \ 2256 TARGET_MODE_SPEC_FUNCTIONS \ 2257 BE8_SPEC_FUNCTION 2258 2259 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified 2260 via the configuration option --with-mode or via the command line. The 2261 function target_mode_check is called to do the check with either: 2262 - an array of -march values if any is given; 2263 - an array of -mcpu values if any is given; 2264 - an empty array. */ 2265 #define TARGET_MODE_SPECS \ 2266 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" 2267 2268 /* Generate a canonical string to represent the architecture selected. */ 2269 #define ARCH_CANONICAL_SPECS \ 2270 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ 2271 " %{march=*: arch %*} " \ 2272 " %{mfpu=*: fpu %*} " \ 2273 " %{mfloat-abi=*: abi %*}" \ 2274 " %<march=*) " 2275 2276 /* Complete set of specs for the driver. Commas separate the 2277 individual rules so that any option suppression (%<opt...)is 2278 completed before starting subsequent rules. */ 2279 #define DRIVER_SELF_SPECS \ 2280 MCPU_MTUNE_NATIVE_SPECS, \ 2281 TARGET_MODE_SPECS, \ 2282 ARCH_CANONICAL_SPECS 2283 2284 #define TARGET_SUPPORTS_WIDE_INT 1 2285 2286 /* For switching between functions with different target attributes. */ 2287 #define SWITCHABLE_TARGET 1 2288 2289 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute 2290 representation for SHF_ARM_PURECODE in GCC. */ 2291 #define SECTION_ARM_PURECODE SECTION_MACH_DEP 2292 2293 #endif /* ! GCC_ARM_H */ 2294