1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 4 Free Software Foundation, Inc. 5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 6 and Martin Simmons (@harleqn.co.uk). 7 More major hacks by Richard Earnshaw (rearnsha@arm.com) 8 Minor hacks by Nick Clifton (nickc@cygnus.com) 9 10 This file is part of GCC. 11 12 GCC is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published 14 by the Free Software Foundation; either version 3, or (at your 15 option) any later version. 16 17 GCC is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with GCC; see the file COPYING3. If not see 24 <http://www.gnu.org/licenses/>. */ 25 26 #ifndef GCC_ARM_H 27 #define GCC_ARM_H 28 29 /* We can't use enum machine_mode inside a generator file because it 30 hasn't been created yet; we shouldn't be using any code that 31 needs the real definition though, so this ought to be safe. */ 32 #ifdef GENERATOR_FILE 33 #define MACHMODE int 34 #else 35 #include "insn-modes.h" 36 #define MACHMODE enum machine_mode 37 #endif 38 39 #include "config/vxworks-dummy.h" 40 41 /* The architecture define. */ 42 extern char arm_arch_name[]; 43 44 /* Target CPU builtins. */ 45 #define TARGET_CPU_CPP_BUILTINS() \ 46 do \ 47 { \ 48 /* Define __arm__ even when in thumb mode, for \ 49 consistency with armcc. */ \ 50 builtin_define ("__arm__"); \ 51 builtin_define ("__APCS_32__"); \ 52 if (TARGET_THUMB) \ 53 builtin_define ("__thumb__"); \ 54 if (TARGET_THUMB2) \ 55 builtin_define ("__thumb2__"); \ 56 \ 57 if (TARGET_BIG_END) \ 58 { \ 59 builtin_define ("__ARMEB__"); \ 60 if (TARGET_THUMB) \ 61 builtin_define ("__THUMBEB__"); \ 62 if (TARGET_LITTLE_WORDS) \ 63 builtin_define ("__ARMWEL__"); \ 64 } \ 65 else \ 66 { \ 67 builtin_define ("__ARMEL__"); \ 68 if (TARGET_THUMB) \ 69 builtin_define ("__THUMBEL__"); \ 70 } \ 71 \ 72 if (TARGET_SOFT_FLOAT) \ 73 builtin_define ("__SOFTFP__"); \ 74 \ 75 if (TARGET_VFP) \ 76 builtin_define ("__VFP_FP__"); \ 77 \ 78 if (TARGET_NEON) \ 79 builtin_define ("__ARM_NEON__"); \ 80 \ 81 /* Add a define for interworking. \ 82 Needed when building libgcc.a. */ \ 83 if (arm_cpp_interwork) \ 84 builtin_define ("__THUMB_INTERWORK__"); \ 85 \ 86 builtin_assert ("cpu=arm"); \ 87 builtin_assert ("machine=arm"); \ 88 \ 89 builtin_define (arm_arch_name); \ 90 if (arm_arch_cirrus) \ 91 builtin_define ("__MAVERICK__"); \ 92 if (arm_arch_xscale) \ 93 builtin_define ("__XSCALE__"); \ 94 if (arm_arch_iwmmxt) \ 95 builtin_define ("__IWMMXT__"); \ 96 if (TARGET_AAPCS_BASED) \ 97 { \ 98 builtin_define ("__ARM_EABI__"); \ 99 builtin_define ("__ARM_PCS"); \ 100 if (TARGET_HARD_FLOAT && TARGET_VFP) \ 101 builtin_define ("__ARM_PCS_VFP"); \ 102 } \ 103 if (TARGET_IDIV) \ 104 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ 105 } while (0) 106 107 /* The various ARM cores. */ 108 enum processor_type 109 { 110 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 111 IDENT, 112 #include "arm-cores.def" 113 #undef ARM_CORE 114 /* Used to indicate that no processor has been specified. */ 115 arm_none 116 }; 117 118 enum target_cpus 119 { 120 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 121 TARGET_CPU_##IDENT, 122 #include "arm-cores.def" 123 #undef ARM_CORE 124 TARGET_CPU_generic 125 }; 126 127 /* The processor for which instructions should be scheduled. */ 128 extern enum processor_type arm_tune; 129 130 typedef enum arm_cond_code 131 { 132 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 133 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 134 } 135 arm_cc; 136 137 extern arm_cc arm_current_cc; 138 139 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 140 141 extern int arm_target_label; 142 extern int arm_ccfsm_state; 143 extern GTY(()) rtx arm_target_insn; 144 /* The label of the current constant pool. */ 145 extern rtx pool_vector_label; 146 /* Set to 1 when a return insn is output, this means that the epilogue 147 is not needed. */ 148 extern int return_used_this_function; 149 /* Callback to output language specific object attributes. */ 150 extern void (*arm_lang_output_object_attributes_hook)(void); 151 152 /* Just in case configure has failed to define anything. */ 153 #ifndef TARGET_CPU_DEFAULT 154 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 155 #endif 156 157 158 #undef CPP_SPEC 159 #define CPP_SPEC "%(subtarget_cpp_spec) \ 160 %{msoft-float:%{mhard-float: \ 161 %e-msoft-float and -mhard_float may not be used together}} \ 162 %{mbig-endian:%{mlittle-endian: \ 163 %e-mbig-endian and -mlittle-endian may not be used together}}" 164 165 #ifndef CC1_SPEC 166 #define CC1_SPEC "" 167 #endif 168 169 /* This macro defines names of additional specifications to put in the specs 170 that can be used in various specifications like CC1_SPEC. Its definition 171 is an initializer with a subgrouping for each command option. 172 173 Each subgrouping contains a string constant, that defines the 174 specification name, and a string constant that used by the GCC driver 175 program. 176 177 Do not define this macro if it does not need to do anything. */ 178 #define EXTRA_SPECS \ 179 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 180 SUBTARGET_EXTRA_SPECS 181 182 #ifndef SUBTARGET_EXTRA_SPECS 183 #define SUBTARGET_EXTRA_SPECS 184 #endif 185 186 #ifndef SUBTARGET_CPP_SPEC 187 #define SUBTARGET_CPP_SPEC "" 188 #endif 189 190 /* Run-time Target Specification. */ 191 #ifndef TARGET_VERSION 192 #define TARGET_VERSION fputs (" (ARM/generic)", stderr); 193 #endif 194 195 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 196 /* Use hardware floating point instructions. */ 197 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 198 /* Use hardware floating point calling convention. */ 199 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 200 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA) 201 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK) 202 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 203 #define TARGET_IWMMXT (arm_arch_iwmmxt) 204 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 205 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 206 #define TARGET_ARM (! TARGET_THUMB) 207 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 208 #define TARGET_BACKTRACE (leaf_function_p () \ 209 ? TARGET_TPCS_LEAF_FRAME \ 210 : TARGET_TPCS_FRAME) 211 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN) 212 #define TARGET_AAPCS_BASED \ 213 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 214 215 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 216 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 217 218 /* Only 16-bit thumb code. */ 219 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 220 /* Arm or Thumb-2 32-bit code. */ 221 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 222 /* 32-bit Thumb-2 code. */ 223 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 224 /* Thumb-1 only. */ 225 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 226 /* FPA emulator without LFM. */ 227 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2) 228 229 /* The following two macros concern the ability to execute coprocessor 230 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 231 only ever tested when we know we are generating for VFP hardware; we need 232 to be more careful with TARGET_NEON as noted below. */ 233 234 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 235 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 236 237 /* FPU supports VFPv3 instructions. */ 238 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 239 240 /* FPU only supports VFP single-precision instructions. */ 241 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 242 243 /* FPU supports VFP double-precision instructions. */ 244 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 245 246 /* FPU supports half-precision floating-point with NEON element load/store. */ 247 #define TARGET_NEON_FP16 \ 248 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 249 250 /* FPU supports VFP half-precision floating-point. */ 251 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 252 253 /* FPU supports Neon instructions. The setting of this macro gets 254 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 255 and TARGET_HARD_FLOAT to ensure that NEON instructions are 256 available. */ 257 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 258 && TARGET_VFP && arm_fpu_desc->neon) 259 260 /* "DSP" multiply instructions, eg. SMULxy. */ 261 #define TARGET_DSP_MULTIPLY \ 262 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 263 /* Integer SIMD instructions, and extend-accumulate instructions. */ 264 #define TARGET_INT_SIMD \ 265 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 266 267 /* Should MOVW/MOVT be used in preference to a constant pool. */ 268 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size) 269 270 /* We could use unified syntax for arm mode, but for now we just use it 271 for Thumb-2. */ 272 #define TARGET_UNIFIED_ASM TARGET_THUMB2 273 274 /* Nonzero if integer division instructions supported. */ 275 #define TARGET_IDIV (arm_arch_hwdiv) 276 277 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 278 then TARGET_AAPCS_BASED must be true -- but the converse does not 279 hold. TARGET_BPABI implies the use of the BPABI runtime library, 280 etc., in addition to just the AAPCS calling conventions. */ 281 #ifndef TARGET_BPABI 282 #define TARGET_BPABI false 283 #endif 284 285 /* Support for a compile-time default CPU, et cetera. The rules are: 286 --with-arch is ignored if -march or -mcpu are specified. 287 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 288 by --with-arch. 289 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 290 by -march). 291 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are 292 specified. 293 --with-fpu is ignored if -mfpu is specified. 294 --with-abi is ignored is -mabi is specified. */ 295 #define OPTION_DEFAULT_SPECS \ 296 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 297 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 298 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 299 {"float", \ 300 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \ 301 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 302 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 303 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, 304 305 /* Which floating point model to use. */ 306 enum arm_fp_model 307 { 308 ARM_FP_MODEL_UNKNOWN, 309 /* FPA model (Hardware or software). */ 310 ARM_FP_MODEL_FPA, 311 /* Cirrus Maverick floating point model. */ 312 ARM_FP_MODEL_MAVERICK, 313 /* VFP floating point model. */ 314 ARM_FP_MODEL_VFP 315 }; 316 317 enum vfp_reg_type 318 { 319 VFP_NONE = 0, 320 VFP_REG_D16, 321 VFP_REG_D32, 322 VFP_REG_SINGLE 323 }; 324 325 extern const struct arm_fpu_desc 326 { 327 const char *name; 328 enum arm_fp_model model; 329 int rev; 330 enum vfp_reg_type regs; 331 int neon; 332 int fp16; 333 } *arm_fpu_desc; 334 335 /* Which floating point hardware to schedule for. */ 336 extern int arm_fpu_attr; 337 338 enum float_abi_type 339 { 340 ARM_FLOAT_ABI_SOFT, 341 ARM_FLOAT_ABI_SOFTFP, 342 ARM_FLOAT_ABI_HARD 343 }; 344 345 extern enum float_abi_type arm_float_abi; 346 347 #ifndef TARGET_DEFAULT_FLOAT_ABI 348 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 349 #endif 350 351 /* Which __fp16 format to use. 352 The enumeration values correspond to the numbering for the 353 Tag_ABI_FP_16bit_format attribute. 354 */ 355 enum arm_fp16_format_type 356 { 357 ARM_FP16_FORMAT_NONE = 0, 358 ARM_FP16_FORMAT_IEEE = 1, 359 ARM_FP16_FORMAT_ALTERNATIVE = 2 360 }; 361 362 extern enum arm_fp16_format_type arm_fp16_format; 363 #define LARGEST_EXPONENT_IS_NORMAL(bits) \ 364 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) 365 366 /* Which ABI to use. */ 367 enum arm_abi_type 368 { 369 ARM_ABI_APCS, 370 ARM_ABI_ATPCS, 371 ARM_ABI_AAPCS, 372 ARM_ABI_IWMMXT, 373 ARM_ABI_AAPCS_LINUX 374 }; 375 376 extern enum arm_abi_type arm_abi; 377 378 #ifndef ARM_DEFAULT_ABI 379 #define ARM_DEFAULT_ABI ARM_ABI_APCS 380 #endif 381 382 /* Which thread pointer access sequence to use. */ 383 enum arm_tp_type { 384 TP_AUTO, 385 TP_SOFT, 386 TP_CP15 387 }; 388 389 extern enum arm_tp_type target_thread_pointer; 390 391 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 392 extern int arm_arch3m; 393 394 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 395 extern int arm_arch4; 396 397 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 398 extern int arm_arch4t; 399 400 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 401 extern int arm_arch5; 402 403 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 404 extern int arm_arch5e; 405 406 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 407 extern int arm_arch6; 408 409 /* Nonzero if instructions not present in the 'M' profile can be used. */ 410 extern int arm_arch_notm; 411 412 /* Nonzero if instructions present in ARMv7E-M can be used. */ 413 extern int arm_arch7em; 414 415 /* Nonzero if this chip can benefit from load scheduling. */ 416 extern int arm_ld_sched; 417 418 /* Nonzero if generating thumb code. */ 419 extern int thumb_code; 420 421 /* Nonzero if this chip is a StrongARM. */ 422 extern int arm_tune_strongarm; 423 424 /* Nonzero if this chip is a Cirrus variant. */ 425 extern int arm_arch_cirrus; 426 427 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 428 extern int arm_arch_iwmmxt; 429 430 /* Nonzero if this chip is an XScale. */ 431 extern int arm_arch_xscale; 432 433 /* Nonzero if tuning for XScale. */ 434 extern int arm_tune_xscale; 435 436 /* Nonzero if tuning for stores via the write buffer. */ 437 extern int arm_tune_wbuf; 438 439 /* Nonzero if tuning for Cortex-A9. */ 440 extern int arm_tune_cortex_a9; 441 442 /* Nonzero if we should define __THUMB_INTERWORK__ in the 443 preprocessor. 444 XXX This is a bit of a hack, it's intended to help work around 445 problems in GLD which doesn't understand that armv5t code is 446 interworking clean. */ 447 extern int arm_cpp_interwork; 448 449 /* Nonzero if chip supports Thumb 2. */ 450 extern int arm_arch_thumb2; 451 452 /* Nonzero if chip supports integer division instruction. */ 453 extern int arm_arch_hwdiv; 454 455 #ifndef TARGET_DEFAULT 456 #define TARGET_DEFAULT (MASK_APCS_FRAME) 457 #endif 458 459 /* The frame pointer register used in gcc has nothing to do with debugging; 460 that is controlled by the APCS-FRAME option. */ 461 #define CAN_DEBUG_WITHOUT_FP 462 463 #define OVERRIDE_OPTIONS arm_override_options () 464 465 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 466 arm_optimization_options ((LEVEL), (SIZE)) 467 468 /* Nonzero if PIC code requires explicit qualifiers to generate 469 PLT and GOT relocs rather than the assembler doing so implicitly. 470 Subtargets can override these if required. */ 471 #ifndef NEED_GOT_RELOC 472 #define NEED_GOT_RELOC 0 473 #endif 474 #ifndef NEED_PLT_RELOC 475 #define NEED_PLT_RELOC 0 476 #endif 477 478 /* Nonzero if we need to refer to the GOT with a PC-relative 479 offset. In other words, generate 480 481 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 482 483 rather than 484 485 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 486 487 The default is true, which matches NetBSD. Subtargets can 488 override this if required. */ 489 #ifndef GOT_PCREL 490 #define GOT_PCREL 1 491 #endif 492 493 /* Target machine storage Layout. */ 494 495 496 /* Define this macro if it is advisable to hold scalars in registers 497 in a wider mode than that declared by the program. In such cases, 498 the value is constrained to be within the bounds of the declared 499 type, but kept valid in the wider mode. The signedness of the 500 extension may differ from that of the type. */ 501 502 /* It is far faster to zero extend chars than to sign extend them */ 503 504 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 505 if (GET_MODE_CLASS (MODE) == MODE_INT \ 506 && GET_MODE_SIZE (MODE) < 4) \ 507 { \ 508 if (MODE == QImode) \ 509 UNSIGNEDP = 1; \ 510 else if (MODE == HImode) \ 511 UNSIGNEDP = 1; \ 512 (MODE) = SImode; \ 513 } 514 515 /* Define this if most significant bit is lowest numbered 516 in instructions that operate on numbered bit-fields. */ 517 #define BITS_BIG_ENDIAN 0 518 519 /* Define this if most significant byte of a word is the lowest numbered. 520 Most ARM processors are run in little endian mode, so that is the default. 521 If you want to have it run-time selectable, change the definition in a 522 cover file to be TARGET_BIG_ENDIAN. */ 523 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 524 525 /* Define this if most significant word of a multiword number is the lowest 526 numbered. 527 This is always false, even when in big-endian mode. */ 528 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 529 530 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based 531 on processor pre-defineds when compiling libgcc2.c. */ 532 #if defined(__ARMEB__) && !defined(__ARMWEL__) 533 #define LIBGCC2_WORDS_BIG_ENDIAN 1 534 #else 535 #define LIBGCC2_WORDS_BIG_ENDIAN 0 536 #endif 537 538 /* Define this if most significant word of doubles is the lowest numbered. 539 The rules are different based on whether or not we use FPA-format, 540 VFP-format or some other floating point co-processor's format doubles. */ 541 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) 542 543 #define UNITS_PER_WORD 4 544 545 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword 546 registers when autovectorizing for Neon, at least until multiple vector 547 widths are supported properly by the middle-end. */ 548 #define UNITS_PER_SIMD_WORD(MODE) \ 549 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD) 550 551 /* True if natural alignment is used for doubleword types. */ 552 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 553 554 #define DOUBLEWORD_ALIGNMENT 64 555 556 #define PARM_BOUNDARY 32 557 558 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 559 560 #define PREFERRED_STACK_BOUNDARY \ 561 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 562 563 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 564 565 /* The lowest bit is used to indicate Thumb-mode functions, so the 566 vbit must go into the delta field of pointers to member 567 functions. */ 568 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 569 570 #define EMPTY_FIELD_BOUNDARY 32 571 572 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 573 574 /* XXX Blah -- this macro is used directly by libobjc. Since it 575 supports no vector modes, cut out the complexity and fall back 576 on BIGGEST_FIELD_ALIGNMENT. */ 577 #ifdef IN_TARGET_LIBS 578 #define BIGGEST_FIELD_ALIGNMENT 64 579 #endif 580 581 /* Make strings word-aligned so strcpy from constants will be faster. */ 582 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 583 584 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 585 ((TREE_CODE (EXP) == STRING_CST \ 586 && !optimize_size \ 587 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 588 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 589 590 /* Align definitions of arrays, unions and structures so that 591 initializations and copies can be made more efficient. This is not 592 ABI-changing, so it only affects places where we can see the 593 definition. */ 594 #define DATA_ALIGNMENT(EXP, ALIGN) \ 595 ((((ALIGN) < BITS_PER_WORD) \ 596 && (TREE_CODE (EXP) == ARRAY_TYPE \ 597 || TREE_CODE (EXP) == UNION_TYPE \ 598 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 599 600 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 601 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) 602 603 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 604 value set in previous versions of this toolchain was 8, which produces more 605 compact structures. The command line option -mstructure_size_boundary=<n> 606 can be used to change this value. For compatibility with the ARM SDK 607 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 608 0020D) page 2-20 says "Structures are aligned on word boundaries". 609 The AAPCS specifies a value of 8. */ 610 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 611 extern int arm_structure_size_boundary; 612 613 /* This is the value used to initialize arm_structure_size_boundary. If a 614 particular arm target wants to change the default value it should change 615 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 616 for an example of this. */ 617 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 618 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 619 #endif 620 621 /* Nonzero if move instructions will actually fail to work 622 when given unaligned data. */ 623 #define STRICT_ALIGNMENT 1 624 625 /* wchar_t is unsigned under the AAPCS. */ 626 #ifndef WCHAR_TYPE 627 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 628 629 #define WCHAR_TYPE_SIZE BITS_PER_WORD 630 #endif 631 632 #ifndef SIZE_TYPE 633 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 634 #endif 635 636 #ifndef PTRDIFF_TYPE 637 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 638 #endif 639 640 /* AAPCS requires that structure alignment is affected by bitfields. */ 641 #ifndef PCC_BITFIELD_TYPE_MATTERS 642 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 643 #endif 644 645 646 /* Standard register usage. */ 647 648 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 649 (S - saved over call). 650 651 r0 * argument word/integer result 652 r1-r3 argument word 653 654 r4-r8 S register variable 655 r9 S (rfp) register variable (real frame pointer) 656 657 r10 F S (sl) stack limit (used by -mapcs-stack-check) 658 r11 F S (fp) argument pointer 659 r12 (ip) temp workspace 660 r13 F S (sp) lower end of current stack frame 661 r14 (lr) link address/workspace 662 r15 F (pc) program counter 663 664 f0 floating point result 665 f1-f3 floating point scratch 666 667 f4-f7 S floating point variable 668 669 cc This is NOT a real register, but is used internally 670 to represent things that use or set the condition 671 codes. 672 sfp This isn't either. It is used during rtl generation 673 since the offset between the frame pointer and the 674 auto's isn't known until after register allocation. 675 afp Nor this, we only need this because of non-local 676 goto. Without it fp appears to be used and the 677 elimination code won't get rid of sfp. It tracks 678 fp exactly at all times. 679 680 *: See CONDITIONAL_REGISTER_USAGE */ 681 682 /* 683 mvf0 Cirrus floating point result 684 mvf1-mvf3 Cirrus floating point scratch 685 mvf4-mvf15 S Cirrus floating point variable. */ 686 687 /* s0-s15 VFP scratch (aka d0-d7). 688 s16-s31 S VFP variable (aka d8-d15). 689 vfpcc Not a real register. Represents the VFP condition 690 code flags. */ 691 692 /* The stack backtrace structure is as follows: 693 fp points to here: | save code pointer | [fp] 694 | return link value | [fp, #-4] 695 | return sp value | [fp, #-8] 696 | return fp value | [fp, #-12] 697 [| saved r10 value |] 698 [| saved r9 value |] 699 [| saved r8 value |] 700 [| saved r7 value |] 701 [| saved r6 value |] 702 [| saved r5 value |] 703 [| saved r4 value |] 704 [| saved r3 value |] 705 [| saved r2 value |] 706 [| saved r1 value |] 707 [| saved r0 value |] 708 [| saved f7 value |] three words 709 [| saved f6 value |] three words 710 [| saved f5 value |] three words 711 [| saved f4 value |] three words 712 r0-r3 are not normally saved in a C function. */ 713 714 /* 1 for registers that have pervasive standard uses 715 and are not available for the register allocator. */ 716 #define FIXED_REGISTERS \ 717 { \ 718 0,0,0,0,0,0,0,0, \ 719 0,0,0,0,0,1,0,1, \ 720 0,0,0,0,0,0,0,0, \ 721 1,1,1, \ 722 1,1,1,1,1,1,1,1, \ 723 1,1,1,1,1,1,1,1, \ 724 1,1,1,1,1,1,1,1, \ 725 1,1,1,1,1,1,1,1, \ 726 1,1,1,1, \ 727 1,1,1,1,1,1,1,1, \ 728 1,1,1,1,1,1,1,1, \ 729 1,1,1,1,1,1,1,1, \ 730 1,1,1,1,1,1,1,1, \ 731 1,1,1,1,1,1,1,1, \ 732 1,1,1,1,1,1,1,1, \ 733 1,1,1,1,1,1,1,1, \ 734 1,1,1,1,1,1,1,1, \ 735 1 \ 736 } 737 738 /* 1 for registers not available across function calls. 739 These must include the FIXED_REGISTERS and also any 740 registers that can be used without being saved. 741 The latter must include the registers where values are returned 742 and the register where structure-value addresses are passed. 743 Aside from that, you can include as many other registers as you like. 744 The CC is not preserved over function calls on the ARM 6, so it is 745 easier to assume this for all. SFP is preserved, since FP is. */ 746 #define CALL_USED_REGISTERS \ 747 { \ 748 1,1,1,1,0,0,0,0, \ 749 0,0,0,0,1,1,1,1, \ 750 1,1,1,1,0,0,0,0, \ 751 1,1,1, \ 752 1,1,1,1,1,1,1,1, \ 753 1,1,1,1,1,1,1,1, \ 754 1,1,1,1,1,1,1,1, \ 755 1,1,1,1,1,1,1,1, \ 756 1,1,1,1, \ 757 1,1,1,1,1,1,1,1, \ 758 1,1,1,1,1,1,1,1, \ 759 1,1,1,1,1,1,1,1, \ 760 1,1,1,1,1,1,1,1, \ 761 1,1,1,1,1,1,1,1, \ 762 1,1,1,1,1,1,1,1, \ 763 1,1,1,1,1,1,1,1, \ 764 1,1,1,1,1,1,1,1, \ 765 1 \ 766 } 767 768 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 769 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 770 #endif 771 772 #define CONDITIONAL_REGISTER_USAGE \ 773 { \ 774 int regno; \ 775 \ 776 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \ 777 { \ 778 for (regno = FIRST_FPA_REGNUM; \ 779 regno <= LAST_FPA_REGNUM; ++regno) \ 780 fixed_regs[regno] = call_used_regs[regno] = 1; \ 781 } \ 782 \ 783 if (TARGET_THUMB && optimize_size) \ 784 { \ 785 /* When optimizing for size, it's better not to use \ 786 the HI regs, because of the overhead of stacking \ 787 them. */ \ 788 /* ??? Is this still true for thumb2? */ \ 789 for (regno = FIRST_HI_REGNUM; \ 790 regno <= LAST_HI_REGNUM; ++regno) \ 791 fixed_regs[regno] = call_used_regs[regno] = 1; \ 792 } \ 793 \ 794 /* The link register can be clobbered by any branch insn, \ 795 but we have no way to track that at present, so mark \ 796 it as unavailable. */ \ 797 if (TARGET_THUMB1) \ 798 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \ 799 \ 800 if (TARGET_32BIT && TARGET_HARD_FLOAT) \ 801 { \ 802 if (TARGET_MAVERICK) \ 803 { \ 804 for (regno = FIRST_FPA_REGNUM; \ 805 regno <= LAST_FPA_REGNUM; ++ regno) \ 806 fixed_regs[regno] = call_used_regs[regno] = 1; \ 807 for (regno = FIRST_CIRRUS_FP_REGNUM; \ 808 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ 809 { \ 810 fixed_regs[regno] = 0; \ 811 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ 812 } \ 813 } \ 814 if (TARGET_VFP) \ 815 { \ 816 /* VFPv3 registers are disabled when earlier VFP \ 817 versions are selected due to the definition of \ 818 LAST_VFP_REGNUM. */ \ 819 for (regno = FIRST_VFP_REGNUM; \ 820 regno <= LAST_VFP_REGNUM; ++ regno) \ 821 { \ 822 fixed_regs[regno] = 0; \ 823 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \ 824 || regno >= FIRST_VFP_REGNUM + 32; \ 825 } \ 826 } \ 827 } \ 828 \ 829 if (TARGET_REALLY_IWMMXT) \ 830 { \ 831 regno = FIRST_IWMMXT_GR_REGNUM; \ 832 /* The 2002/10/09 revision of the XScale ABI has wCG0 \ 833 and wCG1 as call-preserved registers. The 2002/11/21 \ 834 revision changed this so that all wCG registers are \ 835 scratch registers. */ \ 836 for (regno = FIRST_IWMMXT_GR_REGNUM; \ 837 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \ 838 fixed_regs[regno] = 0; \ 839 /* The XScale ABI has wR0 - wR9 as scratch registers, \ 840 the rest as call-preserved registers. */ \ 841 for (regno = FIRST_IWMMXT_REGNUM; \ 842 regno <= LAST_IWMMXT_REGNUM; ++ regno) \ 843 { \ 844 fixed_regs[regno] = 0; \ 845 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \ 846 } \ 847 } \ 848 \ 849 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 850 { \ 851 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 852 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 853 } \ 854 else if (TARGET_APCS_STACK) \ 855 { \ 856 fixed_regs[10] = 1; \ 857 call_used_regs[10] = 1; \ 858 } \ 859 /* -mcaller-super-interworking reserves r11 for calls to \ 860 _interwork_r11_call_via_rN(). Making the register global \ 861 is an easy way of ensuring that it remains valid for all \ 862 calls. */ \ 863 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \ 864 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \ 865 { \ 866 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 867 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 868 if (TARGET_CALLER_INTERWORKING) \ 869 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 870 } \ 871 SUBTARGET_CONDITIONAL_REGISTER_USAGE \ 872 } 873 874 /* These are a couple of extensions to the formats accepted 875 by asm_fprintf: 876 %@ prints out ASM_COMMENT_START 877 %r prints out REGISTER_PREFIX reg_names[arg] */ 878 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 879 case '@': \ 880 fputs (ASM_COMMENT_START, FILE); \ 881 break; \ 882 \ 883 case 'r': \ 884 fputs (REGISTER_PREFIX, FILE); \ 885 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 886 break; 887 888 /* Round X up to the nearest word. */ 889 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 890 891 /* Convert fron bytes to ints. */ 892 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 893 894 /* The number of (integer) registers required to hold a quantity of type MODE. 895 Also used for VFP registers. */ 896 #define ARM_NUM_REGS(MODE) \ 897 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 898 899 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 900 #define ARM_NUM_REGS2(MODE, TYPE) \ 901 ARM_NUM_INTS ((MODE) == BLKmode ? \ 902 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 903 904 /* The number of (integer) argument register available. */ 905 #define NUM_ARG_REGS 4 906 907 /* And similarly for the VFP. */ 908 #define NUM_VFP_ARG_REGS 16 909 910 /* Return the register number of the N'th (integer) argument. */ 911 #define ARG_REGISTER(N) (N - 1) 912 913 /* Specify the registers used for certain standard purposes. 914 The values of these macros are register numbers. */ 915 916 /* The number of the last argument register. */ 917 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 918 919 /* The numbers of the Thumb register ranges. */ 920 #define FIRST_LO_REGNUM 0 921 #define LAST_LO_REGNUM 7 922 #define FIRST_HI_REGNUM 8 923 #define LAST_HI_REGNUM 11 924 925 #ifndef TARGET_UNWIND_INFO 926 /* We use sjlj exceptions for backwards compatibility. */ 927 #define MUST_USE_SJLJ_EXCEPTIONS 1 928 #endif 929 930 /* We can generate DWARF2 Unwind info, even though we don't use it. */ 931 #define DWARF2_UNWIND_INFO 1 932 933 /* Use r0 and r1 to pass exception handling information. */ 934 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 935 936 /* The register that holds the return address in exception handlers. */ 937 #define ARM_EH_STACKADJ_REGNUM 2 938 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 939 940 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 941 as an invisible last argument (possible since varargs don't exist in 942 Pascal), so the following is not true. */ 943 #define STATIC_CHAIN_REGNUM 12 944 945 /* Define this to be where the real frame pointer is if it is not possible to 946 work out the offset between the frame pointer and the automatic variables 947 until after register allocation has taken place. FRAME_POINTER_REGNUM 948 should point to a special register that we will make sure is eliminated. 949 950 For the Thumb we have another problem. The TPCS defines the frame pointer 951 as r11, and GCC believes that it is always possible to use the frame pointer 952 as base register for addressing purposes. (See comments in 953 find_reloads_address()). But - the Thumb does not allow high registers, 954 including r11, to be used as base address registers. Hence our problem. 955 956 The solution used here, and in the old thumb port is to use r7 instead of 957 r11 as the hard frame pointer and to have special code to generate 958 backtrace structures on the stack (if required to do so via a command line 959 option) using r11. This is the only 'user visible' use of r11 as a frame 960 pointer. */ 961 #define ARM_HARD_FRAME_POINTER_REGNUM 11 962 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 963 964 #define HARD_FRAME_POINTER_REGNUM \ 965 (TARGET_ARM \ 966 ? ARM_HARD_FRAME_POINTER_REGNUM \ 967 : THUMB_HARD_FRAME_POINTER_REGNUM) 968 969 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 970 971 /* Register to use for pushing function arguments. */ 972 #define STACK_POINTER_REGNUM SP_REGNUM 973 974 /* ARM floating pointer registers. */ 975 #define FIRST_FPA_REGNUM 16 976 #define LAST_FPA_REGNUM 23 977 #define IS_FPA_REGNUM(REGNUM) \ 978 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM)) 979 980 #define FIRST_IWMMXT_GR_REGNUM 43 981 #define LAST_IWMMXT_GR_REGNUM 46 982 #define FIRST_IWMMXT_REGNUM 47 983 #define LAST_IWMMXT_REGNUM 62 984 #define IS_IWMMXT_REGNUM(REGNUM) \ 985 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 986 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 987 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 988 989 /* Base register for access to local variables of the function. */ 990 #define FRAME_POINTER_REGNUM 25 991 992 /* Base register for access to arguments of the function. */ 993 #define ARG_POINTER_REGNUM 26 994 995 #define FIRST_CIRRUS_FP_REGNUM 27 996 #define LAST_CIRRUS_FP_REGNUM 42 997 #define IS_CIRRUS_REGNUM(REGNUM) \ 998 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) 999 1000 #define FIRST_VFP_REGNUM 63 1001 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */ 1002 #define LAST_VFP_REGNUM \ 1003 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1004 1005 #define IS_VFP_REGNUM(REGNUM) \ 1006 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1007 1008 /* VFP registers are split into two types: those defined by VFP versions < 3 1009 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1010 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1011 in various parts of the backend, we implement as "fake" single-precision 1012 registers (which would be S32-S63, but cannot be used in that way). The 1013 following macros define these ranges of registers. */ 1014 #define LAST_LO_VFP_REGNUM 94 1015 #define FIRST_HI_VFP_REGNUM 95 1016 #define LAST_HI_VFP_REGNUM 126 1017 1018 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1019 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1020 1021 /* DFmode values are only valid in even register pairs. */ 1022 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1023 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1024 1025 /* Neon Quad values must start at a multiple of four registers. */ 1026 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1027 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1028 1029 /* Neon structures of vectors must be in even register pairs and there 1030 must be enough registers available. Because of various patterns 1031 requiring quad registers, we require them to start at a multiple of 1032 four. */ 1033 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1034 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1035 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1036 1037 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ 1038 /* + 16 Cirrus registers take us up to 43. */ 1039 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1040 /* VFP (VFP3) adds 32 (64) + 1 more. */ 1041 #define FIRST_PSEUDO_REGISTER 128 1042 1043 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1044 1045 /* Value should be nonzero if functions must have frame pointers. 1046 Zero means the frame pointer need not be set up (and parms may be accessed 1047 via the stack pointer) in functions that seem suitable. 1048 If we have to have a frame pointer we might as well make use of it. 1049 APCS says that the frame pointer does not need to be pushed in leaf 1050 functions, or simple tail call functions. */ 1051 1052 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1053 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1054 #endif 1055 1056 /* Return number of consecutive hard regs needed starting at reg REGNO 1057 to hold something of mode MODE. 1058 This is ordinarily the length in words of a value of mode MODE 1059 but can be less for certain modes in special long registers. 1060 1061 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP 1062 mode. */ 1063 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1064 ((TARGET_32BIT \ 1065 && REGNO >= FIRST_FPA_REGNUM \ 1066 && REGNO != FRAME_POINTER_REGNUM \ 1067 && REGNO != ARG_POINTER_REGNUM) \ 1068 && !IS_VFP_REGNUM (REGNO) \ 1069 ? 1 : ARM_NUM_REGS (MODE)) 1070 1071 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1072 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1073 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1074 1075 /* Value is 1 if it is a good idea to tie two pseudo registers 1076 when one has mode MODE1 and one has mode MODE2. 1077 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1078 for any hard reg, then this must be 0 for correct output. */ 1079 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1080 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 1081 1082 #define VALID_IWMMXT_REG_MODE(MODE) \ 1083 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1084 1085 /* Modes valid for Neon D registers. */ 1086 #define VALID_NEON_DREG_MODE(MODE) \ 1087 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1088 || (MODE) == V2SFmode || (MODE) == DImode) 1089 1090 /* Modes valid for Neon Q registers. */ 1091 #define VALID_NEON_QREG_MODE(MODE) \ 1092 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1093 || (MODE) == V4SFmode || (MODE) == V2DImode) 1094 1095 /* Structure modes valid for Neon registers. */ 1096 #define VALID_NEON_STRUCT_MODE(MODE) \ 1097 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1098 || (MODE) == CImode || (MODE) == XImode) 1099 1100 /* The order in which register should be allocated. It is good to use ip 1101 since no saving is required (though calls clobber it) and it never contains 1102 function parameters. It is quite good to use lr since other calls may 1103 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1104 least likely to contain a function parameter; in addition results are 1105 returned in r0. 1106 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1107 then D8-D15. The reason for doing this is to attempt to reduce register 1108 pressure when both single- and double-precision registers are used in a 1109 function. */ 1110 1111 #define REG_ALLOC_ORDER \ 1112 { \ 1113 3, 2, 1, 0, 12, 14, 4, 5, \ 1114 6, 7, 8, 10, 9, 11, 13, 15, \ 1115 16, 17, 18, 19, 20, 21, 22, 23, \ 1116 27, 28, 29, 30, 31, 32, 33, 34, \ 1117 35, 36, 37, 38, 39, 40, 41, 42, \ 1118 43, 44, 45, 46, 47, 48, 49, 50, \ 1119 51, 52, 53, 54, 55, 56, 57, 58, \ 1120 59, 60, 61, 62, \ 1121 24, 25, 26, \ 1122 95, 96, 97, 98, 99, 100, 101, 102, \ 1123 103, 104, 105, 106, 107, 108, 109, 110, \ 1124 111, 112, 113, 114, 115, 116, 117, 118, \ 1125 119, 120, 121, 122, 123, 124, 125, 126, \ 1126 78, 77, 76, 75, 74, 73, 72, 71, \ 1127 70, 69, 68, 67, 66, 65, 64, 63, \ 1128 79, 80, 81, 82, 83, 84, 85, 86, \ 1129 87, 88, 89, 90, 91, 92, 93, 94, \ 1130 127 \ 1131 } 1132 1133 /* Use different register alloc ordering for Thumb. */ 1134 #define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc () 1135 1136 /* Interrupt functions can only use registers that have already been 1137 saved by the prologue, even if they would normally be 1138 call-clobbered. */ 1139 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1140 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1141 df_regs_ever_live_p (DST)) 1142 1143 /* Register and constant classes. */ 1144 1145 /* Register classes: used to be simple, just all ARM regs or all FPA regs 1146 Now that the Thumb is involved it has become more complicated. */ 1147 enum reg_class 1148 { 1149 NO_REGS, 1150 FPA_REGS, 1151 CIRRUS_REGS, 1152 VFP_D0_D7_REGS, 1153 VFP_LO_REGS, 1154 VFP_HI_REGS, 1155 VFP_REGS, 1156 IWMMXT_GR_REGS, 1157 IWMMXT_REGS, 1158 LO_REGS, 1159 STACK_REG, 1160 BASE_REGS, 1161 HI_REGS, 1162 CC_REG, 1163 VFPCC_REG, 1164 GENERAL_REGS, 1165 CORE_REGS, 1166 ALL_REGS, 1167 LIM_REG_CLASSES 1168 }; 1169 1170 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1171 1172 /* Give names of register classes as strings for dump file. */ 1173 #define REG_CLASS_NAMES \ 1174 { \ 1175 "NO_REGS", \ 1176 "FPA_REGS", \ 1177 "CIRRUS_REGS", \ 1178 "VFP_D0_D7_REGS", \ 1179 "VFP_LO_REGS", \ 1180 "VFP_HI_REGS", \ 1181 "VFP_REGS", \ 1182 "IWMMXT_GR_REGS", \ 1183 "IWMMXT_REGS", \ 1184 "LO_REGS", \ 1185 "STACK_REG", \ 1186 "BASE_REGS", \ 1187 "HI_REGS", \ 1188 "CC_REG", \ 1189 "VFPCC_REG", \ 1190 "GENERAL_REGS", \ 1191 "CORE_REGS", \ 1192 "ALL_REGS", \ 1193 } 1194 1195 /* Define which registers fit in which classes. 1196 This is an initializer for a vector of HARD_REG_SET 1197 of length N_REG_CLASSES. */ 1198 #define REG_CLASS_CONTENTS \ 1199 { \ 1200 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1201 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \ 1202 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \ 1203 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1204 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \ 1205 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \ 1206 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \ 1207 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \ 1208 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \ 1209 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1210 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1211 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1212 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1213 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ 1214 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ 1215 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1216 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1217 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ 1218 } 1219 1220 /* Any of the VFP register classes. */ 1221 #define IS_VFP_CLASS(X) \ 1222 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1223 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1224 1225 /* The same information, inverted: 1226 Return the class number of the smallest class containing 1227 reg number REGNO. This could be a conditional expression 1228 or could index an array. */ 1229 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1230 1231 /* The following macro defines cover classes for Integrated Register 1232 Allocator. Cover classes is a set of non-intersected register 1233 classes covering all hard registers used for register allocation 1234 purpose. Any move between two registers of a cover class should be 1235 cheaper than load or store of the registers. The macro value is 1236 array of register classes with LIM_REG_CLASSES used as the end 1237 marker. */ 1238 1239 #define IRA_COVER_CLASSES \ 1240 { \ 1241 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\ 1242 LIM_REG_CLASSES \ 1243 } 1244 1245 /* FPA registers can't do subreg as all values are reformatted to internal 1246 precision. VFP registers may only be accessed in the mode they 1247 were set. */ 1248 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1249 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1250 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ 1251 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ 1252 : 0) 1253 1254 /* We need to define this for LO_REGS on thumb. Otherwise we can end up 1255 using r0-r4 for function arguments, r7 for the stack frame and don't 1256 have enough left over to do doubleword arithmetic. */ 1257 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 1258 ((TARGET_THUMB && (CLASS) == LO_REGS) \ 1259 || (CLASS) == CC_REG) 1260 1261 /* The class value for index registers, and the one for base regs. */ 1262 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1263 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1264 1265 /* For the Thumb the high registers cannot be used as base registers 1266 when addressing quantities in QI or HI mode; if we don't know the 1267 mode, then we must be conservative. */ 1268 #define MODE_BASE_REG_CLASS(MODE) \ 1269 (TARGET_32BIT ? CORE_REGS : \ 1270 (((MODE) == SImode) ? BASE_REGS : LO_REGS)) 1271 1272 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1273 instead of BASE_REGS. */ 1274 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1275 1276 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1277 registers explicitly used in the rtl to be used as spill registers 1278 but prevents the compiler from extending the lifetime of these 1279 registers. */ 1280 #define SMALL_REGISTER_CLASSES TARGET_THUMB1 1281 1282 /* Given an rtx X being reloaded into a reg required to be 1283 in class CLASS, return the class of reg to actually use. 1284 In general this is just CLASS, but for the Thumb core registers and 1285 immediate constants we prefer a LO_REGS class or a subset. */ 1286 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1287 (TARGET_32BIT ? (CLASS) : \ 1288 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \ 1289 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \ 1290 ? LO_REGS : (CLASS))) 1291 1292 /* Must leave BASE_REGS reloads alone */ 1293 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1294 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1295 ? ((true_regnum (X) == -1 ? LO_REGS \ 1296 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1297 : NO_REGS)) \ 1298 : NO_REGS) 1299 1300 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1301 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1302 ? ((true_regnum (X) == -1 ? LO_REGS \ 1303 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1304 : NO_REGS)) \ 1305 : NO_REGS) 1306 1307 /* Return the register class of a scratch register needed to copy IN into 1308 or out of a register in CLASS in MODE. If it can be done directly, 1309 NO_REGS is returned. */ 1310 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1311 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1312 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1313 && IS_VFP_CLASS (CLASS)) \ 1314 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1315 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1316 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1317 : TARGET_32BIT \ 1318 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1319 ? GENERAL_REGS : NO_REGS) \ 1320 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1321 1322 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1323 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1324 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1325 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1326 && IS_VFP_CLASS (CLASS)) \ 1327 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1328 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1329 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1330 /* Cannot load constants into Cirrus registers. */ \ 1331 (TARGET_MAVERICK && TARGET_HARD_FLOAT \ 1332 && (CLASS) == CIRRUS_REGS \ 1333 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ 1334 ? GENERAL_REGS : \ 1335 (TARGET_32BIT ? \ 1336 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1337 && CONSTANT_P (X)) \ 1338 ? GENERAL_REGS : \ 1339 (((MODE) == HImode && ! arm_arch4 \ 1340 && (GET_CODE (X) == MEM \ 1341 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ 1342 && true_regnum (X) == -1))) \ 1343 ? GENERAL_REGS : NO_REGS) \ 1344 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1345 1346 /* Try a machine-dependent way of reloading an illegitimate address 1347 operand. If we find one, push the reload and jump to WIN. This 1348 macro is used in only one place: `find_reloads_address' in reload.c. 1349 1350 For the ARM, we wish to handle large displacements off a base 1351 register by splitting the addend across a MOV and the mem insn. 1352 This can cut the number of reloads needed. */ 1353 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1354 do \ 1355 { \ 1356 if (GET_CODE (X) == PLUS \ 1357 && GET_CODE (XEXP (X, 0)) == REG \ 1358 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ 1359 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ 1360 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1361 { \ 1362 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1363 HOST_WIDE_INT low, high; \ 1364 \ 1365 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \ 1366 low = ((val & 0xf) ^ 0x8) - 0x8; \ 1367 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ 1368 /* Need to be careful, -256 is not a valid offset. */ \ 1369 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1370 else if (MODE == SImode \ 1371 || (MODE == SFmode && TARGET_SOFT_FLOAT) \ 1372 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ 1373 /* Need to be careful, -4096 is not a valid offset. */ \ 1374 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ 1375 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ 1376 /* Need to be careful, -256 is not a valid offset. */ \ 1377 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1378 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1379 && TARGET_HARD_FLOAT && TARGET_FPA) \ 1380 /* Need to be careful, -1024 is not a valid offset. */ \ 1381 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ 1382 else \ 1383 break; \ 1384 \ 1385 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ 1386 ^ (unsigned HOST_WIDE_INT) 0x80000000) \ 1387 - (unsigned HOST_WIDE_INT) 0x80000000); \ 1388 /* Check for overflow or zero */ \ 1389 if (low == 0 || high == 0 || (high + low != val)) \ 1390 break; \ 1391 \ 1392 /* Reload the high part into a base reg; leave the low part \ 1393 in the mem. */ \ 1394 X = gen_rtx_PLUS (GET_MODE (X), \ 1395 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ 1396 GEN_INT (high)), \ 1397 GEN_INT (low)); \ 1398 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1399 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ 1400 VOIDmode, 0, 0, OPNUM, TYPE); \ 1401 goto WIN; \ 1402 } \ 1403 } \ 1404 while (0) 1405 1406 /* XXX If an HImode FP+large_offset address is converted to an HImode 1407 SP+large_offset address, then reload won't know how to fix it. It sees 1408 only that SP isn't valid for HImode, and so reloads the SP into an index 1409 register, but the resulting address is still invalid because the offset 1410 is too big. We fix it here instead by reloading the entire address. */ 1411 /* We could probably achieve better results by defining PROMOTE_MODE to help 1412 cope with the variances between the Thumb's signed and unsigned byte and 1413 halfword load instructions. */ 1414 /* ??? This should be safe for thumb2, but we may be able to do better. */ 1415 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1416 do { \ 1417 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1418 if (new_x) \ 1419 { \ 1420 X = new_x; \ 1421 goto WIN; \ 1422 } \ 1423 } while (0) 1424 1425 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1426 if (TARGET_ARM) \ 1427 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1428 else \ 1429 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1430 1431 /* Return the maximum number of consecutive registers 1432 needed to represent mode MODE in a register of class CLASS. 1433 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ 1434 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1435 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) 1436 1437 /* If defined, gives a class of registers that cannot be used as the 1438 operand of a SUBREG that changes the mode of the object illegally. */ 1439 1440 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. 1441 Moves between VFP_REGS and GENERAL_REGS are a single insn, but 1442 it is typically more expensive than a single memory access. We set 1443 the cost to less than two memory accesses so that floating 1444 point to integer conversion does not go through memory. */ 1445 #define REGISTER_MOVE_COST(MODE, FROM, TO) \ 1446 (TARGET_32BIT ? \ 1447 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ 1448 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ 1449 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \ 1450 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \ 1451 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ 1452 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ 1453 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ 1454 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ 1455 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ 1456 2) \ 1457 : \ 1458 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) 1459 1460 /* Stack layout; function entry, exit and calling. */ 1461 1462 /* Define this if pushing a word on the stack 1463 makes the stack pointer a smaller address. */ 1464 #define STACK_GROWS_DOWNWARD 1 1465 1466 /* Define this to nonzero if the nominal address of the stack frame 1467 is at the high-address end of the local variables; 1468 that is, each additional local variable allocated 1469 goes at a more negative offset in the frame. */ 1470 #define FRAME_GROWS_DOWNWARD 1 1471 1472 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1473 When present, it is one word in size, and sits at the top of the frame, 1474 between the soft frame pointer and either r7 or r11. 1475 1476 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1477 and only then if some outgoing arguments are passed on the stack. It would 1478 be tempting to also check whether the stack arguments are passed by indirect 1479 calls, but there seems to be no reason in principle why a post-reload pass 1480 couldn't convert a direct call into an indirect one. */ 1481 #define CALLER_INTERWORKING_SLOT_SIZE \ 1482 (TARGET_CALLER_INTERWORKING \ 1483 && crtl->outgoing_args_size != 0 \ 1484 ? UNITS_PER_WORD : 0) 1485 1486 /* Offset within stack frame to start allocating local variables at. 1487 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1488 first local allocated. Otherwise, it is the offset to the BEGINNING 1489 of the first local allocated. */ 1490 #define STARTING_FRAME_OFFSET 0 1491 1492 /* If we generate an insn to push BYTES bytes, 1493 this says how many the stack pointer really advances by. */ 1494 /* The push insns do not do this rounding implicitly. 1495 So don't define this. */ 1496 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1497 1498 /* Define this if the maximum size of all the outgoing args is to be 1499 accumulated and pushed during the prologue. The amount can be 1500 found in the variable crtl->outgoing_args_size. */ 1501 #define ACCUMULATE_OUTGOING_ARGS 1 1502 1503 /* Offset of first parameter from the argument pointer register value. */ 1504 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1505 1506 /* Value is the number of byte of arguments automatically 1507 popped when returning from a subroutine call. 1508 FUNDECL is the declaration node of the function (as a tree), 1509 FUNTYPE is the data type of the function (as a tree), 1510 or for a library call it is an identifier node for the subroutine name. 1511 SIZE is the number of bytes of arguments passed on the stack. 1512 1513 On the ARM, the caller does not pop any of its arguments that were passed 1514 on the stack. */ 1515 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 1516 1517 /* Define how to find the value returned by a library function 1518 assuming the value has mode MODE. */ 1519 #define LIBCALL_VALUE(MODE) \ 1520 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \ 1521 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \ 1522 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1523 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \ 1524 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \ 1525 && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1526 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ 1527 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \ 1528 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ 1529 : gen_rtx_REG (MODE, ARG_REGISTER (1))) 1530 1531 /* 1 if REGNO is a possible register number for a function value. */ 1532 #define FUNCTION_VALUE_REGNO_P(REGNO) \ 1533 ((REGNO) == ARG_REGISTER (1) \ 1534 || (TARGET_AAPCS_BASED && TARGET_32BIT \ 1535 && TARGET_VFP && TARGET_HARD_FLOAT \ 1536 && (REGNO) == FIRST_VFP_REGNUM) \ 1537 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \ 1538 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \ 1539 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \ 1540 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \ 1541 && TARGET_HARD_FLOAT_ABI && TARGET_FPA)) 1542 1543 /* Amount of memory needed for an untyped call to save all possible return 1544 registers. */ 1545 #define APPLY_RESULT_SIZE arm_apply_result_size() 1546 1547 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1548 values must be in memory. On the ARM, they need only do so if larger 1549 than a word, or if they contain elements offset from zero in the struct. */ 1550 #define DEFAULT_PCC_STRUCT_RETURN 0 1551 1552 /* These bits describe the different types of function supported 1553 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1554 normal function and an interworked function, for example. Knowing the 1555 type of a function is important for determining its prologue and 1556 epilogue sequences. 1557 Note value 7 is currently unassigned. Also note that the interrupt 1558 function types all have bit 2 set, so that they can be tested for easily. 1559 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1560 machine_function structure is initialized (to zero) func_type will 1561 default to unknown. This will force the first use of arm_current_func_type 1562 to call arm_compute_func_type. */ 1563 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1564 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1565 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1566 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1567 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1568 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1569 1570 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1571 1572 /* In addition functions can have several type modifiers, 1573 outlined by these bit masks: */ 1574 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1575 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1576 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1577 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1578 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1579 1580 /* Some macros to test these flags. */ 1581 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1582 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1583 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1584 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1585 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1586 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1587 1588 1589 /* Structure used to hold the function stack frame layout. Offsets are 1590 relative to the stack pointer on function entry. Positive offsets are 1591 in the direction of stack growth. 1592 Only soft_frame is used in thumb mode. */ 1593 1594 typedef struct GTY(()) arm_stack_offsets 1595 { 1596 int saved_args; /* ARG_POINTER_REGNUM. */ 1597 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1598 int saved_regs; 1599 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1600 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1601 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1602 unsigned int saved_regs_mask; 1603 } 1604 arm_stack_offsets; 1605 1606 /* A C structure for machine-specific, per-function data. 1607 This is added to the cfun structure. */ 1608 typedef struct GTY(()) machine_function 1609 { 1610 /* Additional stack adjustment in __builtin_eh_throw. */ 1611 rtx eh_epilogue_sp_ofs; 1612 /* Records if LR has to be saved for far jumps. */ 1613 int far_jump_used; 1614 /* Records if ARG_POINTER was ever live. */ 1615 int arg_pointer_live; 1616 /* Records if the save of LR has been eliminated. */ 1617 int lr_save_eliminated; 1618 /* The size of the stack frame. Only valid after reload. */ 1619 arm_stack_offsets stack_offsets; 1620 /* Records the type of the current function. */ 1621 unsigned long func_type; 1622 /* Record if the function has a variable argument list. */ 1623 int uses_anonymous_args; 1624 /* Records if sibcalls are blocked because an argument 1625 register is needed to preserve stack alignment. */ 1626 int sibcall_blocked; 1627 /* The PIC register for this function. This might be a pseudo. */ 1628 rtx pic_reg; 1629 /* Labels for per-function Thumb call-via stubs. One per potential calling 1630 register. We can never call via LR or PC. We can call via SP if a 1631 trampoline happens to be on the top of the stack. */ 1632 rtx call_via[14]; 1633 /* Set to 1 when a return insn is output, this means that the epilogue 1634 is not needed. */ 1635 int return_used_this_function; 1636 } 1637 machine_function; 1638 1639 /* As in the machine_function, a global set of call-via labels, for code 1640 that is in text_section. */ 1641 extern GTY(()) rtx thumb_call_via_label[14]; 1642 1643 /* The number of potential ways of assigning to a co-processor. */ 1644 #define ARM_NUM_COPROC_SLOTS 1 1645 1646 /* Enumeration of procedure calling standard variants. We don't really 1647 support all of these yet. */ 1648 enum arm_pcs 1649 { 1650 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1651 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1652 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1653 /* This must be the last AAPCS variant. */ 1654 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1655 ARM_PCS_ATPCS, /* ATPCS. */ 1656 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1657 ARM_PCS_UNKNOWN 1658 }; 1659 1660 /* A C type for declaring a variable that is used as the first argument of 1661 `FUNCTION_ARG' and other related values. */ 1662 typedef struct 1663 { 1664 /* This is the number of registers of arguments scanned so far. */ 1665 int nregs; 1666 /* This is the number of iWMMXt register arguments scanned so far. */ 1667 int iwmmxt_nregs; 1668 int named_count; 1669 int nargs; 1670 /* Which procedure call variant to use for this call. */ 1671 enum arm_pcs pcs_variant; 1672 1673 /* AAPCS related state tracking. */ 1674 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1675 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1676 this argument, or -1 if using core 1677 registers. */ 1678 int aapcs_ncrn; 1679 int aapcs_next_ncrn; 1680 rtx aapcs_reg; /* Register assigned to this argument. */ 1681 int aapcs_partial; /* How many bytes are passed in regs (if 1682 split between core regs and stack. 1683 Zero otherwise. */ 1684 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1685 int can_split; /* Argument can be split between core regs 1686 and the stack. */ 1687 /* Private data for tracking VFP register allocation */ 1688 unsigned aapcs_vfp_regs_free; 1689 unsigned aapcs_vfp_reg_alloc; 1690 int aapcs_vfp_rcount; 1691 MACHMODE aapcs_vfp_rmode; 1692 } CUMULATIVE_ARGS; 1693 1694 /* Define where to put the arguments to a function. 1695 Value is zero to push the argument on the stack, 1696 or a hard register in which to store the argument. 1697 1698 MODE is the argument's machine mode. 1699 TYPE is the data type of the argument (as a tree). 1700 This is null for libcalls where that information may 1701 not be available. 1702 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1703 the preceding args and about the function being called. 1704 NAMED is nonzero if this argument is a named parameter 1705 (otherwise it is an extra parameter matching an ellipsis). 1706 1707 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 1708 other arguments are passed on the stack. If (NAMED == 0) (which happens 1709 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is 1710 defined), say it is passed in the stack (function_prologue will 1711 indeed make it pass in the stack if necessary). */ 1712 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1713 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1714 1715 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1716 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1717 1718 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1719 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1720 1721 /* For AAPCS, padding should never be below the argument. For other ABIs, 1722 * mimic the default. */ 1723 #define PAD_VARARGS_DOWN \ 1724 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1725 1726 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1727 for a call to a function whose data type is FNTYPE. 1728 For a library call, FNTYPE is 0. 1729 On the ARM, the offset starts at 0. */ 1730 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1731 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1732 1733 /* Update the data in CUM to advance over an argument 1734 of mode MODE and data type TYPE. 1735 (TYPE is null for libcalls where that information may not be available.) */ 1736 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1737 arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1738 1739 /* If defined, a C expression that gives the alignment boundary, in bits, of an 1740 argument with the specified mode and type. If it is not defined, 1741 `PARM_BOUNDARY' is used for all arguments. */ 1742 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \ 1743 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \ 1744 ? DOUBLEWORD_ALIGNMENT \ 1745 : PARM_BOUNDARY ) 1746 1747 /* 1 if N is a possible register number for function argument passing. 1748 On the ARM, r0-r3 are used to pass args. */ 1749 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1750 (IN_RANGE ((REGNO), 0, 3) \ 1751 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1752 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1753 || (TARGET_IWMMXT_ABI \ 1754 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1755 1756 1757 /* If your target environment doesn't prefix user functions with an 1758 underscore, you may wish to re-define this to prevent any conflicts. */ 1759 #ifndef ARM_MCOUNT_NAME 1760 #define ARM_MCOUNT_NAME "*mcount" 1761 #endif 1762 1763 /* Call the function profiler with a given profile label. The Acorn 1764 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1765 On the ARM the full profile code will look like: 1766 .data 1767 LP1 1768 .word 0 1769 .text 1770 mov ip, lr 1771 bl mcount 1772 .word LP1 1773 1774 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1775 will output the .text section. 1776 1777 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1778 ``prof'' doesn't seem to mind about this! 1779 1780 Note - this version of the code is designed to work in both ARM and 1781 Thumb modes. */ 1782 #ifndef ARM_FUNCTION_PROFILER 1783 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1784 { \ 1785 char temp[20]; \ 1786 rtx sym; \ 1787 \ 1788 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1789 IP_REGNUM, LR_REGNUM); \ 1790 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1791 fputc ('\n', STREAM); \ 1792 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1793 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1794 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1795 } 1796 #endif 1797 1798 #ifdef THUMB_FUNCTION_PROFILER 1799 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1800 if (TARGET_ARM) \ 1801 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1802 else \ 1803 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1804 #else 1805 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1806 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1807 #endif 1808 1809 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1810 the stack pointer does not matter. The value is tested only in 1811 functions that have frame pointers. 1812 No definition is equivalent to always zero. 1813 1814 On the ARM, the function epilogue recovers the stack pointer from the 1815 frame. */ 1816 #define EXIT_IGNORE_STACK 1 1817 1818 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) 1819 1820 /* Determine if the epilogue should be output as RTL. 1821 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1822 /* This is disabled for Thumb-2 because it will confuse the 1823 conditional insn counter. */ 1824 #define USE_RETURN_INSN(ISCOND) \ 1825 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) 1826 1827 /* Definitions for register eliminations. 1828 1829 This is an array of structures. Each structure initializes one pair 1830 of eliminable registers. The "from" register number is given first, 1831 followed by "to". Eliminations of the same "from" register are listed 1832 in order of preference. 1833 1834 We have two registers that can be eliminated on the ARM. First, the 1835 arg pointer register can often be eliminated in favor of the stack 1836 pointer register. Secondly, the pseudo frame pointer register can always 1837 be eliminated; it is replaced with either the stack or the real frame 1838 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1839 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1840 1841 #define ELIMINABLE_REGS \ 1842 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1843 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1844 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1845 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1846 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1847 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1848 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1849 1850 /* Define the offset between two registers, one to be eliminated, and the 1851 other its replacement, at the start of a routine. */ 1852 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1853 if (TARGET_ARM) \ 1854 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1855 else \ 1856 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1857 1858 /* Special case handling of the location of arguments passed on the stack. */ 1859 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1860 1861 /* Initialize data used by insn expanders. This is called from insn_emit, 1862 once for every function before code is generated. */ 1863 #define INIT_EXPANDERS arm_init_expanders () 1864 1865 /* Length in units of the trampoline for entering a nested function. */ 1866 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1867 1868 /* Alignment required for a trampoline in bits. */ 1869 #define TRAMPOLINE_ALIGNMENT 32 1870 1871 /* Addressing modes, and classification of registers for them. */ 1872 #define HAVE_POST_INCREMENT 1 1873 #define HAVE_PRE_INCREMENT TARGET_32BIT 1874 #define HAVE_POST_DECREMENT TARGET_32BIT 1875 #define HAVE_PRE_DECREMENT TARGET_32BIT 1876 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1877 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1878 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1879 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1880 1881 /* Macros to check register numbers against specific register classes. */ 1882 1883 /* These assume that REGNO is a hard or pseudo reg number. 1884 They give nonzero only if REGNO is a hard reg of the suitable class 1885 or a pseudo reg currently allocated to a suitable hard reg. 1886 Since they use reg_renumber, they are safe only once reg_renumber 1887 has been allocated, which happens in local-alloc.c. */ 1888 #define TEST_REGNO(R, TEST, VALUE) \ 1889 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1890 1891 /* Don't allow the pc to be used. */ 1892 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1893 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1894 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1895 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1896 1897 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1898 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1899 || (GET_MODE_SIZE (MODE) >= 4 \ 1900 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1901 1902 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1903 (TARGET_THUMB1 \ 1904 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1905 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1906 1907 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1908 For Thumb, we can not use SP + reg, so reject SP. */ 1909 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1910 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1911 1912 /* For ARM code, we don't care about the mode, but for Thumb, the index 1913 must be suitable for use in a QImode load. */ 1914 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1915 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1916 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1917 1918 /* Maximum number of registers that can appear in a valid memory address. 1919 Shifts in addresses can't be by a register. */ 1920 #define MAX_REGS_PER_ADDRESS 2 1921 1922 /* Recognize any constant value that is a valid address. */ 1923 /* XXX We can address any constant, eventually... */ 1924 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1925 #define CONSTANT_ADDRESS_P(X) \ 1926 (GET_CODE (X) == SYMBOL_REF \ 1927 && (CONSTANT_POOL_ADDRESS_P (X) \ 1928 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1929 1930 /* True if SYMBOL + OFFSET constants must refer to something within 1931 SYMBOL's section. */ 1932 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1933 1934 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1935 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1936 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1937 #endif 1938 1939 /* Nonzero if the constant value X is a legitimate general operand. 1940 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1941 1942 On the ARM, allow any integer (invalid ones are removed later by insn 1943 patterns), nice doubles and symbol_refs which refer to the function's 1944 constant pool XXX. 1945 1946 When generating pic allow anything. */ 1947 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) 1948 1949 #define THUMB_LEGITIMATE_CONSTANT_P(X) \ 1950 ( GET_CODE (X) == CONST_INT \ 1951 || GET_CODE (X) == CONST_DOUBLE \ 1952 || CONSTANT_ADDRESS_P (X) \ 1953 || flag_pic) 1954 1955 #define LEGITIMATE_CONSTANT_P(X) \ 1956 (!arm_cannot_force_const_mem (X) \ 1957 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \ 1958 : THUMB_LEGITIMATE_CONSTANT_P (X))) 1959 1960 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1961 #define SUBTARGET_NAME_ENCODING_LENGTHS 1962 #endif 1963 1964 /* This is a C fragment for the inside of a switch statement. 1965 Each case label should return the number of characters to 1966 be stripped from the start of a function's name, if that 1967 name starts with the indicated character. */ 1968 #define ARM_NAME_ENCODING_LENGTHS \ 1969 case '*': return 1; \ 1970 SUBTARGET_NAME_ENCODING_LENGTHS 1971 1972 /* This is how to output a reference to a user-level label named NAME. 1973 `assemble_name' uses this. */ 1974 #undef ASM_OUTPUT_LABELREF 1975 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1976 arm_asm_output_labelref (FILE, NAME) 1977 1978 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1979 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1980 if (TARGET_THUMB2) \ 1981 thumb2_asm_output_opcode (STREAM); 1982 1983 /* The EABI specifies that constructors should go in .init_array. 1984 Other targets use .ctors for compatibility. */ 1985 #ifndef ARM_EABI_CTORS_SECTION_OP 1986 #define ARM_EABI_CTORS_SECTION_OP \ 1987 "\t.section\t.init_array,\"aw\",%init_array" 1988 #endif 1989 #ifndef ARM_EABI_DTORS_SECTION_OP 1990 #define ARM_EABI_DTORS_SECTION_OP \ 1991 "\t.section\t.fini_array,\"aw\",%fini_array" 1992 #endif 1993 #define ARM_CTORS_SECTION_OP \ 1994 "\t.section\t.ctors,\"aw\",%progbits" 1995 #define ARM_DTORS_SECTION_OP \ 1996 "\t.section\t.dtors,\"aw\",%progbits" 1997 1998 /* Define CTORS_SECTION_ASM_OP. */ 1999 #undef CTORS_SECTION_ASM_OP 2000 #undef DTORS_SECTION_ASM_OP 2001 #ifndef IN_LIBGCC2 2002 # define CTORS_SECTION_ASM_OP \ 2003 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 2004 # define DTORS_SECTION_ASM_OP \ 2005 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 2006 #else /* !defined (IN_LIBGCC2) */ 2007 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 2008 so we cannot use the definition above. */ 2009 # ifdef __ARM_EABI__ 2010 /* The .ctors section is not part of the EABI, so we do not define 2011 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 2012 from trying to use it. We do define it when doing normal 2013 compilation, as .init_array can be used instead of .ctors. */ 2014 /* There is no need to emit begin or end markers when using 2015 init_array; the dynamic linker will compute the size of the 2016 array itself based on special symbols created by the static 2017 linker. However, we do need to arrange to set up 2018 exception-handling here. */ 2019 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 2020 # define CTOR_LIST_END /* empty */ 2021 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 2022 # define DTOR_LIST_END /* empty */ 2023 # else /* !defined (__ARM_EABI__) */ 2024 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 2025 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 2026 # endif /* !defined (__ARM_EABI__) */ 2027 #endif /* !defined (IN_LIBCC2) */ 2028 2029 /* True if the operating system can merge entities with vague linkage 2030 (e.g., symbols in COMDAT group) during dynamic linking. */ 2031 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 2032 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 2033 #endif 2034 2035 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 2036 2037 #ifdef TARGET_UNWIND_INFO 2038 #define ARM_EABI_UNWIND_TABLES \ 2039 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables) 2040 #else 2041 #define ARM_EABI_UNWIND_TABLES 0 2042 #endif 2043 2044 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2045 and check its validity for a certain class. 2046 We have two alternate definitions for each of them. 2047 The usual definition accepts all pseudo regs; the other rejects 2048 them unless they have been allocated suitable hard regs. 2049 The symbol REG_OK_STRICT causes the latter definition to be used. 2050 Thumb-2 has the same restrictions as arm. */ 2051 #ifndef REG_OK_STRICT 2052 2053 #define ARM_REG_OK_FOR_BASE_P(X) \ 2054 (REGNO (X) <= LAST_ARM_REGNUM \ 2055 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2056 || REGNO (X) == FRAME_POINTER_REGNUM \ 2057 || REGNO (X) == ARG_POINTER_REGNUM) 2058 2059 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2060 ((REGNO (X) <= LAST_ARM_REGNUM \ 2061 && REGNO (X) != STACK_POINTER_REGNUM) \ 2062 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2063 || REGNO (X) == FRAME_POINTER_REGNUM \ 2064 || REGNO (X) == ARG_POINTER_REGNUM) 2065 2066 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2067 (REGNO (X) <= LAST_LO_REGNUM \ 2068 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2069 || (GET_MODE_SIZE (MODE) >= 4 \ 2070 && (REGNO (X) == STACK_POINTER_REGNUM \ 2071 || (X) == hard_frame_pointer_rtx \ 2072 || (X) == arg_pointer_rtx))) 2073 2074 #define REG_STRICT_P 0 2075 2076 #else /* REG_OK_STRICT */ 2077 2078 #define ARM_REG_OK_FOR_BASE_P(X) \ 2079 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 2080 2081 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2082 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 2083 2084 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2085 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 2086 2087 #define REG_STRICT_P 1 2088 2089 #endif /* REG_OK_STRICT */ 2090 2091 /* Now define some helpers in terms of the above. */ 2092 2093 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2094 (TARGET_THUMB1 \ 2095 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2096 : ARM_REG_OK_FOR_BASE_P (X)) 2097 2098 /* For 16-bit Thumb, a valid index register is anything that can be used in 2099 a byte load instruction. */ 2100 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2101 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2102 2103 /* Nonzero if X is a hard reg that can be used as an index 2104 or if it is a pseudo reg. On the Thumb, the stack pointer 2105 is not suitable. */ 2106 #define REG_OK_FOR_INDEX_P(X) \ 2107 (TARGET_THUMB1 \ 2108 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2109 : ARM_REG_OK_FOR_INDEX_P (X)) 2110 2111 /* Nonzero if X can be the base register in a reg+reg addressing mode. 2112 For Thumb, we can not use SP + reg, so reject SP. */ 2113 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2114 REG_OK_FOR_INDEX_P (X) 2115 2116 #define ARM_BASE_REGISTER_RTX_P(X) \ 2117 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) 2118 2119 #define ARM_INDEX_REGISTER_RTX_P(X) \ 2120 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) 2121 2122 /* Define this for compatibility reasons. */ 2123 #define HANDLE_PRAGMA_PACK_PUSH_POP 1 2124 2125 /* Specify the machine mode that this machine uses 2126 for the index in the tablejump instruction. */ 2127 #define CASE_VECTOR_MODE Pmode 2128 2129 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 2130 || (TARGET_THUMB1 \ 2131 && (optimize_size || flag_pic))) 2132 2133 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2134 (TARGET_THUMB1 \ 2135 ? (min >= 0 && max < 512 \ 2136 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2137 : min >= -256 && max < 256 \ 2138 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2139 : min >= 0 && max < 8192 \ 2140 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2141 : min >= -4096 && max < 4096 \ 2142 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2143 : SImode) \ 2144 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \ 2145 : (max >= 0x200) ? HImode \ 2146 : QImode)) 2147 2148 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2149 unsigned is probably best, but may break some code. */ 2150 #ifndef DEFAULT_SIGNED_CHAR 2151 #define DEFAULT_SIGNED_CHAR 0 2152 #endif 2153 2154 /* Max number of bytes we can move from memory to memory 2155 in one reasonably fast instruction. */ 2156 #define MOVE_MAX 4 2157 2158 #undef MOVE_RATIO 2159 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2160 2161 /* Define if operations between registers always perform the operation 2162 on the full register even if a narrower mode is specified. */ 2163 #define WORD_REGISTER_OPERATIONS 2164 2165 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2166 will either zero-extend or sign-extend. The value of this macro should 2167 be the code that says which one of the two operations is implicitly 2168 done, UNKNOWN if none. */ 2169 #define LOAD_EXTEND_OP(MODE) \ 2170 (TARGET_THUMB ? ZERO_EXTEND : \ 2171 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2172 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2173 2174 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2175 #define SLOW_BYTE_ACCESS 0 2176 2177 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2178 2179 /* Immediate shift counts are truncated by the output routines (or was it 2180 the assembler?). Shift counts in a register are truncated by ARM. Note 2181 that the native compiler puts too large (> 32) immediate shift counts 2182 into a register and shifts by the register, letting the ARM decide what 2183 to do instead of doing that itself. */ 2184 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2185 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2186 On the arm, Y in a register is used modulo 256 for the shift. Only for 2187 rotates is modulo 32 used. */ 2188 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2189 2190 /* All integers have the same format so truncation is easy. */ 2191 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2192 2193 /* Calling from registers is a massive pain. */ 2194 #define NO_FUNCTION_CSE 1 2195 2196 /* The machine modes of pointers and functions */ 2197 #define Pmode SImode 2198 #define FUNCTION_MODE Pmode 2199 2200 #define ARM_FRAME_RTX(X) \ 2201 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2202 || (X) == arg_pointer_rtx) 2203 2204 /* Moves to and from memory are quite expensive */ 2205 #define MEMORY_MOVE_COST(M, CLASS, IN) \ 2206 (TARGET_32BIT ? 10 : \ 2207 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ 2208 * (CLASS == LO_REGS ? 1 : 2))) 2209 2210 /* Try to generate sequences that don't involve branches, we can then use 2211 conditional instructions */ 2212 #define BRANCH_COST(speed_p, predictable_p) \ 2213 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) 2214 2215 /* Position Independent Code. */ 2216 /* We decide which register to use based on the compilation options and 2217 the assembler in use; this is more general than the APCS restriction of 2218 using sb (r9) all the time. */ 2219 extern unsigned arm_pic_register; 2220 2221 /* The register number of the register used to address a table of static 2222 data addresses in memory. */ 2223 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2224 2225 /* We can't directly access anything that contains a symbol, 2226 nor can we indirect via the constant pool. One exception is 2227 UNSPEC_TLS, which is always PIC. */ 2228 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2229 (!(symbol_mentioned_p (X) \ 2230 || label_mentioned_p (X) \ 2231 || (GET_CODE (X) == SYMBOL_REF \ 2232 && CONSTANT_POOL_ADDRESS_P (X) \ 2233 && (symbol_mentioned_p (get_pool_constant (X)) \ 2234 || label_mentioned_p (get_pool_constant (X))))) \ 2235 || tls_mentioned_p (X)) 2236 2237 /* We need to know when we are making a constant pool; this determines 2238 whether data needs to be in the GOT or can be referenced via a GOT 2239 offset. */ 2240 extern int making_const_table; 2241 2242 /* Handle pragmas for compatibility with Intel's compilers. */ 2243 /* Also abuse this to register additional C specific EABI attributes. */ 2244 #define REGISTER_TARGET_PRAGMAS() do { \ 2245 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2246 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2247 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2248 arm_lang_object_attributes_init(); \ 2249 } while (0) 2250 2251 /* Condition code information. */ 2252 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2253 return the mode to be used for the comparison. */ 2254 2255 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2256 2257 #define REVERSIBLE_CC_MODE(MODE) 1 2258 2259 #define REVERSE_CONDITION(CODE,MODE) \ 2260 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2261 ? reverse_condition_maybe_unordered (code) \ 2262 : reverse_condition (code)) 2263 2264 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 2265 do \ 2266 { \ 2267 if (GET_CODE (OP1) == CONST_INT \ 2268 && ! (const_ok_for_arm (INTVAL (OP1)) \ 2269 || (const_ok_for_arm (- INTVAL (OP1))))) \ 2270 { \ 2271 rtx const_op = OP1; \ 2272 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \ 2273 &const_op); \ 2274 OP1 = const_op; \ 2275 } \ 2276 } \ 2277 while (0) 2278 2279 /* The arm5 clz instruction returns 32. */ 2280 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2281 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2282 2283 #undef ASM_APP_OFF 2284 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ 2285 TARGET_THUMB2 ? "\t.thumb\n" : "") 2286 2287 /* Output a push or a pop instruction (only used when profiling). 2288 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2289 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2290 that r7 isn't used by the function profiler, so we can use it as a 2291 scratch reg. WARNING: This isn't safe in the general case! It may be 2292 sensitive to future changes in final.c:profile_function. */ 2293 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2294 do \ 2295 { \ 2296 if (TARGET_ARM) \ 2297 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2298 STACK_POINTER_REGNUM, REGNO); \ 2299 else if (TARGET_THUMB1 \ 2300 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2301 { \ 2302 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2303 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2304 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2305 } \ 2306 else \ 2307 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2308 } while (0) 2309 2310 2311 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2312 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2313 do \ 2314 { \ 2315 if (TARGET_ARM) \ 2316 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2317 STACK_POINTER_REGNUM, REGNO); \ 2318 else if (TARGET_THUMB1 \ 2319 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2320 { \ 2321 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2322 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2323 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2324 } \ 2325 else \ 2326 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2327 } while (0) 2328 2329 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 2330 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 2331 2332 /* This is how to output a label which precedes a jumptable. Since 2333 Thumb instructions are 2 bytes, we may need explicit alignment here. */ 2334 #undef ASM_OUTPUT_CASE_LABEL 2335 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 2336 do \ 2337 { \ 2338 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \ 2339 ASM_OUTPUT_ALIGN (FILE, 2); \ 2340 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ 2341 } \ 2342 while (0) 2343 2344 /* Make sure subsequent insns are aligned after a TBB. */ 2345 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ 2346 do \ 2347 { \ 2348 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ 2349 ASM_OUTPUT_ALIGN (FILE, 1); \ 2350 } \ 2351 while (0) 2352 2353 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2354 do \ 2355 { \ 2356 if (TARGET_THUMB) \ 2357 { \ 2358 if (is_called_in_ARM_mode (DECL) \ 2359 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2360 && cfun->is_thunk)) \ 2361 fprintf (STREAM, "\t.code 32\n") ; \ 2362 else if (TARGET_THUMB1) \ 2363 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2364 else \ 2365 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2366 } \ 2367 if (TARGET_POKE_FUNCTION_NAME) \ 2368 arm_poke_function_name (STREAM, (const char *) NAME); \ 2369 } \ 2370 while (0) 2371 2372 /* For aliases of functions we use .thumb_set instead. */ 2373 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2374 do \ 2375 { \ 2376 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2377 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2378 \ 2379 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2380 { \ 2381 fprintf (FILE, "\t.thumb_set "); \ 2382 assemble_name (FILE, LABEL1); \ 2383 fprintf (FILE, ","); \ 2384 assemble_name (FILE, LABEL2); \ 2385 fprintf (FILE, "\n"); \ 2386 } \ 2387 else \ 2388 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2389 } \ 2390 while (0) 2391 2392 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2393 /* To support -falign-* switches we need to use .p2align so 2394 that alignment directives in code sections will be padded 2395 with no-op instructions, rather than zeroes. */ 2396 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2397 if ((LOG) != 0) \ 2398 { \ 2399 if ((MAX_SKIP) == 0) \ 2400 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2401 else \ 2402 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2403 (int) (LOG), (int) (MAX_SKIP)); \ 2404 } 2405 #endif 2406 2407 /* Add two bytes to the length of conditionally executed Thumb-2 2408 instructions for the IT instruction. */ 2409 #define ADJUST_INSN_LENGTH(insn, length) \ 2410 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2411 length += 2; 2412 2413 /* Only perform branch elimination (by making instructions conditional) if 2414 we're optimizing. For Thumb-2 check if any IT instructions need 2415 outputting. */ 2416 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2417 if (TARGET_ARM && optimize) \ 2418 arm_final_prescan_insn (INSN); \ 2419 else if (TARGET_THUMB2) \ 2420 thumb2_final_prescan_insn (INSN); \ 2421 else if (TARGET_THUMB1) \ 2422 thumb1_final_prescan_insn (INSN) 2423 2424 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2425 (CODE == '@' || CODE == '|' || CODE == '.' \ 2426 || CODE == '(' || CODE == ')' || CODE == '#' \ 2427 || (TARGET_32BIT && (CODE == '?')) \ 2428 || (TARGET_THUMB2 && (CODE == '!')) \ 2429 || (TARGET_THUMB && (CODE == '_'))) 2430 2431 /* Output an operand of an instruction. */ 2432 #define PRINT_OPERAND(STREAM, X, CODE) \ 2433 arm_print_operand (STREAM, X, CODE) 2434 2435 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2436 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2437 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2438 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2439 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2440 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2441 : 0)))) 2442 2443 /* Output the address of an operand. */ 2444 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2445 { \ 2446 int is_minus = GET_CODE (X) == MINUS; \ 2447 \ 2448 if (GET_CODE (X) == REG) \ 2449 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ 2450 else if (GET_CODE (X) == PLUS || is_minus) \ 2451 { \ 2452 rtx base = XEXP (X, 0); \ 2453 rtx index = XEXP (X, 1); \ 2454 HOST_WIDE_INT offset = 0; \ 2455 if (GET_CODE (base) != REG \ 2456 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \ 2457 { \ 2458 /* Ensure that BASE is a register. */ \ 2459 /* (one of them must be). */ \ 2460 /* Also ensure the SP is not used as in index register. */ \ 2461 rtx temp = base; \ 2462 base = index; \ 2463 index = temp; \ 2464 } \ 2465 switch (GET_CODE (index)) \ 2466 { \ 2467 case CONST_INT: \ 2468 offset = INTVAL (index); \ 2469 if (is_minus) \ 2470 offset = -offset; \ 2471 asm_fprintf (STREAM, "[%r, #%wd]", \ 2472 REGNO (base), offset); \ 2473 break; \ 2474 \ 2475 case REG: \ 2476 asm_fprintf (STREAM, "[%r, %s%r]", \ 2477 REGNO (base), is_minus ? "-" : "", \ 2478 REGNO (index)); \ 2479 break; \ 2480 \ 2481 case MULT: \ 2482 case ASHIFTRT: \ 2483 case LSHIFTRT: \ 2484 case ASHIFT: \ 2485 case ROTATERT: \ 2486 { \ 2487 asm_fprintf (STREAM, "[%r, %s%r", \ 2488 REGNO (base), is_minus ? "-" : "", \ 2489 REGNO (XEXP (index, 0))); \ 2490 arm_print_operand (STREAM, index, 'S'); \ 2491 fputs ("]", STREAM); \ 2492 break; \ 2493 } \ 2494 \ 2495 default: \ 2496 gcc_unreachable (); \ 2497 } \ 2498 } \ 2499 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ 2500 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ 2501 { \ 2502 extern enum machine_mode output_memory_reference_mode; \ 2503 \ 2504 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ 2505 \ 2506 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 2507 asm_fprintf (STREAM, "[%r, #%s%d]!", \ 2508 REGNO (XEXP (X, 0)), \ 2509 GET_CODE (X) == PRE_DEC ? "-" : "", \ 2510 GET_MODE_SIZE (output_memory_reference_mode)); \ 2511 else \ 2512 asm_fprintf (STREAM, "[%r], #%s%d", \ 2513 REGNO (XEXP (X, 0)), \ 2514 GET_CODE (X) == POST_DEC ? "-" : "", \ 2515 GET_MODE_SIZE (output_memory_reference_mode)); \ 2516 } \ 2517 else if (GET_CODE (X) == PRE_MODIFY) \ 2518 { \ 2519 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \ 2520 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2521 asm_fprintf (STREAM, "#%wd]!", \ 2522 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2523 else \ 2524 asm_fprintf (STREAM, "%r]!", \ 2525 REGNO (XEXP (XEXP (X, 1), 1))); \ 2526 } \ 2527 else if (GET_CODE (X) == POST_MODIFY) \ 2528 { \ 2529 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \ 2530 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2531 asm_fprintf (STREAM, "#%wd", \ 2532 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2533 else \ 2534 asm_fprintf (STREAM, "%r", \ 2535 REGNO (XEXP (XEXP (X, 1), 1))); \ 2536 } \ 2537 else output_addr_const (STREAM, X); \ 2538 } 2539 2540 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2541 { \ 2542 if (GET_CODE (X) == REG) \ 2543 asm_fprintf (STREAM, "[%r]", REGNO (X)); \ 2544 else if (GET_CODE (X) == POST_INC) \ 2545 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ 2546 else if (GET_CODE (X) == PLUS) \ 2547 { \ 2548 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ 2549 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2550 asm_fprintf (STREAM, "[%r, #%wd]", \ 2551 REGNO (XEXP (X, 0)), \ 2552 INTVAL (XEXP (X, 1))); \ 2553 else \ 2554 asm_fprintf (STREAM, "[%r, %r]", \ 2555 REGNO (XEXP (X, 0)), \ 2556 REGNO (XEXP (X, 1))); \ 2557 } \ 2558 else \ 2559 output_addr_const (STREAM, X); \ 2560 } 2561 2562 #define PRINT_OPERAND_ADDRESS(STREAM, X) \ 2563 if (TARGET_32BIT) \ 2564 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ 2565 else \ 2566 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) 2567 2568 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \ 2569 if (arm_output_addr_const_extra (file, x) == FALSE) \ 2570 goto fail 2571 2572 /* A C expression whose value is RTL representing the value of the return 2573 address for the frame COUNT steps up from the current frame. */ 2574 2575 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2576 arm_return_addr (COUNT, FRAME) 2577 2578 /* Mask of the bits in the PC that contain the real return address 2579 when running in 26-bit mode. */ 2580 #define RETURN_ADDR_MASK26 (0x03fffffc) 2581 2582 /* Pick up the return address upon entry to a procedure. Used for 2583 dwarf2 unwind information. This also enables the table driven 2584 mechanism. */ 2585 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2586 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2587 2588 /* Used to mask out junk bits from the return address, such as 2589 processor state, interrupt status, condition codes and the like. */ 2590 #define MASK_RETURN_ADDR \ 2591 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2592 in 26 bit mode, the condition codes must be masked out of the \ 2593 return address. This does not apply to ARM6 and later processors \ 2594 when running in 32 bit mode. */ \ 2595 ((arm_arch4 || TARGET_THUMB) \ 2596 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2597 : arm_gen_return_addr_mask ()) 2598 2599 2600 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have 2601 symbolic names defined here (which would require too much duplication). 2602 FIXME? */ 2603 enum arm_builtins 2604 { 2605 ARM_BUILTIN_GETWCX, 2606 ARM_BUILTIN_SETWCX, 2607 2608 ARM_BUILTIN_WZERO, 2609 2610 ARM_BUILTIN_WAVG2BR, 2611 ARM_BUILTIN_WAVG2HR, 2612 ARM_BUILTIN_WAVG2B, 2613 ARM_BUILTIN_WAVG2H, 2614 2615 ARM_BUILTIN_WACCB, 2616 ARM_BUILTIN_WACCH, 2617 ARM_BUILTIN_WACCW, 2618 2619 ARM_BUILTIN_WMACS, 2620 ARM_BUILTIN_WMACSZ, 2621 ARM_BUILTIN_WMACU, 2622 ARM_BUILTIN_WMACUZ, 2623 2624 ARM_BUILTIN_WSADB, 2625 ARM_BUILTIN_WSADBZ, 2626 ARM_BUILTIN_WSADH, 2627 ARM_BUILTIN_WSADHZ, 2628 2629 ARM_BUILTIN_WALIGN, 2630 2631 ARM_BUILTIN_TMIA, 2632 ARM_BUILTIN_TMIAPH, 2633 ARM_BUILTIN_TMIABB, 2634 ARM_BUILTIN_TMIABT, 2635 ARM_BUILTIN_TMIATB, 2636 ARM_BUILTIN_TMIATT, 2637 2638 ARM_BUILTIN_TMOVMSKB, 2639 ARM_BUILTIN_TMOVMSKH, 2640 ARM_BUILTIN_TMOVMSKW, 2641 2642 ARM_BUILTIN_TBCSTB, 2643 ARM_BUILTIN_TBCSTH, 2644 ARM_BUILTIN_TBCSTW, 2645 2646 ARM_BUILTIN_WMADDS, 2647 ARM_BUILTIN_WMADDU, 2648 2649 ARM_BUILTIN_WPACKHSS, 2650 ARM_BUILTIN_WPACKWSS, 2651 ARM_BUILTIN_WPACKDSS, 2652 ARM_BUILTIN_WPACKHUS, 2653 ARM_BUILTIN_WPACKWUS, 2654 ARM_BUILTIN_WPACKDUS, 2655 2656 ARM_BUILTIN_WADDB, 2657 ARM_BUILTIN_WADDH, 2658 ARM_BUILTIN_WADDW, 2659 ARM_BUILTIN_WADDSSB, 2660 ARM_BUILTIN_WADDSSH, 2661 ARM_BUILTIN_WADDSSW, 2662 ARM_BUILTIN_WADDUSB, 2663 ARM_BUILTIN_WADDUSH, 2664 ARM_BUILTIN_WADDUSW, 2665 ARM_BUILTIN_WSUBB, 2666 ARM_BUILTIN_WSUBH, 2667 ARM_BUILTIN_WSUBW, 2668 ARM_BUILTIN_WSUBSSB, 2669 ARM_BUILTIN_WSUBSSH, 2670 ARM_BUILTIN_WSUBSSW, 2671 ARM_BUILTIN_WSUBUSB, 2672 ARM_BUILTIN_WSUBUSH, 2673 ARM_BUILTIN_WSUBUSW, 2674 2675 ARM_BUILTIN_WAND, 2676 ARM_BUILTIN_WANDN, 2677 ARM_BUILTIN_WOR, 2678 ARM_BUILTIN_WXOR, 2679 2680 ARM_BUILTIN_WCMPEQB, 2681 ARM_BUILTIN_WCMPEQH, 2682 ARM_BUILTIN_WCMPEQW, 2683 ARM_BUILTIN_WCMPGTUB, 2684 ARM_BUILTIN_WCMPGTUH, 2685 ARM_BUILTIN_WCMPGTUW, 2686 ARM_BUILTIN_WCMPGTSB, 2687 ARM_BUILTIN_WCMPGTSH, 2688 ARM_BUILTIN_WCMPGTSW, 2689 2690 ARM_BUILTIN_TEXTRMSB, 2691 ARM_BUILTIN_TEXTRMSH, 2692 ARM_BUILTIN_TEXTRMSW, 2693 ARM_BUILTIN_TEXTRMUB, 2694 ARM_BUILTIN_TEXTRMUH, 2695 ARM_BUILTIN_TEXTRMUW, 2696 ARM_BUILTIN_TINSRB, 2697 ARM_BUILTIN_TINSRH, 2698 ARM_BUILTIN_TINSRW, 2699 2700 ARM_BUILTIN_WMAXSW, 2701 ARM_BUILTIN_WMAXSH, 2702 ARM_BUILTIN_WMAXSB, 2703 ARM_BUILTIN_WMAXUW, 2704 ARM_BUILTIN_WMAXUH, 2705 ARM_BUILTIN_WMAXUB, 2706 ARM_BUILTIN_WMINSW, 2707 ARM_BUILTIN_WMINSH, 2708 ARM_BUILTIN_WMINSB, 2709 ARM_BUILTIN_WMINUW, 2710 ARM_BUILTIN_WMINUH, 2711 ARM_BUILTIN_WMINUB, 2712 2713 ARM_BUILTIN_WMULUM, 2714 ARM_BUILTIN_WMULSM, 2715 ARM_BUILTIN_WMULUL, 2716 2717 ARM_BUILTIN_PSADBH, 2718 ARM_BUILTIN_WSHUFH, 2719 2720 ARM_BUILTIN_WSLLH, 2721 ARM_BUILTIN_WSLLW, 2722 ARM_BUILTIN_WSLLD, 2723 ARM_BUILTIN_WSRAH, 2724 ARM_BUILTIN_WSRAW, 2725 ARM_BUILTIN_WSRAD, 2726 ARM_BUILTIN_WSRLH, 2727 ARM_BUILTIN_WSRLW, 2728 ARM_BUILTIN_WSRLD, 2729 ARM_BUILTIN_WRORH, 2730 ARM_BUILTIN_WRORW, 2731 ARM_BUILTIN_WRORD, 2732 ARM_BUILTIN_WSLLHI, 2733 ARM_BUILTIN_WSLLWI, 2734 ARM_BUILTIN_WSLLDI, 2735 ARM_BUILTIN_WSRAHI, 2736 ARM_BUILTIN_WSRAWI, 2737 ARM_BUILTIN_WSRADI, 2738 ARM_BUILTIN_WSRLHI, 2739 ARM_BUILTIN_WSRLWI, 2740 ARM_BUILTIN_WSRLDI, 2741 ARM_BUILTIN_WRORHI, 2742 ARM_BUILTIN_WRORWI, 2743 ARM_BUILTIN_WRORDI, 2744 2745 ARM_BUILTIN_WUNPCKIHB, 2746 ARM_BUILTIN_WUNPCKIHH, 2747 ARM_BUILTIN_WUNPCKIHW, 2748 ARM_BUILTIN_WUNPCKILB, 2749 ARM_BUILTIN_WUNPCKILH, 2750 ARM_BUILTIN_WUNPCKILW, 2751 2752 ARM_BUILTIN_WUNPCKEHSB, 2753 ARM_BUILTIN_WUNPCKEHSH, 2754 ARM_BUILTIN_WUNPCKEHSW, 2755 ARM_BUILTIN_WUNPCKEHUB, 2756 ARM_BUILTIN_WUNPCKEHUH, 2757 ARM_BUILTIN_WUNPCKEHUW, 2758 ARM_BUILTIN_WUNPCKELSB, 2759 ARM_BUILTIN_WUNPCKELSH, 2760 ARM_BUILTIN_WUNPCKELSW, 2761 ARM_BUILTIN_WUNPCKELUB, 2762 ARM_BUILTIN_WUNPCKELUH, 2763 ARM_BUILTIN_WUNPCKELUW, 2764 2765 ARM_BUILTIN_THREAD_POINTER, 2766 2767 ARM_BUILTIN_NEON_BASE, 2768 2769 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */ 2770 }; 2771 2772 /* Do not emit .note.GNU-stack by default. */ 2773 #ifndef NEED_INDICATE_EXEC_STACK 2774 #define NEED_INDICATE_EXEC_STACK 0 2775 #endif 2776 2777 #endif /* ! GCC_ARM_H */ 2778