1 /* Functions and structures shared between arm and aarch64. 2 3 Copyright (C) 1991-2015 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 3, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 23 #ifndef GCC_AARCH_COMMON_PROTOS_H 24 #define GCC_AARCH_COMMON_PROTOS_H 25 26 extern int aarch_crypto_can_dual_issue (rtx_insn *, rtx_insn *); 27 extern bool aarch_rev16_p (rtx); 28 extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode); 29 extern bool aarch_rev16_shright_mask_imm_p (rtx, machine_mode); 30 extern int arm_early_load_addr_dep (rtx, rtx); 31 extern int arm_early_store_addr_dep (rtx, rtx); 32 extern int arm_mac_accumulator_is_mul_result (rtx, rtx); 33 extern int arm_mac_accumulator_is_result (rtx, rtx); 34 extern int arm_no_early_alu_shift_dep (rtx, rtx); 35 extern int arm_no_early_alu_shift_value_dep (rtx, rtx); 36 extern int arm_no_early_mul_dep (rtx, rtx); 37 extern int arm_no_early_store_addr_dep (rtx, rtx); 38 extern bool arm_rtx_shift_left_p (rtx); 39 40 /* RTX cost table definitions. These are used when tuning for speed rather 41 than for size and should reflect the _additional_ cost over the cost 42 of the fastest instruction in the machine, which is COSTS_N_INSNS (1). 43 Therefore it's okay for some costs to be 0. 44 Costs may not have a negative value. */ 45 struct alu_cost_table 46 { 47 const int arith; /* ADD/SUB. */ 48 const int logical; /* AND/ORR/EOR/BIC, etc. */ 49 const int shift; /* Simple shift. */ 50 const int shift_reg; /* Simple shift by reg. */ 51 const int arith_shift; /* Additional when arith also shifts... */ 52 const int arith_shift_reg; /* ... and when the shift is by a reg. */ 53 const int log_shift; /* Additional when logic also shifts... */ 54 const int log_shift_reg; /* ... and when the shift is by a reg. */ 55 const int extend; /* Zero/sign extension. */ 56 const int extend_arith; /* Extend and arith. */ 57 const int bfi; /* Bit-field insert. */ 58 const int bfx; /* Bit-field extraction. */ 59 const int clz; /* Count Leading Zeros. */ 60 const int rev; /* Reverse bits/bytes. */ 61 const int non_exec; /* Extra cost when not executing insn. */ 62 const bool non_exec_costs_exec; /* True if non-execution must add the exec 63 cost. */ 64 }; 65 66 struct mult_cost_table 67 { 68 const int simple; 69 const int flag_setting; /* Additional cost if multiply sets flags. */ 70 const int extend; 71 const int add; 72 const int extend_add; 73 const int idiv; 74 }; 75 76 /* Calculations of LDM costs are complex. We assume an initial cost 77 (ldm_1st) which will load the number of registers mentioned in 78 ldm_regs_per_insn_1st registers; then each additional 79 ldm_regs_per_insn_subsequent registers cost one more insn. 80 Similarly for STM operations. 81 Therefore the ldm_regs_per_insn_1st/stm_regs_per_insn_1st and 82 ldm_regs_per_insn_subsequent/stm_regs_per_insn_subsequent fields indicate 83 the number of registers loaded/stored and are expressed by a simple integer 84 and not by a COSTS_N_INSNS (N) expression. 85 */ 86 struct mem_cost_table 87 { 88 const int load; 89 const int load_sign_extend; /* Additional to load cost. */ 90 const int ldrd; /* Cost of LDRD. */ 91 const int ldm_1st; 92 const int ldm_regs_per_insn_1st; 93 const int ldm_regs_per_insn_subsequent; 94 const int loadf; /* SFmode. */ 95 const int loadd; /* DFmode. */ 96 const int load_unaligned; /* Extra for unaligned loads. */ 97 const int store; 98 const int strd; 99 const int stm_1st; 100 const int stm_regs_per_insn_1st; 101 const int stm_regs_per_insn_subsequent; 102 const int storef; /* SFmode. */ 103 const int stored; /* DFmode. */ 104 const int store_unaligned; /* Extra for unaligned stores. */ 105 }; 106 107 struct fp_cost_table 108 { 109 const int div; 110 const int mult; 111 const int mult_addsub; /* Non-fused. */ 112 const int fma; /* Fused. */ 113 const int addsub; 114 const int fpconst; /* Immediate. */ 115 const int neg; /* NEG and ABS. */ 116 const int compare; 117 const int widen; /* Widen to this size. */ 118 const int narrow; /* Narrow from this size. */ 119 const int toint; 120 const int fromint; 121 const int roundint; /* V8 round to integral, remains FP format. */ 122 }; 123 124 struct vector_cost_table 125 { 126 const int alu; 127 }; 128 129 struct cpu_cost_table 130 { 131 const struct alu_cost_table alu; 132 const struct mult_cost_table mult[2]; /* SImode and DImode. */ 133 const struct mem_cost_table ldst; 134 const struct fp_cost_table fp[2]; /* SFmode and DFmode. */ 135 const struct vector_cost_table vect; 136 }; 137 138 139 #endif /* GCC_AARCH_COMMON_PROTOS_H */ 140