1; Options for the Synopsys DesignWare ARC port of the compiler 2; 3; Copyright (C) 2005-2015 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 3, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT 13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15; License for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING3. If not see 19; <http://www.gnu.org/licenses/>. 20 21HeaderInclude 22config/arc/arc-opts.h 23 24mbig-endian 25Target Report RejectNegative Mask(BIG_ENDIAN) 26Compile code for big endian mode 27 28mlittle-endian 29Target Report RejectNegative InverseMask(BIG_ENDIAN) 30Compile code for little endian mode. This is the default 31 32mno-cond-exec 33Target Report RejectNegative Mask(NO_COND_EXEC) 34Disable ARCompact specific pass to generate conditional execution instructions 35 36mA5 37Target Report 38Generate ARCompact 32-bit code for ARCtangent-A5 processor 39 40mA6 41Target Report 42Generate ARCompact 32-bit code for ARC600 processor 43 44mARC600 45Target Report 46Same as -mA6 47 48mARC601 49Target Report 50Generate ARCompact 32-bit code for ARC601 processor 51 52mA7 53Target Report 54Generate ARCompact 32-bit code for ARC700 processor 55 56mARC700 57Target Report 58Same as -mA7 59 60mmixed-code 61Target Report Mask(MIXED_CODE_SET) 62Tweak register allocation to help 16-bit instruction generation 63; originally this was: 64;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions for ARCtangent-A5 and higher processors 65; but we do that without -mmixed-code, too, it's just a different instruction 66; count / size tradeoff. 67 68; We use an explict definition for the negative form because that is the 69; actually interesting option, and we want that to have its own comment. 70mvolatile-cache 71Target Report RejectNegative Mask(VOLATILE_CACHE_SET) 72Use ordinarily cached memory accesses for volatile references 73 74mno-volatile-cache 75Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET) 76Enable cache bypass for volatile references 77 78mbarrel-shifter 79Target Report Mask(BARREL_SHIFTER) 80Generate instructions supported by barrel shifter 81 82mnorm 83Target Report Mask(NORM_SET) 84Generate norm instruction 85 86mswap 87Target Report Mask(SWAP_SET) 88Generate swap instruction 89 90mmul64 91Target Report Mask(MUL64_SET) 92Generate mul64 and mulu64 instructions 93 94mno-mpy 95Target Report Mask(NOMPY_SET) 96Do not generate mpy instructions for ARC700 97 98mea 99Target Report Mask(EA_SET) 100Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported 101 102msoft-float 103Target Report Mask(0) 104Dummy flag. This is the default unless FPX switches are provided explicitly 105 106mlong-calls 107Target Report Mask(LONG_CALLS_SET) 108Generate call insns as register indirect calls 109 110mno-brcc 111Target Report Mask(NO_BRCC_SET) 112Do no generate BRcc instructions in arc_reorg. 113 114msdata 115Target Report InverseMask(NO_SDATA_SET) 116Generate sdata references. This is the default, unless you compile for PIC. 117 118mno-millicode 119Target Report Mask(NO_MILLICODE_THUNK_SET) 120Do not generate millicode thunks (needed only with -Os) 121 122mspfp 123Target Report Mask(SPFP_COMPACT_SET) 124FPX: Generate Single Precision FPX (compact) instructions. 125 126mspfp-compact 127Target Report Mask(SPFP_COMPACT_SET) MaskExists 128FPX: Generate Single Precision FPX (compact) instructions. 129 130mspfp-fast 131Target Report Mask(SPFP_FAST_SET) 132FPX: Generate Single Precision FPX (fast) instructions. 133 134margonaut 135Target Report Mask(ARGONAUT_SET) 136FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions. 137 138mdpfp 139Target Report Mask(DPFP_COMPACT_SET) 140FPX: Generate Double Precision FPX (compact) instructions. 141 142mdpfp-compact 143Target Report Mask(DPFP_COMPACT_SET) MaskExists 144FPX: Generate Double Precision FPX (compact) instructions. 145 146mdpfp-fast 147Target Report Mask(DPFP_FAST_SET) 148FPX: Generate Double Precision FPX (fast) instructions. 149 150mno-dpfp-lrsr 151Target Report Mask(DPFP_DISABLE_LRSR) 152Disable LR and SR instructions from using FPX extension aux registers. 153 154msimd 155Target Report Mask(SIMD_SET) 156Enable generation of ARC SIMD instructions via target-specific builtins. 157 158mcpu= 159Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE) 160-mcpu=CPU Compile code for ARC variant CPU 161 162Enum 163Name(processor_type) Type(enum processor_type) 164 165EnumValue 166Enum(processor_type) String(A5) Value(PROCESSOR_A5) 167 168EnumValue 169Enum(processor_type) String(ARC600) Value(PROCESSOR_ARC600) 170 171EnumValue 172Enum(processor_type) String(ARC601) Value(PROCESSOR_ARC601) 173 174EnumValue 175Enum(processor_type) String(ARC700) Value(PROCESSOR_ARC700) 176 177msize-level= 178Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1) 179size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os 180 181misize 182Target Report PchIgnore Var(TARGET_DUMPISIZE) 183Annotate assembler instructions with estimated addresses 184 185mmultcost= 186Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1) 187Cost to assume for a multiply instruction, with 4 being equal to a normal insn. 188 189mtune=ARC600 190Target RejectNegative Var(arc_tune, TUNE_ARC600) 191Tune for ARC600 cpu. 192 193mtune=ARC601 194Target RejectNegative Var(arc_tune, TUNE_ARC600) 195Tune for ARC601 cpu. 196 197mtune=ARC700 198Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD) 199Tune for ARC700 R4.2 Cpu with standard multiplier block. 200 201mtune=ARC700-xmac 202Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC) 203Tune for ARC700 R4.2 Cpu with XMAC block. 204 205mtune=ARC725D 206Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC) 207Tune for ARC700 R4.2 Cpu with XMAC block. 208 209mtune=ARC750D 210Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC) 211Tune for ARC700 R4.2 Cpu with XMAC block. 212 213mindexed-loads 214Target Var(TARGET_INDEXED_LOADS) 215Enable the use of indexed loads 216 217mauto-modify-reg 218Target Var(TARGET_AUTO_MODIFY_REG) 219Enable the use of pre/post modify with register displacement. 220 221mmul32x16 222Target Report Mask(MULMAC_32BY16_SET) 223Generate 32x16 multiply and mac instructions 224 225; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) , 226; alas, basic-block.h is not included in options.c . 227munalign-prob-threshold= 228Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2) 229Set probability threshold for unaligning branches 230 231mmedium-calls 232Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT) 233Don't use less than 25 bit addressing range for calls. 234 235mannotate-align 236Target Var(TARGET_ANNOTATE_ALIGN) 237Explain what alignment considerations lead to the decision to make an insn short or long. 238 239malign-call 240Target Var(TARGET_ALIGN_CALL) 241Do alignment optimizations for call instructions. 242 243mRcq 244Target Var(TARGET_Rcq) 245Enable Rcq constraint handling - most short code generation depends on this. 246 247mRcw 248Target Var(TARGET_Rcw) 249Enable Rcw constraint handling - ccfsm condexec mostly depends on this. 250 251mearly-cbranchsi 252Target Var(TARGET_EARLY_CBRANCHSI) 253Enable pre-reload use of cbranchsi pattern 254 255mbbit-peephole 256Target Var(TARGET_BBIT_PEEPHOLE) 257Enable bbit peephole2 258 259mcase-vector-pcrel 260Target Var(TARGET_CASE_VECTOR_PC_RELATIVE) 261Use pc-relative switch case tables - this enables case table shortening. 262 263mcompact-casesi 264Target Var(TARGET_COMPACT_CASESI) 265Enable compact casesi pattern 266 267mq-class 268Target Var(TARGET_Q_CLASS) 269Enable 'q' instruction alternatives. 270 271mexpand-adddi 272Target Var(TARGET_EXPAND_ADDDI) 273Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc. 274 275 276; Flags used by the assembler, but for which we define preprocessor 277; macro symbols as well. 278mcrc 279Target Report 280Enable variable polynomial CRC extension 281 282mdsp-packa 283Target Report 284Enable DSP 3.1 Pack A extensions 285 286mdvbf 287Target Report 288Enable dual viterbi butterfly extension 289 290mmac-d16 291Target Report Undocumented 292 293mmac-24 294Target Report Undocumented 295 296mtelephony 297Target Report RejectNegative 298Enable Dual and Single Operand Instructions for Telephony 299 300mxy 301Target Report 302Enable XY Memory extension (DSP version 3) 303 304; ARC700 4.10 extension instructions 305mlock 306Target Report 307Enable Locked Load/Store Conditional extension 308 309mswape 310Target Report 311Enable swap byte ordering extension instruction 312 313mrtsc 314Target Report 315Enable 64-bit Time-Stamp Counter extension instruction 316 317mno-epilogue-cfi 318Target Report RejectNegative InverseMask(EPILOGUE_CFI) 319Disable generation of cfi for epilogues. 320 321mepilogue-cfi 322Target RejectNegative Mask(EPILOGUE_CFI) 323Enable generation of cfi for epilogues. 324 325EB 326Target 327Pass -EB option through to linker. 328 329EL 330Target 331Pass -EL option through to linker. 332 333marclinux 334target 335Pass -marclinux option through to linker. 336 337marclinux_prof 338target 339Pass -marclinux_prof option through to linker. 340 341;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra. 342;Target InverseMask(NO_LRA) 343; lra still won't allow to configure libgcc; see PR rtl-optimization/55464. 344; so don't enable by default. 345mlra 346Target Mask(LRA) 347Enable lra 348 349mlra-priority-none 350Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE) 351Don't indicate any priority with TARGET_REGISTER_PRIORITY 352 353mlra-priority-compact 354Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT) 355Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY 356 357mlra-priority-noncompact 358Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT) 359Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY 360 361mucb-mcount 362Target Report Var(TARGET_UCB_MCOUNT) 363instrument with mcount calls as in the ucb code 364 365; backward-compatibility aliases, translated by DRIVER_SELF_SPECS 366 367mEA 368Target 369 370multcost= 371Target RejectNegative Joined 372 373; Unfortunately, listing the full option name gives us clashes 374; with OPT_opt_name being claimed for both opt_name and opt-name, 375; so we leave out the last character or more. 376mbarrel_shifte 377Target Joined 378 379mspfp_ 380Target Joined 381 382mdpfp_ 383Target Joined 384 385mdsp_pack 386Target Joined 387 388mmac_ 389Target Joined 390 391