1; Options for the Synopsys DesignWare ARC port of the compiler 2; 3; Copyright (C) 2005-2017 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 3, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT 13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15; License for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING3. If not see 19; <http://www.gnu.org/licenses/>. 20 21HeaderInclude 22config/arc/arc-opts.h 23 24mbig-endian 25Target Report RejectNegative Mask(BIG_ENDIAN) 26Compile code for big endian mode. 27 28mlittle-endian 29Target Report RejectNegative InverseMask(BIG_ENDIAN) 30Compile code for little endian mode. This is the default. 31 32mno-cond-exec 33Target Report RejectNegative Mask(NO_COND_EXEC) 34Disable ARCompact specific pass to generate conditional execution instructions. 35 36mA6 37Target Report 38Generate ARCompact 32-bit code for ARC600 processor. 39 40mARC600 41Target Report 42Same as -mA6. 43 44mARC601 45Target Report 46Generate ARCompact 32-bit code for ARC601 processor. 47 48mA7 49Target Report 50Generate ARCompact 32-bit code for ARC700 processor. 51 52mARC700 53Target Report 54Same as -mA7. 55 56mmpy-option= 57Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option) 58-mmpy-option=MPY Compile ARCv2 code with a multiplier design option. 59 60Enum 61Name(arc_mpy) Type(int) 62 63EnumValue 64Enum(arc_mpy) String(0) Value(0) 65 66EnumValue 67Enum(arc_mpy) String(none) Value(0) Canonical 68 69EnumValue 70Enum(arc_mpy) String(1) Value(1) 71 72EnumValue 73Enum(arc_mpy) String(w) Value(1) Canonical 74 75EnumValue 76Enum(arc_mpy) String(2) Value(2) 77 78EnumValue 79Enum(arc_mpy) String(mpy) Value(2) 80 81EnumValue 82Enum(arc_mpy) String(wlh1) Value(2) Canonical 83 84EnumValue 85Enum(arc_mpy) String(3) Value(3) 86 87EnumValue 88Enum(arc_mpy) String(wlh2) Value(3) Canonical 89 90EnumValue 91Enum(arc_mpy) String(4) Value(4) 92 93EnumValue 94Enum(arc_mpy) String(wlh3) Value(4) Canonical 95 96EnumValue 97Enum(arc_mpy) String(5) Value(5) 98 99EnumValue 100Enum(arc_mpy) String(wlh4) Value(5) Canonical 101 102EnumValue 103Enum(arc_mpy) String(6) Value(6) 104 105EnumValue 106Enum(arc_mpy) String(wlh5) Value(6) Canonical 107 108EnumValue 109Enum(arc_mpy) String(7) Value(7) 110 111EnumValue 112Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical 113 114EnumValue 115Enum(arc_mpy) String(8) Value(8) 116 117EnumValue 118Enum(arc_mpy) String(plus_macd) Value(8) Canonical 119 120EnumValue 121Enum(arc_mpy) String(9) Value(9) 122 123EnumValue 124Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical 125 126mdiv-rem 127Target Report Mask(DIVREM) 128Enable DIV-REM instructions for ARCv2. 129 130mcode-density 131Target Report Mask(CODE_DENSITY) 132Enable code density instructions for ARCv2. 133 134mmixed-code 135Target Report Mask(MIXED_CODE_SET) 136Tweak register allocation to help 16-bit instruction generation. 137; originally this was: 138;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions 139; but we do that without -mmixed-code, too, it's just a different instruction 140; count / size tradeoff. 141 142; We use an explict definition for the negative form because that is the 143; actually interesting option, and we want that to have its own comment. 144mvolatile-cache 145Target Report RejectNegative Mask(VOLATILE_CACHE_SET) 146Use ordinarily cached memory accesses for volatile references. 147 148mno-volatile-cache 149Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET) 150Enable cache bypass for volatile references. 151 152mbarrel-shifter 153Target Report Mask(BARREL_SHIFTER) 154Generate instructions supported by barrel shifter. 155 156mnorm 157Target Report Mask(NORM_SET) 158Generate norm instruction. 159 160mswap 161Target Report Mask(SWAP_SET) 162Generate swap instruction. 163 164mmul64 165Target Report Mask(MUL64_SET) 166Generate mul64 and mulu64 instructions. 167 168mno-mpy 169Target Report Mask(NOMPY_SET) Warn(%qs is deprecated) 170Do not generate mpy instructions for ARC700. 171 172mea 173Target Report Mask(EA_SET) 174Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported. 175 176msoft-float 177Target Report Mask(0) 178Dummy flag. This is the default unless FPX switches are provided explicitly. 179 180mlong-calls 181Target Report Mask(LONG_CALLS_SET) 182Generate call insns as register indirect calls. 183 184mno-brcc 185Target Report Mask(NO_BRCC_SET) 186Do no generate BRcc instructions in arc_reorg. 187 188msdata 189Target Report InverseMask(NO_SDATA_SET) 190Generate sdata references. This is the default, unless you compile for PIC. 191 192mno-millicode 193Target Report Mask(NO_MILLICODE_THUNK_SET) 194Do not generate millicode thunks (needed only with -Os). 195 196mspfp 197Target Report Mask(SPFP_COMPACT_SET) 198FPX: Generate Single Precision FPX (compact) instructions. 199 200mspfp-compact 201Target Report Mask(SPFP_COMPACT_SET) MaskExists 202FPX: Generate Single Precision FPX (compact) instructions. 203 204mspfp-fast 205Target Report Mask(SPFP_FAST_SET) 206FPX: Generate Single Precision FPX (fast) instructions. 207 208margonaut 209Target Report Mask(ARGONAUT_SET) 210FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions. 211 212mdpfp 213Target Report Mask(DPFP_COMPACT_SET) 214FPX: Generate Double Precision FPX (compact) instructions. 215 216mdpfp-compact 217Target Report Mask(DPFP_COMPACT_SET) MaskExists 218FPX: Generate Double Precision FPX (compact) instructions. 219 220mdpfp-fast 221Target Report Mask(DPFP_FAST_SET) 222FPX: Generate Double Precision FPX (fast) instructions. 223 224mno-dpfp-lrsr 225Target Report Mask(DPFP_DISABLE_LRSR) 226Disable LR and SR instructions from using FPX extension aux registers. 227 228msimd 229Target Report Mask(SIMD_SET) 230Enable generation of ARC SIMD instructions via target-specific builtins. 231 232mcpu= 233Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE) 234-mcpu=CPU Compile code for ARC variant CPU. 235 236msize-level= 237Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1) 238size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os. 239 240misize 241Target Report PchIgnore Var(TARGET_DUMPISIZE) 242Annotate assembler instructions with estimated addresses. 243 244mmultcost= 245Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1) 246Cost to assume for a multiply instruction, with 4 being equal to a normal insn. 247 248mtune=ARC600 249Target RejectNegative Var(arc_tune, TUNE_ARC600) 250Tune for ARC600 cpu. 251 252mtune=ARC601 253Target RejectNegative Var(arc_tune, TUNE_ARC600) 254Tune for ARC601 cpu. 255 256mtune=ARC700 257Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD) 258Tune for ARC700 R4.2 Cpu with standard multiplier block. 259 260mtune=ARC700-xmac 261Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC) 262Tune for ARC700 R4.2 Cpu with XMAC block. 263 264mtune=ARC725D 265Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC) 266Tune for ARC700 R4.2 Cpu with XMAC block. 267 268mtune=ARC750D 269Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC) 270Tune for ARC700 R4.2 Cpu with XMAC block. 271 272mindexed-loads 273Target Var(TARGET_INDEXED_LOADS) 274Enable the use of indexed loads. 275 276mauto-modify-reg 277Target Var(TARGET_AUTO_MODIFY_REG) 278Enable the use of pre/post modify with register displacement. 279 280mmul32x16 281Target Report Mask(MULMAC_32BY16_SET) 282Generate 32x16 multiply and mac instructions. 283 284; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) , 285; alas, basic-block.h is not included in options.c . 286munalign-prob-threshold= 287Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2) 288Set probability threshold for unaligning branches. 289 290mmedium-calls 291Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT) 292Don't use less than 25 bit addressing range for calls. 293 294mannotate-align 295Target Var(TARGET_ANNOTATE_ALIGN) 296Explain what alignment considerations lead to the decision to make an insn short or long. 297 298malign-call 299Target Var(TARGET_ALIGN_CALL) 300Do alignment optimizations for call instructions. 301 302mRcq 303Target Var(TARGET_Rcq) 304Enable Rcq constraint handling - most short code generation depends on this. 305 306mRcw 307Target Var(TARGET_Rcw) 308Enable Rcw constraint handling - ccfsm condexec mostly depends on this. 309 310mearly-cbranchsi 311Target Var(TARGET_EARLY_CBRANCHSI) 312Enable pre-reload use of cbranchsi pattern. 313 314mbbit-peephole 315Target Var(TARGET_BBIT_PEEPHOLE) 316Enable bbit peephole2. 317 318mcase-vector-pcrel 319Target Var(TARGET_CASE_VECTOR_PC_RELATIVE) 320Use pc-relative switch case tables - this enables case table shortening. 321 322mcompact-casesi 323Target Var(TARGET_COMPACT_CASESI) 324Enable compact casesi pattern. 325 326mq-class 327Target Var(TARGET_Q_CLASS) 328Enable 'q' instruction alternatives. 329 330mexpand-adddi 331Target Var(TARGET_EXPAND_ADDDI) 332Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc. 333 334 335; Flags used by the assembler, but for which we define preprocessor 336; macro symbols as well. 337mcrc 338Target Report Warn(%qs is deprecated) 339Enable variable polynomial CRC extension. 340 341mdsp-packa 342Target Report Warn(%qs is deprecated) 343Enable DSP 3.1 Pack A extensions. 344 345mdvbf 346Target Report Warn(%qs is deprecated) 347Enable dual viterbi butterfly extension. 348 349mmac-d16 350Target Report Undocumented Warn(%qs is deprecated) 351 352mmac-24 353Target Report Undocumented Warn(%qs is deprecated) 354 355mtelephony 356Target Report RejectNegative Warn(%qs is deprecated) 357Enable Dual and Single Operand Instructions for Telephony. 358 359mxy 360Target Report 361Enable XY Memory extension (DSP version 3). 362 363; ARC700 4.10 extension instructions 364mlock 365Target Report 366Enable Locked Load/Store Conditional extension. 367 368mswape 369Target Report 370Enable swap byte ordering extension instruction. 371 372mrtsc 373Target Report Warn(%qs is deprecated) 374Enable 64-bit Time-Stamp Counter extension instruction. 375 376EB 377Target 378Pass -EB option through to linker. 379 380EL 381Target 382Pass -EL option through to linker. 383 384marclinux 385Target 386Pass -marclinux option through to linker. 387 388marclinux_prof 389Target 390Pass -marclinux_prof option through to linker. 391 392;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra. 393;Target InverseMask(NO_LRA) 394; lra still won't allow to configure libgcc; see PR rtl-optimization/55464. 395; so don't enable by default. 396mlra 397Target Mask(LRA) 398Enable lra. 399 400mlra-priority-none 401Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE) 402Don't indicate any priority with TARGET_REGISTER_PRIORITY. 403 404mlra-priority-compact 405Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT) 406Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. 407 408mlra-priority-noncompact 409Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT) 410Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. 411 412; backward-compatibility aliases, translated by DRIVER_SELF_SPECS 413 414mEA 415Target 416 417multcost= 418Target RejectNegative Joined 419 420matomic 421Target Report Mask(ATOMIC) 422Enable atomic instructions. 423 424mll64 425Target Report Mask(LL64) 426Enable double load/store instructions for ARC HS. 427 428mfpu= 429Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build) 430Specify the name of the target floating point configuration. 431 432Enum 433Name(arc_fpu) Type(int) 434 435EnumValue 436Enum(arc_fpu) String(fpus) Value(FPU_FPUS) 437 438EnumValue 439Enum(arc_fpu) String(fpud) Value(FPU_FPUD) 440 441EnumValue 442Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA) 443 444EnumValue 445Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV) 446 447EnumValue 448Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA) 449 450EnumValue 451Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL) 452 453EnumValue 454Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV) 455 456EnumValue 457Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV) 458 459EnumValue 460Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA) 461 462EnumValue 463Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA) 464 465EnumValue 466Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL) 467 468EnumValue 469Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL) 470 471mtp-regno= 472Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT) 473Specify thread pointer register number. 474 475mtp-regno=none 476Target RejectNegative Var(arc_tp_regno,-1) 477 478mbitops 479Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT) 480Enable use of NPS400 bit operations. 481 482mcmem 483Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT) 484Enable use of NPS400 xld/xst extension. 485 486munaligned-access 487Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT) 488Enable unaligned word and halfword accesses to packed data. 489