1 /* Definitions of target machine for GNU compiler, Argonaut ARC cpu. 2 Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2004, 2005, 3 2007, 2008, 2009 Free Software Foundation, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 /* ??? This is an old port, and is undoubtedly suffering from bit rot. */ 22 23 /* Things to do: 24 25 - incscc, decscc? 26 - print active compiler options in assembler output 27 */ 28 29 30 #undef ASM_SPEC 31 #undef LINK_SPEC 32 #undef STARTFILE_SPEC 33 #undef ENDFILE_SPEC 34 #undef SIZE_TYPE 35 #undef PTRDIFF_TYPE 36 #undef WCHAR_TYPE 37 #undef WCHAR_TYPE_SIZE 38 #undef ASM_OUTPUT_LABELREF 39 40 /* Print subsidiary information on the compiler version in use. */ 41 #define TARGET_VERSION fprintf (stderr, " (arc)") 42 43 /* Names to predefine in the preprocessor for this target machine. */ 44 #define TARGET_CPU_CPP_BUILTINS() \ 45 do \ 46 { \ 47 builtin_define ("__arc__"); \ 48 if (TARGET_BIG_ENDIAN) \ 49 builtin_define ("__big_endian__"); \ 50 if (arc_cpu_type == 0) \ 51 builtin_define ("__base__"); \ 52 builtin_assert ("cpu=arc"); \ 53 builtin_assert ("machine=arc"); \ 54 } while (0) 55 56 /* Pass -mmangle-cpu if we get -mcpu=*. 57 Doing it this way lets one have it on as default with -mcpu=*, 58 but also lets one turn it off with -mno-mangle-cpu. */ 59 #define CC1_SPEC "\ 60 %{mcpu=*:-mmangle-cpu} \ 61 %{EB:%{EL:%emay not use both -EB and -EL}} \ 62 %{EB:-mbig-endian} %{EL:-mlittle-endian} \ 63 " 64 65 #define ASM_SPEC "%{v} %{EB} %{EL}" 66 67 #define LINK_SPEC "%{v} %{EB} %{EL}" 68 69 #define STARTFILE_SPEC "%{!shared:crt0.o%s} crtinit.o%s" 70 71 #define ENDFILE_SPEC "crtfini.o%s" 72 73 /* Instruction set characteristics. 74 These are internal macros, set by the appropriate -mcpu= option. */ 75 76 /* Nonzero means the cpu has a barrel shifter. */ 77 #define TARGET_SHIFTER 0 78 79 /* Which cpu we're compiling for. */ 80 extern int arc_cpu_type; 81 82 /* Check if CPU is an extension and set `arc_cpu_type' and `arc_mangle_cpu' 83 appropriately. The result should be nonzero if the cpu is recognized, 84 otherwise zero. This is intended to be redefined in a cover file. 85 This is used by arc_init. */ 86 #define ARC_EXTENSION_CPU(cpu) 0 87 88 /* Sometimes certain combinations of command options do not make 89 sense on a particular target machine. You can define a macro 90 `OVERRIDE_OPTIONS' to take account of this. This macro, if 91 defined, is executed once just after all the command options have 92 been parsed. 93 94 Don't use this macro to turn on various extra optimizations for 95 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 96 97 98 #define OVERRIDE_OPTIONS \ 99 do { \ 100 /* These need to be done at start up. It's convenient to do them here. */ \ 101 arc_init (); \ 102 } while (0) 103 104 /* Target machine storage layout. */ 105 106 /* Define this if most significant bit is lowest numbered 107 in instructions that operate on numbered bit-fields. */ 108 #define BITS_BIG_ENDIAN 1 109 110 /* Define this if most significant byte of a word is the lowest numbered. */ 111 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN) 112 113 /* Define this if most significant word of a multiword number is the lowest 114 numbered. */ 115 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN) 116 117 /* Define this to set the endianness to use in libgcc2.c, which can 118 not depend on target_flags. */ 119 #ifdef __big_endian__ 120 #define LIBGCC2_WORDS_BIG_ENDIAN 1 121 #else 122 #define LIBGCC2_WORDS_BIG_ENDIAN 0 123 #endif 124 125 /* Width of a word, in units (bytes). */ 126 #define UNITS_PER_WORD 4 127 128 /* Define this macro if it is advisable to hold scalars in registers 129 in a wider mode than that declared by the program. In such cases, 130 the value is constrained to be within the bounds of the declared 131 type, but kept valid in the wider mode. The signedness of the 132 extension may differ from that of the type. */ 133 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 134 if (GET_MODE_CLASS (MODE) == MODE_INT \ 135 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 136 { \ 137 (MODE) = SImode; \ 138 } 139 140 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 141 #define PARM_BOUNDARY 32 142 143 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 144 #define STACK_BOUNDARY 64 145 146 /* ALIGN FRAMES on word boundaries */ 147 #define ARC_STACK_ALIGN(LOC) (((LOC)+7) & ~7) 148 149 /* Allocation boundary (in *bits*) for the code of a function. */ 150 #define FUNCTION_BOUNDARY 32 151 152 /* Alignment of field after `int : 0' in a structure. */ 153 #define EMPTY_FIELD_BOUNDARY 32 154 155 /* Every structure's size must be a multiple of this. */ 156 #define STRUCTURE_SIZE_BOUNDARY 8 157 158 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 159 #define PCC_BITFIELD_TYPE_MATTERS 1 160 161 /* No data type wants to be aligned rounder than this. */ 162 /* This is bigger than currently necessary for the ARC. If 8 byte floats are 163 ever added it's not clear whether they'll need such alignment or not. For 164 now we assume they will. We can always relax it if necessary but the 165 reverse isn't true. */ 166 #define BIGGEST_ALIGNMENT 64 167 168 /* The best alignment to use in cases where we have a choice. */ 169 #define FASTEST_ALIGNMENT 32 170 171 /* Make strings word-aligned so strcpy from constants will be faster. */ 172 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 173 ((TREE_CODE (EXP) == STRING_CST \ 174 && (ALIGN) < FASTEST_ALIGNMENT) \ 175 ? FASTEST_ALIGNMENT : (ALIGN)) 176 177 /* Make arrays of chars word-aligned for the same reasons. */ 178 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 179 (TREE_CODE (TYPE) == ARRAY_TYPE \ 180 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 181 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 182 183 /* Set this nonzero if move instructions will actually fail to work 184 when given unaligned data. */ 185 /* On the ARC the lower address bits are masked to 0 as necessary. The chip 186 won't croak when given an unaligned address, but the insn will still fail 187 to produce the correct result. */ 188 #define STRICT_ALIGNMENT 1 189 190 /* Layout of source language data types. */ 191 192 #define SHORT_TYPE_SIZE 16 193 #define INT_TYPE_SIZE 32 194 #define LONG_TYPE_SIZE 32 195 #define LONG_LONG_TYPE_SIZE 64 196 #define FLOAT_TYPE_SIZE 32 197 #define DOUBLE_TYPE_SIZE 64 198 #define LONG_DOUBLE_TYPE_SIZE 64 199 200 /* Define this as 1 if `char' should by default be signed; else as 0. */ 201 #define DEFAULT_SIGNED_CHAR 1 202 203 #define SIZE_TYPE "long unsigned int" 204 #define PTRDIFF_TYPE "long int" 205 #define WCHAR_TYPE "short unsigned int" 206 #define WCHAR_TYPE_SIZE 16 207 208 /* Standard register usage. */ 209 210 /* Number of actual hardware registers. 211 The hardware registers are assigned numbers for the compiler 212 from 0 to just below FIRST_PSEUDO_REGISTER. 213 All registers that the compiler knows about must be given numbers, 214 even those that are not normally considered general registers. */ 215 /* Registers 61, 62, and 63 are not really registers and we needn't treat 216 them as such. We still need a register for the condition code. */ 217 #define FIRST_PSEUDO_REGISTER 62 218 219 /* 1 for registers that have pervasive standard uses 220 and are not available for the register allocator. 221 222 0-28 - general purpose registers 223 29 - ilink1 (interrupt link register) 224 30 - ilink2 (interrupt link register) 225 31 - blink (branch link register) 226 32-59 - reserved for extensions 227 60 - LP_COUNT 228 61 - condition code 229 230 For doc purposes: 231 61 - short immediate data indicator (setting flags) 232 62 - long immediate data indicator 233 63 - short immediate data indicator (not setting flags). 234 235 The general purpose registers are further broken down into: 236 0-7 - arguments/results 237 8-15 - call used 238 16-23 - call saved 239 24 - call used, static chain pointer 240 25 - call used, gptmp 241 26 - global pointer 242 27 - frame pointer 243 28 - stack pointer 244 245 By default, the extension registers are not available. */ 246 247 #define FIXED_REGISTERS \ 248 { 0, 0, 0, 0, 0, 0, 0, 0, \ 249 0, 0, 0, 0, 0, 0, 0, 0, \ 250 0, 0, 0, 0, 0, 0, 0, 0, \ 251 0, 0, 0, 1, 1, 1, 1, 0, \ 252 \ 253 1, 1, 1, 1, 1, 1, 1, 1, \ 254 1, 1, 1, 1, 1, 1, 1, 1, \ 255 1, 1, 1, 1, 1, 1, 1, 1, \ 256 1, 1, 1, 1, 1, 1 } 257 258 /* 1 for registers not available across function calls. 259 These must include the FIXED_REGISTERS and also any 260 registers that can be used without being saved. 261 The latter must include the registers where values are returned 262 and the register where structure-value addresses are passed. 263 Aside from that, you can include as many other registers as you like. */ 264 265 #define CALL_USED_REGISTERS \ 266 { 1, 1, 1, 1, 1, 1, 1, 1, \ 267 1, 1, 1, 1, 1, 1, 1, 1, \ 268 0, 0, 0, 0, 0, 0, 0, 0, \ 269 1, 1, 1, 1, 1, 1, 1, 1, \ 270 \ 271 1, 1, 1, 1, 1, 1, 1, 1, \ 272 1, 1, 1, 1, 1, 1, 1, 1, \ 273 1, 1, 1, 1, 1, 1, 1, 1, \ 274 1, 1, 1, 1, 1, 1 } 275 276 /* If defined, an initializer for a vector of integers, containing the 277 numbers of hard registers in the order in which GCC should 278 prefer to use them (from most preferred to least). */ 279 #define REG_ALLOC_ORDER \ 280 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \ 281 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 31, \ 282 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 283 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, \ 284 27, 28, 29, 30 } 285 286 /* Macro to conditionally modify fixed_regs/call_used_regs. */ 287 #define CONDITIONAL_REGISTER_USAGE \ 288 do { \ 289 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 290 { \ 291 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 292 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 293 } \ 294 } while (0) 295 296 /* Return number of consecutive hard regs needed starting at reg REGNO 297 to hold something of mode MODE. 298 This is ordinarily the length in words of a value of mode MODE 299 but can be less for certain modes in special long registers. */ 300 #define HARD_REGNO_NREGS(REGNO, MODE) \ 301 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 302 303 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 304 extern const unsigned int arc_hard_regno_mode_ok[]; 305 extern unsigned int arc_mode_class[]; 306 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 307 ((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0) 308 309 /* A C expression that is nonzero if it is desirable to choose 310 register allocation so as to avoid move instructions between a 311 value of mode MODE1 and a value of mode MODE2. 312 313 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 314 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 315 MODE2)' must be zero. */ 316 317 /* Tie QI/HI/SI modes together. */ 318 #define MODES_TIEABLE_P(MODE1, MODE2) \ 319 (GET_MODE_CLASS (MODE1) == MODE_INT \ 320 && GET_MODE_CLASS (MODE2) == MODE_INT \ 321 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 322 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD) 323 324 /* Register classes and constants. */ 325 326 /* Define the classes of registers for register constraints in the 327 machine description. Also define ranges of constants. 328 329 One of the classes must always be named ALL_REGS and include all hard regs. 330 If there is more than one class, another class must be named NO_REGS 331 and contain no registers. 332 333 The name GENERAL_REGS must be the name of a class (or an alias for 334 another name such as ALL_REGS). This is the class of registers 335 that is allowed by "g" or "r" in a register constraint. 336 Also, registers outside this class are allocated only when 337 instructions express preferences for them. 338 339 The classes must be numbered in nondecreasing order; that is, 340 a larger-numbered class must never be contained completely 341 in a smaller-numbered class. 342 343 For any two classes, it is very desirable that there be another 344 class that represents their union. 345 346 It is important that any condition codes have class NO_REGS. 347 See `register_operand'. */ 348 349 enum reg_class { 350 NO_REGS, LPCOUNT_REG, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES 351 }; 352 353 #define N_REG_CLASSES (int) LIM_REG_CLASSES 354 355 /* Give names of register classes as strings for dump file. */ 356 #define REG_CLASS_NAMES \ 357 { "NO_REGS", "LPCOUNT_REG", "GENERAL_REGS", "ALL_REGS" } 358 359 /* Define which registers fit in which classes. 360 This is an initializer for a vector of HARD_REG_SET 361 of length N_REG_CLASSES. */ 362 363 #define REG_CLASS_CONTENTS \ 364 { {0, 0}, {0, 0x10000000}, {0xffffffff, 0xfffffff}, \ 365 {0xffffffff, 0x1fffffff} } 366 367 /* The same information, inverted: 368 Return the class number of the smallest class containing 369 reg number REGNO. This could be a conditional expression 370 or could index an array. */ 371 extern enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 372 #define REGNO_REG_CLASS(REGNO) \ 373 (arc_regno_reg_class[REGNO]) 374 375 /* The class value for index registers, and the one for base regs. */ 376 #define INDEX_REG_CLASS GENERAL_REGS 377 #define BASE_REG_CLASS GENERAL_REGS 378 379 /* Get reg_class from a letter such as appears in the machine description. */ 380 #define REG_CLASS_FROM_LETTER(C) \ 381 ((C) == 'l' ? LPCOUNT_REG /* ??? needed? */ \ 382 : NO_REGS) 383 384 /* These assume that REGNO is a hard or pseudo reg number. 385 They give nonzero only if REGNO is a hard reg of the suitable class 386 or a pseudo reg currently allocated to a suitable hard reg. 387 Since they use reg_renumber, they are safe only once reg_renumber 388 has been allocated, which happens in local-alloc.c. */ 389 #define REGNO_OK_FOR_BASE_P(REGNO) \ 390 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) 391 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 392 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) 393 394 /* Given an rtx X being reloaded into a reg required to be 395 in class CLASS, return the class of reg to actually use. 396 In general this is just CLASS; but on some machines 397 in some cases it is preferable to use a more restrictive class. */ 398 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 399 (CLASS) 400 401 /* Return the maximum number of consecutive registers 402 needed to represent mode MODE in a register of class CLASS. */ 403 #define CLASS_MAX_NREGS(CLASS, MODE) \ 404 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 405 406 /* The letters I, J, K, L, M, N, O, P in a register constraint string 407 can be used to stand for particular ranges of immediate operands. 408 This macro defines what the ranges are. 409 C is the letter, and VALUE is a constant value. 410 Return 1 if VALUE is in the range specified by C. */ 411 /* 'I' is used for short immediates (always signed). 412 'J' is used for long immediates. 413 'K' is used for any constant up to 64 bits (for 64x32 situations?). */ 414 415 /* local to this file */ 416 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200) 417 /* local to this file */ 418 #define LARGE_INT(X) \ 419 ((X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \ 420 && (unsigned HOST_WIDE_INT)(X) <= (unsigned HOST_WIDE_INT) 0xffffffff) 421 422 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 423 ((C) == 'I' ? SMALL_INT (VALUE) \ 424 : (C) == 'J' ? LARGE_INT (VALUE) \ 425 : (C) == 'K' ? 1 \ 426 : 0) 427 428 /* Similar, but for floating constants, and defining letters G and H. 429 Here VALUE is the CONST_DOUBLE rtx itself. */ 430 /* 'G' is used for integer values for the multiplication insns where the 431 operands are extended from 4 bytes to 8 bytes. 432 'H' is used when any 64-bit constant is allowed. */ 433 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 434 ((C) == 'G' ? arc_double_limm_p (VALUE) \ 435 : (C) == 'H' ? 1 \ 436 : 0) 437 438 /* A C expression that defines the optional machine-dependent constraint 439 letters that can be used to segregate specific types of operands, 440 usually memory references, for the target machine. It should return 1 if 441 VALUE corresponds to the operand type represented by the constraint letter 442 C. If C is not defined as an extra constraint, the value returned should 443 be 0 regardless of VALUE. */ 444 /* ??? This currently isn't used. Waiting for PIC. */ 445 #if 0 446 #define EXTRA_CONSTRAINT(VALUE, C) \ 447 ((C) == 'R' ? (SYMBOL_REF_FUNCTION_P (VALUE) || GET_CODE (VALUE) == LABEL_REF) \ 448 : 0) 449 #endif 450 451 /* Stack layout and stack pointer usage. */ 452 453 /* Define this macro if pushing a word onto the stack moves the stack 454 pointer to a smaller address. */ 455 #define STACK_GROWS_DOWNWARD 456 457 /* Define this to nonzero if the nominal address of the stack frame 458 is at the high-address end of the local variables; 459 that is, each additional local variable allocated 460 goes at a more negative offset in the frame. */ 461 #define FRAME_GROWS_DOWNWARD 1 462 463 /* Offset within stack frame to start allocating local variables at. 464 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 465 first local allocated. Otherwise, it is the offset to the BEGINNING 466 of the first local allocated. */ 467 #define STARTING_FRAME_OFFSET 0 468 469 /* Offset from the stack pointer register to the first location at which 470 outgoing arguments are placed. */ 471 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET (0) 472 473 /* Offset of first parameter from the argument pointer register value. */ 474 /* 4 bytes for each of previous fp, return address, and previous gp. 475 4 byte reserved area for future considerations. */ 476 #define FIRST_PARM_OFFSET(FNDECL) 16 477 478 /* A C expression whose value is RTL representing the address in a 479 stack frame where the pointer to the caller's frame is stored. 480 Assume that FRAMEADDR is an RTL expression for the address of the 481 stack frame itself. 482 483 If you don't define this macro, the default is to return the value 484 of FRAMEADDR--that is, the stack frame address is also the address 485 of the stack word that points to the previous frame. */ 486 /* ??? unfinished */ 487 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/ 488 489 /* A C expression whose value is RTL representing the value of the 490 return address for the frame COUNT steps up from the current frame. 491 FRAMEADDR is the frame pointer of the COUNT frame, or the frame 492 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' 493 is defined. */ 494 /* The current return address is in r31. The return address of anything 495 farther back is at [%fp,4]. */ 496 #if 0 /* The default value should work. */ 497 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 498 (((COUNT) == -1) \ 499 ? gen_rtx_REG (Pmode, 31) \ 500 : copy_to_reg (gen_rtx_MEM (Pmode, \ 501 memory_address (Pmode, \ 502 plus_constant ((FRAME), \ 503 UNITS_PER_WORD))))) 504 #endif 505 506 /* Register to use for pushing function arguments. */ 507 #define STACK_POINTER_REGNUM 28 508 509 /* Base register for access to local variables of the function. */ 510 #define FRAME_POINTER_REGNUM 27 511 512 /* Base register for access to arguments of the function. */ 513 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 514 515 /* Register in which static-chain is passed to a function. This must 516 not be a register used by the prologue. */ 517 #define STATIC_CHAIN_REGNUM 24 518 519 /* C statement to store the difference between the frame pointer 520 and the stack pointer values immediately after the function prologue. */ 521 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ 522 ((VAR) = arc_compute_frame_size (get_frame_size ())) 523 524 /* Function argument passing. */ 525 526 /* If defined, the maximum amount of space required for outgoing 527 arguments will be computed and placed into the variable 528 `crtl->outgoing_args_size'. No space will be pushed 529 onto the stack for each call; instead, the function prologue should 530 increase the stack frame size by this amount. */ 531 #define ACCUMULATE_OUTGOING_ARGS 1 532 533 /* Value is the number of bytes of arguments automatically 534 popped when returning from a subroutine call. 535 FUNDECL is the declaration node of the function (as a tree), 536 FUNTYPE is the data type of the function (as a tree), 537 or for a library call it is an identifier node for the subroutine name. 538 SIZE is the number of bytes of arguments passed on the stack. */ 539 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0 540 541 /* Define a data type for recording info about an argument list 542 during the scan of that argument list. This data type should 543 hold all necessary information about the function itself 544 and about the args processed so far, enough to enable macros 545 such as FUNCTION_ARG to determine where the next arg should go. */ 546 #define CUMULATIVE_ARGS int 547 548 /* Initialize a variable CUM of type CUMULATIVE_ARGS 549 for a call to a function whose data type is FNTYPE. 550 For a library call, FNTYPE is 0. */ 551 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 552 ((CUM) = 0) 553 554 /* The number of registers used for parameter passing. Local to this file. */ 555 #define MAX_ARC_PARM_REGS 8 556 557 /* 1 if N is a possible register number for function argument passing. */ 558 #define FUNCTION_ARG_REGNO_P(N) \ 559 ((unsigned) (N) < MAX_ARC_PARM_REGS) 560 561 /* The ROUND_ADVANCE* macros are local to this file. */ 562 /* Round SIZE up to a word boundary. */ 563 #define ROUND_ADVANCE(SIZE) \ 564 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 565 566 /* Round arg MODE/TYPE up to the next word boundary. */ 567 #define ROUND_ADVANCE_ARG(MODE, TYPE) \ 568 ((MODE) == BLKmode \ 569 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ 570 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) 571 572 /* Round CUM up to the necessary point for argument MODE/TYPE. */ 573 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \ 574 ((((MODE) == BLKmode ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) \ 575 > BITS_PER_WORD) \ 576 ? (((CUM) + 1) & ~1) \ 577 : (CUM)) 578 579 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in 580 a reg. This includes arguments that have to be passed by reference as the 581 pointer to them is passed in a reg if one is available (and that is what 582 we're given). 583 This macro is only used in this file. */ 584 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 585 ((CUM) < MAX_ARC_PARM_REGS \ 586 && ((ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \ 587 + ROUND_ADVANCE_ARG ((MODE), (TYPE)) \ 588 <= MAX_ARC_PARM_REGS))) 589 590 /* Determine where to put an argument to a function. 591 Value is zero to push the argument on the stack, 592 or a hard register in which to store the argument. 593 594 MODE is the argument's machine mode. 595 TYPE is the data type of the argument (as a tree). 596 This is null for libcalls where that information may 597 not be available. 598 CUM is a variable of type CUMULATIVE_ARGS which gives info about 599 the preceding args and about the function being called. 600 NAMED is nonzero if this argument is a named parameter 601 (otherwise it is an extra parameter matching an ellipsis). */ 602 /* On the ARC the first MAX_ARC_PARM_REGS args are normally in registers 603 and the rest are pushed. */ 604 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 605 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 606 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \ 607 : 0) 608 609 /* Update the data in CUM to advance over an argument 610 of mode MODE and data type TYPE. 611 (TYPE is null for libcalls where that information may not be available.) */ 612 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 613 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \ 614 + ROUND_ADVANCE_ARG ((MODE), (TYPE)))) 615 616 /* If defined, a C expression that gives the alignment boundary, in bits, 617 of an argument with the specified mode and type. If it is not defined, 618 PARM_BOUNDARY is used for all arguments. */ 619 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 620 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \ 621 ? PARM_BOUNDARY \ 622 : 2 * PARM_BOUNDARY) 623 624 /* Function results. */ 625 626 /* Define how to find the value returned by a function. 627 VALTYPE is the data type of the value (as a tree). 628 If the precise function being called is known, FUNC is its FUNCTION_DECL; 629 otherwise, FUNC is 0. */ 630 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0) 631 632 /* Define how to find the value returned by a library function 633 assuming the value has mode MODE. */ 634 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) 635 636 /* 1 if N is a possible register number for a function value 637 as seen by the caller. */ 638 /* ??? What about r1 in DI/DF values. */ 639 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 640 641 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ 642 #define DEFAULT_PCC_STRUCT_RETURN 0 643 644 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 645 the stack pointer does not matter. The value is tested only in 646 functions that have frame pointers. 647 No definition is equivalent to always zero. */ 648 #define EXIT_IGNORE_STACK 0 649 650 /* Epilogue delay slots. */ 651 #define DELAY_SLOTS_FOR_EPILOGUE arc_delay_slots_for_epilogue () 652 653 #define ELIGIBLE_FOR_EPILOGUE_DELAY(TRIAL, SLOTS_FILLED) \ 654 arc_eligible_for_epilogue_delay (TRIAL, SLOTS_FILLED) 655 656 /* Output assembler code to FILE to increment profiler label # LABELNO 657 for profiling a function entry. */ 658 #define FUNCTION_PROFILER(FILE, LABELNO) 659 660 #define TRAMPOLINE_ALIGNMENT 32 661 #define TRAMPOLINE_SIZE 16 662 663 /* Addressing modes, and classification of registers for them. */ 664 665 /* Maximum number of registers that can appear in a valid memory address. */ 666 /* The `ld' insn allows 2, but the `st' insn only allows 1. */ 667 #define MAX_REGS_PER_ADDRESS 1 668 669 /* We have pre inc/dec (load/store with update). */ 670 #define HAVE_PRE_INCREMENT 1 671 #define HAVE_PRE_DECREMENT 1 672 673 /* Recognize any constant value that is a valid address. */ 674 #define CONSTANT_ADDRESS_P(X) \ 675 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 676 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST) 677 678 /* Nonzero if the constant value X is a legitimate general operand. 679 We can handle any 32- or 64-bit constant. */ 680 /* "1" should work since the largest constant should be a 64 bit critter. */ 681 /* ??? Not sure what to do for 64x32 compiler. */ 682 #define LEGITIMATE_CONSTANT_P(X) 1 683 684 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 685 and check its validity for a certain class. 686 We have two alternate definitions for each of them. 687 The usual definition accepts all pseudo regs; the other rejects 688 them unless they have been allocated suitable hard regs. 689 The symbol REG_OK_STRICT causes the latter definition to be used. 690 691 Most source files want to accept pseudo regs in the hope that 692 they will get allocated to the class that the insn wants them to be in. 693 Source files for reload pass need to be strict. 694 After reload, it makes no difference, since pseudo regs have 695 been eliminated by then. */ 696 697 #ifndef REG_OK_STRICT 698 699 /* Nonzero if X is a hard reg that can be used as an index 700 or if it is a pseudo reg. */ 701 #define REG_OK_FOR_INDEX_P(X) \ 702 ((unsigned) REGNO (X) - 32 >= FIRST_PSEUDO_REGISTER - 32) 703 /* Nonzero if X is a hard reg that can be used as a base reg 704 or if it is a pseudo reg. */ 705 #define REG_OK_FOR_BASE_P(X) \ 706 ((unsigned) REGNO (X) - 32 >= FIRST_PSEUDO_REGISTER - 32) 707 708 #else 709 710 /* Nonzero if X is a hard reg that can be used as an index. */ 711 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 712 /* Nonzero if X is a hard reg that can be used as a base reg. */ 713 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 714 715 #endif 716 717 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 718 that is a valid memory address for an instruction. 719 The MODE argument is the machine mode for the MEM expression 720 that wants to use this address. */ 721 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm] 722 but the `st' insn only allows [reg],[reg+shimm],[limm]. 723 The only thing we can do is only allow the most strict case `st' and hope 724 other parts optimize out the restrictions for `ld'. */ 725 726 /* local to this file */ 727 #define RTX_OK_FOR_BASE_P(X) \ 728 (REG_P (X) && REG_OK_FOR_BASE_P (X)) 729 730 /* local to this file */ 731 #define RTX_OK_FOR_INDEX_P(X) \ 732 (0 && /*???*/ REG_P (X) && REG_OK_FOR_INDEX_P (X)) 733 734 /* local to this file */ 735 /* ??? Loads can handle any constant, stores can only handle small ones. */ 736 #define RTX_OK_FOR_OFFSET_P(X) \ 737 (GET_CODE (X) == CONST_INT && SMALL_INT (INTVAL (X))) 738 739 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \ 740 (GET_CODE (X) == PLUS \ 741 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ 742 && (RTX_OK_FOR_INDEX_P (XEXP (X, 1)) \ 743 || RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))) 744 745 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 746 { if (RTX_OK_FOR_BASE_P (X)) \ 747 goto ADDR; \ 748 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \ 749 goto ADDR; \ 750 if (GET_CODE (X) == CONST_INT && LARGE_INT (INTVAL (X))) \ 751 goto ADDR; \ 752 if (GET_CODE (X) == SYMBOL_REF \ 753 || GET_CODE (X) == LABEL_REF \ 754 || GET_CODE (X) == CONST) \ 755 goto ADDR; \ 756 if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 757 /* We're restricted here by the `st' insn. */ \ 758 && RTX_OK_FOR_BASE_P (XEXP ((X), 0))) \ 759 goto ADDR; \ 760 } 761 762 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 763 return the mode to be used for the comparison. */ 764 #define SELECT_CC_MODE(OP, X, Y) \ 765 arc_select_cc_mode (OP, X, Y) 766 767 /* Return nonzero if SELECT_CC_MODE will never return MODE for a 768 floating point inequality comparison. */ 769 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ 770 771 /* Costs. */ 772 773 /* Compute extra cost of moving data between one register class 774 and another. */ 775 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2 776 777 /* Compute the cost of moving data between registers and memory. */ 778 /* Memory is 3 times as expensive as registers. 779 ??? Is that the right way to look at it? */ 780 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ 781 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12) 782 783 /* The cost of a branch insn. */ 784 /* ??? What's the right value here? Branches are certainly more 785 expensive than reg->reg moves. */ 786 #define BRANCH_COST(speed_p, predictable_p) 2 787 788 /* Nonzero if access to memory by bytes is slow and undesirable. 789 For RISC chips, it means that access to memory by bytes is no 790 better than access by words when possible, so grab a whole word 791 and maybe make use of that. */ 792 #define SLOW_BYTE_ACCESS 1 793 794 /* Define this macro if it is as good or better to call a constant 795 function address than to call an address kept in a register. */ 796 /* On the ARC, calling through registers is slow. */ 797 #define NO_FUNCTION_CSE 798 799 /* Section selection. */ 800 /* WARNING: These section names also appear in dwarfout.c. */ 801 802 /* The names of the text, data, and readonly-data sections are runtime 803 selectable. */ 804 805 #define ARC_SECTION_FORMAT "\t.section %s" 806 #define ARC_DEFAULT_TEXT_SECTION ".text" 807 #define ARC_DEFAULT_DATA_SECTION ".data" 808 #define ARC_DEFAULT_RODATA_SECTION ".rodata" 809 810 extern const char *arc_text_section, *arc_data_section, *arc_rodata_section; 811 812 /* initfini.c uses this in an asm. */ 813 #if defined (CRT_INIT) || defined (CRT_FINI) 814 #define TEXT_SECTION_ASM_OP "\t.section .text" 815 #else 816 #define TEXT_SECTION_ASM_OP arc_text_section 817 #endif 818 #define DATA_SECTION_ASM_OP arc_data_section 819 820 #undef READONLY_DATA_SECTION_ASM_OP 821 #define READONLY_DATA_SECTION_ASM_OP arc_rodata_section 822 823 #define BSS_SECTION_ASM_OP "\t.section .bss" 824 825 /* Define this macro if jump tables (for tablejump insns) should be 826 output in the text section, along with the assembler instructions. 827 Otherwise, the readonly data section is used. 828 This macro is irrelevant if there is no separate readonly data section. */ 829 /*#define JUMP_TABLES_IN_TEXT_SECTION*/ 830 831 /* For DWARF. Marginally different than default so output is "prettier" 832 (and consistent with above). */ 833 #define PUSHSECTION_ASM_OP "\t.section " 834 835 /* Tell crtstuff.c we're using ELF. */ 836 #define OBJECT_FORMAT_ELF 837 838 /* PIC */ 839 840 /* The register number of the register used to address a table of static 841 data addresses in memory. In some cases this register is defined by a 842 processor's ``application binary interface'' (ABI). When this macro 843 is defined, RTL is generated for this register once, as with the stack 844 pointer and frame pointer registers. If this macro is not defined, it 845 is up to the machine-dependent files to allocate such a register (if 846 necessary). */ 847 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 26 : INVALID_REGNUM) 848 849 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is 850 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM 851 is not defined. */ 852 /* This register is call-saved on the ARC. */ 853 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ 854 855 /* A C expression that is nonzero if X is a legitimate immediate 856 operand on the target machine when generating position independent code. 857 You can assume that X satisfies CONSTANT_P, so you need not 858 check this. You can also assume `flag_pic' is true, so you need not 859 check it either. You need not define this macro if all constants 860 (including SYMBOL_REF) can be immediate operands when generating 861 position independent code. */ 862 /*#define LEGITIMATE_PIC_OPERAND_P(X)*/ 863 864 /* Control the assembler format that we output. */ 865 866 /* A C string constant describing how to begin a comment in the target 867 assembler language. The compiler assumes that the comment will 868 end at the end of the line. */ 869 #define ASM_COMMENT_START ";" 870 871 /* Output to assembler file text saying following lines 872 may contain character constants, extra white space, comments, etc. */ 873 #define ASM_APP_ON "" 874 875 /* Output to assembler file text saying following lines 876 no longer contain unusual constructs. */ 877 #define ASM_APP_OFF "" 878 879 /* Globalizing directive for a label. */ 880 #define GLOBAL_ASM_OP "\t.global\t" 881 882 /* This is how to output a reference to a user-level label named NAME. 883 `assemble_name' uses this. */ 884 /* We mangle all user labels to provide protection from linking code 885 compiled for different cpus. */ 886 /* We work around a dwarfout.c deficiency by watching for labels from it and 887 not adding the '_' prefix nor the cpu suffix. There is a comment in 888 dwarfout.c that says it should be using (*targetm.asm_out.internal_label). */ 889 extern const char *arc_mangle_cpu; 890 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 891 do { \ 892 if ((NAME)[0] == '.' && (NAME)[1] == 'L') \ 893 fprintf (FILE, "%s", NAME); \ 894 else \ 895 { \ 896 fputc ('_', FILE); \ 897 if (TARGET_MANGLE_CPU && arc_mangle_cpu != NULL) \ 898 fprintf (FILE, "%s_", arc_mangle_cpu); \ 899 fprintf (FILE, "%s", NAME); \ 900 } \ 901 } while (0) 902 903 /* Assembler pseudo-op to equate one value with another. */ 904 /* ??? This is needed because dwarfout.c provides a default definition too 905 late for defaults.h (which contains the default definition of ASM_OUTPUT_DEF 906 that we use). */ 907 #define SET_ASM_OP "\t.set\t" 908 909 /* How to refer to registers in assembler output. 910 This sequence is indexed by compiler's hard-register-number (see above). */ 911 #define REGISTER_NAMES \ 912 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 913 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 914 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 915 "r24", "r25", "r26", "fp", "sp", "ilink1", "ilink2", "blink", \ 916 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 917 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ 918 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 919 "r56", "r57", "r58", "r59", "lp_count", "cc"} 920 921 /* Entry to the insn conditionalizer. */ 922 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 923 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS) 924 925 /* A C expression which evaluates to true if CODE is a valid 926 punctuation character for use in the `PRINT_OPERAND' macro. */ 927 extern char arc_punct_chars[256]; 928 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 929 arc_punct_chars[(unsigned char) (CHAR)] 930 931 /* Print operand X (an rtx) in assembler syntax to file FILE. 932 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 933 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 934 #define PRINT_OPERAND(FILE, X, CODE) \ 935 arc_print_operand (FILE, X, CODE) 936 937 /* A C compound statement to output to stdio stream STREAM the 938 assembler syntax for an instruction operand that is a memory 939 reference whose address is ADDR. ADDR is an RTL expression. */ 940 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 941 arc_print_operand_address (FILE, ADDR) 942 943 /* This is how to output an element of a case-vector that is absolute. */ 944 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 945 do { \ 946 char label[30]; \ 947 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 948 fprintf (FILE, "\t.word %%st("); \ 949 assemble_name (FILE, label); \ 950 fprintf (FILE, ")\n"); \ 951 } while (0) 952 953 /* This is how to output an element of a case-vector that is relative. */ 954 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 955 do { \ 956 char label[30]; \ 957 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 958 fprintf (FILE, "\t.word %%st("); \ 959 assemble_name (FILE, label); \ 960 fprintf (FILE, "-"); \ 961 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ 962 assemble_name (FILE, label); \ 963 fprintf (FILE, ")\n"); \ 964 } while (0) 965 966 /* The desired alignment for the location counter at the beginning 967 of a loop. */ 968 /* On the ARC, align loops to 32 byte boundaries (cache line size) 969 if -malign-loops. */ 970 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0) 971 972 /* This is how to output an assembler line 973 that says to advance the location counter 974 to a multiple of 2**LOG bytes. */ 975 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 976 do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0) 977 978 /* Debugging information. */ 979 980 /* Generate DBX and DWARF debugging information. */ 981 #define DBX_DEBUGGING_INFO 1 982 983 /* Prefer STABS (for now). */ 984 #undef PREFERRED_DEBUGGING_TYPE 985 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG 986 987 /* Turn off splitting of long stabs. */ 988 #define DBX_CONTIN_LENGTH 0 989 990 /* Miscellaneous. */ 991 992 /* Specify the machine mode that this machine uses 993 for the index in the tablejump instruction. */ 994 #define CASE_VECTOR_MODE Pmode 995 996 /* Define if operations between registers always perform the operation 997 on the full register even if a narrower mode is specified. */ 998 #define WORD_REGISTER_OPERATIONS 999 1000 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1001 will either zero-extend or sign-extend. The value of this macro should 1002 be the code that says which one of the two operations is implicitly 1003 done, UNKNOWN if none. */ 1004 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1005 1006 /* Max number of bytes we can move from memory to memory 1007 in one reasonably fast instruction. */ 1008 #define MOVE_MAX 4 1009 1010 /* Define this to be nonzero if shift instructions ignore all but the low-order 1011 few bits. */ 1012 #define SHIFT_COUNT_TRUNCATED 1 1013 1014 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1015 is done just by pretending it is already truncated. */ 1016 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1017 1018 /* Specify the machine mode that pointers have. 1019 After generation of rtl, the compiler makes no further distinction 1020 between pointers and any other objects of this machine mode. */ 1021 /* ??? The arc doesn't have full 32-bit pointers, but making this PSImode has 1022 its own problems (you have to add extendpsisi2 and trucnsipsi2 but how does 1023 one do it without getting excess code?). Try to avoid it. */ 1024 #define Pmode SImode 1025 1026 /* A function address in a call instruction. */ 1027 #define FUNCTION_MODE SImode 1028 1029 /* alloca should avoid clobbering the old register save area. */ 1030 /* ??? Not defined in tm.texi. */ 1031 #define SETJMP_VIA_SAVE_AREA 1032 1033 /* ARC function types. */ 1034 enum arc_function_type { 1035 ARC_FUNCTION_UNKNOWN, ARC_FUNCTION_NORMAL, 1036 /* These are interrupt handlers. The name corresponds to the register 1037 name that contains the return address. */ 1038 ARC_FUNCTION_ILINK1, ARC_FUNCTION_ILINK2 1039 }; 1040 #define ARC_INTERRUPT_P(TYPE) \ 1041 ((TYPE) == ARC_FUNCTION_ILINK1 || (TYPE) == ARC_FUNCTION_ILINK2) 1042 /* Compute the type of a function from its DECL. */ 1043