1 /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. 2 Copyright (C) 1994-2019 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #ifndef GCC_ARC_H 21 #define GCC_ARC_H 22 23 #include <stdbool.h> 24 25 /* Things to do: 26 27 - incscc, decscc? 28 29 */ 30 31 #define SYMBOL_FLAG_SHORT_CALL (SYMBOL_FLAG_MACH_DEP << 0) 32 #define SYMBOL_FLAG_MEDIUM_CALL (SYMBOL_FLAG_MACH_DEP << 1) 33 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 2) 34 #define SYMBOL_FLAG_CMEM (SYMBOL_FLAG_MACH_DEP << 3) 35 36 #ifndef TARGET_CPU_DEFAULT 37 #define TARGET_CPU_DEFAULT PROCESSOR_arc700 38 #endif 39 40 /* Check if this symbol has a long_call attribute in its declaration */ 41 #define SYMBOL_REF_LONG_CALL_P(X) \ 42 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) 43 44 /* Check if this symbol has a medium_call attribute in its declaration */ 45 #define SYMBOL_REF_MEDIUM_CALL_P(X) \ 46 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_MEDIUM_CALL) != 0) 47 48 /* Check if this symbol has a short_call attribute in its declaration */ 49 #define SYMBOL_REF_SHORT_CALL_P(X) \ 50 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SHORT_CALL) != 0) 51 52 /* Names to predefine in the preprocessor for this target machine. */ 53 #define TARGET_CPU_CPP_BUILTINS() arc_cpu_cpp_builtins (pfile) 54 55 /* Macros enabled by specific command line option. FIXME: to be 56 deprecatd. */ 57 #define CPP_SPEC "\ 58 %{msimd:-D__Xsimd} %{mno-mpy:-D__Xno_mpy} %{mswap:-D__Xswap} \ 59 %{mmin-max:-D__Xmin_max} %{mEA:-D__Xea} \ 60 %{mspfp*:-D__Xspfp} %{mdpfp*:-D__Xdpfp} \ 61 %{mmac-d16:-D__Xxmac_d16} %{mmac-24:-D__Xxmac_24} \ 62 %{mdsp-packa:-D__Xdsp_packa} %{mcrc:-D__Xcrc} %{mdvbf:-D__Xdvbf} \ 63 %{mtelephony:-D__Xtelephony} %{mxy:-D__Xxy} %{mmul64: -D__Xmult32} \ 64 %{mlock:-D__Xlock} %{mswape:-D__Xswape} %{mrtsc:-D__Xrtsc} \ 65 %(subtarget_cpp_spec)" 66 67 #undef CC1_SPEC 68 #define CC1_SPEC "%{EB:%{EL:%emay not use both -EB and -EL}} \ 69 %{EB:-mbig-endian} %{EL:-mlittle-endian} \ 70 %{G*} \ 71 " 72 extern const char *arc_cpu_to_as (int argc, const char **argv); 73 74 #define EXTRA_SPEC_FUNCTIONS \ 75 { "cpu_to_as", arc_cpu_to_as }, 76 77 /* This macro defines names of additional specifications to put in the specs 78 that can be used in various specifications like CC1_SPEC. Its definition 79 is an initializer with a subgrouping for each command option. 80 81 Each subgrouping contains a string constant, that defines the 82 specification name, and a string constant that used by the GCC driver 83 program. 84 85 Do not define this macro if it does not need to do anything. */ 86 #define EXTRA_SPECS \ 87 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 88 SUBTARGET_EXTRA_SPECS 89 90 #ifndef SUBTARGET_EXTRA_SPECS 91 #define SUBTARGET_EXTRA_SPECS 92 #endif 93 94 #ifndef SUBTARGET_CPP_SPEC 95 #define SUBTARGET_CPP_SPEC "" 96 #endif 97 98 #undef ASM_SPEC 99 #define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \ 100 "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} %{mfpu=fpuda*:-mfpuda}" 101 102 #define OPTION_DEFAULT_SPECS \ 103 {"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}}}}}" } 104 105 #ifndef DRIVER_ENDIAN_SELF_SPECS 106 #define DRIVER_ENDIAN_SELF_SPECS "" 107 #endif 108 109 #define DRIVER_SELF_SPECS DRIVER_ENDIAN_SELF_SPECS \ 110 "%{mARC600|mA6: -mcpu=arc600 %<mARC600 %<mA6 %<mARC600}" \ 111 "%{mARC601: -mcpu=arc601 %<mARC601}" \ 112 "%{mARC700|mA7: -mcpu=arc700 %<mARC700 %<mA7}" \ 113 "%{mEA: -mea %<mEA}" 114 115 /* Run-time compilation parameters selecting different hardware subsets. */ 116 117 #define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET) 118 119 #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET) 120 #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \ 121 || TARGET_FP_DP_AX) 122 123 #define SUBTARGET_SWITCHES 124 125 /* Instruction set characteristics. 126 These are internal macros, set by the appropriate -m option. */ 127 128 /* Non-zero means the cpu supports norm instruction. This flag is set by 129 default for A7, and only for pre A7 cores when -mnorm is given. */ 130 #define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET || TARGET_HS) 131 /* Indicate if an optimized floating point emulation library is available. */ 132 #define TARGET_OPTFPE (TARGET_ARC700 || TARGET_FPX_QUARK) 133 134 /* Non-zero means the cpu supports swap instruction. This flag is set by 135 default for A7, and only for pre A7 cores when -mswap is given. */ 136 #define TARGET_SWAP (TARGET_ARC700 || TARGET_SWAP_SET) 137 138 /* Provide some macros for size / scheduling features of the ARC700, so 139 that we can pick & choose features if we get a new cpu family member. */ 140 141 /* Should we try to unalign likely taken branches without a delay slot. */ 142 #define TARGET_UNALIGN_BRANCH (TARGET_ARC700 && !optimize_size) 143 144 /* Should we add padding before a return insn to avoid mispredict? */ 145 #define TARGET_PAD_RETURN (TARGET_ARC700 && !optimize_size) 146 147 /* For an anulled-true delay slot insn for a delayed branch, should we only 148 use conditional execution? */ 149 #define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700 && !TARGET_V2) 150 151 #define TARGET_ARC600 ((arc_selected_cpu->arch_info->arch_id \ 152 == BASE_ARCH_6xx) \ 153 && (TARGET_BARREL_SHIFTER)) 154 #define TARGET_ARC601 ((arc_selected_cpu->arch_info->arch_id \ 155 == BASE_ARCH_6xx) \ 156 && (!TARGET_BARREL_SHIFTER)) 157 #define TARGET_ARC700 (arc_selected_cpu->arch_info->arch_id \ 158 == BASE_ARCH_700) 159 /* An NPS400 is a specialisation of ARC700, so it is correct for NPS400 160 TARGET_ARC700 is true, and TARGET_NPS400 is true. */ 161 #define TARGET_NPS400 ((arc_selected_cpu->arch_info->arch_id \ 162 == BASE_ARCH_700) \ 163 && (arc_selected_cpu->processor \ 164 == PROCESSOR_nps400)) 165 #define TARGET_EM (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_em) 166 #define TARGET_HS (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_hs) 167 #define TARGET_V2 (TARGET_EM || TARGET_HS) 168 169 #ifndef UNALIGNED_ACCESS_DEFAULT 170 #define UNALIGNED_ACCESS_DEFAULT 0 171 #endif 172 173 #ifndef TARGET_NPS_BITOPS_DEFAULT 174 #define TARGET_NPS_BITOPS_DEFAULT 0 175 #endif 176 177 #ifndef TARGET_NPS_CMEM_DEFAULT 178 #define TARGET_NPS_CMEM_DEFAULT 0 179 #endif 180 181 /* Enable the RRQ instruction alternatives. */ 182 183 #define TARGET_RRQ_CLASS TARGET_NPS_BITOPS 184 185 /* Target machine storage layout. */ 186 187 /* We want zero_extract to mean the same 188 no matter what the byte endianness is. */ 189 #define BITS_BIG_ENDIAN 0 190 191 /* Define this if most significant byte of a word is the lowest numbered. */ 192 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN) 193 194 /* Define this if most significant word of a multiword number is the lowest 195 numbered. */ 196 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN) 197 198 /* Width in bits of a "word", which is the contents of a machine register. 199 Note that this is not necessarily the width of data type `int'; 200 if using 16-bit ints on a 68000, this would still be 32. 201 But on a machine with 16-bit registers, this would be 16. */ 202 #define BITS_PER_WORD 32 203 204 /* Width of a word, in units (bytes). */ 205 #define UNITS_PER_WORD 4 206 207 /* Define this macro if it is advisable to hold scalars in registers 208 in a wider mode than that declared by the program. In such cases, 209 the value is constrained to be within the bounds of the declared 210 type, but kept valid in the wider mode. The signedness of the 211 extension may differ from that of the type. */ 212 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 213 if (GET_MODE_CLASS (MODE) == MODE_INT \ 214 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 215 { \ 216 (MODE) = SImode; \ 217 } 218 219 /* Width in bits of a pointer. 220 See also the macro `Pmode' defined below. */ 221 #define POINTER_SIZE 32 222 223 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 224 #define PARM_BOUNDARY 32 225 226 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 227 /* TOCHECK: Changed from 64 to 32 */ 228 #define STACK_BOUNDARY 32 229 230 /* ALIGN FRAMES on word boundaries. */ 231 #define ARC_STACK_ALIGN(LOC) \ 232 (((LOC) + STACK_BOUNDARY / BITS_PER_UNIT - 1) & -STACK_BOUNDARY/BITS_PER_UNIT) 233 234 /* Allocation boundary (in *bits*) for the code of a function. */ 235 #define FUNCTION_BOUNDARY 32 236 237 /* Alignment of field after `int : 0' in a structure. */ 238 #define EMPTY_FIELD_BOUNDARY 32 239 240 /* Every structure's size must be a multiple of this. */ 241 #define STRUCTURE_SIZE_BOUNDARY 8 242 243 /* A bitfield declared as `int' forces `int' alignment for the struct. */ 244 #define PCC_BITFIELD_TYPE_MATTERS 1 245 246 /* An expression for the alignment of a structure field FIELD if the 247 alignment computed in the usual way (including applying of 248 `BIGGEST_ALIGNMENT' and `BIGGEST_FIELD_ALIGNMENT' to the 249 alignment) is COMPUTED. It overrides alignment only if the field 250 alignment has not been set by the `__attribute__ ((aligned (N)))' 251 construct. 252 */ 253 254 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ 255 (TYPE_MODE (strip_array_types (TYPE)) == DFmode \ 256 ? MIN ((COMPUTED), 32) : (COMPUTED)) 257 258 259 260 /* No data type wants to be aligned rounder than this. */ 261 /* This is bigger than currently necessary for the ARC. If 8 byte floats are 262 ever added it's not clear whether they'll need such alignment or not. For 263 now we assume they will. We can always relax it if necessary but the 264 reverse isn't true. */ 265 /* TOCHECK: Changed from 64 to 32 */ 266 #define BIGGEST_ALIGNMENT 32 267 268 /* The best alignment to use in cases where we have a choice. */ 269 #define FASTEST_ALIGNMENT 32 270 271 /* Make arrays of chars word-aligned for the same reasons. */ 272 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 273 (TREE_CODE (TYPE) == ARRAY_TYPE \ 274 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 275 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 276 277 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 278 (TREE_CODE (TYPE) == ARRAY_TYPE \ 279 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 280 && arc_size_opt_level < 3 \ 281 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 282 283 /* Set this nonzero if move instructions will actually fail to work 284 when given unaligned data. */ 285 /* On the ARC the lower address bits are masked to 0 as necessary. The chip 286 won't croak when given an unaligned address, but the insn will still fail 287 to produce the correct result. */ 288 #define STRICT_ALIGNMENT (!unaligned_access) 289 290 /* Layout of source language data types. */ 291 292 #define SHORT_TYPE_SIZE 16 293 #define INT_TYPE_SIZE 32 294 #define LONG_TYPE_SIZE 32 295 #define LONG_LONG_TYPE_SIZE 64 296 #define FLOAT_TYPE_SIZE 32 297 #define DOUBLE_TYPE_SIZE 64 298 #define LONG_DOUBLE_TYPE_SIZE 64 299 300 /* Define this as 1 if `char' should by default be signed; else as 0. */ 301 #define DEFAULT_SIGNED_CHAR 0 302 303 #undef SIZE_TYPE 304 #define SIZE_TYPE "unsigned int" 305 306 #undef PTRDIFF_TYPE 307 #define PTRDIFF_TYPE "int" 308 309 #undef WCHAR_TYPE 310 #define WCHAR_TYPE "int" 311 312 #undef WCHAR_TYPE_SIZE 313 #define WCHAR_TYPE_SIZE 32 314 315 /* Standard register usage. */ 316 317 /* Number of actual hardware registers. 318 The hardware registers are assigned numbers for the compiler 319 from 0 to just below FIRST_PSEUDO_REGISTER. 320 All registers that the compiler knows about must be given numbers, 321 even those that are not normally considered general registers. 322 323 Registers 61, 62, and 63 are not really registers and we needn't treat 324 them as such. We still need a register for the condition code and 325 argument pointer. */ 326 327 /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs 328 r144, r145 = ARG_POINTER, FRAME_POINTER 329 and therefore the pseudo registers start from r146. */ 330 #define FIRST_PSEUDO_REGISTER 146 331 332 /* 1 for registers that have pervasive standard uses 333 and are not available for the register allocator. 334 335 0-28 - general purpose registers 336 29 - ilink1 (interrupt link register) 337 30 - ilink2 (interrupt link register) 338 31 - blink (branch link register) 339 32-59 - reserved for extensions 340 60 - LP_COUNT 341 61 - condition code 342 62 - argument pointer 343 63 - program counter 344 345 FWIW, this is how the 61-63 encodings are used by the hardware: 346 61 - reserved 347 62 - long immediate data indicator 348 63 - PCL (program counter aligned to 32 bit, read-only) 349 350 The general purpose registers are further broken down into: 351 352 0-7 - arguments/results 353 8-12 - call used (r11 - static chain pointer) 354 13-25 - call saved 355 26 - global pointer 356 27 - frame pointer 357 28 - stack pointer 358 29 - ilink1 359 30 - ilink2 360 31 - return address register 361 362 By default, the extension registers are not available. */ 363 /* Present implementations only have VR0-VR23 only. */ 364 #define FIXED_REGISTERS \ 365 { 0, 0, 0, 0, 0, 0, 0, 0, \ 366 0, 0, 0, 0, 0, 0, 0, 0, \ 367 0, 0, 0, 0, 0, 0, 0, 0, \ 368 0, 0, 1, 0, 1, 1, 1, 1, \ 369 \ 370 1, 1, 1, 1, 1, 1, 1, 1, \ 371 0, 0, 0, 0, 1, 1, 1, 1, \ 372 1, 1, 1, 1, 1, 1, 1, 1, \ 373 1, 1, 1, 1, 1, 1, 1, 1, \ 374 \ 375 0, 0, 0, 0, 0, 0, 0, 0, \ 376 0, 0, 0, 0, 0, 0, 0, 0, \ 377 0, 0, 0, 0, 0, 0, 0, 0, \ 378 1, 1, 1, 1, 1, 1, 1, 1, \ 379 \ 380 1, 1, 1, 1, 1, 1, 1, 1, \ 381 1, 1, 1, 1, 1, 1, 1, 1, \ 382 1, 1, 1, 1, 1, 1, 1, 1, \ 383 1, 1, 1, 1, 1, 1, 1, 1, \ 384 \ 385 0, 0, 0, 0, 0, 0, 0, 0, \ 386 0, 0, 0, 0, 0, 0, 0, 0, \ 387 1, 1} 388 389 /* 1 for registers not available across function calls. 390 These must include the FIXED_REGISTERS and also any 391 registers that can be used without being saved. 392 The latter must include the registers where values are returned 393 and the register where structure-value addresses are passed. 394 Aside from that, you can include as many other registers as you like. */ 395 #define CALL_USED_REGISTERS \ 396 { \ 397 1, 1, 1, 1, 1, 1, 1, 1, \ 398 1, 1, 1, 1, 1, 0, 0, 0, \ 399 0, 0, 0, 0, 0, 0, 0, 0, \ 400 0, 0, 1, 0, 1, 1, 1, 1, \ 401 \ 402 1, 1, 1, 1, 1, 1, 1, 1, \ 403 1, 1, 1, 1, 1, 1, 1, 1, \ 404 1, 1, 1, 1, 1, 1, 1, 1, \ 405 1, 1, 1, 1, 1, 1, 1, 1, \ 406 \ 407 0, 0, 0, 0, 0, 0, 0, 0, \ 408 0, 0, 0, 0, 0, 0, 0, 0, \ 409 0, 0, 0, 0, 0, 0, 0, 0, \ 410 1, 1, 1, 1, 1, 1, 1, 1, \ 411 \ 412 1, 1, 1, 1, 1, 1, 1, 1, \ 413 1, 1, 1, 1, 1, 1, 1, 1, \ 414 1, 1, 1, 1, 1, 1, 1, 1, \ 415 1, 1, 1, 1, 1, 1, 1, 1, \ 416 \ 417 0, 0, 0, 0, 0, 0, 0, 0, \ 418 0, 0, 0, 0, 0, 0, 0, 0, \ 419 1, 1} 420 421 /* If defined, an initializer for a vector of integers, containing the 422 numbers of hard registers in the order in which GCC should 423 prefer to use them (from most preferred to least). */ 424 #define REG_ALLOC_ORDER \ 425 { \ 426 /* General registers. */ \ 427 2, 3, 12, 13, 14, 15, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, \ 428 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 30, \ 429 /* Extension core registers. */ \ 430 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 431 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ 432 /* VR regs. */ \ 433 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ 434 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ 435 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ 436 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \ 437 124, 125, 126, 127, \ 438 /* DMA registers. */ \ 439 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, \ 440 142, 143, \ 441 /* Register not used for general use. */ \ 442 62, FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 443 SP_REG, ILINK1_REG, RETURN_ADDR_REGNUM, LP_COUNT, CC_REG, PCL_REG \ 444 } 445 446 /* Use different register alloc ordering for Thumb. */ 447 #define ADJUST_REG_ALLOC_ORDER arc_adjust_reg_alloc_order () 448 449 /* Tell IRA to use the order we define rather than messing it up with its 450 own cost calculations. */ 451 #define HONOR_REG_ALLOC_ORDER 1 452 453 /* Internal macros to classify a register number as to whether it's a 454 general purpose register for compact insns (r0-r3,r12-r15), or 455 stack pointer (r28). */ 456 457 #define COMPACT_GP_REG_P(REGNO) \ 458 (((signed)(REGNO) >= 0 && (REGNO) <= 3) || ((REGNO) >= 12 && (REGNO) <= 15)) 459 #define SP_REG_P(REGNO) ((REGNO) == 28) 460 461 462 463 /* Register classes and constants. */ 464 465 /* Define the classes of registers for register constraints in the 466 machine description. Also define ranges of constants. 467 468 One of the classes must always be named ALL_REGS and include all hard regs. 469 If there is more than one class, another class must be named NO_REGS 470 and contain no registers. 471 472 The name GENERAL_REGS must be the name of a class (or an alias for 473 another name such as ALL_REGS). This is the class of registers 474 that is allowed by "g" or "r" in a register constraint. 475 Also, registers outside this class are allocated only when 476 instructions express preferences for them. 477 478 The classes must be numbered in nondecreasing order; that is, 479 a larger-numbered class must never be contained completely 480 in a smaller-numbered class. 481 482 For any two classes, it is very desirable that there be another 483 class that represents their union. 484 485 It is important that any condition codes have class NO_REGS. 486 See `register_operand'. */ 487 488 enum reg_class 489 { 490 NO_REGS, 491 R0_REGS, /* 'x' */ 492 R0R1_CD_REGS, /* 'Rsd' */ 493 R0R3_CD_REGS, /* 'Rcd' */ 494 ARCOMPACT16_REGS, /* 'q' */ 495 SIBCALL_REGS, /* "Rsc" */ 496 AC16_H_REGS, /* 'h' */ 497 DOUBLE_REGS, /* 'D' */ 498 GENERAL_REGS, /* 'r' */ 499 SIMD_VR_REGS, /* 'v' */ 500 SIMD_DMA_CONFIG_REGS, /* 'd' */ 501 ALL_REGS, 502 LIM_REG_CLASSES 503 }; 504 505 #define N_REG_CLASSES (int) LIM_REG_CLASSES 506 507 /* Give names of register classes as strings for dump file. */ 508 #define REG_CLASS_NAMES \ 509 { \ 510 "NO_REGS", \ 511 "R0_REGS", \ 512 "R0R1_CD_REGS", \ 513 "R0R3_CD_REGS", \ 514 "ARCOMPACT16_REGS", \ 515 "SIBCALL_REGS", \ 516 "AC16_H_REGS", \ 517 "DOUBLE_REGS", \ 518 "GENERAL_REGS", \ 519 "SIMD_VR_REGS", \ 520 "SIMD_DMA_CONFIG_REGS", \ 521 "ALL_REGS" \ 522 } 523 524 /* Define which registers fit in which classes. 525 This is an initializer for a vector of HARD_REG_SET 526 of length N_REG_CLASSES. */ 527 528 #define REG_CLASS_CONTENTS \ 529 { \ 530 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* NO_REGS. */\ 531 {0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'x'. */ \ 532 {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsd'. */ \ 533 {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rcd'. */ \ 534 {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'q'. */ \ 535 {0x00001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsc'. */ \ 536 {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'h'. */ \ 537 {0x00000000, 0x00000f00, 0x00000000, 0x00000000, 0x00000000}, /* 'D'. */ \ 538 {0xffffffff, 0x8fffffff, 0x00000000, 0x00000000, 0x00030000}, /* 'r'. */ \ 539 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000}, /* 'v'. */ \ 540 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'd'. */ \ 541 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* ALL_REGS. */\ 542 } 543 544 /* Local macros to mark the first and last regs of different classes. */ 545 #define ARC_FIRST_SIMD_VR_REG 64 546 #define ARC_LAST_SIMD_VR_REG 127 547 548 #define ARC_FIRST_SIMD_DMA_CONFIG_REG 128 549 #define ARC_FIRST_SIMD_DMA_CONFIG_IN_REG 128 550 #define ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG 136 551 #define ARC_LAST_SIMD_DMA_CONFIG_REG 143 552 553 /* ARCv2 double-register accumulator. */ 554 #define ACC_REG_FIRST 58 555 #define ACC_REG_LAST 59 556 #define ACCL_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST + 1 : ACC_REG_FIRST) 557 #define ACCH_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST : ACC_REG_FIRST + 1) 558 559 /* The same information, inverted: 560 Return the class number of the smallest class containing 561 reg number REGNO. This could be a conditional expression 562 or could index an array. */ 563 564 extern enum reg_class arc_regno_reg_class[]; 565 566 #define REGNO_REG_CLASS(REGNO) (arc_regno_reg_class[REGNO]) 567 568 /* The class value for valid index registers. An index register is 569 one used in an address where its value is either multiplied by 570 a scale factor or added to another register (as well as added to a 571 displacement). */ 572 573 #define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS) 574 575 /* The class value for valid base registers. A base register is one used in 576 an address which is the register value plus a displacement. */ 577 578 #define BASE_REG_CLASS GENERAL_REGS 579 580 /* These assume that REGNO is a hard or pseudo reg number. 581 They give nonzero only if REGNO is a hard reg of the suitable class 582 or a pseudo reg currently allocated to a suitable hard reg. 583 Since they use reg_renumber, they are safe only once reg_renumber 584 has been allocated, which happens in local-alloc.c. */ 585 #define REGNO_OK_FOR_BASE_P(REGNO) \ 586 ((REGNO) < 29 \ 587 || ((REGNO) == ARG_POINTER_REGNUM) \ 588 || ((REGNO) == FRAME_POINTER_REGNUM) \ 589 || ((REGNO) == PCL_REG) \ 590 || ((unsigned) reg_renumber[REGNO] < 29) \ 591 || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \ 592 || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \ 593 || (fixed_regs[REGNO] == 0 && (REGNO) == R30_REG)) 594 595 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) 596 597 /* Given an rtx X being reloaded into a reg required to be 598 in class CLASS, return the class of reg to actually use. 599 In general this is just CLASS; but on some machines 600 in some cases it is preferable to use a more restrictive class. */ 601 602 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 603 arc_preferred_reload_class((X), (CLASS)) 604 605 extern enum reg_class arc_preferred_reload_class (rtx, enum reg_class); 606 607 /* Return the maximum number of consecutive registers 608 needed to represent mode MODE in a register of class CLASS. */ 609 610 #define CLASS_MAX_NREGS(CLASS, MODE) \ 611 (( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1: \ 612 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 613 614 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200) 615 #define SMALL_INT_RANGE(X, OFFSET, SHIFT) \ 616 ((unsigned) (((X) >> (SHIFT)) + 0x100) \ 617 < 0x200 - ((unsigned) (OFFSET) >> (SHIFT))) 618 #define SIGNED_INT12(X) ((unsigned) ((X) + 0x800) < 0x1000) 619 #define SIGNED_INT16(X) ((unsigned) ((X) + 0x8000) < 0x10000) 620 #define LARGE_INT(X) \ 621 (((X) < 0) \ 622 ? (X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \ 623 : (unsigned HOST_WIDE_INT) (X) <= (unsigned HOST_WIDE_INT) 0xffffffff) 624 #define UNSIGNED_INT3(X) ((unsigned) (X) < 0x8) 625 #define UNSIGNED_INT5(X) ((unsigned) (X) < 0x20) 626 #define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40) 627 #define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80) 628 #define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100) 629 #define UNSIGNED_INT12(X) ((unsigned) (X) < 0x800) 630 #define UNSIGNED_INT16(X) ((unsigned) (X) < 0x10000) 631 #define IS_ONE(X) ((X) == 1) 632 #define IS_ZERO(X) ((X) == 0) 633 634 /* Stack layout and stack pointer usage. */ 635 636 /* Define this macro if pushing a word onto the stack moves the stack 637 pointer to a smaller address. */ 638 #define STACK_GROWS_DOWNWARD 1 639 640 /* Define this if the nominal address of the stack frame 641 is at the high-address end of the local variables; 642 that is, each additional local variable allocated 643 goes at a more negative offset in the frame. */ 644 #define FRAME_GROWS_DOWNWARD 1 645 646 /* Offset from the stack pointer register to the first location at which 647 outgoing arguments are placed. */ 648 #define STACK_POINTER_OFFSET (0) 649 650 /* Offset of first parameter from the argument pointer register value. */ 651 #define FIRST_PARM_OFFSET(FNDECL) (0) 652 653 /* A C expression whose value is RTL representing the address in a 654 stack frame where the pointer to the caller's frame is stored. 655 Assume that FRAMEADDR is an RTL expression for the address of the 656 stack frame itself. 657 658 If you don't define this macro, the default is to return the value 659 of FRAMEADDR--that is, the stack frame address is also the address 660 of the stack word that points to the previous frame. */ 661 /* ??? unfinished */ 662 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/ 663 664 /* A C expression whose value is RTL representing the value of the 665 return address for the frame COUNT steps up from the current frame. 666 FRAMEADDR is the frame pointer of the COUNT frame, or the frame 667 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' 668 is defined. */ 669 /* The current return address is in r31. The return address of anything 670 farther back is at [%fp,4]. */ 671 672 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 673 arc_return_addr_rtx(COUNT,FRAME) 674 675 /* Register to use for pushing function arguments. */ 676 #define STACK_POINTER_REGNUM 28 677 678 /* Base register for access to local variables of the function. */ 679 #define FRAME_POINTER_REGNUM 145 680 #define HARD_FRAME_POINTER_REGNUM 27 681 682 /* Base register for access to arguments of the function. This register 683 will be eliminated into either fp or sp. */ 684 #define ARG_POINTER_REGNUM 144 685 686 #define RETURN_ADDR_REGNUM 31 687 688 /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */ 689 /* Register in which static-chain is passed to a function. This must 690 not be a register used by the prologue. */ 691 #define STATIC_CHAIN_REGNUM 11 692 693 /* Function argument passing. */ 694 695 /* If defined, the maximum amount of space required for outgoing 696 arguments will be computed and placed into the variable 697 `crtl->outgoing_args_size'. No space will be pushed 698 onto the stack for each call; instead, the function prologue should 699 increase the stack frame size by this amount. */ 700 #define ACCUMULATE_OUTGOING_ARGS 1 701 702 /* Define a data type for recording info about an argument list 703 during the scan of that argument list. This data type should 704 hold all necessary information about the function itself 705 and about the args processed so far, enough to enable macros 706 such as FUNCTION_ARG to determine where the next arg should go. */ 707 #define CUMULATIVE_ARGS int 708 709 /* Initialize a variable CUM of type CUMULATIVE_ARGS 710 for a call to a function whose data type is FNTYPE. 711 For a library call, FNTYPE is 0. */ 712 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \ 713 ((CUM) = 0) 714 715 /* The number of registers used for parameter passing. Local to this file. */ 716 #define MAX_ARC_PARM_REGS (TARGET_RF16 ? 4 : 8) 717 718 /* 1 if N is a possible register number for function argument passing. */ 719 #define FUNCTION_ARG_REGNO_P(N) \ 720 ((unsigned) (N) < MAX_ARC_PARM_REGS) 721 722 /* The ROUND_ADVANCE* macros are local to this file. */ 723 /* Round SIZE up to a word boundary. */ 724 #define ROUND_ADVANCE(SIZE) \ 725 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 726 727 /* Round arg MODE/TYPE up to the next word boundary. */ 728 #define ROUND_ADVANCE_ARG(MODE, TYPE) \ 729 ((MODE) == BLKmode \ 730 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ 731 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) 732 733 #define ARC_FUNCTION_ARG_BOUNDARY(MODE,TYPE) PARM_BOUNDARY 734 /* Round CUM up to the necessary point for argument MODE/TYPE. */ 735 /* N.B. Vectors have alignment exceeding BIGGEST_ALIGNMENT. 736 ARC_FUNCTION_ARG_BOUNDARY reduces this to no more than 32 bit. */ 737 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \ 738 ((((CUM) - 1) | (ARC_FUNCTION_ARG_BOUNDARY ((MODE), (TYPE)) - 1)/BITS_PER_WORD)\ 739 + 1) 740 741 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in 742 a reg. This includes arguments that have to be passed by reference as the 743 pointer to them is passed in a reg if one is available (and that is what 744 we're given). 745 When passing arguments NAMED is always 1. When receiving arguments NAMED 746 is 1 for each argument except the last in a stdarg/varargs function. In 747 a stdarg function we want to treat the last named arg as named. In a 748 varargs function we want to treat the last named arg (which is 749 `__builtin_va_alist') as unnamed. 750 This macro is only used in this file. */ 751 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 752 ((CUM) < MAX_ARC_PARM_REGS) 753 754 755 /* Function results. */ 756 757 /* Define how to find the value returned by a library function 758 assuming the value has mode MODE. */ 759 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) 760 761 /* 1 if N is a possible register number for a function value 762 as seen by the caller. */ 763 /* ??? What about r1 in DI/DF values. */ 764 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 765 766 /* Tell GCC to use RETURN_IN_MEMORY. */ 767 #define DEFAULT_PCC_STRUCT_RETURN 0 768 769 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 770 the stack pointer does not matter. The value is tested only in 771 functions that have frame pointers. 772 No definition is equivalent to always zero. */ 773 #define EXIT_IGNORE_STACK 0 774 775 #define EPILOGUE_USES(REGNO) arc_epilogue_uses ((REGNO)) 776 777 #define EH_USES(REGNO) arc_eh_uses((REGNO)) 778 779 /* Definitions for register eliminations. 780 781 This is an array of structures. Each structure initializes one pair 782 of eliminable registers. The "from" register number is given first, 783 followed by "to". Eliminations of the same "from" register are listed 784 in order of preference. 785 786 We have two registers that can be eliminated on the ARC. First, the 787 argument pointer register can always be eliminated in favor of the stack 788 pointer register or frame pointer register. Secondly, the frame pointer 789 register can often be eliminated in favor of the stack pointer register. 790 */ 791 792 #define ELIMINABLE_REGS \ 793 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 794 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 795 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 796 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 797 798 /* Define the offset between two registers, one to be eliminated, and the other 799 its replacement, at the start of a routine. */ 800 extern int arc_initial_elimination_offset(int from, int to); 801 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 802 (OFFSET) = arc_initial_elimination_offset ((FROM), (TO)) 803 804 /* All the work done in PROFILE_HOOK, but still required. */ 805 #undef FUNCTION_PROFILER 806 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 807 808 #define NO_PROFILE_COUNTERS 1 809 810 /* Trampolines. */ 811 812 /* Length in units of the trampoline for entering a nested function. */ 813 #define TRAMPOLINE_SIZE 16 814 815 /* Alignment required for a trampoline in bits . */ 816 /* For actual data alignment we just need 32, no more than the stack; 817 however, to reduce cache coherency issues, we want to make sure that 818 trampoline instructions always appear the same in any given cache line. */ 819 #define TRAMPOLINE_ALIGNMENT 256 820 821 /* Library calls. */ 822 823 /* Addressing modes, and classification of registers for them. */ 824 825 /* Maximum number of registers that can appear in a valid memory address. */ 826 /* The `ld' insn allows 2, but the `st' insn only allows 1. */ 827 #define MAX_REGS_PER_ADDRESS 1 828 829 /* We have pre inc/dec (load/store with update). */ 830 #define HAVE_PRE_INCREMENT 1 831 #define HAVE_PRE_DECREMENT 1 832 #define HAVE_POST_INCREMENT 1 833 #define HAVE_POST_DECREMENT 1 834 #define HAVE_PRE_MODIFY_DISP 1 835 #define HAVE_POST_MODIFY_DISP 1 836 #define HAVE_PRE_MODIFY_REG 1 837 #define HAVE_POST_MODIFY_REG 1 838 /* ??? should also do PRE_MODIFY_REG / POST_MODIFY_REG, but that requires 839 a special predicate for the memory operand of stores, like for the SH. */ 840 841 /* Recognize any constant value that is a valid address. */ 842 #define CONSTANT_ADDRESS_P(X) \ 843 (flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)): \ 844 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 845 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)) 846 847 /* Is the argument a const_int rtx, containing an exact power of 2 */ 848 #define IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X)) 849 #define IS_POWEROF2_OR_0_P(X) (! ( (X) & ((X) - 1))) 850 851 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 852 and check its validity for a certain class. 853 We have two alternate definitions for each of them. 854 The *_NONSTRICT definition accepts all pseudo regs; the other rejects 855 them unless they have been allocated suitable hard regs. 856 857 Most source files want to accept pseudo regs in the hope that 858 they will get allocated to the class that the insn wants them to be in. 859 Source files for reload pass need to be strict. 860 After reload, it makes no difference, since pseudo regs have 861 been eliminated by then. */ 862 863 /* Nonzero if X is a hard reg that can be used as an index 864 or if it is a pseudo reg. */ 865 #define REG_OK_FOR_INDEX_P_NONSTRICT(X) \ 866 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \ 867 || REGNO_OK_FOR_BASE_P (REGNO (X))) 868 869 /* Nonzero if X is a hard reg that can be used as a base reg 870 or if it is a pseudo reg. */ 871 #define REG_OK_FOR_BASE_P_NONSTRICT(X) \ 872 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \ 873 || REGNO_OK_FOR_BASE_P (REGNO (X))) 874 875 /* Nonzero if X is a hard reg that can be used as an index. */ 876 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 877 /* Nonzero if X is a hard reg that can be used as a base reg. */ 878 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 879 880 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 881 that is a valid memory address for an instruction. 882 The MODE argument is the machine mode for the MEM expression 883 that wants to use this address. */ 884 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm] 885 but the `st' insn only allows [reg],[reg+shimm],[limm]. 886 The only thing we can do is only allow the most strict case `st' and hope 887 other parts optimize out the restrictions for `ld'. */ 888 889 #define RTX_OK_FOR_BASE_P(X, STRICT) \ 890 (REG_P (X) \ 891 && ((STRICT) ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P_NONSTRICT (X))) 892 893 #define RTX_OK_FOR_INDEX_P(X, STRICT) \ 894 (REG_P (X) \ 895 && ((STRICT) ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P_NONSTRICT (X))) 896 897 /* A C compound statement that attempts to replace X, which is an address 898 that needs reloading, with a valid memory address for an operand of 899 mode MODE. WIN is a C statement label elsewhere in the code. 900 901 We try to get a normal form 902 of the address. That will allow inheritance of the address reloads. */ 903 904 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 905 do { \ 906 if (arc_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ 907 goto WIN; \ 908 } while (0) 909 910 /* Reading lp_count for anything but the lp instruction is very slow on the 911 ARC700. */ 912 #define DONT_REALLOC(REGNO,MODE) \ 913 (TARGET_ARC700 && (REGNO) == 60) 914 915 916 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 917 return the mode to be used for the comparison. */ 918 /*extern machine_mode arc_select_cc_mode ();*/ 919 #define SELECT_CC_MODE(OP, X, Y) \ 920 arc_select_cc_mode (OP, X, Y) 921 922 /* Return non-zero if SELECT_CC_MODE will never return MODE for a 923 floating point inequality comparison. */ 924 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ 925 926 /* Costs. */ 927 928 /* The cost of a branch insn. */ 929 /* ??? What's the right value here? Branches are certainly more 930 expensive than reg->reg moves. */ 931 #define BRANCH_COST(speed_p, predictable_p) 2 932 933 /* Scc sets the destination to 1 and then conditionally zeroes it. 934 Best case, ORed SCCs can be made into clear - condset - condset. 935 But it could also end up as five insns. So say it costs four on 936 average. 937 These extra instructions - and the second comparison - will also be 938 an extra cost if the first comparison would have been decisive. 939 So get an average saving, with a probability of the first branch 940 beging decisive of p0, we want: 941 p0 * (branch_cost - 4) > (1 - p0) * 5 942 ??? We don't get to see that probability to evaluate, so we can 943 only wildly guess that it might be 50%. 944 ??? The compiler also lacks the notion of branch predictability. */ 945 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 946 (BRANCH_COST (optimize_function_for_speed_p (cfun), \ 947 false) > 9) 948 949 /* Nonzero if access to memory by bytes is slow and undesirable. 950 For RISC chips, it means that access to memory by bytes is no 951 better than access by words when possible, so grab a whole word 952 and maybe make use of that. */ 953 #define SLOW_BYTE_ACCESS 0 954 955 /* Define this macro if it is as good or better to call a constant 956 function address than to call an address kept in a register. */ 957 /* On the ARC, calling through registers is slow. */ 958 #define NO_FUNCTION_CSE 1 959 960 /* Section selection. */ 961 /* WARNING: These section names also appear in dwarfout.c. */ 962 963 #define TEXT_SECTION_ASM_OP "\t.section\t.text" 964 #define DATA_SECTION_ASM_OP "\t.section\t.data" 965 966 #define BSS_SECTION_ASM_OP "\t.section\t.bss" 967 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata" 968 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss" 969 970 /* Expression whose value is a string, including spacing, containing the 971 assembler operation to identify the following data as initialization/termination 972 code. If not defined, GCC will assume such a section does not exist. */ 973 #define INIT_SECTION_ASM_OP "\t.section\t.init" 974 #define FINI_SECTION_ASM_OP "\t.section\t.fini" 975 976 /* Define this macro if jump tables (for tablejump insns) should be 977 output in the text section, along with the assembler instructions. 978 Otherwise, the readonly data section is used. 979 This macro is irrelevant if there is no separate readonly data section. */ 980 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic || CASE_VECTOR_PC_RELATIVE) 981 982 /* For DWARF. Marginally different than default so output is "prettier" 983 (and consistent with above). */ 984 #define PUSHSECTION_FORMAT "\t%s %s\n" 985 986 /* Tell crtstuff.c we're using ELF. */ 987 #define OBJECT_FORMAT_ELF 988 989 /* PIC */ 990 991 /* The register number of the register used to address a table of static 992 data addresses in memory. In some cases this register is defined by a 993 processor's ``application binary interface'' (ABI). When this macro 994 is defined, RTL is generated for this register once, as with the stack 995 pointer and frame pointer registers. If this macro is not defined, it 996 is up to the machine-dependent files to allocate such a register (if 997 necessary). */ 998 #define PIC_OFFSET_TABLE_REGNUM 26 999 1000 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is 1001 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM 1002 is not defined. */ 1003 /* This register is call-saved on the ARC. */ 1004 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ 1005 1006 /* A C expression that is nonzero if X is a legitimate immediate 1007 operand on the target machine when generating position independent code. 1008 You can assume that X satisfies CONSTANT_P, so you need not 1009 check this. You can also assume `flag_pic' is true, so you need not 1010 check it either. You need not define this macro if all constants 1011 (including SYMBOL_REF) can be immediate operands when generating 1012 position independent code. */ 1013 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1014 (!arc_raw_symbolic_reference_mentioned_p ((X), true)) 1015 1016 /* PIC and small data don't mix on ARC because they use the same register. */ 1017 #define SDATA_BASE_REGNUM 26 1018 1019 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1020 (flag_pic \ 1021 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 1022 : DW_EH_PE_absptr) 1023 1024 /* Control the assembler format that we output. */ 1025 1026 /* A C string constant describing how to begin a comment in the target 1027 assembler language. The compiler assumes that the comment will 1028 end at the end of the line. */ 1029 /* Gas needs this to be "#" in order to recognize line directives. */ 1030 #define ASM_COMMENT_START "#" 1031 1032 /* Output to assembler file text saying following lines 1033 may contain character constants, extra white space, comments, etc. */ 1034 #undef ASM_APP_ON 1035 #define ASM_APP_ON "" 1036 1037 /* Output to assembler file text saying following lines 1038 no longer contain unusual constructs. */ 1039 #undef ASM_APP_OFF 1040 #define ASM_APP_OFF "" 1041 1042 /* Globalizing directive for a label. */ 1043 #define GLOBAL_ASM_OP "\t.global\t" 1044 1045 /* This is how to output an assembler line defining a `char' constant. */ 1046 #define ASM_OUTPUT_CHAR(FILE, VALUE) \ 1047 ( fprintf (FILE, "\t.byte\t"), \ 1048 output_addr_const (FILE, (VALUE)), \ 1049 fprintf (FILE, "\n")) 1050 1051 /* This is how to output an assembler line defining a `short' constant. */ 1052 #define ASM_OUTPUT_SHORT(FILE, VALUE) \ 1053 ( fprintf (FILE, "\t.hword\t"), \ 1054 output_addr_const (FILE, (VALUE)), \ 1055 fprintf (FILE, "\n")) 1056 1057 /* This is how to output an assembler line defining an `int' constant. 1058 We also handle symbol output here. Code addresses must be right shifted 1059 by 2 because that's how the jump instruction wants them. */ 1060 #define ASM_OUTPUT_INT(FILE, VALUE) \ 1061 do { \ 1062 fprintf (FILE, "\t.word\t"); \ 1063 if (GET_CODE (VALUE) == LABEL_REF) \ 1064 { \ 1065 fprintf (FILE, "%%st(@"); \ 1066 output_addr_const (FILE, (VALUE)); \ 1067 fprintf (FILE, ")"); \ 1068 } \ 1069 else \ 1070 output_addr_const (FILE, (VALUE)); \ 1071 fprintf (FILE, "\n"); \ 1072 } while (0) 1073 1074 /* This is how to output an assembler line defining a `float' constant. */ 1075 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \ 1076 { \ 1077 long t; \ 1078 char str[30]; \ 1079 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ 1080 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ 1081 fprintf (FILE, "\t.word\t0x%lx %s %s\n", \ 1082 t, ASM_COMMENT_START, str); \ 1083 } 1084 1085 /* This is how to output an assembler line defining a `double' constant. */ 1086 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \ 1087 { \ 1088 long t[2]; \ 1089 char str[30]; \ 1090 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ 1091 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ 1092 fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \ 1093 t[0], ASM_COMMENT_START, str, t[1]); \ 1094 } 1095 1096 /* This is how to output the definition of a user-level label named NAME, 1097 such as the label on a static function or variable NAME. */ 1098 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1099 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 1100 1101 #define ASM_NAME_P(NAME) ( NAME[0]=='*') 1102 1103 /* This is how to output a reference to a user-level label named NAME. 1104 `assemble_name' uses this. */ 1105 /* We work around a dwarfout.c deficiency by watching for labels from it and 1106 not adding the '_' prefix. There is a comment in 1107 dwarfout.c that says it should be using ASM_OUTPUT_INTERNAL_LABEL. */ 1108 #define ASM_OUTPUT_LABELREF(FILE, NAME1) \ 1109 do { \ 1110 const char *NAME; \ 1111 NAME = (*targetm.strip_name_encoding)(NAME1); \ 1112 if ((NAME)[0] == '.' && (NAME)[1] == 'L') \ 1113 fprintf (FILE, "%s", NAME); \ 1114 else \ 1115 { \ 1116 if (!ASM_NAME_P (NAME1)) \ 1117 fprintf (FILE, "%s", user_label_prefix); \ 1118 fprintf (FILE, "%s", NAME); \ 1119 } \ 1120 } while (0) 1121 1122 /* This is how to output a reference to a symbol_ref / label_ref as 1123 (part of) an operand. To disambiguate from register names like 1124 a1 / a2 / status etc, symbols are preceded by '@'. */ 1125 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \ 1126 ASM_OUTPUT_LABEL_REF ((FILE), XSTR ((SYM), 0)) 1127 #define ASM_OUTPUT_LABEL_REF(FILE,STR) \ 1128 do \ 1129 { \ 1130 fputc ('@', file); \ 1131 assemble_name ((FILE), (STR)); \ 1132 } \ 1133 while (0) 1134 1135 /* Store in OUTPUT a string (made with alloca) containing 1136 an assembler-name for a local static variable named NAME. 1137 LABELNO is an integer which is different for each call. */ 1138 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1139 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1140 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 1141 1142 /* The following macro defines the format used to output the second 1143 operand of the .type assembler directive. Different svr4 assemblers 1144 expect various different forms for this operand. The one given here 1145 is just a default. You may need to override it in your machine- 1146 specific tm.h file (depending upon the particulars of your assembler). */ 1147 1148 #undef TYPE_OPERAND_FMT 1149 #define TYPE_OPERAND_FMT "@%s" 1150 1151 /* A C string containing the appropriate assembler directive to 1152 specify the size of a symbol, without any arguments. On systems 1153 that use ELF, the default (in `config/elfos.h') is `"\t.size\t"'; 1154 on other systems, the default is not to define this macro. */ 1155 #undef SIZE_ASM_OP 1156 #define SIZE_ASM_OP "\t.size\t" 1157 1158 /* Assembler pseudo-op to equate one value with another. */ 1159 /* ??? This is needed because dwarfout.c provides a default definition too 1160 late for defaults.h (which contains the default definition of ASM_OTPUT_DEF 1161 that we use). */ 1162 #ifdef SET_ASM_OP 1163 #undef SET_ASM_OP 1164 #endif 1165 #define SET_ASM_OP "\t.set\t" 1166 1167 extern char rname29[], rname30[]; 1168 extern char rname56[], rname57[], rname58[], rname59[]; 1169 /* How to refer to registers in assembler output. 1170 This sequence is indexed by compiler's hard-register-number (see above). */ 1171 #define REGISTER_NAMES \ 1172 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1173 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1174 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 1175 "r24", "r25", "gp", "fp", "sp", rname29, rname30, "blink", \ 1176 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 1177 "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \ 1178 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 1179 rname56,rname57,rname58,rname59,"lp_count", "cc", "limm", "pcl", \ 1180 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", \ 1181 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", \ 1182 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", \ 1183 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", \ 1184 "vr32", "vr33", "vr34", "vr35", "vr36", "vr37", "vr38", "vr39", \ 1185 "vr40", "vr41", "vr42", "vr43", "vr44", "vr45", "vr46", "vr47", \ 1186 "vr48", "vr49", "vr50", "vr51", "vr52", "vr53", "vr54", "vr55", \ 1187 "vr56", "vr57", "vr58", "vr59", "vr60", "vr61", "vr62", "vr63", \ 1188 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ 1189 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ 1190 "arg", "frame" \ 1191 } 1192 1193 #define ADDITIONAL_REGISTER_NAMES \ 1194 { \ 1195 {"ilink", 29}, \ 1196 {"r29", 29}, \ 1197 {"r30", 30}, \ 1198 {"r40", 40}, \ 1199 {"r41", 41}, \ 1200 {"r42", 42}, \ 1201 {"r43", 43}, \ 1202 {"r56", 56}, \ 1203 {"r57", 57}, \ 1204 {"r58", 58}, \ 1205 {"r59", 59} \ 1206 } 1207 1208 /* Entry to the insn conditionalizer. */ 1209 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 1210 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS) 1211 1212 /* A C expression which evaluates to true if CODE is a valid 1213 punctuation character for use in the `PRINT_OPERAND' macro. */ 1214 extern char arc_punct_chars[]; 1215 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 1216 arc_punct_chars[(unsigned char) (CHAR)] 1217 1218 /* Print operand X (an rtx) in assembler syntax to file FILE. 1219 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1220 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 1221 #define PRINT_OPERAND(FILE, X, CODE) \ 1222 arc_print_operand (FILE, X, CODE) 1223 1224 /* A C compound statement to output to stdio stream STREAM the 1225 assembler syntax for an instruction operand that is a memory 1226 reference whose address is ADDR. ADDR is an RTL expression. 1227 1228 On some machines, the syntax for a symbolic address depends on 1229 the section that the address refers to. On these machines, 1230 define the macro `ENCODE_SECTION_INFO' to store the information 1231 into the `symbol_ref', and then check for it here. */ 1232 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1233 arc_print_operand_address (FILE, ADDR) 1234 1235 /* This is how to output an element of a case-vector that is absolute. */ 1236 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1237 do { \ 1238 char label[30]; \ 1239 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1240 fprintf (FILE, "\t.word "); \ 1241 assemble_name (FILE, label); \ 1242 fprintf (FILE, "\n"); \ 1243 } while (0) 1244 1245 /* This is how to output an element of a case-vector that is relative. */ 1246 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1247 do { \ 1248 char label[30]; \ 1249 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1250 if (!TARGET_BI_BIH) \ 1251 { \ 1252 switch (GET_MODE (BODY)) \ 1253 { \ 1254 case E_QImode: fprintf (FILE, "\t.byte "); break; \ 1255 case E_HImode: fprintf (FILE, "\t.hword "); break; \ 1256 case E_SImode: fprintf (FILE, "\t.word "); break; \ 1257 default: gcc_unreachable (); \ 1258 } \ 1259 assemble_name (FILE, label); \ 1260 fprintf (FILE, "-"); \ 1261 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ 1262 assemble_name (FILE, label); \ 1263 fprintf (FILE, "\n"); \ 1264 } \ 1265 else \ 1266 { \ 1267 switch (GET_MODE (BODY)) \ 1268 { \ 1269 case E_SImode: fprintf (FILE, "\tb\t@"); break; \ 1270 case E_HImode: \ 1271 case E_QImode: fprintf (FILE, "\tb_s\t@"); break; \ 1272 default: gcc_unreachable (); \ 1273 } \ 1274 assemble_name (FILE, label); \ 1275 fprintf(FILE, "\n"); \ 1276 } \ 1277 } while (0) 1278 1279 /* Defined to also emit an .align in elfos.h. We don't want that. */ 1280 #undef ASM_OUTPUT_CASE_LABEL 1281 1282 /* ADDR_DIFF_VECs are in the text section and thus can affect the 1283 current alignment. */ 1284 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ 1285 do \ 1286 { \ 1287 if (GET_CODE (PATTERN (JUMPTABLE)) == ADDR_DIFF_VEC \ 1288 && ((GET_MODE_SIZE (as_a <scalar_int_mode> \ 1289 (GET_MODE (PATTERN (JUMPTABLE)))) \ 1290 * XVECLEN (PATTERN (JUMPTABLE), 1) + 1) \ 1291 & 2)) \ 1292 arc_toggle_unalign (); \ 1293 } \ 1294 while (0) 1295 1296 #define JUMP_ALIGN(LABEL) (arc_size_opt_level < 2 ? 2 : 0) 1297 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 1298 (JUMP_ALIGN(LABEL) \ 1299 ? JUMP_ALIGN(LABEL) \ 1300 : GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 1301 ? 1 : 0) 1302 /* The desired alignment for the location counter at the beginning 1303 of a loop. */ 1304 /* On the ARC, align loops to 4 byte boundaries unless doing all-out size 1305 optimization. */ 1306 #define LOOP_ALIGN(X) 0 1307 1308 #define LABEL_ALIGN(LABEL) (arc_label_align (LABEL)) 1309 1310 /* This is how to output an assembler line 1311 that says to advance the location counter 1312 to a multiple of 2**LOG bytes. */ 1313 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1314 do { \ 1315 if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ 1316 if ((LOG) > 1) \ 1317 arc_clear_unalign (); \ 1318 } while (0) 1319 1320 /* ASM_OUTPUT_ALIGNED_DECL_LOCAL (STREAM, DECL, NAME, SIZE, ALIGNMENT) 1321 Define this macro when you need to see the variable's decl in order to 1322 chose what to output. */ 1323 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ 1324 arc_asm_output_aligned_decl_local (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) 1325 1326 /* Debugging information. */ 1327 1328 /* Generate DBX and DWARF debugging information. */ 1329 #ifdef DBX_DEBUGGING_INFO 1330 #undef DBX_DEBUGGING_INFO 1331 #endif 1332 #define DBX_DEBUGGING_INFO 1333 1334 #ifdef DWARF2_DEBUGGING_INFO 1335 #undef DWARF2_DEBUGGING_INFO 1336 #endif 1337 #define DWARF2_DEBUGGING_INFO 1338 1339 /* Prefer STABS (for now). */ 1340 #undef PREFERRED_DEBUGGING_TYPE 1341 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1342 1343 /* How to renumber registers for dbx and gdb. */ 1344 #define DBX_REGISTER_NUMBER(REGNO) \ 1345 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \ 1346 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \ 1347 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 59) \ 1348 ? ((REGNO) == 57 \ 1349 ? 58 /* MMED */ \ 1350 : ((REGNO) & 1) ^ TARGET_BIG_ENDIAN \ 1351 ? 59 /* MHI */ \ 1352 : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \ 1353 : (REGNO)) 1354 1355 #define DWARF_FRAME_REGNUM(REG) (REG) 1356 1357 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31) 1358 1359 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31) 1360 1361 /* Frame info. */ 1362 1363 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 1364 1365 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 1366 1367 /* Turn off splitting of long stabs. */ 1368 #define DBX_CONTIN_LENGTH 0 1369 1370 /* Miscellaneous. */ 1371 1372 /* Specify the machine mode that this machine uses 1373 for the index in the tablejump instruction. 1374 If we have pc relative case vectors, we start the case vector shortening 1375 with QImode. */ 1376 #define CASE_VECTOR_MODE \ 1377 (TARGET_BI_BIH ? SImode \ 1378 : (optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode) 1379 1380 /* Define as C expression which evaluates to nonzero if the tablejump 1381 instruction expects the table to contain offsets from the address of the 1382 table. 1383 Do not define this if the table should contain absolute addresses. */ 1384 #define CASE_VECTOR_PC_RELATIVE \ 1385 (TARGET_CASE_VECTOR_PC_RELATIVE || TARGET_BI_BIH) 1386 1387 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ 1388 (TARGET_BI_BIH ? \ 1389 ((MIN_OFFSET) >= -512 && (MAX_OFFSET) <= 508 ? HImode : SImode) \ 1390 : ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ 1391 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ 1392 : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \ 1393 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ 1394 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \ 1395 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \ 1396 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \ 1397 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \ 1398 : SImode)) 1399 1400 #define ADDR_VEC_ALIGN(VEC_INSN) \ 1401 (TARGET_BI_BIH ? 0 \ 1402 : exact_log2 (GET_MODE_SIZE (as_a <scalar_int_mode> \ 1403 (GET_MODE (PATTERN (VEC_INSN)))))) 1404 1405 #define INSN_LENGTH_ALIGNMENT(INSN) \ 1406 ((JUMP_TABLE_DATA_P (INSN) \ 1407 && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \ 1408 && GET_MODE (PATTERN (INSN)) == QImode) \ 1409 ? 0 : length_unit_log) 1410 1411 /* Define if operations between registers always perform the operation 1412 on the full register even if a narrower mode is specified. */ 1413 #define WORD_REGISTER_OPERATIONS 1 1414 1415 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1416 will either zero-extend or sign-extend. The value of this macro should 1417 be the code that says which one of the two operations is implicitly 1418 done, NIL if none. */ 1419 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1420 1421 1422 /* Max number of bytes we can move from memory to memory 1423 in one reasonably fast instruction. */ 1424 #define MOVE_MAX 4 1425 1426 /* Undo the effects of the movmem pattern presence on STORE_BY_PIECES_P . */ 1427 #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3) 1428 1429 /* Define this to be nonzero if shift instructions ignore all but the 1430 low-order few bits. 1431 */ 1432 #define SHIFT_COUNT_TRUNCATED 1 1433 1434 /* We assume that the store-condition-codes instructions store 0 for false 1435 and some other value for true. This is the value stored for true. */ 1436 #define STORE_FLAG_VALUE 1 1437 1438 /* Specify the machine mode that pointers have. 1439 After generation of rtl, the compiler makes no further distinction 1440 between pointers and any other objects of this machine mode. */ 1441 /* ARCompact has full 32-bit pointers. */ 1442 #define Pmode SImode 1443 1444 /* A function address in a call instruction. */ 1445 #define FUNCTION_MODE SImode 1446 1447 /* Define the information needed to generate branch and scc insns. This is 1448 stored from the compare operation. Note that we can't use "rtx" here 1449 since it hasn't been defined! */ 1450 extern struct rtx_def *arc_compare_op0, *arc_compare_op1; 1451 1452 /* ARC function types. */ 1453 enum arc_function_type { 1454 /* No function should have the unknown type. This value is used to 1455 indicate the that function type has not yet been computed. */ 1456 ARC_FUNCTION_UNKNOWN = 0, 1457 1458 /* The normal function type indicates that the function has the 1459 standard prologue and epilogue. */ 1460 ARC_FUNCTION_NORMAL = 1 << 0, 1461 /* These are interrupt handlers. The name corresponds to the register 1462 name that contains the return address. */ 1463 ARC_FUNCTION_ILINK1 = 1 << 1, 1464 ARC_FUNCTION_ILINK2 = 1 << 2, 1465 /* Fast interrupt is only available on ARCv2 processors. */ 1466 ARC_FUNCTION_FIRQ = 1 << 3, 1467 /* The naked function type indicates that the function does not have 1468 prologue or epilogue, and that no stack frame is available. */ 1469 ARC_FUNCTION_NAKED = 1 << 4 1470 }; 1471 1472 /* Check if a function is an interrupt function. */ 1473 #define ARC_INTERRUPT_P(TYPE) \ 1474 (((TYPE) & (ARC_FUNCTION_ILINK1 | ARC_FUNCTION_ILINK2 \ 1475 | ARC_FUNCTION_FIRQ)) != 0) 1476 1477 /* Check if a function is a fast interrupt function. */ 1478 #define ARC_FAST_INTERRUPT_P(TYPE) (((TYPE) & ARC_FUNCTION_FIRQ) != 0) 1479 1480 /* Check if a function is normal, that is, has standard prologue and 1481 epilogue. */ 1482 #define ARC_NORMAL_P(TYPE) (((TYPE) & ARC_FUNCTION_NORMAL) != 0) 1483 1484 /* Check if a function is naked. */ 1485 #define ARC_NAKED_P(TYPE) (((TYPE) & ARC_FUNCTION_NAKED) != 0) 1486 1487 /* Called by crtstuff.c to make calls to function FUNCTION that are defined in 1488 SECTION_OP, and then to switch back to text section. */ 1489 #undef CRT_CALL_STATIC_FUNCTION 1490 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 1491 asm (SECTION_OP "\n\t" \ 1492 "add r12,pcl,@" USER_LABEL_PREFIX #FUNC "@pcl\n\t" \ 1493 "jl [r12]\n" \ 1494 TEXT_SECTION_ASM_OP); 1495 1496 /* This macro expands to the name of the scratch register r12, used for 1497 temporary calculations according to the ABI. */ 1498 #define ARC_TEMP_SCRATCH_REG "r12" 1499 1500 /* The C++ compiler must use one bit to indicate whether the function 1501 that will be called through a pointer-to-member-function is 1502 virtual. Normally, we assume that the low-order bit of a function 1503 pointer must always be zero. Then, by ensuring that the 1504 vtable_index is odd, we can distinguish which variant of the union 1505 is in use. But, on some platforms function pointers can be odd, 1506 and so this doesn't work. In that case, we use the low-order bit 1507 of the `delta' field, and shift the remainder of the `delta' field 1508 to the left. We needed to do this for A4 because the address was always 1509 shifted and thus could be odd. */ 1510 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \ 1511 (ptrmemfunc_vbit_in_pfn) 1512 1513 #define INSN_SETS_ARE_DELAYED(X) \ 1514 (GET_CODE (X) == INSN \ 1515 && GET_CODE (PATTERN (X)) != SEQUENCE \ 1516 && GET_CODE (PATTERN (X)) != USE \ 1517 && GET_CODE (PATTERN (X)) != CLOBBER \ 1518 && (get_attr_type (X) == TYPE_CALL || get_attr_type (X) == TYPE_SFUNC)) 1519 1520 #define INSN_REFERENCES_ARE_DELAYED(insn) \ 1521 (INSN_SETS_ARE_DELAYED (insn)) 1522 1523 #define CALL_ATTR(X, NAME) \ 1524 ((CALL_P (X) || NONJUMP_INSN_P (X)) \ 1525 && GET_CODE (PATTERN (X)) != USE \ 1526 && GET_CODE (PATTERN (X)) != CLOBBER \ 1527 && get_attr_is_##NAME (X) == IS_##NAME##_YES) \ 1528 1529 #define REVERSE_CONDITION(CODE,MODE) \ 1530 (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \ 1531 || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \ 1532 || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \ 1533 || (MODE) == CC_FPUmode || (MODE) == CC_FPUEmode) \ 1534 ? reverse_condition_maybe_unordered ((CODE)) \ 1535 : reverse_condition ((CODE))) 1536 1537 #define ADJUST_INSN_LENGTH(X, LENGTH) \ 1538 ((LENGTH) \ 1539 = (GET_CODE (PATTERN (X)) == SEQUENCE \ 1540 ? ((LENGTH) \ 1541 + arc_adjust_insn_length ( \ 1542 as_a <rtx_sequence *> (PATTERN (X))->insn (0), \ 1543 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)), \ 1544 true) \ 1545 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)) \ 1546 + arc_adjust_insn_length ( \ 1547 as_a <rtx_sequence *> (PATTERN (X))->insn (1), \ 1548 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1)), \ 1549 true) \ 1550 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1))) \ 1551 : arc_adjust_insn_length ((X), (LENGTH), false))) 1552 1553 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C,STR) ((C) == '`') 1554 1555 #define INIT_EXPANDERS arc_init_expanders () 1556 1557 enum 1558 { 1559 ARC_LRA_PRIORITY_NONE, ARC_LRA_PRIORITY_NONCOMPACT, ARC_LRA_PRIORITY_COMPACT 1560 }; 1561 1562 /* The define_cond_exec construct is rather crude, as we can't have 1563 different ones with different conditions apply to different sets 1564 of instructions. We can't use an attribute test inside the condition, 1565 because that would lead to infinite recursion as the attribute test 1566 needs to recognize the insn. So, instead we have a clause for 1567 the pattern condition of all sfunc patterns which is only relevant for 1568 the predicated varaint. */ 1569 #define SFUNC_CHECK_PREDICABLE \ 1570 (GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS) 1571 1572 /* MPYW feature macro. Only valid for ARCHS and ARCEM cores. */ 1573 #define TARGET_MPYW ((arc_mpy_option > 0) && TARGET_V2) 1574 /* Full ARCv2 multiplication feature macro. */ 1575 #define TARGET_MULTI ((arc_mpy_option > 1) && TARGET_V2) 1576 /* General MPY feature macro. */ 1577 #define TARGET_MPY ((TARGET_ARC700 && (!TARGET_NOMPY_SET)) || TARGET_MULTI) 1578 /* ARC700 MPY feature macro. */ 1579 #define TARGET_ARC700_MPY (TARGET_ARC700 && (!TARGET_NOMPY_SET)) 1580 /* Any multiplication feature macro. */ 1581 #define TARGET_ANY_MPY \ 1582 (TARGET_MPY || TARGET_MUL64_SET || TARGET_MULMAC_32BY16_SET) 1583 /* PLUS_DMPY feature macro. */ 1584 #define TARGET_PLUS_DMPY ((arc_mpy_option > 6) && TARGET_HS) 1585 /* PLUS_MACD feature macro. */ 1586 #define TARGET_PLUS_MACD ((arc_mpy_option > 7) && TARGET_HS) 1587 /* PLUS_QMACW feature macro. */ 1588 #define TARGET_PLUS_QMACW ((arc_mpy_option > 8) && TARGET_HS) 1589 1590 /* ARC600 and ARC601 feature macro. */ 1591 #define TARGET_ARC600_FAMILY (TARGET_ARC600 || TARGET_ARC601) 1592 /* ARC600, ARC601 and ARC700 feature macro. */ 1593 #define TARGET_ARCOMPACT_FAMILY \ 1594 (TARGET_ARC600 || TARGET_ARC601 || TARGET_ARC700) 1595 /* Loop count register can be read in very next instruction after has 1596 been written to by an ordinary instruction. */ 1597 #define TARGET_LP_WR_INTERLOCK (!TARGET_ARC600_FAMILY) 1598 1599 /* FPU defines. */ 1600 /* Any FPU support. */ 1601 #define TARGET_HARD_FLOAT ((arc_fpu_build & (FPU_SP | FPU_DP)) != 0) 1602 /* Single precision floating point support. */ 1603 #define TARGET_FP_SP_BASE ((arc_fpu_build & FPU_SP) != 0) 1604 /* Double precision floating point support. */ 1605 #define TARGET_FP_DP_BASE ((arc_fpu_build & FPU_DP) != 0) 1606 /* Single precision floating point support with fused operation. */ 1607 #define TARGET_FP_SP_FUSED ((arc_fpu_build & FPU_SF) != 0) 1608 /* Double precision floating point support with fused operation. */ 1609 #define TARGET_FP_DP_FUSED ((arc_fpu_build & FPU_DF) != 0) 1610 /* Single precision floating point conversion instruction support. */ 1611 #define TARGET_FP_SP_CONV ((arc_fpu_build & FPU_SC) != 0) 1612 /* Double precision floating point conversion instruction support. */ 1613 #define TARGET_FP_DP_CONV ((arc_fpu_build & FPU_DC) != 0) 1614 /* Single precision floating point SQRT/DIV instruction support. */ 1615 #define TARGET_FP_SP_SQRT ((arc_fpu_build & FPU_SD) != 0) 1616 /* Double precision floating point SQRT/DIV instruction support. */ 1617 #define TARGET_FP_DP_SQRT ((arc_fpu_build & FPU_DD) != 0) 1618 /* Double precision floating point assist instruction support. */ 1619 #define TARGET_FP_DP_AX ((arc_fpu_build & FPX_DP) != 0) 1620 /* Custom FP instructions used by QuarkSE EM cpu. */ 1621 #define TARGET_FPX_QUARK (TARGET_EM && TARGET_SPFP \ 1622 && (arc_fpu_build == FPX_QK)) 1623 /* DBNZ support is available for ARCv2 core3 and newer cpus. */ 1624 #define TARGET_DBNZ (TARGET_V2 && (arc_tune >= ARC_TUNE_CORE_3)) 1625 1626 /* BI/BIH feature macro. */ 1627 #define TARGET_BI_BIH (TARGET_BRANCH_INDEX && TARGET_CODE_DENSITY) 1628 1629 /* The default option for BI/BIH instructions. */ 1630 #define DEFAULT_BRANCH_INDEX 0 1631 1632 #ifndef TARGET_LRA 1633 #define TARGET_LRA arc_lra_p() 1634 #endif 1635 1636 #endif /* GCC_ARC_H */ 1637