1;; Machine description for AArch64 architecture. 2;; Copyright (C) 2009-2019 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; ------------------------------------------------------------------- 22;; Mode Iterators 23;; ------------------------------------------------------------------- 24 25 26;; Iterator for General Purpose Integer registers (32- and 64-bit modes) 27(define_mode_iterator GPI [SI DI]) 28 29;; Iterator for HI, SI, DI, some instructions can only work on these modes. 30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI]) 31 32;; Iterator for QI and HI modes 33(define_mode_iterator SHORT [QI HI]) 34 35;; Iterator for all integer modes (up to 64-bit) 36(define_mode_iterator ALLI [QI HI SI DI]) 37 38;; Iterator for all integer modes (up to 128-bit) 39(define_mode_iterator ALLI_TI [QI HI SI DI TI]) 40 41;; Iterator for all integer modes that can be extended (up to 64-bit) 42(define_mode_iterator ALLX [QI HI SI]) 43 44;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) 45(define_mode_iterator GPF [SF DF]) 46 47;; Iterator for all scalar floating point modes (HF, SF, DF) 48(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF]) 49 50;; Iterator for all scalar floating point modes (HF, SF, DF) 51(define_mode_iterator GPF_HF [HF SF DF]) 52 53;; Iterator for all scalar floating point modes (HF, SF, DF and TF) 54(define_mode_iterator GPF_TF_F16 [HF SF DF TF]) 55 56;; Double vector modes. 57(define_mode_iterator VDF [V2SF V4HF]) 58 59;; Iterator for all scalar floating point modes (SF, DF and TF) 60(define_mode_iterator GPF_TF [SF DF TF]) 61 62;; Integer Advanced SIMD modes. 63(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) 64 65;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes. 66(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) 67 68;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD 69;; integer modes; 64-bit scalar integer mode. 70(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) 71 72;; Double vector modes. 73(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF]) 74 75;; All modes stored in registers d0-d31. 76(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF]) 77 78;; Copy of the above. 79(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF]) 80 81;; Advanced SIMD, 64-bit container, all integer modes. 82(define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) 83 84;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes 85(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) 86 87;; Quad vector modes. 88(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF]) 89 90;; Copy of the above. 91(define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF]) 92 93;; Quad integer vector modes. 94(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI]) 95 96;; VQ without 2 element modes. 97(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF]) 98 99;; Quad vector with only 2 element modes. 100(define_mode_iterator VQ_2E [V2DI V2DF]) 101 102;; This mode iterator allows :P to be used for patterns that operate on 103;; addresses in different modes. In LP64, only DI will match, while in 104;; ILP32, either can match. 105(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode") 106 (DI "ptr_mode == DImode || Pmode == DImode")]) 107 108;; This mode iterator allows :PTR to be used for patterns that operate on 109;; pointer-sized quantities. Exactly one of the two alternatives will match. 110(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) 111 112;; Advanced SIMD Float modes suitable for moving, loading and storing. 113(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF]) 114 115;; Advanced SIMD Float modes. 116(define_mode_iterator VDQF [V2SF V4SF V2DF]) 117(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") 118 (V8HF "TARGET_SIMD_F16INST") 119 V2SF V4SF V2DF]) 120 121;; Advanced SIMD Float modes, and DF. 122(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST") 123 (V8HF "TARGET_SIMD_F16INST") 124 V2SF V4SF V2DF DF]) 125(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST") 126 (V8HF "TARGET_SIMD_F16INST") 127 V2SF V4SF V2DF 128 (HF "TARGET_SIMD_F16INST") 129 SF DF]) 130 131;; Advanced SIMD single Float modes. 132(define_mode_iterator VDQSF [V2SF V4SF]) 133 134;; Quad vector Float modes with half/single elements. 135(define_mode_iterator VQ_HSF [V8HF V4SF]) 136 137;; Modes suitable to use as the return type of a vcond expression. 138(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) 139 140;; All scalar and Advanced SIMD Float modes. 141(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) 142 143;; Advanced SIMD Float modes with 2 elements. 144(define_mode_iterator V2F [V2SF V2DF]) 145 146;; All Advanced SIMD modes on which we support any arithmetic operations. 147(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) 148 149;; All Advanced SIMD modes suitable for moving, loading, and storing. 150(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI 151 V4HF V8HF V2SF V4SF V2DF]) 152 153;; The VALL_F16 modes except the 128-bit 2-element ones. 154(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI 155 V4HF V8HF V2SF V4SF]) 156 157;; All Advanced SIMD modes barring HF modes, plus DI. 158(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) 159 160;; All Advanced SIMD modes and DI. 161(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI 162 V4HF V8HF V2SF V4SF V2DF DI]) 163 164;; All Advanced SIMD modes, plus DI and DF. 165(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI 166 V2DI V4HF V8HF V2SF V4SF V2DF DI DF]) 167 168;; Advanced SIMD modes for Integer reduction across lanes. 169(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) 170 171;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes. 172(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI]) 173 174;; All double integer narrow-able modes. 175(define_mode_iterator VDN [V4HI V2SI DI]) 176 177;; All quad integer narrow-able modes. 178(define_mode_iterator VQN [V8HI V4SI V2DI]) 179 180;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit 181;; integer modes 182(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) 183 184;; All quad integer widen-able modes. 185(define_mode_iterator VQW [V16QI V8HI V4SI]) 186 187;; Double vector modes for combines. 188(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF]) 189 190;; Advanced SIMD modes except double int. 191(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) 192(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI 193 V4HF V8HF V2SF V4SF V2DF]) 194 195;; Advanced SIMD modes for S type. 196(define_mode_iterator VDQ_SI [V2SI V4SI]) 197 198;; Advanced SIMD modes for S and D. 199(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI]) 200 201;; Advanced SIMD modes for H, S and D. 202(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") 203 (V8HI "TARGET_SIMD_F16INST") 204 V2SI V4SI V2DI]) 205 206;; Scalar and Advanced SIMD modes for S and D. 207(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI]) 208 209;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H. 210(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") 211 (V8HI "TARGET_SIMD_F16INST") 212 V2SI V4SI V2DI 213 (HI "TARGET_SIMD_F16INST") 214 SI DI]) 215 216;; Advanced SIMD modes for Q and H types. 217(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) 218 219;; Advanced SIMD modes for H and S types. 220(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) 221 222;; Advanced SIMD modes for H, S and D types. 223(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) 224 225;; Advanced SIMD and scalar integer modes for H and S. 226(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) 227 228;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes. 229(define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) 230 231;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. 232(define_mode_iterator VD_HSI [V4HI V2SI]) 233 234;; Scalar 64-bit container: 16, 32-bit integer modes 235(define_mode_iterator SD_HSI [HI SI]) 236 237;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. 238(define_mode_iterator VQ_HSI [V8HI V4SI]) 239 240;; All byte modes. 241(define_mode_iterator VB [V8QI V16QI]) 242 243;; 2 and 4 lane SI modes. 244(define_mode_iterator VS [V2SI V4SI]) 245 246(define_mode_iterator TX [TI TF]) 247 248;; Advanced SIMD opaque structure modes. 249(define_mode_iterator VSTRUCT [OI CI XI]) 250 251;; Double scalar modes 252(define_mode_iterator DX [DI DF]) 253 254;; Duplicate of the above 255(define_mode_iterator DX2 [DI DF]) 256 257;; Single scalar modes 258(define_mode_iterator SX [SI SF]) 259 260;; Duplicate of the above 261(define_mode_iterator SX2 [SI SF]) 262 263;; Single and double integer and float modes 264(define_mode_iterator DSX [DF DI SF SI]) 265 266 267;; Modes available for Advanced SIMD <f>mul lane operations. 268(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI 269 (V4HF "TARGET_SIMD_F16INST") 270 (V8HF "TARGET_SIMD_F16INST") 271 V2SF V4SF V2DF]) 272 273;; Modes available for Advanced SIMD <f>mul lane operations changing lane 274;; count. 275(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF]) 276 277;; All SVE vector modes. 278(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI 279 VNx8HF VNx4SF VNx2DF]) 280 281;; All SVE vector structure modes. 282(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI 283 VNx16HF VNx8SF VNx4DF 284 VNx48QI VNx24HI VNx12SI VNx6DI 285 VNx24HF VNx12SF VNx6DF 286 VNx64QI VNx32HI VNx16SI VNx8DI 287 VNx32HF VNx16SF VNx8DF]) 288 289;; All SVE vector modes that have 8-bit or 16-bit elements. 290(define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF]) 291 292;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements. 293(define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF]) 294 295;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements. 296(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI]) 297 298;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements. 299(define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI]) 300 301;; All SVE floating-point vector modes that have 16-bit or 32-bit elements. 302(define_mode_iterator SVE_HSF [VNx8HF VNx4SF]) 303 304;; All SVE vector modes that have 32-bit or 64-bit elements. 305(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF]) 306 307;; All SVE vector modes that have 32-bit elements. 308(define_mode_iterator SVE_S [VNx4SI VNx4SF]) 309 310;; All SVE vector modes that have 64-bit elements. 311(define_mode_iterator SVE_D [VNx2DI VNx2DF]) 312 313;; All SVE integer vector modes that have 32-bit or 64-bit elements. 314(define_mode_iterator SVE_SDI [VNx4SI VNx2DI]) 315 316;; All SVE integer vector modes. 317(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI]) 318 319;; All SVE floating-point vector modes. 320(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF]) 321 322;; All SVE predicate modes. 323(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI]) 324 325;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements. 326(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI]) 327 328;; ------------------------------------------------------------------ 329;; Unspec enumerations for Advance SIMD. These could well go into 330;; aarch64.md but for their use in int_iterators here. 331;; ------------------------------------------------------------------ 332 333(define_c_enum "unspec" 334 [ 335 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. 336 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. 337 UNSPEC_ABS ; Used in aarch64-simd.md. 338 UNSPEC_FMAX ; Used in aarch64-simd.md. 339 UNSPEC_FMAXNMV ; Used in aarch64-simd.md. 340 UNSPEC_FMAXV ; Used in aarch64-simd.md. 341 UNSPEC_FMIN ; Used in aarch64-simd.md. 342 UNSPEC_FMINNMV ; Used in aarch64-simd.md. 343 UNSPEC_FMINV ; Used in aarch64-simd.md. 344 UNSPEC_FADDV ; Used in aarch64-simd.md. 345 UNSPEC_ADDV ; Used in aarch64-simd.md. 346 UNSPEC_SMAXV ; Used in aarch64-simd.md. 347 UNSPEC_SMINV ; Used in aarch64-simd.md. 348 UNSPEC_UMAXV ; Used in aarch64-simd.md. 349 UNSPEC_UMINV ; Used in aarch64-simd.md. 350 UNSPEC_SHADD ; Used in aarch64-simd.md. 351 UNSPEC_UHADD ; Used in aarch64-simd.md. 352 UNSPEC_SRHADD ; Used in aarch64-simd.md. 353 UNSPEC_URHADD ; Used in aarch64-simd.md. 354 UNSPEC_SHSUB ; Used in aarch64-simd.md. 355 UNSPEC_UHSUB ; Used in aarch64-simd.md. 356 UNSPEC_SRHSUB ; Used in aarch64-simd.md. 357 UNSPEC_URHSUB ; Used in aarch64-simd.md. 358 UNSPEC_ADDHN ; Used in aarch64-simd.md. 359 UNSPEC_RADDHN ; Used in aarch64-simd.md. 360 UNSPEC_SUBHN ; Used in aarch64-simd.md. 361 UNSPEC_RSUBHN ; Used in aarch64-simd.md. 362 UNSPEC_ADDHN2 ; Used in aarch64-simd.md. 363 UNSPEC_RADDHN2 ; Used in aarch64-simd.md. 364 UNSPEC_SUBHN2 ; Used in aarch64-simd.md. 365 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md. 366 UNSPEC_SQDMULH ; Used in aarch64-simd.md. 367 UNSPEC_SQRDMULH ; Used in aarch64-simd.md. 368 UNSPEC_PMUL ; Used in aarch64-simd.md. 369 UNSPEC_FMULX ; Used in aarch64-simd.md. 370 UNSPEC_USQADD ; Used in aarch64-simd.md. 371 UNSPEC_SUQADD ; Used in aarch64-simd.md. 372 UNSPEC_SQXTUN ; Used in aarch64-simd.md. 373 UNSPEC_SQXTN ; Used in aarch64-simd.md. 374 UNSPEC_UQXTN ; Used in aarch64-simd.md. 375 UNSPEC_SSRA ; Used in aarch64-simd.md. 376 UNSPEC_USRA ; Used in aarch64-simd.md. 377 UNSPEC_SRSRA ; Used in aarch64-simd.md. 378 UNSPEC_URSRA ; Used in aarch64-simd.md. 379 UNSPEC_SRSHR ; Used in aarch64-simd.md. 380 UNSPEC_URSHR ; Used in aarch64-simd.md. 381 UNSPEC_SQSHLU ; Used in aarch64-simd.md. 382 UNSPEC_SQSHL ; Used in aarch64-simd.md. 383 UNSPEC_UQSHL ; Used in aarch64-simd.md. 384 UNSPEC_SQSHRUN ; Used in aarch64-simd.md. 385 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md. 386 UNSPEC_SQSHRN ; Used in aarch64-simd.md. 387 UNSPEC_UQSHRN ; Used in aarch64-simd.md. 388 UNSPEC_SQRSHRN ; Used in aarch64-simd.md. 389 UNSPEC_UQRSHRN ; Used in aarch64-simd.md. 390 UNSPEC_SSHL ; Used in aarch64-simd.md. 391 UNSPEC_USHL ; Used in aarch64-simd.md. 392 UNSPEC_SRSHL ; Used in aarch64-simd.md. 393 UNSPEC_URSHL ; Used in aarch64-simd.md. 394 UNSPEC_SQRSHL ; Used in aarch64-simd.md. 395 UNSPEC_UQRSHL ; Used in aarch64-simd.md. 396 UNSPEC_SSLI ; Used in aarch64-simd.md. 397 UNSPEC_USLI ; Used in aarch64-simd.md. 398 UNSPEC_SSRI ; Used in aarch64-simd.md. 399 UNSPEC_USRI ; Used in aarch64-simd.md. 400 UNSPEC_SSHLL ; Used in aarch64-simd.md. 401 UNSPEC_USHLL ; Used in aarch64-simd.md. 402 UNSPEC_ADDP ; Used in aarch64-simd.md. 403 UNSPEC_TBL ; Used in vector permute patterns. 404 UNSPEC_TBX ; Used in vector permute patterns. 405 UNSPEC_CONCAT ; Used in vector permute patterns. 406 407 ;; The following permute unspecs are generated directly by 408 ;; aarch64_expand_vec_perm_const, so any changes to the underlying 409 ;; instructions would need a corresponding change there. 410 UNSPEC_ZIP1 ; Used in vector permute patterns. 411 UNSPEC_ZIP2 ; Used in vector permute patterns. 412 UNSPEC_UZP1 ; Used in vector permute patterns. 413 UNSPEC_UZP2 ; Used in vector permute patterns. 414 UNSPEC_TRN1 ; Used in vector permute patterns. 415 UNSPEC_TRN2 ; Used in vector permute patterns. 416 UNSPEC_EXT ; Used in vector permute patterns. 417 UNSPEC_REV64 ; Used in vector reverse patterns (permute). 418 UNSPEC_REV32 ; Used in vector reverse patterns (permute). 419 UNSPEC_REV16 ; Used in vector reverse patterns (permute). 420 421 UNSPEC_AESE ; Used in aarch64-simd.md. 422 UNSPEC_AESD ; Used in aarch64-simd.md. 423 UNSPEC_AESMC ; Used in aarch64-simd.md. 424 UNSPEC_AESIMC ; Used in aarch64-simd.md. 425 UNSPEC_SHA1C ; Used in aarch64-simd.md. 426 UNSPEC_SHA1M ; Used in aarch64-simd.md. 427 UNSPEC_SHA1P ; Used in aarch64-simd.md. 428 UNSPEC_SHA1H ; Used in aarch64-simd.md. 429 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md. 430 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md. 431 UNSPEC_SHA256H ; Used in aarch64-simd.md. 432 UNSPEC_SHA256H2 ; Used in aarch64-simd.md. 433 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. 434 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. 435 UNSPEC_PMULL ; Used in aarch64-simd.md. 436 UNSPEC_PMULL2 ; Used in aarch64-simd.md. 437 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. 438 UNSPEC_VEC_SHR ; Used in aarch64-simd.md. 439 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md. 440 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. 441 UNSPEC_FMAXNM ; Used in aarch64-simd.md. 442 UNSPEC_FMINNM ; Used in aarch64-simd.md. 443 UNSPEC_SDOT ; Used in aarch64-simd.md. 444 UNSPEC_UDOT ; Used in aarch64-simd.md. 445 UNSPEC_SM3SS1 ; Used in aarch64-simd.md. 446 UNSPEC_SM3TT1A ; Used in aarch64-simd.md. 447 UNSPEC_SM3TT1B ; Used in aarch64-simd.md. 448 UNSPEC_SM3TT2A ; Used in aarch64-simd.md. 449 UNSPEC_SM3TT2B ; Used in aarch64-simd.md. 450 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md. 451 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md. 452 UNSPEC_SM4E ; Used in aarch64-simd.md. 453 UNSPEC_SM4EKEY ; Used in aarch64-simd.md. 454 UNSPEC_SHA512H ; Used in aarch64-simd.md. 455 UNSPEC_SHA512H2 ; Used in aarch64-simd.md. 456 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md. 457 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md. 458 UNSPEC_FMLAL ; Used in aarch64-simd.md. 459 UNSPEC_FMLSL ; Used in aarch64-simd.md. 460 UNSPEC_FMLAL2 ; Used in aarch64-simd.md. 461 UNSPEC_FMLSL2 ; Used in aarch64-simd.md. 462 UNSPEC_SEL ; Used in aarch64-sve.md. 463 UNSPEC_ANDV ; Used in aarch64-sve.md. 464 UNSPEC_IORV ; Used in aarch64-sve.md. 465 UNSPEC_XORV ; Used in aarch64-sve.md. 466 UNSPEC_ANDF ; Used in aarch64-sve.md. 467 UNSPEC_IORF ; Used in aarch64-sve.md. 468 UNSPEC_XORF ; Used in aarch64-sve.md. 469 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md. 470 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md. 471 UNSPEC_COND_ADD ; Used in aarch64-sve.md. 472 UNSPEC_COND_SUB ; Used in aarch64-sve.md. 473 UNSPEC_COND_MUL ; Used in aarch64-sve.md. 474 UNSPEC_COND_DIV ; Used in aarch64-sve.md. 475 UNSPEC_COND_MAX ; Used in aarch64-sve.md. 476 UNSPEC_COND_MIN ; Used in aarch64-sve.md. 477 UNSPEC_COND_FMLA ; Used in aarch64-sve.md. 478 UNSPEC_COND_FMLS ; Used in aarch64-sve.md. 479 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md. 480 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md. 481 UNSPEC_COND_LT ; Used in aarch64-sve.md. 482 UNSPEC_COND_LE ; Used in aarch64-sve.md. 483 UNSPEC_COND_EQ ; Used in aarch64-sve.md. 484 UNSPEC_COND_NE ; Used in aarch64-sve.md. 485 UNSPEC_COND_GE ; Used in aarch64-sve.md. 486 UNSPEC_COND_GT ; Used in aarch64-sve.md. 487 UNSPEC_LASTB ; Used in aarch64-sve.md. 488 UNSPEC_FCADD90 ; Used in aarch64-simd.md. 489 UNSPEC_FCADD270 ; Used in aarch64-simd.md. 490 UNSPEC_FCMLA ; Used in aarch64-simd.md. 491 UNSPEC_FCMLA90 ; Used in aarch64-simd.md. 492 UNSPEC_FCMLA180 ; Used in aarch64-simd.md. 493 UNSPEC_FCMLA270 ; Used in aarch64-simd.md. 494]) 495 496;; ------------------------------------------------------------------ 497;; Unspec enumerations for Atomics. They are here so that they can be 498;; used in the int_iterators for atomic operations. 499;; ------------------------------------------------------------------ 500 501(define_c_enum "unspecv" 502 [ 503 UNSPECV_LX ; Represent a load-exclusive. 504 UNSPECV_SX ; Represent a store-exclusive. 505 UNSPECV_LDA ; Represent an atomic load or load-acquire. 506 UNSPECV_STL ; Represent an atomic store or store-release. 507 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap. 508 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange. 509 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS. 510 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP. 511 UNSPECV_ATOMIC_OP ; Represent an atomic operation. 512 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or 513 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic 514 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor 515 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add 516]) 517 518;; ------------------------------------------------------------------- 519;; Mode attributes 520;; ------------------------------------------------------------------- 521 522;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the 523;; 32-bit version and "%x0" in the 64-bit version. 524(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) 525 526;; The size of access, in bytes. 527(define_mode_attr ldst_sz [(SI "4") (DI "8")]) 528;; Likewise for load/store pair. 529(define_mode_attr ldpstp_sz [(SI "8") (DI "16")]) 530 531;; For inequal width int to float conversion 532(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")]) 533(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) 534 535;; For width of fp registers in fcvt instruction 536(define_mode_attr fpw [(DI "s") (SI "d")]) 537 538(define_mode_attr short_mask [(HI "65535") (QI "255")]) 539 540;; For constraints used in scalar immediate vector moves 541(define_mode_attr hq [(HI "h") (QI "q")]) 542 543;; For doubling width of an integer mode 544(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) 545 546(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")]) 547 548(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")]) 549 550;; For scalar usage of vector/FP registers 551(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") 552 (HF "h") (SF "s") (DF "d") 553 (V8QI "") (V16QI "") 554 (V4HI "") (V8HI "") 555 (V2SI "") (V4SI "") 556 (V2DI "") (V2SF "") 557 (V4SF "") (V4HF "") 558 (V8HF "") (V2DF "")]) 559 560;; For scalar usage of vector/FP registers, narrowing 561(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") 562 (V8QI "") (V16QI "") 563 (V4HI "") (V8HI "") 564 (V2SI "") (V4SI "") 565 (V2DI "") (V2SF "") 566 (V4SF "") (V2DF "")]) 567 568;; For scalar usage of vector/FP registers, widening 569(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") 570 (V8QI "") (V16QI "") 571 (V4HI "") (V8HI "") 572 (V2SI "") (V4SI "") 573 (V2DI "") (V2SF "") 574 (V4SF "") (V2DF "")]) 575 576;; Register Type Name and Vector Arrangement Specifier for when 577;; we are doing scalar for DI and SIMD for SI (ignoring all but 578;; lane 0). 579(define_mode_attr rtn [(DI "d") (SI "")]) 580(define_mode_attr vas [(DI "") (SI ".2s")]) 581 582;; Map a vector to the number of units in it, if the size of the mode 583;; is constant. 584(define_mode_attr nunits [(V8QI "8") (V16QI "16") 585 (V4HI "4") (V8HI "8") 586 (V2SI "2") (V4SI "4") 587 (V2DI "2") 588 (V4HF "4") (V8HF "8") 589 (V2SF "2") (V4SF "4") 590 (V1DF "1") (V2DF "2") 591 (DI "1") (DF "1")]) 592 593;; Map a mode to the number of bits in it, if the size of the mode 594;; is constant. 595(define_mode_attr bitsize [(V8QI "64") (V16QI "128") 596 (V4HI "64") (V8HI "128") 597 (V2SI "64") (V4SI "128") 598 (V2DI "128")]) 599 600;; Map a floating point or integer mode to the appropriate register name prefix 601(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")]) 602 603;; Give the length suffix letter for a sign- or zero-extension. 604(define_mode_attr size [(QI "b") (HI "h") (SI "w")]) 605 606;; Give the number of bits in the mode 607(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) 608 609;; Give the ordinal of the MSB in the mode 610(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63") 611 (HF "#15") (SF "#31") (DF "#63")]) 612 613;; Attribute to describe constants acceptable in logical operations 614(define_mode_attr lconst [(SI "K") (DI "L")]) 615 616;; Attribute to describe constants acceptable in logical and operations 617(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")]) 618 619;; Map a mode to a specific constraint character. 620(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) 621 622;; Map modes to Usg and Usj constraints for SISD right shifts 623(define_mode_attr cmode_simd [(SI "g") (DI "j")]) 624 625(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") 626 (V4HI "4h") (V8HI "8h") 627 (V2SI "2s") (V4SI "4s") 628 (DI "1d") (DF "1d") 629 (V2DI "2d") (V2SF "2s") 630 (V4SF "4s") (V2DF "2d") 631 (V4HF "4h") (V8HF "8h")]) 632 633(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32") 634 (V4SI "32") (V2DI "64")]) 635 636(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") 637 (V4HI ".4h") (V8HI ".8h") 638 (V2SI ".2s") (V4SI ".4s") 639 (V2DI ".2d") (V4HF ".4h") 640 (V8HF ".8h") (V2SF ".2s") 641 (V4SF ".4s") (V2DF ".2d") 642 (DI "") (SI "") 643 (HI "") (QI "") 644 (TI "") (HF "") 645 (SF "") (DF "")]) 646 647;; Register suffix narrowed modes for VQN. 648(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") 649 (V2DI ".2s") 650 (DI "") (SI "") 651 (HI "")]) 652 653;; Mode-to-individual element type mapping. 654(define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b") 655 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h") 656 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s") 657 (V2DI "d") (VNx2DI "d") (VNx2BI "d") 658 (V4HF "h") (V8HF "h") (VNx8HF "h") 659 (V2SF "s") (V4SF "s") (VNx4SF "s") 660 (V2DF "d") (VNx2DF "d") 661 (HF "h") 662 (SF "s") (DF "d") 663 (QI "b") (HI "h") 664 (SI "s") (DI "d")]) 665 666;; Equivalent of "size" for a vector element. 667(define_mode_attr Vesize [(VNx16QI "b") 668 (VNx8HI "h") (VNx8HF "h") 669 (VNx4SI "w") (VNx4SF "w") 670 (VNx2DI "d") (VNx2DF "d") 671 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b") 672 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h") 673 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h") 674 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w") 675 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w") 676 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d") 677 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")]) 678 679;; Vetype is used everywhere in scheduling type and assembly output, 680;; sometimes they are not the same, for example HF modes on some 681;; instructions. stype is defined to represent scheduling type 682;; more accurately. 683(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s") 684 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s") 685 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") 686 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s") 687 (SI "s") (DI "d")]) 688 689;; Mode-to-bitwise operation type mapping. 690(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") 691 (V4HI "8b") (V8HI "16b") 692 (V2SI "8b") (V4SI "16b") 693 (V2DI "16b") (V4HF "8b") 694 (V8HF "16b") (V2SF "8b") 695 (V4SF "16b") (V2DF "16b") 696 (DI "8b") (DF "8b") 697 (SI "8b") (SF "8b")]) 698 699;; Define element mode for each vector mode. 700(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI") 701 (V4HI "HI") (V8HI "HI") (VNx8HI "HI") 702 (V2SI "SI") (V4SI "SI") (VNx4SI "SI") 703 (DI "DI") (V2DI "DI") (VNx2DI "DI") 704 (V4HF "HF") (V8HF "HF") (VNx8HF "HF") 705 (V2SF "SF") (V4SF "SF") (VNx4SF "SF") 706 (DF "DF") (V2DF "DF") (VNx2DF "DF") 707 (SI "SI") (HI "HI") 708 (QI "QI")]) 709 710;; Define element mode for each vector mode (lower case). 711(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi") 712 (V4HI "hi") (V8HI "hi") (VNx8HI "hi") 713 (V2SI "si") (V4SI "si") (VNx4SI "si") 714 (DI "di") (V2DI "di") (VNx2DI "di") 715 (V4HF "hf") (V8HF "hf") (VNx8HF "hf") 716 (V2SF "sf") (V4SF "sf") (VNx4SF "sf") 717 (V2DF "df") (DF "df") (VNx2DF "df") 718 (SI "si") (HI "hi") 719 (QI "qi")]) 720 721;; Element mode with floating-point values replaced by like-sized integers. 722(define_mode_attr VEL_INT [(VNx16QI "QI") 723 (VNx8HI "HI") (VNx8HF "HI") 724 (VNx4SI "SI") (VNx4SF "SI") 725 (VNx2DI "DI") (VNx2DF "DI")]) 726 727;; Gives the mode of the 128-bit lowpart of an SVE vector. 728(define_mode_attr V128 [(VNx16QI "V16QI") 729 (VNx8HI "V8HI") (VNx8HF "V8HF") 730 (VNx4SI "V4SI") (VNx4SF "V4SF") 731 (VNx2DI "V2DI") (VNx2DF "V2DF")]) 732 733;; ...and again in lower case. 734(define_mode_attr v128 [(VNx16QI "v16qi") 735 (VNx8HI "v8hi") (VNx8HF "v8hf") 736 (VNx4SI "v4si") (VNx4SF "v4sf") 737 (VNx2DI "v2di") (VNx2DF "v2df")]) 738 739;; 64-bit container modes the inner or scalar source mode. 740(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI") 741 (V4HI "V4HI") (V8HI "V4HI") 742 (V2SI "V2SI") (V4SI "V2SI") 743 (DI "DI") (V2DI "DI") 744 (V2SF "V2SF") (V4SF "V2SF") 745 (V2DF "DF")]) 746 747;; 128-bit container modes the inner or scalar source mode. 748(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI") 749 (V4HI "V8HI") (V8HI "V8HI") 750 (V2SI "V4SI") (V4SI "V4SI") 751 (DI "V2DI") (V2DI "V2DI") 752 (V4HF "V8HF") (V8HF "V8HF") 753 (V2SF "V2SF") (V4SF "V4SF") 754 (V2DF "V2DF") (SI "V4SI") 755 (HI "V8HI") (QI "V16QI")]) 756 757;; Half modes of all vector modes. 758(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") 759 (V4HI "V2HI") (V8HI "V4HI") 760 (V2SI "SI") (V4SI "V2SI") 761 (V2DI "DI") (V2SF "SF") 762 (V4SF "V2SF") (V4HF "V2HF") 763 (V8HF "V4HF") (V2DF "DF")]) 764 765;; Half modes of all vector modes, in lower-case. 766(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi") 767 (V4HI "v2hi") (V8HI "v4hi") 768 (V2SI "si") (V4SI "v2si") 769 (V2DI "di") (V2SF "sf") 770 (V4SF "v2sf") (V2DF "df")]) 771 772;; Double modes of vector modes. 773(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") 774 (V4HF "V8HF") 775 (V2SI "V4SI") (V2SF "V4SF") 776 (SI "V2SI") (DI "V2DI") 777 (DF "V2DF")]) 778 779;; Register suffix for double-length mode. 780(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")]) 781 782;; Double modes of vector modes (lower case). 783(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") 784 (V4HF "v8hf") 785 (V2SI "v4si") (V2SF "v4sf") 786 (SI "v2si") (DI "v2di") 787 (DF "v2df")]) 788 789;; Modes with double-width elements. 790(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI") 791 (V4HI "V2SI") (V8HI "V4SI") 792 (V2SI "DI") (V4SI "V2DI")]) 793 794;; Narrowed modes for VDN. 795(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") 796 (DI "V2SI")]) 797 798;; Narrowed double-modes for VQN (Used for XTN). 799(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") 800 (V2DI "V2SI") 801 (DI "SI") (SI "HI") 802 (HI "QI")]) 803 804;; Narrowed quad-modes for VQN (Used for XTN2). 805(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") 806 (V2DI "V4SI")]) 807 808;; Register suffix narrowed modes for VQN. 809(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") 810 (V2DI "2s")]) 811 812;; Register suffix narrowed modes for VQN. 813(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") 814 (V2DI "4s")]) 815 816;; Widened modes of vector modes. 817(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") 818 (V2SI "V2DI") (V16QI "V8HI") 819 (V8HI "V4SI") (V4SI "V2DI") 820 (HI "SI") (SI "DI") 821 (V8HF "V4SF") (V4SF "V2DF") 822 (V4HF "V4SF") (V2SF "V2DF") 823 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF") 824 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI") 825 (VNx4SI "VNx2DI") 826 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI") 827 (VNx4BI "VNx2BI")]) 828 829;; Predicate mode associated with VWIDE. 830(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")]) 831 832;; Widened modes of vector modes, lowercase 833(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf") 834 (VNx16QI "vnx8hi") (VNx8HI "vnx4si") 835 (VNx4SI "vnx2di") 836 (VNx8HF "vnx4sf") (VNx4SF "vnx2df") 837 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi") 838 (VNx4BI "vnx2bi")]) 839 840;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. 841(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") 842 (V2SI "2d") (V16QI "8h") 843 (V8HI "4s") (V4SI "2d") 844 (V8HF "4s") (V4SF "2d")]) 845 846;; SVE vector after widening 847(define_mode_attr Vewtype [(VNx16QI "h") 848 (VNx8HI "s") (VNx8HF "s") 849 (VNx4SI "d") (VNx4SF "d")]) 850 851;; Widened mode register suffixes for VDW/VQW. 852(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") 853 (V2SI ".2d") (V16QI ".8h") 854 (V8HI ".4s") (V4SI ".2d") 855 (V4HF ".4s") (V2SF ".2d") 856 (SI "") (HI "")]) 857 858;; Lower part register suffixes for VQW/VQ_HSF. 859(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") 860 (V4SI "2s") (V8HF "4h") 861 (V4SF "2s")]) 862 863;; Define corresponding core/FP element mode for each vector mode. 864(define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w") 865 (V4HI "w") (V8HI "w") (VNx8HI "w") 866 (V2SI "w") (V4SI "w") (VNx4SI "w") 867 (DI "x") (V2DI "x") (VNx2DI "x") 868 (VNx8HF "h") 869 (V2SF "s") (V4SF "s") (VNx4SF "s") 870 (V2DF "d") (VNx2DF "d")]) 871 872;; Corresponding core element mode for each vector mode. This is a 873;; variation on <vw> mapping FP modes to GP regs. 874(define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w") 875 (V4HI "w") (V8HI "w") (VNx8HI "w") 876 (V2SI "w") (V4SI "w") (VNx4SI "w") 877 (DI "x") (V2DI "x") (VNx2DI "x") 878 (V4HF "w") (V8HF "w") (VNx8HF "w") 879 (V2SF "w") (V4SF "w") (VNx4SF "w") 880 (V2DF "x") (VNx2DF "x")]) 881 882;; Double vector types for ALLX. 883(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) 884 885;; Mode with floating-point values replaced by like-sized integers. 886(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI") 887 (V4HI "V4HI") (V8HI "V8HI") 888 (V2SI "V2SI") (V4SI "V4SI") 889 (DI "DI") (V2DI "V2DI") 890 (V4HF "V4HI") (V8HF "V8HI") 891 (V2SF "V2SI") (V4SF "V4SI") 892 (DF "DI") (V2DF "V2DI") 893 (SF "SI") (SI "SI") 894 (HF "HI") 895 (VNx16QI "VNx16QI") 896 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI") 897 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI") 898 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI") 899]) 900 901;; Lower case mode with floating-point values replaced by like-sized integers. 902(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi") 903 (V4HI "v4hi") (V8HI "v8hi") 904 (V2SI "v2si") (V4SI "v4si") 905 (DI "di") (V2DI "v2di") 906 (V4HF "v4hi") (V8HF "v8hi") 907 (V2SF "v2si") (V4SF "v4si") 908 (DF "di") (V2DF "v2di") 909 (SF "si") 910 (VNx16QI "vnx16qi") 911 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi") 912 (VNx4SI "vnx4si") (VNx4SF "vnx4si") 913 (VNx2DI "vnx2di") (VNx2DF "vnx2di") 914]) 915 916;; Floating-point equivalent of selected modes. 917(define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF") 918 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")]) 919(define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf") 920 (VNx2DI "vnx2df") (VNx2DF "vnx2df")]) 921 922;; Mode for vector conditional operations where the comparison has 923;; different type from the lhs. 924(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF") 925 (V2DI "V2DF") (V2SF "V2SI") 926 (V4SF "V4SI") (V2DF "V2DI")]) 927 928(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf") 929 (V2DI "v2df") (V2SF "v2si") 930 (V4SF "v4si") (V2DF "v2di")]) 931 932;; Lower case element modes (as used in shift immediate patterns). 933(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") 934 (V4HI "hi") (V8HI "hi") 935 (V2SI "si") (V4SI "si") 936 (DI "di") (V2DI "di") 937 (QI "qi") (HI "hi") 938 (SI "si")]) 939 940;; Vm for lane instructions is restricted to FP_LO_REGS. 941(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") 942 (V2SI "w") (V4SI "w") (SI "w")]) 943 944(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")]) 945 946;; This is both the number of Q-Registers needed to hold the corresponding 947;; opaque large integer mode, and the number of elements touched by the 948;; ld..._lane and st..._lane operations. 949(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) 950 951;; Mode for atomic operation suffixes 952(define_mode_attr atomic_sfx 953 [(QI "b") (HI "h") (SI "") (DI "")]) 954 955(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") 956 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf") 957 (SF "si") (DF "di") (SI "sf") (DI "df") 958 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf") 959 (V8HI "v8hf") (HF "hi") (HI "hf")]) 960(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") 961 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF") 962 (SF "SI") (DF "DI") (SI "SF") (DI "DF") 963 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF") 964 (V8HI "V8HF") (HF "HI") (HI "HF")]) 965 966 967;; for the inequal width integer to fp conversions 968(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")]) 969(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")]) 970 971(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI") 972 (V4HI "V8HI") (V8HI "V4HI") 973 (V2SI "V4SI") (V4SI "V2SI") 974 (DI "V2DI") (V2DI "DI") 975 (V2SF "V4SF") (V4SF "V2SF") 976 (V4HF "V8HF") (V8HF "V4HF") 977 (DF "V2DF") (V2DF "DF")]) 978 979(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64") 980 (V4HI "to_128") (V8HI "to_64") 981 (V2SI "to_128") (V4SI "to_64") 982 (DI "to_128") (V2DI "to_64") 983 (V4HF "to_128") (V8HF "to_64") 984 (V2SF "to_128") (V4SF "to_64") 985 (DF "to_128") (V2DF "to_64")]) 986 987;; For certain vector-by-element multiplication instructions we must 988;; constrain the 16-bit cases to use only V0-V15. This is covered by 989;; the 'x' constraint. All other modes may use the 'w' constraint. 990(define_mode_attr h_con [(V2SI "w") (V4SI "w") 991 (V4HI "x") (V8HI "x") 992 (V4HF "x") (V8HF "x") 993 (V2SF "w") (V4SF "w") 994 (V2DF "w") (DF "w")]) 995 996;; Defined to 'f' for types whose element type is a float type. 997(define_mode_attr f [(V8QI "") (V16QI "") 998 (V4HI "") (V8HI "") 999 (V2SI "") (V4SI "") 1000 (DI "") (V2DI "") 1001 (V4HF "f") (V8HF "f") 1002 (V2SF "f") (V4SF "f") 1003 (V2DF "f") (DF "f")]) 1004 1005;; Defined to '_fp' for types whose element type is a float type. 1006(define_mode_attr fp [(V8QI "") (V16QI "") 1007 (V4HI "") (V8HI "") 1008 (V2SI "") (V4SI "") 1009 (DI "") (V2DI "") 1010 (V4HF "_fp") (V8HF "_fp") 1011 (V2SF "_fp") (V4SF "_fp") 1012 (V2DF "_fp") (DF "_fp") 1013 (SF "_fp")]) 1014 1015;; Defined to '_q' for 128-bit types. 1016(define_mode_attr q [(V8QI "") (V16QI "_q") 1017 (V4HI "") (V8HI "_q") 1018 (V2SI "") (V4SI "_q") 1019 (DI "") (V2DI "_q") 1020 (V4HF "") (V8HF "_q") 1021 (V2SF "") (V4SF "_q") 1022 (V2DF "_q") 1023 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")]) 1024 1025(define_mode_attr vp [(V8QI "v") (V16QI "v") 1026 (V4HI "v") (V8HI "v") 1027 (V2SI "p") (V4SI "v") 1028 (V2DI "p") (V2DF "p") 1029 (V2SF "p") (V4SF "v") 1030 (V4HF "v") (V8HF "v")]) 1031 1032(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")]) 1033(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")]) 1034 1035 1036;; Register suffix for DOTPROD input types from the return type. 1037(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")]) 1038 1039;; Sum of lengths of instructions needed to move vector registers of a mode. 1040(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")]) 1041 1042;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32. 1043;; No need of iterator for -fPIC as it use got_lo12 for both modes. 1044(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")]) 1045 1046;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub 1047(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")]) 1048 1049(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")]) 1050 1051(define_mode_attr f16quad [(V2SF "") (V4SF "q")]) 1052 1053(define_code_attr f16mac [(plus "a") (minus "s")]) 1054 1055;; Map smax to smin and umax to umin. 1056(define_code_attr max_opp [(smax "smin") (umax "umin")]) 1057 1058;; The number of subvectors in an SVE_STRUCT. 1059(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2") 1060 (VNx8SI "2") (VNx4DI "2") 1061 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2") 1062 (VNx48QI "3") (VNx24HI "3") 1063 (VNx12SI "3") (VNx6DI "3") 1064 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3") 1065 (VNx64QI "4") (VNx32HI "4") 1066 (VNx16SI "4") (VNx8DI "4") 1067 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")]) 1068 1069;; The number of instruction bytes needed for an SVE_STRUCT move. This is 1070;; equal to vector_count * 4. 1071(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8") 1072 (VNx8SI "8") (VNx4DI "8") 1073 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8") 1074 (VNx48QI "12") (VNx24HI "12") 1075 (VNx12SI "12") (VNx6DI "12") 1076 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12") 1077 (VNx64QI "16") (VNx32HI "16") 1078 (VNx16SI "16") (VNx8DI "16") 1079 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")]) 1080 1081;; The type of a subvector in an SVE_STRUCT. 1082(define_mode_attr VSINGLE [(VNx32QI "VNx16QI") 1083 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF") 1084 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF") 1085 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF") 1086 (VNx48QI "VNx16QI") 1087 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF") 1088 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF") 1089 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF") 1090 (VNx64QI "VNx16QI") 1091 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF") 1092 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF") 1093 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")]) 1094 1095;; ...and again in lower case. 1096(define_mode_attr vsingle [(VNx32QI "vnx16qi") 1097 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf") 1098 (VNx8SI "vnx4si") (VNx8SF "vnx4sf") 1099 (VNx4DI "vnx2di") (VNx4DF "vnx2df") 1100 (VNx48QI "vnx16qi") 1101 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf") 1102 (VNx12SI "vnx4si") (VNx12SF "vnx4sf") 1103 (VNx6DI "vnx2di") (VNx6DF "vnx2df") 1104 (VNx64QI "vnx16qi") 1105 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf") 1106 (VNx16SI "vnx4si") (VNx16SF "vnx4sf") 1107 (VNx8DI "vnx2di") (VNx8DF "vnx2df")]) 1108 1109;; The predicate mode associated with an SVE data mode. For structure modes 1110;; this is equivalent to the <VPRED> of the subvector mode. 1111(define_mode_attr VPRED [(VNx16QI "VNx16BI") 1112 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI") 1113 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI") 1114 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI") 1115 (VNx32QI "VNx16BI") 1116 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI") 1117 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI") 1118 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI") 1119 (VNx48QI "VNx16BI") 1120 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI") 1121 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI") 1122 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI") 1123 (VNx64QI "VNx16BI") 1124 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI") 1125 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI") 1126 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")]) 1127 1128;; ...and again in lower case. 1129(define_mode_attr vpred [(VNx16QI "vnx16bi") 1130 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi") 1131 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi") 1132 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi") 1133 (VNx32QI "vnx16bi") 1134 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi") 1135 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi") 1136 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi") 1137 (VNx48QI "vnx16bi") 1138 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi") 1139 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi") 1140 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi") 1141 (VNx64QI "vnx16bi") 1142 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi") 1143 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi") 1144 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")]) 1145 1146;; On AArch64 the By element instruction doesn't have a 2S variant. 1147;; However because the instruction always selects a pair of values 1148;; The normal 3SAME instruction can be used here instead. 1149(define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]") 1150 (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]") 1151 ]) 1152 1153;; ------------------------------------------------------------------- 1154;; Code Iterators 1155;; ------------------------------------------------------------------- 1156 1157;; This code iterator allows the various shifts supported on the core 1158(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert]) 1159 1160;; This code iterator allows the shifts supported in arithmetic instructions 1161(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) 1162 1163;; Code iterator for logical operations 1164(define_code_iterator LOGICAL [and ior xor]) 1165 1166;; LOGICAL without AND. 1167(define_code_iterator LOGICAL_OR [ior xor]) 1168 1169;; Code iterator for logical operations whose :nlogical works on SIMD registers. 1170(define_code_iterator NLOGICAL [and ior]) 1171 1172;; Code iterator for unary negate and bitwise complement. 1173(define_code_iterator NEG_NOT [neg not]) 1174 1175;; Code iterator for sign/zero extension 1176(define_code_iterator ANY_EXTEND [sign_extend zero_extend]) 1177 1178;; All division operations (signed/unsigned) 1179(define_code_iterator ANY_DIV [div udiv]) 1180 1181;; Code iterator for sign/zero extraction 1182(define_code_iterator ANY_EXTRACT [sign_extract zero_extract]) 1183 1184;; Code iterator for equality comparisons 1185(define_code_iterator EQL [eq ne]) 1186 1187;; Code iterator for less-than and greater/equal-to 1188(define_code_iterator LTGE [lt ge]) 1189 1190;; Iterator for __sync_<op> operations that where the operation can be 1191;; represented directly RTL. This is all of the sync operations bar 1192;; nand. 1193(define_code_iterator atomic_op [plus minus ior xor and]) 1194 1195;; Iterator for integer conversions 1196(define_code_iterator FIXUORS [fix unsigned_fix]) 1197 1198;; Iterator for float conversions 1199(define_code_iterator FLOATUORS [float unsigned_float]) 1200 1201;; Code iterator for variants of vector max and min. 1202(define_code_iterator MAXMIN [smax smin umax umin]) 1203 1204(define_code_iterator FMAXMIN [smax smin]) 1205 1206;; Signed and unsigned max operations. 1207(define_code_iterator USMAX [smax umax]) 1208 1209;; Code iterator for variants of vector max and min. 1210(define_code_iterator ADDSUB [plus minus]) 1211 1212;; Code iterator for variants of vector saturating binary ops. 1213(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus]) 1214 1215;; Code iterator for variants of vector saturating unary ops. 1216(define_code_iterator UNQOPS [ss_neg ss_abs]) 1217 1218;; Code iterator for signed variants of vector saturating binary ops. 1219(define_code_iterator SBINQOPS [ss_plus ss_minus]) 1220 1221;; Comparison operators for <F>CM. 1222(define_code_iterator COMPARISONS [lt le eq ge gt]) 1223 1224;; Unsigned comparison operators. 1225(define_code_iterator UCOMPARISONS [ltu leu geu gtu]) 1226 1227;; Unsigned comparison operators. 1228(define_code_iterator FAC_COMPARISONS [lt le ge gt]) 1229 1230;; SVE integer unary operations. 1231(define_code_iterator SVE_INT_UNARY [abs neg not popcount]) 1232 1233;; SVE floating-point unary operations. 1234(define_code_iterator SVE_FP_UNARY [abs neg sqrt]) 1235 1236;; SVE integer binary operations. 1237(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin 1238 and ior xor]) 1239 1240;; SVE integer binary division operations. 1241(define_code_iterator SVE_INT_BINARY_SD [div udiv]) 1242 1243;; SVE floating-point operations with an unpredicated all-register form. 1244(define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult]) 1245 1246;; SVE integer comparisons. 1247(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu]) 1248 1249;; SVE floating-point comparisons. 1250(define_code_iterator SVE_FP_CMP [lt le eq ne ge gt]) 1251 1252;; ------------------------------------------------------------------- 1253;; Code Attributes 1254;; ------------------------------------------------------------------- 1255;; Map rtl objects to optab names 1256(define_code_attr optab [(ashift "ashl") 1257 (ashiftrt "ashr") 1258 (lshiftrt "lshr") 1259 (rotatert "rotr") 1260 (sign_extend "extend") 1261 (zero_extend "zero_extend") 1262 (sign_extract "extv") 1263 (zero_extract "extzv") 1264 (fix "fix") 1265 (unsigned_fix "fixuns") 1266 (float "float") 1267 (unsigned_float "floatuns") 1268 (popcount "popcount") 1269 (and "and") 1270 (ior "ior") 1271 (xor "xor") 1272 (not "one_cmpl") 1273 (neg "neg") 1274 (plus "add") 1275 (minus "sub") 1276 (mult "mul") 1277 (div "div") 1278 (udiv "udiv") 1279 (ss_plus "qadd") 1280 (us_plus "qadd") 1281 (ss_minus "qsub") 1282 (us_minus "qsub") 1283 (ss_neg "qneg") 1284 (ss_abs "qabs") 1285 (smin "smin") 1286 (smax "smax") 1287 (umin "umin") 1288 (umax "umax") 1289 (eq "eq") 1290 (ne "ne") 1291 (lt "lt") 1292 (ge "ge") 1293 (le "le") 1294 (gt "gt") 1295 (ltu "ltu") 1296 (leu "leu") 1297 (geu "geu") 1298 (gtu "gtu") 1299 (abs "abs") 1300 (sqrt "sqrt")]) 1301 1302;; For comparison operators we use the FCM* and CM* instructions. 1303;; As there are no CMLE or CMLT instructions which act on 3 vector 1304;; operands, we must use CMGE or CMGT and swap the order of the 1305;; source operands. 1306 1307(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") 1308 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) 1309(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") 1310 (ltu "2") (leu "2") (geu "1") (gtu "1")]) 1311(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") 1312 (ltu "1") (leu "1") (geu "2") (gtu "2")]) 1313 1314(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") 1315 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU") 1316 (gtu "GTU")]) 1317 1318;; The AArch64 condition associated with an rtl comparison code. 1319(define_code_attr cmp_op [(lt "lt") 1320 (le "le") 1321 (eq "eq") 1322 (ne "ne") 1323 (ge "ge") 1324 (gt "gt") 1325 (ltu "lo") 1326 (leu "ls") 1327 (geu "hs") 1328 (gtu "hi")]) 1329 1330(define_code_attr fix_trunc_optab [(fix "fix_trunc") 1331 (unsigned_fix "fixuns_trunc")]) 1332 1333;; Optab prefix for sign/zero-extending operations 1334(define_code_attr su_optab [(sign_extend "") (zero_extend "u") 1335 (div "") (udiv "u") 1336 (fix "") (unsigned_fix "u") 1337 (float "s") (unsigned_float "u") 1338 (ss_plus "s") (us_plus "u") 1339 (ss_minus "s") (us_minus "u")]) 1340 1341;; Similar for the instruction mnemonics 1342(define_code_attr shift [(ashift "lsl") (ashiftrt "asr") 1343 (lshiftrt "lsr") (rotatert "ror")]) 1344 1345;; Map shift operators onto underlying bit-field instructions 1346(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") 1347 (lshiftrt "ubfx") (rotatert "extr")]) 1348 1349;; Logical operator instruction mnemonics 1350(define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) 1351 1352;; Operation names for negate and bitwise complement. 1353(define_code_attr neg_not_op [(neg "neg") (not "not")]) 1354 1355;; Similar, but when the second operand is inverted. 1356(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) 1357 1358;; Similar, but when both operands are inverted. 1359(define_code_attr logical_nn [(and "nor") (ior "nand")]) 1360 1361;; Sign- or zero-extending data-op 1362(define_code_attr su [(sign_extend "s") (zero_extend "u") 1363 (sign_extract "s") (zero_extract "u") 1364 (fix "s") (unsigned_fix "u") 1365 (div "s") (udiv "u") 1366 (smax "s") (umax "u") 1367 (smin "s") (umin "u")]) 1368 1369;; Whether a shift is left or right. 1370(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")]) 1371 1372;; Emit conditional branch instructions. 1373(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")]) 1374 1375;; Emit cbz/cbnz depending on comparison type. 1376(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) 1377 1378;; Emit inverted cbz/cbnz depending on comparison type. 1379(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")]) 1380 1381;; Emit tbz/tbnz depending on comparison type. 1382(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) 1383 1384;; Emit inverted tbz/tbnz depending on comparison type. 1385(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")]) 1386 1387;; Max/min attributes. 1388(define_code_attr maxmin [(smax "max") 1389 (smin "min") 1390 (umax "max") 1391 (umin "min")]) 1392 1393;; MLA/MLS attributes. 1394(define_code_attr as [(ss_plus "a") (ss_minus "s")]) 1395 1396;; Atomic operations 1397(define_code_attr atomic_optab 1398 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")]) 1399 1400(define_code_attr atomic_op_operand 1401 [(ior "aarch64_logical_operand") 1402 (xor "aarch64_logical_operand") 1403 (and "aarch64_logical_operand") 1404 (plus "aarch64_plus_operand") 1405 (minus "aarch64_plus_operand")]) 1406 1407;; Constants acceptable for atomic operations. 1408;; This definition must appear in this file before the iterators it refers to. 1409(define_code_attr const_atomic 1410 [(plus "IJ") (minus "IJ") 1411 (xor "<lconst_atomic>") (ior "<lconst_atomic>") 1412 (and "<lconst_atomic>")]) 1413 1414;; Attribute to describe constants acceptable in atomic logical operations 1415(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")]) 1416 1417;; The integer SVE instruction that implements an rtx code. 1418(define_code_attr sve_int_op [(plus "add") 1419 (minus "sub") 1420 (mult "mul") 1421 (div "sdiv") 1422 (udiv "udiv") 1423 (abs "abs") 1424 (neg "neg") 1425 (smin "smin") 1426 (smax "smax") 1427 (umin "umin") 1428 (umax "umax") 1429 (and "and") 1430 (ior "orr") 1431 (xor "eor") 1432 (not "not") 1433 (popcount "cnt")]) 1434 1435(define_code_attr sve_int_op_rev [(plus "add") 1436 (minus "subr") 1437 (mult "mul") 1438 (div "sdivr") 1439 (udiv "udivr") 1440 (smin "smin") 1441 (smax "smax") 1442 (umin "umin") 1443 (umax "umax") 1444 (and "and") 1445 (ior "orr") 1446 (xor "eor")]) 1447 1448;; The floating-point SVE instruction that implements an rtx code. 1449(define_code_attr sve_fp_op [(plus "fadd") 1450 (minus "fsub") 1451 (mult "fmul") 1452 (neg "fneg") 1453 (abs "fabs") 1454 (sqrt "fsqrt")]) 1455 1456;; The SVE immediate constraint to use for an rtl code. 1457(define_code_attr sve_imm_con [(eq "vsc") 1458 (ne "vsc") 1459 (lt "vsc") 1460 (ge "vsc") 1461 (le "vsc") 1462 (gt "vsc") 1463 (ltu "vsd") 1464 (leu "vsd") 1465 (geu "vsd") 1466 (gtu "vsd")]) 1467 1468;; ------------------------------------------------------------------- 1469;; Int Iterators. 1470;; ------------------------------------------------------------------- 1471 1472;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions. 1473(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL]) 1474 1475;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions. 1476(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2]) 1477 1478;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions. 1479(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP]) 1480 1481(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV 1482 UNSPEC_SMAXV UNSPEC_SMINV]) 1483 1484(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV 1485 UNSPEC_FMAXNMV UNSPEC_FMINNMV]) 1486 1487(define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV]) 1488 1489(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF]) 1490 1491(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD 1492 UNSPEC_SRHADD UNSPEC_URHADD 1493 UNSPEC_SHSUB UNSPEC_UHSUB 1494 UNSPEC_SRHSUB UNSPEC_URHSUB]) 1495 1496(define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD]) 1497 1498(define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD]) 1499 1500(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT]) 1501 1502(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN 1503 UNSPEC_SUBHN UNSPEC_RSUBHN]) 1504 1505(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 1506 UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) 1507 1508(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN 1509 UNSPEC_FMAXNM UNSPEC_FMINNM]) 1510 1511(define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP]) 1512 1513(define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716]) 1514 1515(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) 1516 1517(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) 1518 1519(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN]) 1520 1521(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL 1522 UNSPEC_SRSHL UNSPEC_URSHL]) 1523 1524(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL]) 1525 1526(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL 1527 UNSPEC_SQRSHL UNSPEC_UQRSHL]) 1528 1529(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA 1530 UNSPEC_SRSRA UNSPEC_URSRA]) 1531 1532(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI 1533 UNSPEC_SSRI UNSPEC_USRI]) 1534 1535 1536(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR]) 1537 1538(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) 1539 1540(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN 1541 UNSPEC_SQSHRN UNSPEC_UQSHRN 1542 UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) 1543 1544(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH]) 1545 1546(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 1547 UNSPEC_TRN1 UNSPEC_TRN2 1548 UNSPEC_UZP1 UNSPEC_UZP2]) 1549 1550(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 1551 UNSPEC_UZP1 UNSPEC_UZP2]) 1552 1553(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) 1554 1555(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM 1556 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX 1557 UNSPEC_FRINTA]) 1558 1559(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM 1560 UNSPEC_FRINTA UNSPEC_FRINTN]) 1561 1562(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU]) 1563(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF]) 1564 1565(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W 1566 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH 1567 UNSPEC_CRC32CW UNSPEC_CRC32CX]) 1568 1569(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD]) 1570(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) 1571 1572(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) 1573 1574(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) 1575 1576(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2]) 1577 1578(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B 1579 UNSPEC_SM3TT2A UNSPEC_SM3TT2B]) 1580 1581(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2]) 1582 1583;; Iterators for fp16 operations 1584 1585(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL]) 1586 1587(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2]) 1588 1589(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI 1590 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO]) 1591 1592(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI]) 1593 1594(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART]) 1595 1596(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_ADD UNSPEC_COND_SUB 1597 UNSPEC_COND_MUL UNSPEC_COND_DIV 1598 UNSPEC_COND_MAX UNSPEC_COND_MIN]) 1599 1600(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA 1601 UNSPEC_COND_FMLS 1602 UNSPEC_COND_FNMLA 1603 UNSPEC_COND_FNMLS]) 1604 1605(define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE 1606 UNSPEC_COND_EQ UNSPEC_COND_NE 1607 UNSPEC_COND_GE UNSPEC_COND_GT]) 1608 1609(define_int_iterator FCADD [UNSPEC_FCADD90 1610 UNSPEC_FCADD270]) 1611 1612(define_int_iterator FCMLA [UNSPEC_FCMLA 1613 UNSPEC_FCMLA90 1614 UNSPEC_FCMLA180 1615 UNSPEC_FCMLA270]) 1616 1617;; Iterators for atomic operations. 1618 1619(define_int_iterator ATOMIC_LDOP 1620 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC 1621 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS]) 1622 1623(define_int_attr atomic_ldop 1624 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr") 1625 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) 1626 1627(define_int_attr atomic_ldoptab 1628 [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic") 1629 (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) 1630 1631;; ------------------------------------------------------------------- 1632;; Int Iterators Attributes. 1633;; ------------------------------------------------------------------- 1634 1635;; The optab associated with an operation. Note that for ANDF, IORF 1636;; and XORF, the optab pattern is not actually defined; we just use this 1637;; name for consistency with the integer patterns. 1638(define_int_attr optab [(UNSPEC_ANDF "and") 1639 (UNSPEC_IORF "ior") 1640 (UNSPEC_XORF "xor") 1641 (UNSPEC_ANDV "and") 1642 (UNSPEC_IORV "ior") 1643 (UNSPEC_XORV "xor") 1644 (UNSPEC_COND_ADD "add") 1645 (UNSPEC_COND_SUB "sub") 1646 (UNSPEC_COND_MUL "mul") 1647 (UNSPEC_COND_DIV "div") 1648 (UNSPEC_COND_MAX "smax") 1649 (UNSPEC_COND_MIN "smin") 1650 (UNSPEC_COND_FMLA "fma") 1651 (UNSPEC_COND_FMLS "fnma") 1652 (UNSPEC_COND_FNMLA "fnms") 1653 (UNSPEC_COND_FNMLS "fms")]) 1654 1655(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") 1656 (UNSPEC_UMINV "umin") 1657 (UNSPEC_SMAXV "smax") 1658 (UNSPEC_SMINV "smin") 1659 (UNSPEC_FMAX "smax_nan") 1660 (UNSPEC_FMAXNMV "smax") 1661 (UNSPEC_FMAXV "smax_nan") 1662 (UNSPEC_FMIN "smin_nan") 1663 (UNSPEC_FMINNMV "smin") 1664 (UNSPEC_FMINV "smin_nan") 1665 (UNSPEC_FMAXNM "fmax") 1666 (UNSPEC_FMINNM "fmin")]) 1667 1668(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") 1669 (UNSPEC_UMINV "umin") 1670 (UNSPEC_SMAXV "smax") 1671 (UNSPEC_SMINV "smin") 1672 (UNSPEC_FMAX "fmax") 1673 (UNSPEC_FMAXNMV "fmaxnm") 1674 (UNSPEC_FMAXV "fmax") 1675 (UNSPEC_FMIN "fmin") 1676 (UNSPEC_FMINNMV "fminnm") 1677 (UNSPEC_FMINV "fmin") 1678 (UNSPEC_FMAXNM "fmaxnm") 1679 (UNSPEC_FMINNM "fminnm")]) 1680 1681(define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv") 1682 (UNSPEC_IORV "orv") 1683 (UNSPEC_XORV "eorv")]) 1684 1685;; The SVE logical instruction that implements an unspec. 1686(define_int_attr logicalf_op [(UNSPEC_ANDF "and") 1687 (UNSPEC_IORF "orr") 1688 (UNSPEC_XORF "eor")]) 1689 1690;; "s" for signed operations and "u" for unsigned ones. 1691(define_int_attr su [(UNSPEC_UNPACKSHI "s") 1692 (UNSPEC_UNPACKUHI "u") 1693 (UNSPEC_UNPACKSLO "s") 1694 (UNSPEC_UNPACKULO "u") 1695 (UNSPEC_SMUL_HIGHPART "s") 1696 (UNSPEC_UMUL_HIGHPART "u")]) 1697 1698(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") 1699 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") 1700 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") 1701 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur") 1702 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") 1703 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u") 1704 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u") 1705 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u") 1706 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") 1707 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") 1708 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") 1709 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") 1710 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") 1711 (UNSPEC_SSLI "s") (UNSPEC_USLI "u") 1712 (UNSPEC_SSRI "s") (UNSPEC_USRI "u") 1713 (UNSPEC_USRA "u") (UNSPEC_SSRA "s") 1714 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr") 1715 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") 1716 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") 1717 (UNSPEC_UQSHL "u") 1718 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") 1719 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") 1720 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") 1721 (UNSPEC_USHL "u") (UNSPEC_SSHL "s") 1722 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") 1723 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") 1724 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") 1725 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u") 1726]) 1727 1728(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") 1729 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") 1730 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") 1731 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") 1732 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") 1733 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") 1734]) 1735 1736(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") 1737 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")]) 1738 1739(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") 1740 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") 1741 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") 1742 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "") 1743 (UNSPEC_SHADD "") (UNSPEC_UHADD "u") 1744 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")]) 1745 1746(define_int_attr addsub [(UNSPEC_SHADD "add") 1747 (UNSPEC_UHADD "add") 1748 (UNSPEC_SRHADD "add") 1749 (UNSPEC_URHADD "add") 1750 (UNSPEC_SHSUB "sub") 1751 (UNSPEC_UHSUB "sub") 1752 (UNSPEC_SRHSUB "sub") 1753 (UNSPEC_URHSUB "sub") 1754 (UNSPEC_ADDHN "add") 1755 (UNSPEC_SUBHN "sub") 1756 (UNSPEC_RADDHN "add") 1757 (UNSPEC_RSUBHN "sub") 1758 (UNSPEC_ADDHN2 "add") 1759 (UNSPEC_SUBHN2 "sub") 1760 (UNSPEC_RADDHN2 "add") 1761 (UNSPEC_RSUBHN2 "sub")]) 1762 1763(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "") 1764 (UNSPEC_SSRI "offset_") 1765 (UNSPEC_USRI "offset_")]) 1766 1767;; Standard pattern names for floating-point rounding instructions. 1768(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") 1769 (UNSPEC_FRINTP "ceil") 1770 (UNSPEC_FRINTM "floor") 1771 (UNSPEC_FRINTI "nearbyint") 1772 (UNSPEC_FRINTX "rint") 1773 (UNSPEC_FRINTA "round") 1774 (UNSPEC_FRINTN "frintn")]) 1775 1776;; frint suffix for floating-point rounding instructions. 1777(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") 1778 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") 1779 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") 1780 (UNSPEC_FRINTN "n")]) 1781 1782(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") 1783 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") 1784 (UNSPEC_FRINTN "frintn")]) 1785 1786(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf") 1787 (UNSPEC_UCVTF "ucvtf") 1788 (UNSPEC_FCVTZS "fcvtzs") 1789 (UNSPEC_FCVTZU "fcvtzu")]) 1790 1791;; Pointer authentication mnemonic prefix. 1792(define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci") 1793 (UNSPEC_AUTISP "auti") 1794 (UNSPEC_PACI1716 "paci") 1795 (UNSPEC_AUTI1716 "auti")]) 1796 1797;; Pointer authentication HINT number for NOP space instructions using A Key. 1798(define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25") 1799 (UNSPEC_AUTISP "29") 1800 (UNSPEC_PACI1716 "8") 1801 (UNSPEC_AUTI1716 "12")]) 1802 1803(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") 1804 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") 1805 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")]) 1806 1807; op code for REV instructions (size within which elements are reversed). 1808(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") 1809 (UNSPEC_REV16 "16")]) 1810 1811(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") 1812 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") 1813 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2") 1814 (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi") 1815 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")]) 1816 1817;; Return true if the associated optab refers to the high-numbered lanes, 1818;; false if it refers to the low-numbered lanes. The convention is for 1819;; "hi" to refer to the low-numbered lanes (the first ones in memory) 1820;; for big-endian. 1821(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN") 1822 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN") 1823 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN") 1824 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")]) 1825 1826(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") 1827 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") 1828 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") 1829 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")]) 1830 1831(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") 1832 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI") 1833 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI") 1834 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")]) 1835 1836(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")]) 1837(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")]) 1838 1839(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p") 1840 (UNSPEC_SHA1M "m")]) 1841 1842(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) 1843 1844(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")]) 1845 1846(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")]) 1847 1848(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b") 1849 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")]) 1850 1851(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")]) 1852 1853(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s") 1854 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")]) 1855 1856;; The condition associated with an UNSPEC_COND_<xx>. 1857(define_int_attr cmp_op [(UNSPEC_COND_LT "lt") 1858 (UNSPEC_COND_LE "le") 1859 (UNSPEC_COND_EQ "eq") 1860 (UNSPEC_COND_NE "ne") 1861 (UNSPEC_COND_GE "ge") 1862 (UNSPEC_COND_GT "gt")]) 1863 1864(define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd") 1865 (UNSPEC_COND_SUB "fsub") 1866 (UNSPEC_COND_MUL "fmul") 1867 (UNSPEC_COND_DIV "fdiv") 1868 (UNSPEC_COND_MAX "fmaxnm") 1869 (UNSPEC_COND_MIN "fminnm")]) 1870 1871(define_int_attr sve_fp_op_rev [(UNSPEC_COND_ADD "fadd") 1872 (UNSPEC_COND_SUB "fsubr") 1873 (UNSPEC_COND_MUL "fmul") 1874 (UNSPEC_COND_DIV "fdivr") 1875 (UNSPEC_COND_MAX "fmaxnm") 1876 (UNSPEC_COND_MIN "fminnm")]) 1877 1878(define_int_attr rot [(UNSPEC_FCADD90 "90") 1879 (UNSPEC_FCADD270 "270") 1880 (UNSPEC_FCMLA "0") 1881 (UNSPEC_FCMLA90 "90") 1882 (UNSPEC_FCMLA180 "180") 1883 (UNSPEC_FCMLA270 "270")]) 1884 1885(define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla") 1886 (UNSPEC_COND_FMLS "fmls") 1887 (UNSPEC_COND_FNMLA "fnmla") 1888 (UNSPEC_COND_FNMLS "fnmls")]) 1889 1890(define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad") 1891 (UNSPEC_COND_FMLS "fmsb") 1892 (UNSPEC_COND_FNMLA "fnmad") 1893 (UNSPEC_COND_FNMLS "fnmsb")]) 1894 1895(define_int_attr commutative [(UNSPEC_COND_ADD "true") 1896 (UNSPEC_COND_SUB "false") 1897 (UNSPEC_COND_MUL "true") 1898 (UNSPEC_COND_DIV "false") 1899 (UNSPEC_COND_MIN "true") 1900 (UNSPEC_COND_MAX "true")]) 1901