1;; Machine description for AArch64 architecture. 2;; Copyright (C) 2009-2015 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; ------------------------------------------------------------------- 22;; Mode Iterators 23;; ------------------------------------------------------------------- 24 25 26;; Iterator for General Purpose Integer registers (32- and 64-bit modes) 27(define_mode_iterator GPI [SI DI]) 28 29;; Iterator for QI and HI modes 30(define_mode_iterator SHORT [QI HI]) 31 32;; Iterator for all integer modes (up to 64-bit) 33(define_mode_iterator ALLI [QI HI SI DI]) 34 35;; Iterator for all integer modes that can be extended (up to 64-bit) 36(define_mode_iterator ALLX [QI HI SI]) 37 38;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) 39(define_mode_iterator GPF [SF DF]) 40 41;; Integer vector modes. 42(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) 43 44;; vector and scalar, 64 & 128-bit container, all integer modes 45(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) 46 47;; vector and scalar, 64 & 128-bit container: all vector integer modes; 48;; 64-bit scalar integer mode 49(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) 50 51;; Double vector modes. 52(define_mode_iterator VD [V8QI V4HI V2SI V2SF]) 53 54;; vector, 64-bit container, all integer modes 55(define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) 56 57;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes 58(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) 59 60;; Quad vector modes. 61(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF]) 62 63;; VQ without 2 element modes. 64(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V4SF]) 65 66;; Quad vector with only 2 element modes. 67(define_mode_iterator VQ_2E [V2DI V2DF]) 68 69;; This mode iterator allows :P to be used for patterns that operate on 70;; addresses in different modes. In LP64, only DI will match, while in 71;; ILP32, either can match. 72(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode") 73 (DI "ptr_mode == DImode || Pmode == DImode")]) 74 75;; This mode iterator allows :PTR to be used for patterns that operate on 76;; pointer-sized quantities. Exactly one of the two alternatives will match. 77(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) 78 79;; Vector Float modes. 80(define_mode_iterator VDQF [V2SF V4SF V2DF]) 81 82;; Vector Float modes, and DF. 83(define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF]) 84 85;; Vector single Float modes. 86(define_mode_iterator VDQSF [V2SF V4SF]) 87 88;; Modes suitable to use as the return type of a vcond expression. 89(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) 90 91;; All Float modes. 92(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) 93 94;; Vector Float modes with 2 elements. 95(define_mode_iterator V2F [V2SF V2DF]) 96 97;; All modes. 98(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) 99 100;; All vector modes and DI. 101(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) 102 103;; All vector modes and DI and DF. 104(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI 105 V2DI V2SF V4SF V2DF DI DF]) 106 107;; Vector modes for Integer reduction across lanes. 108(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) 109 110;; Vector modes(except V2DI) for Integer reduction across lanes. 111(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI]) 112 113;; All double integer narrow-able modes. 114(define_mode_iterator VDN [V4HI V2SI DI]) 115 116;; All quad integer narrow-able modes. 117(define_mode_iterator VQN [V8HI V4SI V2DI]) 118 119;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes 120(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) 121 122;; All quad integer widen-able modes. 123(define_mode_iterator VQW [V16QI V8HI V4SI]) 124 125;; Double vector modes for combines. 126(define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF]) 127 128;; Vector modes except double int. 129(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) 130 131;; Vector modes for S type. 132(define_mode_iterator VDQ_SI [V2SI V4SI]) 133 134;; Vector modes for Q and H types. 135(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) 136 137;; Vector modes for H and S types. 138(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) 139 140;; Vector modes for H, S and D types. 141(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) 142 143;; Vector and scalar integer modes for H and S 144(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) 145 146;; Vector and scalar 64-bit container: 16, 32-bit integer modes 147(define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) 148 149;; Vector 64-bit container: 16, 32-bit integer modes 150(define_mode_iterator VD_HSI [V4HI V2SI]) 151 152;; Scalar 64-bit container: 16, 32-bit integer modes 153(define_mode_iterator SD_HSI [HI SI]) 154 155;; Vector 64-bit container: 16, 32-bit integer modes 156(define_mode_iterator VQ_HSI [V8HI V4SI]) 157 158;; All byte modes. 159(define_mode_iterator VB [V8QI V16QI]) 160 161;; 2 and 4 lane SI modes. 162(define_mode_iterator VS [V2SI V4SI]) 163 164(define_mode_iterator TX [TI TF]) 165 166;; Opaque structure modes. 167(define_mode_iterator VSTRUCT [OI CI XI]) 168 169;; Double scalar modes 170(define_mode_iterator DX [DI DF]) 171 172;; Modes available for <f>mul lane operations. 173(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) 174 175;; Modes available for <f>mul lane operations changing lane count. 176(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF]) 177 178;; ------------------------------------------------------------------ 179;; Unspec enumerations for Advance SIMD. These could well go into 180;; aarch64.md but for their use in int_iterators here. 181;; ------------------------------------------------------------------ 182 183(define_c_enum "unspec" 184 [ 185 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. 186 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. 187 UNSPEC_ABS ; Used in aarch64-simd.md. 188 UNSPEC_FMAX ; Used in aarch64-simd.md. 189 UNSPEC_FMAXNMV ; Used in aarch64-simd.md. 190 UNSPEC_FMAXV ; Used in aarch64-simd.md. 191 UNSPEC_FMIN ; Used in aarch64-simd.md. 192 UNSPEC_FMINNMV ; Used in aarch64-simd.md. 193 UNSPEC_FMINV ; Used in aarch64-simd.md. 194 UNSPEC_FADDV ; Used in aarch64-simd.md. 195 UNSPEC_ADDV ; Used in aarch64-simd.md. 196 UNSPEC_SMAXV ; Used in aarch64-simd.md. 197 UNSPEC_SMINV ; Used in aarch64-simd.md. 198 UNSPEC_UMAXV ; Used in aarch64-simd.md. 199 UNSPEC_UMINV ; Used in aarch64-simd.md. 200 UNSPEC_SHADD ; Used in aarch64-simd.md. 201 UNSPEC_UHADD ; Used in aarch64-simd.md. 202 UNSPEC_SRHADD ; Used in aarch64-simd.md. 203 UNSPEC_URHADD ; Used in aarch64-simd.md. 204 UNSPEC_SHSUB ; Used in aarch64-simd.md. 205 UNSPEC_UHSUB ; Used in aarch64-simd.md. 206 UNSPEC_SRHSUB ; Used in aarch64-simd.md. 207 UNSPEC_URHSUB ; Used in aarch64-simd.md. 208 UNSPEC_ADDHN ; Used in aarch64-simd.md. 209 UNSPEC_RADDHN ; Used in aarch64-simd.md. 210 UNSPEC_SUBHN ; Used in aarch64-simd.md. 211 UNSPEC_RSUBHN ; Used in aarch64-simd.md. 212 UNSPEC_ADDHN2 ; Used in aarch64-simd.md. 213 UNSPEC_RADDHN2 ; Used in aarch64-simd.md. 214 UNSPEC_SUBHN2 ; Used in aarch64-simd.md. 215 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md. 216 UNSPEC_SQDMULH ; Used in aarch64-simd.md. 217 UNSPEC_SQRDMULH ; Used in aarch64-simd.md. 218 UNSPEC_PMUL ; Used in aarch64-simd.md. 219 UNSPEC_USQADD ; Used in aarch64-simd.md. 220 UNSPEC_SUQADD ; Used in aarch64-simd.md. 221 UNSPEC_SQXTUN ; Used in aarch64-simd.md. 222 UNSPEC_SQXTN ; Used in aarch64-simd.md. 223 UNSPEC_UQXTN ; Used in aarch64-simd.md. 224 UNSPEC_SSRA ; Used in aarch64-simd.md. 225 UNSPEC_USRA ; Used in aarch64-simd.md. 226 UNSPEC_SRSRA ; Used in aarch64-simd.md. 227 UNSPEC_URSRA ; Used in aarch64-simd.md. 228 UNSPEC_SRSHR ; Used in aarch64-simd.md. 229 UNSPEC_URSHR ; Used in aarch64-simd.md. 230 UNSPEC_SQSHLU ; Used in aarch64-simd.md. 231 UNSPEC_SQSHL ; Used in aarch64-simd.md. 232 UNSPEC_UQSHL ; Used in aarch64-simd.md. 233 UNSPEC_SQSHRUN ; Used in aarch64-simd.md. 234 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md. 235 UNSPEC_SQSHRN ; Used in aarch64-simd.md. 236 UNSPEC_UQSHRN ; Used in aarch64-simd.md. 237 UNSPEC_SQRSHRN ; Used in aarch64-simd.md. 238 UNSPEC_UQRSHRN ; Used in aarch64-simd.md. 239 UNSPEC_SSHL ; Used in aarch64-simd.md. 240 UNSPEC_USHL ; Used in aarch64-simd.md. 241 UNSPEC_SRSHL ; Used in aarch64-simd.md. 242 UNSPEC_URSHL ; Used in aarch64-simd.md. 243 UNSPEC_SQRSHL ; Used in aarch64-simd.md. 244 UNSPEC_UQRSHL ; Used in aarch64-simd.md. 245 UNSPEC_SSLI ; Used in aarch64-simd.md. 246 UNSPEC_USLI ; Used in aarch64-simd.md. 247 UNSPEC_SSRI ; Used in aarch64-simd.md. 248 UNSPEC_USRI ; Used in aarch64-simd.md. 249 UNSPEC_SSHLL ; Used in aarch64-simd.md. 250 UNSPEC_USHLL ; Used in aarch64-simd.md. 251 UNSPEC_ADDP ; Used in aarch64-simd.md. 252 UNSPEC_TBL ; Used in vector permute patterns. 253 UNSPEC_CONCAT ; Used in vector permute patterns. 254 UNSPEC_ZIP1 ; Used in vector permute patterns. 255 UNSPEC_ZIP2 ; Used in vector permute patterns. 256 UNSPEC_UZP1 ; Used in vector permute patterns. 257 UNSPEC_UZP2 ; Used in vector permute patterns. 258 UNSPEC_TRN1 ; Used in vector permute patterns. 259 UNSPEC_TRN2 ; Used in vector permute patterns. 260 UNSPEC_EXT ; Used in aarch64-simd.md. 261 UNSPEC_REV64 ; Used in vector reverse patterns (permute). 262 UNSPEC_REV32 ; Used in vector reverse patterns (permute). 263 UNSPEC_REV16 ; Used in vector reverse patterns (permute). 264 UNSPEC_AESE ; Used in aarch64-simd.md. 265 UNSPEC_AESD ; Used in aarch64-simd.md. 266 UNSPEC_AESMC ; Used in aarch64-simd.md. 267 UNSPEC_AESIMC ; Used in aarch64-simd.md. 268 UNSPEC_SHA1C ; Used in aarch64-simd.md. 269 UNSPEC_SHA1M ; Used in aarch64-simd.md. 270 UNSPEC_SHA1P ; Used in aarch64-simd.md. 271 UNSPEC_SHA1H ; Used in aarch64-simd.md. 272 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md. 273 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md. 274 UNSPEC_SHA256H ; Used in aarch64-simd.md. 275 UNSPEC_SHA256H2 ; Used in aarch64-simd.md. 276 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. 277 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. 278 UNSPEC_PMULL ; Used in aarch64-simd.md. 279 UNSPEC_PMULL2 ; Used in aarch64-simd.md. 280 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. 281 UNSPEC_VEC_SHR ; Used in aarch64-simd.md. 282]) 283 284;; ------------------------------------------------------------------- 285;; Mode attributes 286;; ------------------------------------------------------------------- 287 288;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the 289;; 32-bit version and "%x0" in the 64-bit version. 290(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) 291 292;; For inequal width int to float conversion 293(define_mode_attr w1 [(SF "w") (DF "x")]) 294(define_mode_attr w2 [(SF "x") (DF "w")]) 295 296;; For constraints used in scalar immediate vector moves 297(define_mode_attr hq [(HI "h") (QI "q")]) 298 299;; For doubling width of an integer mode 300(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) 301 302;; For scalar usage of vector/FP registers 303(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") 304 (SF "s") (DF "d") 305 (V8QI "") (V16QI "") 306 (V4HI "") (V8HI "") 307 (V2SI "") (V4SI "") 308 (V2DI "") (V2SF "") 309 (V4SF "") (V2DF "")]) 310 311;; For scalar usage of vector/FP registers, narrowing 312(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") 313 (V8QI "") (V16QI "") 314 (V4HI "") (V8HI "") 315 (V2SI "") (V4SI "") 316 (V2DI "") (V2SF "") 317 (V4SF "") (V2DF "")]) 318 319;; For scalar usage of vector/FP registers, widening 320(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") 321 (V8QI "") (V16QI "") 322 (V4HI "") (V8HI "") 323 (V2SI "") (V4SI "") 324 (V2DI "") (V2SF "") 325 (V4SF "") (V2DF "")]) 326 327;; Register Type Name and Vector Arrangement Specifier for when 328;; we are doing scalar for DI and SIMD for SI (ignoring all but 329;; lane 0). 330(define_mode_attr rtn [(DI "d") (SI "")]) 331(define_mode_attr vas [(DI "") (SI ".2s")]) 332 333;; Map a floating point mode to the appropriate register name prefix 334(define_mode_attr s [(SF "s") (DF "d")]) 335 336;; Give the length suffix letter for a sign- or zero-extension. 337(define_mode_attr size [(QI "b") (HI "h") (SI "w")]) 338 339;; Give the number of bits in the mode 340(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) 341 342;; Give the ordinal of the MSB in the mode 343(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")]) 344 345;; Attribute to describe constants acceptable in logical operations 346(define_mode_attr lconst [(SI "K") (DI "L")]) 347 348;; Map a mode to a specific constraint character. 349(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) 350 351(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") 352 (V4HI "4h") (V8HI "8h") 353 (V2SI "2s") (V4SI "4s") 354 (DI "1d") (DF "1d") 355 (V2DI "2d") (V2SF "2s") 356 (V4SF "4s") (V2DF "2d")]) 357 358(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32") 359 (V4SI "32") (V2DI "64")]) 360 361(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") 362 (V4HI ".4h") (V8HI ".8h") 363 (V2SI ".2s") (V4SI ".4s") 364 (V2DI ".2d") (V2SF ".2s") 365 (V4SF ".4s") (V2DF ".2d") 366 (DI "") (SI "") 367 (HI "") (QI "") 368 (TI "") (SF "") 369 (DF "")]) 370 371;; Register suffix narrowed modes for VQN. 372(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") 373 (V2DI ".2s") 374 (DI "") (SI "") 375 (HI "")]) 376 377;; Mode-to-individual element type mapping. 378(define_mode_attr Vetype [(V8QI "b") (V16QI "b") 379 (V4HI "h") (V8HI "h") 380 (V2SI "s") (V4SI "s") 381 (V2DI "d") (V2SF "s") 382 (V4SF "s") (V2DF "d") 383 (SF "s") (DF "d") 384 (QI "b") (HI "h") 385 (SI "s") (DI "d")]) 386 387;; Mode-to-bitwise operation type mapping. 388(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") 389 (V4HI "8b") (V8HI "16b") 390 (V2SI "8b") (V4SI "16b") 391 (V2DI "16b") (V2SF "8b") 392 (V4SF "16b") (V2DF "16b") 393 (DI "8b") (DF "8b") 394 (SI "8b")]) 395 396;; Define element mode for each vector mode. 397(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") 398 (V4HI "HI") (V8HI "HI") 399 (V2SI "SI") (V4SI "SI") 400 (DI "DI") (V2DI "DI") 401 (V2SF "SF") (V4SF "SF") 402 (V2DF "DF") (DF "DF") 403 (SI "SI") (HI "HI") 404 (QI "QI")]) 405 406;; 64-bit container modes the inner or scalar source mode. 407(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI") 408 (V4HI "V4HI") (V8HI "V4HI") 409 (V2SI "V2SI") (V4SI "V2SI") 410 (DI "DI") (V2DI "DI") 411 (V2SF "V2SF") (V4SF "V2SF") 412 (V2DF "DF")]) 413 414;; 128-bit container modes the inner or scalar source mode. 415(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI") 416 (V4HI "V8HI") (V8HI "V8HI") 417 (V2SI "V4SI") (V4SI "V4SI") 418 (DI "V2DI") (V2DI "V2DI") 419 (V2SF "V2SF") (V4SF "V4SF") 420 (V2DF "V2DF") (SI "V4SI") 421 (HI "V8HI") (QI "V16QI")]) 422 423;; Half modes of all vector modes. 424(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") 425 (V4HI "V2HI") (V8HI "V4HI") 426 (V2SI "SI") (V4SI "V2SI") 427 (V2DI "DI") (V2SF "SF") 428 (V4SF "V2SF") (V2DF "DF")]) 429 430;; Double modes of vector modes. 431(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") 432 (V2SI "V4SI") (V2SF "V4SF") 433 (SI "V2SI") (DI "V2DI") 434 (DF "V2DF")]) 435 436;; Double modes of vector modes (lower case). 437(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") 438 (V2SI "v4si") (V2SF "v4sf") 439 (SI "v2si") (DI "v2di") 440 (DF "v2df")]) 441 442;; Narrowed modes for VDN. 443(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") 444 (DI "V2SI")]) 445 446;; Narrowed double-modes for VQN (Used for XTN). 447(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") 448 (V2DI "V2SI") 449 (DI "SI") (SI "HI") 450 (HI "QI")]) 451 452;; Narrowed quad-modes for VQN (Used for XTN2). 453(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") 454 (V2DI "V4SI")]) 455 456;; Register suffix narrowed modes for VQN. 457(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") 458 (V2DI "2s")]) 459 460;; Register suffix narrowed modes for VQN. 461(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") 462 (V2DI "4s")]) 463 464;; Widened modes of vector modes. 465(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") 466 (V2SI "V2DI") (V16QI "V8HI") 467 (V8HI "V4SI") (V4SI "V2DI") 468 (HI "SI") (SI "DI")] 469 470) 471 472;; Widened mode register suffixes for VD_BHSI/VQW. 473(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") 474 (V2SI "2d") (V16QI "8h") 475 (V8HI "4s") (V4SI "2d")]) 476 477;; Widened mode register suffixes for VDW/VQW. 478(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") 479 (V2SI ".2d") (V16QI ".8h") 480 (V8HI ".4s") (V4SI ".2d") 481 (SI "") (HI "")]) 482 483;; Lower part register suffixes for VQW. 484(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") 485 (V4SI "2s")]) 486 487;; Define corresponding core/FP element mode for each vector mode. 488(define_mode_attr vw [(V8QI "w") (V16QI "w") 489 (V4HI "w") (V8HI "w") 490 (V2SI "w") (V4SI "w") 491 (DI "x") (V2DI "x") 492 (V2SF "s") (V4SF "s") 493 (V2DF "d")]) 494 495;; Corresponding core element mode for each vector mode. This is a 496;; variation on <vw> mapping FP modes to GP regs. 497(define_mode_attr vwcore [(V8QI "w") (V16QI "w") 498 (V4HI "w") (V8HI "w") 499 (V2SI "w") (V4SI "w") 500 (DI "x") (V2DI "x") 501 (V2SF "w") (V4SF "w") 502 (V2DF "x")]) 503 504;; Double vector types for ALLX. 505(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) 506 507;; Mode of result of comparison operations. 508(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") 509 (V4HI "V4HI") (V8HI "V8HI") 510 (V2SI "V2SI") (V4SI "V4SI") 511 (DI "DI") (V2DI "V2DI") 512 (V2SF "V2SI") (V4SF "V4SI") 513 (V2DF "V2DI") (DF "DI") 514 (SF "SI")]) 515 516;; Lower case mode of results of comparison operations. 517(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") 518 (V4HI "v4hi") (V8HI "v8hi") 519 (V2SI "v2si") (V4SI "v4si") 520 (DI "di") (V2DI "v2di") 521 (V2SF "v2si") (V4SF "v4si") 522 (V2DF "v2di") (DF "di") 523 (SF "si")]) 524 525;; Lower case element modes (as used in shift immediate patterns). 526(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") 527 (V4HI "hi") (V8HI "hi") 528 (V2SI "si") (V4SI "si") 529 (DI "di") (V2DI "di") 530 (QI "qi") (HI "hi") 531 (SI "si")]) 532 533;; Vm for lane instructions is restricted to FP_LO_REGS. 534(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") 535 (V2SI "w") (V4SI "w") (SI "w")]) 536 537(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")]) 538 539(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) 540 541(define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI") 542 (V2SI "V8SI") (V2SF "V8SF") 543 (DI "V4DI") (DF "V4DF") 544 (V16QI "V32QI") (V8HI "V16HI") 545 (V4SI "V8SI") (V4SF "V8SF") 546 (V2DI "V4DI") (V2DF "V4DF")]) 547 548(define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI") 549 (V2SI "V12SI") (V2SF "V12SF") 550 (DI "V6DI") (DF "V6DF") 551 (V16QI "V48QI") (V8HI "V24HI") 552 (V4SI "V12SI") (V4SF "V12SF") 553 (V2DI "V6DI") (V2DF "V6DF")]) 554 555(define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI") 556 (V2SI "V16SI") (V2SF "V16SF") 557 (DI "V8DI") (DF "V8DF") 558 (V16QI "V64QI") (V8HI "V32HI") 559 (V4SI "V16SI") (V4SF "V16SF") 560 (V2DI "V8DI") (V2DF "V8DF")]) 561 562(define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")]) 563 564;; Mode of pair of elements for each vector mode, to define transfer 565;; size for structure lane/dup loads and stores. 566(define_mode_attr V_TWO_ELEM [(V8QI "HI") (V16QI "HI") 567 (V4HI "SI") (V8HI "SI") 568 (V2SI "V2SI") (V4SI "V2SI") 569 (DI "V2DI") (V2DI "V2DI") 570 (V2SF "V2SF") (V4SF "V2SF") 571 (DF "V2DI") (V2DF "V2DI")]) 572 573;; Similar, for three elements. 574(define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK") 575 (V4HI "BLK") (V8HI "BLK") 576 (V2SI "BLK") (V4SI "BLK") 577 (DI "EI") (V2DI "EI") 578 (V2SF "BLK") (V4SF "BLK") 579 (DF "EI") (V2DF "EI")]) 580 581;; Similar, for four elements. 582(define_mode_attr V_FOUR_ELEM [(V8QI "SI") (V16QI "SI") 583 (V4HI "V4HI") (V8HI "V4HI") 584 (V2SI "V4SI") (V4SI "V4SI") 585 (DI "OI") (V2DI "OI") 586 (V2SF "V4SF") (V4SF "V4SF") 587 (DF "OI") (V2DF "OI")]) 588 589 590;; Mode for atomic operation suffixes 591(define_mode_attr atomic_sfx 592 [(QI "b") (HI "h") (SI "") (DI "")]) 593 594(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (SF "si") (DF "di")]) 595(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (SF "SI") (DF "DI")]) 596 597;; for the inequal width integer to fp conversions 598(define_mode_attr fcvt_iesize [(SF "di") (DF "si")]) 599(define_mode_attr FCVT_IESIZE [(SF "DI") (DF "SI")]) 600 601(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI") 602 (V4HI "V8HI") (V8HI "V4HI") 603 (V2SI "V4SI") (V4SI "V2SI") 604 (DI "V2DI") (V2DI "DI") 605 (V2SF "V4SF") (V4SF "V2SF") 606 (DF "V2DF") (V2DF "DF")]) 607 608(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64") 609 (V4HI "to_128") (V8HI "to_64") 610 (V2SI "to_128") (V4SI "to_64") 611 (DI "to_128") (V2DI "to_64") 612 (V2SF "to_128") (V4SF "to_64") 613 (DF "to_128") (V2DF "to_64")]) 614 615;; For certain vector-by-element multiplication instructions we must 616;; constrain the HI cases to use only V0-V15. This is covered by 617;; the 'x' constraint. All other modes may use the 'w' constraint. 618(define_mode_attr h_con [(V2SI "w") (V4SI "w") 619 (V4HI "x") (V8HI "x") 620 (V2SF "w") (V4SF "w") 621 (V2DF "w") (DF "w")]) 622 623;; Defined to 'f' for types whose element type is a float type. 624(define_mode_attr f [(V8QI "") (V16QI "") 625 (V4HI "") (V8HI "") 626 (V2SI "") (V4SI "") 627 (DI "") (V2DI "") 628 (V2SF "f") (V4SF "f") 629 (V2DF "f") (DF "f")]) 630 631;; Defined to '_fp' for types whose element type is a float type. 632(define_mode_attr fp [(V8QI "") (V16QI "") 633 (V4HI "") (V8HI "") 634 (V2SI "") (V4SI "") 635 (DI "") (V2DI "") 636 (V2SF "_fp") (V4SF "_fp") 637 (V2DF "_fp") (DF "_fp") 638 (SF "_fp")]) 639 640;; Defined to '_q' for 128-bit types. 641(define_mode_attr q [(V8QI "") (V16QI "_q") 642 (V4HI "") (V8HI "_q") 643 (V2SI "") (V4SI "_q") 644 (DI "") (V2DI "_q") 645 (V2SF "") (V4SF "_q") 646 (V2DF "_q") 647 (QI "") (HI "") (SI "") (DI "") (SF "") (DF "")]) 648 649(define_mode_attr vp [(V8QI "v") (V16QI "v") 650 (V4HI "v") (V8HI "v") 651 (V2SI "p") (V4SI "v") 652 (V2DI "p") (V2DF "p") 653 (V2SF "p") (V4SF "v")]) 654 655(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")]) 656(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")]) 657 658(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")]) 659 660;; ------------------------------------------------------------------- 661;; Code Iterators 662;; ------------------------------------------------------------------- 663 664;; This code iterator allows the various shifts supported on the core 665(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert]) 666 667;; This code iterator allows the shifts supported in arithmetic instructions 668(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) 669 670;; Code iterator for logical operations 671(define_code_iterator LOGICAL [and ior xor]) 672 673;; Code iterator for logical operations whose :nlogical works on SIMD registers. 674(define_code_iterator NLOGICAL [and ior]) 675 676;; Code iterator for sign/zero extension 677(define_code_iterator ANY_EXTEND [sign_extend zero_extend]) 678 679;; All division operations (signed/unsigned) 680(define_code_iterator ANY_DIV [div udiv]) 681 682;; Code iterator for sign/zero extraction 683(define_code_iterator ANY_EXTRACT [sign_extract zero_extract]) 684 685;; Code iterator for equality comparisons 686(define_code_iterator EQL [eq ne]) 687 688;; Code iterator for less-than and greater/equal-to 689(define_code_iterator LTGE [lt ge]) 690 691;; Iterator for __sync_<op> operations that where the operation can be 692;; represented directly RTL. This is all of the sync operations bar 693;; nand. 694(define_code_iterator atomic_op [plus minus ior xor and]) 695 696;; Iterator for integer conversions 697(define_code_iterator FIXUORS [fix unsigned_fix]) 698 699;; Iterator for float conversions 700(define_code_iterator FLOATUORS [float unsigned_float]) 701 702;; Code iterator for variants of vector max and min. 703(define_code_iterator MAXMIN [smax smin umax umin]) 704 705(define_code_iterator FMAXMIN [smax smin]) 706 707;; Code iterator for variants of vector max and min. 708(define_code_iterator ADDSUB [plus minus]) 709 710;; Code iterator for variants of vector saturating binary ops. 711(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus]) 712 713;; Code iterator for variants of vector saturating unary ops. 714(define_code_iterator UNQOPS [ss_neg ss_abs]) 715 716;; Code iterator for signed variants of vector saturating binary ops. 717(define_code_iterator SBINQOPS [ss_plus ss_minus]) 718 719;; Comparison operators for <F>CM. 720(define_code_iterator COMPARISONS [lt le eq ge gt]) 721 722;; Unsigned comparison operators. 723(define_code_iterator UCOMPARISONS [ltu leu geu gtu]) 724 725;; Unsigned comparison operators. 726(define_code_iterator FAC_COMPARISONS [lt le ge gt]) 727 728;; ------------------------------------------------------------------- 729;; Code Attributes 730;; ------------------------------------------------------------------- 731;; Map rtl objects to optab names 732(define_code_attr optab [(ashift "ashl") 733 (ashiftrt "ashr") 734 (lshiftrt "lshr") 735 (rotatert "rotr") 736 (sign_extend "extend") 737 (zero_extend "zero_extend") 738 (sign_extract "extv") 739 (zero_extract "extzv") 740 (fix "fix") 741 (unsigned_fix "fixuns") 742 (float "float") 743 (unsigned_float "floatuns") 744 (and "and") 745 (ior "ior") 746 (xor "xor") 747 (not "one_cmpl") 748 (neg "neg") 749 (plus "add") 750 (minus "sub") 751 (ss_plus "qadd") 752 (us_plus "qadd") 753 (ss_minus "qsub") 754 (us_minus "qsub") 755 (ss_neg "qneg") 756 (ss_abs "qabs") 757 (eq "eq") 758 (ne "ne") 759 (lt "lt") 760 (ge "ge") 761 (le "le") 762 (gt "gt") 763 (ltu "ltu") 764 (leu "leu") 765 (geu "geu") 766 (gtu "gtu")]) 767 768;; For comparison operators we use the FCM* and CM* instructions. 769;; As there are no CMLE or CMLT instructions which act on 3 vector 770;; operands, we must use CMGE or CMGT and swap the order of the 771;; source operands. 772 773(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") 774 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) 775(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") 776 (ltu "2") (leu "2") (geu "1") (gtu "1")]) 777(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") 778 (ltu "1") (leu "1") (geu "2") (gtu "2")]) 779 780(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") 781 (ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")]) 782 783(define_code_attr fix_trunc_optab [(fix "fix_trunc") 784 (unsigned_fix "fixuns_trunc")]) 785 786;; Optab prefix for sign/zero-extending operations 787(define_code_attr su_optab [(sign_extend "") (zero_extend "u") 788 (div "") (udiv "u") 789 (fix "") (unsigned_fix "u") 790 (float "s") (unsigned_float "u") 791 (ss_plus "s") (us_plus "u") 792 (ss_minus "s") (us_minus "u")]) 793 794;; Similar for the instruction mnemonics 795(define_code_attr shift [(ashift "lsl") (ashiftrt "asr") 796 (lshiftrt "lsr") (rotatert "ror")]) 797 798;; Map shift operators onto underlying bit-field instructions 799(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") 800 (lshiftrt "ubfx") (rotatert "extr")]) 801 802;; Logical operator instruction mnemonics 803(define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) 804 805;; Similar, but when not(op) 806(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) 807 808;; Sign- or zero-extending load 809(define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")]) 810 811;; Sign- or zero-extending data-op 812(define_code_attr su [(sign_extend "s") (zero_extend "u") 813 (sign_extract "s") (zero_extract "u") 814 (fix "s") (unsigned_fix "u") 815 (div "s") (udiv "u") 816 (smax "s") (umax "u") 817 (smin "s") (umin "u")]) 818 819;; Emit conditional branch instructions. 820(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")]) 821 822;; Emit cbz/cbnz depending on comparison type. 823(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) 824 825;; Emit tbz/tbnz depending on comparison type. 826(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) 827 828;; Max/min attributes. 829(define_code_attr maxmin [(smax "max") 830 (smin "min") 831 (umax "max") 832 (umin "min")]) 833 834;; MLA/MLS attributes. 835(define_code_attr as [(ss_plus "a") (ss_minus "s")]) 836 837;; Atomic operations 838(define_code_attr atomic_optab 839 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")]) 840 841(define_code_attr atomic_op_operand 842 [(ior "aarch64_logical_operand") 843 (xor "aarch64_logical_operand") 844 (and "aarch64_logical_operand") 845 (plus "aarch64_plus_operand") 846 (minus "aarch64_plus_operand")]) 847 848;; Constants acceptable for atomic operations. 849;; This definition must appear in this file before the iterators it refers to. 850(define_code_attr const_atomic 851 [(plus "IJ") (minus "IJ") 852 (xor "<lconst_atomic>") (ior "<lconst_atomic>") 853 (and "<lconst_atomic>")]) 854 855;; Attribute to describe constants acceptable in atomic logical operations 856(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")]) 857 858;; ------------------------------------------------------------------- 859;; Int Iterators. 860;; ------------------------------------------------------------------- 861(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV 862 UNSPEC_SMAXV UNSPEC_SMINV]) 863 864(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV 865 UNSPEC_FMAXNMV UNSPEC_FMINNMV]) 866 867(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD 868 UNSPEC_SRHADD UNSPEC_URHADD 869 UNSPEC_SHSUB UNSPEC_UHSUB 870 UNSPEC_SRHSUB UNSPEC_URHSUB]) 871 872 873(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN 874 UNSPEC_SUBHN UNSPEC_RSUBHN]) 875 876(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 877 UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) 878 879(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN]) 880 881(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) 882 883(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) 884 885(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN]) 886 887(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL 888 UNSPEC_SRSHL UNSPEC_URSHL]) 889 890(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL]) 891 892(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL 893 UNSPEC_SQRSHL UNSPEC_UQRSHL]) 894 895(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA 896 UNSPEC_SRSRA UNSPEC_URSRA]) 897 898(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI 899 UNSPEC_SSRI UNSPEC_USRI]) 900 901 902(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR]) 903 904(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) 905 906(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN 907 UNSPEC_SQSHRN UNSPEC_UQSHRN 908 UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) 909 910(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 911 UNSPEC_TRN1 UNSPEC_TRN2 912 UNSPEC_UZP1 UNSPEC_UZP2]) 913 914(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) 915 916(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM 917 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX 918 UNSPEC_FRINTA]) 919 920(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM 921 UNSPEC_FRINTA UNSPEC_FRINTN]) 922 923(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) 924 925(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W 926 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH 927 UNSPEC_CRC32CW UNSPEC_CRC32CX]) 928 929(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD]) 930(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) 931 932(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) 933 934(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) 935 936;; ------------------------------------------------------------------- 937;; Int Iterators Attributes. 938;; ------------------------------------------------------------------- 939(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") 940 (UNSPEC_UMINV "umin") 941 (UNSPEC_SMAXV "smax") 942 (UNSPEC_SMINV "smin") 943 (UNSPEC_FMAX "smax_nan") 944 (UNSPEC_FMAXNMV "smax") 945 (UNSPEC_FMAXV "smax_nan") 946 (UNSPEC_FMIN "smin_nan") 947 (UNSPEC_FMINNMV "smin") 948 (UNSPEC_FMINV "smin_nan")]) 949 950(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") 951 (UNSPEC_UMINV "umin") 952 (UNSPEC_SMAXV "smax") 953 (UNSPEC_SMINV "smin") 954 (UNSPEC_FMAX "fmax") 955 (UNSPEC_FMAXNMV "fmaxnm") 956 (UNSPEC_FMAXV "fmax") 957 (UNSPEC_FMIN "fmin") 958 (UNSPEC_FMINNMV "fminnm") 959 (UNSPEC_FMINV "fmin")]) 960 961(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") 962 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") 963 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") 964 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur") 965 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") 966 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") 967 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") 968 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") 969 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") 970 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") 971 (UNSPEC_SSLI "s") (UNSPEC_USLI "u") 972 (UNSPEC_SSRI "s") (UNSPEC_USRI "u") 973 (UNSPEC_USRA "u") (UNSPEC_SSRA "s") 974 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr") 975 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") 976 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") 977 (UNSPEC_UQSHL "u") 978 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") 979 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") 980 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") 981 (UNSPEC_USHL "u") (UNSPEC_SSHL "s") 982 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") 983 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") 984 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") 985]) 986 987(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") 988 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") 989 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") 990 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") 991 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") 992 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") 993]) 994 995(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") 996 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")]) 997 998(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") 999 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") 1000 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") 1001 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")]) 1002 1003(define_int_attr addsub [(UNSPEC_SHADD "add") 1004 (UNSPEC_UHADD "add") 1005 (UNSPEC_SRHADD "add") 1006 (UNSPEC_URHADD "add") 1007 (UNSPEC_SHSUB "sub") 1008 (UNSPEC_UHSUB "sub") 1009 (UNSPEC_SRHSUB "sub") 1010 (UNSPEC_URHSUB "sub") 1011 (UNSPEC_ADDHN "add") 1012 (UNSPEC_SUBHN "sub") 1013 (UNSPEC_RADDHN "add") 1014 (UNSPEC_RSUBHN "sub") 1015 (UNSPEC_ADDHN2 "add") 1016 (UNSPEC_SUBHN2 "sub") 1017 (UNSPEC_RADDHN2 "add") 1018 (UNSPEC_RSUBHN2 "sub")]) 1019 1020(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "") 1021 (UNSPEC_SSRI "offset_") 1022 (UNSPEC_USRI "offset_")]) 1023 1024;; Standard pattern names for floating-point rounding instructions. 1025(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") 1026 (UNSPEC_FRINTP "ceil") 1027 (UNSPEC_FRINTM "floor") 1028 (UNSPEC_FRINTI "nearbyint") 1029 (UNSPEC_FRINTX "rint") 1030 (UNSPEC_FRINTA "round") 1031 (UNSPEC_FRINTN "frintn")]) 1032 1033;; frint suffix for floating-point rounding instructions. 1034(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") 1035 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") 1036 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") 1037 (UNSPEC_FRINTN "n")]) 1038 1039(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") 1040 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") 1041 (UNSPEC_FRINTN "frintn")]) 1042 1043(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") 1044 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") 1045 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")]) 1046 1047; op code for REV instructions (size within which elements are reversed). 1048(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") 1049 (UNSPEC_REV16 "16")]) 1050 1051(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") 1052 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") 1053 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) 1054 1055(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) 1056 1057(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") 1058 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") 1059 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") 1060 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")]) 1061 1062(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") 1063 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI") 1064 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI") 1065 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")]) 1066 1067(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")]) 1068(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")]) 1069 1070(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p") 1071 (UNSPEC_SHA1M "m")]) 1072 1073(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) 1074