1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2013 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_H 23 #define GCC_AARCH64_H 24 25 /* Target CPU builtins. */ 26 #define TARGET_CPU_CPP_BUILTINS() \ 27 do \ 28 { \ 29 builtin_define ("__aarch64__"); \ 30 if (TARGET_BIG_END) \ 31 builtin_define ("__AARCH64EB__"); \ 32 else \ 33 builtin_define ("__AARCH64EL__"); \ 34 \ 35 switch (aarch64_cmodel) \ 36 { \ 37 case AARCH64_CMODEL_TINY: \ 38 case AARCH64_CMODEL_TINY_PIC: \ 39 builtin_define ("__AARCH64_CMODEL_TINY__"); \ 40 break; \ 41 case AARCH64_CMODEL_SMALL: \ 42 case AARCH64_CMODEL_SMALL_PIC: \ 43 builtin_define ("__AARCH64_CMODEL_SMALL__");\ 44 break; \ 45 case AARCH64_CMODEL_LARGE: \ 46 builtin_define ("__AARCH64_CMODEL_LARGE__"); \ 47 break; \ 48 default: \ 49 break; \ 50 } \ 51 \ 52 } while (0) 53 54 55 56 /* Target machine storage layout. */ 57 58 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 59 if (GET_MODE_CLASS (MODE) == MODE_INT \ 60 && GET_MODE_SIZE (MODE) < 4) \ 61 { \ 62 if (MODE == QImode || MODE == HImode) \ 63 { \ 64 MODE = SImode; \ 65 } \ 66 } 67 68 /* Bits are always numbered from the LSBit. */ 69 #define BITS_BIG_ENDIAN 0 70 71 /* Big/little-endian flavour. */ 72 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 73 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 74 75 /* AdvSIMD is supported in the default configuration, unless disabled by 76 -mgeneral-regs-only or the +nosimd extension. */ 77 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) 78 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) 79 80 #define UNITS_PER_WORD 8 81 82 #define UNITS_PER_VREG 16 83 84 #define PARM_BOUNDARY 64 85 86 #define STACK_BOUNDARY 128 87 88 #define FUNCTION_BOUNDARY 32 89 90 #define EMPTY_FIELD_BOUNDARY 32 91 92 #define BIGGEST_ALIGNMENT 128 93 94 #define SHORT_TYPE_SIZE 16 95 96 #define INT_TYPE_SIZE 32 97 98 #define LONG_TYPE_SIZE 64 /* XXX This should be an option */ 99 100 #define LONG_LONG_TYPE_SIZE 64 101 102 #define FLOAT_TYPE_SIZE 32 103 104 #define DOUBLE_TYPE_SIZE 64 105 106 #define LONG_DOUBLE_TYPE_SIZE 128 107 108 /* The architecture reserves all bits of the address for hardware use, 109 so the vbit must go into the delta field of pointers to member 110 functions. This is the same config as that in the AArch32 111 port. */ 112 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 113 114 /* Make strings word-aligned so that strcpy from constants will be 115 faster. */ 116 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 117 ((TREE_CODE (EXP) == STRING_CST \ 118 && !optimize_size \ 119 && (ALIGN) < BITS_PER_WORD) \ 120 ? BITS_PER_WORD : ALIGN) 121 122 #define DATA_ALIGNMENT(EXP, ALIGN) \ 123 ((((ALIGN) < BITS_PER_WORD) \ 124 && (TREE_CODE (EXP) == ARRAY_TYPE \ 125 || TREE_CODE (EXP) == UNION_TYPE \ 126 || TREE_CODE (EXP) == RECORD_TYPE)) \ 127 ? BITS_PER_WORD : (ALIGN)) 128 129 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) 130 131 #define STRUCTURE_SIZE_BOUNDARY 8 132 133 /* Defined by the ABI */ 134 #define WCHAR_TYPE "unsigned int" 135 #define WCHAR_TYPE_SIZE 32 136 137 /* Using long long breaks -ansi and -std=c90, so these will need to be 138 made conditional for an LLP64 ABI. */ 139 140 #define SIZE_TYPE "long unsigned int" 141 142 #define PTRDIFF_TYPE "long int" 143 144 #define PCC_BITFIELD_TYPE_MATTERS 1 145 146 147 /* Instruction tuning/selection flags. */ 148 149 /* Bit values used to identify processor capabilities. */ 150 #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ 151 #define AARCH64_FL_FP (1 << 1) /* Has FP. */ 152 #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ 153 #define AARCH64_FL_SLOWMUL (1 << 3) /* A slow multiply core. */ 154 155 /* Has FP and SIMD. */ 156 #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) 157 158 /* Has FP without SIMD. */ 159 #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) 160 161 /* Architecture flags that effect instruction selection. */ 162 #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) 163 164 /* Macros to test ISA flags. */ 165 extern unsigned long aarch64_isa_flags; 166 #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) 167 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) 168 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) 169 170 /* Macros to test tuning flags. */ 171 extern unsigned long aarch64_tune_flags; 172 #define AARCH64_TUNE_SLOWMUL (aarch64_tune_flags & AARCH64_FL_SLOWMUL) 173 174 175 /* Standard register usage. */ 176 177 /* 31 64-bit general purpose registers R0-R30: 178 R30 LR (link register) 179 R29 FP (frame pointer) 180 R19-R28 Callee-saved registers 181 R18 The platform register; use as temporary register. 182 R17 IP1 The second intra-procedure-call temporary register 183 (can be used by call veneers and PLT code); otherwise use 184 as a temporary register 185 R16 IP0 The first intra-procedure-call temporary register (can 186 be used by call veneers and PLT code); otherwise use as a 187 temporary register 188 R9-R15 Temporary registers 189 R8 Structure value parameter / temporary register 190 R0-R7 Parameter/result registers 191 192 SP stack pointer, encoded as X/R31 where permitted. 193 ZR zero register, encoded as X/R31 elsewhere 194 195 32 x 128-bit floating-point/vector registers 196 V16-V31 Caller-saved (temporary) registers 197 V8-V15 Callee-saved registers 198 V0-V7 Parameter/result registers 199 200 The vector register V0 holds scalar B0, H0, S0 and D0 in its least 201 significant bits. Unlike AArch32 S1 is not packed into D0, 202 etc. */ 203 204 /* Note that we don't mark X30 as a call-clobbered register. The idea is 205 that it's really the call instructions themselves which clobber X30. 206 We don't care what the called function does with it afterwards. 207 208 This approach makes it easier to implement sibcalls. Unlike normal 209 calls, sibcalls don't clobber X30, so the register reaches the 210 called function intact. EPILOGUE_USES says that X30 is useful 211 to the called function. */ 212 213 #define FIXED_REGISTERS \ 214 { \ 215 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ 216 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ 217 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 218 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 219 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ 220 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 221 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ 222 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ 223 1, 1, 1, /* SFP, AP, CC */ \ 224 } 225 226 #define CALL_USED_REGISTERS \ 227 { \ 228 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ 229 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ 230 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 231 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 232 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ 233 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 234 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ 235 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ 236 1, 1, 1, /* SFP, AP, CC */ \ 237 } 238 239 #define REGISTER_NAMES \ 240 { \ 241 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ 242 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ 243 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 244 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ 245 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 246 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 247 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 248 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 249 "sfp", "ap", "cc", \ 250 } 251 252 /* Generate the register aliases for core register N */ 253 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ 254 {"w" # N, R0_REGNUM + (N)} 255 256 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ 257 {"d" # N, V0_REGNUM + (N)}, \ 258 {"s" # N, V0_REGNUM + (N)}, \ 259 {"h" # N, V0_REGNUM + (N)}, \ 260 {"b" # N, V0_REGNUM + (N)} 261 262 /* Provide aliases for all of the ISA defined register name forms. 263 These aliases are convenient for use in the clobber lists of inline 264 asm statements. */ 265 266 #define ADDITIONAL_REGISTER_NAMES \ 267 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ 268 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ 269 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ 270 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ 271 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ 272 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ 273 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ 274 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), /* 31 omitted */ \ 275 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ 276 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ 277 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ 278 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ 279 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ 280 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ 281 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ 282 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ 283 } 284 285 /* Say that the epilogue uses the return address register. Note that 286 in the case of sibcalls, the values "used by the epilogue" are 287 considered live at the start of the called function. */ 288 289 #define EPILOGUE_USES(REGNO) \ 290 ((REGNO) == LR_REGNUM) 291 292 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 293 the stack pointer does not matter. The value is tested only in 294 functions that have frame pointers. */ 295 #define EXIT_IGNORE_STACK 1 296 297 #define STATIC_CHAIN_REGNUM R18_REGNUM 298 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM 299 #define FRAME_POINTER_REGNUM SFP_REGNUM 300 #define STACK_POINTER_REGNUM SP_REGNUM 301 #define ARG_POINTER_REGNUM AP_REGNUM 302 #define FIRST_PSEUDO_REGISTER 67 303 304 /* The number of (integer) argument register available. */ 305 #define NUM_ARG_REGS 8 306 #define NUM_FP_ARG_REGS 8 307 308 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most 309 four members. */ 310 #define HA_MAX_NUM_FLDS 4 311 312 /* External dwarf register number scheme. These number are used to 313 identify registers in dwarf debug information, the values are 314 defined by the AArch64 ABI. The numbering scheme is independent of 315 GCC's internal register numbering scheme. */ 316 317 #define AARCH64_DWARF_R0 0 318 319 /* The number of R registers, note 31! not 32. */ 320 #define AARCH64_DWARF_NUMBER_R 31 321 322 #define AARCH64_DWARF_SP 31 323 #define AARCH64_DWARF_V0 64 324 325 /* The number of V registers. */ 326 #define AARCH64_DWARF_NUMBER_V 32 327 328 /* For signal frames we need to use an alternative return column. This 329 value must not correspond to a hard register and must be out of the 330 range of DWARF_FRAME_REGNUM(). */ 331 #define DWARF_ALT_FRAME_RETURN_COLUMN \ 332 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) 333 334 /* We add 1 extra frame register for use as the 335 DWARF_ALT_FRAME_RETURN_COLUMN. */ 336 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) 337 338 339 #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) 340 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 341 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 342 as the default definition in dwarf2out.c. */ 343 #undef DWARF_FRAME_REGNUM 344 #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) 345 346 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 347 348 #define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE) 349 350 #define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE) 351 352 #define MODES_TIEABLE_P(MODE1, MODE2) \ 353 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 354 355 #define DWARF2_UNWIND_INFO 1 356 357 /* Use R0 through R3 to pass exception handling information. */ 358 #define EH_RETURN_DATA_REGNO(N) \ 359 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) 360 361 /* Select a format to encode pointers in exception handling data. */ 362 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 363 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) 364 365 /* The register that holds the return address in exception handlers. */ 366 #define AARCH64_EH_STACKADJ_REGNUM (R0_REGNUM + 4) 367 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM) 368 369 /* Don't use __builtin_setjmp until we've defined it. */ 370 #undef DONT_USE_BUILTIN_SETJMP 371 #define DONT_USE_BUILTIN_SETJMP 1 372 373 /* Register in which the structure value is to be returned. */ 374 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM 375 376 /* Non-zero if REGNO is part of the Core register set. 377 378 The rather unusual way of expressing this check is to avoid 379 warnings when building the compiler when R0_REGNUM is 0 and REGNO 380 is unsigned. */ 381 #define GP_REGNUM_P(REGNO) \ 382 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) 383 384 #define FP_REGNUM_P(REGNO) \ 385 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) 386 387 #define FP_LO_REGNUM_P(REGNO) \ 388 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) 389 390 391 /* Register and constant classes. */ 392 393 enum reg_class 394 { 395 NO_REGS, 396 CORE_REGS, 397 GENERAL_REGS, 398 STACK_REG, 399 POINTER_REGS, 400 FP_LO_REGS, 401 FP_REGS, 402 ALL_REGS, 403 LIM_REG_CLASSES /* Last */ 404 }; 405 406 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 407 408 #define REG_CLASS_NAMES \ 409 { \ 410 "NO_REGS", \ 411 "CORE_REGS", \ 412 "GENERAL_REGS", \ 413 "STACK_REG", \ 414 "POINTER_REGS", \ 415 "FP_LO_REGS", \ 416 "FP_REGS", \ 417 "ALL_REGS" \ 418 } 419 420 #define REG_CLASS_CONTENTS \ 421 { \ 422 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 423 { 0x7fffffff, 0x00000000, 0x00000003 }, /* CORE_REGS */ \ 424 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ 425 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 426 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ 427 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ 428 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 429 { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ 430 } 431 432 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) 433 434 #define INDEX_REG_CLASS CORE_REGS 435 #define BASE_REG_CLASS POINTER_REGS 436 437 /* Register pairs used to eliminate unneeded registers that point intoi 438 the stack frame. */ 439 #define ELIMINABLE_REGS \ 440 { \ 441 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 442 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 443 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 444 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 445 } 446 447 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 448 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) 449 450 /* CPU/ARCH option handling. */ 451 #include "config/aarch64/aarch64-opts.h" 452 453 enum target_cpus 454 { 455 #define AARCH64_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 456 TARGET_CPU_##IDENT, 457 #include "aarch64-cores.def" 458 #undef AARCH64_CORE 459 TARGET_CPU_generic 460 }; 461 462 /* If there is no CPU defined at configure, use "generic" as default. */ 463 #ifndef TARGET_CPU_DEFAULT 464 #define TARGET_CPU_DEFAULT \ 465 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) 466 #endif 467 468 /* If inserting NOP before a mult-accumulate insn remember to adjust the 469 length so that conditional branching code is updated appropriately. */ 470 #define ADJUST_INSN_LENGTH(insn, length) \ 471 do \ 472 { \ 473 if (aarch64_madd_needs_nop (insn)) \ 474 length += 4; \ 475 } while (0) 476 477 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 478 aarch64_final_prescan_insn (INSN); \ 479 480 /* The processor for which instructions should be scheduled. */ 481 extern enum aarch64_processor aarch64_tune; 482 483 /* RTL generation support. */ 484 #define INIT_EXPANDERS aarch64_init_expanders () 485 486 487 /* Stack layout; function entry, exit and calling. */ 488 #define STACK_GROWS_DOWNWARD 1 489 490 #define FRAME_GROWS_DOWNWARD 0 491 492 #define STARTING_FRAME_OFFSET 0 493 494 #define ACCUMULATE_OUTGOING_ARGS 1 495 496 #define FIRST_PARM_OFFSET(FNDECL) 0 497 498 /* Fix for VFP */ 499 #define LIBCALL_VALUE(MODE) \ 500 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) 501 502 #define DEFAULT_PCC_STRUCT_RETURN 0 503 504 #define AARCH64_ROUND_UP(X, ALIGNMENT) \ 505 (((X) + ((ALIGNMENT) - 1)) & ~((ALIGNMENT) - 1)) 506 507 #define AARCH64_ROUND_DOWN(X, ALIGNMENT) \ 508 ((X) & ~((ALIGNMENT) - 1)) 509 510 #ifdef HOST_WIDE_INT 511 struct GTY (()) aarch64_frame 512 { 513 HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; 514 HOST_WIDE_INT saved_regs_size; 515 /* Padding if needed after the all the callee save registers have 516 been saved. */ 517 HOST_WIDE_INT padding0; 518 HOST_WIDE_INT hardfp_offset; /* HARD_FRAME_POINTER_REGNUM */ 519 HOST_WIDE_INT fp_lr_offset; /* Space needed for saving fp and/or lr */ 520 521 bool laid_out; 522 }; 523 524 typedef struct GTY (()) machine_function 525 { 526 struct aarch64_frame frame; 527 528 /* The number of extra stack bytes taken up by register varargs. 529 This area is allocated by the callee at the very top of the frame. */ 530 HOST_WIDE_INT saved_varargs_size; 531 532 } machine_function; 533 #endif 534 535 536 /* Which ABI to use. */ 537 enum arm_abi_type 538 { 539 ARM_ABI_AAPCS64 540 }; 541 542 enum arm_pcs 543 { 544 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ 545 ARM_PCS_UNKNOWN 546 }; 547 548 549 extern enum arm_abi_type arm_abi; 550 extern enum arm_pcs arm_pcs_variant; 551 #ifndef ARM_DEFAULT_ABI 552 #define ARM_DEFAULT_ABI ARM_ABI_AAPCS64 553 #endif 554 555 #ifndef ARM_DEFAULT_PCS 556 #define ARM_DEFAULT_PCS ARM_PCS_AAPCS64 557 #endif 558 559 /* We can't use enum machine_mode inside a generator file because it 560 hasn't been created yet; we shouldn't be using any code that 561 needs the real definition though, so this ought to be safe. */ 562 #ifdef GENERATOR_FILE 563 #define MACHMODE int 564 #else 565 #include "insn-modes.h" 566 #define MACHMODE enum machine_mode 567 #endif 568 569 570 /* AAPCS related state tracking. */ 571 typedef struct 572 { 573 enum arm_pcs pcs_variant; 574 int aapcs_arg_processed; /* No need to lay out this argument again. */ 575 int aapcs_ncrn; /* Next Core register number. */ 576 int aapcs_nextncrn; /* Next next core register number. */ 577 int aapcs_nvrn; /* Next Vector register number. */ 578 int aapcs_nextnvrn; /* Next Next Vector register number. */ 579 rtx aapcs_reg; /* Register assigned to this argument. This 580 is NULL_RTX if this parameter goes on 581 the stack. */ 582 MACHMODE aapcs_vfp_rmode; 583 int aapcs_stack_words; /* If the argument is passed on the stack, this 584 is the number of words needed, after rounding 585 up. Only meaningful when 586 aapcs_reg == NULL_RTX. */ 587 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the 588 stack arg area so far. */ 589 } CUMULATIVE_ARGS; 590 591 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 592 (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward) 593 594 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 595 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 596 597 #define PAD_VARARGS_DOWN 0 598 599 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 600 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 601 602 #define FUNCTION_ARG_REGNO_P(REGNO) \ 603 aarch64_function_arg_regno_p(REGNO) 604 605 606 /* ISA Features. */ 607 608 /* Addressing modes, etc. */ 609 #define HAVE_POST_INCREMENT 1 610 #define HAVE_PRE_INCREMENT 1 611 #define HAVE_POST_DECREMENT 1 612 #define HAVE_PRE_DECREMENT 1 613 #define HAVE_POST_MODIFY_DISP 1 614 #define HAVE_PRE_MODIFY_DISP 1 615 616 #define MAX_REGS_PER_ADDRESS 2 617 618 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) 619 620 /* Try a machine-dependent way of reloading an illegitimate address 621 operand. If we find one, push the reload and jump to WIN. This 622 macro is used in only one place: `find_reloads_address' in reload.c. */ 623 624 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 625 do { \ 626 rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \ 627 IND_L); \ 628 if (new_x) \ 629 { \ 630 X = new_x; \ 631 goto WIN; \ 632 } \ 633 } while (0) 634 635 #define REGNO_OK_FOR_BASE_P(REGNO) \ 636 aarch64_regno_ok_for_base_p (REGNO, true) 637 638 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 639 aarch64_regno_ok_for_index_p (REGNO, true) 640 641 #define LEGITIMATE_PIC_OPERAND_P(X) \ 642 aarch64_legitimate_pic_operand_p (X) 643 644 #define CASE_VECTOR_MODE Pmode 645 646 #define DEFAULT_SIGNED_CHAR 0 647 648 /* An integer expression for the size in bits of the largest integer machine 649 mode that should actually be used. We allow pairs of registers. */ 650 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 651 652 /* Maximum bytes moved by a single instruction (load/store pair). */ 653 #define MOVE_MAX (UNITS_PER_WORD * 2) 654 655 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ 656 #define AARCH64_CALL_RATIO 8 657 658 /* When optimizing for size, give a better estimate of the length of a memcpy 659 call, but use the default otherwise. But move_by_pieces_ninsns() counts 660 memory-to-memory moves, and we'll have to generate a load & store for each, 661 so halve the value to take that into account. */ 662 #define MOVE_RATIO(speed) \ 663 (((speed) ? 15 : AARCH64_CALL_RATIO) / 2) 664 665 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 666 of the length of a memset call, but use the default otherwise. */ 667 #define CLEAR_RATIO(speed) \ 668 ((speed) ? 15 : AARCH64_CALL_RATIO) 669 670 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when 671 optimizing for size adjust the ratio to account for the overhead of loading 672 the constant. */ 673 #define SET_RATIO(speed) \ 674 ((speed) ? 15 : AARCH64_CALL_RATIO - 2) 675 676 /* STORE_BY_PIECES_P can be used when copying a constant string, but 677 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR). 678 For now we always fail this and let the move_by_pieces code copy 679 the string from read-only memory. */ 680 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0 681 682 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is 683 rarely a good idea in straight-line code since it adds an extra address 684 dependency between each instruction. Better to use incrementing offsets. */ 685 #define USE_LOAD_POST_INCREMENT(MODE) 0 686 #define USE_LOAD_POST_DECREMENT(MODE) 0 687 #define USE_LOAD_PRE_INCREMENT(MODE) 0 688 #define USE_LOAD_PRE_DECREMENT(MODE) 0 689 #define USE_STORE_POST_INCREMENT(MODE) 0 690 #define USE_STORE_POST_DECREMENT(MODE) 0 691 #define USE_STORE_PRE_INCREMENT(MODE) 0 692 #define USE_STORE_PRE_DECREMENT(MODE) 0 693 694 /* ?? #define WORD_REGISTER_OPERATIONS */ 695 696 /* Define if loading from memory in MODE, an integral mode narrower than 697 BITS_PER_WORD will either zero-extend or sign-extend. The value of this 698 macro should be the code that says which one of the two operations is 699 implicitly done, or UNKNOWN if none. */ 700 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 701 702 /* Define this macro to be non-zero if instructions will fail to work 703 if given data not on the nominal alignment. */ 704 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 705 706 /* Define this macro to be non-zero if accessing less than a word of 707 memory is no faster than accessing a word of memory, i.e., if such 708 accesses require more than one instruction or if there is no 709 difference in cost. 710 Although there's no difference in instruction count or cycles, 711 in AArch64 we don't want to expand to a sub-word to a 64-bit access 712 if we don't have to, for power-saving reasons. */ 713 #define SLOW_BYTE_ACCESS 0 714 715 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 716 717 #define NO_FUNCTION_CSE 1 718 719 #define Pmode DImode 720 #define FUNCTION_MODE Pmode 721 722 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) 723 724 #define REVERSE_CONDITION(CODE, MODE) \ 725 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 726 ? reverse_condition_maybe_unordered (CODE) \ 727 : reverse_condition (CODE)) 728 729 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 730 ((VALUE) = ((MODE) == SImode ? 32 : 64), 2) 731 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 732 ((VALUE) = ((MODE) == SImode ? 32 : 64), 2) 733 734 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 735 736 #define RETURN_ADDR_RTX aarch64_return_addr 737 738 #define TRAMPOLINE_SIZE aarch64_trampoline_size () 739 740 /* Trampolines contain dwords, so must be dword aligned. */ 741 #define TRAMPOLINE_ALIGNMENT 64 742 743 /* Put trampolines in the text section so that mapping symbols work 744 correctly. */ 745 #define TRAMPOLINE_SECTION text_section 746 747 /* Costs, etc. */ 748 #define MEMORY_MOVE_COST(M, CLASS, IN) \ 749 (GET_MODE_SIZE (M) < 8 ? 8 : GET_MODE_SIZE (M)) 750 751 /* To start with. */ 752 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2 753 754 755 /* Assembly output. */ 756 757 /* For now we'll make all jump tables pc-relative. */ 758 #define CASE_VECTOR_PC_RELATIVE 1 759 760 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 761 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ 762 : (min < -0x1f0 || max > 0x1f0) ? HImode \ 763 : QImode) 764 765 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 766 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 767 768 #define PRINT_OPERAND(STREAM, X, CODE) aarch64_print_operand (STREAM, X, CODE) 769 770 #define PRINT_OPERAND_ADDRESS(STREAM, X) \ 771 aarch64_print_operand_address (STREAM, X) 772 773 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 774 aarch64_function_profiler (STREAM, LABELNO) 775 776 /* For some reason, the Linux headers think they know how to define 777 these macros. They don't!!! */ 778 #undef ASM_APP_ON 779 #undef ASM_APP_OFF 780 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" 781 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" 782 783 #define CONSTANT_POOL_BEFORE_FUNCTION 0 784 785 /* This definition should be relocated to aarch64-elf-raw.h. This macro 786 should be undefined in aarch64-linux.h and a clear_cache pattern 787 implmented to emit either the call to __aarch64_sync_cache_range() 788 directly or preferably the appropriate sycall or cache clear 789 instructions inline. */ 790 #define CLEAR_INSN_CACHE(beg, end) \ 791 extern void __aarch64_sync_cache_range (void *, void *); \ 792 __aarch64_sync_cache_range (beg, end) 793 794 /* VFP registers may only be accessed in the mode they 795 were set. */ 796 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 797 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 798 ? reg_classes_intersect_p (FP_REGS, (CLASS)) \ 799 : 0) 800 801 802 #define SHIFT_COUNT_TRUNCATED !TARGET_SIMD 803 804 /* Callee only saves lower 64-bits of a 128-bit register. Tell the 805 compiler the callee clobbers the top 64-bits when restoring the 806 bottom 64-bits. */ 807 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 808 (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8) 809 810 /* Check TLS Descriptors mechanism is selected. */ 811 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) 812 813 extern enum aarch64_code_model aarch64_cmodel; 814 815 /* When using the tiny addressing model conditional and unconditional branches 816 can span the whole of the available address space (1MB). */ 817 #define HAS_LONG_COND_BRANCH \ 818 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 819 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 820 821 #define HAS_LONG_UNCOND_BRANCH \ 822 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 823 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 824 825 /* Modes valid for AdvSIMD Q registers. */ 826 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ 827 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 828 || (MODE) == V4SFmode || (MODE) == V2DImode || mode == V2DFmode) 829 830 #endif /* GCC_AARCH64_H */ 831