1/* Machine description for AArch64 architecture. 2 Copyright (C) 2012-2013 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21/* In the list below, the BUILTIN_<ITERATOR> macros should 22 correspond to the iterator used to construct the instruction's 23 patterns in aarch64-simd.md. A helpful idiom to follow when 24 adding new builtins is to add a line for each pattern in the md 25 file. Thus, ADDP, which has one pattern defined for the VD_BHSI 26 iterator, and one for DImode, has two entries below. */ 27 28 BUILTIN_VD_RE (CREATE, create) 29 BUILTIN_VQ_S (GETLANE, get_lane_signed) 30 BUILTIN_VDQ (GETLANE, get_lane_unsigned) 31 BUILTIN_VDQF (GETLANE, get_lane) 32 VAR1 (GETLANE, get_lane, di) 33 BUILTIN_VDC (COMBINE, combine) 34 BUILTIN_VB (BINOP, pmul) 35 BUILTIN_VDQF (UNOP, sqrt) 36 BUILTIN_VD_BHSI (BINOP, addp) 37 VAR1 (UNOP, addp, di) 38 39 BUILTIN_VD_RE (REINTERP, reinterpretdi) 40 BUILTIN_VDC (REINTERP, reinterpretv8qi) 41 BUILTIN_VDC (REINTERP, reinterpretv4hi) 42 BUILTIN_VDC (REINTERP, reinterpretv2si) 43 BUILTIN_VDC (REINTERP, reinterpretv2sf) 44 BUILTIN_VQ (REINTERP, reinterpretv16qi) 45 BUILTIN_VQ (REINTERP, reinterpretv8hi) 46 BUILTIN_VQ (REINTERP, reinterpretv4si) 47 BUILTIN_VQ (REINTERP, reinterpretv4sf) 48 BUILTIN_VQ (REINTERP, reinterpretv2di) 49 BUILTIN_VQ (REINTERP, reinterpretv2df) 50 51 BUILTIN_VDQ_I (BINOP, dup_lane) 52 BUILTIN_SDQ_I (BINOP, dup_lane) 53 /* Implemented by aarch64_<sur>q<r>shl<mode>. */ 54 BUILTIN_VSDQ_I (BINOP, sqshl) 55 BUILTIN_VSDQ_I (BINOP, uqshl) 56 BUILTIN_VSDQ_I (BINOP, sqrshl) 57 BUILTIN_VSDQ_I (BINOP, uqrshl) 58 /* Implemented by aarch64_<su_optab><optab><mode>. */ 59 BUILTIN_VSDQ_I (BINOP, sqadd) 60 BUILTIN_VSDQ_I (BINOP, uqadd) 61 BUILTIN_VSDQ_I (BINOP, sqsub) 62 BUILTIN_VSDQ_I (BINOP, uqsub) 63 /* Implemented by aarch64_<sur>qadd<mode>. */ 64 BUILTIN_VSDQ_I (BINOP, suqadd) 65 BUILTIN_VSDQ_I (BINOP, usqadd) 66 67 /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */ 68 BUILTIN_VDC (GETLANE, get_dregoi) 69 BUILTIN_VDC (GETLANE, get_dregci) 70 BUILTIN_VDC (GETLANE, get_dregxi) 71 /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */ 72 BUILTIN_VQ (GETLANE, get_qregoi) 73 BUILTIN_VQ (GETLANE, get_qregci) 74 BUILTIN_VQ (GETLANE, get_qregxi) 75 /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */ 76 BUILTIN_VQ (SETLANE, set_qregoi) 77 BUILTIN_VQ (SETLANE, set_qregci) 78 BUILTIN_VQ (SETLANE, set_qregxi) 79 /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */ 80 BUILTIN_VDC (LOADSTRUCT, ld2) 81 BUILTIN_VDC (LOADSTRUCT, ld3) 82 BUILTIN_VDC (LOADSTRUCT, ld4) 83 /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */ 84 BUILTIN_VQ (LOADSTRUCT, ld2) 85 BUILTIN_VQ (LOADSTRUCT, ld3) 86 BUILTIN_VQ (LOADSTRUCT, ld4) 87 /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */ 88 BUILTIN_VDC (STORESTRUCT, st2) 89 BUILTIN_VDC (STORESTRUCT, st3) 90 BUILTIN_VDC (STORESTRUCT, st4) 91 /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */ 92 BUILTIN_VQ (STORESTRUCT, st2) 93 BUILTIN_VQ (STORESTRUCT, st3) 94 BUILTIN_VQ (STORESTRUCT, st4) 95 96 BUILTIN_VQW (BINOP, saddl2) 97 BUILTIN_VQW (BINOP, uaddl2) 98 BUILTIN_VQW (BINOP, ssubl2) 99 BUILTIN_VQW (BINOP, usubl2) 100 BUILTIN_VQW (BINOP, saddw2) 101 BUILTIN_VQW (BINOP, uaddw2) 102 BUILTIN_VQW (BINOP, ssubw2) 103 BUILTIN_VQW (BINOP, usubw2) 104 /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */ 105 BUILTIN_VDW (BINOP, saddl) 106 BUILTIN_VDW (BINOP, uaddl) 107 BUILTIN_VDW (BINOP, ssubl) 108 BUILTIN_VDW (BINOP, usubl) 109 /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */ 110 BUILTIN_VDW (BINOP, saddw) 111 BUILTIN_VDW (BINOP, uaddw) 112 BUILTIN_VDW (BINOP, ssubw) 113 BUILTIN_VDW (BINOP, usubw) 114 /* Implemented by aarch64_<sur>h<addsub><mode>. */ 115 BUILTIN_VQ_S (BINOP, shadd) 116 BUILTIN_VQ_S (BINOP, uhadd) 117 BUILTIN_VQ_S (BINOP, srhadd) 118 BUILTIN_VQ_S (BINOP, urhadd) 119 /* Implemented by aarch64_<sur><addsub>hn<mode>. */ 120 BUILTIN_VQN (BINOP, addhn) 121 BUILTIN_VQN (BINOP, raddhn) 122 /* Implemented by aarch64_<sur><addsub>hn2<mode>. */ 123 BUILTIN_VQN (TERNOP, addhn2) 124 BUILTIN_VQN (TERNOP, raddhn2) 125 126 BUILTIN_VSQN_HSDI (UNOP, sqmovun) 127 /* Implemented by aarch64_<sur>qmovn<mode>. */ 128 BUILTIN_VSQN_HSDI (UNOP, sqmovn) 129 BUILTIN_VSQN_HSDI (UNOP, uqmovn) 130 /* Implemented by aarch64_s<optab><mode>. */ 131 BUILTIN_VSDQ_I_BHSI (UNOP, sqabs) 132 BUILTIN_VSDQ_I_BHSI (UNOP, sqneg) 133 134 BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane) 135 BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane) 136 BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq) 137 BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq) 138 BUILTIN_VQ_HSI (TERNOP, sqdmlal2) 139 BUILTIN_VQ_HSI (TERNOP, sqdmlsl2) 140 BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane) 141 BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane) 142 BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq) 143 BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq) 144 BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n) 145 BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n) 146 /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */ 147 BUILTIN_VSD_HSI (TERNOP, sqdmlal) 148 BUILTIN_VSD_HSI (TERNOP, sqdmlsl) 149 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */ 150 BUILTIN_VD_HSI (TERNOP, sqdmlal_n) 151 BUILTIN_VD_HSI (TERNOP, sqdmlsl_n) 152 153 BUILTIN_VSD_HSI (BINOP, sqdmull) 154 BUILTIN_VSD_HSI (TERNOP, sqdmull_lane) 155 BUILTIN_VD_HSI (TERNOP, sqdmull_laneq) 156 BUILTIN_VD_HSI (BINOP, sqdmull_n) 157 BUILTIN_VQ_HSI (BINOP, sqdmull2) 158 BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane) 159 BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq) 160 BUILTIN_VQ_HSI (BINOP, sqdmull2_n) 161 /* Implemented by aarch64_sq<r>dmulh<mode>. */ 162 BUILTIN_VSDQ_HSI (BINOP, sqdmulh) 163 BUILTIN_VSDQ_HSI (BINOP, sqrdmulh) 164 /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */ 165 BUILTIN_VDQHS (TERNOP, sqdmulh_lane) 166 BUILTIN_VDQHS (TERNOP, sqdmulh_laneq) 167 BUILTIN_VDQHS (TERNOP, sqrdmulh_lane) 168 BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq) 169 BUILTIN_SD_HSI (TERNOP, sqdmulh_lane) 170 BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane) 171 172 BUILTIN_VSDQ_I_DI (BINOP, sshl_n) 173 BUILTIN_VSDQ_I_DI (BINOP, ushl_n) 174 /* Implemented by aarch64_<sur>shl<mode>. */ 175 BUILTIN_VSDQ_I_DI (BINOP, sshl) 176 BUILTIN_VSDQ_I_DI (BINOP, ushl) 177 BUILTIN_VSDQ_I_DI (BINOP, srshl) 178 BUILTIN_VSDQ_I_DI (BINOP, urshl) 179 180 BUILTIN_VSDQ_I_DI (SHIFTIMM, sshr_n) 181 BUILTIN_VSDQ_I_DI (SHIFTIMM, ushr_n) 182 /* Implemented by aarch64_<sur>shr_n<mode>. */ 183 BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n) 184 BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n) 185 /* Implemented by aarch64_<sur>sra_n<mode>. */ 186 BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n) 187 BUILTIN_VSDQ_I_DI (SHIFTACC, usra_n) 188 BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n) 189 BUILTIN_VSDQ_I_DI (SHIFTACC, ursra_n) 190 /* Implemented by aarch64_<sur>shll_n<mode>. */ 191 BUILTIN_VDW (SHIFTIMM, sshll_n) 192 BUILTIN_VDW (SHIFTIMM, ushll_n) 193 /* Implemented by aarch64_<sur>shll2_n<mode>. */ 194 BUILTIN_VQW (SHIFTIMM, sshll2_n) 195 BUILTIN_VQW (SHIFTIMM, ushll2_n) 196 /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */ 197 BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n) 198 BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n) 199 BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n) 200 BUILTIN_VSQN_HSDI (SHIFTIMM, uqshrn_n) 201 BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n) 202 BUILTIN_VSQN_HSDI (SHIFTIMM, uqrshrn_n) 203 /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */ 204 BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n) 205 BUILTIN_VSDQ_I_DI (SHIFTINSERT, usri_n) 206 BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n) 207 BUILTIN_VSDQ_I_DI (SHIFTINSERT, usli_n) 208 /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */ 209 BUILTIN_VSDQ_I (SHIFTIMM, sqshlu_n) 210 BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n) 211 BUILTIN_VSDQ_I (SHIFTIMM, uqshl_n) 212 213 /* Implemented by aarch64_cm<cmp><mode>. */ 214 BUILTIN_VSDQ_I_DI (BINOP, cmeq) 215 BUILTIN_VSDQ_I_DI (BINOP, cmge) 216 BUILTIN_VSDQ_I_DI (BINOP, cmgt) 217 BUILTIN_VSDQ_I_DI (BINOP, cmle) 218 BUILTIN_VSDQ_I_DI (BINOP, cmlt) 219 /* Implemented by aarch64_cm<cmp><mode>. */ 220 BUILTIN_VSDQ_I_DI (BINOP, cmgeu) 221 BUILTIN_VSDQ_I_DI (BINOP, cmgtu) 222 BUILTIN_VSDQ_I_DI (BINOP, cmtst) 223 224 /* Implemented by aarch64_<fmaxmin><mode>. */ 225 BUILTIN_VDQF (BINOP, fmax) 226 BUILTIN_VDQF (BINOP, fmin) 227 /* Implemented by aarch64_<maxmin><mode>. */ 228 BUILTIN_VDQ_BHSI (BINOP, smax) 229 BUILTIN_VDQ_BHSI (BINOP, smin) 230 BUILTIN_VDQ_BHSI (BINOP, umax) 231 BUILTIN_VDQ_BHSI (BINOP, umin) 232 233 /* Implemented by aarch64_frint<frint_suffix><mode>. */ 234 BUILTIN_VDQF (UNOP, frintz) 235 BUILTIN_VDQF (UNOP, frintp) 236 BUILTIN_VDQF (UNOP, frintm) 237 BUILTIN_VDQF (UNOP, frinti) 238 BUILTIN_VDQF (UNOP, frintx) 239 BUILTIN_VDQF (UNOP, frinta) 240 241 /* Implemented by aarch64_fcvt<frint_suffix><su><mode>. */ 242 BUILTIN_VDQF (UNOP, fcvtzs) 243 BUILTIN_VDQF (UNOP, fcvtzu) 244 BUILTIN_VDQF (UNOP, fcvtas) 245 BUILTIN_VDQF (UNOP, fcvtau) 246 BUILTIN_VDQF (UNOP, fcvtps) 247 BUILTIN_VDQF (UNOP, fcvtpu) 248 BUILTIN_VDQF (UNOP, fcvtms) 249 BUILTIN_VDQF (UNOP, fcvtmu) 250 251 /* Implemented by 252 aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ 253 BUILTIN_VALL (BINOP, zip1) 254 BUILTIN_VALL (BINOP, zip2) 255 BUILTIN_VALL (BINOP, uzp1) 256 BUILTIN_VALL (BINOP, uzp2) 257 BUILTIN_VALL (BINOP, trn1) 258 BUILTIN_VALL (BINOP, trn2) 259 260 /* Implemented by aarch64_ld1<VALL:mode>. */ 261 BUILTIN_VALL (LOAD1, ld1) 262 263 /* Implemented by aarch64_st1<VALL:mode>. */ 264 BUILTIN_VALL (STORE1, st1) 265 266