1/* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2013 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21CC_MODE (CCFP); 22CC_MODE (CCFPE); 23CC_MODE (CC_SWP); 24CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS). */ 25CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS). */ 26CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */ 27 28/* Vector modes. */ 29VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */ 30VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI. */ 31VECTOR_MODES (FLOAT, 8); /* V2SF. */ 32VECTOR_MODES (FLOAT, 16); /* V4SF V2DF. */ 33 34/* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */ 35INT_MODE (OI, 32); 36 37/* Opaque integer modes for 3, 6 or 8 Neon double registers (2 is 38 TImode). */ 39INT_MODE (EI, 24); 40INT_MODE (CI, 48); 41INT_MODE (XI, 64); 42 43/* Vector modes for register lists. */ 44VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI. */ 45VECTOR_MODES (FLOAT, 32); /* V8SF V4DF. */ 46 47VECTOR_MODES (INT, 48); /* V32QI V16HI V8SI V4DI. */ 48VECTOR_MODES (FLOAT, 48); /* V8SF V4DF. */ 49 50VECTOR_MODES (INT, 64); /* V32QI V16HI V8SI V4DI. */ 51VECTOR_MODES (FLOAT, 64); /* V8SF V4DF. */ 52 53/* Quad float: 128-bit floating mode for long doubles. */ 54FLOAT_MODE (TF, 16, ieee_quad_format); 55