1 /* IA-32 common hooks. 2 Copyright (C) 1988-2015 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "diagnostic-core.h" 24 #include "tm.h" 25 #include "tm_p.h" 26 #include "common/common-target.h" 27 #include "common/common-target-def.h" 28 #include "opts.h" 29 #include "flags.h" 30 31 /* Define a set of ISAs which are available when a given ISA is 32 enabled. MMX and SSE ISAs are handled separately. */ 33 34 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX 35 #define OPTION_MASK_ISA_3DNOW_SET \ 36 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET) 37 38 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE 39 #define OPTION_MASK_ISA_SSE2_SET \ 40 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET) 41 #define OPTION_MASK_ISA_SSE3_SET \ 42 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET) 43 #define OPTION_MASK_ISA_SSSE3_SET \ 44 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET) 45 #define OPTION_MASK_ISA_SSE4_1_SET \ 46 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET) 47 #define OPTION_MASK_ISA_SSE4_2_SET \ 48 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET) 49 #define OPTION_MASK_ISA_AVX_SET \ 50 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \ 51 | OPTION_MASK_ISA_XSAVE_SET) 52 #define OPTION_MASK_ISA_FMA_SET \ 53 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) 54 #define OPTION_MASK_ISA_AVX2_SET \ 55 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) 56 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR 57 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE 58 #define OPTION_MASK_ISA_XSAVEOPT_SET \ 59 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE) 60 #define OPTION_MASK_ISA_AVX512F_SET \ 61 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET) 62 #define OPTION_MASK_ISA_AVX512CD_SET \ 63 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET) 64 #define OPTION_MASK_ISA_AVX512PF_SET \ 65 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET) 66 #define OPTION_MASK_ISA_AVX512ER_SET \ 67 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET) 68 #define OPTION_MASK_ISA_AVX512DQ_SET \ 69 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) 70 #define OPTION_MASK_ISA_AVX512BW_SET \ 71 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) 72 #define OPTION_MASK_ISA_AVX512VL_SET \ 73 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) 74 #define OPTION_MASK_ISA_AVX512IFMA_SET \ 75 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) 76 #define OPTION_MASK_ISA_AVX512VBMI_SET \ 77 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) 78 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM 79 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW 80 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED 81 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX 82 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1 83 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT 84 #define OPTION_MASK_ISA_XSAVES_SET \ 85 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE) 86 #define OPTION_MASK_ISA_XSAVEC_SET \ 87 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE) 88 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB 89 90 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same 91 as -msse4.2. */ 92 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET 93 94 #define OPTION_MASK_ISA_SSE4A_SET \ 95 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET) 96 #define OPTION_MASK_ISA_FMA4_SET \ 97 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \ 98 | OPTION_MASK_ISA_AVX_SET) 99 #define OPTION_MASK_ISA_XOP_SET \ 100 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) 101 #define OPTION_MASK_ISA_LWP_SET \ 102 OPTION_MASK_ISA_LWP 103 104 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */ 105 #define OPTION_MASK_ISA_AES_SET \ 106 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET) 107 #define OPTION_MASK_ISA_SHA_SET \ 108 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET) 109 #define OPTION_MASK_ISA_PCLMUL_SET \ 110 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) 111 112 #define OPTION_MASK_ISA_ABM_SET \ 113 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) 114 115 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI 116 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 117 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT 118 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM 119 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT 120 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16 121 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF 122 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE 123 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 124 125 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE 126 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND 127 #define OPTION_MASK_ISA_F16C_SET \ 128 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) 129 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX 130 131 /* Define a set of ISAs which aren't available when a given ISA is 132 disabled. MMX and SSE ISAs are handled separately. */ 133 134 #define OPTION_MASK_ISA_MMX_UNSET \ 135 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET) 136 #define OPTION_MASK_ISA_3DNOW_UNSET \ 137 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET) 138 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A 139 140 #define OPTION_MASK_ISA_SSE_UNSET \ 141 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET) 142 #define OPTION_MASK_ISA_SSE2_UNSET \ 143 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET) 144 #define OPTION_MASK_ISA_SSE3_UNSET \ 145 (OPTION_MASK_ISA_SSE3 \ 146 | OPTION_MASK_ISA_SSSE3_UNSET \ 147 | OPTION_MASK_ISA_SSE4A_UNSET ) 148 #define OPTION_MASK_ISA_SSSE3_UNSET \ 149 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET) 150 #define OPTION_MASK_ISA_SSE4_1_UNSET \ 151 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET) 152 #define OPTION_MASK_ISA_SSE4_2_UNSET \ 153 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) 154 #define OPTION_MASK_ISA_AVX_UNSET \ 155 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ 156 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ 157 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET) 158 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA 159 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR 160 #define OPTION_MASK_ISA_XSAVE_UNSET \ 161 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET) 162 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT 163 #define OPTION_MASK_ISA_AVX2_UNSET \ 164 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) 165 #define OPTION_MASK_ISA_AVX512F_UNSET \ 166 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ 167 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ 168 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \ 169 | OPTION_MASK_ISA_AVX512VL_UNSET) 170 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD 171 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF 172 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER 173 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ 174 #define OPTION_MASK_ISA_AVX512BW_UNSET \ 175 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) 176 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL 177 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA 178 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI 179 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM 180 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW 181 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED 182 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX 183 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1 184 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT 185 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC 186 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES 187 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB 188 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX 189 190 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same 191 as -mno-sse4.1. */ 192 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET 193 194 #define OPTION_MASK_ISA_SSE4A_UNSET \ 195 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET) 196 197 #define OPTION_MASK_ISA_FMA4_UNSET \ 198 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) 199 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP 200 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP 201 202 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES 203 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA 204 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL 205 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM 206 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI 207 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 208 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT 209 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM 210 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT 211 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16 212 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF 213 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE 214 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 215 216 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE 217 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND 218 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C 219 220 /* Implement TARGET_HANDLE_OPTION. */ 221 222 bool 223 ix86_handle_option (struct gcc_options *opts, 224 struct gcc_options *opts_set ATTRIBUTE_UNUSED, 225 const struct cl_decoded_option *decoded, 226 location_t loc) 227 { 228 size_t code = decoded->opt_index; 229 int value = decoded->value; 230 231 switch (code) 232 { 233 case OPT_mmmx: 234 if (value) 235 { 236 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET; 237 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET; 238 } 239 else 240 { 241 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET; 242 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET; 243 } 244 return true; 245 246 case OPT_m3dnow: 247 if (value) 248 { 249 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET; 250 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET; 251 } 252 else 253 { 254 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET; 255 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET; 256 } 257 return true; 258 259 case OPT_m3dnowa: 260 return false; 261 262 case OPT_msse: 263 if (value) 264 { 265 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET; 266 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET; 267 } 268 else 269 { 270 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET; 271 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET; 272 } 273 return true; 274 275 case OPT_msse2: 276 if (value) 277 { 278 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET; 279 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET; 280 } 281 else 282 { 283 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET; 284 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET; 285 } 286 return true; 287 288 case OPT_msse3: 289 if (value) 290 { 291 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET; 292 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET; 293 } 294 else 295 { 296 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET; 297 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET; 298 } 299 return true; 300 301 case OPT_mssse3: 302 if (value) 303 { 304 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET; 305 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET; 306 } 307 else 308 { 309 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET; 310 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET; 311 } 312 return true; 313 314 case OPT_msse4_1: 315 if (value) 316 { 317 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET; 318 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET; 319 } 320 else 321 { 322 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET; 323 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET; 324 } 325 return true; 326 327 case OPT_msse4_2: 328 if (value) 329 { 330 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET; 331 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET; 332 } 333 else 334 { 335 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET; 336 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET; 337 } 338 return true; 339 340 case OPT_mavx: 341 if (value) 342 { 343 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; 344 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; 345 } 346 else 347 { 348 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET; 349 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET; 350 } 351 return true; 352 353 case OPT_mavx2: 354 if (value) 355 { 356 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; 357 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; 358 } 359 else 360 { 361 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET; 362 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET; 363 } 364 return true; 365 366 case OPT_mavx512f: 367 if (value) 368 { 369 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; 370 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; 371 } 372 else 373 { 374 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET; 375 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET; 376 } 377 return true; 378 379 case OPT_mavx512cd: 380 if (value) 381 { 382 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET; 383 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET; 384 } 385 else 386 { 387 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET; 388 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET; 389 } 390 return true; 391 392 case OPT_mavx512pf: 393 if (value) 394 { 395 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET; 396 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET; 397 } 398 else 399 { 400 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET; 401 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET; 402 } 403 return true; 404 405 case OPT_mavx512er: 406 if (value) 407 { 408 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET; 409 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET; 410 } 411 else 412 { 413 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET; 414 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET; 415 } 416 return true; 417 418 case OPT_mavx512dq: 419 if (value) 420 { 421 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET; 422 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET; 423 } 424 else 425 { 426 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET; 427 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET; 428 } 429 return true; 430 431 case OPT_mavx512bw: 432 if (value) 433 { 434 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET; 435 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET; 436 } 437 else 438 { 439 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET; 440 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET; 441 } 442 return true; 443 444 case OPT_mavx512vl: 445 if (value) 446 { 447 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET; 448 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET; 449 } 450 else 451 { 452 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET; 453 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET; 454 } 455 return true; 456 457 case OPT_mavx512ifma: 458 if (value) 459 { 460 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET; 461 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET; 462 } 463 else 464 { 465 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET; 466 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET; 467 } 468 return true; 469 470 case OPT_mavx512vbmi: 471 if (value) 472 { 473 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET; 474 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET; 475 } 476 else 477 { 478 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET; 479 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET; 480 } 481 return true; 482 483 case OPT_mfma: 484 if (value) 485 { 486 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET; 487 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET; 488 } 489 else 490 { 491 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET; 492 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET; 493 } 494 return true; 495 496 case OPT_mrtm: 497 if (value) 498 { 499 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET; 500 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET; 501 } 502 else 503 { 504 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET; 505 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET; 506 } 507 return true; 508 509 case OPT_msse4: 510 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET; 511 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET; 512 return true; 513 514 case OPT_mno_sse4: 515 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET; 516 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET; 517 return true; 518 519 case OPT_msse4a: 520 if (value) 521 { 522 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET; 523 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET; 524 } 525 else 526 { 527 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET; 528 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET; 529 } 530 return true; 531 532 case OPT_mfma4: 533 if (value) 534 { 535 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET; 536 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET; 537 } 538 else 539 { 540 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET; 541 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET; 542 } 543 return true; 544 545 case OPT_mxop: 546 if (value) 547 { 548 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET; 549 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET; 550 } 551 else 552 { 553 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET; 554 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET; 555 } 556 return true; 557 558 case OPT_mlwp: 559 if (value) 560 { 561 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET; 562 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET; 563 } 564 else 565 { 566 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET; 567 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET; 568 } 569 return true; 570 571 case OPT_mabm: 572 if (value) 573 { 574 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET; 575 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET; 576 } 577 else 578 { 579 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET; 580 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET; 581 } 582 return true; 583 584 case OPT_mbmi: 585 if (value) 586 { 587 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET; 588 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET; 589 } 590 else 591 { 592 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET; 593 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET; 594 } 595 return true; 596 597 case OPT_mbmi2: 598 if (value) 599 { 600 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET; 601 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET; 602 } 603 else 604 { 605 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET; 606 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET; 607 } 608 return true; 609 610 case OPT_mlzcnt: 611 if (value) 612 { 613 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET; 614 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET; 615 } 616 else 617 { 618 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET; 619 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET; 620 } 621 return true; 622 623 case OPT_mtbm: 624 if (value) 625 { 626 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET; 627 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET; 628 } 629 else 630 { 631 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET; 632 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET; 633 } 634 return true; 635 636 case OPT_mpopcnt: 637 if (value) 638 { 639 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET; 640 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET; 641 } 642 else 643 { 644 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET; 645 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET; 646 } 647 return true; 648 649 case OPT_msahf: 650 if (value) 651 { 652 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET; 653 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET; 654 } 655 else 656 { 657 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET; 658 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET; 659 } 660 return true; 661 662 case OPT_mcx16: 663 if (value) 664 { 665 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET; 666 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET; 667 } 668 else 669 { 670 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET; 671 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET; 672 } 673 return true; 674 675 case OPT_mmovbe: 676 if (value) 677 { 678 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET; 679 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET; 680 } 681 else 682 { 683 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET; 684 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET; 685 } 686 return true; 687 688 case OPT_mcrc32: 689 if (value) 690 { 691 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET; 692 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET; 693 } 694 else 695 { 696 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET; 697 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET; 698 } 699 return true; 700 701 case OPT_maes: 702 if (value) 703 { 704 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET; 705 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET; 706 } 707 else 708 { 709 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET; 710 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET; 711 } 712 return true; 713 714 case OPT_msha: 715 if (value) 716 { 717 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET; 718 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET; 719 } 720 else 721 { 722 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET; 723 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET; 724 } 725 return true; 726 727 case OPT_mpclmul: 728 if (value) 729 { 730 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET; 731 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET; 732 } 733 else 734 { 735 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET; 736 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET; 737 } 738 return true; 739 740 case OPT_mfsgsbase: 741 if (value) 742 { 743 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET; 744 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET; 745 } 746 else 747 { 748 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET; 749 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET; 750 } 751 return true; 752 753 case OPT_mrdrnd: 754 if (value) 755 { 756 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET; 757 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET; 758 } 759 else 760 { 761 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET; 762 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET; 763 } 764 return true; 765 766 case OPT_mf16c: 767 if (value) 768 { 769 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET; 770 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET; 771 } 772 else 773 { 774 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET; 775 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET; 776 } 777 return true; 778 779 case OPT_mfxsr: 780 if (value) 781 { 782 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET; 783 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET; 784 } 785 else 786 { 787 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET; 788 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET; 789 } 790 return true; 791 792 case OPT_mxsave: 793 if (value) 794 { 795 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET; 796 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET; 797 } 798 else 799 { 800 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET; 801 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET; 802 } 803 return true; 804 805 case OPT_mxsaveopt: 806 if (value) 807 { 808 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET; 809 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET; 810 } 811 else 812 { 813 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET; 814 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET; 815 } 816 return true; 817 818 case OPT_mxsavec: 819 if (value) 820 { 821 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET; 822 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET; 823 } 824 else 825 { 826 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET; 827 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET; 828 } 829 return true; 830 831 case OPT_mxsaves: 832 if (value) 833 { 834 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET; 835 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET; 836 } 837 else 838 { 839 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET; 840 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET; 841 } 842 return true; 843 844 case OPT_mrdseed: 845 if (value) 846 { 847 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET; 848 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET; 849 } 850 else 851 { 852 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET; 853 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET; 854 } 855 return true; 856 857 case OPT_mprfchw: 858 if (value) 859 { 860 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET; 861 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET; 862 } 863 else 864 { 865 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET; 866 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET; 867 } 868 return true; 869 870 case OPT_madx: 871 if (value) 872 { 873 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET; 874 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET; 875 } 876 else 877 { 878 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET; 879 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET; 880 } 881 return true; 882 883 case OPT_mprefetchwt1: 884 if (value) 885 { 886 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET; 887 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET; 888 } 889 else 890 { 891 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET; 892 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET; 893 } 894 return true; 895 896 case OPT_mclflushopt: 897 if (value) 898 { 899 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET; 900 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET; 901 } 902 else 903 { 904 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET; 905 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET; 906 } 907 return true; 908 909 case OPT_mclwb: 910 if (value) 911 { 912 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET; 913 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET; 914 } 915 else 916 { 917 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET; 918 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET; 919 } 920 return true; 921 922 case OPT_mmwaitx: 923 if (value) 924 { 925 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MWAITX_SET; 926 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MWAITX_SET; 927 } 928 else 929 { 930 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MWAITX_UNSET; 931 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MWAITX_UNSET; 932 } 933 return true; 934 935 /* Comes from final.c -- no real reason to change it. */ 936 #define MAX_CODE_ALIGN 16 937 938 case OPT_malign_loops_: 939 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops"); 940 if (value > MAX_CODE_ALIGN) 941 error_at (loc, "-malign-loops=%d is not between 0 and %d", 942 value, MAX_CODE_ALIGN); 943 else 944 opts->x_align_loops = 1 << value; 945 return true; 946 947 case OPT_malign_jumps_: 948 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps"); 949 if (value > MAX_CODE_ALIGN) 950 error_at (loc, "-malign-jumps=%d is not between 0 and %d", 951 value, MAX_CODE_ALIGN); 952 else 953 opts->x_align_jumps = 1 << value; 954 return true; 955 956 case OPT_malign_functions_: 957 warning_at (loc, 0, 958 "-malign-functions is obsolete, use -falign-functions"); 959 if (value > MAX_CODE_ALIGN) 960 error_at (loc, "-malign-functions=%d is not between 0 and %d", 961 value, MAX_CODE_ALIGN); 962 else 963 opts->x_align_functions = 1 << value; 964 return true; 965 966 case OPT_mbranch_cost_: 967 if (value > 5) 968 { 969 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value); 970 opts->x_ix86_branch_cost = 5; 971 } 972 return true; 973 974 default: 975 return true; 976 } 977 } 978 979 static const struct default_options ix86_option_optimization_table[] = 980 { 981 /* Enable redundant extension instructions removal at -O2 and higher. */ 982 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, 983 /* Enable function splitting at -O2 and higher. */ 984 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 }, 985 /* Turn off -fschedule-insns by default. It tends to make the 986 problem with not enough registers even worse. */ 987 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 }, 988 989 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS 990 SUBTARGET_OPTIMIZATION_OPTIONS, 991 #endif 992 { OPT_LEVELS_NONE, 0, NULL, 0 } 993 }; 994 995 /* Implement TARGET_OPTION_INIT_STRUCT. */ 996 997 static void 998 ix86_option_init_struct (struct gcc_options *opts) 999 { 1000 if (TARGET_MACHO) 1001 /* The Darwin libraries never set errno, so we might as well 1002 avoid calling them when that's the only reason we would. */ 1003 opts->x_flag_errno_math = 0; 1004 1005 opts->x_flag_pcc_struct_return = 2; 1006 opts->x_flag_asynchronous_unwind_tables = 2; 1007 } 1008 1009 /* On the x86 -fsplit-stack and -fstack-protector both use the same 1010 field in the TCB, so they can not be used together. */ 1011 1012 static bool 1013 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED, 1014 struct gcc_options *opts ATTRIBUTE_UNUSED) 1015 { 1016 bool ret = true; 1017 1018 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET 1019 if (report) 1020 error ("%<-fsplit-stack%> currently only supported on GNU/Linux"); 1021 ret = false; 1022 #else 1023 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) 1024 { 1025 if (report) 1026 error ("%<-fsplit-stack%> requires " 1027 "assembler support for CFI directives"); 1028 ret = false; 1029 } 1030 #endif 1031 1032 return ret; 1033 } 1034 1035 /* Implement TARGET_EXCEPT_UNWIND_INFO. */ 1036 1037 static enum unwind_info_type 1038 i386_except_unwind_info (struct gcc_options *opts) 1039 { 1040 /* Honor the --enable-sjlj-exceptions configure switch. */ 1041 #ifdef CONFIG_SJLJ_EXCEPTIONS 1042 if (CONFIG_SJLJ_EXCEPTIONS) 1043 return UI_SJLJ; 1044 #endif 1045 1046 /* On windows 64, prefer SEH exceptions over anything else. */ 1047 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables) 1048 return UI_SEH; 1049 1050 if (DWARF2_UNWIND_INFO) 1051 return UI_DWARF2; 1052 1053 return UI_SJLJ; 1054 } 1055 1056 #undef TARGET_EXCEPT_UNWIND_INFO 1057 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info 1058 1059 #undef TARGET_DEFAULT_TARGET_FLAGS 1060 #define TARGET_DEFAULT_TARGET_FLAGS \ 1061 (TARGET_DEFAULT \ 1062 | TARGET_SUBTARGET_DEFAULT \ 1063 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT) 1064 1065 #undef TARGET_HANDLE_OPTION 1066 #define TARGET_HANDLE_OPTION ix86_handle_option 1067 1068 #undef TARGET_OPTION_OPTIMIZATION_TABLE 1069 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table 1070 #undef TARGET_OPTION_INIT_STRUCT 1071 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct 1072 1073 #undef TARGET_SUPPORTS_SPLIT_STACK 1074 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack 1075 1076 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; 1077