1 /* IA-32 common hooks. 2 Copyright (C) 1988-2013 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "diagnostic-core.h" 24 #include "tm.h" 25 #include "tm_p.h" 26 #include "common/common-target.h" 27 #include "common/common-target-def.h" 28 #include "opts.h" 29 #include "flags.h" 30 31 /* Define a set of ISAs which are available when a given ISA is 32 enabled. MMX and SSE ISAs are handled separately. */ 33 34 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX 35 #define OPTION_MASK_ISA_3DNOW_SET \ 36 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET) 37 38 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE 39 #define OPTION_MASK_ISA_SSE2_SET \ 40 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET) 41 #define OPTION_MASK_ISA_SSE3_SET \ 42 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET) 43 #define OPTION_MASK_ISA_SSSE3_SET \ 44 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET) 45 #define OPTION_MASK_ISA_SSE4_1_SET \ 46 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET) 47 #define OPTION_MASK_ISA_SSE4_2_SET \ 48 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET) 49 #define OPTION_MASK_ISA_AVX_SET \ 50 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \ 51 | OPTION_MASK_ISA_XSAVE_SET) 52 #define OPTION_MASK_ISA_FMA_SET \ 53 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) 54 #define OPTION_MASK_ISA_AVX2_SET \ 55 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) 56 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR 57 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE 58 #define OPTION_MASK_ISA_XSAVEOPT_SET \ 59 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE) 60 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM 61 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW 62 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED 63 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX 64 65 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same 66 as -msse4.2. */ 67 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET 68 69 #define OPTION_MASK_ISA_SSE4A_SET \ 70 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET) 71 #define OPTION_MASK_ISA_FMA4_SET \ 72 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \ 73 | OPTION_MASK_ISA_AVX_SET) 74 #define OPTION_MASK_ISA_XOP_SET \ 75 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) 76 #define OPTION_MASK_ISA_LWP_SET \ 77 OPTION_MASK_ISA_LWP 78 79 /* AES and PCLMUL need SSE2 because they use xmm registers */ 80 #define OPTION_MASK_ISA_AES_SET \ 81 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET) 82 #define OPTION_MASK_ISA_PCLMUL_SET \ 83 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) 84 85 #define OPTION_MASK_ISA_ABM_SET \ 86 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) 87 88 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI 89 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 90 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM 91 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT 92 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16 93 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF 94 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE 95 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 96 97 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE 98 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND 99 #define OPTION_MASK_ISA_F16C_SET \ 100 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) 101 102 /* Define a set of ISAs which aren't available when a given ISA is 103 disabled. MMX and SSE ISAs are handled separately. */ 104 105 #define OPTION_MASK_ISA_MMX_UNSET \ 106 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET) 107 #define OPTION_MASK_ISA_3DNOW_UNSET \ 108 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET) 109 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A 110 111 #define OPTION_MASK_ISA_SSE_UNSET \ 112 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET) 113 #define OPTION_MASK_ISA_SSE2_UNSET \ 114 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET) 115 #define OPTION_MASK_ISA_SSE3_UNSET \ 116 (OPTION_MASK_ISA_SSE3 \ 117 | OPTION_MASK_ISA_SSSE3_UNSET \ 118 | OPTION_MASK_ISA_SSE4A_UNSET ) 119 #define OPTION_MASK_ISA_SSSE3_UNSET \ 120 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET) 121 #define OPTION_MASK_ISA_SSE4_1_UNSET \ 122 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET) 123 #define OPTION_MASK_ISA_SSE4_2_UNSET \ 124 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) 125 #define OPTION_MASK_ISA_AVX_UNSET \ 126 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ 127 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ 128 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET) 129 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA 130 #define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2 131 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR 132 #define OPTION_MASK_ISA_XSAVE_UNSET \ 133 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET) 134 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT 135 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM 136 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW 137 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED 138 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX 139 140 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same 141 as -mno-sse4.1. */ 142 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET 143 144 #define OPTION_MASK_ISA_SSE4A_UNSET \ 145 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET) 146 147 #define OPTION_MASK_ISA_FMA4_UNSET \ 148 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) 149 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP 150 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP 151 152 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES 153 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL 154 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM 155 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI 156 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 157 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM 158 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT 159 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16 160 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF 161 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE 162 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 163 164 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE 165 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND 166 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C 167 168 /* Implement TARGET_HANDLE_OPTION. */ 169 170 bool 171 ix86_handle_option (struct gcc_options *opts, 172 struct gcc_options *opts_set ATTRIBUTE_UNUSED, 173 const struct cl_decoded_option *decoded, 174 location_t loc) 175 { 176 size_t code = decoded->opt_index; 177 int value = decoded->value; 178 179 switch (code) 180 { 181 case OPT_mmmx: 182 if (value) 183 { 184 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET; 185 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET; 186 } 187 else 188 { 189 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET; 190 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET; 191 } 192 return true; 193 194 case OPT_m3dnow: 195 if (value) 196 { 197 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET; 198 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET; 199 } 200 else 201 { 202 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET; 203 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET; 204 } 205 return true; 206 207 case OPT_m3dnowa: 208 return false; 209 210 case OPT_msse: 211 if (value) 212 { 213 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET; 214 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET; 215 } 216 else 217 { 218 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET; 219 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET; 220 } 221 return true; 222 223 case OPT_msse2: 224 if (value) 225 { 226 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET; 227 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET; 228 } 229 else 230 { 231 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET; 232 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET; 233 } 234 return true; 235 236 case OPT_msse3: 237 if (value) 238 { 239 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET; 240 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET; 241 } 242 else 243 { 244 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET; 245 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET; 246 } 247 return true; 248 249 case OPT_mssse3: 250 if (value) 251 { 252 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET; 253 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET; 254 } 255 else 256 { 257 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET; 258 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET; 259 } 260 return true; 261 262 case OPT_msse4_1: 263 if (value) 264 { 265 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET; 266 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET; 267 } 268 else 269 { 270 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET; 271 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET; 272 } 273 return true; 274 275 case OPT_msse4_2: 276 if (value) 277 { 278 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET; 279 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET; 280 } 281 else 282 { 283 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET; 284 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET; 285 } 286 return true; 287 288 case OPT_mavx: 289 if (value) 290 { 291 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; 292 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; 293 } 294 else 295 { 296 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET; 297 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET; 298 } 299 return true; 300 301 case OPT_mavx2: 302 if (value) 303 { 304 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; 305 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; 306 } 307 else 308 { 309 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET; 310 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET; 311 } 312 return true; 313 314 case OPT_mfma: 315 if (value) 316 { 317 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET; 318 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET; 319 } 320 else 321 { 322 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET; 323 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET; 324 } 325 return true; 326 327 case OPT_mrtm: 328 if (value) 329 { 330 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET; 331 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET; 332 } 333 else 334 { 335 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET; 336 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET; 337 } 338 return true; 339 340 case OPT_msse4: 341 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET; 342 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET; 343 return true; 344 345 case OPT_mno_sse4: 346 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET; 347 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET; 348 return true; 349 350 case OPT_msse4a: 351 if (value) 352 { 353 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET; 354 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET; 355 } 356 else 357 { 358 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET; 359 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET; 360 } 361 return true; 362 363 case OPT_mfma4: 364 if (value) 365 { 366 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET; 367 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET; 368 } 369 else 370 { 371 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET; 372 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET; 373 } 374 return true; 375 376 case OPT_mxop: 377 if (value) 378 { 379 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET; 380 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET; 381 } 382 else 383 { 384 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET; 385 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET; 386 } 387 return true; 388 389 case OPT_mlwp: 390 if (value) 391 { 392 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET; 393 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET; 394 } 395 else 396 { 397 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET; 398 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET; 399 } 400 return true; 401 402 case OPT_mabm: 403 if (value) 404 { 405 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET; 406 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET; 407 } 408 else 409 { 410 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET; 411 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET; 412 } 413 return true; 414 415 case OPT_mbmi: 416 if (value) 417 { 418 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET; 419 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET; 420 } 421 else 422 { 423 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET; 424 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET; 425 } 426 return true; 427 428 case OPT_mbmi2: 429 if (value) 430 { 431 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET; 432 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET; 433 } 434 else 435 { 436 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET; 437 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET; 438 } 439 return true; 440 441 case OPT_mtbm: 442 if (value) 443 { 444 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET; 445 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET; 446 } 447 else 448 { 449 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET; 450 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET; 451 } 452 return true; 453 454 case OPT_mpopcnt: 455 if (value) 456 { 457 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET; 458 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET; 459 } 460 else 461 { 462 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET; 463 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET; 464 } 465 return true; 466 467 case OPT_msahf: 468 if (value) 469 { 470 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET; 471 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET; 472 } 473 else 474 { 475 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET; 476 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET; 477 } 478 return true; 479 480 case OPT_mcx16: 481 if (value) 482 { 483 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET; 484 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET; 485 } 486 else 487 { 488 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET; 489 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET; 490 } 491 return true; 492 493 case OPT_mmovbe: 494 if (value) 495 { 496 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET; 497 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET; 498 } 499 else 500 { 501 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET; 502 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET; 503 } 504 return true; 505 506 case OPT_mcrc32: 507 if (value) 508 { 509 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET; 510 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET; 511 } 512 else 513 { 514 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET; 515 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET; 516 } 517 return true; 518 519 case OPT_maes: 520 if (value) 521 { 522 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET; 523 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET; 524 } 525 else 526 { 527 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET; 528 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET; 529 } 530 return true; 531 532 case OPT_mpclmul: 533 if (value) 534 { 535 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET; 536 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET; 537 } 538 else 539 { 540 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET; 541 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET; 542 } 543 return true; 544 545 case OPT_mfsgsbase: 546 if (value) 547 { 548 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET; 549 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET; 550 } 551 else 552 { 553 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET; 554 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET; 555 } 556 return true; 557 558 case OPT_mrdrnd: 559 if (value) 560 { 561 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET; 562 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET; 563 } 564 else 565 { 566 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET; 567 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET; 568 } 569 return true; 570 571 case OPT_mf16c: 572 if (value) 573 { 574 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET; 575 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET; 576 } 577 else 578 { 579 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET; 580 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET; 581 } 582 return true; 583 584 case OPT_mfxsr: 585 if (value) 586 { 587 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET; 588 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET; 589 } 590 else 591 { 592 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET; 593 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET; 594 } 595 return true; 596 597 case OPT_mxsave: 598 if (value) 599 { 600 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET; 601 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET; 602 } 603 else 604 { 605 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET; 606 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET; 607 } 608 return true; 609 610 case OPT_mxsaveopt: 611 if (value) 612 { 613 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET; 614 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET; 615 } 616 else 617 { 618 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET; 619 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET; 620 } 621 return true; 622 623 case OPT_mrdseed: 624 if (value) 625 { 626 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET; 627 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET; 628 } 629 else 630 { 631 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET; 632 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET; 633 } 634 return true; 635 636 case OPT_mprfchw: 637 if (value) 638 { 639 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET; 640 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET; 641 } 642 else 643 { 644 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET; 645 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET; 646 } 647 return true; 648 649 case OPT_madx: 650 if (value) 651 { 652 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET; 653 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET; 654 } 655 else 656 { 657 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET; 658 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET; 659 } 660 return true; 661 662 /* Comes from final.c -- no real reason to change it. */ 663 #define MAX_CODE_ALIGN 16 664 665 case OPT_malign_loops_: 666 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops"); 667 if (value > MAX_CODE_ALIGN) 668 error_at (loc, "-malign-loops=%d is not between 0 and %d", 669 value, MAX_CODE_ALIGN); 670 else 671 opts->x_align_loops = 1 << value; 672 return true; 673 674 case OPT_malign_jumps_: 675 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps"); 676 if (value > MAX_CODE_ALIGN) 677 error_at (loc, "-malign-jumps=%d is not between 0 and %d", 678 value, MAX_CODE_ALIGN); 679 else 680 opts->x_align_jumps = 1 << value; 681 return true; 682 683 case OPT_malign_functions_: 684 warning_at (loc, 0, 685 "-malign-functions is obsolete, use -falign-functions"); 686 if (value > MAX_CODE_ALIGN) 687 error_at (loc, "-malign-functions=%d is not between 0 and %d", 688 value, MAX_CODE_ALIGN); 689 else 690 opts->x_align_functions = 1 << value; 691 return true; 692 693 case OPT_mbranch_cost_: 694 if (value > 5) 695 { 696 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value); 697 opts->x_ix86_branch_cost = 5; 698 } 699 return true; 700 701 default: 702 return true; 703 } 704 } 705 706 static const struct default_options ix86_option_optimization_table[] = 707 { 708 /* Enable redundant extension instructions removal at -O2 and higher. */ 709 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, 710 /* Turn off -fschedule-insns by default. It tends to make the 711 problem with not enough registers even worse. */ 712 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 }, 713 714 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS 715 SUBTARGET_OPTIMIZATION_OPTIONS, 716 #endif 717 { OPT_LEVELS_NONE, 0, NULL, 0 } 718 }; 719 720 /* Implement TARGET_OPTION_INIT_STRUCT. */ 721 722 static void 723 ix86_option_init_struct (struct gcc_options *opts) 724 { 725 if (TARGET_MACHO) 726 /* The Darwin libraries never set errno, so we might as well 727 avoid calling them when that's the only reason we would. */ 728 opts->x_flag_errno_math = 0; 729 730 opts->x_flag_pcc_struct_return = 2; 731 opts->x_flag_asynchronous_unwind_tables = 2; 732 opts->x_flag_vect_cost_model = 1; 733 } 734 735 /* On the x86 -fsplit-stack and -fstack-protector both use the same 736 field in the TCB, so they can not be used together. */ 737 738 static bool 739 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED, 740 struct gcc_options *opts ATTRIBUTE_UNUSED) 741 { 742 bool ret = true; 743 744 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET 745 if (report) 746 error ("%<-fsplit-stack%> currently only supported on GNU/Linux"); 747 ret = false; 748 #else 749 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) 750 { 751 if (report) 752 error ("%<-fsplit-stack%> requires " 753 "assembler support for CFI directives"); 754 ret = false; 755 } 756 #endif 757 758 return ret; 759 } 760 761 /* Implement TARGET_EXCEPT_UNWIND_INFO. */ 762 763 static enum unwind_info_type 764 i386_except_unwind_info (struct gcc_options *opts) 765 { 766 /* Honor the --enable-sjlj-exceptions configure switch. */ 767 #ifdef CONFIG_SJLJ_EXCEPTIONS 768 if (CONFIG_SJLJ_EXCEPTIONS) 769 return UI_SJLJ; 770 #endif 771 772 /* On windows 64, prefer SEH exceptions over anything else. */ 773 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables) 774 return UI_SEH; 775 776 if (DWARF2_UNWIND_INFO) 777 return UI_DWARF2; 778 779 return UI_SJLJ; 780 } 781 782 #undef TARGET_EXCEPT_UNWIND_INFO 783 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info 784 785 #undef TARGET_DEFAULT_TARGET_FLAGS 786 #define TARGET_DEFAULT_TARGET_FLAGS \ 787 (TARGET_DEFAULT \ 788 | TARGET_SUBTARGET_DEFAULT \ 789 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT) 790 791 #undef TARGET_HANDLE_OPTION 792 #define TARGET_HANDLE_OPTION ix86_handle_option 793 794 #undef TARGET_OPTION_OPTIMIZATION_TABLE 795 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table 796 #undef TARGET_OPTION_INIT_STRUCT 797 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct 798 799 #undef TARGET_SUPPORTS_SPLIT_STACK 800 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack 801 802 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; 803