1 /* Optimize by combining instructions for GNU compiler. 2 Copyright (C) 1987-2017 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 /* This module is essentially the "combiner" phase of the U. of Arizona 21 Portable Optimizer, but redone to work on our list-structured 22 representation for RTL instead of their string representation. 23 24 The LOG_LINKS of each insn identify the most recent assignment 25 to each REG used in the insn. It is a list of previous insns, 26 each of which contains a SET for a REG that is used in this insn 27 and not used or set in between. LOG_LINKs never cross basic blocks. 28 They were set up by the preceding pass (lifetime analysis). 29 30 We try to combine each pair of insns joined by a logical link. 31 We also try to combine triplets of insns A, B and C when C has 32 a link back to B and B has a link back to A. Likewise for a 33 small number of quadruplets of insns A, B, C and D for which 34 there's high likelihood of success. 35 36 LOG_LINKS does not have links for use of the CC0. They don't 37 need to, because the insn that sets the CC0 is always immediately 38 before the insn that tests it. So we always regard a branch 39 insn as having a logical link to the preceding insn. The same is true 40 for an insn explicitly using CC0. 41 42 We check (with use_crosses_set_p) to avoid combining in such a way 43 as to move a computation to a place where its value would be different. 44 45 Combination is done by mathematically substituting the previous 46 insn(s) values for the regs they set into the expressions in 47 the later insns that refer to these regs. If the result is a valid insn 48 for our target machine, according to the machine description, 49 we install it, delete the earlier insns, and update the data flow 50 information (LOG_LINKS and REG_NOTES) for what we did. 51 52 There are a few exceptions where the dataflow information isn't 53 completely updated (however this is only a local issue since it is 54 regenerated before the next pass that uses it): 55 56 - reg_live_length is not updated 57 - reg_n_refs is not adjusted in the rare case when a register is 58 no longer required in a computation 59 - there are extremely rare cases (see distribute_notes) when a 60 REG_DEAD note is lost 61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be 62 removed because there is no way to know which register it was 63 linking 64 65 To simplify substitution, we combine only when the earlier insn(s) 66 consist of only a single assignment. To simplify updating afterward, 67 we never combine when a subroutine call appears in the middle. 68 69 Since we do not represent assignments to CC0 explicitly except when that 70 is all an insn does, there is no LOG_LINKS entry in an insn that uses 71 the condition code for the insn that set the condition code. 72 Fortunately, these two insns must be consecutive. 73 Therefore, every JUMP_INSN is taken to have an implicit logical link 74 to the preceding insn. This is not quite right, since non-jumps can 75 also use the condition code; but in practice such insns would not 76 combine anyway. */ 77 78 #include "config.h" 79 #include "system.h" 80 #include "coretypes.h" 81 #include "backend.h" 82 #include "target.h" 83 #include "rtl.h" 84 #include "tree.h" 85 #include "cfghooks.h" 86 #include "predict.h" 87 #include "df.h" 88 #include "memmodel.h" 89 #include "tm_p.h" 90 #include "optabs.h" 91 #include "regs.h" 92 #include "emit-rtl.h" 93 #include "recog.h" 94 #include "cgraph.h" 95 #include "stor-layout.h" 96 #include "cfgrtl.h" 97 #include "cfgcleanup.h" 98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ 99 #include "explow.h" 100 #include "insn-attr.h" 101 #include "rtlhooks-def.h" 102 #include "params.h" 103 #include "tree-pass.h" 104 #include "valtrack.h" 105 #include "rtl-iter.h" 106 #include "print-rtl.h" 107 108 /* Number of attempts to combine instructions in this function. */ 109 110 static int combine_attempts; 111 112 /* Number of attempts that got as far as substitution in this function. */ 113 114 static int combine_merges; 115 116 /* Number of instructions combined with added SETs in this function. */ 117 118 static int combine_extras; 119 120 /* Number of instructions combined in this function. */ 121 122 static int combine_successes; 123 124 /* Totals over entire compilation. */ 125 126 static int total_attempts, total_merges, total_extras, total_successes; 127 128 /* combine_instructions may try to replace the right hand side of the 129 second instruction with the value of an associated REG_EQUAL note 130 before throwing it at try_combine. That is problematic when there 131 is a REG_DEAD note for a register used in the old right hand side 132 and can cause distribute_notes to do wrong things. This is the 133 second instruction if it has been so modified, null otherwise. */ 134 135 static rtx_insn *i2mod; 136 137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */ 138 139 static rtx i2mod_old_rhs; 140 141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */ 142 143 static rtx i2mod_new_rhs; 144 145 struct reg_stat_type { 146 /* Record last point of death of (hard or pseudo) register n. */ 147 rtx_insn *last_death; 148 149 /* Record last point of modification of (hard or pseudo) register n. */ 150 rtx_insn *last_set; 151 152 /* The next group of fields allows the recording of the last value assigned 153 to (hard or pseudo) register n. We use this information to see if an 154 operation being processed is redundant given a prior operation performed 155 on the register. For example, an `and' with a constant is redundant if 156 all the zero bits are already known to be turned off. 157 158 We use an approach similar to that used by cse, but change it in the 159 following ways: 160 161 (1) We do not want to reinitialize at each label. 162 (2) It is useful, but not critical, to know the actual value assigned 163 to a register. Often just its form is helpful. 164 165 Therefore, we maintain the following fields: 166 167 last_set_value the last value assigned 168 last_set_label records the value of label_tick when the 169 register was assigned 170 last_set_table_tick records the value of label_tick when a 171 value using the register is assigned 172 last_set_invalid set to nonzero when it is not valid 173 to use the value of this register in some 174 register's value 175 176 To understand the usage of these tables, it is important to understand 177 the distinction between the value in last_set_value being valid and 178 the register being validly contained in some other expression in the 179 table. 180 181 (The next two parameters are out of date). 182 183 reg_stat[i].last_set_value is valid if it is nonzero, and either 184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick. 185 186 Register I may validly appear in any expression returned for the value 187 of another register if reg_n_sets[i] is 1. It may also appear in the 188 value for register J if reg_stat[j].last_set_invalid is zero, or 189 reg_stat[i].last_set_label < reg_stat[j].last_set_label. 190 191 If an expression is found in the table containing a register which may 192 not validly appear in an expression, the register is replaced by 193 something that won't match, (clobber (const_int 0)). */ 194 195 /* Record last value assigned to (hard or pseudo) register n. */ 196 197 rtx last_set_value; 198 199 /* Record the value of label_tick when an expression involving register n 200 is placed in last_set_value. */ 201 202 int last_set_table_tick; 203 204 /* Record the value of label_tick when the value for register n is placed in 205 last_set_value. */ 206 207 int last_set_label; 208 209 /* These fields are maintained in parallel with last_set_value and are 210 used to store the mode in which the register was last set, the bits 211 that were known to be zero when it was last set, and the number of 212 sign bits copies it was known to have when it was last set. */ 213 214 unsigned HOST_WIDE_INT last_set_nonzero_bits; 215 char last_set_sign_bit_copies; 216 ENUM_BITFIELD(machine_mode) last_set_mode : 8; 217 218 /* Set nonzero if references to register n in expressions should not be 219 used. last_set_invalid is set nonzero when this register is being 220 assigned to and last_set_table_tick == label_tick. */ 221 222 char last_set_invalid; 223 224 /* Some registers that are set more than once and used in more than one 225 basic block are nevertheless always set in similar ways. For example, 226 a QImode register may be loaded from memory in two places on a machine 227 where byte loads zero extend. 228 229 We record in the following fields if a register has some leading bits 230 that are always equal to the sign bit, and what we know about the 231 nonzero bits of a register, specifically which bits are known to be 232 zero. 233 234 If an entry is zero, it means that we don't know anything special. */ 235 236 unsigned char sign_bit_copies; 237 238 unsigned HOST_WIDE_INT nonzero_bits; 239 240 /* Record the value of the label_tick when the last truncation 241 happened. The field truncated_to_mode is only valid if 242 truncation_label == label_tick. */ 243 244 int truncation_label; 245 246 /* Record the last truncation seen for this register. If truncation 247 is not a nop to this mode we might be able to save an explicit 248 truncation if we know that value already contains a truncated 249 value. */ 250 251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8; 252 }; 253 254 255 static vec<reg_stat_type> reg_stat; 256 257 /* One plus the highest pseudo for which we track REG_N_SETS. 258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once, 259 but during combine_split_insns new pseudos can be created. As we don't have 260 updated DF information in that case, it is hard to initialize the array 261 after growing. The combiner only cares about REG_N_SETS (regno) == 1, 262 so instead of growing the arrays, just assume all newly created pseudos 263 during combine might be set multiple times. */ 264 265 static unsigned int reg_n_sets_max; 266 267 /* Record the luid of the last insn that invalidated memory 268 (anything that writes memory, and subroutine calls, but not pushes). */ 269 270 static int mem_last_set; 271 272 /* Record the luid of the last CALL_INSN 273 so we can tell whether a potential combination crosses any calls. */ 274 275 static int last_call_luid; 276 277 /* When `subst' is called, this is the insn that is being modified 278 (by combining in a previous insn). The PATTERN of this insn 279 is still the old pattern partially modified and it should not be 280 looked at, but this may be used to examine the successors of the insn 281 to judge whether a simplification is valid. */ 282 283 static rtx_insn *subst_insn; 284 285 /* This is the lowest LUID that `subst' is currently dealing with. 286 get_last_value will not return a value if the register was set at or 287 after this LUID. If not for this mechanism, we could get confused if 288 I2 or I1 in try_combine were an insn that used the old value of a register 289 to obtain a new value. In that case, we might erroneously get the 290 new value of the register when we wanted the old one. */ 291 292 static int subst_low_luid; 293 294 /* This contains any hard registers that are used in newpat; reg_dead_at_p 295 must consider all these registers to be always live. */ 296 297 static HARD_REG_SET newpat_used_regs; 298 299 /* This is an insn to which a LOG_LINKS entry has been added. If this 300 insn is the earlier than I2 or I3, combine should rescan starting at 301 that location. */ 302 303 static rtx_insn *added_links_insn; 304 305 /* Basic block in which we are performing combines. */ 306 static basic_block this_basic_block; 307 static bool optimize_this_for_speed_p; 308 309 310 /* Length of the currently allocated uid_insn_cost array. */ 311 312 static int max_uid_known; 313 314 /* The following array records the insn_rtx_cost for every insn 315 in the instruction stream. */ 316 317 static int *uid_insn_cost; 318 319 /* The following array records the LOG_LINKS for every insn in the 320 instruction stream as struct insn_link pointers. */ 321 322 struct insn_link { 323 rtx_insn *insn; 324 unsigned int regno; 325 struct insn_link *next; 326 }; 327 328 static struct insn_link **uid_log_links; 329 330 static inline int 331 insn_uid_check (const_rtx insn) 332 { 333 int uid = INSN_UID (insn); 334 gcc_checking_assert (uid <= max_uid_known); 335 return uid; 336 } 337 338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)]) 339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)]) 340 341 #define FOR_EACH_LOG_LINK(L, INSN) \ 342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next) 343 344 /* Links for LOG_LINKS are allocated from this obstack. */ 345 346 static struct obstack insn_link_obstack; 347 348 /* Allocate a link. */ 349 350 static inline struct insn_link * 351 alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next) 352 { 353 struct insn_link *l 354 = (struct insn_link *) obstack_alloc (&insn_link_obstack, 355 sizeof (struct insn_link)); 356 l->insn = insn; 357 l->regno = regno; 358 l->next = next; 359 return l; 360 } 361 362 /* Incremented for each basic block. */ 363 364 static int label_tick; 365 366 /* Reset to label_tick for each extended basic block in scanning order. */ 367 368 static int label_tick_ebb_start; 369 370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the 371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ 372 373 static machine_mode nonzero_bits_mode; 374 375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can 376 be safely used. It is zero while computing them and after combine has 377 completed. This former test prevents propagating values based on 378 previously set values, which can be incorrect if a variable is modified 379 in a loop. */ 380 381 static int nonzero_sign_valid; 382 383 384 /* Record one modification to rtl structure 385 to be undone by storing old_contents into *where. */ 386 387 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS }; 388 389 struct undo 390 { 391 struct undo *next; 392 enum undo_kind kind; 393 union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents; 394 union { rtx *r; int *i; struct insn_link **l; } where; 395 }; 396 397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them. 398 num_undo says how many are currently recorded. 399 400 other_insn is nonzero if we have modified some other insn in the process 401 of working on subst_insn. It must be verified too. */ 402 403 struct undobuf 404 { 405 struct undo *undos; 406 struct undo *frees; 407 rtx_insn *other_insn; 408 }; 409 410 static struct undobuf undobuf; 411 412 /* Number of times the pseudo being substituted for 413 was found and replaced. */ 414 415 static int n_occurrences; 416 417 static rtx reg_nonzero_bits_for_combine (const_rtx, machine_mode, const_rtx, 418 machine_mode, 419 unsigned HOST_WIDE_INT, 420 unsigned HOST_WIDE_INT *); 421 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, machine_mode, const_rtx, 422 machine_mode, 423 unsigned int, unsigned int *); 424 static void do_SUBST (rtx *, rtx); 425 static void do_SUBST_INT (int *, int); 426 static void init_reg_last (void); 427 static void setup_incoming_promotions (rtx_insn *); 428 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *); 429 static int cant_combine_insn_p (rtx_insn *); 430 static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *, 431 rtx_insn *, rtx_insn *, rtx *, rtx *); 432 static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *); 433 static int contains_muldiv (rtx); 434 static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *, 435 int *, rtx_insn *); 436 static void undo_all (void); 437 static void undo_commit (void); 438 static rtx *find_split_point (rtx *, rtx_insn *, bool); 439 static rtx subst (rtx, rtx, rtx, int, int, int); 440 static rtx combine_simplify_rtx (rtx, machine_mode, int, int); 441 static rtx simplify_if_then_else (rtx); 442 static rtx simplify_set (rtx); 443 static rtx simplify_logical (rtx); 444 static rtx expand_compound_operation (rtx); 445 static const_rtx expand_field_assignment (const_rtx); 446 static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, 447 rtx, unsigned HOST_WIDE_INT, int, int, int); 448 static rtx extract_left_shift (rtx, int); 449 static int get_pos_from_mask (unsigned HOST_WIDE_INT, 450 unsigned HOST_WIDE_INT *); 451 static rtx canon_reg_for_combine (rtx, rtx); 452 static rtx force_to_mode (rtx, machine_mode, 453 unsigned HOST_WIDE_INT, int); 454 static rtx if_then_else_cond (rtx, rtx *, rtx *); 455 static rtx known_cond (rtx, enum rtx_code, rtx, rtx); 456 static int rtx_equal_for_field_assignment_p (rtx, rtx, bool = false); 457 static rtx make_field_assignment (rtx); 458 static rtx apply_distributive_law (rtx); 459 static rtx distribute_and_simplify_rtx (rtx, int); 460 static rtx simplify_and_const_int_1 (machine_mode, rtx, 461 unsigned HOST_WIDE_INT); 462 static rtx simplify_and_const_int (rtx, machine_mode, rtx, 463 unsigned HOST_WIDE_INT); 464 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code, 465 HOST_WIDE_INT, machine_mode, int *); 466 static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int); 467 static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx, 468 int); 469 static int recog_for_combine (rtx *, rtx_insn *, rtx *); 470 static rtx gen_lowpart_for_combine (machine_mode, rtx); 471 static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode, 472 rtx, rtx *); 473 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *); 474 static void update_table_tick (rtx); 475 static void record_value_for_reg (rtx, rtx_insn *, rtx); 476 static void check_promoted_subreg (rtx_insn *, rtx); 477 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *); 478 static void record_dead_and_set_regs (rtx_insn *); 479 static int get_last_value_validate (rtx *, rtx_insn *, int, int); 480 static rtx get_last_value (const_rtx); 481 static int use_crosses_set_p (const_rtx, int); 482 static void reg_dead_at_p_1 (rtx, const_rtx, void *); 483 static int reg_dead_at_p (rtx, rtx_insn *); 484 static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *); 485 static int reg_bitfield_target_p (rtx, rtx); 486 static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx); 487 static void distribute_links (struct insn_link *); 488 static void mark_used_regs_combine (rtx); 489 static void record_promoted_value (rtx_insn *, rtx); 490 static bool unmentioned_reg_p (rtx, rtx); 491 static void record_truncated_values (rtx *, void *); 492 static bool reg_truncated_to_mode (machine_mode, const_rtx); 493 static rtx gen_lowpart_or_truncate (machine_mode, rtx); 494 495 496 /* It is not safe to use ordinary gen_lowpart in combine. 497 See comments in gen_lowpart_for_combine. */ 498 #undef RTL_HOOKS_GEN_LOWPART 499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine 500 501 /* Our implementation of gen_lowpart never emits a new pseudo. */ 502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT 503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine 504 505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS 506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine 507 508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES 509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine 510 511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE 512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode 513 514 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER; 515 516 517 /* Convenience wrapper for the canonicalize_comparison target hook. 518 Target hooks cannot use enum rtx_code. */ 519 static inline void 520 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1, 521 bool op0_preserve_value) 522 { 523 int code_int = (int)*code; 524 targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value); 525 *code = (enum rtx_code)code_int; 526 } 527 528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if 529 PATTERN can not be split. Otherwise, it returns an insn sequence. 530 This is a wrapper around split_insns which ensures that the 531 reg_stat vector is made larger if the splitter creates a new 532 register. */ 533 534 static rtx_insn * 535 combine_split_insns (rtx pattern, rtx_insn *insn) 536 { 537 rtx_insn *ret; 538 unsigned int nregs; 539 540 ret = split_insns (pattern, insn); 541 nregs = max_reg_num (); 542 if (nregs > reg_stat.length ()) 543 reg_stat.safe_grow_cleared (nregs); 544 return ret; 545 } 546 547 /* This is used by find_single_use to locate an rtx in LOC that 548 contains exactly one use of DEST, which is typically either a REG 549 or CC0. It returns a pointer to the innermost rtx expression 550 containing DEST. Appearances of DEST that are being used to 551 totally replace it are not counted. */ 552 553 static rtx * 554 find_single_use_1 (rtx dest, rtx *loc) 555 { 556 rtx x = *loc; 557 enum rtx_code code = GET_CODE (x); 558 rtx *result = NULL; 559 rtx *this_result; 560 int i; 561 const char *fmt; 562 563 switch (code) 564 { 565 case CONST: 566 case LABEL_REF: 567 case SYMBOL_REF: 568 CASE_CONST_ANY: 569 case CLOBBER: 570 return 0; 571 572 case SET: 573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG 574 of a REG that occupies all of the REG, the insn uses DEST if 575 it is mentioned in the destination or the source. Otherwise, we 576 need just check the source. */ 577 if (GET_CODE (SET_DEST (x)) != CC0 578 && GET_CODE (SET_DEST (x)) != PC 579 && !REG_P (SET_DEST (x)) 580 && ! (GET_CODE (SET_DEST (x)) == SUBREG 581 && REG_P (SUBREG_REG (SET_DEST (x))) 582 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 583 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 584 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 585 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) 586 break; 587 588 return find_single_use_1 (dest, &SET_SRC (x)); 589 590 case MEM: 591 case SUBREG: 592 return find_single_use_1 (dest, &XEXP (x, 0)); 593 594 default: 595 break; 596 } 597 598 /* If it wasn't one of the common cases above, check each expression and 599 vector of this code. Look for a unique usage of DEST. */ 600 601 fmt = GET_RTX_FORMAT (code); 602 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 603 { 604 if (fmt[i] == 'e') 605 { 606 if (dest == XEXP (x, i) 607 || (REG_P (dest) && REG_P (XEXP (x, i)) 608 && REGNO (dest) == REGNO (XEXP (x, i)))) 609 this_result = loc; 610 else 611 this_result = find_single_use_1 (dest, &XEXP (x, i)); 612 613 if (result == NULL) 614 result = this_result; 615 else if (this_result) 616 /* Duplicate usage. */ 617 return NULL; 618 } 619 else if (fmt[i] == 'E') 620 { 621 int j; 622 623 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 624 { 625 if (XVECEXP (x, i, j) == dest 626 || (REG_P (dest) 627 && REG_P (XVECEXP (x, i, j)) 628 && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) 629 this_result = loc; 630 else 631 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); 632 633 if (result == NULL) 634 result = this_result; 635 else if (this_result) 636 return NULL; 637 } 638 } 639 } 640 641 return result; 642 } 643 644 645 /* See if DEST, produced in INSN, is used only a single time in the 646 sequel. If so, return a pointer to the innermost rtx expression in which 647 it is used. 648 649 If PLOC is nonzero, *PLOC is set to the insn containing the single use. 650 651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't 652 care about REG_DEAD notes or LOG_LINKS. 653 654 Otherwise, we find the single use by finding an insn that has a 655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is 656 only referenced once in that insn, we know that it must be the first 657 and last insn referencing DEST. */ 658 659 static rtx * 660 find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc) 661 { 662 basic_block bb; 663 rtx_insn *next; 664 rtx *result; 665 struct insn_link *link; 666 667 if (dest == cc0_rtx) 668 { 669 next = NEXT_INSN (insn); 670 if (next == 0 671 || (!NONJUMP_INSN_P (next) && !JUMP_P (next))) 672 return 0; 673 674 result = find_single_use_1 (dest, &PATTERN (next)); 675 if (result && ploc) 676 *ploc = next; 677 return result; 678 } 679 680 if (!REG_P (dest)) 681 return 0; 682 683 bb = BLOCK_FOR_INSN (insn); 684 for (next = NEXT_INSN (insn); 685 next && BLOCK_FOR_INSN (next) == bb; 686 next = NEXT_INSN (next)) 687 if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest)) 688 { 689 FOR_EACH_LOG_LINK (link, next) 690 if (link->insn == insn && link->regno == REGNO (dest)) 691 break; 692 693 if (link) 694 { 695 result = find_single_use_1 (dest, &PATTERN (next)); 696 if (ploc) 697 *ploc = next; 698 return result; 699 } 700 } 701 702 return 0; 703 } 704 705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some 706 insn. The substitution can be undone by undo_all. If INTO is already 707 set to NEWVAL, do not record this change. Because computing NEWVAL might 708 also call SUBST, we have to compute it before we put anything into 709 the undo table. */ 710 711 static void 712 do_SUBST (rtx *into, rtx newval) 713 { 714 struct undo *buf; 715 rtx oldval = *into; 716 717 if (oldval == newval) 718 return; 719 720 /* We'd like to catch as many invalid transformations here as 721 possible. Unfortunately, there are way too many mode changes 722 that are perfectly valid, so we'd waste too much effort for 723 little gain doing the checks here. Focus on catching invalid 724 transformations involving integer constants. */ 725 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT 726 && CONST_INT_P (newval)) 727 { 728 /* Sanity check that we're replacing oldval with a CONST_INT 729 that is a valid sign-extension for the original mode. */ 730 gcc_assert (INTVAL (newval) 731 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval))); 732 733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a 734 CONST_INT is not valid, because after the replacement, the 735 original mode would be gone. Unfortunately, we can't tell 736 when do_SUBST is called to replace the operand thereof, so we 737 perform this test on oldval instead, checking whether an 738 invalid replacement took place before we got here. */ 739 gcc_assert (!(GET_CODE (oldval) == SUBREG 740 && CONST_INT_P (SUBREG_REG (oldval)))); 741 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND 742 && CONST_INT_P (XEXP (oldval, 0)))); 743 } 744 745 if (undobuf.frees) 746 buf = undobuf.frees, undobuf.frees = buf->next; 747 else 748 buf = XNEW (struct undo); 749 750 buf->kind = UNDO_RTX; 751 buf->where.r = into; 752 buf->old_contents.r = oldval; 753 *into = newval; 754 755 buf->next = undobuf.undos, undobuf.undos = buf; 756 } 757 758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL)) 759 760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution 761 for the value of a HOST_WIDE_INT value (including CONST_INT) is 762 not safe. */ 763 764 static void 765 do_SUBST_INT (int *into, int newval) 766 { 767 struct undo *buf; 768 int oldval = *into; 769 770 if (oldval == newval) 771 return; 772 773 if (undobuf.frees) 774 buf = undobuf.frees, undobuf.frees = buf->next; 775 else 776 buf = XNEW (struct undo); 777 778 buf->kind = UNDO_INT; 779 buf->where.i = into; 780 buf->old_contents.i = oldval; 781 *into = newval; 782 783 buf->next = undobuf.undos, undobuf.undos = buf; 784 } 785 786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL)) 787 788 /* Similar to SUBST, but just substitute the mode. This is used when 789 changing the mode of a pseudo-register, so that any other 790 references to the entry in the regno_reg_rtx array will change as 791 well. */ 792 793 static void 794 do_SUBST_MODE (rtx *into, machine_mode newval) 795 { 796 struct undo *buf; 797 machine_mode oldval = GET_MODE (*into); 798 799 if (oldval == newval) 800 return; 801 802 if (undobuf.frees) 803 buf = undobuf.frees, undobuf.frees = buf->next; 804 else 805 buf = XNEW (struct undo); 806 807 buf->kind = UNDO_MODE; 808 buf->where.r = into; 809 buf->old_contents.m = oldval; 810 adjust_reg_mode (*into, newval); 811 812 buf->next = undobuf.undos, undobuf.undos = buf; 813 } 814 815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL)) 816 817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */ 818 819 static void 820 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval) 821 { 822 struct undo *buf; 823 struct insn_link * oldval = *into; 824 825 if (oldval == newval) 826 return; 827 828 if (undobuf.frees) 829 buf = undobuf.frees, undobuf.frees = buf->next; 830 else 831 buf = XNEW (struct undo); 832 833 buf->kind = UNDO_LINKS; 834 buf->where.l = into; 835 buf->old_contents.l = oldval; 836 *into = newval; 837 838 buf->next = undobuf.undos, undobuf.undos = buf; 839 } 840 841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval) 842 843 /* Subroutine of try_combine. Determine whether the replacement patterns 844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost 845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note 846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and 847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost 848 of all the instructions can be estimated and the replacements are more 849 expensive than the original sequence. */ 850 851 static bool 852 combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3, 853 rtx newpat, rtx newi2pat, rtx newotherpat) 854 { 855 int i0_cost, i1_cost, i2_cost, i3_cost; 856 int new_i2_cost, new_i3_cost; 857 int old_cost, new_cost; 858 859 /* Lookup the original insn_rtx_costs. */ 860 i2_cost = INSN_COST (i2); 861 i3_cost = INSN_COST (i3); 862 863 if (i1) 864 { 865 i1_cost = INSN_COST (i1); 866 if (i0) 867 { 868 i0_cost = INSN_COST (i0); 869 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0 870 ? i0_cost + i1_cost + i2_cost + i3_cost : 0); 871 } 872 else 873 { 874 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0 875 ? i1_cost + i2_cost + i3_cost : 0); 876 i0_cost = 0; 877 } 878 } 879 else 880 { 881 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0; 882 i1_cost = i0_cost = 0; 883 } 884 885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice; 886 correct that. */ 887 if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2)) 888 old_cost -= i1_cost; 889 890 891 /* Calculate the replacement insn_rtx_costs. */ 892 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p); 893 if (newi2pat) 894 { 895 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p); 896 new_cost = (new_i2_cost > 0 && new_i3_cost > 0) 897 ? new_i2_cost + new_i3_cost : 0; 898 } 899 else 900 { 901 new_cost = new_i3_cost; 902 new_i2_cost = 0; 903 } 904 905 if (undobuf.other_insn) 906 { 907 int old_other_cost, new_other_cost; 908 909 old_other_cost = INSN_COST (undobuf.other_insn); 910 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p); 911 if (old_other_cost > 0 && new_other_cost > 0) 912 { 913 old_cost += old_other_cost; 914 new_cost += new_other_cost; 915 } 916 else 917 old_cost = 0; 918 } 919 920 /* Disallow this combination if both new_cost and old_cost are greater than 921 zero, and new_cost is greater than old cost. */ 922 int reject = old_cost > 0 && new_cost > old_cost; 923 924 if (dump_file) 925 { 926 fprintf (dump_file, "%s combination of insns ", 927 reject ? "rejecting" : "allowing"); 928 if (i0) 929 fprintf (dump_file, "%d, ", INSN_UID (i0)); 930 if (i1 && INSN_UID (i1) != INSN_UID (i2)) 931 fprintf (dump_file, "%d, ", INSN_UID (i1)); 932 fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3)); 933 934 fprintf (dump_file, "original costs "); 935 if (i0) 936 fprintf (dump_file, "%d + ", i0_cost); 937 if (i1 && INSN_UID (i1) != INSN_UID (i2)) 938 fprintf (dump_file, "%d + ", i1_cost); 939 fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost); 940 941 if (newi2pat) 942 fprintf (dump_file, "replacement costs %d + %d = %d\n", 943 new_i2_cost, new_i3_cost, new_cost); 944 else 945 fprintf (dump_file, "replacement cost %d\n", new_cost); 946 } 947 948 if (reject) 949 return false; 950 951 /* Update the uid_insn_cost array with the replacement costs. */ 952 INSN_COST (i2) = new_i2_cost; 953 INSN_COST (i3) = new_i3_cost; 954 if (i1) 955 { 956 INSN_COST (i1) = 0; 957 if (i0) 958 INSN_COST (i0) = 0; 959 } 960 961 return true; 962 } 963 964 965 /* Delete any insns that copy a register to itself. */ 966 967 static void 968 delete_noop_moves (void) 969 { 970 rtx_insn *insn, *next; 971 basic_block bb; 972 973 FOR_EACH_BB_FN (bb, cfun) 974 { 975 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next) 976 { 977 next = NEXT_INSN (insn); 978 if (INSN_P (insn) && noop_move_p (insn)) 979 { 980 if (dump_file) 981 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn)); 982 983 delete_insn_and_edges (insn); 984 } 985 } 986 } 987 } 988 989 990 /* Return false if we do not want to (or cannot) combine DEF. */ 991 static bool 992 can_combine_def_p (df_ref def) 993 { 994 /* Do not consider if it is pre/post modification in MEM. */ 995 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY) 996 return false; 997 998 unsigned int regno = DF_REF_REGNO (def); 999 1000 /* Do not combine frame pointer adjustments. */ 1001 if ((regno == FRAME_POINTER_REGNUM 1002 && (!reload_completed || frame_pointer_needed)) 1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER 1004 && regno == HARD_FRAME_POINTER_REGNUM 1005 && (!reload_completed || frame_pointer_needed)) 1006 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 1007 && regno == ARG_POINTER_REGNUM && fixed_regs[regno])) 1008 return false; 1009 1010 return true; 1011 } 1012 1013 /* Return false if we do not want to (or cannot) combine USE. */ 1014 static bool 1015 can_combine_use_p (df_ref use) 1016 { 1017 /* Do not consider the usage of the stack pointer by function call. */ 1018 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE) 1019 return false; 1020 1021 return true; 1022 } 1023 1024 /* Fill in log links field for all insns. */ 1025 1026 static void 1027 create_log_links (void) 1028 { 1029 basic_block bb; 1030 rtx_insn **next_use; 1031 rtx_insn *insn; 1032 df_ref def, use; 1033 1034 next_use = XCNEWVEC (rtx_insn *, max_reg_num ()); 1035 1036 /* Pass through each block from the end, recording the uses of each 1037 register and establishing log links when def is encountered. 1038 Note that we do not clear next_use array in order to save time, 1039 so we have to test whether the use is in the same basic block as def. 1040 1041 There are a few cases below when we do not consider the definition or 1042 usage -- these are taken from original flow.c did. Don't ask me why it is 1043 done this way; I don't know and if it works, I don't want to know. */ 1044 1045 FOR_EACH_BB_FN (bb, cfun) 1046 { 1047 FOR_BB_INSNS_REVERSE (bb, insn) 1048 { 1049 if (!NONDEBUG_INSN_P (insn)) 1050 continue; 1051 1052 /* Log links are created only once. */ 1053 gcc_assert (!LOG_LINKS (insn)); 1054 1055 FOR_EACH_INSN_DEF (def, insn) 1056 { 1057 unsigned int regno = DF_REF_REGNO (def); 1058 rtx_insn *use_insn; 1059 1060 if (!next_use[regno]) 1061 continue; 1062 1063 if (!can_combine_def_p (def)) 1064 continue; 1065 1066 use_insn = next_use[regno]; 1067 next_use[regno] = NULL; 1068 1069 if (BLOCK_FOR_INSN (use_insn) != bb) 1070 continue; 1071 1072 /* flow.c claimed: 1073 1074 We don't build a LOG_LINK for hard registers contained 1075 in ASM_OPERANDs. If these registers get replaced, 1076 we might wind up changing the semantics of the insn, 1077 even if reload can make what appear to be valid 1078 assignments later. */ 1079 if (regno < FIRST_PSEUDO_REGISTER 1080 && asm_noperands (PATTERN (use_insn)) >= 0) 1081 continue; 1082 1083 /* Don't add duplicate links between instructions. */ 1084 struct insn_link *links; 1085 FOR_EACH_LOG_LINK (links, use_insn) 1086 if (insn == links->insn && regno == links->regno) 1087 break; 1088 1089 if (!links) 1090 LOG_LINKS (use_insn) 1091 = alloc_insn_link (insn, regno, LOG_LINKS (use_insn)); 1092 } 1093 1094 FOR_EACH_INSN_USE (use, insn) 1095 if (can_combine_use_p (use)) 1096 next_use[DF_REF_REGNO (use)] = insn; 1097 } 1098 } 1099 1100 free (next_use); 1101 } 1102 1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return 1104 true if we found a LOG_LINK that proves that A feeds B. This only works 1105 if there are no instructions between A and B which could have a link 1106 depending on A, since in that case we would not record a link for B. 1107 We also check the implicit dependency created by a cc0 setter/user 1108 pair. */ 1109 1110 static bool 1111 insn_a_feeds_b (rtx_insn *a, rtx_insn *b) 1112 { 1113 struct insn_link *links; 1114 FOR_EACH_LOG_LINK (links, b) 1115 if (links->insn == a) 1116 return true; 1117 if (HAVE_cc0 && sets_cc0_p (a)) 1118 return true; 1119 return false; 1120 } 1121 1122 /* Main entry point for combiner. F is the first insn of the function. 1123 NREGS is the first unused pseudo-reg number. 1124 1125 Return nonzero if the combiner has turned an indirect jump 1126 instruction into a direct jump. */ 1127 static int 1128 combine_instructions (rtx_insn *f, unsigned int nregs) 1129 { 1130 rtx_insn *insn, *next; 1131 rtx_insn *prev; 1132 struct insn_link *links, *nextlinks; 1133 rtx_insn *first; 1134 basic_block last_bb; 1135 1136 int new_direct_jump_p = 0; 1137 1138 for (first = f; first && !NONDEBUG_INSN_P (first); ) 1139 first = NEXT_INSN (first); 1140 if (!first) 1141 return 0; 1142 1143 combine_attempts = 0; 1144 combine_merges = 0; 1145 combine_extras = 0; 1146 combine_successes = 0; 1147 1148 rtl_hooks = combine_rtl_hooks; 1149 1150 reg_stat.safe_grow_cleared (nregs); 1151 1152 init_recog_no_volatile (); 1153 1154 /* Allocate array for insn info. */ 1155 max_uid_known = get_max_uid (); 1156 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1); 1157 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1); 1158 gcc_obstack_init (&insn_link_obstack); 1159 1160 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); 1161 1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause 1163 problems when, for example, we have j <<= 1 in a loop. */ 1164 1165 nonzero_sign_valid = 0; 1166 label_tick = label_tick_ebb_start = 1; 1167 1168 /* Scan all SETs and see if we can deduce anything about what 1169 bits are known to be zero for some registers and how many copies 1170 of the sign bit are known to exist for those registers. 1171 1172 Also set any known values so that we can use it while searching 1173 for what bits are known to be set. */ 1174 1175 setup_incoming_promotions (first); 1176 /* Allow the entry block and the first block to fall into the same EBB. 1177 Conceptually the incoming promotions are assigned to the entry block. */ 1178 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun); 1179 1180 create_log_links (); 1181 FOR_EACH_BB_FN (this_basic_block, cfun) 1182 { 1183 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); 1184 last_call_luid = 0; 1185 mem_last_set = -1; 1186 1187 label_tick++; 1188 if (!single_pred_p (this_basic_block) 1189 || single_pred (this_basic_block) != last_bb) 1190 label_tick_ebb_start = label_tick; 1191 last_bb = this_basic_block; 1192 1193 FOR_BB_INSNS (this_basic_block, insn) 1194 if (INSN_P (insn) && BLOCK_FOR_INSN (insn)) 1195 { 1196 rtx links; 1197 1198 subst_low_luid = DF_INSN_LUID (insn); 1199 subst_insn = insn; 1200 1201 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, 1202 insn); 1203 record_dead_and_set_regs (insn); 1204 1205 if (AUTO_INC_DEC) 1206 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 1207 if (REG_NOTE_KIND (links) == REG_INC) 1208 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, 1209 insn); 1210 1211 /* Record the current insn_rtx_cost of this instruction. */ 1212 if (NONJUMP_INSN_P (insn)) 1213 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn), 1214 optimize_this_for_speed_p); 1215 if (dump_file) 1216 fprintf (dump_file, "insn_cost %d: %d\n", 1217 INSN_UID (insn), INSN_COST (insn)); 1218 } 1219 } 1220 1221 nonzero_sign_valid = 1; 1222 1223 /* Now scan all the insns in forward order. */ 1224 label_tick = label_tick_ebb_start = 1; 1225 init_reg_last (); 1226 setup_incoming_promotions (first); 1227 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun); 1228 int max_combine = PARAM_VALUE (PARAM_MAX_COMBINE_INSNS); 1229 1230 FOR_EACH_BB_FN (this_basic_block, cfun) 1231 { 1232 rtx_insn *last_combined_insn = NULL; 1233 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); 1234 last_call_luid = 0; 1235 mem_last_set = -1; 1236 1237 label_tick++; 1238 if (!single_pred_p (this_basic_block) 1239 || single_pred (this_basic_block) != last_bb) 1240 label_tick_ebb_start = label_tick; 1241 last_bb = this_basic_block; 1242 1243 rtl_profile_for_bb (this_basic_block); 1244 for (insn = BB_HEAD (this_basic_block); 1245 insn != NEXT_INSN (BB_END (this_basic_block)); 1246 insn = next ? next : NEXT_INSN (insn)) 1247 { 1248 next = 0; 1249 if (!NONDEBUG_INSN_P (insn)) 1250 continue; 1251 1252 while (last_combined_insn 1253 && (!NONDEBUG_INSN_P (last_combined_insn) 1254 || last_combined_insn->deleted ())) 1255 last_combined_insn = PREV_INSN (last_combined_insn); 1256 if (last_combined_insn == NULL_RTX 1257 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block 1258 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn)) 1259 last_combined_insn = insn; 1260 1261 /* See if we know about function return values before this 1262 insn based upon SUBREG flags. */ 1263 check_promoted_subreg (insn, PATTERN (insn)); 1264 1265 /* See if we can find hardregs and subreg of pseudos in 1266 narrower modes. This could help turning TRUNCATEs 1267 into SUBREGs. */ 1268 note_uses (&PATTERN (insn), record_truncated_values, NULL); 1269 1270 /* Try this insn with each insn it links back to. */ 1271 1272 FOR_EACH_LOG_LINK (links, insn) 1273 if ((next = try_combine (insn, links->insn, NULL, 1274 NULL, &new_direct_jump_p, 1275 last_combined_insn)) != 0) 1276 { 1277 statistics_counter_event (cfun, "two-insn combine", 1); 1278 goto retry; 1279 } 1280 1281 /* Try each sequence of three linked insns ending with this one. */ 1282 1283 if (max_combine >= 3) 1284 FOR_EACH_LOG_LINK (links, insn) 1285 { 1286 rtx_insn *link = links->insn; 1287 1288 /* If the linked insn has been replaced by a note, then there 1289 is no point in pursuing this chain any further. */ 1290 if (NOTE_P (link)) 1291 continue; 1292 1293 FOR_EACH_LOG_LINK (nextlinks, link) 1294 if ((next = try_combine (insn, link, nextlinks->insn, 1295 NULL, &new_direct_jump_p, 1296 last_combined_insn)) != 0) 1297 { 1298 statistics_counter_event (cfun, "three-insn combine", 1); 1299 goto retry; 1300 } 1301 } 1302 1303 /* Try to combine a jump insn that uses CC0 1304 with a preceding insn that sets CC0, and maybe with its 1305 logical predecessor as well. 1306 This is how we make decrement-and-branch insns. 1307 We need this special code because data flow connections 1308 via CC0 do not get entered in LOG_LINKS. */ 1309 1310 if (HAVE_cc0 1311 && JUMP_P (insn) 1312 && (prev = prev_nonnote_insn (insn)) != 0 1313 && NONJUMP_INSN_P (prev) 1314 && sets_cc0_p (PATTERN (prev))) 1315 { 1316 if ((next = try_combine (insn, prev, NULL, NULL, 1317 &new_direct_jump_p, 1318 last_combined_insn)) != 0) 1319 goto retry; 1320 1321 FOR_EACH_LOG_LINK (nextlinks, prev) 1322 if ((next = try_combine (insn, prev, nextlinks->insn, 1323 NULL, &new_direct_jump_p, 1324 last_combined_insn)) != 0) 1325 goto retry; 1326 } 1327 1328 /* Do the same for an insn that explicitly references CC0. */ 1329 if (HAVE_cc0 && NONJUMP_INSN_P (insn) 1330 && (prev = prev_nonnote_insn (insn)) != 0 1331 && NONJUMP_INSN_P (prev) 1332 && sets_cc0_p (PATTERN (prev)) 1333 && GET_CODE (PATTERN (insn)) == SET 1334 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) 1335 { 1336 if ((next = try_combine (insn, prev, NULL, NULL, 1337 &new_direct_jump_p, 1338 last_combined_insn)) != 0) 1339 goto retry; 1340 1341 FOR_EACH_LOG_LINK (nextlinks, prev) 1342 if ((next = try_combine (insn, prev, nextlinks->insn, 1343 NULL, &new_direct_jump_p, 1344 last_combined_insn)) != 0) 1345 goto retry; 1346 } 1347 1348 /* Finally, see if any of the insns that this insn links to 1349 explicitly references CC0. If so, try this insn, that insn, 1350 and its predecessor if it sets CC0. */ 1351 if (HAVE_cc0) 1352 { 1353 FOR_EACH_LOG_LINK (links, insn) 1354 if (NONJUMP_INSN_P (links->insn) 1355 && GET_CODE (PATTERN (links->insn)) == SET 1356 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn))) 1357 && (prev = prev_nonnote_insn (links->insn)) != 0 1358 && NONJUMP_INSN_P (prev) 1359 && sets_cc0_p (PATTERN (prev)) 1360 && (next = try_combine (insn, links->insn, 1361 prev, NULL, &new_direct_jump_p, 1362 last_combined_insn)) != 0) 1363 goto retry; 1364 } 1365 1366 /* Try combining an insn with two different insns whose results it 1367 uses. */ 1368 if (max_combine >= 3) 1369 FOR_EACH_LOG_LINK (links, insn) 1370 for (nextlinks = links->next; nextlinks; 1371 nextlinks = nextlinks->next) 1372 if ((next = try_combine (insn, links->insn, 1373 nextlinks->insn, NULL, 1374 &new_direct_jump_p, 1375 last_combined_insn)) != 0) 1376 1377 { 1378 statistics_counter_event (cfun, "three-insn combine", 1); 1379 goto retry; 1380 } 1381 1382 /* Try four-instruction combinations. */ 1383 if (max_combine >= 4) 1384 FOR_EACH_LOG_LINK (links, insn) 1385 { 1386 struct insn_link *next1; 1387 rtx_insn *link = links->insn; 1388 1389 /* If the linked insn has been replaced by a note, then there 1390 is no point in pursuing this chain any further. */ 1391 if (NOTE_P (link)) 1392 continue; 1393 1394 FOR_EACH_LOG_LINK (next1, link) 1395 { 1396 rtx_insn *link1 = next1->insn; 1397 if (NOTE_P (link1)) 1398 continue; 1399 /* I0 -> I1 -> I2 -> I3. */ 1400 FOR_EACH_LOG_LINK (nextlinks, link1) 1401 if ((next = try_combine (insn, link, link1, 1402 nextlinks->insn, 1403 &new_direct_jump_p, 1404 last_combined_insn)) != 0) 1405 { 1406 statistics_counter_event (cfun, "four-insn combine", 1); 1407 goto retry; 1408 } 1409 /* I0, I1 -> I2, I2 -> I3. */ 1410 for (nextlinks = next1->next; nextlinks; 1411 nextlinks = nextlinks->next) 1412 if ((next = try_combine (insn, link, link1, 1413 nextlinks->insn, 1414 &new_direct_jump_p, 1415 last_combined_insn)) != 0) 1416 { 1417 statistics_counter_event (cfun, "four-insn combine", 1); 1418 goto retry; 1419 } 1420 } 1421 1422 for (next1 = links->next; next1; next1 = next1->next) 1423 { 1424 rtx_insn *link1 = next1->insn; 1425 if (NOTE_P (link1)) 1426 continue; 1427 /* I0 -> I2; I1, I2 -> I3. */ 1428 FOR_EACH_LOG_LINK (nextlinks, link) 1429 if ((next = try_combine (insn, link, link1, 1430 nextlinks->insn, 1431 &new_direct_jump_p, 1432 last_combined_insn)) != 0) 1433 { 1434 statistics_counter_event (cfun, "four-insn combine", 1); 1435 goto retry; 1436 } 1437 /* I0 -> I1; I1, I2 -> I3. */ 1438 FOR_EACH_LOG_LINK (nextlinks, link1) 1439 if ((next = try_combine (insn, link, link1, 1440 nextlinks->insn, 1441 &new_direct_jump_p, 1442 last_combined_insn)) != 0) 1443 { 1444 statistics_counter_event (cfun, "four-insn combine", 1); 1445 goto retry; 1446 } 1447 } 1448 } 1449 1450 /* Try this insn with each REG_EQUAL note it links back to. */ 1451 FOR_EACH_LOG_LINK (links, insn) 1452 { 1453 rtx set, note; 1454 rtx_insn *temp = links->insn; 1455 if ((set = single_set (temp)) != 0 1456 && (note = find_reg_equal_equiv_note (temp)) != 0 1457 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST 1458 /* Avoid using a register that may already been marked 1459 dead by an earlier instruction. */ 1460 && ! unmentioned_reg_p (note, SET_SRC (set)) 1461 && (GET_MODE (note) == VOIDmode 1462 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set))) 1463 : (GET_MODE (SET_DEST (set)) == GET_MODE (note) 1464 && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT 1465 || (GET_MODE (XEXP (SET_DEST (set), 0)) 1466 == GET_MODE (note)))))) 1467 { 1468 /* Temporarily replace the set's source with the 1469 contents of the REG_EQUAL note. The insn will 1470 be deleted or recognized by try_combine. */ 1471 rtx orig_src = SET_SRC (set); 1472 rtx orig_dest = SET_DEST (set); 1473 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT) 1474 SET_DEST (set) = XEXP (SET_DEST (set), 0); 1475 SET_SRC (set) = note; 1476 i2mod = temp; 1477 i2mod_old_rhs = copy_rtx (orig_src); 1478 i2mod_new_rhs = copy_rtx (note); 1479 next = try_combine (insn, i2mod, NULL, NULL, 1480 &new_direct_jump_p, 1481 last_combined_insn); 1482 i2mod = NULL; 1483 if (next) 1484 { 1485 statistics_counter_event (cfun, "insn-with-note combine", 1); 1486 goto retry; 1487 } 1488 SET_SRC (set) = orig_src; 1489 SET_DEST (set) = orig_dest; 1490 } 1491 } 1492 1493 if (!NOTE_P (insn)) 1494 record_dead_and_set_regs (insn); 1495 1496 retry: 1497 ; 1498 } 1499 } 1500 1501 default_rtl_profile (); 1502 clear_bb_flags (); 1503 new_direct_jump_p |= purge_all_dead_edges (); 1504 delete_noop_moves (); 1505 1506 /* Clean up. */ 1507 obstack_free (&insn_link_obstack, NULL); 1508 free (uid_log_links); 1509 free (uid_insn_cost); 1510 reg_stat.release (); 1511 1512 { 1513 struct undo *undo, *next; 1514 for (undo = undobuf.frees; undo; undo = next) 1515 { 1516 next = undo->next; 1517 free (undo); 1518 } 1519 undobuf.frees = 0; 1520 } 1521 1522 total_attempts += combine_attempts; 1523 total_merges += combine_merges; 1524 total_extras += combine_extras; 1525 total_successes += combine_successes; 1526 1527 nonzero_sign_valid = 0; 1528 rtl_hooks = general_rtl_hooks; 1529 1530 /* Make recognizer allow volatile MEMs again. */ 1531 init_recog (); 1532 1533 return new_direct_jump_p; 1534 } 1535 1536 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */ 1537 1538 static void 1539 init_reg_last (void) 1540 { 1541 unsigned int i; 1542 reg_stat_type *p; 1543 1544 FOR_EACH_VEC_ELT (reg_stat, i, p) 1545 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies)); 1546 } 1547 1548 /* Set up any promoted values for incoming argument registers. */ 1549 1550 static void 1551 setup_incoming_promotions (rtx_insn *first) 1552 { 1553 tree arg; 1554 bool strictly_local = false; 1555 1556 for (arg = DECL_ARGUMENTS (current_function_decl); arg; 1557 arg = DECL_CHAIN (arg)) 1558 { 1559 rtx x, reg = DECL_INCOMING_RTL (arg); 1560 int uns1, uns3; 1561 machine_mode mode1, mode2, mode3, mode4; 1562 1563 /* Only continue if the incoming argument is in a register. */ 1564 if (!REG_P (reg)) 1565 continue; 1566 1567 /* Determine, if possible, whether all call sites of the current 1568 function lie within the current compilation unit. (This does 1569 take into account the exporting of a function via taking its 1570 address, and so forth.) */ 1571 strictly_local = cgraph_node::local_info (current_function_decl)->local; 1572 1573 /* The mode and signedness of the argument before any promotions happen 1574 (equal to the mode of the pseudo holding it at that stage). */ 1575 mode1 = TYPE_MODE (TREE_TYPE (arg)); 1576 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg)); 1577 1578 /* The mode and signedness of the argument after any source language and 1579 TARGET_PROMOTE_PROTOTYPES-driven promotions. */ 1580 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg)); 1581 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg)); 1582 1583 /* The mode and signedness of the argument as it is actually passed, 1584 see assign_parm_setup_reg in function.c. */ 1585 mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3, 1586 TREE_TYPE (cfun->decl), 0); 1587 1588 /* The mode of the register in which the argument is being passed. */ 1589 mode4 = GET_MODE (reg); 1590 1591 /* Eliminate sign extensions in the callee when: 1592 (a) A mode promotion has occurred; */ 1593 if (mode1 == mode3) 1594 continue; 1595 /* (b) The mode of the register is the same as the mode of 1596 the argument as it is passed; */ 1597 if (mode3 != mode4) 1598 continue; 1599 /* (c) There's no language level extension; */ 1600 if (mode1 == mode2) 1601 ; 1602 /* (c.1) All callers are from the current compilation unit. If that's 1603 the case we don't have to rely on an ABI, we only have to know 1604 what we're generating right now, and we know that we will do the 1605 mode1 to mode2 promotion with the given sign. */ 1606 else if (!strictly_local) 1607 continue; 1608 /* (c.2) The combination of the two promotions is useful. This is 1609 true when the signs match, or if the first promotion is unsigned. 1610 In the later case, (sign_extend (zero_extend x)) is the same as 1611 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */ 1612 else if (uns1) 1613 uns3 = true; 1614 else if (uns3) 1615 continue; 1616 1617 /* Record that the value was promoted from mode1 to mode3, 1618 so that any sign extension at the head of the current 1619 function may be eliminated. */ 1620 x = gen_rtx_CLOBBER (mode1, const0_rtx); 1621 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x); 1622 record_value_for_reg (reg, first, x); 1623 } 1624 } 1625 1626 /* If MODE has a precision lower than PREC and SRC is a non-negative constant 1627 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits 1628 because some machines (maybe most) will actually do the sign-extension and 1629 this is the conservative approach. 1630 1631 ??? For 2.5, try to tighten up the MD files in this regard instead of this 1632 kludge. */ 1633 1634 static rtx 1635 sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec) 1636 { 1637 if (GET_MODE_PRECISION (mode) < prec 1638 && CONST_INT_P (src) 1639 && INTVAL (src) > 0 1640 && val_signbit_known_set_p (mode, INTVAL (src))) 1641 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (mode)); 1642 1643 return src; 1644 } 1645 1646 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists) 1647 and SET. */ 1648 1649 static void 1650 update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set, 1651 rtx x) 1652 { 1653 rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX; 1654 unsigned HOST_WIDE_INT bits = 0; 1655 rtx reg_equal = NULL, src = SET_SRC (set); 1656 unsigned int num = 0; 1657 1658 if (reg_equal_note) 1659 reg_equal = XEXP (reg_equal_note, 0); 1660 1661 if (SHORT_IMMEDIATES_SIGN_EXTEND) 1662 { 1663 src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD); 1664 if (reg_equal) 1665 reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD); 1666 } 1667 1668 /* Don't call nonzero_bits if it cannot change anything. */ 1669 if (rsp->nonzero_bits != HOST_WIDE_INT_M1U) 1670 { 1671 bits = nonzero_bits (src, nonzero_bits_mode); 1672 if (reg_equal && bits) 1673 bits &= nonzero_bits (reg_equal, nonzero_bits_mode); 1674 rsp->nonzero_bits |= bits; 1675 } 1676 1677 /* Don't call num_sign_bit_copies if it cannot change anything. */ 1678 if (rsp->sign_bit_copies != 1) 1679 { 1680 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); 1681 if (reg_equal && num != GET_MODE_PRECISION (GET_MODE (x))) 1682 { 1683 unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x)); 1684 if (num == 0 || numeq > num) 1685 num = numeq; 1686 } 1687 if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies) 1688 rsp->sign_bit_copies = num; 1689 } 1690 } 1691 1692 /* Called via note_stores. If X is a pseudo that is narrower than 1693 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. 1694 1695 If we are setting only a portion of X and we can't figure out what 1696 portion, assume all bits will be used since we don't know what will 1697 be happening. 1698 1699 Similarly, set how many bits of X are known to be copies of the sign bit 1700 at all locations in the function. This is the smallest number implied 1701 by any set of X. */ 1702 1703 static void 1704 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data) 1705 { 1706 rtx_insn *insn = (rtx_insn *) data; 1707 1708 if (REG_P (x) 1709 && REGNO (x) >= FIRST_PSEUDO_REGISTER 1710 /* If this register is undefined at the start of the file, we can't 1711 say what its contents were. */ 1712 && ! REGNO_REG_SET_P 1713 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x)) 1714 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))) 1715 { 1716 reg_stat_type *rsp = ®_stat[REGNO (x)]; 1717 1718 if (set == 0 || GET_CODE (set) == CLOBBER) 1719 { 1720 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); 1721 rsp->sign_bit_copies = 1; 1722 return; 1723 } 1724 1725 /* If this register is being initialized using itself, and the 1726 register is uninitialized in this basic block, and there are 1727 no LOG_LINKS which set the register, then part of the 1728 register is uninitialized. In that case we can't assume 1729 anything about the number of nonzero bits. 1730 1731 ??? We could do better if we checked this in 1732 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we 1733 could avoid making assumptions about the insn which initially 1734 sets the register, while still using the information in other 1735 insns. We would have to be careful to check every insn 1736 involved in the combination. */ 1737 1738 if (insn 1739 && reg_referenced_p (x, PATTERN (insn)) 1740 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)), 1741 REGNO (x))) 1742 { 1743 struct insn_link *link; 1744 1745 FOR_EACH_LOG_LINK (link, insn) 1746 if (dead_or_set_p (link->insn, x)) 1747 break; 1748 if (!link) 1749 { 1750 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); 1751 rsp->sign_bit_copies = 1; 1752 return; 1753 } 1754 } 1755 1756 /* If this is a complex assignment, see if we can convert it into a 1757 simple assignment. */ 1758 set = expand_field_assignment (set); 1759 1760 /* If this is a simple assignment, or we have a paradoxical SUBREG, 1761 set what we know about X. */ 1762 1763 if (SET_DEST (set) == x 1764 || (paradoxical_subreg_p (SET_DEST (set)) 1765 && SUBREG_REG (SET_DEST (set)) == x)) 1766 update_rsp_from_reg_equal (rsp, insn, set, x); 1767 else 1768 { 1769 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); 1770 rsp->sign_bit_copies = 1; 1771 } 1772 } 1773 } 1774 1775 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are 1776 optionally insns that were previously combined into I3 or that will be 1777 combined into the merger of INSN and I3. The order is PRED, PRED2, 1778 INSN, SUCC, SUCC2, I3. 1779 1780 Return 0 if the combination is not allowed for any reason. 1781 1782 If the combination is allowed, *PDEST will be set to the single 1783 destination of INSN and *PSRC to the single source, and this function 1784 will return 1. */ 1785 1786 static int 1787 can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED, 1788 rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2, 1789 rtx *pdest, rtx *psrc) 1790 { 1791 int i; 1792 const_rtx set = 0; 1793 rtx src, dest; 1794 rtx_insn *p; 1795 rtx link; 1796 bool all_adjacent = true; 1797 int (*is_volatile_p) (const_rtx); 1798 1799 if (succ) 1800 { 1801 if (succ2) 1802 { 1803 if (next_active_insn (succ2) != i3) 1804 all_adjacent = false; 1805 if (next_active_insn (succ) != succ2) 1806 all_adjacent = false; 1807 } 1808 else if (next_active_insn (succ) != i3) 1809 all_adjacent = false; 1810 if (next_active_insn (insn) != succ) 1811 all_adjacent = false; 1812 } 1813 else if (next_active_insn (insn) != i3) 1814 all_adjacent = false; 1815 1816 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. 1817 or a PARALLEL consisting of such a SET and CLOBBERs. 1818 1819 If INSN has CLOBBER parallel parts, ignore them for our processing. 1820 By definition, these happen during the execution of the insn. When it 1821 is merged with another insn, all bets are off. If they are, in fact, 1822 needed and aren't also supplied in I3, they may be added by 1823 recog_for_combine. Otherwise, it won't match. 1824 1825 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED 1826 note. 1827 1828 Get the source and destination of INSN. If more than one, can't 1829 combine. */ 1830 1831 if (GET_CODE (PATTERN (insn)) == SET) 1832 set = PATTERN (insn); 1833 else if (GET_CODE (PATTERN (insn)) == PARALLEL 1834 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 1835 { 1836 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 1837 { 1838 rtx elt = XVECEXP (PATTERN (insn), 0, i); 1839 1840 switch (GET_CODE (elt)) 1841 { 1842 /* This is important to combine floating point insns 1843 for the SH4 port. */ 1844 case USE: 1845 /* Combining an isolated USE doesn't make sense. 1846 We depend here on combinable_i3pat to reject them. */ 1847 /* The code below this loop only verifies that the inputs of 1848 the SET in INSN do not change. We call reg_set_between_p 1849 to verify that the REG in the USE does not change between 1850 I3 and INSN. 1851 If the USE in INSN was for a pseudo register, the matching 1852 insn pattern will likely match any register; combining this 1853 with any other USE would only be safe if we knew that the 1854 used registers have identical values, or if there was 1855 something to tell them apart, e.g. different modes. For 1856 now, we forgo such complicated tests and simply disallow 1857 combining of USES of pseudo registers with any other USE. */ 1858 if (REG_P (XEXP (elt, 0)) 1859 && GET_CODE (PATTERN (i3)) == PARALLEL) 1860 { 1861 rtx i3pat = PATTERN (i3); 1862 int i = XVECLEN (i3pat, 0) - 1; 1863 unsigned int regno = REGNO (XEXP (elt, 0)); 1864 1865 do 1866 { 1867 rtx i3elt = XVECEXP (i3pat, 0, i); 1868 1869 if (GET_CODE (i3elt) == USE 1870 && REG_P (XEXP (i3elt, 0)) 1871 && (REGNO (XEXP (i3elt, 0)) == regno 1872 ? reg_set_between_p (XEXP (elt, 0), 1873 PREV_INSN (insn), i3) 1874 : regno >= FIRST_PSEUDO_REGISTER)) 1875 return 0; 1876 } 1877 while (--i >= 0); 1878 } 1879 break; 1880 1881 /* We can ignore CLOBBERs. */ 1882 case CLOBBER: 1883 break; 1884 1885 case SET: 1886 /* Ignore SETs whose result isn't used but not those that 1887 have side-effects. */ 1888 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) 1889 && insn_nothrow_p (insn) 1890 && !side_effects_p (elt)) 1891 break; 1892 1893 /* If we have already found a SET, this is a second one and 1894 so we cannot combine with this insn. */ 1895 if (set) 1896 return 0; 1897 1898 set = elt; 1899 break; 1900 1901 default: 1902 /* Anything else means we can't combine. */ 1903 return 0; 1904 } 1905 } 1906 1907 if (set == 0 1908 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, 1909 so don't do anything with it. */ 1910 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) 1911 return 0; 1912 } 1913 else 1914 return 0; 1915 1916 if (set == 0) 1917 return 0; 1918 1919 /* The simplification in expand_field_assignment may call back to 1920 get_last_value, so set safe guard here. */ 1921 subst_low_luid = DF_INSN_LUID (insn); 1922 1923 set = expand_field_assignment (set); 1924 src = SET_SRC (set), dest = SET_DEST (set); 1925 1926 /* Do not eliminate user-specified register if it is in an 1927 asm input because we may break the register asm usage defined 1928 in GCC manual if allow to do so. 1929 Be aware that this may cover more cases than we expect but this 1930 should be harmless. */ 1931 if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest) 1932 && extract_asm_operands (PATTERN (i3))) 1933 return 0; 1934 1935 /* Don't eliminate a store in the stack pointer. */ 1936 if (dest == stack_pointer_rtx 1937 /* Don't combine with an insn that sets a register to itself if it has 1938 a REG_EQUAL note. This may be part of a LIBCALL sequence. */ 1939 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 1940 /* Can't merge an ASM_OPERANDS. */ 1941 || GET_CODE (src) == ASM_OPERANDS 1942 /* Can't merge a function call. */ 1943 || GET_CODE (src) == CALL 1944 /* Don't eliminate a function call argument. */ 1945 || (CALL_P (i3) 1946 && (find_reg_fusage (i3, USE, dest) 1947 || (REG_P (dest) 1948 && REGNO (dest) < FIRST_PSEUDO_REGISTER 1949 && global_regs[REGNO (dest)]))) 1950 /* Don't substitute into an incremented register. */ 1951 || FIND_REG_INC_NOTE (i3, dest) 1952 || (succ && FIND_REG_INC_NOTE (succ, dest)) 1953 || (succ2 && FIND_REG_INC_NOTE (succ2, dest)) 1954 /* Don't substitute into a non-local goto, this confuses CFG. */ 1955 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX)) 1956 /* Make sure that DEST is not used after INSN but before SUCC, or 1957 after SUCC and before SUCC2, or after SUCC2 but before I3. */ 1958 || (!all_adjacent 1959 && ((succ2 1960 && (reg_used_between_p (dest, succ2, i3) 1961 || reg_used_between_p (dest, succ, succ2))) 1962 || (!succ2 && succ && reg_used_between_p (dest, succ, i3)) 1963 || (succ 1964 /* SUCC and SUCC2 can be split halves from a PARALLEL; in 1965 that case SUCC is not in the insn stream, so use SUCC2 1966 instead for this test. */ 1967 && reg_used_between_p (dest, insn, 1968 succ2 1969 && INSN_UID (succ) == INSN_UID (succ2) 1970 ? succ2 : succ)))) 1971 /* Make sure that the value that is to be substituted for the register 1972 does not use any registers whose values alter in between. However, 1973 If the insns are adjacent, a use can't cross a set even though we 1974 think it might (this can happen for a sequence of insns each setting 1975 the same destination; last_set of that register might point to 1976 a NOTE). If INSN has a REG_EQUIV note, the register is always 1977 equivalent to the memory so the substitution is valid even if there 1978 are intervening stores. Also, don't move a volatile asm or 1979 UNSPEC_VOLATILE across any other insns. */ 1980 || (! all_adjacent 1981 && (((!MEM_P (src) 1982 || ! find_reg_note (insn, REG_EQUIV, src)) 1983 && use_crosses_set_p (src, DF_INSN_LUID (insn))) 1984 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) 1985 || GET_CODE (src) == UNSPEC_VOLATILE)) 1986 /* Don't combine across a CALL_INSN, because that would possibly 1987 change whether the life span of some REGs crosses calls or not, 1988 and it is a pain to update that information. 1989 Exception: if source is a constant, moving it later can't hurt. 1990 Accept that as a special case. */ 1991 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src))) 1992 return 0; 1993 1994 /* DEST must either be a REG or CC0. */ 1995 if (REG_P (dest)) 1996 { 1997 /* If register alignment is being enforced for multi-word items in all 1998 cases except for parameters, it is possible to have a register copy 1999 insn referencing a hard register that is not allowed to contain the 2000 mode being copied and which would not be valid as an operand of most 2001 insns. Eliminate this problem by not combining with such an insn. 2002 2003 Also, on some machines we don't want to extend the life of a hard 2004 register. */ 2005 2006 if (REG_P (src) 2007 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER 2008 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) 2009 /* Don't extend the life of a hard register unless it is 2010 user variable (if we have few registers) or it can't 2011 fit into the desired register (meaning something special 2012 is going on). 2013 Also avoid substituting a return register into I3, because 2014 reload can't handle a conflict with constraints of other 2015 inputs. */ 2016 || (REGNO (src) < FIRST_PSEUDO_REGISTER 2017 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) 2018 return 0; 2019 } 2020 else if (GET_CODE (dest) != CC0) 2021 return 0; 2022 2023 2024 if (GET_CODE (PATTERN (i3)) == PARALLEL) 2025 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) 2026 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER) 2027 { 2028 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0); 2029 2030 /* If the clobber represents an earlyclobber operand, we must not 2031 substitute an expression containing the clobbered register. 2032 As we do not analyze the constraint strings here, we have to 2033 make the conservative assumption. However, if the register is 2034 a fixed hard reg, the clobber cannot represent any operand; 2035 we leave it up to the machine description to either accept or 2036 reject use-and-clobber patterns. */ 2037 if (!REG_P (reg) 2038 || REGNO (reg) >= FIRST_PSEUDO_REGISTER 2039 || !fixed_regs[REGNO (reg)]) 2040 if (reg_overlap_mentioned_p (reg, src)) 2041 return 0; 2042 } 2043 2044 /* If INSN contains anything volatile, or is an `asm' (whether volatile 2045 or not), reject, unless nothing volatile comes between it and I3 */ 2046 2047 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) 2048 { 2049 /* Make sure neither succ nor succ2 contains a volatile reference. */ 2050 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2))) 2051 return 0; 2052 if (succ != 0 && volatile_refs_p (PATTERN (succ))) 2053 return 0; 2054 /* We'll check insns between INSN and I3 below. */ 2055 } 2056 2057 /* If INSN is an asm, and DEST is a hard register, reject, since it has 2058 to be an explicit register variable, and was chosen for a reason. */ 2059 2060 if (GET_CODE (src) == ASM_OPERANDS 2061 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER) 2062 return 0; 2063 2064 /* If INSN contains volatile references (specifically volatile MEMs), 2065 we cannot combine across any other volatile references. 2066 Even if INSN doesn't contain volatile references, any intervening 2067 volatile insn might affect machine state. */ 2068 2069 is_volatile_p = volatile_refs_p (PATTERN (insn)) 2070 ? volatile_refs_p 2071 : volatile_insn_p; 2072 2073 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 2074 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p))) 2075 return 0; 2076 2077 /* If INSN contains an autoincrement or autodecrement, make sure that 2078 register is not used between there and I3, and not already used in 2079 I3 either. Neither must it be used in PRED or SUCC, if they exist. 2080 Also insist that I3 not be a jump; if it were one 2081 and the incremented register were spilled, we would lose. */ 2082 2083 if (AUTO_INC_DEC) 2084 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 2085 if (REG_NOTE_KIND (link) == REG_INC 2086 && (JUMP_P (i3) 2087 || reg_used_between_p (XEXP (link, 0), insn, i3) 2088 || (pred != NULL_RTX 2089 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred))) 2090 || (pred2 != NULL_RTX 2091 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2))) 2092 || (succ != NULL_RTX 2093 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ))) 2094 || (succ2 != NULL_RTX 2095 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2))) 2096 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) 2097 return 0; 2098 2099 /* Don't combine an insn that follows a CC0-setting insn. 2100 An insn that uses CC0 must not be separated from the one that sets it. 2101 We do, however, allow I2 to follow a CC0-setting insn if that insn 2102 is passed as I1; in that case it will be deleted also. 2103 We also allow combining in this case if all the insns are adjacent 2104 because that would leave the two CC0 insns adjacent as well. 2105 It would be more logical to test whether CC0 occurs inside I1 or I2, 2106 but that would be much slower, and this ought to be equivalent. */ 2107 2108 if (HAVE_cc0) 2109 { 2110 p = prev_nonnote_insn (insn); 2111 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p)) 2112 && ! all_adjacent) 2113 return 0; 2114 } 2115 2116 /* If we get here, we have passed all the tests and the combination is 2117 to be allowed. */ 2118 2119 *pdest = dest; 2120 *psrc = src; 2121 2122 return 1; 2123 } 2124 2125 /* LOC is the location within I3 that contains its pattern or the component 2126 of a PARALLEL of the pattern. We validate that it is valid for combining. 2127 2128 One problem is if I3 modifies its output, as opposed to replacing it 2129 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as 2130 doing so would produce an insn that is not equivalent to the original insns. 2131 2132 Consider: 2133 2134 (set (reg:DI 101) (reg:DI 100)) 2135 (set (subreg:SI (reg:DI 101) 0) <foo>) 2136 2137 This is NOT equivalent to: 2138 2139 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) 2140 (set (reg:DI 101) (reg:DI 100))]) 2141 2142 Not only does this modify 100 (in which case it might still be valid 2143 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. 2144 2145 We can also run into a problem if I2 sets a register that I1 2146 uses and I1 gets directly substituted into I3 (not via I2). In that 2147 case, we would be getting the wrong value of I2DEST into I3, so we 2148 must reject the combination. This case occurs when I2 and I1 both 2149 feed into I3, rather than when I1 feeds into I2, which feeds into I3. 2150 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source 2151 of a SET must prevent combination from occurring. The same situation 2152 can occur for I0, in which case I0_NOT_IN_SRC is set. 2153 2154 Before doing the above check, we first try to expand a field assignment 2155 into a set of logical operations. 2156 2157 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which 2158 we place a register that is both set and used within I3. If more than one 2159 such register is detected, we fail. 2160 2161 Return 1 if the combination is valid, zero otherwise. */ 2162 2163 static int 2164 combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest, 2165 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed) 2166 { 2167 rtx x = *loc; 2168 2169 if (GET_CODE (x) == SET) 2170 { 2171 rtx set = x ; 2172 rtx dest = SET_DEST (set); 2173 rtx src = SET_SRC (set); 2174 rtx inner_dest = dest; 2175 rtx subdest; 2176 2177 while (GET_CODE (inner_dest) == STRICT_LOW_PART 2178 || GET_CODE (inner_dest) == SUBREG 2179 || GET_CODE (inner_dest) == ZERO_EXTRACT) 2180 inner_dest = XEXP (inner_dest, 0); 2181 2182 /* Check for the case where I3 modifies its output, as discussed 2183 above. We don't want to prevent pseudos from being combined 2184 into the address of a MEM, so only prevent the combination if 2185 i1 or i2 set the same MEM. */ 2186 if ((inner_dest != dest && 2187 (!MEM_P (inner_dest) 2188 || rtx_equal_p (i2dest, inner_dest) 2189 || (i1dest && rtx_equal_p (i1dest, inner_dest)) 2190 || (i0dest && rtx_equal_p (i0dest, inner_dest))) 2191 && (reg_overlap_mentioned_p (i2dest, inner_dest) 2192 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)) 2193 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest)))) 2194 2195 /* This is the same test done in can_combine_p except we can't test 2196 all_adjacent; we don't have to, since this instruction will stay 2197 in place, thus we are not considering increasing the lifetime of 2198 INNER_DEST. 2199 2200 Also, if this insn sets a function argument, combining it with 2201 something that might need a spill could clobber a previous 2202 function argument; the all_adjacent test in can_combine_p also 2203 checks this; here, we do a more specific test for this case. */ 2204 2205 || (REG_P (inner_dest) 2206 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 2207 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), 2208 GET_MODE (inner_dest)))) 2209 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)) 2210 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src))) 2211 return 0; 2212 2213 /* If DEST is used in I3, it is being killed in this insn, so 2214 record that for later. We have to consider paradoxical 2215 subregs here, since they kill the whole register, but we 2216 ignore partial subregs, STRICT_LOW_PART, etc. 2217 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the 2218 STACK_POINTER_REGNUM, since these are always considered to be 2219 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ 2220 subdest = dest; 2221 if (GET_CODE (subdest) == SUBREG 2222 && (GET_MODE_SIZE (GET_MODE (subdest)) 2223 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest))))) 2224 subdest = SUBREG_REG (subdest); 2225 if (pi3dest_killed 2226 && REG_P (subdest) 2227 && reg_referenced_p (subdest, PATTERN (i3)) 2228 && REGNO (subdest) != FRAME_POINTER_REGNUM 2229 && (HARD_FRAME_POINTER_IS_FRAME_POINTER 2230 || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM) 2231 && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM 2232 || (REGNO (subdest) != ARG_POINTER_REGNUM 2233 || ! fixed_regs [REGNO (subdest)])) 2234 && REGNO (subdest) != STACK_POINTER_REGNUM) 2235 { 2236 if (*pi3dest_killed) 2237 return 0; 2238 2239 *pi3dest_killed = subdest; 2240 } 2241 } 2242 2243 else if (GET_CODE (x) == PARALLEL) 2244 { 2245 int i; 2246 2247 for (i = 0; i < XVECLEN (x, 0); i++) 2248 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest, 2249 i1_not_in_src, i0_not_in_src, pi3dest_killed)) 2250 return 0; 2251 } 2252 2253 return 1; 2254 } 2255 2256 /* Return 1 if X is an arithmetic expression that contains a multiplication 2257 and division. We don't count multiplications by powers of two here. */ 2258 2259 static int 2260 contains_muldiv (rtx x) 2261 { 2262 switch (GET_CODE (x)) 2263 { 2264 case MOD: case DIV: case UMOD: case UDIV: 2265 return 1; 2266 2267 case MULT: 2268 return ! (CONST_INT_P (XEXP (x, 1)) 2269 && pow2p_hwi (UINTVAL (XEXP (x, 1)))); 2270 default: 2271 if (BINARY_P (x)) 2272 return contains_muldiv (XEXP (x, 0)) 2273 || contains_muldiv (XEXP (x, 1)); 2274 2275 if (UNARY_P (x)) 2276 return contains_muldiv (XEXP (x, 0)); 2277 2278 return 0; 2279 } 2280 } 2281 2282 /* Determine whether INSN can be used in a combination. Return nonzero if 2283 not. This is used in try_combine to detect early some cases where we 2284 can't perform combinations. */ 2285 2286 static int 2287 cant_combine_insn_p (rtx_insn *insn) 2288 { 2289 rtx set; 2290 rtx src, dest; 2291 2292 /* If this isn't really an insn, we can't do anything. 2293 This can occur when flow deletes an insn that it has merged into an 2294 auto-increment address. */ 2295 if (!NONDEBUG_INSN_P (insn)) 2296 return 1; 2297 2298 /* Never combine loads and stores involving hard regs that are likely 2299 to be spilled. The register allocator can usually handle such 2300 reg-reg moves by tying. If we allow the combiner to make 2301 substitutions of likely-spilled regs, reload might die. 2302 As an exception, we allow combinations involving fixed regs; these are 2303 not available to the register allocator so there's no risk involved. */ 2304 2305 set = single_set (insn); 2306 if (! set) 2307 return 0; 2308 src = SET_SRC (set); 2309 dest = SET_DEST (set); 2310 if (GET_CODE (src) == SUBREG) 2311 src = SUBREG_REG (src); 2312 if (GET_CODE (dest) == SUBREG) 2313 dest = SUBREG_REG (dest); 2314 if (REG_P (src) && REG_P (dest) 2315 && ((HARD_REGISTER_P (src) 2316 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)) 2317 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src)))) 2318 || (HARD_REGISTER_P (dest) 2319 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest)) 2320 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest)))))) 2321 return 1; 2322 2323 return 0; 2324 } 2325 2326 struct likely_spilled_retval_info 2327 { 2328 unsigned regno, nregs; 2329 unsigned mask; 2330 }; 2331 2332 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask 2333 hard registers that are known to be written to / clobbered in full. */ 2334 static void 2335 likely_spilled_retval_1 (rtx x, const_rtx set, void *data) 2336 { 2337 struct likely_spilled_retval_info *const info = 2338 (struct likely_spilled_retval_info *) data; 2339 unsigned regno, nregs; 2340 unsigned new_mask; 2341 2342 if (!REG_P (XEXP (set, 0))) 2343 return; 2344 regno = REGNO (x); 2345 if (regno >= info->regno + info->nregs) 2346 return; 2347 nregs = REG_NREGS (x); 2348 if (regno + nregs <= info->regno) 2349 return; 2350 new_mask = (2U << (nregs - 1)) - 1; 2351 if (regno < info->regno) 2352 new_mask >>= info->regno - regno; 2353 else 2354 new_mask <<= regno - info->regno; 2355 info->mask &= ~new_mask; 2356 } 2357 2358 /* Return nonzero iff part of the return value is live during INSN, and 2359 it is likely spilled. This can happen when more than one insn is needed 2360 to copy the return value, e.g. when we consider to combine into the 2361 second copy insn for a complex value. */ 2362 2363 static int 2364 likely_spilled_retval_p (rtx_insn *insn) 2365 { 2366 rtx_insn *use = BB_END (this_basic_block); 2367 rtx reg; 2368 rtx_insn *p; 2369 unsigned regno, nregs; 2370 /* We assume here that no machine mode needs more than 2371 32 hard registers when the value overlaps with a register 2372 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */ 2373 unsigned mask; 2374 struct likely_spilled_retval_info info; 2375 2376 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use) 2377 return 0; 2378 reg = XEXP (PATTERN (use), 0); 2379 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg))) 2380 return 0; 2381 regno = REGNO (reg); 2382 nregs = REG_NREGS (reg); 2383 if (nregs == 1) 2384 return 0; 2385 mask = (2U << (nregs - 1)) - 1; 2386 2387 /* Disregard parts of the return value that are set later. */ 2388 info.regno = regno; 2389 info.nregs = nregs; 2390 info.mask = mask; 2391 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p)) 2392 if (INSN_P (p)) 2393 note_stores (PATTERN (p), likely_spilled_retval_1, &info); 2394 mask = info.mask; 2395 2396 /* Check if any of the (probably) live return value registers is 2397 likely spilled. */ 2398 nregs --; 2399 do 2400 { 2401 if ((mask & 1 << nregs) 2402 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs))) 2403 return 1; 2404 } while (nregs--); 2405 return 0; 2406 } 2407 2408 /* Adjust INSN after we made a change to its destination. 2409 2410 Changing the destination can invalidate notes that say something about 2411 the results of the insn and a LOG_LINK pointing to the insn. */ 2412 2413 static void 2414 adjust_for_new_dest (rtx_insn *insn) 2415 { 2416 /* For notes, be conservative and simply remove them. */ 2417 remove_reg_equal_equiv_notes (insn); 2418 2419 /* The new insn will have a destination that was previously the destination 2420 of an insn just above it. Call distribute_links to make a LOG_LINK from 2421 the next use of that destination. */ 2422 2423 rtx set = single_set (insn); 2424 gcc_assert (set); 2425 2426 rtx reg = SET_DEST (set); 2427 2428 while (GET_CODE (reg) == ZERO_EXTRACT 2429 || GET_CODE (reg) == STRICT_LOW_PART 2430 || GET_CODE (reg) == SUBREG) 2431 reg = XEXP (reg, 0); 2432 gcc_assert (REG_P (reg)); 2433 2434 distribute_links (alloc_insn_link (insn, REGNO (reg), NULL)); 2435 2436 df_insn_rescan (insn); 2437 } 2438 2439 /* Return TRUE if combine can reuse reg X in mode MODE. 2440 ADDED_SETS is nonzero if the original set is still required. */ 2441 static bool 2442 can_change_dest_mode (rtx x, int added_sets, machine_mode mode) 2443 { 2444 unsigned int regno; 2445 2446 if (!REG_P (x)) 2447 return false; 2448 2449 regno = REGNO (x); 2450 /* Allow hard registers if the new mode is legal, and occupies no more 2451 registers than the old mode. */ 2452 if (regno < FIRST_PSEUDO_REGISTER) 2453 return (HARD_REGNO_MODE_OK (regno, mode) 2454 && REG_NREGS (x) >= hard_regno_nregs[regno][mode]); 2455 2456 /* Or a pseudo that is only used once. */ 2457 return (regno < reg_n_sets_max 2458 && REG_N_SETS (regno) == 1 2459 && !added_sets 2460 && !REG_USERVAR_P (x)); 2461 } 2462 2463 2464 /* Check whether X, the destination of a set, refers to part of 2465 the register specified by REG. */ 2466 2467 static bool 2468 reg_subword_p (rtx x, rtx reg) 2469 { 2470 /* Check that reg is an integer mode register. */ 2471 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) 2472 return false; 2473 2474 if (GET_CODE (x) == STRICT_LOW_PART 2475 || GET_CODE (x) == ZERO_EXTRACT) 2476 x = XEXP (x, 0); 2477 2478 return GET_CODE (x) == SUBREG 2479 && SUBREG_REG (x) == reg 2480 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT; 2481 } 2482 2483 /* Delete the unconditional jump INSN and adjust the CFG correspondingly. 2484 Note that the INSN should be deleted *after* removing dead edges, so 2485 that the kept edge is the fallthrough edge for a (set (pc) (pc)) 2486 but not for a (set (pc) (label_ref FOO)). */ 2487 2488 static void 2489 update_cfg_for_uncondjump (rtx_insn *insn) 2490 { 2491 basic_block bb = BLOCK_FOR_INSN (insn); 2492 gcc_assert (BB_END (bb) == insn); 2493 2494 purge_dead_edges (bb); 2495 2496 delete_insn (insn); 2497 if (EDGE_COUNT (bb->succs) == 1) 2498 { 2499 rtx_insn *insn; 2500 2501 single_succ_edge (bb)->flags |= EDGE_FALLTHRU; 2502 2503 /* Remove barriers from the footer if there are any. */ 2504 for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn)) 2505 if (BARRIER_P (insn)) 2506 { 2507 if (PREV_INSN (insn)) 2508 SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); 2509 else 2510 BB_FOOTER (bb) = NEXT_INSN (insn); 2511 if (NEXT_INSN (insn)) 2512 SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); 2513 } 2514 else if (LABEL_P (insn)) 2515 break; 2516 } 2517 } 2518 2519 /* Return whether PAT is a PARALLEL of exactly N register SETs followed 2520 by an arbitrary number of CLOBBERs. */ 2521 static bool 2522 is_parallel_of_n_reg_sets (rtx pat, int n) 2523 { 2524 if (GET_CODE (pat) != PARALLEL) 2525 return false; 2526 2527 int len = XVECLEN (pat, 0); 2528 if (len < n) 2529 return false; 2530 2531 int i; 2532 for (i = 0; i < n; i++) 2533 if (GET_CODE (XVECEXP (pat, 0, i)) != SET 2534 || !REG_P (SET_DEST (XVECEXP (pat, 0, i)))) 2535 return false; 2536 for ( ; i < len; i++) 2537 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER 2538 || XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 2539 return false; 2540 2541 return true; 2542 } 2543 2544 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some 2545 CLOBBERs), can be split into individual SETs in that order, without 2546 changing semantics. */ 2547 static bool 2548 can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n) 2549 { 2550 if (!insn_nothrow_p (insn)) 2551 return false; 2552 2553 rtx pat = PATTERN (insn); 2554 2555 int i, j; 2556 for (i = 0; i < n; i++) 2557 { 2558 if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i)))) 2559 return false; 2560 2561 rtx reg = SET_DEST (XVECEXP (pat, 0, i)); 2562 2563 for (j = i + 1; j < n; j++) 2564 if (reg_referenced_p (reg, XVECEXP (pat, 0, j))) 2565 return false; 2566 } 2567 2568 return true; 2569 } 2570 2571 /* Try to combine the insns I0, I1 and I2 into I3. 2572 Here I0, I1 and I2 appear earlier than I3. 2573 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into 2574 I3. 2575 2576 If we are combining more than two insns and the resulting insn is not 2577 recognized, try splitting it into two insns. If that happens, I2 and I3 2578 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE. 2579 Otherwise, I0, I1 and I2 are pseudo-deleted. 2580 2581 Return 0 if the combination does not work. Then nothing is changed. 2582 If we did the combination, return the insn at which combine should 2583 resume scanning. 2584 2585 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a 2586 new direct jump instruction. 2587 2588 LAST_COMBINED_INSN is either I3, or some insn after I3 that has 2589 been I3 passed to an earlier try_combine within the same basic 2590 block. */ 2591 2592 static rtx_insn * 2593 try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, 2594 int *new_direct_jump_p, rtx_insn *last_combined_insn) 2595 { 2596 /* New patterns for I3 and I2, respectively. */ 2597 rtx newpat, newi2pat = 0; 2598 rtvec newpat_vec_with_clobbers = 0; 2599 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0; 2600 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not 2601 dead. */ 2602 int added_sets_0, added_sets_1, added_sets_2; 2603 /* Total number of SETs to put into I3. */ 2604 int total_sets; 2605 /* Nonzero if I2's or I1's body now appears in I3. */ 2606 int i2_is_used = 0, i1_is_used = 0; 2607 /* INSN_CODEs for new I3, new I2, and user of condition code. */ 2608 int insn_code_number, i2_code_number = 0, other_code_number = 0; 2609 /* Contains I3 if the destination of I3 is used in its source, which means 2610 that the old life of I3 is being killed. If that usage is placed into 2611 I2 and not in I3, a REG_DEAD note must be made. */ 2612 rtx i3dest_killed = 0; 2613 /* SET_DEST and SET_SRC of I2, I1 and I0. */ 2614 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0; 2615 /* Copy of SET_SRC of I1 and I0, if needed. */ 2616 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0; 2617 /* Set if I2DEST was reused as a scratch register. */ 2618 bool i2scratch = false; 2619 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */ 2620 rtx i0pat = 0, i1pat = 0, i2pat = 0; 2621 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ 2622 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; 2623 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0; 2624 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0; 2625 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0; 2626 /* Notes that must be added to REG_NOTES in I3 and I2. */ 2627 rtx new_i3_notes, new_i2_notes; 2628 /* Notes that we substituted I3 into I2 instead of the normal case. */ 2629 int i3_subst_into_i2 = 0; 2630 /* Notes that I1, I2 or I3 is a MULT operation. */ 2631 int have_mult = 0; 2632 int swap_i2i3 = 0; 2633 int changed_i3_dest = 0; 2634 2635 int maxreg; 2636 rtx_insn *temp_insn; 2637 rtx temp_expr; 2638 struct insn_link *link; 2639 rtx other_pat = 0; 2640 rtx new_other_notes; 2641 int i; 2642 2643 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can 2644 never be). */ 2645 if (i1 == i2 || i0 == i2 || (i0 && i0 == i1)) 2646 return 0; 2647 2648 /* Only try four-insn combinations when there's high likelihood of 2649 success. Look for simple insns, such as loads of constants or 2650 binary operations involving a constant. */ 2651 if (i0) 2652 { 2653 int i; 2654 int ngood = 0; 2655 int nshift = 0; 2656 rtx set0, set3; 2657 2658 if (!flag_expensive_optimizations) 2659 return 0; 2660 2661 for (i = 0; i < 4; i++) 2662 { 2663 rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3; 2664 rtx set = single_set (insn); 2665 rtx src; 2666 if (!set) 2667 continue; 2668 src = SET_SRC (set); 2669 if (CONSTANT_P (src)) 2670 { 2671 ngood += 2; 2672 break; 2673 } 2674 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1))) 2675 ngood++; 2676 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT 2677 || GET_CODE (src) == LSHIFTRT) 2678 nshift++; 2679 } 2680 2681 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2 2682 are likely manipulating its value. Ideally we'll be able to combine 2683 all four insns into a bitfield insertion of some kind. 2684 2685 Note the source in I0 might be inside a sign/zero extension and the 2686 memory modes in I0 and I3 might be different. So extract the address 2687 from the destination of I3 and search for it in the source of I0. 2688 2689 In the event that there's a match but the source/dest do not actually 2690 refer to the same memory, the worst that happens is we try some 2691 combinations that we wouldn't have otherwise. */ 2692 if ((set0 = single_set (i0)) 2693 /* Ensure the source of SET0 is a MEM, possibly buried inside 2694 an extension. */ 2695 && (GET_CODE (SET_SRC (set0)) == MEM 2696 || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND 2697 || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND) 2698 && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM)) 2699 && (set3 = single_set (i3)) 2700 /* Ensure the destination of SET3 is a MEM. */ 2701 && GET_CODE (SET_DEST (set3)) == MEM 2702 /* Would it be better to extract the base address for the MEM 2703 in SET3 and look for that? I don't have cases where it matters 2704 but I could envision such cases. */ 2705 && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0))) 2706 ngood += 2; 2707 2708 if (ngood < 2 && nshift < 2) 2709 return 0; 2710 } 2711 2712 /* Exit early if one of the insns involved can't be used for 2713 combinations. */ 2714 if (CALL_P (i2) 2715 || (i1 && CALL_P (i1)) 2716 || (i0 && CALL_P (i0)) 2717 || cant_combine_insn_p (i3) 2718 || cant_combine_insn_p (i2) 2719 || (i1 && cant_combine_insn_p (i1)) 2720 || (i0 && cant_combine_insn_p (i0)) 2721 || likely_spilled_retval_p (i3)) 2722 return 0; 2723 2724 combine_attempts++; 2725 undobuf.other_insn = 0; 2726 2727 /* Reset the hard register usage information. */ 2728 CLEAR_HARD_REG_SET (newpat_used_regs); 2729 2730 if (dump_file && (dump_flags & TDF_DETAILS)) 2731 { 2732 if (i0) 2733 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n", 2734 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); 2735 else if (i1) 2736 fprintf (dump_file, "\nTrying %d, %d -> %d:\n", 2737 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); 2738 else 2739 fprintf (dump_file, "\nTrying %d -> %d:\n", 2740 INSN_UID (i2), INSN_UID (i3)); 2741 } 2742 2743 /* If multiple insns feed into one of I2 or I3, they can be in any 2744 order. To simplify the code below, reorder them in sequence. */ 2745 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2)) 2746 std::swap (i0, i2); 2747 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1)) 2748 std::swap (i0, i1); 2749 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2)) 2750 std::swap (i1, i2); 2751 2752 added_links_insn = 0; 2753 2754 /* First check for one important special case that the code below will 2755 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL 2756 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, 2757 we may be able to replace that destination with the destination of I3. 2758 This occurs in the common code where we compute both a quotient and 2759 remainder into a structure, in which case we want to do the computation 2760 directly into the structure to avoid register-register copies. 2761 2762 Note that this case handles both multiple sets in I2 and also cases 2763 where I2 has a number of CLOBBERs inside the PARALLEL. 2764 2765 We make very conservative checks below and only try to handle the 2766 most common cases of this. For example, we only handle the case 2767 where I2 and I3 are adjacent to avoid making difficult register 2768 usage tests. */ 2769 2770 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET 2771 && REG_P (SET_SRC (PATTERN (i3))) 2772 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 2773 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) 2774 && GET_CODE (PATTERN (i2)) == PARALLEL 2775 && ! side_effects_p (SET_DEST (PATTERN (i3))) 2776 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code 2777 below would need to check what is inside (and reg_overlap_mentioned_p 2778 doesn't support those codes anyway). Don't allow those destinations; 2779 the resulting insn isn't likely to be recognized anyway. */ 2780 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT 2781 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART 2782 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), 2783 SET_DEST (PATTERN (i3))) 2784 && next_active_insn (i2) == i3) 2785 { 2786 rtx p2 = PATTERN (i2); 2787 2788 /* Make sure that the destination of I3, 2789 which we are going to substitute into one output of I2, 2790 is not used within another output of I2. We must avoid making this: 2791 (parallel [(set (mem (reg 69)) ...) 2792 (set (reg 69) ...)]) 2793 which is not well-defined as to order of actions. 2794 (Besides, reload can't handle output reloads for this.) 2795 2796 The problem can also happen if the dest of I3 is a memory ref, 2797 if another dest in I2 is an indirect memory ref. 2798 2799 Neither can this PARALLEL be an asm. We do not allow combining 2800 that usually (see can_combine_p), so do not here either. */ 2801 bool ok = true; 2802 for (i = 0; ok && i < XVECLEN (p2, 0); i++) 2803 { 2804 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 2805 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 2806 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), 2807 SET_DEST (XVECEXP (p2, 0, i)))) 2808 ok = false; 2809 else if (GET_CODE (XVECEXP (p2, 0, i)) == SET 2810 && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS) 2811 ok = false; 2812 } 2813 2814 if (ok) 2815 for (i = 0; i < XVECLEN (p2, 0); i++) 2816 if (GET_CODE (XVECEXP (p2, 0, i)) == SET 2817 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) 2818 { 2819 combine_merges++; 2820 2821 subst_insn = i3; 2822 subst_low_luid = DF_INSN_LUID (i2); 2823 2824 added_sets_2 = added_sets_1 = added_sets_0 = 0; 2825 i2src = SET_SRC (XVECEXP (p2, 0, i)); 2826 i2dest = SET_DEST (XVECEXP (p2, 0, i)); 2827 i2dest_killed = dead_or_set_p (i2, i2dest); 2828 2829 /* Replace the dest in I2 with our dest and make the resulting 2830 insn the new pattern for I3. Then skip to where we validate 2831 the pattern. Everything was set up above. */ 2832 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3))); 2833 newpat = p2; 2834 i3_subst_into_i2 = 1; 2835 goto validate_replacement; 2836 } 2837 } 2838 2839 /* If I2 is setting a pseudo to a constant and I3 is setting some 2840 sub-part of it to another constant, merge them by making a new 2841 constant. */ 2842 if (i1 == 0 2843 && (temp_expr = single_set (i2)) != 0 2844 && CONST_SCALAR_INT_P (SET_SRC (temp_expr)) 2845 && GET_CODE (PATTERN (i3)) == SET 2846 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3))) 2847 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr))) 2848 { 2849 rtx dest = SET_DEST (PATTERN (i3)); 2850 int offset = -1; 2851 int width = 0; 2852 2853 if (GET_CODE (dest) == ZERO_EXTRACT) 2854 { 2855 if (CONST_INT_P (XEXP (dest, 1)) 2856 && CONST_INT_P (XEXP (dest, 2))) 2857 { 2858 width = INTVAL (XEXP (dest, 1)); 2859 offset = INTVAL (XEXP (dest, 2)); 2860 dest = XEXP (dest, 0); 2861 if (BITS_BIG_ENDIAN) 2862 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset; 2863 } 2864 } 2865 else 2866 { 2867 if (GET_CODE (dest) == STRICT_LOW_PART) 2868 dest = XEXP (dest, 0); 2869 width = GET_MODE_PRECISION (GET_MODE (dest)); 2870 offset = 0; 2871 } 2872 2873 if (offset >= 0) 2874 { 2875 /* If this is the low part, we're done. */ 2876 if (subreg_lowpart_p (dest)) 2877 ; 2878 /* Handle the case where inner is twice the size of outer. */ 2879 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr))) 2880 == 2 * GET_MODE_PRECISION (GET_MODE (dest))) 2881 offset += GET_MODE_PRECISION (GET_MODE (dest)); 2882 /* Otherwise give up for now. */ 2883 else 2884 offset = -1; 2885 } 2886 2887 if (offset >= 0) 2888 { 2889 rtx inner = SET_SRC (PATTERN (i3)); 2890 rtx outer = SET_SRC (temp_expr); 2891 2892 wide_int o 2893 = wi::insert (rtx_mode_t (outer, GET_MODE (SET_DEST (temp_expr))), 2894 rtx_mode_t (inner, GET_MODE (dest)), 2895 offset, width); 2896 2897 combine_merges++; 2898 subst_insn = i3; 2899 subst_low_luid = DF_INSN_LUID (i2); 2900 added_sets_2 = added_sets_1 = added_sets_0 = 0; 2901 i2dest = SET_DEST (temp_expr); 2902 i2dest_killed = dead_or_set_p (i2, i2dest); 2903 2904 /* Replace the source in I2 with the new constant and make the 2905 resulting insn the new pattern for I3. Then skip to where we 2906 validate the pattern. Everything was set up above. */ 2907 SUBST (SET_SRC (temp_expr), 2908 immed_wide_int_const (o, GET_MODE (SET_DEST (temp_expr)))); 2909 2910 newpat = PATTERN (i2); 2911 2912 /* The dest of I3 has been replaced with the dest of I2. */ 2913 changed_i3_dest = 1; 2914 goto validate_replacement; 2915 } 2916 } 2917 2918 /* If we have no I1 and I2 looks like: 2919 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) 2920 (set Y OP)]) 2921 make up a dummy I1 that is 2922 (set Y OP) 2923 and change I2 to be 2924 (set (reg:CC X) (compare:CC Y (const_int 0))) 2925 2926 (We can ignore any trailing CLOBBERs.) 2927 2928 This undoes a previous combination and allows us to match a branch-and- 2929 decrement insn. */ 2930 2931 if (!HAVE_cc0 && i1 == 0 2932 && is_parallel_of_n_reg_sets (PATTERN (i2), 2) 2933 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) 2934 == MODE_CC) 2935 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE 2936 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx 2937 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), 2938 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))) 2939 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3) 2940 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)) 2941 { 2942 /* We make I1 with the same INSN_UID as I2. This gives it 2943 the same DF_INSN_LUID for value tracking. Our fake I1 will 2944 never appear in the insn stream so giving it the same INSN_UID 2945 as I2 will not cause a problem. */ 2946 2947 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2), 2948 XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2), 2949 -1, NULL_RTX); 2950 INSN_UID (i1) = INSN_UID (i2); 2951 2952 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); 2953 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), 2954 SET_DEST (PATTERN (i1))); 2955 unsigned int regno = REGNO (SET_DEST (PATTERN (i1))); 2956 SUBST_LINK (LOG_LINKS (i2), 2957 alloc_insn_link (i1, regno, LOG_LINKS (i2))); 2958 } 2959 2960 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs), 2961 make those two SETs separate I1 and I2 insns, and make an I0 that is 2962 the original I1. */ 2963 if (!HAVE_cc0 && i0 == 0 2964 && is_parallel_of_n_reg_sets (PATTERN (i2), 2) 2965 && can_split_parallel_of_n_reg_sets (i2, 2) 2966 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3) 2967 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3) 2968 && !find_reg_note (i2, REG_UNUSED, 0)) 2969 { 2970 /* If there is no I1, there is no I0 either. */ 2971 i0 = i1; 2972 2973 /* We make I1 with the same INSN_UID as I2. This gives it 2974 the same DF_INSN_LUID for value tracking. Our fake I1 will 2975 never appear in the insn stream so giving it the same INSN_UID 2976 as I2 will not cause a problem. */ 2977 2978 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2), 2979 XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2), 2980 -1, NULL_RTX); 2981 INSN_UID (i1) = INSN_UID (i2); 2982 2983 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1)); 2984 } 2985 2986 /* Verify that I2 and I1 are valid for combining. */ 2987 if (! can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src) 2988 || (i1 && ! can_combine_p (i1, i3, i0, NULL, i2, NULL, 2989 &i1dest, &i1src)) 2990 || (i0 && ! can_combine_p (i0, i3, NULL, NULL, i1, i2, 2991 &i0dest, &i0src))) 2992 { 2993 undo_all (); 2994 return 0; 2995 } 2996 2997 /* Record whether I2DEST is used in I2SRC and similarly for the other 2998 cases. Knowing this will help in register status updating below. */ 2999 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); 3000 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); 3001 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); 3002 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src); 3003 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src); 3004 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src); 3005 i2dest_killed = dead_or_set_p (i2, i2dest); 3006 i1dest_killed = i1 && dead_or_set_p (i1, i1dest); 3007 i0dest_killed = i0 && dead_or_set_p (i0, i0dest); 3008 3009 /* For the earlier insns, determine which of the subsequent ones they 3010 feed. */ 3011 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2); 3012 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1); 3013 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2) 3014 : (!reg_overlap_mentioned_p (i1dest, i0dest) 3015 && reg_overlap_mentioned_p (i0dest, i2src)))); 3016 3017 /* Ensure that I3's pattern can be the destination of combines. */ 3018 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest, 3019 i1 && i2dest_in_i1src && !i1_feeds_i2_n, 3020 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n) 3021 || (i1dest_in_i0src && !i0_feeds_i1_n)), 3022 &i3dest_killed)) 3023 { 3024 undo_all (); 3025 return 0; 3026 } 3027 3028 /* See if any of the insns is a MULT operation. Unless one is, we will 3029 reject a combination that is, since it must be slower. Be conservative 3030 here. */ 3031 if (GET_CODE (i2src) == MULT 3032 || (i1 != 0 && GET_CODE (i1src) == MULT) 3033 || (i0 != 0 && GET_CODE (i0src) == MULT) 3034 || (GET_CODE (PATTERN (i3)) == SET 3035 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) 3036 have_mult = 1; 3037 3038 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. 3039 We used to do this EXCEPT in one case: I3 has a post-inc in an 3040 output operand. However, that exception can give rise to insns like 3041 mov r3,(r3)+ 3042 which is a famous insn on the PDP-11 where the value of r3 used as the 3043 source was model-dependent. Avoid this sort of thing. */ 3044 3045 #if 0 3046 if (!(GET_CODE (PATTERN (i3)) == SET 3047 && REG_P (SET_SRC (PATTERN (i3))) 3048 && MEM_P (SET_DEST (PATTERN (i3))) 3049 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC 3050 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) 3051 /* It's not the exception. */ 3052 #endif 3053 if (AUTO_INC_DEC) 3054 { 3055 rtx link; 3056 for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) 3057 if (REG_NOTE_KIND (link) == REG_INC 3058 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) 3059 || (i1 != 0 3060 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) 3061 { 3062 undo_all (); 3063 return 0; 3064 } 3065 } 3066 3067 /* See if the SETs in I1 or I2 need to be kept around in the merged 3068 instruction: whenever the value set there is still needed past I3. 3069 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3. 3070 3071 For the SET in I1, we have two cases: if I1 and I2 independently feed 3072 into I3, the set in I1 needs to be kept around unless I1DEST dies 3073 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set 3074 in I1 needs to be kept around unless I1DEST dies or is set in either 3075 I2 or I3. The same considerations apply to I0. */ 3076 3077 added_sets_2 = !dead_or_set_p (i3, i2dest); 3078 3079 if (i1) 3080 added_sets_1 = !(dead_or_set_p (i3, i1dest) 3081 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest))); 3082 else 3083 added_sets_1 = 0; 3084 3085 if (i0) 3086 added_sets_0 = !(dead_or_set_p (i3, i0dest) 3087 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)) 3088 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) 3089 && dead_or_set_p (i2, i0dest))); 3090 else 3091 added_sets_0 = 0; 3092 3093 /* We are about to copy insns for the case where they need to be kept 3094 around. Check that they can be copied in the merged instruction. */ 3095 3096 if (targetm.cannot_copy_insn_p 3097 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2)) 3098 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1)) 3099 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0)))) 3100 { 3101 undo_all (); 3102 return 0; 3103 } 3104 3105 /* If the set in I2 needs to be kept around, we must make a copy of 3106 PATTERN (I2), so that when we substitute I1SRC for I1DEST in 3107 PATTERN (I2), we are only substituting for the original I1DEST, not into 3108 an already-substituted copy. This also prevents making self-referential 3109 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to 3110 I2DEST. */ 3111 3112 if (added_sets_2) 3113 { 3114 if (GET_CODE (PATTERN (i2)) == PARALLEL) 3115 i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src)); 3116 else 3117 i2pat = copy_rtx (PATTERN (i2)); 3118 } 3119 3120 if (added_sets_1) 3121 { 3122 if (GET_CODE (PATTERN (i1)) == PARALLEL) 3123 i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src)); 3124 else 3125 i1pat = copy_rtx (PATTERN (i1)); 3126 } 3127 3128 if (added_sets_0) 3129 { 3130 if (GET_CODE (PATTERN (i0)) == PARALLEL) 3131 i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src)); 3132 else 3133 i0pat = copy_rtx (PATTERN (i0)); 3134 } 3135 3136 combine_merges++; 3137 3138 /* Substitute in the latest insn for the regs set by the earlier ones. */ 3139 3140 maxreg = max_reg_num (); 3141 3142 subst_insn = i3; 3143 3144 /* Many machines that don't use CC0 have insns that can both perform an 3145 arithmetic operation and set the condition code. These operations will 3146 be represented as a PARALLEL with the first element of the vector 3147 being a COMPARE of an arithmetic operation with the constant zero. 3148 The second element of the vector will set some pseudo to the result 3149 of the same arithmetic operation. If we simplify the COMPARE, we won't 3150 match such a pattern and so will generate an extra insn. Here we test 3151 for this case, where both the comparison and the operation result are 3152 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with 3153 I2SRC. Later we will make the PARALLEL that contains I2. */ 3154 3155 if (!HAVE_cc0 && i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET 3156 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE 3157 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1)) 3158 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) 3159 { 3160 rtx newpat_dest; 3161 rtx *cc_use_loc = NULL; 3162 rtx_insn *cc_use_insn = NULL; 3163 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1); 3164 machine_mode compare_mode, orig_compare_mode; 3165 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN; 3166 3167 newpat = PATTERN (i3); 3168 newpat_dest = SET_DEST (newpat); 3169 compare_mode = orig_compare_mode = GET_MODE (newpat_dest); 3170 3171 if (undobuf.other_insn == 0 3172 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3, 3173 &cc_use_insn))) 3174 { 3175 compare_code = orig_compare_code = GET_CODE (*cc_use_loc); 3176 compare_code = simplify_compare_const (compare_code, 3177 GET_MODE (i2dest), op0, &op1); 3178 target_canonicalize_comparison (&compare_code, &op0, &op1, 1); 3179 } 3180 3181 /* Do the rest only if op1 is const0_rtx, which may be the 3182 result of simplification. */ 3183 if (op1 == const0_rtx) 3184 { 3185 /* If a single use of the CC is found, prepare to modify it 3186 when SELECT_CC_MODE returns a new CC-class mode, or when 3187 the above simplify_compare_const() returned a new comparison 3188 operator. undobuf.other_insn is assigned the CC use insn 3189 when modifying it. */ 3190 if (cc_use_loc) 3191 { 3192 #ifdef SELECT_CC_MODE 3193 machine_mode new_mode 3194 = SELECT_CC_MODE (compare_code, op0, op1); 3195 if (new_mode != orig_compare_mode 3196 && can_change_dest_mode (SET_DEST (newpat), 3197 added_sets_2, new_mode)) 3198 { 3199 unsigned int regno = REGNO (newpat_dest); 3200 compare_mode = new_mode; 3201 if (regno < FIRST_PSEUDO_REGISTER) 3202 newpat_dest = gen_rtx_REG (compare_mode, regno); 3203 else 3204 { 3205 SUBST_MODE (regno_reg_rtx[regno], compare_mode); 3206 newpat_dest = regno_reg_rtx[regno]; 3207 } 3208 } 3209 #endif 3210 /* Cases for modifying the CC-using comparison. */ 3211 if (compare_code != orig_compare_code 3212 /* ??? Do we need to verify the zero rtx? */ 3213 && XEXP (*cc_use_loc, 1) == const0_rtx) 3214 { 3215 /* Replace cc_use_loc with entire new RTX. */ 3216 SUBST (*cc_use_loc, 3217 gen_rtx_fmt_ee (compare_code, compare_mode, 3218 newpat_dest, const0_rtx)); 3219 undobuf.other_insn = cc_use_insn; 3220 } 3221 else if (compare_mode != orig_compare_mode) 3222 { 3223 /* Just replace the CC reg with a new mode. */ 3224 SUBST (XEXP (*cc_use_loc, 0), newpat_dest); 3225 undobuf.other_insn = cc_use_insn; 3226 } 3227 } 3228 3229 /* Now we modify the current newpat: 3230 First, SET_DEST(newpat) is updated if the CC mode has been 3231 altered. For targets without SELECT_CC_MODE, this should be 3232 optimized away. */ 3233 if (compare_mode != orig_compare_mode) 3234 SUBST (SET_DEST (newpat), newpat_dest); 3235 /* This is always done to propagate i2src into newpat. */ 3236 SUBST (SET_SRC (newpat), 3237 gen_rtx_COMPARE (compare_mode, op0, op1)); 3238 /* Create new version of i2pat if needed; the below PARALLEL 3239 creation needs this to work correctly. */ 3240 if (! rtx_equal_p (i2src, op0)) 3241 i2pat = gen_rtx_SET (i2dest, op0); 3242 i2_is_used = 1; 3243 } 3244 } 3245 3246 if (i2_is_used == 0) 3247 { 3248 /* It is possible that the source of I2 or I1 may be performing 3249 an unneeded operation, such as a ZERO_EXTEND of something 3250 that is known to have the high part zero. Handle that case 3251 by letting subst look at the inner insns. 3252 3253 Another way to do this would be to have a function that tries 3254 to simplify a single insn instead of merging two or more 3255 insns. We don't do this because of the potential of infinite 3256 loops and because of the potential extra memory required. 3257 However, doing it the way we are is a bit of a kludge and 3258 doesn't catch all cases. 3259 3260 But only do this if -fexpensive-optimizations since it slows 3261 things down and doesn't usually win. 3262 3263 This is not done in the COMPARE case above because the 3264 unmodified I2PAT is used in the PARALLEL and so a pattern 3265 with a modified I2SRC would not match. */ 3266 3267 if (flag_expensive_optimizations) 3268 { 3269 /* Pass pc_rtx so no substitutions are done, just 3270 simplifications. */ 3271 if (i1) 3272 { 3273 subst_low_luid = DF_INSN_LUID (i1); 3274 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0); 3275 } 3276 3277 subst_low_luid = DF_INSN_LUID (i2); 3278 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); 3279 } 3280 3281 n_occurrences = 0; /* `subst' counts here */ 3282 subst_low_luid = DF_INSN_LUID (i2); 3283 3284 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique 3285 copy of I2SRC each time we substitute it, in order to avoid creating 3286 self-referential RTL when we will be substituting I1SRC for I1DEST 3287 later. Likewise if I0 feeds into I2, either directly or indirectly 3288 through I1, and I0DEST is in I0SRC. */ 3289 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0, 3290 (i1_feeds_i2_n && i1dest_in_i1src) 3291 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) 3292 && i0dest_in_i0src)); 3293 substed_i2 = 1; 3294 3295 /* Record whether I2's body now appears within I3's body. */ 3296 i2_is_used = n_occurrences; 3297 } 3298 3299 /* If we already got a failure, don't try to do more. Otherwise, try to 3300 substitute I1 if we have it. */ 3301 3302 if (i1 && GET_CODE (newpat) != CLOBBER) 3303 { 3304 /* Check that an autoincrement side-effect on I1 has not been lost. 3305 This happens if I1DEST is mentioned in I2 and dies there, and 3306 has disappeared from the new pattern. */ 3307 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 3308 && i1_feeds_i2_n 3309 && dead_or_set_p (i2, i1dest) 3310 && !reg_overlap_mentioned_p (i1dest, newpat)) 3311 /* Before we can do this substitution, we must redo the test done 3312 above (see detailed comments there) that ensures I1DEST isn't 3313 mentioned in any SETs in NEWPAT that are field assignments. */ 3314 || !combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX, 3315 0, 0, 0)) 3316 { 3317 undo_all (); 3318 return 0; 3319 } 3320 3321 n_occurrences = 0; 3322 subst_low_luid = DF_INSN_LUID (i1); 3323 3324 /* If the following substitution will modify I1SRC, make a copy of it 3325 for the case where it is substituted for I1DEST in I2PAT later. */ 3326 if (added_sets_2 && i1_feeds_i2_n) 3327 i1src_copy = copy_rtx (i1src); 3328 3329 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique 3330 copy of I1SRC each time we substitute it, in order to avoid creating 3331 self-referential RTL when we will be substituting I0SRC for I0DEST 3332 later. */ 3333 newpat = subst (newpat, i1dest, i1src, 0, 0, 3334 i0_feeds_i1_n && i0dest_in_i0src); 3335 substed_i1 = 1; 3336 3337 /* Record whether I1's body now appears within I3's body. */ 3338 i1_is_used = n_occurrences; 3339 } 3340 3341 /* Likewise for I0 if we have it. */ 3342 3343 if (i0 && GET_CODE (newpat) != CLOBBER) 3344 { 3345 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0 3346 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest)) 3347 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))) 3348 && !reg_overlap_mentioned_p (i0dest, newpat)) 3349 || !combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX, 3350 0, 0, 0)) 3351 { 3352 undo_all (); 3353 return 0; 3354 } 3355 3356 /* If the following substitution will modify I0SRC, make a copy of it 3357 for the case where it is substituted for I0DEST in I1PAT later. */ 3358 if (added_sets_1 && i0_feeds_i1_n) 3359 i0src_copy = copy_rtx (i0src); 3360 /* And a copy for I0DEST in I2PAT substitution. */ 3361 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n) 3362 || (i0_feeds_i2_n))) 3363 i0src_copy2 = copy_rtx (i0src); 3364 3365 n_occurrences = 0; 3366 subst_low_luid = DF_INSN_LUID (i0); 3367 newpat = subst (newpat, i0dest, i0src, 0, 0, 0); 3368 substed_i0 = 1; 3369 } 3370 3371 /* Fail if an autoincrement side-effect has been duplicated. Be careful 3372 to count all the ways that I2SRC and I1SRC can be used. */ 3373 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 3374 && i2_is_used + added_sets_2 > 1) 3375 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 3376 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) 3377 > 1)) 3378 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0 3379 && (n_occurrences + added_sets_0 3380 + (added_sets_1 && i0_feeds_i1_n) 3381 + (added_sets_2 && i0_feeds_i2_n) 3382 > 1)) 3383 /* Fail if we tried to make a new register. */ 3384 || max_reg_num () != maxreg 3385 /* Fail if we couldn't do something and have a CLOBBER. */ 3386 || GET_CODE (newpat) == CLOBBER 3387 /* Fail if this new pattern is a MULT and we didn't have one before 3388 at the outer level. */ 3389 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT 3390 && ! have_mult)) 3391 { 3392 undo_all (); 3393 return 0; 3394 } 3395 3396 /* If the actions of the earlier insns must be kept 3397 in addition to substituting them into the latest one, 3398 we must make a new PARALLEL for the latest insn 3399 to hold additional the SETs. */ 3400 3401 if (added_sets_0 || added_sets_1 || added_sets_2) 3402 { 3403 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2; 3404 combine_extras++; 3405 3406 if (GET_CODE (newpat) == PARALLEL) 3407 { 3408 rtvec old = XVEC (newpat, 0); 3409 total_sets = XVECLEN (newpat, 0) + extra_sets; 3410 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 3411 memcpy (XVEC (newpat, 0)->elem, &old->elem[0], 3412 sizeof (old->elem[0]) * old->num_elem); 3413 } 3414 else 3415 { 3416 rtx old = newpat; 3417 total_sets = 1 + extra_sets; 3418 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 3419 XVECEXP (newpat, 0, 0) = old; 3420 } 3421 3422 if (added_sets_0) 3423 XVECEXP (newpat, 0, --total_sets) = i0pat; 3424 3425 if (added_sets_1) 3426 { 3427 rtx t = i1pat; 3428 if (i0_feeds_i1_n) 3429 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0); 3430 3431 XVECEXP (newpat, 0, --total_sets) = t; 3432 } 3433 if (added_sets_2) 3434 { 3435 rtx t = i2pat; 3436 if (i1_feeds_i2_n) 3437 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0, 3438 i0_feeds_i1_n && i0dest_in_i0src); 3439 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n) 3440 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0); 3441 3442 XVECEXP (newpat, 0, --total_sets) = t; 3443 } 3444 } 3445 3446 validate_replacement: 3447 3448 /* Note which hard regs this insn has as inputs. */ 3449 mark_used_regs_combine (newpat); 3450 3451 /* If recog_for_combine fails, it strips existing clobbers. If we'll 3452 consider splitting this pattern, we might need these clobbers. */ 3453 if (i1 && GET_CODE (newpat) == PARALLEL 3454 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER) 3455 { 3456 int len = XVECLEN (newpat, 0); 3457 3458 newpat_vec_with_clobbers = rtvec_alloc (len); 3459 for (i = 0; i < len; i++) 3460 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i); 3461 } 3462 3463 /* We have recognized nothing yet. */ 3464 insn_code_number = -1; 3465 3466 /* See if this is a PARALLEL of two SETs where one SET's destination is 3467 a register that is unused and this isn't marked as an instruction that 3468 might trap in an EH region. In that case, we just need the other SET. 3469 We prefer this over the PARALLEL. 3470 3471 This can occur when simplifying a divmod insn. We *must* test for this 3472 case here because the code below that splits two independent SETs doesn't 3473 handle this case correctly when it updates the register status. 3474 3475 It's pointless doing this if we originally had two sets, one from 3476 i3, and one from i2. Combining then splitting the parallel results 3477 in the original i2 again plus an invalid insn (which we delete). 3478 The net effect is only to move instructions around, which makes 3479 debug info less accurate. */ 3480 3481 if (!(added_sets_2 && i1 == 0) 3482 && is_parallel_of_n_reg_sets (newpat, 2) 3483 && asm_noperands (newpat) < 0) 3484 { 3485 rtx set0 = XVECEXP (newpat, 0, 0); 3486 rtx set1 = XVECEXP (newpat, 0, 1); 3487 rtx oldpat = newpat; 3488 3489 if (((REG_P (SET_DEST (set1)) 3490 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1))) 3491 || (GET_CODE (SET_DEST (set1)) == SUBREG 3492 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1))))) 3493 && insn_nothrow_p (i3) 3494 && !side_effects_p (SET_SRC (set1))) 3495 { 3496 newpat = set0; 3497 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3498 } 3499 3500 else if (((REG_P (SET_DEST (set0)) 3501 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0))) 3502 || (GET_CODE (SET_DEST (set0)) == SUBREG 3503 && find_reg_note (i3, REG_UNUSED, 3504 SUBREG_REG (SET_DEST (set0))))) 3505 && insn_nothrow_p (i3) 3506 && !side_effects_p (SET_SRC (set0))) 3507 { 3508 newpat = set1; 3509 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3510 3511 if (insn_code_number >= 0) 3512 changed_i3_dest = 1; 3513 } 3514 3515 if (insn_code_number < 0) 3516 newpat = oldpat; 3517 } 3518 3519 /* Is the result of combination a valid instruction? */ 3520 if (insn_code_number < 0) 3521 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3522 3523 /* If we were combining three insns and the result is a simple SET 3524 with no ASM_OPERANDS that wasn't recognized, try to split it into two 3525 insns. There are two ways to do this. It can be split using a 3526 machine-specific method (like when you have an addition of a large 3527 constant) or by combine in the function find_split_point. */ 3528 3529 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET 3530 && asm_noperands (newpat) < 0) 3531 { 3532 rtx parallel, *split; 3533 rtx_insn *m_split_insn; 3534 3535 /* See if the MD file can split NEWPAT. If it can't, see if letting it 3536 use I2DEST as a scratch register will help. In the latter case, 3537 convert I2DEST to the mode of the source of NEWPAT if we can. */ 3538 3539 m_split_insn = combine_split_insns (newpat, i3); 3540 3541 /* We can only use I2DEST as a scratch reg if it doesn't overlap any 3542 inputs of NEWPAT. */ 3543 3544 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be 3545 possible to try that as a scratch reg. This would require adding 3546 more code to make it work though. */ 3547 3548 if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat)) 3549 { 3550 machine_mode new_mode = GET_MODE (SET_DEST (newpat)); 3551 3552 /* ??? Reusing i2dest without resetting the reg_stat entry for it 3553 (temporarily, until we are committed to this instruction 3554 combination) does not work: for example, any call to nonzero_bits 3555 on the register (from a splitter in the MD file, for example) 3556 will get the old information, which is invalid. 3557 3558 Since nowadays we can create registers during combine just fine, 3559 we should just create a new one here, not reuse i2dest. */ 3560 3561 /* First try to split using the original register as a 3562 scratch register. */ 3563 parallel = gen_rtx_PARALLEL (VOIDmode, 3564 gen_rtvec (2, newpat, 3565 gen_rtx_CLOBBER (VOIDmode, 3566 i2dest))); 3567 m_split_insn = combine_split_insns (parallel, i3); 3568 3569 /* If that didn't work, try changing the mode of I2DEST if 3570 we can. */ 3571 if (m_split_insn == 0 3572 && new_mode != GET_MODE (i2dest) 3573 && new_mode != VOIDmode 3574 && can_change_dest_mode (i2dest, added_sets_2, new_mode)) 3575 { 3576 machine_mode old_mode = GET_MODE (i2dest); 3577 rtx ni2dest; 3578 3579 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) 3580 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest)); 3581 else 3582 { 3583 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode); 3584 ni2dest = regno_reg_rtx[REGNO (i2dest)]; 3585 } 3586 3587 parallel = (gen_rtx_PARALLEL 3588 (VOIDmode, 3589 gen_rtvec (2, newpat, 3590 gen_rtx_CLOBBER (VOIDmode, 3591 ni2dest)))); 3592 m_split_insn = combine_split_insns (parallel, i3); 3593 3594 if (m_split_insn == 0 3595 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 3596 { 3597 struct undo *buf; 3598 3599 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode); 3600 buf = undobuf.undos; 3601 undobuf.undos = buf->next; 3602 buf->next = undobuf.frees; 3603 undobuf.frees = buf; 3604 } 3605 } 3606 3607 i2scratch = m_split_insn != 0; 3608 } 3609 3610 /* If recog_for_combine has discarded clobbers, try to use them 3611 again for the split. */ 3612 if (m_split_insn == 0 && newpat_vec_with_clobbers) 3613 { 3614 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers); 3615 m_split_insn = combine_split_insns (parallel, i3); 3616 } 3617 3618 if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX) 3619 { 3620 rtx m_split_pat = PATTERN (m_split_insn); 3621 insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes); 3622 if (insn_code_number >= 0) 3623 newpat = m_split_pat; 3624 } 3625 else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX 3626 && (next_nonnote_nondebug_insn (i2) == i3 3627 || ! use_crosses_set_p (PATTERN (m_split_insn), DF_INSN_LUID (i2)))) 3628 { 3629 rtx i2set, i3set; 3630 rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn)); 3631 newi2pat = PATTERN (m_split_insn); 3632 3633 i3set = single_set (NEXT_INSN (m_split_insn)); 3634 i2set = single_set (m_split_insn); 3635 3636 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3637 3638 /* If I2 or I3 has multiple SETs, we won't know how to track 3639 register status, so don't use these insns. If I2's destination 3640 is used between I2 and I3, we also can't use these insns. */ 3641 3642 if (i2_code_number >= 0 && i2set && i3set 3643 && (next_nonnote_nondebug_insn (i2) == i3 3644 || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) 3645 insn_code_number = recog_for_combine (&newi3pat, i3, 3646 &new_i3_notes); 3647 if (insn_code_number >= 0) 3648 newpat = newi3pat; 3649 3650 /* It is possible that both insns now set the destination of I3. 3651 If so, we must show an extra use of it. */ 3652 3653 if (insn_code_number >= 0) 3654 { 3655 rtx new_i3_dest = SET_DEST (i3set); 3656 rtx new_i2_dest = SET_DEST (i2set); 3657 3658 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT 3659 || GET_CODE (new_i3_dest) == STRICT_LOW_PART 3660 || GET_CODE (new_i3_dest) == SUBREG) 3661 new_i3_dest = XEXP (new_i3_dest, 0); 3662 3663 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT 3664 || GET_CODE (new_i2_dest) == STRICT_LOW_PART 3665 || GET_CODE (new_i2_dest) == SUBREG) 3666 new_i2_dest = XEXP (new_i2_dest, 0); 3667 3668 if (REG_P (new_i3_dest) 3669 && REG_P (new_i2_dest) 3670 && REGNO (new_i3_dest) == REGNO (new_i2_dest) 3671 && REGNO (new_i2_dest) < reg_n_sets_max) 3672 INC_REG_N_SETS (REGNO (new_i2_dest), 1); 3673 } 3674 } 3675 3676 /* If we can split it and use I2DEST, go ahead and see if that 3677 helps things be recognized. Verify that none of the registers 3678 are set between I2 and I3. */ 3679 if (insn_code_number < 0 3680 && (split = find_split_point (&newpat, i3, false)) != 0 3681 && (!HAVE_cc0 || REG_P (i2dest)) 3682 /* We need I2DEST in the proper mode. If it is a hard register 3683 or the only use of a pseudo, we can change its mode. 3684 Make sure we don't change a hard register to have a mode that 3685 isn't valid for it, or change the number of registers. */ 3686 && (GET_MODE (*split) == GET_MODE (i2dest) 3687 || GET_MODE (*split) == VOIDmode 3688 || can_change_dest_mode (i2dest, added_sets_2, 3689 GET_MODE (*split))) 3690 && (next_nonnote_nondebug_insn (i2) == i3 3691 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2))) 3692 /* We can't overwrite I2DEST if its value is still used by 3693 NEWPAT. */ 3694 && ! reg_referenced_p (i2dest, newpat)) 3695 { 3696 rtx newdest = i2dest; 3697 enum rtx_code split_code = GET_CODE (*split); 3698 machine_mode split_mode = GET_MODE (*split); 3699 bool subst_done = false; 3700 newi2pat = NULL_RTX; 3701 3702 i2scratch = true; 3703 3704 /* *SPLIT may be part of I2SRC, so make sure we have the 3705 original expression around for later debug processing. 3706 We should not need I2SRC any more in other cases. */ 3707 if (MAY_HAVE_DEBUG_INSNS) 3708 i2src = copy_rtx (i2src); 3709 else 3710 i2src = NULL; 3711 3712 /* Get NEWDEST as a register in the proper mode. We have already 3713 validated that we can do this. */ 3714 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) 3715 { 3716 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) 3717 newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); 3718 else 3719 { 3720 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode); 3721 newdest = regno_reg_rtx[REGNO (i2dest)]; 3722 } 3723 } 3724 3725 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to 3726 an ASHIFT. This can occur if it was inside a PLUS and hence 3727 appeared to be a memory address. This is a kludge. */ 3728 if (split_code == MULT 3729 && CONST_INT_P (XEXP (*split, 1)) 3730 && INTVAL (XEXP (*split, 1)) > 0 3731 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0) 3732 { 3733 SUBST (*split, gen_rtx_ASHIFT (split_mode, 3734 XEXP (*split, 0), GEN_INT (i))); 3735 /* Update split_code because we may not have a multiply 3736 anymore. */ 3737 split_code = GET_CODE (*split); 3738 } 3739 3740 /* Similarly for (plus (mult FOO (const_int pow2))). */ 3741 if (split_code == PLUS 3742 && GET_CODE (XEXP (*split, 0)) == MULT 3743 && CONST_INT_P (XEXP (XEXP (*split, 0), 1)) 3744 && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0 3745 && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0) 3746 { 3747 rtx nsplit = XEXP (*split, 0); 3748 SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit), 3749 XEXP (nsplit, 0), GEN_INT (i))); 3750 /* Update split_code because we may not have a multiply 3751 anymore. */ 3752 split_code = GET_CODE (*split); 3753 } 3754 3755 #ifdef INSN_SCHEDULING 3756 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should 3757 be written as a ZERO_EXTEND. */ 3758 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))) 3759 { 3760 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's 3761 what it really is. */ 3762 if (load_extend_op (GET_MODE (SUBREG_REG (*split))) 3763 == SIGN_EXTEND) 3764 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, 3765 SUBREG_REG (*split))); 3766 else 3767 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, 3768 SUBREG_REG (*split))); 3769 } 3770 #endif 3771 3772 /* Attempt to split binary operators using arithmetic identities. */ 3773 if (BINARY_P (SET_SRC (newpat)) 3774 && split_mode == GET_MODE (SET_SRC (newpat)) 3775 && ! side_effects_p (SET_SRC (newpat))) 3776 { 3777 rtx setsrc = SET_SRC (newpat); 3778 machine_mode mode = GET_MODE (setsrc); 3779 enum rtx_code code = GET_CODE (setsrc); 3780 rtx src_op0 = XEXP (setsrc, 0); 3781 rtx src_op1 = XEXP (setsrc, 1); 3782 3783 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */ 3784 if (rtx_equal_p (src_op0, src_op1)) 3785 { 3786 newi2pat = gen_rtx_SET (newdest, src_op0); 3787 SUBST (XEXP (setsrc, 0), newdest); 3788 SUBST (XEXP (setsrc, 1), newdest); 3789 subst_done = true; 3790 } 3791 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */ 3792 else if ((code == PLUS || code == MULT) 3793 && GET_CODE (src_op0) == code 3794 && GET_CODE (XEXP (src_op0, 0)) == code 3795 && (INTEGRAL_MODE_P (mode) 3796 || (FLOAT_MODE_P (mode) 3797 && flag_unsafe_math_optimizations))) 3798 { 3799 rtx p = XEXP (XEXP (src_op0, 0), 0); 3800 rtx q = XEXP (XEXP (src_op0, 0), 1); 3801 rtx r = XEXP (src_op0, 1); 3802 rtx s = src_op1; 3803 3804 /* Split both "((X op Y) op X) op Y" and 3805 "((X op Y) op Y) op X" as "T op T" where T is 3806 "X op Y". */ 3807 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s)) 3808 || (rtx_equal_p (p,s) && rtx_equal_p (q,r))) 3809 { 3810 newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0)); 3811 SUBST (XEXP (setsrc, 0), newdest); 3812 SUBST (XEXP (setsrc, 1), newdest); 3813 subst_done = true; 3814 } 3815 /* Split "((X op X) op Y) op Y)" as "T op T" where 3816 T is "X op Y". */ 3817 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s)) 3818 { 3819 rtx tmp = simplify_gen_binary (code, mode, p, r); 3820 newi2pat = gen_rtx_SET (newdest, tmp); 3821 SUBST (XEXP (setsrc, 0), newdest); 3822 SUBST (XEXP (setsrc, 1), newdest); 3823 subst_done = true; 3824 } 3825 } 3826 } 3827 3828 if (!subst_done) 3829 { 3830 newi2pat = gen_rtx_SET (newdest, *split); 3831 SUBST (*split, newdest); 3832 } 3833 3834 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3835 3836 /* recog_for_combine might have added CLOBBERs to newi2pat. 3837 Make sure NEWPAT does not depend on the clobbered regs. */ 3838 if (GET_CODE (newi2pat) == PARALLEL) 3839 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) 3840 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) 3841 { 3842 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); 3843 if (reg_overlap_mentioned_p (reg, newpat)) 3844 { 3845 undo_all (); 3846 return 0; 3847 } 3848 } 3849 3850 /* If the split point was a MULT and we didn't have one before, 3851 don't use one now. */ 3852 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) 3853 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3854 } 3855 } 3856 3857 /* Check for a case where we loaded from memory in a narrow mode and 3858 then sign extended it, but we need both registers. In that case, 3859 we have a PARALLEL with both loads from the same memory location. 3860 We can split this into a load from memory followed by a register-register 3861 copy. This saves at least one insn, more if register allocation can 3862 eliminate the copy. 3863 3864 We cannot do this if the destination of the first assignment is a 3865 condition code register or cc0. We eliminate this case by making sure 3866 the SET_DEST and SET_SRC have the same mode. 3867 3868 We cannot do this if the destination of the second assignment is 3869 a register that we have already assumed is zero-extended. Similarly 3870 for a SUBREG of such a register. */ 3871 3872 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 3873 && GET_CODE (newpat) == PARALLEL 3874 && XVECLEN (newpat, 0) == 2 3875 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 3876 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND 3877 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) 3878 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) 3879 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 3880 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), 3881 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) 3882 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 3883 DF_INSN_LUID (i2)) 3884 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 3885 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 3886 && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)), 3887 (REG_P (temp_expr) 3888 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0 3889 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD 3890 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT 3891 && (reg_stat[REGNO (temp_expr)].nonzero_bits 3892 != GET_MODE_MASK (word_mode)))) 3893 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG 3894 && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), 3895 (REG_P (temp_expr) 3896 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0 3897 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD 3898 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT 3899 && (reg_stat[REGNO (temp_expr)].nonzero_bits 3900 != GET_MODE_MASK (word_mode))))) 3901 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), 3902 SET_SRC (XVECEXP (newpat, 0, 1))) 3903 && ! find_reg_note (i3, REG_UNUSED, 3904 SET_DEST (XVECEXP (newpat, 0, 0)))) 3905 { 3906 rtx ni2dest; 3907 3908 newi2pat = XVECEXP (newpat, 0, 0); 3909 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); 3910 newpat = XVECEXP (newpat, 0, 1); 3911 SUBST (SET_SRC (newpat), 3912 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest)); 3913 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3914 3915 if (i2_code_number >= 0) 3916 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3917 3918 if (insn_code_number >= 0) 3919 swap_i2i3 = 1; 3920 } 3921 3922 /* Similarly, check for a case where we have a PARALLEL of two independent 3923 SETs but we started with three insns. In this case, we can do the sets 3924 as two separate insns. This case occurs when some SET allows two 3925 other insns to combine, but the destination of that SET is still live. 3926 3927 Also do this if we started with two insns and (at least) one of the 3928 resulting sets is a noop; this noop will be deleted later. */ 3929 3930 else if (insn_code_number < 0 && asm_noperands (newpat) < 0 3931 && GET_CODE (newpat) == PARALLEL 3932 && XVECLEN (newpat, 0) == 2 3933 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 3934 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 3935 && (i1 || set_noop_p (XVECEXP (newpat, 0, 0)) 3936 || set_noop_p (XVECEXP (newpat, 0, 1))) 3937 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT 3938 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART 3939 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 3940 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 3941 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), 3942 XVECEXP (newpat, 0, 0)) 3943 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), 3944 XVECEXP (newpat, 0, 1)) 3945 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) 3946 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) 3947 { 3948 rtx set0 = XVECEXP (newpat, 0, 0); 3949 rtx set1 = XVECEXP (newpat, 0, 1); 3950 3951 /* Normally, it doesn't matter which of the two is done first, 3952 but the one that references cc0 can't be the second, and 3953 one which uses any regs/memory set in between i2 and i3 can't 3954 be first. The PARALLEL might also have been pre-existing in i3, 3955 so we need to make sure that we won't wrongly hoist a SET to i2 3956 that would conflict with a death note present in there. */ 3957 if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2)) 3958 && !(REG_P (SET_DEST (set1)) 3959 && find_reg_note (i2, REG_DEAD, SET_DEST (set1))) 3960 && !(GET_CODE (SET_DEST (set1)) == SUBREG 3961 && find_reg_note (i2, REG_DEAD, 3962 SUBREG_REG (SET_DEST (set1)))) 3963 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set0)) 3964 /* If I3 is a jump, ensure that set0 is a jump so that 3965 we do not create invalid RTL. */ 3966 && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx) 3967 ) 3968 { 3969 newi2pat = set1; 3970 newpat = set0; 3971 } 3972 else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2)) 3973 && !(REG_P (SET_DEST (set0)) 3974 && find_reg_note (i2, REG_DEAD, SET_DEST (set0))) 3975 && !(GET_CODE (SET_DEST (set0)) == SUBREG 3976 && find_reg_note (i2, REG_DEAD, 3977 SUBREG_REG (SET_DEST (set0)))) 3978 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set1)) 3979 /* If I3 is a jump, ensure that set1 is a jump so that 3980 we do not create invalid RTL. */ 3981 && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx) 3982 ) 3983 { 3984 newi2pat = set0; 3985 newpat = set1; 3986 } 3987 else 3988 { 3989 undo_all (); 3990 return 0; 3991 } 3992 3993 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3994 3995 if (i2_code_number >= 0) 3996 { 3997 /* recog_for_combine might have added CLOBBERs to newi2pat. 3998 Make sure NEWPAT does not depend on the clobbered regs. */ 3999 if (GET_CODE (newi2pat) == PARALLEL) 4000 { 4001 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) 4002 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) 4003 { 4004 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); 4005 if (reg_overlap_mentioned_p (reg, newpat)) 4006 { 4007 undo_all (); 4008 return 0; 4009 } 4010 } 4011 } 4012 4013 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 4014 } 4015 } 4016 4017 /* If it still isn't recognized, fail and change things back the way they 4018 were. */ 4019 if ((insn_code_number < 0 4020 /* Is the result a reasonable ASM_OPERANDS? */ 4021 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) 4022 { 4023 undo_all (); 4024 return 0; 4025 } 4026 4027 /* If we had to change another insn, make sure it is valid also. */ 4028 if (undobuf.other_insn) 4029 { 4030 CLEAR_HARD_REG_SET (newpat_used_regs); 4031 4032 other_pat = PATTERN (undobuf.other_insn); 4033 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, 4034 &new_other_notes); 4035 4036 if (other_code_number < 0 && ! check_asm_operands (other_pat)) 4037 { 4038 undo_all (); 4039 return 0; 4040 } 4041 } 4042 4043 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether 4044 they are adjacent to each other or not. */ 4045 if (HAVE_cc0) 4046 { 4047 rtx_insn *p = prev_nonnote_insn (i3); 4048 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat 4049 && sets_cc0_p (newi2pat)) 4050 { 4051 undo_all (); 4052 return 0; 4053 } 4054 } 4055 4056 /* Only allow this combination if insn_rtx_costs reports that the 4057 replacement instructions are cheaper than the originals. */ 4058 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat)) 4059 { 4060 undo_all (); 4061 return 0; 4062 } 4063 4064 if (MAY_HAVE_DEBUG_INSNS) 4065 { 4066 struct undo *undo; 4067 4068 for (undo = undobuf.undos; undo; undo = undo->next) 4069 if (undo->kind == UNDO_MODE) 4070 { 4071 rtx reg = *undo->where.r; 4072 machine_mode new_mode = GET_MODE (reg); 4073 machine_mode old_mode = undo->old_contents.m; 4074 4075 /* Temporarily revert mode back. */ 4076 adjust_reg_mode (reg, old_mode); 4077 4078 if (reg == i2dest && i2scratch) 4079 { 4080 /* If we used i2dest as a scratch register with a 4081 different mode, substitute it for the original 4082 i2src while its original mode is temporarily 4083 restored, and then clear i2scratch so that we don't 4084 do it again later. */ 4085 propagate_for_debug (i2, last_combined_insn, reg, i2src, 4086 this_basic_block); 4087 i2scratch = false; 4088 /* Put back the new mode. */ 4089 adjust_reg_mode (reg, new_mode); 4090 } 4091 else 4092 { 4093 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg)); 4094 rtx_insn *first, *last; 4095 4096 if (reg == i2dest) 4097 { 4098 first = i2; 4099 last = last_combined_insn; 4100 } 4101 else 4102 { 4103 first = i3; 4104 last = undobuf.other_insn; 4105 gcc_assert (last); 4106 if (DF_INSN_LUID (last) 4107 < DF_INSN_LUID (last_combined_insn)) 4108 last = last_combined_insn; 4109 } 4110 4111 /* We're dealing with a reg that changed mode but not 4112 meaning, so we want to turn it into a subreg for 4113 the new mode. However, because of REG sharing and 4114 because its mode had already changed, we have to do 4115 it in two steps. First, replace any debug uses of 4116 reg, with its original mode temporarily restored, 4117 with this copy we have created; then, replace the 4118 copy with the SUBREG of the original shared reg, 4119 once again changed to the new mode. */ 4120 propagate_for_debug (first, last, reg, tempreg, 4121 this_basic_block); 4122 adjust_reg_mode (reg, new_mode); 4123 propagate_for_debug (first, last, tempreg, 4124 lowpart_subreg (old_mode, reg, new_mode), 4125 this_basic_block); 4126 } 4127 } 4128 } 4129 4130 /* If we will be able to accept this, we have made a 4131 change to the destination of I3. This requires us to 4132 do a few adjustments. */ 4133 4134 if (changed_i3_dest) 4135 { 4136 PATTERN (i3) = newpat; 4137 adjust_for_new_dest (i3); 4138 } 4139 4140 /* We now know that we can do this combination. Merge the insns and 4141 update the status of registers and LOG_LINKS. */ 4142 4143 if (undobuf.other_insn) 4144 { 4145 rtx note, next; 4146 4147 PATTERN (undobuf.other_insn) = other_pat; 4148 4149 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED, 4150 ensure that they are still valid. Then add any non-duplicate 4151 notes added by recog_for_combine. */ 4152 for (note = REG_NOTES (undobuf.other_insn); note; note = next) 4153 { 4154 next = XEXP (note, 1); 4155 4156 if ((REG_NOTE_KIND (note) == REG_DEAD 4157 && !reg_referenced_p (XEXP (note, 0), 4158 PATTERN (undobuf.other_insn))) 4159 ||(REG_NOTE_KIND (note) == REG_UNUSED 4160 && !reg_set_p (XEXP (note, 0), 4161 PATTERN (undobuf.other_insn))) 4162 /* Simply drop equal note since it may be no longer valid 4163 for other_insn. It may be possible to record that CC 4164 register is changed and only discard those notes, but 4165 in practice it's unnecessary complication and doesn't 4166 give any meaningful improvement. 4167 4168 See PR78559. */ 4169 || REG_NOTE_KIND (note) == REG_EQUAL 4170 || REG_NOTE_KIND (note) == REG_EQUIV) 4171 remove_note (undobuf.other_insn, note); 4172 } 4173 4174 distribute_notes (new_other_notes, undobuf.other_insn, 4175 undobuf.other_insn, NULL, NULL_RTX, NULL_RTX, 4176 NULL_RTX); 4177 } 4178 4179 if (swap_i2i3) 4180 { 4181 rtx_insn *insn; 4182 struct insn_link *link; 4183 rtx ni2dest; 4184 4185 /* I3 now uses what used to be its destination and which is now 4186 I2's destination. This requires us to do a few adjustments. */ 4187 PATTERN (i3) = newpat; 4188 adjust_for_new_dest (i3); 4189 4190 /* We need a LOG_LINK from I3 to I2. But we used to have one, 4191 so we still will. 4192 4193 However, some later insn might be using I2's dest and have 4194 a LOG_LINK pointing at I3. We must remove this link. 4195 The simplest way to remove the link is to point it at I1, 4196 which we know will be a NOTE. */ 4197 4198 /* newi2pat is usually a SET here; however, recog_for_combine might 4199 have added some clobbers. */ 4200 if (GET_CODE (newi2pat) == PARALLEL) 4201 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0)); 4202 else 4203 ni2dest = SET_DEST (newi2pat); 4204 4205 for (insn = NEXT_INSN (i3); 4206 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 4207 || insn != BB_HEAD (this_basic_block->next_bb)); 4208 insn = NEXT_INSN (insn)) 4209 { 4210 if (NONDEBUG_INSN_P (insn) 4211 && reg_referenced_p (ni2dest, PATTERN (insn))) 4212 { 4213 FOR_EACH_LOG_LINK (link, insn) 4214 if (link->insn == i3) 4215 link->insn = i1; 4216 4217 break; 4218 } 4219 } 4220 } 4221 4222 { 4223 rtx i3notes, i2notes, i1notes = 0, i0notes = 0; 4224 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0; 4225 rtx midnotes = 0; 4226 int from_luid; 4227 /* Compute which registers we expect to eliminate. newi2pat may be setting 4228 either i3dest or i2dest, so we must check it. */ 4229 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) 4230 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src 4231 || !i2dest_killed 4232 ? 0 : i2dest); 4233 /* For i1, we need to compute both local elimination and global 4234 elimination information with respect to newi2pat because i1dest 4235 may be the same as i3dest, in which case newi2pat may be setting 4236 i1dest. Global information is used when distributing REG_DEAD 4237 note for i2 and i3, in which case it does matter if newi2pat sets 4238 i1dest or not. 4239 4240 Local information is used when distributing REG_DEAD note for i1, 4241 in which case it doesn't matter if newi2pat sets i1dest or not. 4242 See PR62151, if we have four insns combination: 4243 i0: r0 <- i0src 4244 i1: r1 <- i1src (using r0) 4245 REG_DEAD (r0) 4246 i2: r0 <- i2src (using r1) 4247 i3: r3 <- i3src (using r0) 4248 ix: using r0 4249 From i1's point of view, r0 is eliminated, no matter if it is set 4250 by newi2pat or not. In other words, REG_DEAD info for r0 in i1 4251 should be discarded. 4252 4253 Note local information only affects cases in forms like "I1->I2->I3", 4254 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like 4255 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or 4256 i0dest anyway. */ 4257 rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src 4258 || !i1dest_killed 4259 ? 0 : i1dest); 4260 rtx elim_i1 = (local_elim_i1 == 0 4261 || (newi2pat && reg_set_p (i1dest, newi2pat)) 4262 ? 0 : i1dest); 4263 /* Same case as i1. */ 4264 rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed 4265 ? 0 : i0dest); 4266 rtx elim_i0 = (local_elim_i0 == 0 4267 || (newi2pat && reg_set_p (i0dest, newi2pat)) 4268 ? 0 : i0dest); 4269 4270 /* Get the old REG_NOTES and LOG_LINKS from all our insns and 4271 clear them. */ 4272 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); 4273 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); 4274 if (i1) 4275 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); 4276 if (i0) 4277 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0); 4278 4279 /* Ensure that we do not have something that should not be shared but 4280 occurs multiple times in the new insns. Check this by first 4281 resetting all the `used' flags and then copying anything is shared. */ 4282 4283 reset_used_flags (i3notes); 4284 reset_used_flags (i2notes); 4285 reset_used_flags (i1notes); 4286 reset_used_flags (i0notes); 4287 reset_used_flags (newpat); 4288 reset_used_flags (newi2pat); 4289 if (undobuf.other_insn) 4290 reset_used_flags (PATTERN (undobuf.other_insn)); 4291 4292 i3notes = copy_rtx_if_shared (i3notes); 4293 i2notes = copy_rtx_if_shared (i2notes); 4294 i1notes = copy_rtx_if_shared (i1notes); 4295 i0notes = copy_rtx_if_shared (i0notes); 4296 newpat = copy_rtx_if_shared (newpat); 4297 newi2pat = copy_rtx_if_shared (newi2pat); 4298 if (undobuf.other_insn) 4299 reset_used_flags (PATTERN (undobuf.other_insn)); 4300 4301 INSN_CODE (i3) = insn_code_number; 4302 PATTERN (i3) = newpat; 4303 4304 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3)) 4305 { 4306 for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link; 4307 link = XEXP (link, 1)) 4308 { 4309 if (substed_i2) 4310 { 4311 /* I2SRC must still be meaningful at this point. Some 4312 splitting operations can invalidate I2SRC, but those 4313 operations do not apply to calls. */ 4314 gcc_assert (i2src); 4315 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0), 4316 i2dest, i2src); 4317 } 4318 if (substed_i1) 4319 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0), 4320 i1dest, i1src); 4321 if (substed_i0) 4322 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0), 4323 i0dest, i0src); 4324 } 4325 } 4326 4327 if (undobuf.other_insn) 4328 INSN_CODE (undobuf.other_insn) = other_code_number; 4329 4330 /* We had one special case above where I2 had more than one set and 4331 we replaced a destination of one of those sets with the destination 4332 of I3. In that case, we have to update LOG_LINKS of insns later 4333 in this basic block. Note that this (expensive) case is rare. 4334 4335 Also, in this case, we must pretend that all REG_NOTEs for I2 4336 actually came from I3, so that REG_UNUSED notes from I2 will be 4337 properly handled. */ 4338 4339 if (i3_subst_into_i2) 4340 { 4341 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) 4342 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET 4343 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER) 4344 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) 4345 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest 4346 && ! find_reg_note (i2, REG_UNUSED, 4347 SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) 4348 for (temp_insn = NEXT_INSN (i2); 4349 temp_insn 4350 && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 4351 || BB_HEAD (this_basic_block) != temp_insn); 4352 temp_insn = NEXT_INSN (temp_insn)) 4353 if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn)) 4354 FOR_EACH_LOG_LINK (link, temp_insn) 4355 if (link->insn == i2) 4356 link->insn = i3; 4357 4358 if (i3notes) 4359 { 4360 rtx link = i3notes; 4361 while (XEXP (link, 1)) 4362 link = XEXP (link, 1); 4363 XEXP (link, 1) = i2notes; 4364 } 4365 else 4366 i3notes = i2notes; 4367 i2notes = 0; 4368 } 4369 4370 LOG_LINKS (i3) = NULL; 4371 REG_NOTES (i3) = 0; 4372 LOG_LINKS (i2) = NULL; 4373 REG_NOTES (i2) = 0; 4374 4375 if (newi2pat) 4376 { 4377 if (MAY_HAVE_DEBUG_INSNS && i2scratch) 4378 propagate_for_debug (i2, last_combined_insn, i2dest, i2src, 4379 this_basic_block); 4380 INSN_CODE (i2) = i2_code_number; 4381 PATTERN (i2) = newi2pat; 4382 } 4383 else 4384 { 4385 if (MAY_HAVE_DEBUG_INSNS && i2src) 4386 propagate_for_debug (i2, last_combined_insn, i2dest, i2src, 4387 this_basic_block); 4388 SET_INSN_DELETED (i2); 4389 } 4390 4391 if (i1) 4392 { 4393 LOG_LINKS (i1) = NULL; 4394 REG_NOTES (i1) = 0; 4395 if (MAY_HAVE_DEBUG_INSNS) 4396 propagate_for_debug (i1, last_combined_insn, i1dest, i1src, 4397 this_basic_block); 4398 SET_INSN_DELETED (i1); 4399 } 4400 4401 if (i0) 4402 { 4403 LOG_LINKS (i0) = NULL; 4404 REG_NOTES (i0) = 0; 4405 if (MAY_HAVE_DEBUG_INSNS) 4406 propagate_for_debug (i0, last_combined_insn, i0dest, i0src, 4407 this_basic_block); 4408 SET_INSN_DELETED (i0); 4409 } 4410 4411 /* Get death notes for everything that is now used in either I3 or 4412 I2 and used to die in a previous insn. If we built two new 4413 patterns, move from I1 to I2 then I2 to I3 so that we get the 4414 proper movement on registers that I2 modifies. */ 4415 4416 if (i0) 4417 from_luid = DF_INSN_LUID (i0); 4418 else if (i1) 4419 from_luid = DF_INSN_LUID (i1); 4420 else 4421 from_luid = DF_INSN_LUID (i2); 4422 if (newi2pat) 4423 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes); 4424 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes); 4425 4426 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 4427 if (i3notes) 4428 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL, 4429 elim_i2, elim_i1, elim_i0); 4430 if (i2notes) 4431 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL, 4432 elim_i2, elim_i1, elim_i0); 4433 if (i1notes) 4434 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL, 4435 elim_i2, local_elim_i1, local_elim_i0); 4436 if (i0notes) 4437 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL, 4438 elim_i2, elim_i1, local_elim_i0); 4439 if (midnotes) 4440 distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL, 4441 elim_i2, elim_i1, elim_i0); 4442 4443 /* Distribute any notes added to I2 or I3 by recog_for_combine. We 4444 know these are REG_UNUSED and want them to go to the desired insn, 4445 so we always pass it as i3. */ 4446 4447 if (newi2pat && new_i2_notes) 4448 distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX, 4449 NULL_RTX); 4450 4451 if (new_i3_notes) 4452 distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX, 4453 NULL_RTX); 4454 4455 /* If I3DEST was used in I3SRC, it really died in I3. We may need to 4456 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets 4457 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 4458 in that case, it might delete I2. Similarly for I2 and I1. 4459 Show an additional death due to the REG_DEAD note we make here. If 4460 we discard it in distribute_notes, we will decrement it again. */ 4461 4462 if (i3dest_killed) 4463 { 4464 rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX); 4465 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) 4466 distribute_notes (new_note, NULL, i2, NULL, elim_i2, 4467 elim_i1, elim_i0); 4468 else 4469 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4470 elim_i2, elim_i1, elim_i0); 4471 } 4472 4473 if (i2dest_in_i2src) 4474 { 4475 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX); 4476 if (newi2pat && reg_set_p (i2dest, newi2pat)) 4477 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, 4478 NULL_RTX, NULL_RTX); 4479 else 4480 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4481 NULL_RTX, NULL_RTX, NULL_RTX); 4482 } 4483 4484 if (i1dest_in_i1src) 4485 { 4486 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX); 4487 if (newi2pat && reg_set_p (i1dest, newi2pat)) 4488 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, 4489 NULL_RTX, NULL_RTX); 4490 else 4491 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4492 NULL_RTX, NULL_RTX, NULL_RTX); 4493 } 4494 4495 if (i0dest_in_i0src) 4496 { 4497 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX); 4498 if (newi2pat && reg_set_p (i0dest, newi2pat)) 4499 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, 4500 NULL_RTX, NULL_RTX); 4501 else 4502 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4503 NULL_RTX, NULL_RTX, NULL_RTX); 4504 } 4505 4506 distribute_links (i3links); 4507 distribute_links (i2links); 4508 distribute_links (i1links); 4509 distribute_links (i0links); 4510 4511 if (REG_P (i2dest)) 4512 { 4513 struct insn_link *link; 4514 rtx_insn *i2_insn = 0; 4515 rtx i2_val = 0, set; 4516 4517 /* The insn that used to set this register doesn't exist, and 4518 this life of the register may not exist either. See if one of 4519 I3's links points to an insn that sets I2DEST. If it does, 4520 that is now the last known value for I2DEST. If we don't update 4521 this and I2 set the register to a value that depended on its old 4522 contents, we will get confused. If this insn is used, thing 4523 will be set correctly in combine_instructions. */ 4524 FOR_EACH_LOG_LINK (link, i3) 4525 if ((set = single_set (link->insn)) != 0 4526 && rtx_equal_p (i2dest, SET_DEST (set))) 4527 i2_insn = link->insn, i2_val = SET_SRC (set); 4528 4529 record_value_for_reg (i2dest, i2_insn, i2_val); 4530 4531 /* If the reg formerly set in I2 died only once and that was in I3, 4532 zero its use count so it won't make `reload' do any work. */ 4533 if (! added_sets_2 4534 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) 4535 && ! i2dest_in_i2src 4536 && REGNO (i2dest) < reg_n_sets_max) 4537 INC_REG_N_SETS (REGNO (i2dest), -1); 4538 } 4539 4540 if (i1 && REG_P (i1dest)) 4541 { 4542 struct insn_link *link; 4543 rtx_insn *i1_insn = 0; 4544 rtx i1_val = 0, set; 4545 4546 FOR_EACH_LOG_LINK (link, i3) 4547 if ((set = single_set (link->insn)) != 0 4548 && rtx_equal_p (i1dest, SET_DEST (set))) 4549 i1_insn = link->insn, i1_val = SET_SRC (set); 4550 4551 record_value_for_reg (i1dest, i1_insn, i1_val); 4552 4553 if (! added_sets_1 4554 && ! i1dest_in_i1src 4555 && REGNO (i1dest) < reg_n_sets_max) 4556 INC_REG_N_SETS (REGNO (i1dest), -1); 4557 } 4558 4559 if (i0 && REG_P (i0dest)) 4560 { 4561 struct insn_link *link; 4562 rtx_insn *i0_insn = 0; 4563 rtx i0_val = 0, set; 4564 4565 FOR_EACH_LOG_LINK (link, i3) 4566 if ((set = single_set (link->insn)) != 0 4567 && rtx_equal_p (i0dest, SET_DEST (set))) 4568 i0_insn = link->insn, i0_val = SET_SRC (set); 4569 4570 record_value_for_reg (i0dest, i0_insn, i0_val); 4571 4572 if (! added_sets_0 4573 && ! i0dest_in_i0src 4574 && REGNO (i0dest) < reg_n_sets_max) 4575 INC_REG_N_SETS (REGNO (i0dest), -1); 4576 } 4577 4578 /* Update reg_stat[].nonzero_bits et al for any changes that may have 4579 been made to this insn. The order is important, because newi2pat 4580 can affect nonzero_bits of newpat. */ 4581 if (newi2pat) 4582 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); 4583 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); 4584 } 4585 4586 if (undobuf.other_insn != NULL_RTX) 4587 { 4588 if (dump_file) 4589 { 4590 fprintf (dump_file, "modifying other_insn "); 4591 dump_insn_slim (dump_file, undobuf.other_insn); 4592 } 4593 df_insn_rescan (undobuf.other_insn); 4594 } 4595 4596 if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED))) 4597 { 4598 if (dump_file) 4599 { 4600 fprintf (dump_file, "modifying insn i0 "); 4601 dump_insn_slim (dump_file, i0); 4602 } 4603 df_insn_rescan (i0); 4604 } 4605 4606 if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED))) 4607 { 4608 if (dump_file) 4609 { 4610 fprintf (dump_file, "modifying insn i1 "); 4611 dump_insn_slim (dump_file, i1); 4612 } 4613 df_insn_rescan (i1); 4614 } 4615 4616 if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED))) 4617 { 4618 if (dump_file) 4619 { 4620 fprintf (dump_file, "modifying insn i2 "); 4621 dump_insn_slim (dump_file, i2); 4622 } 4623 df_insn_rescan (i2); 4624 } 4625 4626 if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED))) 4627 { 4628 if (dump_file) 4629 { 4630 fprintf (dump_file, "modifying insn i3 "); 4631 dump_insn_slim (dump_file, i3); 4632 } 4633 df_insn_rescan (i3); 4634 } 4635 4636 /* Set new_direct_jump_p if a new return or simple jump instruction 4637 has been created. Adjust the CFG accordingly. */ 4638 if (returnjump_p (i3) || any_uncondjump_p (i3)) 4639 { 4640 *new_direct_jump_p = 1; 4641 mark_jump_label (PATTERN (i3), i3, 0); 4642 update_cfg_for_uncondjump (i3); 4643 } 4644 4645 if (undobuf.other_insn != NULL_RTX 4646 && (returnjump_p (undobuf.other_insn) 4647 || any_uncondjump_p (undobuf.other_insn))) 4648 { 4649 *new_direct_jump_p = 1; 4650 update_cfg_for_uncondjump (undobuf.other_insn); 4651 } 4652 4653 if (GET_CODE (PATTERN (i3)) == TRAP_IF 4654 && XEXP (PATTERN (i3), 0) == const1_rtx) 4655 { 4656 basic_block bb = BLOCK_FOR_INSN (i3); 4657 gcc_assert (bb); 4658 remove_edge (split_block (bb, i3)); 4659 emit_barrier_after_bb (bb); 4660 *new_direct_jump_p = 1; 4661 } 4662 4663 if (undobuf.other_insn 4664 && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF 4665 && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx) 4666 { 4667 basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn); 4668 gcc_assert (bb); 4669 remove_edge (split_block (bb, undobuf.other_insn)); 4670 emit_barrier_after_bb (bb); 4671 *new_direct_jump_p = 1; 4672 } 4673 4674 /* A noop might also need cleaning up of CFG, if it comes from the 4675 simplification of a jump. */ 4676 if (JUMP_P (i3) 4677 && GET_CODE (newpat) == SET 4678 && SET_SRC (newpat) == pc_rtx 4679 && SET_DEST (newpat) == pc_rtx) 4680 { 4681 *new_direct_jump_p = 1; 4682 update_cfg_for_uncondjump (i3); 4683 } 4684 4685 if (undobuf.other_insn != NULL_RTX 4686 && JUMP_P (undobuf.other_insn) 4687 && GET_CODE (PATTERN (undobuf.other_insn)) == SET 4688 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx 4689 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx) 4690 { 4691 *new_direct_jump_p = 1; 4692 update_cfg_for_uncondjump (undobuf.other_insn); 4693 } 4694 4695 combine_successes++; 4696 undo_commit (); 4697 4698 if (added_links_insn 4699 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2)) 4700 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3)) 4701 return added_links_insn; 4702 else 4703 return newi2pat ? i2 : i3; 4704 } 4705 4706 /* Get a marker for undoing to the current state. */ 4707 4708 static void * 4709 get_undo_marker (void) 4710 { 4711 return undobuf.undos; 4712 } 4713 4714 /* Undo the modifications up to the marker. */ 4715 4716 static void 4717 undo_to_marker (void *marker) 4718 { 4719 struct undo *undo, *next; 4720 4721 for (undo = undobuf.undos; undo != marker; undo = next) 4722 { 4723 gcc_assert (undo); 4724 4725 next = undo->next; 4726 switch (undo->kind) 4727 { 4728 case UNDO_RTX: 4729 *undo->where.r = undo->old_contents.r; 4730 break; 4731 case UNDO_INT: 4732 *undo->where.i = undo->old_contents.i; 4733 break; 4734 case UNDO_MODE: 4735 adjust_reg_mode (*undo->where.r, undo->old_contents.m); 4736 break; 4737 case UNDO_LINKS: 4738 *undo->where.l = undo->old_contents.l; 4739 break; 4740 default: 4741 gcc_unreachable (); 4742 } 4743 4744 undo->next = undobuf.frees; 4745 undobuf.frees = undo; 4746 } 4747 4748 undobuf.undos = (struct undo *) marker; 4749 } 4750 4751 /* Undo all the modifications recorded in undobuf. */ 4752 4753 static void 4754 undo_all (void) 4755 { 4756 undo_to_marker (0); 4757 } 4758 4759 /* We've committed to accepting the changes we made. Move all 4760 of the undos to the free list. */ 4761 4762 static void 4763 undo_commit (void) 4764 { 4765 struct undo *undo, *next; 4766 4767 for (undo = undobuf.undos; undo; undo = next) 4768 { 4769 next = undo->next; 4770 undo->next = undobuf.frees; 4771 undobuf.frees = undo; 4772 } 4773 undobuf.undos = 0; 4774 } 4775 4776 /* Find the innermost point within the rtx at LOC, possibly LOC itself, 4777 where we have an arithmetic expression and return that point. LOC will 4778 be inside INSN. 4779 4780 try_combine will call this function to see if an insn can be split into 4781 two insns. */ 4782 4783 static rtx * 4784 find_split_point (rtx *loc, rtx_insn *insn, bool set_src) 4785 { 4786 rtx x = *loc; 4787 enum rtx_code code = GET_CODE (x); 4788 rtx *split; 4789 unsigned HOST_WIDE_INT len = 0; 4790 HOST_WIDE_INT pos = 0; 4791 int unsignedp = 0; 4792 rtx inner = NULL_RTX; 4793 4794 /* First special-case some codes. */ 4795 switch (code) 4796 { 4797 case SUBREG: 4798 #ifdef INSN_SCHEDULING 4799 /* If we are making a paradoxical SUBREG invalid, it becomes a split 4800 point. */ 4801 if (MEM_P (SUBREG_REG (x))) 4802 return loc; 4803 #endif 4804 return find_split_point (&SUBREG_REG (x), insn, false); 4805 4806 case MEM: 4807 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 4808 using LO_SUM and HIGH. */ 4809 if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST 4810 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)) 4811 { 4812 machine_mode address_mode = get_address_mode (x); 4813 4814 SUBST (XEXP (x, 0), 4815 gen_rtx_LO_SUM (address_mode, 4816 gen_rtx_HIGH (address_mode, XEXP (x, 0)), 4817 XEXP (x, 0))); 4818 return &XEXP (XEXP (x, 0), 0); 4819 } 4820 4821 /* If we have a PLUS whose second operand is a constant and the 4822 address is not valid, perhaps will can split it up using 4823 the machine-specific way to split large constants. We use 4824 the first pseudo-reg (one of the virtual regs) as a placeholder; 4825 it will not remain in the result. */ 4826 if (GET_CODE (XEXP (x, 0)) == PLUS 4827 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 4828 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), 4829 MEM_ADDR_SPACE (x))) 4830 { 4831 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; 4832 rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)), 4833 subst_insn); 4834 4835 /* This should have produced two insns, each of which sets our 4836 placeholder. If the source of the second is a valid address, 4837 we can make put both sources together and make a split point 4838 in the middle. */ 4839 4840 if (seq 4841 && NEXT_INSN (seq) != NULL_RTX 4842 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX 4843 && NONJUMP_INSN_P (seq) 4844 && GET_CODE (PATTERN (seq)) == SET 4845 && SET_DEST (PATTERN (seq)) == reg 4846 && ! reg_mentioned_p (reg, 4847 SET_SRC (PATTERN (seq))) 4848 && NONJUMP_INSN_P (NEXT_INSN (seq)) 4849 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET 4850 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg 4851 && memory_address_addr_space_p 4852 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))), 4853 MEM_ADDR_SPACE (x))) 4854 { 4855 rtx src1 = SET_SRC (PATTERN (seq)); 4856 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq))); 4857 4858 /* Replace the placeholder in SRC2 with SRC1. If we can 4859 find where in SRC2 it was placed, that can become our 4860 split point and we can replace this address with SRC2. 4861 Just try two obvious places. */ 4862 4863 src2 = replace_rtx (src2, reg, src1); 4864 split = 0; 4865 if (XEXP (src2, 0) == src1) 4866 split = &XEXP (src2, 0); 4867 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' 4868 && XEXP (XEXP (src2, 0), 0) == src1) 4869 split = &XEXP (XEXP (src2, 0), 0); 4870 4871 if (split) 4872 { 4873 SUBST (XEXP (x, 0), src2); 4874 return split; 4875 } 4876 } 4877 4878 /* If that didn't work, perhaps the first operand is complex and 4879 needs to be computed separately, so make a split point there. 4880 This will occur on machines that just support REG + CONST 4881 and have a constant moved through some previous computation. */ 4882 4883 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0)) 4884 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 4885 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) 4886 return &XEXP (XEXP (x, 0), 0); 4887 } 4888 4889 /* If we have a PLUS whose first operand is complex, try computing it 4890 separately by making a split there. */ 4891 if (GET_CODE (XEXP (x, 0)) == PLUS 4892 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), 4893 MEM_ADDR_SPACE (x)) 4894 && ! OBJECT_P (XEXP (XEXP (x, 0), 0)) 4895 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 4896 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) 4897 return &XEXP (XEXP (x, 0), 0); 4898 break; 4899 4900 case SET: 4901 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a 4902 ZERO_EXTRACT, the most likely reason why this doesn't match is that 4903 we need to put the operand into a register. So split at that 4904 point. */ 4905 4906 if (SET_DEST (x) == cc0_rtx 4907 && GET_CODE (SET_SRC (x)) != COMPARE 4908 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT 4909 && !OBJECT_P (SET_SRC (x)) 4910 && ! (GET_CODE (SET_SRC (x)) == SUBREG 4911 && OBJECT_P (SUBREG_REG (SET_SRC (x))))) 4912 return &SET_SRC (x); 4913 4914 /* See if we can split SET_SRC as it stands. */ 4915 split = find_split_point (&SET_SRC (x), insn, true); 4916 if (split && split != &SET_SRC (x)) 4917 return split; 4918 4919 /* See if we can split SET_DEST as it stands. */ 4920 split = find_split_point (&SET_DEST (x), insn, false); 4921 if (split && split != &SET_DEST (x)) 4922 return split; 4923 4924 /* See if this is a bitfield assignment with everything constant. If 4925 so, this is an IOR of an AND, so split it into that. */ 4926 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 4927 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0))) 4928 && CONST_INT_P (XEXP (SET_DEST (x), 1)) 4929 && CONST_INT_P (XEXP (SET_DEST (x), 2)) 4930 && CONST_INT_P (SET_SRC (x)) 4931 && ((INTVAL (XEXP (SET_DEST (x), 1)) 4932 + INTVAL (XEXP (SET_DEST (x), 2))) 4933 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)))) 4934 && ! side_effects_p (XEXP (SET_DEST (x), 0))) 4935 { 4936 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); 4937 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); 4938 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); 4939 rtx dest = XEXP (SET_DEST (x), 0); 4940 machine_mode mode = GET_MODE (dest); 4941 unsigned HOST_WIDE_INT mask 4942 = (HOST_WIDE_INT_1U << len) - 1; 4943 rtx or_mask; 4944 4945 if (BITS_BIG_ENDIAN) 4946 pos = GET_MODE_PRECISION (mode) - len - pos; 4947 4948 or_mask = gen_int_mode (src << pos, mode); 4949 if (src == mask) 4950 SUBST (SET_SRC (x), 4951 simplify_gen_binary (IOR, mode, dest, or_mask)); 4952 else 4953 { 4954 rtx negmask = gen_int_mode (~(mask << pos), mode); 4955 SUBST (SET_SRC (x), 4956 simplify_gen_binary (IOR, mode, 4957 simplify_gen_binary (AND, mode, 4958 dest, negmask), 4959 or_mask)); 4960 } 4961 4962 SUBST (SET_DEST (x), dest); 4963 4964 split = find_split_point (&SET_SRC (x), insn, true); 4965 if (split && split != &SET_SRC (x)) 4966 return split; 4967 } 4968 4969 /* Otherwise, see if this is an operation that we can split into two. 4970 If so, try to split that. */ 4971 code = GET_CODE (SET_SRC (x)); 4972 4973 switch (code) 4974 { 4975 case AND: 4976 /* If we are AND'ing with a large constant that is only a single 4977 bit and the result is only being used in a context where we 4978 need to know if it is zero or nonzero, replace it with a bit 4979 extraction. This will avoid the large constant, which might 4980 have taken more than one insn to make. If the constant were 4981 not a valid argument to the AND but took only one insn to make, 4982 this is no worse, but if it took more than one insn, it will 4983 be better. */ 4984 4985 if (CONST_INT_P (XEXP (SET_SRC (x), 1)) 4986 && REG_P (XEXP (SET_SRC (x), 0)) 4987 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7 4988 && REG_P (SET_DEST (x)) 4989 && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0 4990 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) 4991 && XEXP (*split, 0) == SET_DEST (x) 4992 && XEXP (*split, 1) == const0_rtx) 4993 { 4994 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), 4995 XEXP (SET_SRC (x), 0), 4996 pos, NULL_RTX, 1, 1, 0, 0); 4997 if (extraction != 0) 4998 { 4999 SUBST (SET_SRC (x), extraction); 5000 return find_split_point (loc, insn, false); 5001 } 5002 } 5003 break; 5004 5005 case NE: 5006 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X 5007 is known to be on, this can be converted into a NEG of a shift. */ 5008 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx 5009 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) 5010 && 1 <= (pos = exact_log2 5011 (nonzero_bits (XEXP (SET_SRC (x), 0), 5012 GET_MODE (XEXP (SET_SRC (x), 0)))))) 5013 { 5014 machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); 5015 5016 SUBST (SET_SRC (x), 5017 gen_rtx_NEG (mode, 5018 gen_rtx_LSHIFTRT (mode, 5019 XEXP (SET_SRC (x), 0), 5020 GEN_INT (pos)))); 5021 5022 split = find_split_point (&SET_SRC (x), insn, true); 5023 if (split && split != &SET_SRC (x)) 5024 return split; 5025 } 5026 break; 5027 5028 case SIGN_EXTEND: 5029 inner = XEXP (SET_SRC (x), 0); 5030 5031 /* We can't optimize if either mode is a partial integer 5032 mode as we don't know how many bits are significant 5033 in those modes. */ 5034 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT 5035 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) 5036 break; 5037 5038 pos = 0; 5039 len = GET_MODE_PRECISION (GET_MODE (inner)); 5040 unsignedp = 0; 5041 break; 5042 5043 case SIGN_EXTRACT: 5044 case ZERO_EXTRACT: 5045 if (CONST_INT_P (XEXP (SET_SRC (x), 1)) 5046 && CONST_INT_P (XEXP (SET_SRC (x), 2))) 5047 { 5048 inner = XEXP (SET_SRC (x), 0); 5049 len = INTVAL (XEXP (SET_SRC (x), 1)); 5050 pos = INTVAL (XEXP (SET_SRC (x), 2)); 5051 5052 if (BITS_BIG_ENDIAN) 5053 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos; 5054 unsignedp = (code == ZERO_EXTRACT); 5055 } 5056 break; 5057 5058 default: 5059 break; 5060 } 5061 5062 if (len && pos >= 0 5063 && pos + len <= GET_MODE_PRECISION (GET_MODE (inner))) 5064 { 5065 machine_mode mode = GET_MODE (SET_SRC (x)); 5066 5067 /* For unsigned, we have a choice of a shift followed by an 5068 AND or two shifts. Use two shifts for field sizes where the 5069 constant might be too large. We assume here that we can 5070 always at least get 8-bit constants in an AND insn, which is 5071 true for every current RISC. */ 5072 5073 if (unsignedp && len <= 8) 5074 { 5075 unsigned HOST_WIDE_INT mask 5076 = (HOST_WIDE_INT_1U << len) - 1; 5077 SUBST (SET_SRC (x), 5078 gen_rtx_AND (mode, 5079 gen_rtx_LSHIFTRT 5080 (mode, gen_lowpart (mode, inner), 5081 GEN_INT (pos)), 5082 gen_int_mode (mask, mode))); 5083 5084 split = find_split_point (&SET_SRC (x), insn, true); 5085 if (split && split != &SET_SRC (x)) 5086 return split; 5087 } 5088 else 5089 { 5090 SUBST (SET_SRC (x), 5091 gen_rtx_fmt_ee 5092 (unsignedp ? LSHIFTRT : ASHIFTRT, mode, 5093 gen_rtx_ASHIFT (mode, 5094 gen_lowpart (mode, inner), 5095 GEN_INT (GET_MODE_PRECISION (mode) 5096 - len - pos)), 5097 GEN_INT (GET_MODE_PRECISION (mode) - len))); 5098 5099 split = find_split_point (&SET_SRC (x), insn, true); 5100 if (split && split != &SET_SRC (x)) 5101 return split; 5102 } 5103 } 5104 5105 /* See if this is a simple operation with a constant as the second 5106 operand. It might be that this constant is out of range and hence 5107 could be used as a split point. */ 5108 if (BINARY_P (SET_SRC (x)) 5109 && CONSTANT_P (XEXP (SET_SRC (x), 1)) 5110 && (OBJECT_P (XEXP (SET_SRC (x), 0)) 5111 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG 5112 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0)))))) 5113 return &XEXP (SET_SRC (x), 1); 5114 5115 /* Finally, see if this is a simple operation with its first operand 5116 not in a register. The operation might require this operand in a 5117 register, so return it as a split point. We can always do this 5118 because if the first operand were another operation, we would have 5119 already found it as a split point. */ 5120 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x))) 5121 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) 5122 return &XEXP (SET_SRC (x), 0); 5123 5124 return 0; 5125 5126 case AND: 5127 case IOR: 5128 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, 5129 it is better to write this as (not (ior A B)) so we can split it. 5130 Similarly for IOR. */ 5131 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) 5132 { 5133 SUBST (*loc, 5134 gen_rtx_NOT (GET_MODE (x), 5135 gen_rtx_fmt_ee (code == IOR ? AND : IOR, 5136 GET_MODE (x), 5137 XEXP (XEXP (x, 0), 0), 5138 XEXP (XEXP (x, 1), 0)))); 5139 return find_split_point (loc, insn, set_src); 5140 } 5141 5142 /* Many RISC machines have a large set of logical insns. If the 5143 second operand is a NOT, put it first so we will try to split the 5144 other operand first. */ 5145 if (GET_CODE (XEXP (x, 1)) == NOT) 5146 { 5147 rtx tem = XEXP (x, 0); 5148 SUBST (XEXP (x, 0), XEXP (x, 1)); 5149 SUBST (XEXP (x, 1), tem); 5150 } 5151 break; 5152 5153 case PLUS: 5154 case MINUS: 5155 /* Canonicalization can produce (minus A (mult B C)), where C is a 5156 constant. It may be better to try splitting (plus (mult B -C) A) 5157 instead if this isn't a multiply by a power of two. */ 5158 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT 5159 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 5160 && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1)))) 5161 { 5162 machine_mode mode = GET_MODE (x); 5163 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1)); 5164 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode); 5165 SUBST (*loc, gen_rtx_PLUS (mode, 5166 gen_rtx_MULT (mode, 5167 XEXP (XEXP (x, 1), 0), 5168 gen_int_mode (other_int, 5169 mode)), 5170 XEXP (x, 0))); 5171 return find_split_point (loc, insn, set_src); 5172 } 5173 5174 /* Split at a multiply-accumulate instruction. However if this is 5175 the SET_SRC, we likely do not have such an instruction and it's 5176 worthless to try this split. */ 5177 if (!set_src 5178 && (GET_CODE (XEXP (x, 0)) == MULT 5179 || (GET_CODE (XEXP (x, 0)) == ASHIFT 5180 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) 5181 return loc; 5182 5183 default: 5184 break; 5185 } 5186 5187 /* Otherwise, select our actions depending on our rtx class. */ 5188 switch (GET_RTX_CLASS (code)) 5189 { 5190 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ 5191 case RTX_TERNARY: 5192 split = find_split_point (&XEXP (x, 2), insn, false); 5193 if (split) 5194 return split; 5195 /* fall through */ 5196 case RTX_BIN_ARITH: 5197 case RTX_COMM_ARITH: 5198 case RTX_COMPARE: 5199 case RTX_COMM_COMPARE: 5200 split = find_split_point (&XEXP (x, 1), insn, false); 5201 if (split) 5202 return split; 5203 /* fall through */ 5204 case RTX_UNARY: 5205 /* Some machines have (and (shift ...) ...) insns. If X is not 5206 an AND, but XEXP (X, 0) is, use it as our split point. */ 5207 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) 5208 return &XEXP (x, 0); 5209 5210 split = find_split_point (&XEXP (x, 0), insn, false); 5211 if (split) 5212 return split; 5213 return loc; 5214 5215 default: 5216 /* Otherwise, we don't have a split point. */ 5217 return 0; 5218 } 5219 } 5220 5221 /* Throughout X, replace FROM with TO, and return the result. 5222 The result is TO if X is FROM; 5223 otherwise the result is X, but its contents may have been modified. 5224 If they were modified, a record was made in undobuf so that 5225 undo_all will (among other things) return X to its original state. 5226 5227 If the number of changes necessary is too much to record to undo, 5228 the excess changes are not made, so the result is invalid. 5229 The changes already made can still be undone. 5230 undobuf.num_undo is incremented for such changes, so by testing that 5231 the caller can tell whether the result is valid. 5232 5233 `n_occurrences' is incremented each time FROM is replaced. 5234 5235 IN_DEST is nonzero if we are processing the SET_DEST of a SET. 5236 5237 IN_COND is nonzero if we are at the top level of a condition. 5238 5239 UNIQUE_COPY is nonzero if each substitution must be unique. We do this 5240 by copying if `n_occurrences' is nonzero. */ 5241 5242 static rtx 5243 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy) 5244 { 5245 enum rtx_code code = GET_CODE (x); 5246 machine_mode op0_mode = VOIDmode; 5247 const char *fmt; 5248 int len, i; 5249 rtx new_rtx; 5250 5251 /* Two expressions are equal if they are identical copies of a shared 5252 RTX or if they are both registers with the same register number 5253 and mode. */ 5254 5255 #define COMBINE_RTX_EQUAL_P(X,Y) \ 5256 ((X) == (Y) \ 5257 || (REG_P (X) && REG_P (Y) \ 5258 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) 5259 5260 /* Do not substitute into clobbers of regs -- this will never result in 5261 valid RTL. */ 5262 if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0))) 5263 return x; 5264 5265 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) 5266 { 5267 n_occurrences++; 5268 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); 5269 } 5270 5271 /* If X and FROM are the same register but different modes, they 5272 will not have been seen as equal above. However, the log links code 5273 will make a LOG_LINKS entry for that case. If we do nothing, we 5274 will try to rerecognize our original insn and, when it succeeds, 5275 we will delete the feeding insn, which is incorrect. 5276 5277 So force this insn not to match in this (rare) case. */ 5278 if (! in_dest && code == REG && REG_P (from) 5279 && reg_overlap_mentioned_p (x, from)) 5280 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 5281 5282 /* If this is an object, we are done unless it is a MEM or LO_SUM, both 5283 of which may contain things that can be combined. */ 5284 if (code != MEM && code != LO_SUM && OBJECT_P (x)) 5285 return x; 5286 5287 /* It is possible to have a subexpression appear twice in the insn. 5288 Suppose that FROM is a register that appears within TO. 5289 Then, after that subexpression has been scanned once by `subst', 5290 the second time it is scanned, TO may be found. If we were 5291 to scan TO here, we would find FROM within it and create a 5292 self-referent rtl structure which is completely wrong. */ 5293 if (COMBINE_RTX_EQUAL_P (x, to)) 5294 return to; 5295 5296 /* Parallel asm_operands need special attention because all of the 5297 inputs are shared across the arms. Furthermore, unsharing the 5298 rtl results in recognition failures. Failure to handle this case 5299 specially can result in circular rtl. 5300 5301 Solve this by doing a normal pass across the first entry of the 5302 parallel, and only processing the SET_DESTs of the subsequent 5303 entries. Ug. */ 5304 5305 if (code == PARALLEL 5306 && GET_CODE (XVECEXP (x, 0, 0)) == SET 5307 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) 5308 { 5309 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy); 5310 5311 /* If this substitution failed, this whole thing fails. */ 5312 if (GET_CODE (new_rtx) == CLOBBER 5313 && XEXP (new_rtx, 0) == const0_rtx) 5314 return new_rtx; 5315 5316 SUBST (XVECEXP (x, 0, 0), new_rtx); 5317 5318 for (i = XVECLEN (x, 0) - 1; i >= 1; i--) 5319 { 5320 rtx dest = SET_DEST (XVECEXP (x, 0, i)); 5321 5322 if (!REG_P (dest) 5323 && GET_CODE (dest) != CC0 5324 && GET_CODE (dest) != PC) 5325 { 5326 new_rtx = subst (dest, from, to, 0, 0, unique_copy); 5327 5328 /* If this substitution failed, this whole thing fails. */ 5329 if (GET_CODE (new_rtx) == CLOBBER 5330 && XEXP (new_rtx, 0) == const0_rtx) 5331 return new_rtx; 5332 5333 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx); 5334 } 5335 } 5336 } 5337 else 5338 { 5339 len = GET_RTX_LENGTH (code); 5340 fmt = GET_RTX_FORMAT (code); 5341 5342 /* We don't need to process a SET_DEST that is a register, CC0, 5343 or PC, so set up to skip this common case. All other cases 5344 where we want to suppress replacing something inside a 5345 SET_SRC are handled via the IN_DEST operand. */ 5346 if (code == SET 5347 && (REG_P (SET_DEST (x)) 5348 || GET_CODE (SET_DEST (x)) == CC0 5349 || GET_CODE (SET_DEST (x)) == PC)) 5350 fmt = "ie"; 5351 5352 /* Trying to simplify the operands of a widening MULT is not likely 5353 to create RTL matching a machine insn. */ 5354 if (code == MULT 5355 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 5356 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) 5357 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND 5358 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND) 5359 && REG_P (XEXP (XEXP (x, 0), 0)) 5360 && REG_P (XEXP (XEXP (x, 1), 0)) 5361 && from == to) 5362 return x; 5363 5364 5365 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a 5366 constant. */ 5367 if (fmt[0] == 'e') 5368 op0_mode = GET_MODE (XEXP (x, 0)); 5369 5370 for (i = 0; i < len; i++) 5371 { 5372 if (fmt[i] == 'E') 5373 { 5374 int j; 5375 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 5376 { 5377 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) 5378 { 5379 new_rtx = (unique_copy && n_occurrences 5380 ? copy_rtx (to) : to); 5381 n_occurrences++; 5382 } 5383 else 5384 { 5385 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0, 5386 unique_copy); 5387 5388 /* If this substitution failed, this whole thing 5389 fails. */ 5390 if (GET_CODE (new_rtx) == CLOBBER 5391 && XEXP (new_rtx, 0) == const0_rtx) 5392 return new_rtx; 5393 } 5394 5395 SUBST (XVECEXP (x, i, j), new_rtx); 5396 } 5397 } 5398 else if (fmt[i] == 'e') 5399 { 5400 /* If this is a register being set, ignore it. */ 5401 new_rtx = XEXP (x, i); 5402 if (in_dest 5403 && i == 0 5404 && (((code == SUBREG || code == ZERO_EXTRACT) 5405 && REG_P (new_rtx)) 5406 || code == STRICT_LOW_PART)) 5407 ; 5408 5409 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) 5410 { 5411 /* In general, don't install a subreg involving two 5412 modes not tieable. It can worsen register 5413 allocation, and can even make invalid reload 5414 insns, since the reg inside may need to be copied 5415 from in the outside mode, and that may be invalid 5416 if it is an fp reg copied in integer mode. 5417 5418 We allow two exceptions to this: It is valid if 5419 it is inside another SUBREG and the mode of that 5420 SUBREG and the mode of the inside of TO is 5421 tieable and it is valid if X is a SET that copies 5422 FROM to CC0. */ 5423 5424 if (GET_CODE (to) == SUBREG 5425 && ! MODES_TIEABLE_P (GET_MODE (to), 5426 GET_MODE (SUBREG_REG (to))) 5427 && ! (code == SUBREG 5428 && MODES_TIEABLE_P (GET_MODE (x), 5429 GET_MODE (SUBREG_REG (to)))) 5430 && (!HAVE_cc0 5431 || (! (code == SET 5432 && i == 1 5433 && XEXP (x, 0) == cc0_rtx)))) 5434 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 5435 5436 if (code == SUBREG 5437 && REG_P (to) 5438 && REGNO (to) < FIRST_PSEUDO_REGISTER 5439 && simplify_subreg_regno (REGNO (to), GET_MODE (to), 5440 SUBREG_BYTE (x), 5441 GET_MODE (x)) < 0) 5442 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 5443 5444 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to); 5445 n_occurrences++; 5446 } 5447 else 5448 /* If we are in a SET_DEST, suppress most cases unless we 5449 have gone inside a MEM, in which case we want to 5450 simplify the address. We assume here that things that 5451 are actually part of the destination have their inner 5452 parts in the first expression. This is true for SUBREG, 5453 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only 5454 things aside from REG and MEM that should appear in a 5455 SET_DEST. */ 5456 new_rtx = subst (XEXP (x, i), from, to, 5457 (((in_dest 5458 && (code == SUBREG || code == STRICT_LOW_PART 5459 || code == ZERO_EXTRACT)) 5460 || code == SET) 5461 && i == 0), 5462 code == IF_THEN_ELSE && i == 0, 5463 unique_copy); 5464 5465 /* If we found that we will have to reject this combination, 5466 indicate that by returning the CLOBBER ourselves, rather than 5467 an expression containing it. This will speed things up as 5468 well as prevent accidents where two CLOBBERs are considered 5469 to be equal, thus producing an incorrect simplification. */ 5470 5471 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx) 5472 return new_rtx; 5473 5474 if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx)) 5475 { 5476 machine_mode mode = GET_MODE (x); 5477 5478 x = simplify_subreg (GET_MODE (x), new_rtx, 5479 GET_MODE (SUBREG_REG (x)), 5480 SUBREG_BYTE (x)); 5481 if (! x) 5482 x = gen_rtx_CLOBBER (mode, const0_rtx); 5483 } 5484 else if (CONST_SCALAR_INT_P (new_rtx) 5485 && (GET_CODE (x) == ZERO_EXTEND 5486 || GET_CODE (x) == FLOAT 5487 || GET_CODE (x) == UNSIGNED_FLOAT)) 5488 { 5489 x = simplify_unary_operation (GET_CODE (x), GET_MODE (x), 5490 new_rtx, 5491 GET_MODE (XEXP (x, 0))); 5492 if (!x) 5493 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 5494 } 5495 else 5496 SUBST (XEXP (x, i), new_rtx); 5497 } 5498 } 5499 } 5500 5501 /* Check if we are loading something from the constant pool via float 5502 extension; in this case we would undo compress_float_constant 5503 optimization and degenerate constant load to an immediate value. */ 5504 if (GET_CODE (x) == FLOAT_EXTEND 5505 && MEM_P (XEXP (x, 0)) 5506 && MEM_READONLY_P (XEXP (x, 0))) 5507 { 5508 rtx tmp = avoid_constant_pool_reference (x); 5509 if (x != tmp) 5510 return x; 5511 } 5512 5513 /* Try to simplify X. If the simplification changed the code, it is likely 5514 that further simplification will help, so loop, but limit the number 5515 of repetitions that will be performed. */ 5516 5517 for (i = 0; i < 4; i++) 5518 { 5519 /* If X is sufficiently simple, don't bother trying to do anything 5520 with it. */ 5521 if (code != CONST_INT && code != REG && code != CLOBBER) 5522 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond); 5523 5524 if (GET_CODE (x) == code) 5525 break; 5526 5527 code = GET_CODE (x); 5528 5529 /* We no longer know the original mode of operand 0 since we 5530 have changed the form of X) */ 5531 op0_mode = VOIDmode; 5532 } 5533 5534 return x; 5535 } 5536 5537 /* If X is a commutative operation whose operands are not in the canonical 5538 order, use substitutions to swap them. */ 5539 5540 static void 5541 maybe_swap_commutative_operands (rtx x) 5542 { 5543 if (COMMUTATIVE_ARITH_P (x) 5544 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 5545 { 5546 rtx temp = XEXP (x, 0); 5547 SUBST (XEXP (x, 0), XEXP (x, 1)); 5548 SUBST (XEXP (x, 1), temp); 5549 } 5550 } 5551 5552 /* Simplify X, a piece of RTL. We just operate on the expression at the 5553 outer level; call `subst' to simplify recursively. Return the new 5554 expression. 5555 5556 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero 5557 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level 5558 of a condition. */ 5559 5560 static rtx 5561 combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest, 5562 int in_cond) 5563 { 5564 enum rtx_code code = GET_CODE (x); 5565 machine_mode mode = GET_MODE (x); 5566 rtx temp; 5567 int i; 5568 5569 /* If this is a commutative operation, put a constant last and a complex 5570 expression first. We don't need to do this for comparisons here. */ 5571 maybe_swap_commutative_operands (x); 5572 5573 /* Try to fold this expression in case we have constants that weren't 5574 present before. */ 5575 temp = 0; 5576 switch (GET_RTX_CLASS (code)) 5577 { 5578 case RTX_UNARY: 5579 if (op0_mode == VOIDmode) 5580 op0_mode = GET_MODE (XEXP (x, 0)); 5581 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); 5582 break; 5583 case RTX_COMPARE: 5584 case RTX_COMM_COMPARE: 5585 { 5586 machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); 5587 if (cmp_mode == VOIDmode) 5588 { 5589 cmp_mode = GET_MODE (XEXP (x, 1)); 5590 if (cmp_mode == VOIDmode) 5591 cmp_mode = op0_mode; 5592 } 5593 temp = simplify_relational_operation (code, mode, cmp_mode, 5594 XEXP (x, 0), XEXP (x, 1)); 5595 } 5596 break; 5597 case RTX_COMM_ARITH: 5598 case RTX_BIN_ARITH: 5599 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); 5600 break; 5601 case RTX_BITFIELD_OPS: 5602 case RTX_TERNARY: 5603 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), 5604 XEXP (x, 1), XEXP (x, 2)); 5605 break; 5606 default: 5607 break; 5608 } 5609 5610 if (temp) 5611 { 5612 x = temp; 5613 code = GET_CODE (temp); 5614 op0_mode = VOIDmode; 5615 mode = GET_MODE (temp); 5616 } 5617 5618 /* If this is a simple operation applied to an IF_THEN_ELSE, try 5619 applying it to the arms of the IF_THEN_ELSE. This often simplifies 5620 things. Check for cases where both arms are testing the same 5621 condition. 5622 5623 Don't do anything if all operands are very simple. */ 5624 5625 if ((BINARY_P (x) 5626 && ((!OBJECT_P (XEXP (x, 0)) 5627 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 5628 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))) 5629 || (!OBJECT_P (XEXP (x, 1)) 5630 && ! (GET_CODE (XEXP (x, 1)) == SUBREG 5631 && OBJECT_P (SUBREG_REG (XEXP (x, 1))))))) 5632 || (UNARY_P (x) 5633 && (!OBJECT_P (XEXP (x, 0)) 5634 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 5635 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))))) 5636 { 5637 rtx cond, true_rtx, false_rtx; 5638 5639 cond = if_then_else_cond (x, &true_rtx, &false_rtx); 5640 if (cond != 0 5641 /* If everything is a comparison, what we have is highly unlikely 5642 to be simpler, so don't use it. */ 5643 && ! (COMPARISON_P (x) 5644 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))) 5645 /* Similarly, if we end up with one of the expressions the same 5646 as the original, it is certainly not simpler. */ 5647 && ! rtx_equal_p (x, true_rtx) 5648 && ! rtx_equal_p (x, false_rtx)) 5649 { 5650 rtx cop1 = const0_rtx; 5651 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); 5652 5653 if (cond_code == NE && COMPARISON_P (cond)) 5654 return x; 5655 5656 /* Simplify the alternative arms; this may collapse the true and 5657 false arms to store-flag values. Be careful to use copy_rtx 5658 here since true_rtx or false_rtx might share RTL with x as a 5659 result of the if_then_else_cond call above. */ 5660 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0); 5661 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0); 5662 5663 /* If true_rtx and false_rtx are not general_operands, an if_then_else 5664 is unlikely to be simpler. */ 5665 if (general_operand (true_rtx, VOIDmode) 5666 && general_operand (false_rtx, VOIDmode)) 5667 { 5668 enum rtx_code reversed; 5669 5670 /* Restarting if we generate a store-flag expression will cause 5671 us to loop. Just drop through in this case. */ 5672 5673 /* If the result values are STORE_FLAG_VALUE and zero, we can 5674 just make the comparison operation. */ 5675 if (true_rtx == const_true_rtx && false_rtx == const0_rtx) 5676 x = simplify_gen_relational (cond_code, mode, VOIDmode, 5677 cond, cop1); 5678 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx 5679 && ((reversed = reversed_comparison_code_parts 5680 (cond_code, cond, cop1, NULL)) 5681 != UNKNOWN)) 5682 x = simplify_gen_relational (reversed, mode, VOIDmode, 5683 cond, cop1); 5684 5685 /* Likewise, we can make the negate of a comparison operation 5686 if the result values are - STORE_FLAG_VALUE and zero. */ 5687 else if (CONST_INT_P (true_rtx) 5688 && INTVAL (true_rtx) == - STORE_FLAG_VALUE 5689 && false_rtx == const0_rtx) 5690 x = simplify_gen_unary (NEG, mode, 5691 simplify_gen_relational (cond_code, 5692 mode, VOIDmode, 5693 cond, cop1), 5694 mode); 5695 else if (CONST_INT_P (false_rtx) 5696 && INTVAL (false_rtx) == - STORE_FLAG_VALUE 5697 && true_rtx == const0_rtx 5698 && ((reversed = reversed_comparison_code_parts 5699 (cond_code, cond, cop1, NULL)) 5700 != UNKNOWN)) 5701 x = simplify_gen_unary (NEG, mode, 5702 simplify_gen_relational (reversed, 5703 mode, VOIDmode, 5704 cond, cop1), 5705 mode); 5706 else 5707 return gen_rtx_IF_THEN_ELSE (mode, 5708 simplify_gen_relational (cond_code, 5709 mode, 5710 VOIDmode, 5711 cond, 5712 cop1), 5713 true_rtx, false_rtx); 5714 5715 code = GET_CODE (x); 5716 op0_mode = VOIDmode; 5717 } 5718 } 5719 } 5720 5721 /* First see if we can apply the inverse distributive law. */ 5722 if (code == PLUS || code == MINUS 5723 || code == AND || code == IOR || code == XOR) 5724 { 5725 x = apply_distributive_law (x); 5726 code = GET_CODE (x); 5727 op0_mode = VOIDmode; 5728 } 5729 5730 /* If CODE is an associative operation not otherwise handled, see if we 5731 can associate some operands. This can win if they are constants or 5732 if they are logically related (i.e. (a & b) & a). */ 5733 if ((code == PLUS || code == MINUS || code == MULT || code == DIV 5734 || code == AND || code == IOR || code == XOR 5735 || code == SMAX || code == SMIN || code == UMAX || code == UMIN) 5736 && ((INTEGRAL_MODE_P (mode) && code != DIV) 5737 || (flag_associative_math && FLOAT_MODE_P (mode)))) 5738 { 5739 if (GET_CODE (XEXP (x, 0)) == code) 5740 { 5741 rtx other = XEXP (XEXP (x, 0), 0); 5742 rtx inner_op0 = XEXP (XEXP (x, 0), 1); 5743 rtx inner_op1 = XEXP (x, 1); 5744 rtx inner; 5745 5746 /* Make sure we pass the constant operand if any as the second 5747 one if this is a commutative operation. */ 5748 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x)) 5749 std::swap (inner_op0, inner_op1); 5750 inner = simplify_binary_operation (code == MINUS ? PLUS 5751 : code == DIV ? MULT 5752 : code, 5753 mode, inner_op0, inner_op1); 5754 5755 /* For commutative operations, try the other pair if that one 5756 didn't simplify. */ 5757 if (inner == 0 && COMMUTATIVE_ARITH_P (x)) 5758 { 5759 other = XEXP (XEXP (x, 0), 1); 5760 inner = simplify_binary_operation (code, mode, 5761 XEXP (XEXP (x, 0), 0), 5762 XEXP (x, 1)); 5763 } 5764 5765 if (inner) 5766 return simplify_gen_binary (code, mode, other, inner); 5767 } 5768 } 5769 5770 /* A little bit of algebraic simplification here. */ 5771 switch (code) 5772 { 5773 case MEM: 5774 /* Ensure that our address has any ASHIFTs converted to MULT in case 5775 address-recognizing predicates are called later. */ 5776 temp = make_compound_operation (XEXP (x, 0), MEM); 5777 SUBST (XEXP (x, 0), temp); 5778 break; 5779 5780 case SUBREG: 5781 if (op0_mode == VOIDmode) 5782 op0_mode = GET_MODE (SUBREG_REG (x)); 5783 5784 /* See if this can be moved to simplify_subreg. */ 5785 if (CONSTANT_P (SUBREG_REG (x)) 5786 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) 5787 /* Don't call gen_lowpart if the inner mode 5788 is VOIDmode and we cannot simplify it, as SUBREG without 5789 inner mode is invalid. */ 5790 && (GET_MODE (SUBREG_REG (x)) != VOIDmode 5791 || gen_lowpart_common (mode, SUBREG_REG (x)))) 5792 return gen_lowpart (mode, SUBREG_REG (x)); 5793 5794 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) 5795 break; 5796 { 5797 rtx temp; 5798 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, 5799 SUBREG_BYTE (x)); 5800 if (temp) 5801 return temp; 5802 5803 /* If op is known to have all lower bits zero, the result is zero. */ 5804 if (!in_dest 5805 && SCALAR_INT_MODE_P (mode) 5806 && SCALAR_INT_MODE_P (op0_mode) 5807 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode) 5808 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) 5809 && HWI_COMPUTABLE_MODE_P (op0_mode) 5810 && (nonzero_bits (SUBREG_REG (x), op0_mode) 5811 & GET_MODE_MASK (mode)) == 0) 5812 return CONST0_RTX (mode); 5813 } 5814 5815 /* Don't change the mode of the MEM if that would change the meaning 5816 of the address. */ 5817 if (MEM_P (SUBREG_REG (x)) 5818 && (MEM_VOLATILE_P (SUBREG_REG (x)) 5819 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0), 5820 MEM_ADDR_SPACE (SUBREG_REG (x))))) 5821 return gen_rtx_CLOBBER (mode, const0_rtx); 5822 5823 /* Note that we cannot do any narrowing for non-constants since 5824 we might have been counting on using the fact that some bits were 5825 zero. We now do this in the SET. */ 5826 5827 break; 5828 5829 case NEG: 5830 temp = expand_compound_operation (XEXP (x, 0)); 5831 5832 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be 5833 replaced by (lshiftrt X C). This will convert 5834 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ 5835 5836 if (GET_CODE (temp) == ASHIFTRT 5837 && CONST_INT_P (XEXP (temp, 1)) 5838 && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1) 5839 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0), 5840 INTVAL (XEXP (temp, 1))); 5841 5842 /* If X has only a single bit that might be nonzero, say, bit I, convert 5843 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of 5844 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to 5845 (sign_extract X 1 Y). But only do this if TEMP isn't a register 5846 or a SUBREG of one since we'd be making the expression more 5847 complex if it was just a register. */ 5848 5849 if (!REG_P (temp) 5850 && ! (GET_CODE (temp) == SUBREG 5851 && REG_P (SUBREG_REG (temp))) 5852 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) 5853 { 5854 rtx temp1 = simplify_shift_const 5855 (NULL_RTX, ASHIFTRT, mode, 5856 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, 5857 GET_MODE_PRECISION (mode) - 1 - i), 5858 GET_MODE_PRECISION (mode) - 1 - i); 5859 5860 /* If all we did was surround TEMP with the two shifts, we 5861 haven't improved anything, so don't use it. Otherwise, 5862 we are better off with TEMP1. */ 5863 if (GET_CODE (temp1) != ASHIFTRT 5864 || GET_CODE (XEXP (temp1, 0)) != ASHIFT 5865 || XEXP (XEXP (temp1, 0), 0) != temp) 5866 return temp1; 5867 } 5868 break; 5869 5870 case TRUNCATE: 5871 /* We can't handle truncation to a partial integer mode here 5872 because we don't know the real bitsize of the partial 5873 integer mode. */ 5874 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) 5875 break; 5876 5877 if (HWI_COMPUTABLE_MODE_P (mode)) 5878 SUBST (XEXP (x, 0), 5879 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), 5880 GET_MODE_MASK (mode), 0)); 5881 5882 /* We can truncate a constant value and return it. */ 5883 if (CONST_INT_P (XEXP (x, 0))) 5884 return gen_int_mode (INTVAL (XEXP (x, 0)), mode); 5885 5886 /* Similarly to what we do in simplify-rtx.c, a truncate of a register 5887 whose value is a comparison can be replaced with a subreg if 5888 STORE_FLAG_VALUE permits. */ 5889 if (HWI_COMPUTABLE_MODE_P (mode) 5890 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 5891 && (temp = get_last_value (XEXP (x, 0))) 5892 && COMPARISON_P (temp)) 5893 return gen_lowpart (mode, XEXP (x, 0)); 5894 break; 5895 5896 case CONST: 5897 /* (const (const X)) can become (const X). Do it this way rather than 5898 returning the inner CONST since CONST can be shared with a 5899 REG_EQUAL note. */ 5900 if (GET_CODE (XEXP (x, 0)) == CONST) 5901 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 5902 break; 5903 5904 case LO_SUM: 5905 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we 5906 can add in an offset. find_split_point will split this address up 5907 again if it doesn't match. */ 5908 if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH 5909 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) 5910 return XEXP (x, 1); 5911 break; 5912 5913 case PLUS: 5914 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) 5915 when c is (const_int (pow2 + 1) / 2) is a sign extension of a 5916 bit-field and can be replaced by either a sign_extend or a 5917 sign_extract. The `and' may be a zero_extend and the two 5918 <c>, -<c> constants may be reversed. */ 5919 if (GET_CODE (XEXP (x, 0)) == XOR 5920 && CONST_INT_P (XEXP (x, 1)) 5921 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 5922 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) 5923 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 5924 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0) 5925 && HWI_COMPUTABLE_MODE_P (mode) 5926 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND 5927 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1)) 5928 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) 5929 == (HOST_WIDE_INT_1U << (i + 1)) - 1)) 5930 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND 5931 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) 5932 == (unsigned int) i + 1)))) 5933 return simplify_shift_const 5934 (NULL_RTX, ASHIFTRT, mode, 5935 simplify_shift_const (NULL_RTX, ASHIFT, mode, 5936 XEXP (XEXP (XEXP (x, 0), 0), 0), 5937 GET_MODE_PRECISION (mode) - (i + 1)), 5938 GET_MODE_PRECISION (mode) - (i + 1)); 5939 5940 /* If only the low-order bit of X is possibly nonzero, (plus x -1) 5941 can become (ashiftrt (ashift (xor x 1) C) C) where C is 5942 the bitsize of the mode - 1. This allows simplification of 5943 "a = (b & 8) == 0;" */ 5944 if (XEXP (x, 1) == constm1_rtx 5945 && !REG_P (XEXP (x, 0)) 5946 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 5947 && REG_P (SUBREG_REG (XEXP (x, 0)))) 5948 && nonzero_bits (XEXP (x, 0), mode) == 1) 5949 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, 5950 simplify_shift_const (NULL_RTX, ASHIFT, mode, 5951 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), 5952 GET_MODE_PRECISION (mode) - 1), 5953 GET_MODE_PRECISION (mode) - 1); 5954 5955 /* If we are adding two things that have no bits in common, convert 5956 the addition into an IOR. This will often be further simplified, 5957 for example in cases like ((a & 1) + (a & 2)), which can 5958 become a & 3. */ 5959 5960 if (HWI_COMPUTABLE_MODE_P (mode) 5961 && (nonzero_bits (XEXP (x, 0), mode) 5962 & nonzero_bits (XEXP (x, 1), mode)) == 0) 5963 { 5964 /* Try to simplify the expression further. */ 5965 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 5966 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0); 5967 5968 /* If we could, great. If not, do not go ahead with the IOR 5969 replacement, since PLUS appears in many special purpose 5970 address arithmetic instructions. */ 5971 if (GET_CODE (temp) != CLOBBER 5972 && (GET_CODE (temp) != IOR 5973 || ((XEXP (temp, 0) != XEXP (x, 0) 5974 || XEXP (temp, 1) != XEXP (x, 1)) 5975 && (XEXP (temp, 0) != XEXP (x, 1) 5976 || XEXP (temp, 1) != XEXP (x, 0))))) 5977 return temp; 5978 } 5979 5980 /* Canonicalize x + x into x << 1. */ 5981 if (GET_MODE_CLASS (mode) == MODE_INT 5982 && rtx_equal_p (XEXP (x, 0), XEXP (x, 1)) 5983 && !side_effects_p (XEXP (x, 0))) 5984 return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx); 5985 5986 break; 5987 5988 case MINUS: 5989 /* (minus <foo> (and <foo> (const_int -pow2))) becomes 5990 (and <foo> (const_int pow2-1)) */ 5991 if (GET_CODE (XEXP (x, 1)) == AND 5992 && CONST_INT_P (XEXP (XEXP (x, 1), 1)) 5993 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1))) 5994 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 5995 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), 5996 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); 5997 break; 5998 5999 case MULT: 6000 /* If we have (mult (plus A B) C), apply the distributive law and then 6001 the inverse distributive law to see if things simplify. This 6002 occurs mostly in addresses, often when unrolling loops. */ 6003 6004 if (GET_CODE (XEXP (x, 0)) == PLUS) 6005 { 6006 rtx result = distribute_and_simplify_rtx (x, 0); 6007 if (result) 6008 return result; 6009 } 6010 6011 /* Try simplify a*(b/c) as (a*b)/c. */ 6012 if (FLOAT_MODE_P (mode) && flag_associative_math 6013 && GET_CODE (XEXP (x, 0)) == DIV) 6014 { 6015 rtx tem = simplify_binary_operation (MULT, mode, 6016 XEXP (XEXP (x, 0), 0), 6017 XEXP (x, 1)); 6018 if (tem) 6019 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); 6020 } 6021 break; 6022 6023 case UDIV: 6024 /* If this is a divide by a power of two, treat it as a shift if 6025 its first operand is a shift. */ 6026 if (CONST_INT_P (XEXP (x, 1)) 6027 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0 6028 && (GET_CODE (XEXP (x, 0)) == ASHIFT 6029 || GET_CODE (XEXP (x, 0)) == LSHIFTRT 6030 || GET_CODE (XEXP (x, 0)) == ASHIFTRT 6031 || GET_CODE (XEXP (x, 0)) == ROTATE 6032 || GET_CODE (XEXP (x, 0)) == ROTATERT)) 6033 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); 6034 break; 6035 6036 case EQ: case NE: 6037 case GT: case GTU: case GE: case GEU: 6038 case LT: case LTU: case LE: case LEU: 6039 case UNEQ: case LTGT: 6040 case UNGT: case UNGE: 6041 case UNLT: case UNLE: 6042 case UNORDERED: case ORDERED: 6043 /* If the first operand is a condition code, we can't do anything 6044 with it. */ 6045 if (GET_CODE (XEXP (x, 0)) == COMPARE 6046 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC 6047 && ! CC0_P (XEXP (x, 0)))) 6048 { 6049 rtx op0 = XEXP (x, 0); 6050 rtx op1 = XEXP (x, 1); 6051 enum rtx_code new_code; 6052 6053 if (GET_CODE (op0) == COMPARE) 6054 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 6055 6056 /* Simplify our comparison, if possible. */ 6057 new_code = simplify_comparison (code, &op0, &op1); 6058 6059 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X 6060 if only the low-order bit is possibly nonzero in X (such as when 6061 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to 6062 (xor X 1) or (minus 1 X); we use the former. Finally, if X is 6063 known to be either 0 or -1, NE becomes a NEG and EQ becomes 6064 (plus X 1). 6065 6066 Remove any ZERO_EXTRACT we made when thinking this was a 6067 comparison. It may now be simpler to use, e.g., an AND. If a 6068 ZERO_EXTRACT is indeed appropriate, it will be placed back by 6069 the call to make_compound_operation in the SET case. 6070 6071 Don't apply these optimizations if the caller would 6072 prefer a comparison rather than a value. 6073 E.g., for the condition in an IF_THEN_ELSE most targets need 6074 an explicit comparison. */ 6075 6076 if (in_cond) 6077 ; 6078 6079 else if (STORE_FLAG_VALUE == 1 6080 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 6081 && op1 == const0_rtx 6082 && mode == GET_MODE (op0) 6083 && nonzero_bits (op0, mode) == 1) 6084 return gen_lowpart (mode, 6085 expand_compound_operation (op0)); 6086 6087 else if (STORE_FLAG_VALUE == 1 6088 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 6089 && op1 == const0_rtx 6090 && mode == GET_MODE (op0) 6091 && (num_sign_bit_copies (op0, mode) 6092 == GET_MODE_PRECISION (mode))) 6093 { 6094 op0 = expand_compound_operation (op0); 6095 return simplify_gen_unary (NEG, mode, 6096 gen_lowpart (mode, op0), 6097 mode); 6098 } 6099 6100 else if (STORE_FLAG_VALUE == 1 6101 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 6102 && op1 == const0_rtx 6103 && mode == GET_MODE (op0) 6104 && nonzero_bits (op0, mode) == 1) 6105 { 6106 op0 = expand_compound_operation (op0); 6107 return simplify_gen_binary (XOR, mode, 6108 gen_lowpart (mode, op0), 6109 const1_rtx); 6110 } 6111 6112 else if (STORE_FLAG_VALUE == 1 6113 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 6114 && op1 == const0_rtx 6115 && mode == GET_MODE (op0) 6116 && (num_sign_bit_copies (op0, mode) 6117 == GET_MODE_PRECISION (mode))) 6118 { 6119 op0 = expand_compound_operation (op0); 6120 return plus_constant (mode, gen_lowpart (mode, op0), 1); 6121 } 6122 6123 /* If STORE_FLAG_VALUE is -1, we have cases similar to 6124 those above. */ 6125 if (in_cond) 6126 ; 6127 6128 else if (STORE_FLAG_VALUE == -1 6129 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 6130 && op1 == const0_rtx 6131 && mode == GET_MODE (op0) 6132 && (num_sign_bit_copies (op0, mode) 6133 == GET_MODE_PRECISION (mode))) 6134 return gen_lowpart (mode, 6135 expand_compound_operation (op0)); 6136 6137 else if (STORE_FLAG_VALUE == -1 6138 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 6139 && op1 == const0_rtx 6140 && mode == GET_MODE (op0) 6141 && nonzero_bits (op0, mode) == 1) 6142 { 6143 op0 = expand_compound_operation (op0); 6144 return simplify_gen_unary (NEG, mode, 6145 gen_lowpart (mode, op0), 6146 mode); 6147 } 6148 6149 else if (STORE_FLAG_VALUE == -1 6150 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 6151 && op1 == const0_rtx 6152 && mode == GET_MODE (op0) 6153 && (num_sign_bit_copies (op0, mode) 6154 == GET_MODE_PRECISION (mode))) 6155 { 6156 op0 = expand_compound_operation (op0); 6157 return simplify_gen_unary (NOT, mode, 6158 gen_lowpart (mode, op0), 6159 mode); 6160 } 6161 6162 /* If X is 0/1, (eq X 0) is X-1. */ 6163 else if (STORE_FLAG_VALUE == -1 6164 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 6165 && op1 == const0_rtx 6166 && mode == GET_MODE (op0) 6167 && nonzero_bits (op0, mode) == 1) 6168 { 6169 op0 = expand_compound_operation (op0); 6170 return plus_constant (mode, gen_lowpart (mode, op0), -1); 6171 } 6172 6173 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just 6174 one bit that might be nonzero, we can convert (ne x 0) to 6175 (ashift x c) where C puts the bit in the sign bit. Remove any 6176 AND with STORE_FLAG_VALUE when we are done, since we are only 6177 going to test the sign bit. */ 6178 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 6179 && HWI_COMPUTABLE_MODE_P (mode) 6180 && val_signbit_p (mode, STORE_FLAG_VALUE) 6181 && op1 == const0_rtx 6182 && mode == GET_MODE (op0) 6183 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) 6184 { 6185 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, 6186 expand_compound_operation (op0), 6187 GET_MODE_PRECISION (mode) - 1 - i); 6188 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) 6189 return XEXP (x, 0); 6190 else 6191 return x; 6192 } 6193 6194 /* If the code changed, return a whole new comparison. 6195 We also need to avoid using SUBST in cases where 6196 simplify_comparison has widened a comparison with a CONST_INT, 6197 since in that case the wider CONST_INT may fail the sanity 6198 checks in do_SUBST. */ 6199 if (new_code != code 6200 || (CONST_INT_P (op1) 6201 && GET_MODE (op0) != GET_MODE (XEXP (x, 0)) 6202 && GET_MODE (op0) != GET_MODE (XEXP (x, 1)))) 6203 return gen_rtx_fmt_ee (new_code, mode, op0, op1); 6204 6205 /* Otherwise, keep this operation, but maybe change its operands. 6206 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ 6207 SUBST (XEXP (x, 0), op0); 6208 SUBST (XEXP (x, 1), op1); 6209 } 6210 break; 6211 6212 case IF_THEN_ELSE: 6213 return simplify_if_then_else (x); 6214 6215 case ZERO_EXTRACT: 6216 case SIGN_EXTRACT: 6217 case ZERO_EXTEND: 6218 case SIGN_EXTEND: 6219 /* If we are processing SET_DEST, we are done. */ 6220 if (in_dest) 6221 return x; 6222 6223 return expand_compound_operation (x); 6224 6225 case SET: 6226 return simplify_set (x); 6227 6228 case AND: 6229 case IOR: 6230 return simplify_logical (x); 6231 6232 case ASHIFT: 6233 case LSHIFTRT: 6234 case ASHIFTRT: 6235 case ROTATE: 6236 case ROTATERT: 6237 /* If this is a shift by a constant amount, simplify it. */ 6238 if (CONST_INT_P (XEXP (x, 1))) 6239 return simplify_shift_const (x, code, mode, XEXP (x, 0), 6240 INTVAL (XEXP (x, 1))); 6241 6242 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1))) 6243 SUBST (XEXP (x, 1), 6244 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)), 6245 (HOST_WIDE_INT_1U 6246 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) 6247 - 1, 6248 0)); 6249 break; 6250 6251 default: 6252 break; 6253 } 6254 6255 return x; 6256 } 6257 6258 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ 6259 6260 static rtx 6261 simplify_if_then_else (rtx x) 6262 { 6263 machine_mode mode = GET_MODE (x); 6264 rtx cond = XEXP (x, 0); 6265 rtx true_rtx = XEXP (x, 1); 6266 rtx false_rtx = XEXP (x, 2); 6267 enum rtx_code true_code = GET_CODE (cond); 6268 int comparison_p = COMPARISON_P (cond); 6269 rtx temp; 6270 int i; 6271 enum rtx_code false_code; 6272 rtx reversed; 6273 6274 /* Simplify storing of the truth value. */ 6275 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) 6276 return simplify_gen_relational (true_code, mode, VOIDmode, 6277 XEXP (cond, 0), XEXP (cond, 1)); 6278 6279 /* Also when the truth value has to be reversed. */ 6280 if (comparison_p 6281 && true_rtx == const0_rtx && false_rtx == const_true_rtx 6282 && (reversed = reversed_comparison (cond, mode))) 6283 return reversed; 6284 6285 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used 6286 in it is being compared against certain values. Get the true and false 6287 comparisons and see if that says anything about the value of each arm. */ 6288 6289 if (comparison_p 6290 && ((false_code = reversed_comparison_code (cond, NULL)) 6291 != UNKNOWN) 6292 && REG_P (XEXP (cond, 0))) 6293 { 6294 HOST_WIDE_INT nzb; 6295 rtx from = XEXP (cond, 0); 6296 rtx true_val = XEXP (cond, 1); 6297 rtx false_val = true_val; 6298 int swapped = 0; 6299 6300 /* If FALSE_CODE is EQ, swap the codes and arms. */ 6301 6302 if (false_code == EQ) 6303 { 6304 swapped = 1, true_code = EQ, false_code = NE; 6305 std::swap (true_rtx, false_rtx); 6306 } 6307 6308 /* If we are comparing against zero and the expression being tested has 6309 only a single bit that might be nonzero, that is its value when it is 6310 not equal to zero. Similarly if it is known to be -1 or 0. */ 6311 6312 if (true_code == EQ && true_val == const0_rtx 6313 && pow2p_hwi (nzb = nonzero_bits (from, GET_MODE (from)))) 6314 { 6315 false_code = EQ; 6316 false_val = gen_int_mode (nzb, GET_MODE (from)); 6317 } 6318 else if (true_code == EQ && true_val == const0_rtx 6319 && (num_sign_bit_copies (from, GET_MODE (from)) 6320 == GET_MODE_PRECISION (GET_MODE (from)))) 6321 { 6322 false_code = EQ; 6323 false_val = constm1_rtx; 6324 } 6325 6326 /* Now simplify an arm if we know the value of the register in the 6327 branch and it is used in the arm. Be careful due to the potential 6328 of locally-shared RTL. */ 6329 6330 if (reg_mentioned_p (from, true_rtx)) 6331 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, 6332 from, true_val), 6333 pc_rtx, pc_rtx, 0, 0, 0); 6334 if (reg_mentioned_p (from, false_rtx)) 6335 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, 6336 from, false_val), 6337 pc_rtx, pc_rtx, 0, 0, 0); 6338 6339 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); 6340 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); 6341 6342 true_rtx = XEXP (x, 1); 6343 false_rtx = XEXP (x, 2); 6344 true_code = GET_CODE (cond); 6345 } 6346 6347 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be 6348 reversed, do so to avoid needing two sets of patterns for 6349 subtract-and-branch insns. Similarly if we have a constant in the true 6350 arm, the false arm is the same as the first operand of the comparison, or 6351 the false arm is more complicated than the true arm. */ 6352 6353 if (comparison_p 6354 && reversed_comparison_code (cond, NULL) != UNKNOWN 6355 && (true_rtx == pc_rtx 6356 || (CONSTANT_P (true_rtx) 6357 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx) 6358 || true_rtx == const0_rtx 6359 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx)) 6360 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx)) 6361 && !OBJECT_P (false_rtx)) 6362 || reg_mentioned_p (true_rtx, false_rtx) 6363 || rtx_equal_p (false_rtx, XEXP (cond, 0)))) 6364 { 6365 true_code = reversed_comparison_code (cond, NULL); 6366 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond))); 6367 SUBST (XEXP (x, 1), false_rtx); 6368 SUBST (XEXP (x, 2), true_rtx); 6369 6370 std::swap (true_rtx, false_rtx); 6371 cond = XEXP (x, 0); 6372 6373 /* It is possible that the conditional has been simplified out. */ 6374 true_code = GET_CODE (cond); 6375 comparison_p = COMPARISON_P (cond); 6376 } 6377 6378 /* If the two arms are identical, we don't need the comparison. */ 6379 6380 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) 6381 return true_rtx; 6382 6383 /* Convert a == b ? b : a to "a". */ 6384 if (true_code == EQ && ! side_effects_p (cond) 6385 && !HONOR_NANS (mode) 6386 && rtx_equal_p (XEXP (cond, 0), false_rtx) 6387 && rtx_equal_p (XEXP (cond, 1), true_rtx)) 6388 return false_rtx; 6389 else if (true_code == NE && ! side_effects_p (cond) 6390 && !HONOR_NANS (mode) 6391 && rtx_equal_p (XEXP (cond, 0), true_rtx) 6392 && rtx_equal_p (XEXP (cond, 1), false_rtx)) 6393 return true_rtx; 6394 6395 /* Look for cases where we have (abs x) or (neg (abs X)). */ 6396 6397 if (GET_MODE_CLASS (mode) == MODE_INT 6398 && comparison_p 6399 && XEXP (cond, 1) == const0_rtx 6400 && GET_CODE (false_rtx) == NEG 6401 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) 6402 && rtx_equal_p (true_rtx, XEXP (cond, 0)) 6403 && ! side_effects_p (true_rtx)) 6404 switch (true_code) 6405 { 6406 case GT: 6407 case GE: 6408 return simplify_gen_unary (ABS, mode, true_rtx, mode); 6409 case LT: 6410 case LE: 6411 return 6412 simplify_gen_unary (NEG, mode, 6413 simplify_gen_unary (ABS, mode, true_rtx, mode), 6414 mode); 6415 default: 6416 break; 6417 } 6418 6419 /* Look for MIN or MAX. */ 6420 6421 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) 6422 && comparison_p 6423 && rtx_equal_p (XEXP (cond, 0), true_rtx) 6424 && rtx_equal_p (XEXP (cond, 1), false_rtx) 6425 && ! side_effects_p (cond)) 6426 switch (true_code) 6427 { 6428 case GE: 6429 case GT: 6430 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx); 6431 case LE: 6432 case LT: 6433 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx); 6434 case GEU: 6435 case GTU: 6436 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx); 6437 case LEU: 6438 case LTU: 6439 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx); 6440 default: 6441 break; 6442 } 6443 6444 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its 6445 second operand is zero, this can be done as (OP Z (mult COND C2)) where 6446 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or 6447 SIGN_EXTEND as long as Z is already extended (so we don't destroy it). 6448 We can do this kind of thing in some cases when STORE_FLAG_VALUE is 6449 neither 1 or -1, but it isn't worth checking for. */ 6450 6451 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 6452 && comparison_p 6453 && GET_MODE_CLASS (mode) == MODE_INT 6454 && ! side_effects_p (x)) 6455 { 6456 rtx t = make_compound_operation (true_rtx, SET); 6457 rtx f = make_compound_operation (false_rtx, SET); 6458 rtx cond_op0 = XEXP (cond, 0); 6459 rtx cond_op1 = XEXP (cond, 1); 6460 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; 6461 machine_mode m = mode; 6462 rtx z = 0, c1 = NULL_RTX; 6463 6464 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS 6465 || GET_CODE (t) == IOR || GET_CODE (t) == XOR 6466 || GET_CODE (t) == ASHIFT 6467 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) 6468 && rtx_equal_p (XEXP (t, 0), f)) 6469 c1 = XEXP (t, 1), op = GET_CODE (t), z = f; 6470 6471 /* If an identity-zero op is commutative, check whether there 6472 would be a match if we swapped the operands. */ 6473 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR 6474 || GET_CODE (t) == XOR) 6475 && rtx_equal_p (XEXP (t, 1), f)) 6476 c1 = XEXP (t, 0), op = GET_CODE (t), z = f; 6477 else if (GET_CODE (t) == SIGN_EXTEND 6478 && (GET_CODE (XEXP (t, 0)) == PLUS 6479 || GET_CODE (XEXP (t, 0)) == MINUS 6480 || GET_CODE (XEXP (t, 0)) == IOR 6481 || GET_CODE (XEXP (t, 0)) == XOR 6482 || GET_CODE (XEXP (t, 0)) == ASHIFT 6483 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 6484 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 6485 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 6486 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 6487 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 6488 && (num_sign_bit_copies (f, GET_MODE (f)) 6489 > (unsigned int) 6490 (GET_MODE_PRECISION (mode) 6491 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0)))))) 6492 { 6493 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 6494 extend_op = SIGN_EXTEND; 6495 m = GET_MODE (XEXP (t, 0)); 6496 } 6497 else if (GET_CODE (t) == SIGN_EXTEND 6498 && (GET_CODE (XEXP (t, 0)) == PLUS 6499 || GET_CODE (XEXP (t, 0)) == IOR 6500 || GET_CODE (XEXP (t, 0)) == XOR) 6501 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 6502 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 6503 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 6504 && (num_sign_bit_copies (f, GET_MODE (f)) 6505 > (unsigned int) 6506 (GET_MODE_PRECISION (mode) 6507 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1)))))) 6508 { 6509 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 6510 extend_op = SIGN_EXTEND; 6511 m = GET_MODE (XEXP (t, 0)); 6512 } 6513 else if (GET_CODE (t) == ZERO_EXTEND 6514 && (GET_CODE (XEXP (t, 0)) == PLUS 6515 || GET_CODE (XEXP (t, 0)) == MINUS 6516 || GET_CODE (XEXP (t, 0)) == IOR 6517 || GET_CODE (XEXP (t, 0)) == XOR 6518 || GET_CODE (XEXP (t, 0)) == ASHIFT 6519 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 6520 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 6521 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 6522 && HWI_COMPUTABLE_MODE_P (mode) 6523 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 6524 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 6525 && ((nonzero_bits (f, GET_MODE (f)) 6526 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) 6527 == 0)) 6528 { 6529 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 6530 extend_op = ZERO_EXTEND; 6531 m = GET_MODE (XEXP (t, 0)); 6532 } 6533 else if (GET_CODE (t) == ZERO_EXTEND 6534 && (GET_CODE (XEXP (t, 0)) == PLUS 6535 || GET_CODE (XEXP (t, 0)) == IOR 6536 || GET_CODE (XEXP (t, 0)) == XOR) 6537 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 6538 && HWI_COMPUTABLE_MODE_P (mode) 6539 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 6540 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 6541 && ((nonzero_bits (f, GET_MODE (f)) 6542 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) 6543 == 0)) 6544 { 6545 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 6546 extend_op = ZERO_EXTEND; 6547 m = GET_MODE (XEXP (t, 0)); 6548 } 6549 6550 if (z) 6551 { 6552 machine_mode cm = m; 6553 if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT) 6554 && GET_MODE (c1) != VOIDmode) 6555 cm = GET_MODE (c1); 6556 temp = subst (simplify_gen_relational (true_code, cm, VOIDmode, 6557 cond_op0, cond_op1), 6558 pc_rtx, pc_rtx, 0, 0, 0); 6559 temp = simplify_gen_binary (MULT, cm, temp, 6560 simplify_gen_binary (MULT, cm, c1, 6561 const_true_rtx)); 6562 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0); 6563 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); 6564 6565 if (extend_op != UNKNOWN) 6566 temp = simplify_gen_unary (extend_op, mode, temp, m); 6567 6568 return temp; 6569 } 6570 } 6571 6572 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or 6573 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the 6574 negation of a single bit, we can convert this operation to a shift. We 6575 can actually do this more generally, but it doesn't seem worth it. */ 6576 6577 if (true_code == NE && XEXP (cond, 1) == const0_rtx 6578 && false_rtx == const0_rtx && CONST_INT_P (true_rtx) 6579 && ((1 == nonzero_bits (XEXP (cond, 0), mode) 6580 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0) 6581 || ((num_sign_bit_copies (XEXP (cond, 0), mode) 6582 == GET_MODE_PRECISION (mode)) 6583 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0))) 6584 return 6585 simplify_shift_const (NULL_RTX, ASHIFT, mode, 6586 gen_lowpart (mode, XEXP (cond, 0)), i); 6587 6588 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only 6589 non-zero bit in A is C1. */ 6590 if (true_code == NE && XEXP (cond, 1) == const0_rtx 6591 && false_rtx == const0_rtx && CONST_INT_P (true_rtx) 6592 && INTEGRAL_MODE_P (GET_MODE (XEXP (cond, 0))) 6593 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode)) 6594 == nonzero_bits (XEXP (cond, 0), GET_MODE (XEXP (cond, 0))) 6595 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0) 6596 { 6597 rtx val = XEXP (cond, 0); 6598 enum machine_mode val_mode = GET_MODE (val); 6599 if (val_mode == mode) 6600 return val; 6601 else if (GET_MODE_PRECISION (val_mode) < GET_MODE_PRECISION (mode)) 6602 return simplify_gen_unary (ZERO_EXTEND, mode, val, val_mode); 6603 } 6604 6605 return x; 6606 } 6607 6608 /* Simplify X, a SET expression. Return the new expression. */ 6609 6610 static rtx 6611 simplify_set (rtx x) 6612 { 6613 rtx src = SET_SRC (x); 6614 rtx dest = SET_DEST (x); 6615 machine_mode mode 6616 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); 6617 rtx_insn *other_insn; 6618 rtx *cc_use; 6619 6620 /* (set (pc) (return)) gets written as (return). */ 6621 if (GET_CODE (dest) == PC && ANY_RETURN_P (src)) 6622 return src; 6623 6624 /* Now that we know for sure which bits of SRC we are using, see if we can 6625 simplify the expression for the object knowing that we only need the 6626 low-order bits. */ 6627 6628 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode)) 6629 { 6630 src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, 0); 6631 SUBST (SET_SRC (x), src); 6632 } 6633 6634 /* If we are setting CC0 or if the source is a COMPARE, look for the use of 6635 the comparison result and try to simplify it unless we already have used 6636 undobuf.other_insn. */ 6637 if ((GET_MODE_CLASS (mode) == MODE_CC 6638 || GET_CODE (src) == COMPARE 6639 || CC0_P (dest)) 6640 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 6641 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) 6642 && COMPARISON_P (*cc_use) 6643 && rtx_equal_p (XEXP (*cc_use, 0), dest)) 6644 { 6645 enum rtx_code old_code = GET_CODE (*cc_use); 6646 enum rtx_code new_code; 6647 rtx op0, op1, tmp; 6648 int other_changed = 0; 6649 rtx inner_compare = NULL_RTX; 6650 machine_mode compare_mode = GET_MODE (dest); 6651 6652 if (GET_CODE (src) == COMPARE) 6653 { 6654 op0 = XEXP (src, 0), op1 = XEXP (src, 1); 6655 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) 6656 { 6657 inner_compare = op0; 6658 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1); 6659 } 6660 } 6661 else 6662 op0 = src, op1 = CONST0_RTX (GET_MODE (src)); 6663 6664 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode, 6665 op0, op1); 6666 if (!tmp) 6667 new_code = old_code; 6668 else if (!CONSTANT_P (tmp)) 6669 { 6670 new_code = GET_CODE (tmp); 6671 op0 = XEXP (tmp, 0); 6672 op1 = XEXP (tmp, 1); 6673 } 6674 else 6675 { 6676 rtx pat = PATTERN (other_insn); 6677 undobuf.other_insn = other_insn; 6678 SUBST (*cc_use, tmp); 6679 6680 /* Attempt to simplify CC user. */ 6681 if (GET_CODE (pat) == SET) 6682 { 6683 rtx new_rtx = simplify_rtx (SET_SRC (pat)); 6684 if (new_rtx != NULL_RTX) 6685 SUBST (SET_SRC (pat), new_rtx); 6686 } 6687 6688 /* Convert X into a no-op move. */ 6689 SUBST (SET_DEST (x), pc_rtx); 6690 SUBST (SET_SRC (x), pc_rtx); 6691 return x; 6692 } 6693 6694 /* Simplify our comparison, if possible. */ 6695 new_code = simplify_comparison (new_code, &op0, &op1); 6696 6697 #ifdef SELECT_CC_MODE 6698 /* If this machine has CC modes other than CCmode, check to see if we 6699 need to use a different CC mode here. */ 6700 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) 6701 compare_mode = GET_MODE (op0); 6702 else if (inner_compare 6703 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC 6704 && new_code == old_code 6705 && op0 == XEXP (inner_compare, 0) 6706 && op1 == XEXP (inner_compare, 1)) 6707 compare_mode = GET_MODE (inner_compare); 6708 else 6709 compare_mode = SELECT_CC_MODE (new_code, op0, op1); 6710 6711 /* If the mode changed, we have to change SET_DEST, the mode in the 6712 compare, and the mode in the place SET_DEST is used. If SET_DEST is 6713 a hard register, just build new versions with the proper mode. If it 6714 is a pseudo, we lose unless it is only time we set the pseudo, in 6715 which case we can safely change its mode. */ 6716 if (!HAVE_cc0 && compare_mode != GET_MODE (dest)) 6717 { 6718 if (can_change_dest_mode (dest, 0, compare_mode)) 6719 { 6720 unsigned int regno = REGNO (dest); 6721 rtx new_dest; 6722 6723 if (regno < FIRST_PSEUDO_REGISTER) 6724 new_dest = gen_rtx_REG (compare_mode, regno); 6725 else 6726 { 6727 SUBST_MODE (regno_reg_rtx[regno], compare_mode); 6728 new_dest = regno_reg_rtx[regno]; 6729 } 6730 6731 SUBST (SET_DEST (x), new_dest); 6732 SUBST (XEXP (*cc_use, 0), new_dest); 6733 other_changed = 1; 6734 6735 dest = new_dest; 6736 } 6737 } 6738 #endif /* SELECT_CC_MODE */ 6739 6740 /* If the code changed, we have to build a new comparison in 6741 undobuf.other_insn. */ 6742 if (new_code != old_code) 6743 { 6744 int other_changed_previously = other_changed; 6745 unsigned HOST_WIDE_INT mask; 6746 rtx old_cc_use = *cc_use; 6747 6748 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), 6749 dest, const0_rtx)); 6750 other_changed = 1; 6751 6752 /* If the only change we made was to change an EQ into an NE or 6753 vice versa, OP0 has only one bit that might be nonzero, and OP1 6754 is zero, check if changing the user of the condition code will 6755 produce a valid insn. If it won't, we can keep the original code 6756 in that insn by surrounding our operation with an XOR. */ 6757 6758 if (((old_code == NE && new_code == EQ) 6759 || (old_code == EQ && new_code == NE)) 6760 && ! other_changed_previously && op1 == const0_rtx 6761 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0)) 6762 && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0)))) 6763 { 6764 rtx pat = PATTERN (other_insn), note = 0; 6765 6766 if ((recog_for_combine (&pat, other_insn, ¬e) < 0 6767 && ! check_asm_operands (pat))) 6768 { 6769 *cc_use = old_cc_use; 6770 other_changed = 0; 6771 6772 op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0, 6773 gen_int_mode (mask, 6774 GET_MODE (op0))); 6775 } 6776 } 6777 } 6778 6779 if (other_changed) 6780 undobuf.other_insn = other_insn; 6781 6782 /* Don't generate a compare of a CC with 0, just use that CC. */ 6783 if (GET_MODE (op0) == compare_mode && op1 == const0_rtx) 6784 { 6785 SUBST (SET_SRC (x), op0); 6786 src = SET_SRC (x); 6787 } 6788 /* Otherwise, if we didn't previously have the same COMPARE we 6789 want, create it from scratch. */ 6790 else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode 6791 || XEXP (src, 0) != op0 || XEXP (src, 1) != op1) 6792 { 6793 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); 6794 src = SET_SRC (x); 6795 } 6796 } 6797 else 6798 { 6799 /* Get SET_SRC in a form where we have placed back any 6800 compound expressions. Then do the checks below. */ 6801 src = make_compound_operation (src, SET); 6802 SUBST (SET_SRC (x), src); 6803 } 6804 6805 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, 6806 and X being a REG or (subreg (reg)), we may be able to convert this to 6807 (set (subreg:m2 x) (op)). 6808 6809 We can always do this if M1 is narrower than M2 because that means that 6810 we only care about the low bits of the result. 6811 6812 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot 6813 perform a narrower operation than requested since the high-order bits will 6814 be undefined. On machine where it is defined, this transformation is safe 6815 as long as M1 and M2 have the same number of words. */ 6816 6817 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 6818 && !OBJECT_P (SUBREG_REG (src)) 6819 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) 6820 / UNITS_PER_WORD) 6821 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) 6822 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) 6823 && (WORD_REGISTER_OPERATIONS 6824 || (GET_MODE_SIZE (GET_MODE (src)) 6825 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))) 6826 #ifdef CANNOT_CHANGE_MODE_CLASS 6827 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER 6828 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest), 6829 GET_MODE (SUBREG_REG (src)), 6830 GET_MODE (src))) 6831 #endif 6832 && (REG_P (dest) 6833 || (GET_CODE (dest) == SUBREG 6834 && REG_P (SUBREG_REG (dest))))) 6835 { 6836 SUBST (SET_DEST (x), 6837 gen_lowpart (GET_MODE (SUBREG_REG (src)), 6838 dest)); 6839 SUBST (SET_SRC (x), SUBREG_REG (src)); 6840 6841 src = SET_SRC (x), dest = SET_DEST (x); 6842 } 6843 6844 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg 6845 in SRC. */ 6846 if (dest == cc0_rtx 6847 && GET_CODE (src) == SUBREG 6848 && subreg_lowpart_p (src) 6849 && (GET_MODE_PRECISION (GET_MODE (src)) 6850 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src))))) 6851 { 6852 rtx inner = SUBREG_REG (src); 6853 machine_mode inner_mode = GET_MODE (inner); 6854 6855 /* Here we make sure that we don't have a sign bit on. */ 6856 if (val_signbit_known_clear_p (GET_MODE (src), 6857 nonzero_bits (inner, inner_mode))) 6858 { 6859 SUBST (SET_SRC (x), inner); 6860 src = SET_SRC (x); 6861 } 6862 } 6863 6864 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this 6865 would require a paradoxical subreg. Replace the subreg with a 6866 zero_extend to avoid the reload that would otherwise be required. */ 6867 6868 enum rtx_code extend_op; 6869 if (paradoxical_subreg_p (src) 6870 && MEM_P (SUBREG_REG (src)) 6871 && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN) 6872 { 6873 SUBST (SET_SRC (x), 6874 gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src))); 6875 6876 src = SET_SRC (x); 6877 } 6878 6879 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we 6880 are comparing an item known to be 0 or -1 against 0, use a logical 6881 operation instead. Check for one of the arms being an IOR of the other 6882 arm with some value. We compute three terms to be IOR'ed together. In 6883 practice, at most two will be nonzero. Then we do the IOR's. */ 6884 6885 if (GET_CODE (dest) != PC 6886 && GET_CODE (src) == IF_THEN_ELSE 6887 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT 6888 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) 6889 && XEXP (XEXP (src, 0), 1) == const0_rtx 6890 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) 6891 && (!HAVE_conditional_move 6892 || ! can_conditionally_move_p (GET_MODE (src))) 6893 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), 6894 GET_MODE (XEXP (XEXP (src, 0), 0))) 6895 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0)))) 6896 && ! side_effects_p (src)) 6897 { 6898 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE 6899 ? XEXP (src, 1) : XEXP (src, 2)); 6900 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE 6901 ? XEXP (src, 2) : XEXP (src, 1)); 6902 rtx term1 = const0_rtx, term2, term3; 6903 6904 if (GET_CODE (true_rtx) == IOR 6905 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) 6906 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx; 6907 else if (GET_CODE (true_rtx) == IOR 6908 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) 6909 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx; 6910 else if (GET_CODE (false_rtx) == IOR 6911 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) 6912 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx; 6913 else if (GET_CODE (false_rtx) == IOR 6914 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) 6915 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx; 6916 6917 term2 = simplify_gen_binary (AND, GET_MODE (src), 6918 XEXP (XEXP (src, 0), 0), true_rtx); 6919 term3 = simplify_gen_binary (AND, GET_MODE (src), 6920 simplify_gen_unary (NOT, GET_MODE (src), 6921 XEXP (XEXP (src, 0), 0), 6922 GET_MODE (src)), 6923 false_rtx); 6924 6925 SUBST (SET_SRC (x), 6926 simplify_gen_binary (IOR, GET_MODE (src), 6927 simplify_gen_binary (IOR, GET_MODE (src), 6928 term1, term2), 6929 term3)); 6930 6931 src = SET_SRC (x); 6932 } 6933 6934 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this 6935 whole thing fail. */ 6936 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) 6937 return src; 6938 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) 6939 return dest; 6940 else 6941 /* Convert this into a field assignment operation, if possible. */ 6942 return make_field_assignment (x); 6943 } 6944 6945 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified 6946 result. */ 6947 6948 static rtx 6949 simplify_logical (rtx x) 6950 { 6951 machine_mode mode = GET_MODE (x); 6952 rtx op0 = XEXP (x, 0); 6953 rtx op1 = XEXP (x, 1); 6954 6955 switch (GET_CODE (x)) 6956 { 6957 case AND: 6958 /* We can call simplify_and_const_int only if we don't lose 6959 any (sign) bits when converting INTVAL (op1) to 6960 "unsigned HOST_WIDE_INT". */ 6961 if (CONST_INT_P (op1) 6962 && (HWI_COMPUTABLE_MODE_P (mode) 6963 || INTVAL (op1) > 0)) 6964 { 6965 x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); 6966 if (GET_CODE (x) != AND) 6967 return x; 6968 6969 op0 = XEXP (x, 0); 6970 op1 = XEXP (x, 1); 6971 } 6972 6973 /* If we have any of (and (ior A B) C) or (and (xor A B) C), 6974 apply the distributive law and then the inverse distributive 6975 law to see if things simplify. */ 6976 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) 6977 { 6978 rtx result = distribute_and_simplify_rtx (x, 0); 6979 if (result) 6980 return result; 6981 } 6982 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) 6983 { 6984 rtx result = distribute_and_simplify_rtx (x, 1); 6985 if (result) 6986 return result; 6987 } 6988 break; 6989 6990 case IOR: 6991 /* If we have (ior (and A B) C), apply the distributive law and then 6992 the inverse distributive law to see if things simplify. */ 6993 6994 if (GET_CODE (op0) == AND) 6995 { 6996 rtx result = distribute_and_simplify_rtx (x, 0); 6997 if (result) 6998 return result; 6999 } 7000 7001 if (GET_CODE (op1) == AND) 7002 { 7003 rtx result = distribute_and_simplify_rtx (x, 1); 7004 if (result) 7005 return result; 7006 } 7007 break; 7008 7009 default: 7010 gcc_unreachable (); 7011 } 7012 7013 return x; 7014 } 7015 7016 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound 7017 operations" because they can be replaced with two more basic operations. 7018 ZERO_EXTEND is also considered "compound" because it can be replaced with 7019 an AND operation, which is simpler, though only one operation. 7020 7021 The function expand_compound_operation is called with an rtx expression 7022 and will convert it to the appropriate shifts and AND operations, 7023 simplifying at each stage. 7024 7025 The function make_compound_operation is called to convert an expression 7026 consisting of shifts and ANDs into the equivalent compound expression. 7027 It is the inverse of this function, loosely speaking. */ 7028 7029 static rtx 7030 expand_compound_operation (rtx x) 7031 { 7032 unsigned HOST_WIDE_INT pos = 0, len; 7033 int unsignedp = 0; 7034 unsigned int modewidth; 7035 rtx tem; 7036 7037 switch (GET_CODE (x)) 7038 { 7039 case ZERO_EXTEND: 7040 unsignedp = 1; 7041 /* FALLTHRU */ 7042 case SIGN_EXTEND: 7043 /* We can't necessarily use a const_int for a multiword mode; 7044 it depends on implicitly extending the value. 7045 Since we don't know the right way to extend it, 7046 we can't tell whether the implicit way is right. 7047 7048 Even for a mode that is no wider than a const_int, 7049 we can't win, because we need to sign extend one of its bits through 7050 the rest of it, and we don't know which bit. */ 7051 if (CONST_INT_P (XEXP (x, 0))) 7052 return x; 7053 7054 /* Return if (subreg:MODE FROM 0) is not a safe replacement for 7055 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM 7056 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be 7057 reloaded. If not for that, MEM's would very rarely be safe. 7058 7059 Reject MODEs bigger than a word, because we might not be able 7060 to reference a two-register group starting with an arbitrary register 7061 (and currently gen_lowpart might crash for a SUBREG). */ 7062 7063 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) 7064 return x; 7065 7066 /* Reject MODEs that aren't scalar integers because turning vector 7067 or complex modes into shifts causes problems. */ 7068 7069 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) 7070 return x; 7071 7072 len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))); 7073 /* If the inner object has VOIDmode (the only way this can happen 7074 is if it is an ASM_OPERANDS), we can't do anything since we don't 7075 know how much masking to do. */ 7076 if (len == 0) 7077 return x; 7078 7079 break; 7080 7081 case ZERO_EXTRACT: 7082 unsignedp = 1; 7083 7084 /* fall through */ 7085 7086 case SIGN_EXTRACT: 7087 /* If the operand is a CLOBBER, just return it. */ 7088 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 7089 return XEXP (x, 0); 7090 7091 if (!CONST_INT_P (XEXP (x, 1)) 7092 || !CONST_INT_P (XEXP (x, 2)) 7093 || GET_MODE (XEXP (x, 0)) == VOIDmode) 7094 return x; 7095 7096 /* Reject MODEs that aren't scalar integers because turning vector 7097 or complex modes into shifts causes problems. */ 7098 7099 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) 7100 return x; 7101 7102 len = INTVAL (XEXP (x, 1)); 7103 pos = INTVAL (XEXP (x, 2)); 7104 7105 /* This should stay within the object being extracted, fail otherwise. */ 7106 if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))) 7107 return x; 7108 7109 if (BITS_BIG_ENDIAN) 7110 pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos; 7111 7112 break; 7113 7114 default: 7115 return x; 7116 } 7117 /* Convert sign extension to zero extension, if we know that the high 7118 bit is not set, as this is easier to optimize. It will be converted 7119 back to cheaper alternative in make_extraction. */ 7120 if (GET_CODE (x) == SIGN_EXTEND 7121 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x)) 7122 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 7123 & ~(((unsigned HOST_WIDE_INT) 7124 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) 7125 >> 1)) 7126 == 0))) 7127 { 7128 machine_mode mode = GET_MODE (x); 7129 rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0)); 7130 rtx temp2 = expand_compound_operation (temp); 7131 7132 /* Make sure this is a profitable operation. */ 7133 if (set_src_cost (x, mode, optimize_this_for_speed_p) 7134 > set_src_cost (temp2, mode, optimize_this_for_speed_p)) 7135 return temp2; 7136 else if (set_src_cost (x, mode, optimize_this_for_speed_p) 7137 > set_src_cost (temp, mode, optimize_this_for_speed_p)) 7138 return temp; 7139 else 7140 return x; 7141 } 7142 7143 /* We can optimize some special cases of ZERO_EXTEND. */ 7144 if (GET_CODE (x) == ZERO_EXTEND) 7145 { 7146 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we 7147 know that the last value didn't have any inappropriate bits 7148 set. */ 7149 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 7150 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 7151 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)) 7152 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) 7153 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 7154 return XEXP (XEXP (x, 0), 0); 7155 7156 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 7157 if (GET_CODE (XEXP (x, 0)) == SUBREG 7158 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 7159 && subreg_lowpart_p (XEXP (x, 0)) 7160 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)) 7161 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) 7162 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 7163 return SUBREG_REG (XEXP (x, 0)); 7164 7165 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo 7166 is a comparison and STORE_FLAG_VALUE permits. This is like 7167 the first case, but it works even when GET_MODE (x) is larger 7168 than HOST_WIDE_INT. */ 7169 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 7170 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 7171 && COMPARISON_P (XEXP (XEXP (x, 0), 0)) 7172 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) 7173 <= HOST_BITS_PER_WIDE_INT) 7174 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 7175 return XEXP (XEXP (x, 0), 0); 7176 7177 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 7178 if (GET_CODE (XEXP (x, 0)) == SUBREG 7179 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 7180 && subreg_lowpart_p (XEXP (x, 0)) 7181 && COMPARISON_P (SUBREG_REG (XEXP (x, 0))) 7182 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) 7183 <= HOST_BITS_PER_WIDE_INT) 7184 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 7185 return SUBREG_REG (XEXP (x, 0)); 7186 7187 } 7188 7189 /* If we reach here, we want to return a pair of shifts. The inner 7190 shift is a left shift of BITSIZE - POS - LEN bits. The outer 7191 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or 7192 logical depending on the value of UNSIGNEDP. 7193 7194 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be 7195 converted into an AND of a shift. 7196 7197 We must check for the case where the left shift would have a negative 7198 count. This can happen in a case like (x >> 31) & 255 on machines 7199 that can't shift by a constant. On those machines, we would first 7200 combine the shift with the AND to produce a variable-position 7201 extraction. Then the constant of 31 would be substituted in 7202 to produce such a position. */ 7203 7204 modewidth = GET_MODE_PRECISION (GET_MODE (x)); 7205 if (modewidth >= pos + len) 7206 { 7207 machine_mode mode = GET_MODE (x); 7208 tem = gen_lowpart (mode, XEXP (x, 0)); 7209 if (!tem || GET_CODE (tem) == CLOBBER) 7210 return x; 7211 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode, 7212 tem, modewidth - pos - len); 7213 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, 7214 mode, tem, modewidth - len); 7215 } 7216 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) 7217 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), 7218 simplify_shift_const (NULL_RTX, LSHIFTRT, 7219 GET_MODE (x), 7220 XEXP (x, 0), pos), 7221 (HOST_WIDE_INT_1U << len) - 1); 7222 else 7223 /* Any other cases we can't handle. */ 7224 return x; 7225 7226 /* If we couldn't do this for some reason, return the original 7227 expression. */ 7228 if (GET_CODE (tem) == CLOBBER) 7229 return x; 7230 7231 return tem; 7232 } 7233 7234 /* X is a SET which contains an assignment of one object into 7235 a part of another (such as a bit-field assignment, STRICT_LOW_PART, 7236 or certain SUBREGS). If possible, convert it into a series of 7237 logical operations. 7238 7239 We half-heartedly support variable positions, but do not at all 7240 support variable lengths. */ 7241 7242 static const_rtx 7243 expand_field_assignment (const_rtx x) 7244 { 7245 rtx inner; 7246 rtx pos; /* Always counts from low bit. */ 7247 int len; 7248 rtx mask, cleared, masked; 7249 machine_mode compute_mode; 7250 7251 /* Loop until we find something we can't simplify. */ 7252 while (1) 7253 { 7254 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART 7255 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) 7256 { 7257 inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); 7258 len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))); 7259 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); 7260 } 7261 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 7262 && CONST_INT_P (XEXP (SET_DEST (x), 1))) 7263 { 7264 inner = XEXP (SET_DEST (x), 0); 7265 len = INTVAL (XEXP (SET_DEST (x), 1)); 7266 pos = XEXP (SET_DEST (x), 2); 7267 7268 /* A constant position should stay within the width of INNER. */ 7269 if (CONST_INT_P (pos) 7270 && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner))) 7271 break; 7272 7273 if (BITS_BIG_ENDIAN) 7274 { 7275 if (CONST_INT_P (pos)) 7276 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len 7277 - INTVAL (pos)); 7278 else if (GET_CODE (pos) == MINUS 7279 && CONST_INT_P (XEXP (pos, 1)) 7280 && (INTVAL (XEXP (pos, 1)) 7281 == GET_MODE_PRECISION (GET_MODE (inner)) - len)) 7282 /* If position is ADJUST - X, new position is X. */ 7283 pos = XEXP (pos, 0); 7284 else 7285 { 7286 HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner)); 7287 pos = simplify_gen_binary (MINUS, GET_MODE (pos), 7288 gen_int_mode (prec - len, 7289 GET_MODE (pos)), 7290 pos); 7291 } 7292 } 7293 } 7294 7295 /* A SUBREG between two modes that occupy the same numbers of words 7296 can be done by moving the SUBREG to the source. */ 7297 else if (GET_CODE (SET_DEST (x)) == SUBREG 7298 /* We need SUBREGs to compute nonzero_bits properly. */ 7299 && nonzero_sign_valid 7300 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 7301 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 7302 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 7303 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) 7304 { 7305 x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)), 7306 gen_lowpart 7307 (GET_MODE (SUBREG_REG (SET_DEST (x))), 7308 SET_SRC (x))); 7309 continue; 7310 } 7311 else 7312 break; 7313 7314 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 7315 inner = SUBREG_REG (inner); 7316 7317 compute_mode = GET_MODE (inner); 7318 7319 /* Don't attempt bitwise arithmetic on non scalar integer modes. */ 7320 if (! SCALAR_INT_MODE_P (compute_mode)) 7321 { 7322 machine_mode imode; 7323 7324 /* Don't do anything for vector or complex integral types. */ 7325 if (! FLOAT_MODE_P (compute_mode)) 7326 break; 7327 7328 /* Try to find an integral mode to pun with. */ 7329 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); 7330 if (imode == BLKmode) 7331 break; 7332 7333 compute_mode = imode; 7334 inner = gen_lowpart (imode, inner); 7335 } 7336 7337 /* Compute a mask of LEN bits, if we can do this on the host machine. */ 7338 if (len >= HOST_BITS_PER_WIDE_INT) 7339 break; 7340 7341 /* Don't try to compute in too wide unsupported modes. */ 7342 if (!targetm.scalar_mode_supported_p (compute_mode)) 7343 break; 7344 7345 /* Now compute the equivalent expression. Make a copy of INNER 7346 for the SET_DEST in case it is a MEM into which we will substitute; 7347 we don't want shared RTL in that case. */ 7348 mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1, 7349 compute_mode); 7350 cleared = simplify_gen_binary (AND, compute_mode, 7351 simplify_gen_unary (NOT, compute_mode, 7352 simplify_gen_binary (ASHIFT, 7353 compute_mode, 7354 mask, pos), 7355 compute_mode), 7356 inner); 7357 masked = simplify_gen_binary (ASHIFT, compute_mode, 7358 simplify_gen_binary ( 7359 AND, compute_mode, 7360 gen_lowpart (compute_mode, SET_SRC (x)), 7361 mask), 7362 pos); 7363 7364 x = gen_rtx_SET (copy_rtx (inner), 7365 simplify_gen_binary (IOR, compute_mode, 7366 cleared, masked)); 7367 } 7368 7369 return x; 7370 } 7371 7372 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, 7373 it is an RTX that represents the (variable) starting position; otherwise, 7374 POS is the (constant) starting bit position. Both are counted from the LSB. 7375 7376 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one. 7377 7378 IN_DEST is nonzero if this is a reference in the destination of a SET. 7379 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, 7380 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will 7381 be used. 7382 7383 IN_COMPARE is nonzero if we are in a COMPARE. This means that a 7384 ZERO_EXTRACT should be built even for bits starting at bit 0. 7385 7386 MODE is the desired mode of the result (if IN_DEST == 0). 7387 7388 The result is an RTX for the extraction or NULL_RTX if the target 7389 can't handle it. */ 7390 7391 static rtx 7392 make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos, 7393 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp, 7394 int in_dest, int in_compare) 7395 { 7396 /* This mode describes the size of the storage area 7397 to fetch the overall value from. Within that, we 7398 ignore the POS lowest bits, etc. */ 7399 machine_mode is_mode = GET_MODE (inner); 7400 machine_mode inner_mode; 7401 machine_mode wanted_inner_mode; 7402 machine_mode wanted_inner_reg_mode = word_mode; 7403 machine_mode pos_mode = word_mode; 7404 machine_mode extraction_mode = word_mode; 7405 machine_mode tmode = mode_for_size (len, MODE_INT, 1); 7406 rtx new_rtx = 0; 7407 rtx orig_pos_rtx = pos_rtx; 7408 HOST_WIDE_INT orig_pos; 7409 7410 if (pos_rtx && CONST_INT_P (pos_rtx)) 7411 pos = INTVAL (pos_rtx), pos_rtx = 0; 7412 7413 if (GET_CODE (inner) == SUBREG 7414 && subreg_lowpart_p (inner) 7415 && (paradoxical_subreg_p (inner) 7416 /* If trying or potentionally trying to extract 7417 bits outside of is_mode, don't look through 7418 non-paradoxical SUBREGs. See PR82192. */ 7419 || (pos_rtx == NULL_RTX 7420 && pos + len <= GET_MODE_PRECISION (is_mode)))) 7421 { 7422 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), 7423 consider just the QI as the memory to extract from. 7424 The subreg adds or removes high bits; its mode is 7425 irrelevant to the meaning of this extraction, 7426 since POS and LEN count from the lsb. */ 7427 if (MEM_P (SUBREG_REG (inner))) 7428 is_mode = GET_MODE (SUBREG_REG (inner)); 7429 inner = SUBREG_REG (inner); 7430 } 7431 else if (GET_CODE (inner) == ASHIFT 7432 && CONST_INT_P (XEXP (inner, 1)) 7433 && pos_rtx == 0 && pos == 0 7434 && len > UINTVAL (XEXP (inner, 1))) 7435 { 7436 /* We're extracting the least significant bits of an rtx 7437 (ashift X (const_int C)), where LEN > C. Extract the 7438 least significant (LEN - C) bits of X, giving an rtx 7439 whose mode is MODE, then shift it left C times. */ 7440 new_rtx = make_extraction (mode, XEXP (inner, 0), 7441 0, 0, len - INTVAL (XEXP (inner, 1)), 7442 unsignedp, in_dest, in_compare); 7443 if (new_rtx != 0) 7444 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1)); 7445 } 7446 else if (GET_CODE (inner) == TRUNCATE 7447 /* If trying or potentionally trying to extract 7448 bits outside of is_mode, don't look through 7449 TRUNCATE. See PR82192. */ 7450 && pos_rtx == NULL_RTX 7451 && pos + len <= GET_MODE_PRECISION (is_mode)) 7452 inner = XEXP (inner, 0); 7453 7454 inner_mode = GET_MODE (inner); 7455 7456 /* See if this can be done without an extraction. We never can if the 7457 width of the field is not the same as that of some integer mode. For 7458 registers, we can only avoid the extraction if the position is at the 7459 low-order bit and this is either not in the destination or we have the 7460 appropriate STRICT_LOW_PART operation available. 7461 7462 For MEM, we can avoid an extract if the field starts on an appropriate 7463 boundary and we can change the mode of the memory reference. */ 7464 7465 if (tmode != BLKmode 7466 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 7467 && !MEM_P (inner) 7468 && (pos == 0 || REG_P (inner)) 7469 && (inner_mode == tmode 7470 || !REG_P (inner) 7471 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode) 7472 || reg_truncated_to_mode (tmode, inner)) 7473 && (! in_dest 7474 || (REG_P (inner) 7475 && have_insn_for (STRICT_LOW_PART, tmode)))) 7476 || (MEM_P (inner) && pos_rtx == 0 7477 && (pos 7478 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) 7479 : BITS_PER_UNIT)) == 0 7480 /* We can't do this if we are widening INNER_MODE (it 7481 may not be aligned, for one thing). */ 7482 && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode) 7483 && (inner_mode == tmode 7484 || (! mode_dependent_address_p (XEXP (inner, 0), 7485 MEM_ADDR_SPACE (inner)) 7486 && ! MEM_VOLATILE_P (inner)))))) 7487 { 7488 /* If INNER is a MEM, make a new MEM that encompasses just the desired 7489 field. If the original and current mode are the same, we need not 7490 adjust the offset. Otherwise, we do if bytes big endian. 7491 7492 If INNER is not a MEM, get a piece consisting of just the field 7493 of interest (in this case POS % BITS_PER_WORD must be 0). */ 7494 7495 if (MEM_P (inner)) 7496 { 7497 HOST_WIDE_INT offset; 7498 7499 /* POS counts from lsb, but make OFFSET count in memory order. */ 7500 if (BYTES_BIG_ENDIAN) 7501 offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT; 7502 else 7503 offset = pos / BITS_PER_UNIT; 7504 7505 new_rtx = adjust_address_nv (inner, tmode, offset); 7506 } 7507 else if (REG_P (inner)) 7508 { 7509 if (tmode != inner_mode) 7510 { 7511 /* We can't call gen_lowpart in a DEST since we 7512 always want a SUBREG (see below) and it would sometimes 7513 return a new hard register. */ 7514 if (pos || in_dest) 7515 { 7516 HOST_WIDE_INT final_word = pos / BITS_PER_WORD; 7517 7518 if (WORDS_BIG_ENDIAN 7519 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) 7520 final_word = ((GET_MODE_SIZE (inner_mode) 7521 - GET_MODE_SIZE (tmode)) 7522 / UNITS_PER_WORD) - final_word; 7523 7524 final_word *= UNITS_PER_WORD; 7525 if (BYTES_BIG_ENDIAN && 7526 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) 7527 final_word += (GET_MODE_SIZE (inner_mode) 7528 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; 7529 7530 /* Avoid creating invalid subregs, for example when 7531 simplifying (x>>32)&255. */ 7532 if (!validate_subreg (tmode, inner_mode, inner, final_word)) 7533 return NULL_RTX; 7534 7535 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word); 7536 } 7537 else 7538 new_rtx = gen_lowpart (tmode, inner); 7539 } 7540 else 7541 new_rtx = inner; 7542 } 7543 else 7544 new_rtx = force_to_mode (inner, tmode, 7545 len >= HOST_BITS_PER_WIDE_INT 7546 ? HOST_WIDE_INT_M1U 7547 : (HOST_WIDE_INT_1U << len) - 1, 0); 7548 7549 /* If this extraction is going into the destination of a SET, 7550 make a STRICT_LOW_PART unless we made a MEM. */ 7551 7552 if (in_dest) 7553 return (MEM_P (new_rtx) ? new_rtx 7554 : (GET_CODE (new_rtx) != SUBREG 7555 ? gen_rtx_CLOBBER (tmode, const0_rtx) 7556 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx))); 7557 7558 if (mode == tmode) 7559 return new_rtx; 7560 7561 if (CONST_SCALAR_INT_P (new_rtx)) 7562 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 7563 mode, new_rtx, tmode); 7564 7565 /* If we know that no extraneous bits are set, and that the high 7566 bit is not set, convert the extraction to the cheaper of 7567 sign and zero extension, that are equivalent in these cases. */ 7568 if (flag_expensive_optimizations 7569 && (HWI_COMPUTABLE_MODE_P (tmode) 7570 && ((nonzero_bits (new_rtx, tmode) 7571 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1)) 7572 == 0))) 7573 { 7574 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx); 7575 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx); 7576 7577 /* Prefer ZERO_EXTENSION, since it gives more information to 7578 backends. */ 7579 if (set_src_cost (temp, mode, optimize_this_for_speed_p) 7580 <= set_src_cost (temp1, mode, optimize_this_for_speed_p)) 7581 return temp; 7582 return temp1; 7583 } 7584 7585 /* Otherwise, sign- or zero-extend unless we already are in the 7586 proper mode. */ 7587 7588 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 7589 mode, new_rtx)); 7590 } 7591 7592 /* Unless this is a COMPARE or we have a funny memory reference, 7593 don't do anything with zero-extending field extracts starting at 7594 the low-order bit since they are simple AND operations. */ 7595 if (pos_rtx == 0 && pos == 0 && ! in_dest 7596 && ! in_compare && unsignedp) 7597 return 0; 7598 7599 /* Unless INNER is not MEM, reject this if we would be spanning bytes or 7600 if the position is not a constant and the length is not 1. In all 7601 other cases, we would only be going outside our object in cases when 7602 an original shift would have been undefined. */ 7603 if (MEM_P (inner) 7604 && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode)) 7605 || (pos_rtx != 0 && len != 1))) 7606 return 0; 7607 7608 enum extraction_pattern pattern = (in_dest ? EP_insv 7609 : unsignedp ? EP_extzv : EP_extv); 7610 7611 /* If INNER is not from memory, we want it to have the mode of a register 7612 extraction pattern's structure operand, or word_mode if there is no 7613 such pattern. The same applies to extraction_mode and pos_mode 7614 and their respective operands. 7615 7616 For memory, assume that the desired extraction_mode and pos_mode 7617 are the same as for a register operation, since at present we don't 7618 have named patterns for aligned memory structures. */ 7619 struct extraction_insn insn; 7620 if (get_best_reg_extraction_insn (&insn, pattern, 7621 GET_MODE_BITSIZE (inner_mode), mode)) 7622 { 7623 wanted_inner_reg_mode = insn.struct_mode; 7624 pos_mode = insn.pos_mode; 7625 extraction_mode = insn.field_mode; 7626 } 7627 7628 /* Never narrow an object, since that might not be safe. */ 7629 7630 if (mode != VOIDmode 7631 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) 7632 extraction_mode = mode; 7633 7634 if (!MEM_P (inner)) 7635 wanted_inner_mode = wanted_inner_reg_mode; 7636 else 7637 { 7638 /* Be careful not to go beyond the extracted object and maintain the 7639 natural alignment of the memory. */ 7640 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT); 7641 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len 7642 > GET_MODE_BITSIZE (wanted_inner_mode)) 7643 { 7644 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode); 7645 gcc_assert (wanted_inner_mode != VOIDmode); 7646 } 7647 } 7648 7649 orig_pos = pos; 7650 7651 if (BITS_BIG_ENDIAN) 7652 { 7653 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to 7654 BITS_BIG_ENDIAN style. If position is constant, compute new 7655 position. Otherwise, build subtraction. 7656 Note that POS is relative to the mode of the original argument. 7657 If it's a MEM we need to recompute POS relative to that. 7658 However, if we're extracting from (or inserting into) a register, 7659 we want to recompute POS relative to wanted_inner_mode. */ 7660 int width = (MEM_P (inner) 7661 ? GET_MODE_BITSIZE (is_mode) 7662 : GET_MODE_BITSIZE (wanted_inner_mode)); 7663 7664 if (pos_rtx == 0) 7665 pos = width - len - pos; 7666 else 7667 pos_rtx 7668 = gen_rtx_MINUS (GET_MODE (pos_rtx), 7669 gen_int_mode (width - len, GET_MODE (pos_rtx)), 7670 pos_rtx); 7671 /* POS may be less than 0 now, but we check for that below. 7672 Note that it can only be less than 0 if !MEM_P (inner). */ 7673 } 7674 7675 /* If INNER has a wider mode, and this is a constant extraction, try to 7676 make it smaller and adjust the byte to point to the byte containing 7677 the value. */ 7678 if (wanted_inner_mode != VOIDmode 7679 && inner_mode != wanted_inner_mode 7680 && ! pos_rtx 7681 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) 7682 && MEM_P (inner) 7683 && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner)) 7684 && ! MEM_VOLATILE_P (inner)) 7685 { 7686 int offset = 0; 7687 7688 /* The computations below will be correct if the machine is big 7689 endian in both bits and bytes or little endian in bits and bytes. 7690 If it is mixed, we must adjust. */ 7691 7692 /* If bytes are big endian and we had a paradoxical SUBREG, we must 7693 adjust OFFSET to compensate. */ 7694 if (BYTES_BIG_ENDIAN 7695 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) 7696 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); 7697 7698 /* We can now move to the desired byte. */ 7699 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode)) 7700 * GET_MODE_SIZE (wanted_inner_mode); 7701 pos %= GET_MODE_BITSIZE (wanted_inner_mode); 7702 7703 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN 7704 && is_mode != wanted_inner_mode) 7705 offset = (GET_MODE_SIZE (is_mode) 7706 - GET_MODE_SIZE (wanted_inner_mode) - offset); 7707 7708 inner = adjust_address_nv (inner, wanted_inner_mode, offset); 7709 } 7710 7711 /* If INNER is not memory, get it into the proper mode. If we are changing 7712 its mode, POS must be a constant and smaller than the size of the new 7713 mode. */ 7714 else if (!MEM_P (inner)) 7715 { 7716 /* On the LHS, don't create paradoxical subregs implicitely truncating 7717 the register unless TRULY_NOOP_TRUNCATION. */ 7718 if (in_dest 7719 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner), 7720 wanted_inner_mode)) 7721 return NULL_RTX; 7722 7723 if (GET_MODE (inner) != wanted_inner_mode 7724 && (pos_rtx != 0 7725 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) 7726 return NULL_RTX; 7727 7728 if (orig_pos < 0) 7729 return NULL_RTX; 7730 7731 inner = force_to_mode (inner, wanted_inner_mode, 7732 pos_rtx 7733 || len + orig_pos >= HOST_BITS_PER_WIDE_INT 7734 ? HOST_WIDE_INT_M1U 7735 : (((HOST_WIDE_INT_1U << len) - 1) 7736 << orig_pos), 7737 0); 7738 } 7739 7740 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we 7741 have to zero extend. Otherwise, we can just use a SUBREG. */ 7742 if (pos_rtx != 0 7743 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) 7744 { 7745 rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx, 7746 GET_MODE (pos_rtx)); 7747 7748 /* If we know that no extraneous bits are set, and that the high 7749 bit is not set, convert extraction to cheaper one - either 7750 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these 7751 cases. */ 7752 if (flag_expensive_optimizations 7753 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx)) 7754 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) 7755 & ~(((unsigned HOST_WIDE_INT) 7756 GET_MODE_MASK (GET_MODE (pos_rtx))) 7757 >> 1)) 7758 == 0))) 7759 { 7760 rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx, 7761 GET_MODE (pos_rtx)); 7762 7763 /* Prefer ZERO_EXTENSION, since it gives more information to 7764 backends. */ 7765 if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p) 7766 < set_src_cost (temp, pos_mode, optimize_this_for_speed_p)) 7767 temp = temp1; 7768 } 7769 pos_rtx = temp; 7770 } 7771 7772 /* Make POS_RTX unless we already have it and it is correct. If we don't 7773 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must 7774 be a CONST_INT. */ 7775 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) 7776 pos_rtx = orig_pos_rtx; 7777 7778 else if (pos_rtx == 0) 7779 pos_rtx = GEN_INT (pos); 7780 7781 /* Make the required operation. See if we can use existing rtx. */ 7782 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, 7783 extraction_mode, inner, GEN_INT (len), pos_rtx); 7784 if (! in_dest) 7785 new_rtx = gen_lowpart (mode, new_rtx); 7786 7787 return new_rtx; 7788 } 7789 7790 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted 7791 with any other operations in X. Return X without that shift if so. */ 7792 7793 static rtx 7794 extract_left_shift (rtx x, int count) 7795 { 7796 enum rtx_code code = GET_CODE (x); 7797 machine_mode mode = GET_MODE (x); 7798 rtx tem; 7799 7800 switch (code) 7801 { 7802 case ASHIFT: 7803 /* This is the shift itself. If it is wide enough, we will return 7804 either the value being shifted if the shift count is equal to 7805 COUNT or a shift for the difference. */ 7806 if (CONST_INT_P (XEXP (x, 1)) 7807 && INTVAL (XEXP (x, 1)) >= count) 7808 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), 7809 INTVAL (XEXP (x, 1)) - count); 7810 break; 7811 7812 case NEG: case NOT: 7813 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) 7814 return simplify_gen_unary (code, mode, tem, mode); 7815 7816 break; 7817 7818 case PLUS: case IOR: case XOR: case AND: 7819 /* If we can safely shift this constant and we find the inner shift, 7820 make a new operation. */ 7821 if (CONST_INT_P (XEXP (x, 1)) 7822 && (UINTVAL (XEXP (x, 1)) 7823 & (((HOST_WIDE_INT_1U << count)) - 1)) == 0 7824 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) 7825 { 7826 HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count; 7827 return simplify_gen_binary (code, mode, tem, 7828 gen_int_mode (val, mode)); 7829 } 7830 break; 7831 7832 default: 7833 break; 7834 } 7835 7836 return 0; 7837 } 7838 7839 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current 7840 level of the expression and MODE is its mode. IN_CODE is as for 7841 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE 7842 that should be used when recursing on operands of *X_PTR. 7843 7844 There are two possible actions: 7845 7846 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE 7847 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value. 7848 7849 - Return a new rtx, which the caller returns directly. */ 7850 7851 static rtx 7852 make_compound_operation_int (machine_mode mode, rtx *x_ptr, 7853 enum rtx_code in_code, 7854 enum rtx_code *next_code_ptr) 7855 { 7856 rtx x = *x_ptr; 7857 enum rtx_code next_code = *next_code_ptr; 7858 enum rtx_code code = GET_CODE (x); 7859 int mode_width = GET_MODE_PRECISION (mode); 7860 rtx rhs, lhs; 7861 rtx new_rtx = 0; 7862 int i; 7863 rtx tem; 7864 bool equality_comparison = false; 7865 7866 if (in_code == EQ) 7867 { 7868 equality_comparison = true; 7869 in_code = COMPARE; 7870 } 7871 7872 /* Process depending on the code of this operation. If NEW is set 7873 nonzero, it will be returned. */ 7874 7875 switch (code) 7876 { 7877 case ASHIFT: 7878 /* Convert shifts by constants into multiplications if inside 7879 an address. */ 7880 if (in_code == MEM && CONST_INT_P (XEXP (x, 1)) 7881 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 7882 && INTVAL (XEXP (x, 1)) >= 0) 7883 { 7884 HOST_WIDE_INT count = INTVAL (XEXP (x, 1)); 7885 HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count; 7886 7887 new_rtx = make_compound_operation (XEXP (x, 0), next_code); 7888 if (GET_CODE (new_rtx) == NEG) 7889 { 7890 new_rtx = XEXP (new_rtx, 0); 7891 multval = -multval; 7892 } 7893 multval = trunc_int_for_mode (multval, mode); 7894 new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode)); 7895 } 7896 break; 7897 7898 case PLUS: 7899 lhs = XEXP (x, 0); 7900 rhs = XEXP (x, 1); 7901 lhs = make_compound_operation (lhs, next_code); 7902 rhs = make_compound_operation (rhs, next_code); 7903 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG) 7904 { 7905 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0), 7906 XEXP (lhs, 1)); 7907 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem); 7908 } 7909 else if (GET_CODE (lhs) == MULT 7910 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0)) 7911 { 7912 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0), 7913 simplify_gen_unary (NEG, mode, 7914 XEXP (lhs, 1), 7915 mode)); 7916 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem); 7917 } 7918 else 7919 { 7920 SUBST (XEXP (x, 0), lhs); 7921 SUBST (XEXP (x, 1), rhs); 7922 } 7923 maybe_swap_commutative_operands (x); 7924 return x; 7925 7926 case MINUS: 7927 lhs = XEXP (x, 0); 7928 rhs = XEXP (x, 1); 7929 lhs = make_compound_operation (lhs, next_code); 7930 rhs = make_compound_operation (rhs, next_code); 7931 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG) 7932 { 7933 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0), 7934 XEXP (rhs, 1)); 7935 return simplify_gen_binary (PLUS, mode, tem, lhs); 7936 } 7937 else if (GET_CODE (rhs) == MULT 7938 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0)) 7939 { 7940 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0), 7941 simplify_gen_unary (NEG, mode, 7942 XEXP (rhs, 1), 7943 mode)); 7944 return simplify_gen_binary (PLUS, mode, tem, lhs); 7945 } 7946 else 7947 { 7948 SUBST (XEXP (x, 0), lhs); 7949 SUBST (XEXP (x, 1), rhs); 7950 return x; 7951 } 7952 7953 case AND: 7954 /* If the second operand is not a constant, we can't do anything 7955 with it. */ 7956 if (!CONST_INT_P (XEXP (x, 1))) 7957 break; 7958 7959 /* If the constant is a power of two minus one and the first operand 7960 is a logical right shift, make an extraction. */ 7961 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 7962 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 7963 { 7964 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 7965 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1, 7966 0, in_code == COMPARE); 7967 } 7968 7969 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ 7970 else if (GET_CODE (XEXP (x, 0)) == SUBREG 7971 && subreg_lowpart_p (XEXP (x, 0)) 7972 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT 7973 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 7974 { 7975 rtx inner_x0 = SUBREG_REG (XEXP (x, 0)); 7976 machine_mode inner_mode = GET_MODE (inner_x0); 7977 new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code); 7978 new_rtx = make_extraction (inner_mode, new_rtx, 0, 7979 XEXP (inner_x0, 1), 7980 i, 1, 0, in_code == COMPARE); 7981 7982 if (new_rtx) 7983 { 7984 /* If we narrowed the mode when dropping the subreg, then 7985 we must zero-extend to keep the semantics of the AND. */ 7986 if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode)) 7987 ; 7988 else if (SCALAR_INT_MODE_P (inner_mode)) 7989 new_rtx = simplify_gen_unary (ZERO_EXTEND, mode, 7990 new_rtx, inner_mode); 7991 else 7992 new_rtx = NULL; 7993 } 7994 7995 /* If that didn't give anything, see if the AND simplifies on 7996 its own. */ 7997 if (!new_rtx && i >= 0) 7998 { 7999 new_rtx = make_compound_operation (XEXP (x, 0), next_code); 8000 new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i, 1, 8001 0, in_code == COMPARE); 8002 } 8003 } 8004 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ 8005 else if ((GET_CODE (XEXP (x, 0)) == XOR 8006 || GET_CODE (XEXP (x, 0)) == IOR) 8007 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT 8008 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT 8009 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 8010 { 8011 /* Apply the distributive law, and then try to make extractions. */ 8012 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, 8013 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), 8014 XEXP (x, 1)), 8015 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), 8016 XEXP (x, 1))); 8017 new_rtx = make_compound_operation (new_rtx, in_code); 8018 } 8019 8020 /* If we are have (and (rotate X C) M) and C is larger than the number 8021 of bits in M, this is an extraction. */ 8022 8023 else if (GET_CODE (XEXP (x, 0)) == ROTATE 8024 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 8025 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0 8026 && i <= INTVAL (XEXP (XEXP (x, 0), 1))) 8027 { 8028 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 8029 new_rtx = make_extraction (mode, new_rtx, 8030 (GET_MODE_PRECISION (mode) 8031 - INTVAL (XEXP (XEXP (x, 0), 1))), 8032 NULL_RTX, i, 1, 0, in_code == COMPARE); 8033 } 8034 8035 /* On machines without logical shifts, if the operand of the AND is 8036 a logical shift and our mask turns off all the propagated sign 8037 bits, we can replace the logical shift with an arithmetic shift. */ 8038 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 8039 && !have_insn_for (LSHIFTRT, mode) 8040 && have_insn_for (ASHIFTRT, mode) 8041 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 8042 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 8043 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 8044 && mode_width <= HOST_BITS_PER_WIDE_INT) 8045 { 8046 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 8047 8048 mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); 8049 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) 8050 SUBST (XEXP (x, 0), 8051 gen_rtx_ASHIFTRT (mode, 8052 make_compound_operation 8053 (XEXP (XEXP (x, 0), 0), next_code), 8054 XEXP (XEXP (x, 0), 1))); 8055 } 8056 8057 /* If the constant is one less than a power of two, this might be 8058 representable by an extraction even if no shift is present. 8059 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless 8060 we are in a COMPARE. */ 8061 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 8062 new_rtx = make_extraction (mode, 8063 make_compound_operation (XEXP (x, 0), 8064 next_code), 8065 0, NULL_RTX, i, 1, 0, in_code == COMPARE); 8066 8067 /* If we are in a comparison and this is an AND with a power of two, 8068 convert this into the appropriate bit extract. */ 8069 else if (in_code == COMPARE 8070 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0 8071 && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1)) 8072 new_rtx = make_extraction (mode, 8073 make_compound_operation (XEXP (x, 0), 8074 next_code), 8075 i, NULL_RTX, 1, 1, 0, 1); 8076 8077 /* If the one operand is a paradoxical subreg of a register or memory and 8078 the constant (limited to the smaller mode) has only zero bits where 8079 the sub expression has known zero bits, this can be expressed as 8080 a zero_extend. */ 8081 else if (GET_CODE (XEXP (x, 0)) == SUBREG) 8082 { 8083 rtx sub; 8084 8085 sub = XEXP (XEXP (x, 0), 0); 8086 machine_mode sub_mode = GET_MODE (sub); 8087 if ((REG_P (sub) || MEM_P (sub)) 8088 && GET_MODE_PRECISION (sub_mode) < mode_width) 8089 { 8090 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode); 8091 unsigned HOST_WIDE_INT mask; 8092 8093 /* original AND constant with all the known zero bits set */ 8094 mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode)); 8095 if ((mask & mode_mask) == mode_mask) 8096 { 8097 new_rtx = make_compound_operation (sub, next_code); 8098 new_rtx = make_extraction (mode, new_rtx, 0, 0, 8099 GET_MODE_PRECISION (sub_mode), 8100 1, 0, in_code == COMPARE); 8101 } 8102 } 8103 } 8104 8105 break; 8106 8107 case LSHIFTRT: 8108 /* If the sign bit is known to be zero, replace this with an 8109 arithmetic shift. */ 8110 if (have_insn_for (ASHIFTRT, mode) 8111 && ! have_insn_for (LSHIFTRT, mode) 8112 && mode_width <= HOST_BITS_PER_WIDE_INT 8113 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) 8114 { 8115 new_rtx = gen_rtx_ASHIFTRT (mode, 8116 make_compound_operation (XEXP (x, 0), 8117 next_code), 8118 XEXP (x, 1)); 8119 break; 8120 } 8121 8122 /* fall through */ 8123 8124 case ASHIFTRT: 8125 lhs = XEXP (x, 0); 8126 rhs = XEXP (x, 1); 8127 8128 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, 8129 this is a SIGN_EXTRACT. */ 8130 if (CONST_INT_P (rhs) 8131 && GET_CODE (lhs) == ASHIFT 8132 && CONST_INT_P (XEXP (lhs, 1)) 8133 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)) 8134 && INTVAL (XEXP (lhs, 1)) >= 0 8135 && INTVAL (rhs) < mode_width) 8136 { 8137 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code); 8138 new_rtx = make_extraction (mode, new_rtx, 8139 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), 8140 NULL_RTX, mode_width - INTVAL (rhs), 8141 code == LSHIFTRT, 0, in_code == COMPARE); 8142 break; 8143 } 8144 8145 /* See if we have operations between an ASHIFTRT and an ASHIFT. 8146 If so, try to merge the shifts into a SIGN_EXTEND. We could 8147 also do this for some cases of SIGN_EXTRACT, but it doesn't 8148 seem worth the effort; the case checked for occurs on Alpha. */ 8149 8150 if (!OBJECT_P (lhs) 8151 && ! (GET_CODE (lhs) == SUBREG 8152 && (OBJECT_P (SUBREG_REG (lhs)))) 8153 && CONST_INT_P (rhs) 8154 && INTVAL (rhs) >= 0 8155 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT 8156 && INTVAL (rhs) < mode_width 8157 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0) 8158 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code), 8159 0, NULL_RTX, mode_width - INTVAL (rhs), 8160 code == LSHIFTRT, 0, in_code == COMPARE); 8161 8162 break; 8163 8164 case SUBREG: 8165 /* Call ourselves recursively on the inner expression. If we are 8166 narrowing the object and it has a different RTL code from 8167 what it originally did, do this SUBREG as a force_to_mode. */ 8168 { 8169 rtx inner = SUBREG_REG (x), simplified; 8170 enum rtx_code subreg_code = in_code; 8171 8172 /* If the SUBREG is masking of a logical right shift, 8173 make an extraction. */ 8174 if (GET_CODE (inner) == LSHIFTRT 8175 && CONST_INT_P (XEXP (inner, 1)) 8176 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner)) 8177 && (UINTVAL (XEXP (inner, 1)) 8178 < GET_MODE_PRECISION (GET_MODE (inner))) 8179 && subreg_lowpart_p (x)) 8180 { 8181 new_rtx = make_compound_operation (XEXP (inner, 0), next_code); 8182 int width = GET_MODE_PRECISION (GET_MODE (inner)) 8183 - INTVAL (XEXP (inner, 1)); 8184 if (width > mode_width) 8185 width = mode_width; 8186 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (inner, 1), 8187 width, 1, 0, in_code == COMPARE); 8188 break; 8189 } 8190 8191 /* If in_code is COMPARE, it isn't always safe to pass it through 8192 to the recursive make_compound_operation call. */ 8193 if (subreg_code == COMPARE 8194 && (!subreg_lowpart_p (x) 8195 || GET_CODE (inner) == SUBREG 8196 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0) 8197 is (const_int 0), rather than 8198 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). 8199 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0) 8200 for non-equality comparisons against 0 is not equivalent 8201 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */ 8202 || (GET_CODE (inner) == AND 8203 && CONST_INT_P (XEXP (inner, 1)) 8204 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner)) 8205 && exact_log2 (UINTVAL (XEXP (inner, 1))) 8206 >= GET_MODE_BITSIZE (mode) - 1))) 8207 subreg_code = SET; 8208 8209 tem = make_compound_operation (inner, subreg_code); 8210 8211 simplified 8212 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x)); 8213 if (simplified) 8214 tem = simplified; 8215 8216 if (GET_CODE (tem) != GET_CODE (inner) 8217 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner)) 8218 && subreg_lowpart_p (x)) 8219 { 8220 rtx newer 8221 = force_to_mode (tem, mode, HOST_WIDE_INT_M1U, 0); 8222 8223 /* If we have something other than a SUBREG, we might have 8224 done an expansion, so rerun ourselves. */ 8225 if (GET_CODE (newer) != SUBREG) 8226 newer = make_compound_operation (newer, in_code); 8227 8228 /* force_to_mode can expand compounds. If it just re-expanded the 8229 compound, use gen_lowpart to convert to the desired mode. */ 8230 if (rtx_equal_p (newer, x) 8231 /* Likewise if it re-expanded the compound only partially. 8232 This happens for SUBREG of ZERO_EXTRACT if they extract 8233 the same number of bits. */ 8234 || (GET_CODE (newer) == SUBREG 8235 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT 8236 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT) 8237 && GET_CODE (inner) == AND 8238 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0)))) 8239 return gen_lowpart (GET_MODE (x), tem); 8240 8241 return newer; 8242 } 8243 8244 if (simplified) 8245 return tem; 8246 } 8247 break; 8248 8249 default: 8250 break; 8251 } 8252 8253 if (new_rtx) 8254 *x_ptr = gen_lowpart (mode, new_rtx); 8255 *next_code_ptr = next_code; 8256 return NULL_RTX; 8257 } 8258 8259 /* Look at the expression rooted at X. Look for expressions 8260 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. 8261 Form these expressions. 8262 8263 Return the new rtx, usually just X. 8264 8265 Also, for machines like the VAX that don't have logical shift insns, 8266 try to convert logical to arithmetic shift operations in cases where 8267 they are equivalent. This undoes the canonicalizations to logical 8268 shifts done elsewhere. 8269 8270 We try, as much as possible, to re-use rtl expressions to save memory. 8271 8272 IN_CODE says what kind of expression we are processing. Normally, it is 8273 SET. In a memory address it is MEM. When processing the arguments of 8274 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more 8275 precisely it is an equality comparison against zero. */ 8276 8277 rtx 8278 make_compound_operation (rtx x, enum rtx_code in_code) 8279 { 8280 enum rtx_code code = GET_CODE (x); 8281 const char *fmt; 8282 int i, j; 8283 enum rtx_code next_code; 8284 rtx new_rtx, tem; 8285 8286 /* Select the code to be used in recursive calls. Once we are inside an 8287 address, we stay there. If we have a comparison, set to COMPARE, 8288 but once inside, go back to our default of SET. */ 8289 8290 next_code = (code == MEM ? MEM 8291 : ((code == COMPARE || COMPARISON_P (x)) 8292 && XEXP (x, 1) == const0_rtx) ? COMPARE 8293 : in_code == COMPARE || in_code == EQ ? SET : in_code); 8294 8295 if (SCALAR_INT_MODE_P (GET_MODE (x))) 8296 { 8297 rtx new_rtx = make_compound_operation_int (GET_MODE (x), &x, 8298 in_code, &next_code); 8299 if (new_rtx) 8300 return new_rtx; 8301 code = GET_CODE (x); 8302 } 8303 8304 /* Now recursively process each operand of this operation. We need to 8305 handle ZERO_EXTEND specially so that we don't lose track of the 8306 inner mode. */ 8307 if (code == ZERO_EXTEND) 8308 { 8309 new_rtx = make_compound_operation (XEXP (x, 0), next_code); 8310 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x), 8311 new_rtx, GET_MODE (XEXP (x, 0))); 8312 if (tem) 8313 return tem; 8314 SUBST (XEXP (x, 0), new_rtx); 8315 return x; 8316 } 8317 8318 fmt = GET_RTX_FORMAT (code); 8319 for (i = 0; i < GET_RTX_LENGTH (code); i++) 8320 if (fmt[i] == 'e') 8321 { 8322 new_rtx = make_compound_operation (XEXP (x, i), next_code); 8323 SUBST (XEXP (x, i), new_rtx); 8324 } 8325 else if (fmt[i] == 'E') 8326 for (j = 0; j < XVECLEN (x, i); j++) 8327 { 8328 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code); 8329 SUBST (XVECEXP (x, i, j), new_rtx); 8330 } 8331 8332 maybe_swap_commutative_operands (x); 8333 return x; 8334 } 8335 8336 /* Given M see if it is a value that would select a field of bits 8337 within an item, but not the entire word. Return -1 if not. 8338 Otherwise, return the starting position of the field, where 0 is the 8339 low-order bit. 8340 8341 *PLEN is set to the length of the field. */ 8342 8343 static int 8344 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen) 8345 { 8346 /* Get the bit number of the first 1 bit from the right, -1 if none. */ 8347 int pos = m ? ctz_hwi (m) : -1; 8348 int len = 0; 8349 8350 if (pos >= 0) 8351 /* Now shift off the low-order zero bits and see if we have a 8352 power of two minus 1. */ 8353 len = exact_log2 ((m >> pos) + 1); 8354 8355 if (len <= 0) 8356 pos = -1; 8357 8358 *plen = len; 8359 return pos; 8360 } 8361 8362 /* If X refers to a register that equals REG in value, replace these 8363 references with REG. */ 8364 static rtx 8365 canon_reg_for_combine (rtx x, rtx reg) 8366 { 8367 rtx op0, op1, op2; 8368 const char *fmt; 8369 int i; 8370 bool copied; 8371 8372 enum rtx_code code = GET_CODE (x); 8373 switch (GET_RTX_CLASS (code)) 8374 { 8375 case RTX_UNARY: 8376 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8377 if (op0 != XEXP (x, 0)) 8378 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0, 8379 GET_MODE (reg)); 8380 break; 8381 8382 case RTX_BIN_ARITH: 8383 case RTX_COMM_ARITH: 8384 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8385 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 8386 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 8387 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); 8388 break; 8389 8390 case RTX_COMPARE: 8391 case RTX_COMM_COMPARE: 8392 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8393 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 8394 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 8395 return simplify_gen_relational (GET_CODE (x), GET_MODE (x), 8396 GET_MODE (op0), op0, op1); 8397 break; 8398 8399 case RTX_TERNARY: 8400 case RTX_BITFIELD_OPS: 8401 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8402 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 8403 op2 = canon_reg_for_combine (XEXP (x, 2), reg); 8404 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2)) 8405 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x), 8406 GET_MODE (op0), op0, op1, op2); 8407 /* FALLTHRU */ 8408 8409 case RTX_OBJ: 8410 if (REG_P (x)) 8411 { 8412 if (rtx_equal_p (get_last_value (reg), x) 8413 || rtx_equal_p (reg, get_last_value (x))) 8414 return reg; 8415 else 8416 break; 8417 } 8418 8419 /* fall through */ 8420 8421 default: 8422 fmt = GET_RTX_FORMAT (code); 8423 copied = false; 8424 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 8425 if (fmt[i] == 'e') 8426 { 8427 rtx op = canon_reg_for_combine (XEXP (x, i), reg); 8428 if (op != XEXP (x, i)) 8429 { 8430 if (!copied) 8431 { 8432 copied = true; 8433 x = copy_rtx (x); 8434 } 8435 XEXP (x, i) = op; 8436 } 8437 } 8438 else if (fmt[i] == 'E') 8439 { 8440 int j; 8441 for (j = 0; j < XVECLEN (x, i); j++) 8442 { 8443 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg); 8444 if (op != XVECEXP (x, i, j)) 8445 { 8446 if (!copied) 8447 { 8448 copied = true; 8449 x = copy_rtx (x); 8450 } 8451 XVECEXP (x, i, j) = op; 8452 } 8453 } 8454 } 8455 8456 break; 8457 } 8458 8459 return x; 8460 } 8461 8462 /* Return X converted to MODE. If the value is already truncated to 8463 MODE we can just return a subreg even though in the general case we 8464 would need an explicit truncation. */ 8465 8466 static rtx 8467 gen_lowpart_or_truncate (machine_mode mode, rtx x) 8468 { 8469 if (!CONST_INT_P (x) 8470 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)) 8471 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x)) 8472 && !(REG_P (x) && reg_truncated_to_mode (mode, x))) 8473 { 8474 /* Bit-cast X into an integer mode. */ 8475 if (!SCALAR_INT_MODE_P (GET_MODE (x))) 8476 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x); 8477 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode), 8478 x, GET_MODE (x)); 8479 } 8480 8481 return gen_lowpart (mode, x); 8482 } 8483 8484 /* See if X can be simplified knowing that we will only refer to it in 8485 MODE and will only refer to those bits that are nonzero in MASK. 8486 If other bits are being computed or if masking operations are done 8487 that select a superset of the bits in MASK, they can sometimes be 8488 ignored. 8489 8490 Return a possibly simplified expression, but always convert X to 8491 MODE. If X is a CONST_INT, AND the CONST_INT with MASK. 8492 8493 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK 8494 are all off in X. This is used when X will be complemented, by either 8495 NOT, NEG, or XOR. */ 8496 8497 static rtx 8498 force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask, 8499 int just_select) 8500 { 8501 enum rtx_code code = GET_CODE (x); 8502 int next_select = just_select || code == XOR || code == NOT || code == NEG; 8503 machine_mode op_mode; 8504 unsigned HOST_WIDE_INT fuller_mask, nonzero; 8505 rtx op0, op1, temp; 8506 8507 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the 8508 code below will do the wrong thing since the mode of such an 8509 expression is VOIDmode. 8510 8511 Also do nothing if X is a CLOBBER; this can happen if X was 8512 the return value from a call to gen_lowpart. */ 8513 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) 8514 return x; 8515 8516 /* We want to perform the operation in its present mode unless we know 8517 that the operation is valid in MODE, in which case we do the operation 8518 in MODE. */ 8519 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) 8520 && have_insn_for (code, mode)) 8521 ? mode : GET_MODE (x)); 8522 8523 /* It is not valid to do a right-shift in a narrower mode 8524 than the one it came in with. */ 8525 if ((code == LSHIFTRT || code == ASHIFTRT) 8526 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x))) 8527 op_mode = GET_MODE (x); 8528 8529 /* Truncate MASK to fit OP_MODE. */ 8530 if (op_mode) 8531 mask &= GET_MODE_MASK (op_mode); 8532 8533 /* When we have an arithmetic operation, or a shift whose count we 8534 do not know, we need to assume that all bits up to the highest-order 8535 bit in MASK will be needed. This is how we form such a mask. */ 8536 if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1))) 8537 fuller_mask = HOST_WIDE_INT_M1U; 8538 else 8539 fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (mask) + 1)) 8540 - 1); 8541 8542 /* Determine what bits of X are guaranteed to be (non)zero. */ 8543 nonzero = nonzero_bits (x, mode); 8544 8545 /* If none of the bits in X are needed, return a zero. */ 8546 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x)) 8547 x = const0_rtx; 8548 8549 /* If X is a CONST_INT, return a new one. Do this here since the 8550 test below will fail. */ 8551 if (CONST_INT_P (x)) 8552 { 8553 if (SCALAR_INT_MODE_P (mode)) 8554 return gen_int_mode (INTVAL (x) & mask, mode); 8555 else 8556 { 8557 x = GEN_INT (INTVAL (x) & mask); 8558 return gen_lowpart_common (mode, x); 8559 } 8560 } 8561 8562 /* If X is narrower than MODE and we want all the bits in X's mode, just 8563 get X in the proper mode. */ 8564 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) 8565 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) 8566 return gen_lowpart (mode, x); 8567 8568 /* We can ignore the effect of a SUBREG if it narrows the mode or 8569 if the constant masks to zero all the bits the mode doesn't have. */ 8570 if (GET_CODE (x) == SUBREG 8571 && subreg_lowpart_p (x) 8572 && ((GET_MODE_SIZE (GET_MODE (x)) 8573 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 8574 || (0 == (mask 8575 & GET_MODE_MASK (GET_MODE (x)) 8576 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) 8577 return force_to_mode (SUBREG_REG (x), mode, mask, next_select); 8578 8579 /* The arithmetic simplifications here only work for scalar integer modes. */ 8580 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x))) 8581 return gen_lowpart_or_truncate (mode, x); 8582 8583 switch (code) 8584 { 8585 case CLOBBER: 8586 /* If X is a (clobber (const_int)), return it since we know we are 8587 generating something that won't match. */ 8588 return x; 8589 8590 case SIGN_EXTEND: 8591 case ZERO_EXTEND: 8592 case ZERO_EXTRACT: 8593 case SIGN_EXTRACT: 8594 x = expand_compound_operation (x); 8595 if (GET_CODE (x) != code) 8596 return force_to_mode (x, mode, mask, next_select); 8597 break; 8598 8599 case TRUNCATE: 8600 /* Similarly for a truncate. */ 8601 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 8602 8603 case AND: 8604 /* If this is an AND with a constant, convert it into an AND 8605 whose constant is the AND of that constant with MASK. If it 8606 remains an AND of MASK, delete it since it is redundant. */ 8607 8608 if (CONST_INT_P (XEXP (x, 1))) 8609 { 8610 x = simplify_and_const_int (x, op_mode, XEXP (x, 0), 8611 mask & INTVAL (XEXP (x, 1))); 8612 8613 /* If X is still an AND, see if it is an AND with a mask that 8614 is just some low-order bits. If so, and it is MASK, we don't 8615 need it. */ 8616 8617 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1)) 8618 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) 8619 == mask)) 8620 x = XEXP (x, 0); 8621 8622 /* If it remains an AND, try making another AND with the bits 8623 in the mode mask that aren't in MASK turned on. If the 8624 constant in the AND is wide enough, this might make a 8625 cheaper constant. */ 8626 8627 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1)) 8628 && GET_MODE_MASK (GET_MODE (x)) != mask 8629 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))) 8630 { 8631 unsigned HOST_WIDE_INT cval 8632 = UINTVAL (XEXP (x, 1)) 8633 | (GET_MODE_MASK (GET_MODE (x)) & ~mask); 8634 rtx y; 8635 8636 y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0), 8637 gen_int_mode (cval, GET_MODE (x))); 8638 if (set_src_cost (y, GET_MODE (x), optimize_this_for_speed_p) 8639 < set_src_cost (x, GET_MODE (x), optimize_this_for_speed_p)) 8640 x = y; 8641 } 8642 8643 break; 8644 } 8645 8646 goto binop; 8647 8648 case PLUS: 8649 /* In (and (plus FOO C1) M), if M is a mask that just turns off 8650 low-order bits (as in an alignment operation) and FOO is already 8651 aligned to that boundary, mask C1 to that boundary as well. 8652 This may eliminate that PLUS and, later, the AND. */ 8653 8654 { 8655 unsigned int width = GET_MODE_PRECISION (mode); 8656 unsigned HOST_WIDE_INT smask = mask; 8657 8658 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative 8659 number, sign extend it. */ 8660 8661 if (width < HOST_BITS_PER_WIDE_INT 8662 && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0) 8663 smask |= HOST_WIDE_INT_M1U << width; 8664 8665 if (CONST_INT_P (XEXP (x, 1)) 8666 && pow2p_hwi (- smask) 8667 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 8668 && (INTVAL (XEXP (x, 1)) & ~smask) != 0) 8669 return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0), 8670 (INTVAL (XEXP (x, 1)) & smask)), 8671 mode, smask, next_select); 8672 } 8673 8674 /* fall through */ 8675 8676 case MULT: 8677 /* Substituting into the operands of a widening MULT is not likely to 8678 create RTL matching a machine insn. */ 8679 if (code == MULT 8680 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 8681 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) 8682 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND 8683 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND) 8684 && REG_P (XEXP (XEXP (x, 0), 0)) 8685 && REG_P (XEXP (XEXP (x, 1), 0))) 8686 return gen_lowpart_or_truncate (mode, x); 8687 8688 /* For PLUS, MINUS and MULT, we need any bits less significant than the 8689 most significant bit in MASK since carries from those bits will 8690 affect the bits we are interested in. */ 8691 mask = fuller_mask; 8692 goto binop; 8693 8694 case MINUS: 8695 /* If X is (minus C Y) where C's least set bit is larger than any bit 8696 in the mask, then we may replace with (neg Y). */ 8697 if (CONST_INT_P (XEXP (x, 0)) 8698 && least_bit_hwi (UINTVAL (XEXP (x, 0))) > mask) 8699 { 8700 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), 8701 GET_MODE (x)); 8702 return force_to_mode (x, mode, mask, next_select); 8703 } 8704 8705 /* Similarly, if C contains every bit in the fuller_mask, then we may 8706 replace with (not Y). */ 8707 if (CONST_INT_P (XEXP (x, 0)) 8708 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0)))) 8709 { 8710 x = simplify_gen_unary (NOT, GET_MODE (x), 8711 XEXP (x, 1), GET_MODE (x)); 8712 return force_to_mode (x, mode, mask, next_select); 8713 } 8714 8715 mask = fuller_mask; 8716 goto binop; 8717 8718 case IOR: 8719 case XOR: 8720 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and 8721 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) 8722 operation which may be a bitfield extraction. Ensure that the 8723 constant we form is not wider than the mode of X. */ 8724 8725 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 8726 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 8727 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 8728 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 8729 && CONST_INT_P (XEXP (x, 1)) 8730 && ((INTVAL (XEXP (XEXP (x, 0), 1)) 8731 + floor_log2 (INTVAL (XEXP (x, 1)))) 8732 < GET_MODE_PRECISION (GET_MODE (x))) 8733 && (UINTVAL (XEXP (x, 1)) 8734 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) 8735 { 8736 temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask) 8737 << INTVAL (XEXP (XEXP (x, 0), 1)), 8738 GET_MODE (x)); 8739 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x), 8740 XEXP (XEXP (x, 0), 0), temp); 8741 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp, 8742 XEXP (XEXP (x, 0), 1)); 8743 return force_to_mode (x, mode, mask, next_select); 8744 } 8745 8746 binop: 8747 /* For most binary operations, just propagate into the operation and 8748 change the mode if we have an operation of that mode. */ 8749 8750 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select); 8751 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select); 8752 8753 /* If we ended up truncating both operands, truncate the result of the 8754 operation instead. */ 8755 if (GET_CODE (op0) == TRUNCATE 8756 && GET_CODE (op1) == TRUNCATE) 8757 { 8758 op0 = XEXP (op0, 0); 8759 op1 = XEXP (op1, 0); 8760 } 8761 8762 op0 = gen_lowpart_or_truncate (op_mode, op0); 8763 op1 = gen_lowpart_or_truncate (op_mode, op1); 8764 8765 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 8766 x = simplify_gen_binary (code, op_mode, op0, op1); 8767 break; 8768 8769 case ASHIFT: 8770 /* For left shifts, do the same, but just for the first operand. 8771 However, we cannot do anything with shifts where we cannot 8772 guarantee that the counts are smaller than the size of the mode 8773 because such a count will have a different meaning in a 8774 wider mode. */ 8775 8776 if (! (CONST_INT_P (XEXP (x, 1)) 8777 && INTVAL (XEXP (x, 1)) >= 0 8778 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode)) 8779 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode 8780 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) 8781 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode)))) 8782 break; 8783 8784 /* If the shift count is a constant and we can do arithmetic in 8785 the mode of the shift, refine which bits we need. Otherwise, use the 8786 conservative form of the mask. */ 8787 if (CONST_INT_P (XEXP (x, 1)) 8788 && INTVAL (XEXP (x, 1)) >= 0 8789 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode) 8790 && HWI_COMPUTABLE_MODE_P (op_mode)) 8791 mask >>= INTVAL (XEXP (x, 1)); 8792 else 8793 mask = fuller_mask; 8794 8795 op0 = gen_lowpart_or_truncate (op_mode, 8796 force_to_mode (XEXP (x, 0), mode, 8797 mask, next_select)); 8798 8799 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 8800 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1)); 8801 break; 8802 8803 case LSHIFTRT: 8804 /* Here we can only do something if the shift count is a constant, 8805 this shift constant is valid for the host, and we can do arithmetic 8806 in OP_MODE. */ 8807 8808 if (CONST_INT_P (XEXP (x, 1)) 8809 && INTVAL (XEXP (x, 1)) >= 0 8810 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 8811 && HWI_COMPUTABLE_MODE_P (op_mode)) 8812 { 8813 rtx inner = XEXP (x, 0); 8814 unsigned HOST_WIDE_INT inner_mask; 8815 8816 /* Select the mask of the bits we need for the shift operand. */ 8817 inner_mask = mask << INTVAL (XEXP (x, 1)); 8818 8819 /* We can only change the mode of the shift if we can do arithmetic 8820 in the mode of the shift and INNER_MASK is no wider than the 8821 width of X's mode. */ 8822 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0) 8823 op_mode = GET_MODE (x); 8824 8825 inner = force_to_mode (inner, op_mode, inner_mask, next_select); 8826 8827 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) 8828 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); 8829 } 8830 8831 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the 8832 shift and AND produces only copies of the sign bit (C2 is one less 8833 than a power of two), we can do this with just a shift. */ 8834 8835 if (GET_CODE (x) == LSHIFTRT 8836 && CONST_INT_P (XEXP (x, 1)) 8837 /* The shift puts one of the sign bit copies in the least significant 8838 bit. */ 8839 && ((INTVAL (XEXP (x, 1)) 8840 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) 8841 >= GET_MODE_PRECISION (GET_MODE (x))) 8842 && pow2p_hwi (mask + 1) 8843 /* Number of bits left after the shift must be more than the mask 8844 needs. */ 8845 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) 8846 <= GET_MODE_PRECISION (GET_MODE (x))) 8847 /* Must be more sign bit copies than the mask needs. */ 8848 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 8849 >= exact_log2 (mask + 1))) 8850 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), 8851 GEN_INT (GET_MODE_PRECISION (GET_MODE (x)) 8852 - exact_log2 (mask + 1))); 8853 8854 goto shiftrt; 8855 8856 case ASHIFTRT: 8857 /* If we are just looking for the sign bit, we don't need this shift at 8858 all, even if it has a variable count. */ 8859 if (val_signbit_p (GET_MODE (x), mask)) 8860 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 8861 8862 /* If this is a shift by a constant, get a mask that contains those bits 8863 that are not copies of the sign bit. We then have two cases: If 8864 MASK only includes those bits, this can be a logical shift, which may 8865 allow simplifications. If MASK is a single-bit field not within 8866 those bits, we are requesting a copy of the sign bit and hence can 8867 shift the sign bit to the appropriate location. */ 8868 8869 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0 8870 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 8871 { 8872 int i; 8873 8874 /* If the considered data is wider than HOST_WIDE_INT, we can't 8875 represent a mask for all its bits in a single scalar. 8876 But we only care about the lower bits, so calculate these. */ 8877 8878 if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) 8879 { 8880 nonzero = HOST_WIDE_INT_M1U; 8881 8882 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 8883 is the number of bits a full-width mask would have set. 8884 We need only shift if these are fewer than nonzero can 8885 hold. If not, we must keep all bits set in nonzero. */ 8886 8887 if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 8888 < HOST_BITS_PER_WIDE_INT) 8889 nonzero >>= INTVAL (XEXP (x, 1)) 8890 + HOST_BITS_PER_WIDE_INT 8891 - GET_MODE_PRECISION (GET_MODE (x)) ; 8892 } 8893 else 8894 { 8895 nonzero = GET_MODE_MASK (GET_MODE (x)); 8896 nonzero >>= INTVAL (XEXP (x, 1)); 8897 } 8898 8899 if ((mask & ~nonzero) == 0) 8900 { 8901 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x), 8902 XEXP (x, 0), INTVAL (XEXP (x, 1))); 8903 if (GET_CODE (x) != ASHIFTRT) 8904 return force_to_mode (x, mode, mask, next_select); 8905 } 8906 8907 else if ((i = exact_log2 (mask)) >= 0) 8908 { 8909 x = simplify_shift_const 8910 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0), 8911 GET_MODE_PRECISION (GET_MODE (x)) - 1 - i); 8912 8913 if (GET_CODE (x) != ASHIFTRT) 8914 return force_to_mode (x, mode, mask, next_select); 8915 } 8916 } 8917 8918 /* If MASK is 1, convert this to an LSHIFTRT. This can be done 8919 even if the shift count isn't a constant. */ 8920 if (mask == 1) 8921 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), 8922 XEXP (x, 0), XEXP (x, 1)); 8923 8924 shiftrt: 8925 8926 /* If this is a zero- or sign-extension operation that just affects bits 8927 we don't care about, remove it. Be sure the call above returned 8928 something that is still a shift. */ 8929 8930 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) 8931 && CONST_INT_P (XEXP (x, 1)) 8932 && INTVAL (XEXP (x, 1)) >= 0 8933 && (INTVAL (XEXP (x, 1)) 8934 <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1)) 8935 && GET_CODE (XEXP (x, 0)) == ASHIFT 8936 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1)) 8937 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, 8938 next_select); 8939 8940 break; 8941 8942 case ROTATE: 8943 case ROTATERT: 8944 /* If the shift count is constant and we can do computations 8945 in the mode of X, compute where the bits we care about are. 8946 Otherwise, we can't do anything. Don't change the mode of 8947 the shift or propagate MODE into the shift, though. */ 8948 if (CONST_INT_P (XEXP (x, 1)) 8949 && INTVAL (XEXP (x, 1)) >= 0) 8950 { 8951 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, 8952 GET_MODE (x), 8953 gen_int_mode (mask, GET_MODE (x)), 8954 XEXP (x, 1)); 8955 if (temp && CONST_INT_P (temp)) 8956 x = simplify_gen_binary (code, GET_MODE (x), 8957 force_to_mode (XEXP (x, 0), GET_MODE (x), 8958 INTVAL (temp), next_select), 8959 XEXP (x, 1)); 8960 } 8961 break; 8962 8963 case NEG: 8964 /* If we just want the low-order bit, the NEG isn't needed since it 8965 won't change the low-order bit. */ 8966 if (mask == 1) 8967 return force_to_mode (XEXP (x, 0), mode, mask, just_select); 8968 8969 /* We need any bits less significant than the most significant bit in 8970 MASK since carries from those bits will affect the bits we are 8971 interested in. */ 8972 mask = fuller_mask; 8973 goto unop; 8974 8975 case NOT: 8976 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the 8977 same as the XOR case above. Ensure that the constant we form is not 8978 wider than the mode of X. */ 8979 8980 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 8981 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 8982 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 8983 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) 8984 < GET_MODE_PRECISION (GET_MODE (x))) 8985 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) 8986 { 8987 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), 8988 GET_MODE (x)); 8989 temp = simplify_gen_binary (XOR, GET_MODE (x), 8990 XEXP (XEXP (x, 0), 0), temp); 8991 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), 8992 temp, XEXP (XEXP (x, 0), 1)); 8993 8994 return force_to_mode (x, mode, mask, next_select); 8995 } 8996 8997 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must 8998 use the full mask inside the NOT. */ 8999 mask = fuller_mask; 9000 9001 unop: 9002 op0 = gen_lowpart_or_truncate (op_mode, 9003 force_to_mode (XEXP (x, 0), mode, mask, 9004 next_select)); 9005 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 9006 x = simplify_gen_unary (code, op_mode, op0, op_mode); 9007 break; 9008 9009 case NE: 9010 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included 9011 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, 9012 which is equal to STORE_FLAG_VALUE. */ 9013 if ((mask & ~STORE_FLAG_VALUE) == 0 9014 && XEXP (x, 1) == const0_rtx 9015 && GET_MODE (XEXP (x, 0)) == mode 9016 && pow2p_hwi (nonzero_bits (XEXP (x, 0), mode)) 9017 && (nonzero_bits (XEXP (x, 0), mode) 9018 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE)) 9019 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 9020 9021 break; 9022 9023 case IF_THEN_ELSE: 9024 /* We have no way of knowing if the IF_THEN_ELSE can itself be 9025 written in a narrower mode. We play it safe and do not do so. */ 9026 9027 op0 = gen_lowpart_or_truncate (GET_MODE (x), 9028 force_to_mode (XEXP (x, 1), mode, 9029 mask, next_select)); 9030 op1 = gen_lowpart_or_truncate (GET_MODE (x), 9031 force_to_mode (XEXP (x, 2), mode, 9032 mask, next_select)); 9033 if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2)) 9034 x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x), 9035 GET_MODE (XEXP (x, 0)), XEXP (x, 0), 9036 op0, op1); 9037 break; 9038 9039 default: 9040 break; 9041 } 9042 9043 /* Ensure we return a value of the proper mode. */ 9044 return gen_lowpart_or_truncate (mode, x); 9045 } 9046 9047 /* Return nonzero if X is an expression that has one of two values depending on 9048 whether some other value is zero or nonzero. In that case, we return the 9049 value that is being tested, *PTRUE is set to the value if the rtx being 9050 returned has a nonzero value, and *PFALSE is set to the other alternative. 9051 9052 If we return zero, we set *PTRUE and *PFALSE to X. */ 9053 9054 static rtx 9055 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse) 9056 { 9057 machine_mode mode = GET_MODE (x); 9058 enum rtx_code code = GET_CODE (x); 9059 rtx cond0, cond1, true0, true1, false0, false1; 9060 unsigned HOST_WIDE_INT nz; 9061 9062 /* If we are comparing a value against zero, we are done. */ 9063 if ((code == NE || code == EQ) 9064 && XEXP (x, 1) == const0_rtx) 9065 { 9066 *ptrue = (code == NE) ? const_true_rtx : const0_rtx; 9067 *pfalse = (code == NE) ? const0_rtx : const_true_rtx; 9068 return XEXP (x, 0); 9069 } 9070 9071 /* If this is a unary operation whose operand has one of two values, apply 9072 our opcode to compute those values. */ 9073 else if (UNARY_P (x) 9074 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) 9075 { 9076 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); 9077 *pfalse = simplify_gen_unary (code, mode, false0, 9078 GET_MODE (XEXP (x, 0))); 9079 return cond0; 9080 } 9081 9082 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would 9083 make can't possibly match and would suppress other optimizations. */ 9084 else if (code == COMPARE) 9085 ; 9086 9087 /* If this is a binary operation, see if either side has only one of two 9088 values. If either one does or if both do and they are conditional on 9089 the same value, compute the new true and false values. */ 9090 else if (BINARY_P (x)) 9091 { 9092 rtx op0 = XEXP (x, 0); 9093 rtx op1 = XEXP (x, 1); 9094 cond0 = if_then_else_cond (op0, &true0, &false0); 9095 cond1 = if_then_else_cond (op1, &true1, &false1); 9096 9097 if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)) 9098 && (REG_P (op0) || REG_P (op1))) 9099 { 9100 /* Try to enable a simplification by undoing work done by 9101 if_then_else_cond if it converted a REG into something more 9102 complex. */ 9103 if (REG_P (op0)) 9104 { 9105 cond0 = 0; 9106 true0 = false0 = op0; 9107 } 9108 else 9109 { 9110 cond1 = 0; 9111 true1 = false1 = op1; 9112 } 9113 } 9114 9115 if ((cond0 != 0 || cond1 != 0) 9116 && ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))) 9117 { 9118 /* If if_then_else_cond returned zero, then true/false are the 9119 same rtl. We must copy one of them to prevent invalid rtl 9120 sharing. */ 9121 if (cond0 == 0) 9122 true0 = copy_rtx (true0); 9123 else if (cond1 == 0) 9124 true1 = copy_rtx (true1); 9125 9126 if (COMPARISON_P (x)) 9127 { 9128 *ptrue = simplify_gen_relational (code, mode, VOIDmode, 9129 true0, true1); 9130 *pfalse = simplify_gen_relational (code, mode, VOIDmode, 9131 false0, false1); 9132 } 9133 else 9134 { 9135 *ptrue = simplify_gen_binary (code, mode, true0, true1); 9136 *pfalse = simplify_gen_binary (code, mode, false0, false1); 9137 } 9138 9139 return cond0 ? cond0 : cond1; 9140 } 9141 9142 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the 9143 operands is zero when the other is nonzero, and vice-versa, 9144 and STORE_FLAG_VALUE is 1 or -1. */ 9145 9146 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 9147 && (code == PLUS || code == IOR || code == XOR || code == MINUS 9148 || code == UMAX) 9149 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 9150 { 9151 rtx op0 = XEXP (XEXP (x, 0), 1); 9152 rtx op1 = XEXP (XEXP (x, 1), 1); 9153 9154 cond0 = XEXP (XEXP (x, 0), 0); 9155 cond1 = XEXP (XEXP (x, 1), 0); 9156 9157 if (COMPARISON_P (cond0) 9158 && COMPARISON_P (cond1) 9159 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) 9160 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 9161 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 9162 || ((swap_condition (GET_CODE (cond0)) 9163 == reversed_comparison_code (cond1, NULL)) 9164 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 9165 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 9166 && ! side_effects_p (x)) 9167 { 9168 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx); 9169 *pfalse = simplify_gen_binary (MULT, mode, 9170 (code == MINUS 9171 ? simplify_gen_unary (NEG, mode, 9172 op1, mode) 9173 : op1), 9174 const_true_rtx); 9175 return cond0; 9176 } 9177 } 9178 9179 /* Similarly for MULT, AND and UMIN, except that for these the result 9180 is always zero. */ 9181 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 9182 && (code == MULT || code == AND || code == UMIN) 9183 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 9184 { 9185 cond0 = XEXP (XEXP (x, 0), 0); 9186 cond1 = XEXP (XEXP (x, 1), 0); 9187 9188 if (COMPARISON_P (cond0) 9189 && COMPARISON_P (cond1) 9190 && SCALAR_INT_MODE_P (mode) 9191 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) 9192 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 9193 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 9194 || ((swap_condition (GET_CODE (cond0)) 9195 == reversed_comparison_code (cond1, NULL)) 9196 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 9197 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 9198 && ! side_effects_p (x)) 9199 { 9200 *ptrue = *pfalse = const0_rtx; 9201 return cond0; 9202 } 9203 } 9204 } 9205 9206 else if (code == IF_THEN_ELSE) 9207 { 9208 /* If we have IF_THEN_ELSE already, extract the condition and 9209 canonicalize it if it is NE or EQ. */ 9210 cond0 = XEXP (x, 0); 9211 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); 9212 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) 9213 return XEXP (cond0, 0); 9214 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) 9215 { 9216 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); 9217 return XEXP (cond0, 0); 9218 } 9219 else 9220 return cond0; 9221 } 9222 9223 /* If X is a SUBREG, we can narrow both the true and false values 9224 if the inner expression, if there is a condition. */ 9225 else if (code == SUBREG 9226 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), 9227 &true0, &false0))) 9228 { 9229 true0 = simplify_gen_subreg (mode, true0, 9230 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 9231 false0 = simplify_gen_subreg (mode, false0, 9232 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 9233 if (true0 && false0) 9234 { 9235 *ptrue = true0; 9236 *pfalse = false0; 9237 return cond0; 9238 } 9239 } 9240 9241 /* If X is a constant, this isn't special and will cause confusions 9242 if we treat it as such. Likewise if it is equivalent to a constant. */ 9243 else if (CONSTANT_P (x) 9244 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) 9245 ; 9246 9247 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that 9248 will be least confusing to the rest of the compiler. */ 9249 else if (mode == BImode) 9250 { 9251 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; 9252 return x; 9253 } 9254 9255 /* If X is known to be either 0 or -1, those are the true and 9256 false values when testing X. */ 9257 else if (x == constm1_rtx || x == const0_rtx 9258 || (mode != VOIDmode && mode != BLKmode 9259 && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode))) 9260 { 9261 *ptrue = constm1_rtx, *pfalse = const0_rtx; 9262 return x; 9263 } 9264 9265 /* Likewise for 0 or a single bit. */ 9266 else if (HWI_COMPUTABLE_MODE_P (mode) 9267 && pow2p_hwi (nz = nonzero_bits (x, mode))) 9268 { 9269 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx; 9270 return x; 9271 } 9272 9273 /* Otherwise fail; show no condition with true and false values the same. */ 9274 *ptrue = *pfalse = x; 9275 return 0; 9276 } 9277 9278 /* Return the value of expression X given the fact that condition COND 9279 is known to be true when applied to REG as its first operand and VAL 9280 as its second. X is known to not be shared and so can be modified in 9281 place. 9282 9283 We only handle the simplest cases, and specifically those cases that 9284 arise with IF_THEN_ELSE expressions. */ 9285 9286 static rtx 9287 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val) 9288 { 9289 enum rtx_code code = GET_CODE (x); 9290 const char *fmt; 9291 int i, j; 9292 9293 if (side_effects_p (x)) 9294 return x; 9295 9296 /* If either operand of the condition is a floating point value, 9297 then we have to avoid collapsing an EQ comparison. */ 9298 if (cond == EQ 9299 && rtx_equal_p (x, reg) 9300 && ! FLOAT_MODE_P (GET_MODE (x)) 9301 && ! FLOAT_MODE_P (GET_MODE (val))) 9302 return val; 9303 9304 if (cond == UNEQ && rtx_equal_p (x, reg)) 9305 return val; 9306 9307 /* If X is (abs REG) and we know something about REG's relationship 9308 with zero, we may be able to simplify this. */ 9309 9310 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) 9311 switch (cond) 9312 { 9313 case GE: case GT: case EQ: 9314 return XEXP (x, 0); 9315 case LT: case LE: 9316 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), 9317 XEXP (x, 0), 9318 GET_MODE (XEXP (x, 0))); 9319 default: 9320 break; 9321 } 9322 9323 /* The only other cases we handle are MIN, MAX, and comparisons if the 9324 operands are the same as REG and VAL. */ 9325 9326 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x)) 9327 { 9328 if (rtx_equal_p (XEXP (x, 0), val)) 9329 { 9330 std::swap (val, reg); 9331 cond = swap_condition (cond); 9332 } 9333 9334 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) 9335 { 9336 if (COMPARISON_P (x)) 9337 { 9338 if (comparison_dominates_p (cond, code)) 9339 return VECTOR_MODE_P (GET_MODE (x)) ? x : const_true_rtx; 9340 9341 code = reversed_comparison_code (x, NULL); 9342 if (code != UNKNOWN 9343 && comparison_dominates_p (cond, code)) 9344 return CONST0_RTX (GET_MODE (x)); 9345 else 9346 return x; 9347 } 9348 else if (code == SMAX || code == SMIN 9349 || code == UMIN || code == UMAX) 9350 { 9351 int unsignedp = (code == UMIN || code == UMAX); 9352 9353 /* Do not reverse the condition when it is NE or EQ. 9354 This is because we cannot conclude anything about 9355 the value of 'SMAX (x, y)' when x is not equal to y, 9356 but we can when x equals y. */ 9357 if ((code == SMAX || code == UMAX) 9358 && ! (cond == EQ || cond == NE)) 9359 cond = reverse_condition (cond); 9360 9361 switch (cond) 9362 { 9363 case GE: case GT: 9364 return unsignedp ? x : XEXP (x, 1); 9365 case LE: case LT: 9366 return unsignedp ? x : XEXP (x, 0); 9367 case GEU: case GTU: 9368 return unsignedp ? XEXP (x, 1) : x; 9369 case LEU: case LTU: 9370 return unsignedp ? XEXP (x, 0) : x; 9371 default: 9372 break; 9373 } 9374 } 9375 } 9376 } 9377 else if (code == SUBREG) 9378 { 9379 machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); 9380 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val); 9381 9382 if (SUBREG_REG (x) != r) 9383 { 9384 /* We must simplify subreg here, before we lose track of the 9385 original inner_mode. */ 9386 new_rtx = simplify_subreg (GET_MODE (x), r, 9387 inner_mode, SUBREG_BYTE (x)); 9388 if (new_rtx) 9389 return new_rtx; 9390 else 9391 SUBST (SUBREG_REG (x), r); 9392 } 9393 9394 return x; 9395 } 9396 /* We don't have to handle SIGN_EXTEND here, because even in the 9397 case of replacing something with a modeless CONST_INT, a 9398 CONST_INT is already (supposed to be) a valid sign extension for 9399 its narrower mode, which implies it's already properly 9400 sign-extended for the wider mode. Now, for ZERO_EXTEND, the 9401 story is different. */ 9402 else if (code == ZERO_EXTEND) 9403 { 9404 machine_mode inner_mode = GET_MODE (XEXP (x, 0)); 9405 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val); 9406 9407 if (XEXP (x, 0) != r) 9408 { 9409 /* We must simplify the zero_extend here, before we lose 9410 track of the original inner_mode. */ 9411 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), 9412 r, inner_mode); 9413 if (new_rtx) 9414 return new_rtx; 9415 else 9416 SUBST (XEXP (x, 0), r); 9417 } 9418 9419 return x; 9420 } 9421 9422 fmt = GET_RTX_FORMAT (code); 9423 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 9424 { 9425 if (fmt[i] == 'e') 9426 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); 9427 else if (fmt[i] == 'E') 9428 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 9429 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), 9430 cond, reg, val)); 9431 } 9432 9433 return x; 9434 } 9435 9436 /* See if X and Y are equal for the purposes of seeing if we can rewrite an 9437 assignment as a field assignment. */ 9438 9439 static int 9440 rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x) 9441 { 9442 if (widen_x && GET_MODE (x) != GET_MODE (y)) 9443 { 9444 if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (y))) 9445 return 0; 9446 if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN) 9447 return 0; 9448 /* For big endian, adjust the memory offset. */ 9449 if (BYTES_BIG_ENDIAN) 9450 x = adjust_address_nv (x, GET_MODE (y), 9451 -subreg_lowpart_offset (GET_MODE (x), 9452 GET_MODE (y))); 9453 else 9454 x = adjust_address_nv (x, GET_MODE (y), 0); 9455 } 9456 9457 if (x == y || rtx_equal_p (x, y)) 9458 return 1; 9459 9460 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) 9461 return 0; 9462 9463 /* Check for a paradoxical SUBREG of a MEM compared with the MEM. 9464 Note that all SUBREGs of MEM are paradoxical; otherwise they 9465 would have been rewritten. */ 9466 if (MEM_P (x) && GET_CODE (y) == SUBREG 9467 && MEM_P (SUBREG_REG (y)) 9468 && rtx_equal_p (SUBREG_REG (y), 9469 gen_lowpart (GET_MODE (SUBREG_REG (y)), x))) 9470 return 1; 9471 9472 if (MEM_P (y) && GET_CODE (x) == SUBREG 9473 && MEM_P (SUBREG_REG (x)) 9474 && rtx_equal_p (SUBREG_REG (x), 9475 gen_lowpart (GET_MODE (SUBREG_REG (x)), y))) 9476 return 1; 9477 9478 /* We used to see if get_last_value of X and Y were the same but that's 9479 not correct. In one direction, we'll cause the assignment to have 9480 the wrong destination and in the case, we'll import a register into this 9481 insn that might have already have been dead. So fail if none of the 9482 above cases are true. */ 9483 return 0; 9484 } 9485 9486 /* See if X, a SET operation, can be rewritten as a bit-field assignment. 9487 Return that assignment if so. 9488 9489 We only handle the most common cases. */ 9490 9491 static rtx 9492 make_field_assignment (rtx x) 9493 { 9494 rtx dest = SET_DEST (x); 9495 rtx src = SET_SRC (x); 9496 rtx assign; 9497 rtx rhs, lhs; 9498 HOST_WIDE_INT c1; 9499 HOST_WIDE_INT pos; 9500 unsigned HOST_WIDE_INT len; 9501 rtx other; 9502 machine_mode mode; 9503 9504 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is 9505 a clear of a one-bit field. We will have changed it to 9506 (and (rotate (const_int -2) POS) DEST), so check for that. Also check 9507 for a SUBREG. */ 9508 9509 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE 9510 && CONST_INT_P (XEXP (XEXP (src, 0), 0)) 9511 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 9512 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 9513 { 9514 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 9515 1, 1, 1, 0); 9516 if (assign != 0) 9517 return gen_rtx_SET (assign, const0_rtx); 9518 return x; 9519 } 9520 9521 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG 9522 && subreg_lowpart_p (XEXP (src, 0)) 9523 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) 9524 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) 9525 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE 9526 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) 9527 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 9528 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 9529 { 9530 assign = make_extraction (VOIDmode, dest, 0, 9531 XEXP (SUBREG_REG (XEXP (src, 0)), 1), 9532 1, 1, 1, 0); 9533 if (assign != 0) 9534 return gen_rtx_SET (assign, const0_rtx); 9535 return x; 9536 } 9537 9538 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a 9539 one-bit field. */ 9540 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT 9541 && XEXP (XEXP (src, 0), 0) == const1_rtx 9542 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 9543 { 9544 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 9545 1, 1, 1, 0); 9546 if (assign != 0) 9547 return gen_rtx_SET (assign, const1_rtx); 9548 return x; 9549 } 9550 9551 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the 9552 SRC is an AND with all bits of that field set, then we can discard 9553 the AND. */ 9554 if (GET_CODE (dest) == ZERO_EXTRACT 9555 && CONST_INT_P (XEXP (dest, 1)) 9556 && GET_CODE (src) == AND 9557 && CONST_INT_P (XEXP (src, 1))) 9558 { 9559 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1)); 9560 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1)); 9561 unsigned HOST_WIDE_INT ze_mask; 9562 9563 if (width >= HOST_BITS_PER_WIDE_INT) 9564 ze_mask = -1; 9565 else 9566 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; 9567 9568 /* Complete overlap. We can remove the source AND. */ 9569 if ((and_mask & ze_mask) == ze_mask) 9570 return gen_rtx_SET (dest, XEXP (src, 0)); 9571 9572 /* Partial overlap. We can reduce the source AND. */ 9573 if ((and_mask & ze_mask) != and_mask) 9574 { 9575 mode = GET_MODE (src); 9576 src = gen_rtx_AND (mode, XEXP (src, 0), 9577 gen_int_mode (and_mask & ze_mask, mode)); 9578 return gen_rtx_SET (dest, src); 9579 } 9580 } 9581 9582 /* The other case we handle is assignments into a constant-position 9583 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents 9584 a mask that has all one bits except for a group of zero bits and 9585 OTHER is known to have zeros where C1 has ones, this is such an 9586 assignment. Compute the position and length from C1. Shift OTHER 9587 to the appropriate position, force it to the required mode, and 9588 make the extraction. Check for the AND in both operands. */ 9589 9590 /* One or more SUBREGs might obscure the constant-position field 9591 assignment. The first one we are likely to encounter is an outer 9592 narrowing SUBREG, which we can just strip for the purposes of 9593 identifying the constant-field assignment. */ 9594 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)) 9595 src = SUBREG_REG (src); 9596 9597 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) 9598 return x; 9599 9600 rhs = expand_compound_operation (XEXP (src, 0)); 9601 lhs = expand_compound_operation (XEXP (src, 1)); 9602 9603 if (GET_CODE (rhs) == AND 9604 && CONST_INT_P (XEXP (rhs, 1)) 9605 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) 9606 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 9607 /* The second SUBREG that might get in the way is a paradoxical 9608 SUBREG around the first operand of the AND. We want to 9609 pretend the operand is as wide as the destination here. We 9610 do this by adjusting the MEM to wider mode for the sole 9611 purpose of the call to rtx_equal_for_field_assignment_p. Also 9612 note this trick only works for MEMs. */ 9613 else if (GET_CODE (rhs) == AND 9614 && paradoxical_subreg_p (XEXP (rhs, 0)) 9615 && MEM_P (SUBREG_REG (XEXP (rhs, 0))) 9616 && CONST_INT_P (XEXP (rhs, 1)) 9617 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)), 9618 dest, true)) 9619 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 9620 else if (GET_CODE (lhs) == AND 9621 && CONST_INT_P (XEXP (lhs, 1)) 9622 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) 9623 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 9624 /* The second SUBREG that might get in the way is a paradoxical 9625 SUBREG around the first operand of the AND. We want to 9626 pretend the operand is as wide as the destination here. We 9627 do this by adjusting the MEM to wider mode for the sole 9628 purpose of the call to rtx_equal_for_field_assignment_p. Also 9629 note this trick only works for MEMs. */ 9630 else if (GET_CODE (lhs) == AND 9631 && paradoxical_subreg_p (XEXP (lhs, 0)) 9632 && MEM_P (SUBREG_REG (XEXP (lhs, 0))) 9633 && CONST_INT_P (XEXP (lhs, 1)) 9634 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)), 9635 dest, true)) 9636 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 9637 else 9638 return x; 9639 9640 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); 9641 if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest)) 9642 || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT 9643 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) 9644 return x; 9645 9646 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); 9647 if (assign == 0) 9648 return x; 9649 9650 /* The mode to use for the source is the mode of the assignment, or of 9651 what is inside a possible STRICT_LOW_PART. */ 9652 mode = (GET_CODE (assign) == STRICT_LOW_PART 9653 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); 9654 9655 /* Shift OTHER right POS places and make it the source, restricting it 9656 to the proper length and mode. */ 9657 9658 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT, 9659 GET_MODE (src), 9660 other, pos), 9661 dest); 9662 src = force_to_mode (src, mode, 9663 GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT 9664 ? HOST_WIDE_INT_M1U 9665 : (HOST_WIDE_INT_1U << len) - 1, 9666 0); 9667 9668 /* If SRC is masked by an AND that does not make a difference in 9669 the value being stored, strip it. */ 9670 if (GET_CODE (assign) == ZERO_EXTRACT 9671 && CONST_INT_P (XEXP (assign, 1)) 9672 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT 9673 && GET_CODE (src) == AND 9674 && CONST_INT_P (XEXP (src, 1)) 9675 && UINTVAL (XEXP (src, 1)) 9676 == (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1) 9677 src = XEXP (src, 0); 9678 9679 return gen_rtx_SET (assign, src); 9680 } 9681 9682 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) 9683 if so. */ 9684 9685 static rtx 9686 apply_distributive_law (rtx x) 9687 { 9688 enum rtx_code code = GET_CODE (x); 9689 enum rtx_code inner_code; 9690 rtx lhs, rhs, other; 9691 rtx tem; 9692 9693 /* Distributivity is not true for floating point as it can change the 9694 value. So we don't do it unless -funsafe-math-optimizations. */ 9695 if (FLOAT_MODE_P (GET_MODE (x)) 9696 && ! flag_unsafe_math_optimizations) 9697 return x; 9698 9699 /* The outer operation can only be one of the following: */ 9700 if (code != IOR && code != AND && code != XOR 9701 && code != PLUS && code != MINUS) 9702 return x; 9703 9704 lhs = XEXP (x, 0); 9705 rhs = XEXP (x, 1); 9706 9707 /* If either operand is a primitive we can't do anything, so get out 9708 fast. */ 9709 if (OBJECT_P (lhs) || OBJECT_P (rhs)) 9710 return x; 9711 9712 lhs = expand_compound_operation (lhs); 9713 rhs = expand_compound_operation (rhs); 9714 inner_code = GET_CODE (lhs); 9715 if (inner_code != GET_CODE (rhs)) 9716 return x; 9717 9718 /* See if the inner and outer operations distribute. */ 9719 switch (inner_code) 9720 { 9721 case LSHIFTRT: 9722 case ASHIFTRT: 9723 case AND: 9724 case IOR: 9725 /* These all distribute except over PLUS. */ 9726 if (code == PLUS || code == MINUS) 9727 return x; 9728 break; 9729 9730 case MULT: 9731 if (code != PLUS && code != MINUS) 9732 return x; 9733 break; 9734 9735 case ASHIFT: 9736 /* This is also a multiply, so it distributes over everything. */ 9737 break; 9738 9739 /* This used to handle SUBREG, but this turned out to be counter- 9740 productive, since (subreg (op ...)) usually is not handled by 9741 insn patterns, and this "optimization" therefore transformed 9742 recognizable patterns into unrecognizable ones. Therefore the 9743 SUBREG case was removed from here. 9744 9745 It is possible that distributing SUBREG over arithmetic operations 9746 leads to an intermediate result than can then be optimized further, 9747 e.g. by moving the outer SUBREG to the other side of a SET as done 9748 in simplify_set. This seems to have been the original intent of 9749 handling SUBREGs here. 9750 9751 However, with current GCC this does not appear to actually happen, 9752 at least on major platforms. If some case is found where removing 9753 the SUBREG case here prevents follow-on optimizations, distributing 9754 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */ 9755 9756 default: 9757 return x; 9758 } 9759 9760 /* Set LHS and RHS to the inner operands (A and B in the example 9761 above) and set OTHER to the common operand (C in the example). 9762 There is only one way to do this unless the inner operation is 9763 commutative. */ 9764 if (COMMUTATIVE_ARITH_P (lhs) 9765 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) 9766 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); 9767 else if (COMMUTATIVE_ARITH_P (lhs) 9768 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) 9769 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); 9770 else if (COMMUTATIVE_ARITH_P (lhs) 9771 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) 9772 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); 9773 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) 9774 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); 9775 else 9776 return x; 9777 9778 /* Form the new inner operation, seeing if it simplifies first. */ 9779 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs); 9780 9781 /* There is one exception to the general way of distributing: 9782 (a | c) ^ (b | c) -> (a ^ b) & ~c */ 9783 if (code == XOR && inner_code == IOR) 9784 { 9785 inner_code = AND; 9786 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); 9787 } 9788 9789 /* We may be able to continuing distributing the result, so call 9790 ourselves recursively on the inner operation before forming the 9791 outer operation, which we return. */ 9792 return simplify_gen_binary (inner_code, GET_MODE (x), 9793 apply_distributive_law (tem), other); 9794 } 9795 9796 /* See if X is of the form (* (+ A B) C), and if so convert to 9797 (+ (* A C) (* B C)) and try to simplify. 9798 9799 Most of the time, this results in no change. However, if some of 9800 the operands are the same or inverses of each other, simplifications 9801 will result. 9802 9803 For example, (and (ior A B) (not B)) can occur as the result of 9804 expanding a bit field assignment. When we apply the distributive 9805 law to this, we get (ior (and (A (not B))) (and (B (not B)))), 9806 which then simplifies to (and (A (not B))). 9807 9808 Note that no checks happen on the validity of applying the inverse 9809 distributive law. This is pointless since we can do it in the 9810 few places where this routine is called. 9811 9812 N is the index of the term that is decomposed (the arithmetic operation, 9813 i.e. (+ A B) in the first example above). !N is the index of the term that 9814 is distributed, i.e. of C in the first example above. */ 9815 static rtx 9816 distribute_and_simplify_rtx (rtx x, int n) 9817 { 9818 machine_mode mode; 9819 enum rtx_code outer_code, inner_code; 9820 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp; 9821 9822 /* Distributivity is not true for floating point as it can change the 9823 value. So we don't do it unless -funsafe-math-optimizations. */ 9824 if (FLOAT_MODE_P (GET_MODE (x)) 9825 && ! flag_unsafe_math_optimizations) 9826 return NULL_RTX; 9827 9828 decomposed = XEXP (x, n); 9829 if (!ARITHMETIC_P (decomposed)) 9830 return NULL_RTX; 9831 9832 mode = GET_MODE (x); 9833 outer_code = GET_CODE (x); 9834 distributed = XEXP (x, !n); 9835 9836 inner_code = GET_CODE (decomposed); 9837 inner_op0 = XEXP (decomposed, 0); 9838 inner_op1 = XEXP (decomposed, 1); 9839 9840 /* Special case (and (xor B C) (not A)), which is equivalent to 9841 (xor (ior A B) (ior A C)) */ 9842 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT) 9843 { 9844 distributed = XEXP (distributed, 0); 9845 outer_code = IOR; 9846 } 9847 9848 if (n == 0) 9849 { 9850 /* Distribute the second term. */ 9851 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed); 9852 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed); 9853 } 9854 else 9855 { 9856 /* Distribute the first term. */ 9857 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0); 9858 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1); 9859 } 9860 9861 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode, 9862 new_op0, new_op1)); 9863 if (GET_CODE (tmp) != outer_code 9864 && (set_src_cost (tmp, mode, optimize_this_for_speed_p) 9865 < set_src_cost (x, mode, optimize_this_for_speed_p))) 9866 return tmp; 9867 9868 return NULL_RTX; 9869 } 9870 9871 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done 9872 in MODE. Return an equivalent form, if different from (and VAROP 9873 (const_int CONSTOP)). Otherwise, return NULL_RTX. */ 9874 9875 static rtx 9876 simplify_and_const_int_1 (machine_mode mode, rtx varop, 9877 unsigned HOST_WIDE_INT constop) 9878 { 9879 unsigned HOST_WIDE_INT nonzero; 9880 unsigned HOST_WIDE_INT orig_constop; 9881 rtx orig_varop; 9882 int i; 9883 9884 orig_varop = varop; 9885 orig_constop = constop; 9886 if (GET_CODE (varop) == CLOBBER) 9887 return NULL_RTX; 9888 9889 /* Simplify VAROP knowing that we will be only looking at some of the 9890 bits in it. 9891 9892 Note by passing in CONSTOP, we guarantee that the bits not set in 9893 CONSTOP are not significant and will never be examined. We must 9894 ensure that is the case by explicitly masking out those bits 9895 before returning. */ 9896 varop = force_to_mode (varop, mode, constop, 0); 9897 9898 /* If VAROP is a CLOBBER, we will fail so return it. */ 9899 if (GET_CODE (varop) == CLOBBER) 9900 return varop; 9901 9902 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP 9903 to VAROP and return the new constant. */ 9904 if (CONST_INT_P (varop)) 9905 return gen_int_mode (INTVAL (varop) & constop, mode); 9906 9907 /* See what bits may be nonzero in VAROP. Unlike the general case of 9908 a call to nonzero_bits, here we don't care about bits outside 9909 MODE. */ 9910 9911 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); 9912 9913 /* Turn off all bits in the constant that are known to already be zero. 9914 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS 9915 which is tested below. */ 9916 9917 constop &= nonzero; 9918 9919 /* If we don't have any bits left, return zero. */ 9920 if (constop == 0) 9921 return const0_rtx; 9922 9923 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is 9924 a power of two, we can replace this with an ASHIFT. */ 9925 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 9926 && (i = exact_log2 (constop)) >= 0) 9927 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); 9928 9929 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR 9930 or XOR, then try to apply the distributive law. This may eliminate 9931 operations if either branch can be simplified because of the AND. 9932 It may also make some cases more complex, but those cases probably 9933 won't match a pattern either with or without this. */ 9934 9935 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) 9936 return 9937 gen_lowpart 9938 (mode, 9939 apply_distributive_law 9940 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop), 9941 simplify_and_const_int (NULL_RTX, 9942 GET_MODE (varop), 9943 XEXP (varop, 0), 9944 constop), 9945 simplify_and_const_int (NULL_RTX, 9946 GET_MODE (varop), 9947 XEXP (varop, 1), 9948 constop)))); 9949 9950 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute 9951 the AND and see if one of the operands simplifies to zero. If so, we 9952 may eliminate it. */ 9953 9954 if (GET_CODE (varop) == PLUS 9955 && pow2p_hwi (constop + 1)) 9956 { 9957 rtx o0, o1; 9958 9959 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); 9960 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); 9961 if (o0 == const0_rtx) 9962 return o1; 9963 if (o1 == const0_rtx) 9964 return o0; 9965 } 9966 9967 /* Make a SUBREG if necessary. If we can't make it, fail. */ 9968 varop = gen_lowpart (mode, varop); 9969 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) 9970 return NULL_RTX; 9971 9972 /* If we are only masking insignificant bits, return VAROP. */ 9973 if (constop == nonzero) 9974 return varop; 9975 9976 if (varop == orig_varop && constop == orig_constop) 9977 return NULL_RTX; 9978 9979 /* Otherwise, return an AND. */ 9980 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode)); 9981 } 9982 9983 9984 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done 9985 in MODE. 9986 9987 Return an equivalent form, if different from X. Otherwise, return X. If 9988 X is zero, we are to always construct the equivalent form. */ 9989 9990 static rtx 9991 simplify_and_const_int (rtx x, machine_mode mode, rtx varop, 9992 unsigned HOST_WIDE_INT constop) 9993 { 9994 rtx tem = simplify_and_const_int_1 (mode, varop, constop); 9995 if (tem) 9996 return tem; 9997 9998 if (!x) 9999 x = simplify_gen_binary (AND, GET_MODE (varop), varop, 10000 gen_int_mode (constop, mode)); 10001 if (GET_MODE (x) != mode) 10002 x = gen_lowpart (mode, x); 10003 return x; 10004 } 10005 10006 /* Given a REG, X, compute which bits in X can be nonzero. 10007 We don't care about bits outside of those defined in MODE. 10008 10009 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 10010 a shift, AND, or zero_extract, we can do better. */ 10011 10012 static rtx 10013 reg_nonzero_bits_for_combine (const_rtx x, machine_mode mode, 10014 const_rtx known_x ATTRIBUTE_UNUSED, 10015 machine_mode known_mode ATTRIBUTE_UNUSED, 10016 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED, 10017 unsigned HOST_WIDE_INT *nonzero) 10018 { 10019 rtx tem; 10020 reg_stat_type *rsp; 10021 10022 /* If X is a register whose nonzero bits value is current, use it. 10023 Otherwise, if X is a register whose value we can find, use that 10024 value. Otherwise, use the previously-computed global nonzero bits 10025 for this register. */ 10026 10027 rsp = ®_stat[REGNO (x)]; 10028 if (rsp->last_set_value != 0 10029 && (rsp->last_set_mode == mode 10030 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT 10031 && GET_MODE_CLASS (mode) == MODE_INT)) 10032 && ((rsp->last_set_label >= label_tick_ebb_start 10033 && rsp->last_set_label < label_tick) 10034 || (rsp->last_set_label == label_tick 10035 && DF_INSN_LUID (rsp->last_set) < subst_low_luid) 10036 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 10037 && REGNO (x) < reg_n_sets_max 10038 && REG_N_SETS (REGNO (x)) == 1 10039 && !REGNO_REG_SET_P 10040 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), 10041 REGNO (x))))) 10042 { 10043 /* Note that, even if the precision of last_set_mode is lower than that 10044 of mode, record_value_for_reg invoked nonzero_bits on the register 10045 with nonzero_bits_mode (because last_set_mode is necessarily integral 10046 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode 10047 are all valid, hence in mode too since nonzero_bits_mode is defined 10048 to the largest HWI_COMPUTABLE_MODE_P mode. */ 10049 *nonzero &= rsp->last_set_nonzero_bits; 10050 return NULL; 10051 } 10052 10053 tem = get_last_value (x); 10054 if (tem) 10055 { 10056 if (SHORT_IMMEDIATES_SIGN_EXTEND) 10057 tem = sign_extend_short_imm (tem, GET_MODE (x), 10058 GET_MODE_PRECISION (mode)); 10059 10060 return tem; 10061 } 10062 10063 if (nonzero_sign_valid && rsp->nonzero_bits) 10064 { 10065 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits; 10066 10067 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)) 10068 /* We don't know anything about the upper bits. */ 10069 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); 10070 10071 *nonzero &= mask; 10072 } 10073 10074 return NULL; 10075 } 10076 10077 /* Return the number of bits at the high-order end of X that are known to 10078 be equal to the sign bit. X will be used in mode MODE; if MODE is 10079 VOIDmode, X will be used in its own mode. The returned value will always 10080 be between 1 and the number of bits in MODE. */ 10081 10082 static rtx 10083 reg_num_sign_bit_copies_for_combine (const_rtx x, machine_mode mode, 10084 const_rtx known_x ATTRIBUTE_UNUSED, 10085 machine_mode known_mode 10086 ATTRIBUTE_UNUSED, 10087 unsigned int known_ret ATTRIBUTE_UNUSED, 10088 unsigned int *result) 10089 { 10090 rtx tem; 10091 reg_stat_type *rsp; 10092 10093 rsp = ®_stat[REGNO (x)]; 10094 if (rsp->last_set_value != 0 10095 && rsp->last_set_mode == mode 10096 && ((rsp->last_set_label >= label_tick_ebb_start 10097 && rsp->last_set_label < label_tick) 10098 || (rsp->last_set_label == label_tick 10099 && DF_INSN_LUID (rsp->last_set) < subst_low_luid) 10100 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 10101 && REGNO (x) < reg_n_sets_max 10102 && REG_N_SETS (REGNO (x)) == 1 10103 && !REGNO_REG_SET_P 10104 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), 10105 REGNO (x))))) 10106 { 10107 *result = rsp->last_set_sign_bit_copies; 10108 return NULL; 10109 } 10110 10111 tem = get_last_value (x); 10112 if (tem != 0) 10113 return tem; 10114 10115 if (nonzero_sign_valid && rsp->sign_bit_copies != 0 10116 && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode)) 10117 *result = rsp->sign_bit_copies; 10118 10119 return NULL; 10120 } 10121 10122 /* Return the number of "extended" bits there are in X, when interpreted 10123 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For 10124 unsigned quantities, this is the number of high-order zero bits. 10125 For signed quantities, this is the number of copies of the sign bit 10126 minus 1. In both case, this function returns the number of "spare" 10127 bits. For example, if two quantities for which this function returns 10128 at least 1 are added, the addition is known not to overflow. 10129 10130 This function will always return 0 unless called during combine, which 10131 implies that it must be called from a define_split. */ 10132 10133 unsigned int 10134 extended_count (const_rtx x, machine_mode mode, int unsignedp) 10135 { 10136 if (nonzero_sign_valid == 0) 10137 return 0; 10138 10139 return (unsignedp 10140 ? (HWI_COMPUTABLE_MODE_P (mode) 10141 ? (unsigned int) (GET_MODE_PRECISION (mode) - 1 10142 - floor_log2 (nonzero_bits (x, mode))) 10143 : 0) 10144 : num_sign_bit_copies (x, mode) - 1); 10145 } 10146 10147 /* This function is called from `simplify_shift_const' to merge two 10148 outer operations. Specifically, we have already found that we need 10149 to perform operation *POP0 with constant *PCONST0 at the outermost 10150 position. We would now like to also perform OP1 with constant CONST1 10151 (with *POP0 being done last). 10152 10153 Return 1 if we can do the operation and update *POP0 and *PCONST0 with 10154 the resulting operation. *PCOMP_P is set to 1 if we would need to 10155 complement the innermost operand, otherwise it is unchanged. 10156 10157 MODE is the mode in which the operation will be done. No bits outside 10158 the width of this mode matter. It is assumed that the width of this mode 10159 is smaller than or equal to HOST_BITS_PER_WIDE_INT. 10160 10161 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, 10162 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper 10163 result is simply *PCONST0. 10164 10165 If the resulting operation cannot be expressed as one operation, we 10166 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ 10167 10168 static int 10169 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p) 10170 { 10171 enum rtx_code op0 = *pop0; 10172 HOST_WIDE_INT const0 = *pconst0; 10173 10174 const0 &= GET_MODE_MASK (mode); 10175 const1 &= GET_MODE_MASK (mode); 10176 10177 /* If OP0 is an AND, clear unimportant bits in CONST1. */ 10178 if (op0 == AND) 10179 const1 &= const0; 10180 10181 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or 10182 if OP0 is SET. */ 10183 10184 if (op1 == UNKNOWN || op0 == SET) 10185 return 1; 10186 10187 else if (op0 == UNKNOWN) 10188 op0 = op1, const0 = const1; 10189 10190 else if (op0 == op1) 10191 { 10192 switch (op0) 10193 { 10194 case AND: 10195 const0 &= const1; 10196 break; 10197 case IOR: 10198 const0 |= const1; 10199 break; 10200 case XOR: 10201 const0 ^= const1; 10202 break; 10203 case PLUS: 10204 const0 += const1; 10205 break; 10206 case NEG: 10207 op0 = UNKNOWN; 10208 break; 10209 default: 10210 break; 10211 } 10212 } 10213 10214 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ 10215 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) 10216 return 0; 10217 10218 /* If the two constants aren't the same, we can't do anything. The 10219 remaining six cases can all be done. */ 10220 else if (const0 != const1) 10221 return 0; 10222 10223 else 10224 switch (op0) 10225 { 10226 case IOR: 10227 if (op1 == AND) 10228 /* (a & b) | b == b */ 10229 op0 = SET; 10230 else /* op1 == XOR */ 10231 /* (a ^ b) | b == a | b */ 10232 {;} 10233 break; 10234 10235 case XOR: 10236 if (op1 == AND) 10237 /* (a & b) ^ b == (~a) & b */ 10238 op0 = AND, *pcomp_p = 1; 10239 else /* op1 == IOR */ 10240 /* (a | b) ^ b == a & ~b */ 10241 op0 = AND, const0 = ~const0; 10242 break; 10243 10244 case AND: 10245 if (op1 == IOR) 10246 /* (a | b) & b == b */ 10247 op0 = SET; 10248 else /* op1 == XOR */ 10249 /* (a ^ b) & b) == (~a) & b */ 10250 *pcomp_p = 1; 10251 break; 10252 default: 10253 break; 10254 } 10255 10256 /* Check for NO-OP cases. */ 10257 const0 &= GET_MODE_MASK (mode); 10258 if (const0 == 0 10259 && (op0 == IOR || op0 == XOR || op0 == PLUS)) 10260 op0 = UNKNOWN; 10261 else if (const0 == 0 && op0 == AND) 10262 op0 = SET; 10263 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) 10264 && op0 == AND) 10265 op0 = UNKNOWN; 10266 10267 *pop0 = op0; 10268 10269 /* ??? Slightly redundant with the above mask, but not entirely. 10270 Moving this above means we'd have to sign-extend the mode mask 10271 for the final test. */ 10272 if (op0 != UNKNOWN && op0 != NEG) 10273 *pconst0 = trunc_int_for_mode (const0, mode); 10274 10275 return 1; 10276 } 10277 10278 /* A helper to simplify_shift_const_1 to determine the mode we can perform 10279 the shift in. The original shift operation CODE is performed on OP in 10280 ORIG_MODE. Return the wider mode MODE if we can perform the operation 10281 in that mode. Return ORIG_MODE otherwise. We can also assume that the 10282 result of the shift is subject to operation OUTER_CODE with operand 10283 OUTER_CONST. */ 10284 10285 static machine_mode 10286 try_widen_shift_mode (enum rtx_code code, rtx op, int count, 10287 machine_mode orig_mode, machine_mode mode, 10288 enum rtx_code outer_code, HOST_WIDE_INT outer_const) 10289 { 10290 if (orig_mode == mode) 10291 return mode; 10292 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode)); 10293 10294 /* In general we can't perform in wider mode for right shift and rotate. */ 10295 switch (code) 10296 { 10297 case ASHIFTRT: 10298 /* We can still widen if the bits brought in from the left are identical 10299 to the sign bit of ORIG_MODE. */ 10300 if (num_sign_bit_copies (op, mode) 10301 > (unsigned) (GET_MODE_PRECISION (mode) 10302 - GET_MODE_PRECISION (orig_mode))) 10303 return mode; 10304 return orig_mode; 10305 10306 case LSHIFTRT: 10307 /* Similarly here but with zero bits. */ 10308 if (HWI_COMPUTABLE_MODE_P (mode) 10309 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0) 10310 return mode; 10311 10312 /* We can also widen if the bits brought in will be masked off. This 10313 operation is performed in ORIG_MODE. */ 10314 if (outer_code == AND) 10315 { 10316 int care_bits = low_bitmask_len (orig_mode, outer_const); 10317 10318 if (care_bits >= 0 10319 && GET_MODE_PRECISION (orig_mode) - care_bits >= count) 10320 return mode; 10321 } 10322 /* fall through */ 10323 10324 case ROTATE: 10325 return orig_mode; 10326 10327 case ROTATERT: 10328 gcc_unreachable (); 10329 10330 default: 10331 return mode; 10332 } 10333 } 10334 10335 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind 10336 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX 10337 if we cannot simplify it. Otherwise, return a simplified value. 10338 10339 The shift is normally computed in the widest mode we find in VAROP, as 10340 long as it isn't a different number of words than RESULT_MODE. Exceptions 10341 are ASHIFTRT and ROTATE, which are always done in their original mode. */ 10342 10343 static rtx 10344 simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode, 10345 rtx varop, int orig_count) 10346 { 10347 enum rtx_code orig_code = code; 10348 rtx orig_varop = varop; 10349 int count; 10350 machine_mode mode = result_mode; 10351 machine_mode shift_mode, tmode; 10352 unsigned int mode_words 10353 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; 10354 /* We form (outer_op (code varop count) (outer_const)). */ 10355 enum rtx_code outer_op = UNKNOWN; 10356 HOST_WIDE_INT outer_const = 0; 10357 int complement_p = 0; 10358 rtx new_rtx, x; 10359 10360 /* Make sure and truncate the "natural" shift on the way in. We don't 10361 want to do this inside the loop as it makes it more difficult to 10362 combine shifts. */ 10363 if (SHIFT_COUNT_TRUNCATED) 10364 orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1; 10365 10366 /* If we were given an invalid count, don't do anything except exactly 10367 what was requested. */ 10368 10369 if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode)) 10370 return NULL_RTX; 10371 10372 count = orig_count; 10373 10374 /* Unless one of the branches of the `if' in this loop does a `continue', 10375 we will `break' the loop after the `if'. */ 10376 10377 while (count != 0) 10378 { 10379 /* If we have an operand of (clobber (const_int 0)), fail. */ 10380 if (GET_CODE (varop) == CLOBBER) 10381 return NULL_RTX; 10382 10383 /* Convert ROTATERT to ROTATE. */ 10384 if (code == ROTATERT) 10385 { 10386 unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode); 10387 code = ROTATE; 10388 count = bitsize - count; 10389 } 10390 10391 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, 10392 mode, outer_op, outer_const); 10393 machine_mode shift_unit_mode = GET_MODE_INNER (shift_mode); 10394 10395 /* Handle cases where the count is greater than the size of the mode 10396 minus 1. For ASHIFT, use the size minus one as the count (this can 10397 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, 10398 take the count modulo the size. For other shifts, the result is 10399 zero. 10400 10401 Since these shifts are being produced by the compiler by combining 10402 multiple operations, each of which are defined, we know what the 10403 result is supposed to be. */ 10404 10405 if (count > (GET_MODE_PRECISION (shift_unit_mode) - 1)) 10406 { 10407 if (code == ASHIFTRT) 10408 count = GET_MODE_PRECISION (shift_unit_mode) - 1; 10409 else if (code == ROTATE || code == ROTATERT) 10410 count %= GET_MODE_PRECISION (shift_unit_mode); 10411 else 10412 { 10413 /* We can't simply return zero because there may be an 10414 outer op. */ 10415 varop = const0_rtx; 10416 count = 0; 10417 break; 10418 } 10419 } 10420 10421 /* If we discovered we had to complement VAROP, leave. Making a NOT 10422 here would cause an infinite loop. */ 10423 if (complement_p) 10424 break; 10425 10426 if (shift_mode == shift_unit_mode) 10427 { 10428 /* An arithmetic right shift of a quantity known to be -1 or 0 10429 is a no-op. */ 10430 if (code == ASHIFTRT 10431 && (num_sign_bit_copies (varop, shift_unit_mode) 10432 == GET_MODE_PRECISION (shift_unit_mode))) 10433 { 10434 count = 0; 10435 break; 10436 } 10437 10438 /* If we are doing an arithmetic right shift and discarding all but 10439 the sign bit copies, this is equivalent to doing a shift by the 10440 bitsize minus one. Convert it into that shift because it will 10441 often allow other simplifications. */ 10442 10443 if (code == ASHIFTRT 10444 && (count + num_sign_bit_copies (varop, shift_unit_mode) 10445 >= GET_MODE_PRECISION (shift_unit_mode))) 10446 count = GET_MODE_PRECISION (shift_unit_mode) - 1; 10447 10448 /* We simplify the tests below and elsewhere by converting 10449 ASHIFTRT to LSHIFTRT if we know the sign bit is clear. 10450 `make_compound_operation' will convert it to an ASHIFTRT for 10451 those machines (such as VAX) that don't have an LSHIFTRT. */ 10452 if (code == ASHIFTRT 10453 && HWI_COMPUTABLE_MODE_P (shift_unit_mode) 10454 && val_signbit_known_clear_p (shift_unit_mode, 10455 nonzero_bits (varop, 10456 shift_unit_mode))) 10457 code = LSHIFTRT; 10458 10459 if (((code == LSHIFTRT 10460 && HWI_COMPUTABLE_MODE_P (shift_unit_mode) 10461 && !(nonzero_bits (varop, shift_unit_mode) >> count)) 10462 || (code == ASHIFT 10463 && HWI_COMPUTABLE_MODE_P (shift_unit_mode) 10464 && !((nonzero_bits (varop, shift_unit_mode) << count) 10465 & GET_MODE_MASK (shift_unit_mode)))) 10466 && !side_effects_p (varop)) 10467 varop = const0_rtx; 10468 } 10469 10470 switch (GET_CODE (varop)) 10471 { 10472 case SIGN_EXTEND: 10473 case ZERO_EXTEND: 10474 case SIGN_EXTRACT: 10475 case ZERO_EXTRACT: 10476 new_rtx = expand_compound_operation (varop); 10477 if (new_rtx != varop) 10478 { 10479 varop = new_rtx; 10480 continue; 10481 } 10482 break; 10483 10484 case MEM: 10485 /* The following rules apply only to scalars. */ 10486 if (shift_mode != shift_unit_mode) 10487 break; 10488 10489 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH 10490 minus the width of a smaller mode, we can do this with a 10491 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ 10492 if ((code == ASHIFTRT || code == LSHIFTRT) 10493 && ! mode_dependent_address_p (XEXP (varop, 0), 10494 MEM_ADDR_SPACE (varop)) 10495 && ! MEM_VOLATILE_P (varop) 10496 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 10497 MODE_INT, 1)) != BLKmode) 10498 { 10499 new_rtx = adjust_address_nv (varop, tmode, 10500 BYTES_BIG_ENDIAN ? 0 10501 : count / BITS_PER_UNIT); 10502 10503 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND 10504 : ZERO_EXTEND, mode, new_rtx); 10505 count = 0; 10506 continue; 10507 } 10508 break; 10509 10510 case SUBREG: 10511 /* The following rules apply only to scalars. */ 10512 if (shift_mode != shift_unit_mode) 10513 break; 10514 10515 /* If VAROP is a SUBREG, strip it as long as the inner operand has 10516 the same number of words as what we've seen so far. Then store 10517 the widest mode in MODE. */ 10518 if (subreg_lowpart_p (varop) 10519 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 10520 > GET_MODE_SIZE (GET_MODE (varop))) 10521 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 10522 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 10523 == mode_words 10524 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT 10525 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT) 10526 { 10527 varop = SUBREG_REG (varop); 10528 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) 10529 mode = GET_MODE (varop); 10530 continue; 10531 } 10532 break; 10533 10534 case MULT: 10535 /* Some machines use MULT instead of ASHIFT because MULT 10536 is cheaper. But it is still better on those machines to 10537 merge two shifts into one. */ 10538 if (CONST_INT_P (XEXP (varop, 1)) 10539 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0) 10540 { 10541 varop 10542 = simplify_gen_binary (ASHIFT, GET_MODE (varop), 10543 XEXP (varop, 0), 10544 GEN_INT (exact_log2 ( 10545 UINTVAL (XEXP (varop, 1))))); 10546 continue; 10547 } 10548 break; 10549 10550 case UDIV: 10551 /* Similar, for when divides are cheaper. */ 10552 if (CONST_INT_P (XEXP (varop, 1)) 10553 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0) 10554 { 10555 varop 10556 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop), 10557 XEXP (varop, 0), 10558 GEN_INT (exact_log2 ( 10559 UINTVAL (XEXP (varop, 1))))); 10560 continue; 10561 } 10562 break; 10563 10564 case ASHIFTRT: 10565 /* If we are extracting just the sign bit of an arithmetic 10566 right shift, that shift is not needed. However, the sign 10567 bit of a wider mode may be different from what would be 10568 interpreted as the sign bit in a narrower mode, so, if 10569 the result is narrower, don't discard the shift. */ 10570 if (code == LSHIFTRT 10571 && count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1) 10572 && (GET_MODE_UNIT_BITSIZE (result_mode) 10573 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop)))) 10574 { 10575 varop = XEXP (varop, 0); 10576 continue; 10577 } 10578 10579 /* fall through */ 10580 10581 case LSHIFTRT: 10582 case ASHIFT: 10583 case ROTATE: 10584 /* The following rules apply only to scalars. */ 10585 if (shift_mode != shift_unit_mode) 10586 break; 10587 10588 /* Here we have two nested shifts. The result is usually the 10589 AND of a new shift with a mask. We compute the result below. */ 10590 if (CONST_INT_P (XEXP (varop, 1)) 10591 && INTVAL (XEXP (varop, 1)) >= 0 10592 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop)) 10593 && HWI_COMPUTABLE_MODE_P (result_mode) 10594 && HWI_COMPUTABLE_MODE_P (mode)) 10595 { 10596 enum rtx_code first_code = GET_CODE (varop); 10597 unsigned int first_count = INTVAL (XEXP (varop, 1)); 10598 unsigned HOST_WIDE_INT mask; 10599 rtx mask_rtx; 10600 10601 /* We have one common special case. We can't do any merging if 10602 the inner code is an ASHIFTRT of a smaller mode. However, if 10603 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) 10604 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), 10605 we can convert it to 10606 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1). 10607 This simplifies certain SIGN_EXTEND operations. */ 10608 if (code == ASHIFT && first_code == ASHIFTRT 10609 && count == (GET_MODE_PRECISION (result_mode) 10610 - GET_MODE_PRECISION (GET_MODE (varop)))) 10611 { 10612 /* C3 has the low-order C1 bits zero. */ 10613 10614 mask = GET_MODE_MASK (mode) 10615 & ~((HOST_WIDE_INT_1U << first_count) - 1); 10616 10617 varop = simplify_and_const_int (NULL_RTX, result_mode, 10618 XEXP (varop, 0), mask); 10619 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, 10620 varop, count); 10621 count = first_count; 10622 code = ASHIFTRT; 10623 continue; 10624 } 10625 10626 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more 10627 than C1 high-order bits equal to the sign bit, we can convert 10628 this to either an ASHIFT or an ASHIFTRT depending on the 10629 two counts. 10630 10631 We cannot do this if VAROP's mode is not SHIFT_MODE. */ 10632 10633 if (code == ASHIFTRT && first_code == ASHIFT 10634 && GET_MODE (varop) == shift_mode 10635 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) 10636 > first_count)) 10637 { 10638 varop = XEXP (varop, 0); 10639 count -= first_count; 10640 if (count < 0) 10641 { 10642 count = -count; 10643 code = ASHIFT; 10644 } 10645 10646 continue; 10647 } 10648 10649 /* There are some cases we can't do. If CODE is ASHIFTRT, 10650 we can only do this if FIRST_CODE is also ASHIFTRT. 10651 10652 We can't do the case when CODE is ROTATE and FIRST_CODE is 10653 ASHIFTRT. 10654 10655 If the mode of this shift is not the mode of the outer shift, 10656 we can't do this if either shift is a right shift or ROTATE. 10657 10658 Finally, we can't do any of these if the mode is too wide 10659 unless the codes are the same. 10660 10661 Handle the case where the shift codes are the same 10662 first. */ 10663 10664 if (code == first_code) 10665 { 10666 if (GET_MODE (varop) != result_mode 10667 && (code == ASHIFTRT || code == LSHIFTRT 10668 || code == ROTATE)) 10669 break; 10670 10671 count += first_count; 10672 varop = XEXP (varop, 0); 10673 continue; 10674 } 10675 10676 if (code == ASHIFTRT 10677 || (code == ROTATE && first_code == ASHIFTRT) 10678 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT 10679 || (GET_MODE (varop) != result_mode 10680 && (first_code == ASHIFTRT || first_code == LSHIFTRT 10681 || first_code == ROTATE 10682 || code == ROTATE))) 10683 break; 10684 10685 /* To compute the mask to apply after the shift, shift the 10686 nonzero bits of the inner shift the same way the 10687 outer shift will. */ 10688 10689 mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)), 10690 result_mode); 10691 10692 mask_rtx 10693 = simplify_const_binary_operation (code, result_mode, mask_rtx, 10694 GEN_INT (count)); 10695 10696 /* Give up if we can't compute an outer operation to use. */ 10697 if (mask_rtx == 0 10698 || !CONST_INT_P (mask_rtx) 10699 || ! merge_outer_ops (&outer_op, &outer_const, AND, 10700 INTVAL (mask_rtx), 10701 result_mode, &complement_p)) 10702 break; 10703 10704 /* If the shifts are in the same direction, we add the 10705 counts. Otherwise, we subtract them. */ 10706 if ((code == ASHIFTRT || code == LSHIFTRT) 10707 == (first_code == ASHIFTRT || first_code == LSHIFTRT)) 10708 count += first_count; 10709 else 10710 count -= first_count; 10711 10712 /* If COUNT is positive, the new shift is usually CODE, 10713 except for the two exceptions below, in which case it is 10714 FIRST_CODE. If the count is negative, FIRST_CODE should 10715 always be used */ 10716 if (count > 0 10717 && ((first_code == ROTATE && code == ASHIFT) 10718 || (first_code == ASHIFTRT && code == LSHIFTRT))) 10719 code = first_code; 10720 else if (count < 0) 10721 code = first_code, count = -count; 10722 10723 varop = XEXP (varop, 0); 10724 continue; 10725 } 10726 10727 /* If we have (A << B << C) for any shift, we can convert this to 10728 (A << C << B). This wins if A is a constant. Only try this if 10729 B is not a constant. */ 10730 10731 else if (GET_CODE (varop) == code 10732 && CONST_INT_P (XEXP (varop, 0)) 10733 && !CONST_INT_P (XEXP (varop, 1))) 10734 { 10735 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make 10736 sure the result will be masked. See PR70222. */ 10737 if (code == LSHIFTRT 10738 && mode != result_mode 10739 && !merge_outer_ops (&outer_op, &outer_const, AND, 10740 GET_MODE_MASK (result_mode) 10741 >> orig_count, result_mode, 10742 &complement_p)) 10743 break; 10744 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing 10745 up outer sign extension (often left and right shift) is 10746 hardly more efficient than the original. See PR70429. */ 10747 if (code == ASHIFTRT && mode != result_mode) 10748 break; 10749 10750 rtx new_rtx = simplify_const_binary_operation (code, mode, 10751 XEXP (varop, 0), 10752 GEN_INT (count)); 10753 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1)); 10754 count = 0; 10755 continue; 10756 } 10757 break; 10758 10759 case NOT: 10760 /* The following rules apply only to scalars. */ 10761 if (shift_mode != shift_unit_mode) 10762 break; 10763 10764 /* Make this fit the case below. */ 10765 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx); 10766 continue; 10767 10768 case IOR: 10769 case AND: 10770 case XOR: 10771 /* The following rules apply only to scalars. */ 10772 if (shift_mode != shift_unit_mode) 10773 break; 10774 10775 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) 10776 with C the size of VAROP - 1 and the shift is logical if 10777 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 10778 we have an (le X 0) operation. If we have an arithmetic shift 10779 and STORE_FLAG_VALUE is 1 or we have a logical shift with 10780 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ 10781 10782 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS 10783 && XEXP (XEXP (varop, 0), 1) == constm1_rtx 10784 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 10785 && (code == LSHIFTRT || code == ASHIFTRT) 10786 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1) 10787 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 10788 { 10789 count = 0; 10790 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), 10791 const0_rtx); 10792 10793 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 10794 varop = gen_rtx_NEG (GET_MODE (varop), varop); 10795 10796 continue; 10797 } 10798 10799 /* If we have (shift (logical)), move the logical to the outside 10800 to allow it to possibly combine with another logical and the 10801 shift to combine with another shift. This also canonicalizes to 10802 what a ZERO_EXTRACT looks like. Also, some machines have 10803 (and (shift)) insns. */ 10804 10805 if (CONST_INT_P (XEXP (varop, 1)) 10806 /* We can't do this if we have (ashiftrt (xor)) and the 10807 constant has its sign bit set in shift_mode with shift_mode 10808 wider than result_mode. */ 10809 && !(code == ASHIFTRT && GET_CODE (varop) == XOR 10810 && result_mode != shift_mode 10811 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), 10812 shift_mode)) 10813 && (new_rtx = simplify_const_binary_operation 10814 (code, result_mode, 10815 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode), 10816 GEN_INT (count))) != 0 10817 && CONST_INT_P (new_rtx) 10818 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), 10819 INTVAL (new_rtx), result_mode, &complement_p)) 10820 { 10821 varop = XEXP (varop, 0); 10822 continue; 10823 } 10824 10825 /* If we can't do that, try to simplify the shift in each arm of the 10826 logical expression, make a new logical expression, and apply 10827 the inverse distributive law. This also can't be done for 10828 (ashiftrt (xor)) where we've widened the shift and the constant 10829 changes the sign bit. */ 10830 if (CONST_INT_P (XEXP (varop, 1)) 10831 && !(code == ASHIFTRT && GET_CODE (varop) == XOR 10832 && result_mode != shift_mode 10833 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), 10834 shift_mode))) 10835 { 10836 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, 10837 XEXP (varop, 0), count); 10838 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, 10839 XEXP (varop, 1), count); 10840 10841 varop = simplify_gen_binary (GET_CODE (varop), shift_mode, 10842 lhs, rhs); 10843 varop = apply_distributive_law (varop); 10844 10845 count = 0; 10846 continue; 10847 } 10848 break; 10849 10850 case EQ: 10851 /* The following rules apply only to scalars. */ 10852 if (shift_mode != shift_unit_mode) 10853 break; 10854 10855 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE 10856 says that the sign bit can be tested, FOO has mode MODE, C is 10857 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit 10858 that may be nonzero. */ 10859 if (code == LSHIFTRT 10860 && XEXP (varop, 1) == const0_rtx 10861 && GET_MODE (XEXP (varop, 0)) == result_mode 10862 && count == (GET_MODE_PRECISION (result_mode) - 1) 10863 && HWI_COMPUTABLE_MODE_P (result_mode) 10864 && STORE_FLAG_VALUE == -1 10865 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 10866 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode, 10867 &complement_p)) 10868 { 10869 varop = XEXP (varop, 0); 10870 count = 0; 10871 continue; 10872 } 10873 break; 10874 10875 case NEG: 10876 /* The following rules apply only to scalars. */ 10877 if (shift_mode != shift_unit_mode) 10878 break; 10879 10880 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less 10881 than the number of bits in the mode is equivalent to A. */ 10882 if (code == LSHIFTRT 10883 && count == (GET_MODE_PRECISION (result_mode) - 1) 10884 && nonzero_bits (XEXP (varop, 0), result_mode) == 1) 10885 { 10886 varop = XEXP (varop, 0); 10887 count = 0; 10888 continue; 10889 } 10890 10891 /* NEG commutes with ASHIFT since it is multiplication. Move the 10892 NEG outside to allow shifts to combine. */ 10893 if (code == ASHIFT 10894 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode, 10895 &complement_p)) 10896 { 10897 varop = XEXP (varop, 0); 10898 continue; 10899 } 10900 break; 10901 10902 case PLUS: 10903 /* The following rules apply only to scalars. */ 10904 if (shift_mode != shift_unit_mode) 10905 break; 10906 10907 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C 10908 is one less than the number of bits in the mode is 10909 equivalent to (xor A 1). */ 10910 if (code == LSHIFTRT 10911 && count == (GET_MODE_PRECISION (result_mode) - 1) 10912 && XEXP (varop, 1) == constm1_rtx 10913 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 10914 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode, 10915 &complement_p)) 10916 { 10917 count = 0; 10918 varop = XEXP (varop, 0); 10919 continue; 10920 } 10921 10922 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits 10923 that might be nonzero in BAR are those being shifted out and those 10924 bits are known zero in FOO, we can replace the PLUS with FOO. 10925 Similarly in the other operand order. This code occurs when 10926 we are computing the size of a variable-size array. */ 10927 10928 if ((code == ASHIFTRT || code == LSHIFTRT) 10929 && count < HOST_BITS_PER_WIDE_INT 10930 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 10931 && (nonzero_bits (XEXP (varop, 1), result_mode) 10932 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) 10933 { 10934 varop = XEXP (varop, 0); 10935 continue; 10936 } 10937 else if ((code == ASHIFTRT || code == LSHIFTRT) 10938 && count < HOST_BITS_PER_WIDE_INT 10939 && HWI_COMPUTABLE_MODE_P (result_mode) 10940 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 10941 >> count) 10942 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 10943 & nonzero_bits (XEXP (varop, 1), 10944 result_mode))) 10945 { 10946 varop = XEXP (varop, 1); 10947 continue; 10948 } 10949 10950 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ 10951 if (code == ASHIFT 10952 && CONST_INT_P (XEXP (varop, 1)) 10953 && (new_rtx = simplify_const_binary_operation 10954 (ASHIFT, result_mode, 10955 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode), 10956 GEN_INT (count))) != 0 10957 && CONST_INT_P (new_rtx) 10958 && merge_outer_ops (&outer_op, &outer_const, PLUS, 10959 INTVAL (new_rtx), result_mode, &complement_p)) 10960 { 10961 varop = XEXP (varop, 0); 10962 continue; 10963 } 10964 10965 /* Check for 'PLUS signbit', which is the canonical form of 'XOR 10966 signbit', and attempt to change the PLUS to an XOR and move it to 10967 the outer operation as is done above in the AND/IOR/XOR case 10968 leg for shift(logical). See details in logical handling above 10969 for reasoning in doing so. */ 10970 if (code == LSHIFTRT 10971 && CONST_INT_P (XEXP (varop, 1)) 10972 && mode_signbit_p (result_mode, XEXP (varop, 1)) 10973 && (new_rtx = simplify_const_binary_operation 10974 (code, result_mode, 10975 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode), 10976 GEN_INT (count))) != 0 10977 && CONST_INT_P (new_rtx) 10978 && merge_outer_ops (&outer_op, &outer_const, XOR, 10979 INTVAL (new_rtx), result_mode, &complement_p)) 10980 { 10981 varop = XEXP (varop, 0); 10982 continue; 10983 } 10984 10985 break; 10986 10987 case MINUS: 10988 /* The following rules apply only to scalars. */ 10989 if (shift_mode != shift_unit_mode) 10990 break; 10991 10992 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) 10993 with C the size of VAROP - 1 and the shift is logical if 10994 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 10995 we have a (gt X 0) operation. If the shift is arithmetic with 10996 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, 10997 we have a (neg (gt X 0)) operation. */ 10998 10999 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 11000 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT 11001 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1) 11002 && (code == LSHIFTRT || code == ASHIFTRT) 11003 && CONST_INT_P (XEXP (XEXP (varop, 0), 1)) 11004 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count 11005 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 11006 { 11007 count = 0; 11008 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), 11009 const0_rtx); 11010 11011 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 11012 varop = gen_rtx_NEG (GET_MODE (varop), varop); 11013 11014 continue; 11015 } 11016 break; 11017 11018 case TRUNCATE: 11019 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) 11020 if the truncate does not affect the value. */ 11021 if (code == LSHIFTRT 11022 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT 11023 && CONST_INT_P (XEXP (XEXP (varop, 0), 1)) 11024 && (INTVAL (XEXP (XEXP (varop, 0), 1)) 11025 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0))) 11026 - GET_MODE_UNIT_PRECISION (GET_MODE (varop))))) 11027 { 11028 rtx varop_inner = XEXP (varop, 0); 11029 11030 varop_inner 11031 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), 11032 XEXP (varop_inner, 0), 11033 GEN_INT 11034 (count + INTVAL (XEXP (varop_inner, 1)))); 11035 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); 11036 count = 0; 11037 continue; 11038 } 11039 break; 11040 11041 default: 11042 break; 11043 } 11044 11045 break; 11046 } 11047 11048 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode, 11049 outer_op, outer_const); 11050 11051 /* We have now finished analyzing the shift. The result should be 11052 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If 11053 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied 11054 to the result of the shift. OUTER_CONST is the relevant constant, 11055 but we must turn off all bits turned off in the shift. */ 11056 11057 if (outer_op == UNKNOWN 11058 && orig_code == code && orig_count == count 11059 && varop == orig_varop 11060 && shift_mode == GET_MODE (varop)) 11061 return NULL_RTX; 11062 11063 /* Make a SUBREG if necessary. If we can't make it, fail. */ 11064 varop = gen_lowpart (shift_mode, varop); 11065 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) 11066 return NULL_RTX; 11067 11068 /* If we have an outer operation and we just made a shift, it is 11069 possible that we could have simplified the shift were it not 11070 for the outer operation. So try to do the simplification 11071 recursively. */ 11072 11073 if (outer_op != UNKNOWN) 11074 x = simplify_shift_const_1 (code, shift_mode, varop, count); 11075 else 11076 x = NULL_RTX; 11077 11078 if (x == NULL_RTX) 11079 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count)); 11080 11081 /* If we were doing an LSHIFTRT in a wider mode than it was originally, 11082 turn off all the bits that the shift would have turned off. */ 11083 if (orig_code == LSHIFTRT && result_mode != shift_mode) 11084 x = simplify_and_const_int (NULL_RTX, shift_mode, x, 11085 GET_MODE_MASK (result_mode) >> orig_count); 11086 11087 /* Do the remainder of the processing in RESULT_MODE. */ 11088 x = gen_lowpart_or_truncate (result_mode, x); 11089 11090 /* If COMPLEMENT_P is set, we have to complement X before doing the outer 11091 operation. */ 11092 if (complement_p) 11093 x = simplify_gen_unary (NOT, result_mode, x, result_mode); 11094 11095 if (outer_op != UNKNOWN) 11096 { 11097 if (GET_RTX_CLASS (outer_op) != RTX_UNARY 11098 && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT) 11099 outer_const = trunc_int_for_mode (outer_const, result_mode); 11100 11101 if (outer_op == AND) 11102 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); 11103 else if (outer_op == SET) 11104 { 11105 /* This means that we have determined that the result is 11106 equivalent to a constant. This should be rare. */ 11107 if (!side_effects_p (x)) 11108 x = GEN_INT (outer_const); 11109 } 11110 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY) 11111 x = simplify_gen_unary (outer_op, result_mode, x, result_mode); 11112 else 11113 x = simplify_gen_binary (outer_op, result_mode, x, 11114 GEN_INT (outer_const)); 11115 } 11116 11117 return x; 11118 } 11119 11120 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 11121 The result of the shift is RESULT_MODE. If we cannot simplify it, 11122 return X or, if it is NULL, synthesize the expression with 11123 simplify_gen_binary. Otherwise, return a simplified value. 11124 11125 The shift is normally computed in the widest mode we find in VAROP, as 11126 long as it isn't a different number of words than RESULT_MODE. Exceptions 11127 are ASHIFTRT and ROTATE, which are always done in their original mode. */ 11128 11129 static rtx 11130 simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode, 11131 rtx varop, int count) 11132 { 11133 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count); 11134 if (tem) 11135 return tem; 11136 11137 if (!x) 11138 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count)); 11139 if (GET_MODE (x) != result_mode) 11140 x = gen_lowpart (result_mode, x); 11141 return x; 11142 } 11143 11144 11145 /* A subroutine of recog_for_combine. See there for arguments and 11146 return value. */ 11147 11148 static int 11149 recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) 11150 { 11151 rtx pat = *pnewpat; 11152 rtx pat_without_clobbers; 11153 int insn_code_number; 11154 int num_clobbers_to_add = 0; 11155 int i; 11156 rtx notes = NULL_RTX; 11157 rtx old_notes, old_pat; 11158 int old_icode; 11159 11160 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER 11161 we use to indicate that something didn't match. If we find such a 11162 thing, force rejection. */ 11163 if (GET_CODE (pat) == PARALLEL) 11164 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 11165 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER 11166 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 11167 return -1; 11168 11169 old_pat = PATTERN (insn); 11170 old_notes = REG_NOTES (insn); 11171 PATTERN (insn) = pat; 11172 REG_NOTES (insn) = NULL_RTX; 11173 11174 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 11175 if (dump_file && (dump_flags & TDF_DETAILS)) 11176 { 11177 if (insn_code_number < 0) 11178 fputs ("Failed to match this instruction:\n", dump_file); 11179 else 11180 fputs ("Successfully matched this instruction:\n", dump_file); 11181 print_rtl_single (dump_file, pat); 11182 } 11183 11184 /* If it isn't, there is the possibility that we previously had an insn 11185 that clobbered some register as a side effect, but the combined 11186 insn doesn't need to do that. So try once more without the clobbers 11187 unless this represents an ASM insn. */ 11188 11189 if (insn_code_number < 0 && ! check_asm_operands (pat) 11190 && GET_CODE (pat) == PARALLEL) 11191 { 11192 int pos; 11193 11194 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) 11195 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 11196 { 11197 if (i != pos) 11198 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); 11199 pos++; 11200 } 11201 11202 SUBST_INT (XVECLEN (pat, 0), pos); 11203 11204 if (pos == 1) 11205 pat = XVECEXP (pat, 0, 0); 11206 11207 PATTERN (insn) = pat; 11208 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 11209 if (dump_file && (dump_flags & TDF_DETAILS)) 11210 { 11211 if (insn_code_number < 0) 11212 fputs ("Failed to match this instruction:\n", dump_file); 11213 else 11214 fputs ("Successfully matched this instruction:\n", dump_file); 11215 print_rtl_single (dump_file, pat); 11216 } 11217 } 11218 11219 pat_without_clobbers = pat; 11220 11221 PATTERN (insn) = old_pat; 11222 REG_NOTES (insn) = old_notes; 11223 11224 /* Recognize all noop sets, these will be killed by followup pass. */ 11225 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) 11226 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; 11227 11228 /* If we had any clobbers to add, make a new pattern than contains 11229 them. Then check to make sure that all of them are dead. */ 11230 if (num_clobbers_to_add) 11231 { 11232 rtx newpat = gen_rtx_PARALLEL (VOIDmode, 11233 rtvec_alloc (GET_CODE (pat) == PARALLEL 11234 ? (XVECLEN (pat, 0) 11235 + num_clobbers_to_add) 11236 : num_clobbers_to_add + 1)); 11237 11238 if (GET_CODE (pat) == PARALLEL) 11239 for (i = 0; i < XVECLEN (pat, 0); i++) 11240 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); 11241 else 11242 XVECEXP (newpat, 0, 0) = pat; 11243 11244 add_clobbers (newpat, insn_code_number); 11245 11246 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; 11247 i < XVECLEN (newpat, 0); i++) 11248 { 11249 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)) 11250 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) 11251 return -1; 11252 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH) 11253 { 11254 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))); 11255 notes = alloc_reg_note (REG_UNUSED, 11256 XEXP (XVECEXP (newpat, 0, i), 0), notes); 11257 } 11258 } 11259 pat = newpat; 11260 } 11261 11262 if (insn_code_number >= 0 11263 && insn_code_number != NOOP_MOVE_INSN_CODE) 11264 { 11265 old_pat = PATTERN (insn); 11266 old_notes = REG_NOTES (insn); 11267 old_icode = INSN_CODE (insn); 11268 PATTERN (insn) = pat; 11269 REG_NOTES (insn) = notes; 11270 INSN_CODE (insn) = insn_code_number; 11271 11272 /* Allow targets to reject combined insn. */ 11273 if (!targetm.legitimate_combined_insn (insn)) 11274 { 11275 if (dump_file && (dump_flags & TDF_DETAILS)) 11276 fputs ("Instruction not appropriate for target.", 11277 dump_file); 11278 11279 /* Callers expect recog_for_combine to strip 11280 clobbers from the pattern on failure. */ 11281 pat = pat_without_clobbers; 11282 notes = NULL_RTX; 11283 11284 insn_code_number = -1; 11285 } 11286 11287 PATTERN (insn) = old_pat; 11288 REG_NOTES (insn) = old_notes; 11289 INSN_CODE (insn) = old_icode; 11290 } 11291 11292 *pnewpat = pat; 11293 *pnotes = notes; 11294 11295 return insn_code_number; 11296 } 11297 11298 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be 11299 expressed as an AND and maybe an LSHIFTRT, to that formulation. 11300 Return whether anything was so changed. */ 11301 11302 static bool 11303 change_zero_ext (rtx pat) 11304 { 11305 bool changed = false; 11306 rtx *src = &SET_SRC (pat); 11307 11308 subrtx_ptr_iterator::array_type array; 11309 FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST) 11310 { 11311 rtx x = **iter; 11312 machine_mode mode = GET_MODE (x); 11313 int size; 11314 11315 if (GET_CODE (x) == ZERO_EXTRACT 11316 && CONST_INT_P (XEXP (x, 1)) 11317 && CONST_INT_P (XEXP (x, 2)) 11318 && GET_MODE (XEXP (x, 0)) != VOIDmode 11319 && GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) 11320 <= GET_MODE_PRECISION (mode)) 11321 { 11322 machine_mode inner_mode = GET_MODE (XEXP (x, 0)); 11323 11324 size = INTVAL (XEXP (x, 1)); 11325 11326 int start = INTVAL (XEXP (x, 2)); 11327 if (BITS_BIG_ENDIAN) 11328 start = GET_MODE_PRECISION (inner_mode) - size - start; 11329 11330 if (start) 11331 x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0), GEN_INT (start)); 11332 else 11333 x = XEXP (x, 0); 11334 11335 if (mode != inner_mode) 11336 { 11337 if (REG_P (x) && HARD_REGISTER_P (x) 11338 && !can_change_dest_mode (x, 0, mode)) 11339 continue; 11340 11341 x = gen_lowpart_SUBREG (mode, x); 11342 } 11343 } 11344 else if (GET_CODE (x) == ZERO_EXTEND 11345 && SCALAR_INT_MODE_P (mode) 11346 && GET_CODE (XEXP (x, 0)) == SUBREG 11347 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0)))) 11348 && !paradoxical_subreg_p (XEXP (x, 0)) 11349 && subreg_lowpart_p (XEXP (x, 0))) 11350 { 11351 size = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))); 11352 x = SUBREG_REG (XEXP (x, 0)); 11353 if (GET_MODE (x) != mode) 11354 { 11355 if (REG_P (x) && HARD_REGISTER_P (x) 11356 && !can_change_dest_mode (x, 0, mode)) 11357 continue; 11358 11359 x = gen_lowpart_SUBREG (mode, x); 11360 } 11361 } 11362 else if (GET_CODE (x) == ZERO_EXTEND 11363 && SCALAR_INT_MODE_P (mode) 11364 && REG_P (XEXP (x, 0)) 11365 && HARD_REGISTER_P (XEXP (x, 0)) 11366 && can_change_dest_mode (XEXP (x, 0), 0, mode)) 11367 { 11368 size = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))); 11369 x = gen_rtx_REG (mode, REGNO (XEXP (x, 0))); 11370 } 11371 else 11372 continue; 11373 11374 if (!(GET_CODE (x) == LSHIFTRT 11375 && CONST_INT_P (XEXP (x, 1)) 11376 && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode))) 11377 { 11378 wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode)); 11379 x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode)); 11380 } 11381 11382 SUBST (**iter, x); 11383 changed = true; 11384 } 11385 11386 if (changed) 11387 FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST) 11388 maybe_swap_commutative_operands (**iter); 11389 11390 rtx *dst = &SET_DEST (pat); 11391 if (GET_CODE (*dst) == ZERO_EXTRACT 11392 && REG_P (XEXP (*dst, 0)) 11393 && CONST_INT_P (XEXP (*dst, 1)) 11394 && CONST_INT_P (XEXP (*dst, 2))) 11395 { 11396 rtx reg = XEXP (*dst, 0); 11397 int width = INTVAL (XEXP (*dst, 1)); 11398 int offset = INTVAL (XEXP (*dst, 2)); 11399 machine_mode mode = GET_MODE (reg); 11400 int reg_width = GET_MODE_PRECISION (mode); 11401 if (BITS_BIG_ENDIAN) 11402 offset = reg_width - width - offset; 11403 11404 rtx x, y, z, w; 11405 wide_int mask = wi::shifted_mask (offset, width, true, reg_width); 11406 wide_int mask2 = wi::shifted_mask (offset, width, false, reg_width); 11407 x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode)); 11408 if (offset) 11409 y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset)); 11410 else 11411 y = SET_SRC (pat); 11412 z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode)); 11413 w = gen_rtx_IOR (mode, x, z); 11414 SUBST (SET_DEST (pat), reg); 11415 SUBST (SET_SRC (pat), w); 11416 11417 changed = true; 11418 } 11419 11420 return changed; 11421 } 11422 11423 /* Like recog, but we receive the address of a pointer to a new pattern. 11424 We try to match the rtx that the pointer points to. 11425 If that fails, we may try to modify or replace the pattern, 11426 storing the replacement into the same pointer object. 11427 11428 Modifications include deletion or addition of CLOBBERs. If the 11429 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT 11430 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that 11431 (and undo if that fails). 11432 11433 PNOTES is a pointer to a location where any REG_UNUSED notes added for 11434 the CLOBBERs are placed. 11435 11436 The value is the final insn code from the pattern ultimately matched, 11437 or -1. */ 11438 11439 static int 11440 recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) 11441 { 11442 rtx pat = *pnewpat; 11443 int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes); 11444 if (insn_code_number >= 0 || check_asm_operands (pat)) 11445 return insn_code_number; 11446 11447 void *marker = get_undo_marker (); 11448 bool changed = false; 11449 11450 if (GET_CODE (pat) == SET) 11451 changed = change_zero_ext (pat); 11452 else if (GET_CODE (pat) == PARALLEL) 11453 { 11454 int i; 11455 for (i = 0; i < XVECLEN (pat, 0); i++) 11456 { 11457 rtx set = XVECEXP (pat, 0, i); 11458 if (GET_CODE (set) == SET) 11459 changed |= change_zero_ext (set); 11460 } 11461 } 11462 11463 if (changed) 11464 { 11465 insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes); 11466 11467 if (insn_code_number < 0) 11468 undo_to_marker (marker); 11469 } 11470 11471 return insn_code_number; 11472 } 11473 11474 /* Like gen_lowpart_general but for use by combine. In combine it 11475 is not possible to create any new pseudoregs. However, it is 11476 safe to create invalid memory addresses, because combine will 11477 try to recognize them and all they will do is make the combine 11478 attempt fail. 11479 11480 If for some reason this cannot do its job, an rtx 11481 (clobber (const_int 0)) is returned. 11482 An insn containing that will not be recognized. */ 11483 11484 static rtx 11485 gen_lowpart_for_combine (machine_mode omode, rtx x) 11486 { 11487 machine_mode imode = GET_MODE (x); 11488 unsigned int osize = GET_MODE_SIZE (omode); 11489 unsigned int isize = GET_MODE_SIZE (imode); 11490 rtx result; 11491 11492 if (omode == imode) 11493 return x; 11494 11495 /* We can only support MODE being wider than a word if X is a 11496 constant integer or has a mode the same size. */ 11497 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD 11498 && ! (CONST_SCALAR_INT_P (x) || isize == osize)) 11499 goto fail; 11500 11501 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart 11502 won't know what to do. So we will strip off the SUBREG here and 11503 process normally. */ 11504 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) 11505 { 11506 x = SUBREG_REG (x); 11507 11508 /* For use in case we fall down into the address adjustments 11509 further below, we need to adjust the known mode and size of 11510 x; imode and isize, since we just adjusted x. */ 11511 imode = GET_MODE (x); 11512 11513 if (imode == omode) 11514 return x; 11515 11516 isize = GET_MODE_SIZE (imode); 11517 } 11518 11519 result = gen_lowpart_common (omode, x); 11520 11521 if (result) 11522 return result; 11523 11524 if (MEM_P (x)) 11525 { 11526 int offset = 0; 11527 11528 /* Refuse to work on a volatile memory ref or one with a mode-dependent 11529 address. */ 11530 if (MEM_VOLATILE_P (x) 11531 || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x))) 11532 goto fail; 11533 11534 /* If we want to refer to something bigger than the original memref, 11535 generate a paradoxical subreg instead. That will force a reload 11536 of the original memref X. */ 11537 if (isize < osize) 11538 return gen_rtx_SUBREG (omode, x, 0); 11539 11540 if (WORDS_BIG_ENDIAN) 11541 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD); 11542 11543 /* Adjust the address so that the address-after-the-data is 11544 unchanged. */ 11545 if (BYTES_BIG_ENDIAN) 11546 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize); 11547 11548 return adjust_address_nv (x, omode, offset); 11549 } 11550 11551 /* If X is a comparison operator, rewrite it in a new mode. This 11552 probably won't match, but may allow further simplifications. */ 11553 else if (COMPARISON_P (x)) 11554 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1)); 11555 11556 /* If we couldn't simplify X any other way, just enclose it in a 11557 SUBREG. Normally, this SUBREG won't match, but some patterns may 11558 include an explicit SUBREG or we may simplify it further in combine. */ 11559 else 11560 { 11561 rtx res; 11562 11563 if (imode == VOIDmode) 11564 { 11565 imode = int_mode_for_mode (omode); 11566 x = gen_lowpart_common (imode, x); 11567 if (x == NULL) 11568 goto fail; 11569 } 11570 res = lowpart_subreg (omode, x, imode); 11571 if (res) 11572 return res; 11573 } 11574 11575 fail: 11576 return gen_rtx_CLOBBER (omode, const0_rtx); 11577 } 11578 11579 /* Try to simplify a comparison between OP0 and a constant OP1, 11580 where CODE is the comparison code that will be tested, into a 11581 (CODE OP0 const0_rtx) form. 11582 11583 The result is a possibly different comparison code to use. 11584 *POP1 may be updated. */ 11585 11586 static enum rtx_code 11587 simplify_compare_const (enum rtx_code code, machine_mode mode, 11588 rtx op0, rtx *pop1) 11589 { 11590 unsigned int mode_width = GET_MODE_PRECISION (mode); 11591 HOST_WIDE_INT const_op = INTVAL (*pop1); 11592 11593 /* Get the constant we are comparing against and turn off all bits 11594 not on in our mode. */ 11595 if (mode != VOIDmode) 11596 const_op = trunc_int_for_mode (const_op, mode); 11597 11598 /* If we are comparing against a constant power of two and the value 11599 being compared can only have that single bit nonzero (e.g., it was 11600 `and'ed with that bit), we can replace this with a comparison 11601 with zero. */ 11602 if (const_op 11603 && (code == EQ || code == NE || code == GE || code == GEU 11604 || code == LT || code == LTU) 11605 && mode_width - 1 < HOST_BITS_PER_WIDE_INT 11606 && pow2p_hwi (const_op & GET_MODE_MASK (mode)) 11607 && (nonzero_bits (op0, mode) 11608 == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode)))) 11609 { 11610 code = (code == EQ || code == GE || code == GEU ? NE : EQ); 11611 const_op = 0; 11612 } 11613 11614 /* Similarly, if we are comparing a value known to be either -1 or 11615 0 with -1, change it to the opposite comparison against zero. */ 11616 if (const_op == -1 11617 && (code == EQ || code == NE || code == GT || code == LE 11618 || code == GEU || code == LTU) 11619 && num_sign_bit_copies (op0, mode) == mode_width) 11620 { 11621 code = (code == EQ || code == LE || code == GEU ? NE : EQ); 11622 const_op = 0; 11623 } 11624 11625 /* Do some canonicalizations based on the comparison code. We prefer 11626 comparisons against zero and then prefer equality comparisons. 11627 If we can reduce the size of a constant, we will do that too. */ 11628 switch (code) 11629 { 11630 case LT: 11631 /* < C is equivalent to <= (C - 1) */ 11632 if (const_op > 0) 11633 { 11634 const_op -= 1; 11635 code = LE; 11636 /* ... fall through to LE case below. */ 11637 gcc_fallthrough (); 11638 } 11639 else 11640 break; 11641 11642 case LE: 11643 /* <= C is equivalent to < (C + 1); we do this for C < 0 */ 11644 if (const_op < 0) 11645 { 11646 const_op += 1; 11647 code = LT; 11648 } 11649 11650 /* If we are doing a <= 0 comparison on a value known to have 11651 a zero sign bit, we can replace this with == 0. */ 11652 else if (const_op == 0 11653 && mode_width - 1 < HOST_BITS_PER_WIDE_INT 11654 && (nonzero_bits (op0, mode) 11655 & (HOST_WIDE_INT_1U << (mode_width - 1))) 11656 == 0) 11657 code = EQ; 11658 break; 11659 11660 case GE: 11661 /* >= C is equivalent to > (C - 1). */ 11662 if (const_op > 0) 11663 { 11664 const_op -= 1; 11665 code = GT; 11666 /* ... fall through to GT below. */ 11667 gcc_fallthrough (); 11668 } 11669 else 11670 break; 11671 11672 case GT: 11673 /* > C is equivalent to >= (C + 1); we do this for C < 0. */ 11674 if (const_op < 0) 11675 { 11676 const_op += 1; 11677 code = GE; 11678 } 11679 11680 /* If we are doing a > 0 comparison on a value known to have 11681 a zero sign bit, we can replace this with != 0. */ 11682 else if (const_op == 0 11683 && mode_width - 1 < HOST_BITS_PER_WIDE_INT 11684 && (nonzero_bits (op0, mode) 11685 & (HOST_WIDE_INT_1U << (mode_width - 1))) 11686 == 0) 11687 code = NE; 11688 break; 11689 11690 case LTU: 11691 /* < C is equivalent to <= (C - 1). */ 11692 if (const_op > 0) 11693 { 11694 const_op -= 1; 11695 code = LEU; 11696 /* ... fall through ... */ 11697 } 11698 /* (unsigned) < 0x80000000 is equivalent to >= 0. */ 11699 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT 11700 && (unsigned HOST_WIDE_INT) const_op 11701 == HOST_WIDE_INT_1U << (mode_width - 1)) 11702 { 11703 const_op = 0; 11704 code = GE; 11705 break; 11706 } 11707 else 11708 break; 11709 11710 case LEU: 11711 /* unsigned <= 0 is equivalent to == 0 */ 11712 if (const_op == 0) 11713 code = EQ; 11714 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ 11715 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT 11716 && (unsigned HOST_WIDE_INT) const_op 11717 == (HOST_WIDE_INT_1U << (mode_width - 1)) - 1) 11718 { 11719 const_op = 0; 11720 code = GE; 11721 } 11722 break; 11723 11724 case GEU: 11725 /* >= C is equivalent to > (C - 1). */ 11726 if (const_op > 1) 11727 { 11728 const_op -= 1; 11729 code = GTU; 11730 /* ... fall through ... */ 11731 } 11732 11733 /* (unsigned) >= 0x80000000 is equivalent to < 0. */ 11734 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT 11735 && (unsigned HOST_WIDE_INT) const_op 11736 == HOST_WIDE_INT_1U << (mode_width - 1)) 11737 { 11738 const_op = 0; 11739 code = LT; 11740 break; 11741 } 11742 else 11743 break; 11744 11745 case GTU: 11746 /* unsigned > 0 is equivalent to != 0 */ 11747 if (const_op == 0) 11748 code = NE; 11749 /* (unsigned) > 0x7fffffff is equivalent to < 0. */ 11750 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT 11751 && (unsigned HOST_WIDE_INT) const_op 11752 == (HOST_WIDE_INT_1U << (mode_width - 1)) - 1) 11753 { 11754 const_op = 0; 11755 code = LT; 11756 } 11757 break; 11758 11759 default: 11760 break; 11761 } 11762 11763 *pop1 = GEN_INT (const_op); 11764 return code; 11765 } 11766 11767 /* Simplify a comparison between *POP0 and *POP1 where CODE is the 11768 comparison code that will be tested. 11769 11770 The result is a possibly different comparison code to use. *POP0 and 11771 *POP1 may be updated. 11772 11773 It is possible that we might detect that a comparison is either always 11774 true or always false. However, we do not perform general constant 11775 folding in combine, so this knowledge isn't useful. Such tautologies 11776 should have been detected earlier. Hence we ignore all such cases. */ 11777 11778 static enum rtx_code 11779 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) 11780 { 11781 rtx op0 = *pop0; 11782 rtx op1 = *pop1; 11783 rtx tem, tem1; 11784 int i; 11785 machine_mode mode, tmode; 11786 11787 /* Try a few ways of applying the same transformation to both operands. */ 11788 while (1) 11789 { 11790 /* The test below this one won't handle SIGN_EXTENDs on these machines, 11791 so check specially. */ 11792 if (!WORD_REGISTER_OPERATIONS 11793 && code != GTU && code != GEU && code != LTU && code != LEU 11794 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT 11795 && GET_CODE (XEXP (op0, 0)) == ASHIFT 11796 && GET_CODE (XEXP (op1, 0)) == ASHIFT 11797 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG 11798 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG 11799 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) 11800 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) 11801 && CONST_INT_P (XEXP (op0, 1)) 11802 && XEXP (op0, 1) == XEXP (op1, 1) 11803 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 11804 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1) 11805 && (INTVAL (XEXP (op0, 1)) 11806 == (GET_MODE_PRECISION (GET_MODE (op0)) 11807 - (GET_MODE_PRECISION 11808 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) 11809 { 11810 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); 11811 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); 11812 } 11813 11814 /* If both operands are the same constant shift, see if we can ignore the 11815 shift. We can if the shift is a rotate or if the bits shifted out of 11816 this shift are known to be zero for both inputs and if the type of 11817 comparison is compatible with the shift. */ 11818 if (GET_CODE (op0) == GET_CODE (op1) 11819 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0)) 11820 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) 11821 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) 11822 && (code != GT && code != LT && code != GE && code != LE)) 11823 || (GET_CODE (op0) == ASHIFTRT 11824 && (code != GTU && code != LTU 11825 && code != GEU && code != LEU))) 11826 && CONST_INT_P (XEXP (op0, 1)) 11827 && INTVAL (XEXP (op0, 1)) >= 0 11828 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 11829 && XEXP (op0, 1) == XEXP (op1, 1)) 11830 { 11831 machine_mode mode = GET_MODE (op0); 11832 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 11833 int shift_count = INTVAL (XEXP (op0, 1)); 11834 11835 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) 11836 mask &= (mask >> shift_count) << shift_count; 11837 else if (GET_CODE (op0) == ASHIFT) 11838 mask = (mask & (mask << shift_count)) >> shift_count; 11839 11840 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 11841 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) 11842 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); 11843 else 11844 break; 11845 } 11846 11847 /* If both operands are AND's of a paradoxical SUBREG by constant, the 11848 SUBREGs are of the same mode, and, in both cases, the AND would 11849 be redundant if the comparison was done in the narrower mode, 11850 do the comparison in the narrower mode (e.g., we are AND'ing with 1 11851 and the operand's possibly nonzero bits are 0xffffff01; in that case 11852 if we only care about QImode, we don't need the AND). This case 11853 occurs if the output mode of an scc insn is not SImode and 11854 STORE_FLAG_VALUE == 1 (e.g., the 386). 11855 11856 Similarly, check for a case where the AND's are ZERO_EXTEND 11857 operations from some narrower mode even though a SUBREG is not 11858 present. */ 11859 11860 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND 11861 && CONST_INT_P (XEXP (op0, 1)) 11862 && CONST_INT_P (XEXP (op1, 1))) 11863 { 11864 rtx inner_op0 = XEXP (op0, 0); 11865 rtx inner_op1 = XEXP (op1, 0); 11866 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); 11867 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); 11868 int changed = 0; 11869 11870 if (paradoxical_subreg_p (inner_op0) 11871 && GET_CODE (inner_op1) == SUBREG 11872 && (GET_MODE (SUBREG_REG (inner_op0)) 11873 == GET_MODE (SUBREG_REG (inner_op1))) 11874 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0))) 11875 <= HOST_BITS_PER_WIDE_INT) 11876 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), 11877 GET_MODE (SUBREG_REG (inner_op0))))) 11878 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), 11879 GET_MODE (SUBREG_REG (inner_op1)))))) 11880 { 11881 op0 = SUBREG_REG (inner_op0); 11882 op1 = SUBREG_REG (inner_op1); 11883 11884 /* The resulting comparison is always unsigned since we masked 11885 off the original sign bit. */ 11886 code = unsigned_condition (code); 11887 11888 changed = 1; 11889 } 11890 11891 else if (c0 == c1) 11892 for (tmode = GET_CLASS_NARROWEST_MODE 11893 (GET_MODE_CLASS (GET_MODE (op0))); 11894 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) 11895 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) 11896 { 11897 op0 = gen_lowpart_or_truncate (tmode, inner_op0); 11898 op1 = gen_lowpart_or_truncate (tmode, inner_op1); 11899 code = unsigned_condition (code); 11900 changed = 1; 11901 break; 11902 } 11903 11904 if (! changed) 11905 break; 11906 } 11907 11908 /* If both operands are NOT, we can strip off the outer operation 11909 and adjust the comparison code for swapped operands; similarly for 11910 NEG, except that this must be an equality comparison. */ 11911 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) 11912 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG 11913 && (code == EQ || code == NE))) 11914 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); 11915 11916 else 11917 break; 11918 } 11919 11920 /* If the first operand is a constant, swap the operands and adjust the 11921 comparison code appropriately, but don't do this if the second operand 11922 is already a constant integer. */ 11923 if (swap_commutative_operands_p (op0, op1)) 11924 { 11925 std::swap (op0, op1); 11926 code = swap_condition (code); 11927 } 11928 11929 /* We now enter a loop during which we will try to simplify the comparison. 11930 For the most part, we only are concerned with comparisons with zero, 11931 but some things may really be comparisons with zero but not start 11932 out looking that way. */ 11933 11934 while (CONST_INT_P (op1)) 11935 { 11936 machine_mode mode = GET_MODE (op0); 11937 unsigned int mode_width = GET_MODE_PRECISION (mode); 11938 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 11939 int equality_comparison_p; 11940 int sign_bit_comparison_p; 11941 int unsigned_comparison_p; 11942 HOST_WIDE_INT const_op; 11943 11944 /* We only want to handle integral modes. This catches VOIDmode, 11945 CCmode, and the floating-point modes. An exception is that we 11946 can handle VOIDmode if OP0 is a COMPARE or a comparison 11947 operation. */ 11948 11949 if (GET_MODE_CLASS (mode) != MODE_INT 11950 && ! (mode == VOIDmode 11951 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0)))) 11952 break; 11953 11954 /* Try to simplify the compare to constant, possibly changing the 11955 comparison op, and/or changing op1 to zero. */ 11956 code = simplify_compare_const (code, mode, op0, &op1); 11957 const_op = INTVAL (op1); 11958 11959 /* Compute some predicates to simplify code below. */ 11960 11961 equality_comparison_p = (code == EQ || code == NE); 11962 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); 11963 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU 11964 || code == GEU); 11965 11966 /* If this is a sign bit comparison and we can do arithmetic in 11967 MODE, say that we will only be needing the sign bit of OP0. */ 11968 if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode)) 11969 op0 = force_to_mode (op0, mode, 11970 HOST_WIDE_INT_1U 11971 << (GET_MODE_PRECISION (mode) - 1), 11972 0); 11973 11974 /* Now try cases based on the opcode of OP0. If none of the cases 11975 does a "continue", we exit this loop immediately after the 11976 switch. */ 11977 11978 switch (GET_CODE (op0)) 11979 { 11980 case ZERO_EXTRACT: 11981 /* If we are extracting a single bit from a variable position in 11982 a constant that has only a single bit set and are comparing it 11983 with zero, we can convert this into an equality comparison 11984 between the position and the location of the single bit. */ 11985 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might 11986 have already reduced the shift count modulo the word size. */ 11987 if (!SHIFT_COUNT_TRUNCATED 11988 && CONST_INT_P (XEXP (op0, 0)) 11989 && XEXP (op0, 1) == const1_rtx 11990 && equality_comparison_p && const_op == 0 11991 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0) 11992 { 11993 if (BITS_BIG_ENDIAN) 11994 i = BITS_PER_WORD - 1 - i; 11995 11996 op0 = XEXP (op0, 2); 11997 op1 = GEN_INT (i); 11998 const_op = i; 11999 12000 /* Result is nonzero iff shift count is equal to I. */ 12001 code = reverse_condition (code); 12002 continue; 12003 } 12004 12005 /* fall through */ 12006 12007 case SIGN_EXTRACT: 12008 tem = expand_compound_operation (op0); 12009 if (tem != op0) 12010 { 12011 op0 = tem; 12012 continue; 12013 } 12014 break; 12015 12016 case NOT: 12017 /* If testing for equality, we can take the NOT of the constant. */ 12018 if (equality_comparison_p 12019 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) 12020 { 12021 op0 = XEXP (op0, 0); 12022 op1 = tem; 12023 continue; 12024 } 12025 12026 /* If just looking at the sign bit, reverse the sense of the 12027 comparison. */ 12028 if (sign_bit_comparison_p) 12029 { 12030 op0 = XEXP (op0, 0); 12031 code = (code == GE ? LT : GE); 12032 continue; 12033 } 12034 break; 12035 12036 case NEG: 12037 /* If testing for equality, we can take the NEG of the constant. */ 12038 if (equality_comparison_p 12039 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) 12040 { 12041 op0 = XEXP (op0, 0); 12042 op1 = tem; 12043 continue; 12044 } 12045 12046 /* The remaining cases only apply to comparisons with zero. */ 12047 if (const_op != 0) 12048 break; 12049 12050 /* When X is ABS or is known positive, 12051 (neg X) is < 0 if and only if X != 0. */ 12052 12053 if (sign_bit_comparison_p 12054 && (GET_CODE (XEXP (op0, 0)) == ABS 12055 || (mode_width <= HOST_BITS_PER_WIDE_INT 12056 && (nonzero_bits (XEXP (op0, 0), mode) 12057 & (HOST_WIDE_INT_1U << (mode_width - 1))) 12058 == 0))) 12059 { 12060 op0 = XEXP (op0, 0); 12061 code = (code == LT ? NE : EQ); 12062 continue; 12063 } 12064 12065 /* If we have NEG of something whose two high-order bits are the 12066 same, we know that "(-a) < 0" is equivalent to "a > 0". */ 12067 if (num_sign_bit_copies (op0, mode) >= 2) 12068 { 12069 op0 = XEXP (op0, 0); 12070 code = swap_condition (code); 12071 continue; 12072 } 12073 break; 12074 12075 case ROTATE: 12076 /* If we are testing equality and our count is a constant, we 12077 can perform the inverse operation on our RHS. */ 12078 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1)) 12079 && (tem = simplify_binary_operation (ROTATERT, mode, 12080 op1, XEXP (op0, 1))) != 0) 12081 { 12082 op0 = XEXP (op0, 0); 12083 op1 = tem; 12084 continue; 12085 } 12086 12087 /* If we are doing a < 0 or >= 0 comparison, it means we are testing 12088 a particular bit. Convert it to an AND of a constant of that 12089 bit. This will be converted into a ZERO_EXTRACT. */ 12090 if (const_op == 0 && sign_bit_comparison_p 12091 && CONST_INT_P (XEXP (op0, 1)) 12092 && mode_width <= HOST_BITS_PER_WIDE_INT) 12093 { 12094 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 12095 (HOST_WIDE_INT_1U 12096 << (mode_width - 1 12097 - INTVAL (XEXP (op0, 1))))); 12098 code = (code == LT ? NE : EQ); 12099 continue; 12100 } 12101 12102 /* Fall through. */ 12103 12104 case ABS: 12105 /* ABS is ignorable inside an equality comparison with zero. */ 12106 if (const_op == 0 && equality_comparison_p) 12107 { 12108 op0 = XEXP (op0, 0); 12109 continue; 12110 } 12111 break; 12112 12113 case SIGN_EXTEND: 12114 /* Can simplify (compare (zero/sign_extend FOO) CONST) to 12115 (compare FOO CONST) if CONST fits in FOO's mode and we 12116 are either testing inequality or have an unsigned 12117 comparison with ZERO_EXTEND or a signed comparison with 12118 SIGN_EXTEND. But don't do it if we don't have a compare 12119 insn of the given mode, since we'd have to revert it 12120 later on, and then we wouldn't know whether to sign- or 12121 zero-extend. */ 12122 mode = GET_MODE (XEXP (op0, 0)); 12123 if (GET_MODE_CLASS (mode) == MODE_INT 12124 && ! unsigned_comparison_p 12125 && HWI_COMPUTABLE_MODE_P (mode) 12126 && trunc_int_for_mode (const_op, mode) == const_op 12127 && have_insn_for (COMPARE, mode)) 12128 { 12129 op0 = XEXP (op0, 0); 12130 continue; 12131 } 12132 break; 12133 12134 case SUBREG: 12135 /* Check for the case where we are comparing A - C1 with C2, that is 12136 12137 (subreg:MODE (plus (A) (-C1))) op (C2) 12138 12139 with C1 a constant, and try to lift the SUBREG, i.e. to do the 12140 comparison in the wider mode. One of the following two conditions 12141 must be true in order for this to be valid: 12142 12143 1. The mode extension results in the same bit pattern being added 12144 on both sides and the comparison is equality or unsigned. As 12145 C2 has been truncated to fit in MODE, the pattern can only be 12146 all 0s or all 1s. 12147 12148 2. The mode extension results in the sign bit being copied on 12149 each side. 12150 12151 The difficulty here is that we have predicates for A but not for 12152 (A - C1) so we need to check that C1 is within proper bounds so 12153 as to perturbate A as little as possible. */ 12154 12155 if (mode_width <= HOST_BITS_PER_WIDE_INT 12156 && subreg_lowpart_p (op0) 12157 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width 12158 && GET_CODE (SUBREG_REG (op0)) == PLUS 12159 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1))) 12160 { 12161 machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); 12162 rtx a = XEXP (SUBREG_REG (op0), 0); 12163 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1)); 12164 12165 if ((c1 > 0 12166 && (unsigned HOST_WIDE_INT) c1 12167 < HOST_WIDE_INT_1U << (mode_width - 1) 12168 && (equality_comparison_p || unsigned_comparison_p) 12169 /* (A - C1) zero-extends if it is positive and sign-extends 12170 if it is negative, C2 both zero- and sign-extends. */ 12171 && ((0 == (nonzero_bits (a, inner_mode) 12172 & ~GET_MODE_MASK (mode)) 12173 && const_op >= 0) 12174 /* (A - C1) sign-extends if it is positive and 1-extends 12175 if it is negative, C2 both sign- and 1-extends. */ 12176 || (num_sign_bit_copies (a, inner_mode) 12177 > (unsigned int) (GET_MODE_PRECISION (inner_mode) 12178 - mode_width) 12179 && const_op < 0))) 12180 || ((unsigned HOST_WIDE_INT) c1 12181 < HOST_WIDE_INT_1U << (mode_width - 2) 12182 /* (A - C1) always sign-extends, like C2. */ 12183 && num_sign_bit_copies (a, inner_mode) 12184 > (unsigned int) (GET_MODE_PRECISION (inner_mode) 12185 - (mode_width - 1)))) 12186 { 12187 op0 = SUBREG_REG (op0); 12188 continue; 12189 } 12190 } 12191 12192 /* If the inner mode is narrower and we are extracting the low part, 12193 we can treat the SUBREG as if it were a ZERO_EXTEND. */ 12194 if (subreg_lowpart_p (op0) 12195 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width) 12196 ; 12197 else if (subreg_lowpart_p (op0) 12198 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 12199 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT 12200 && (code == NE || code == EQ) 12201 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) 12202 <= HOST_BITS_PER_WIDE_INT) 12203 && !paradoxical_subreg_p (op0) 12204 && (nonzero_bits (SUBREG_REG (op0), 12205 GET_MODE (SUBREG_REG (op0))) 12206 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 12207 { 12208 /* Remove outer subregs that don't do anything. */ 12209 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1); 12210 12211 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) 12212 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 12213 { 12214 op0 = SUBREG_REG (op0); 12215 op1 = tem; 12216 continue; 12217 } 12218 break; 12219 } 12220 else 12221 break; 12222 12223 /* FALLTHROUGH */ 12224 12225 case ZERO_EXTEND: 12226 mode = GET_MODE (XEXP (op0, 0)); 12227 if (GET_MODE_CLASS (mode) == MODE_INT 12228 && (unsigned_comparison_p || equality_comparison_p) 12229 && HWI_COMPUTABLE_MODE_P (mode) 12230 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode) 12231 && const_op >= 0 12232 && have_insn_for (COMPARE, mode)) 12233 { 12234 op0 = XEXP (op0, 0); 12235 continue; 12236 } 12237 break; 12238 12239 case PLUS: 12240 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do 12241 this for equality comparisons due to pathological cases involving 12242 overflows. */ 12243 if (equality_comparison_p 12244 && 0 != (tem = simplify_binary_operation (MINUS, mode, 12245 op1, XEXP (op0, 1)))) 12246 { 12247 op0 = XEXP (op0, 0); 12248 op1 = tem; 12249 continue; 12250 } 12251 12252 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ 12253 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx 12254 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) 12255 { 12256 op0 = XEXP (XEXP (op0, 0), 0); 12257 code = (code == LT ? EQ : NE); 12258 continue; 12259 } 12260 break; 12261 12262 case MINUS: 12263 /* We used to optimize signed comparisons against zero, but that 12264 was incorrect. Unsigned comparisons against zero (GTU, LEU) 12265 arrive here as equality comparisons, or (GEU, LTU) are 12266 optimized away. No need to special-case them. */ 12267 12268 /* (eq (minus A B) C) -> (eq A (plus B C)) or 12269 (eq B (minus A C)), whichever simplifies. We can only do 12270 this for equality comparisons due to pathological cases involving 12271 overflows. */ 12272 if (equality_comparison_p 12273 && 0 != (tem = simplify_binary_operation (PLUS, mode, 12274 XEXP (op0, 1), op1))) 12275 { 12276 op0 = XEXP (op0, 0); 12277 op1 = tem; 12278 continue; 12279 } 12280 12281 if (equality_comparison_p 12282 && 0 != (tem = simplify_binary_operation (MINUS, mode, 12283 XEXP (op0, 0), op1))) 12284 { 12285 op0 = XEXP (op0, 1); 12286 op1 = tem; 12287 continue; 12288 } 12289 12290 /* The sign bit of (minus (ashiftrt X C) X), where C is the number 12291 of bits in X minus 1, is one iff X > 0. */ 12292 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT 12293 && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) 12294 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 12295 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 12296 { 12297 op0 = XEXP (op0, 1); 12298 code = (code == GE ? LE : GT); 12299 continue; 12300 } 12301 break; 12302 12303 case XOR: 12304 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification 12305 if C is zero or B is a constant. */ 12306 if (equality_comparison_p 12307 && 0 != (tem = simplify_binary_operation (XOR, mode, 12308 XEXP (op0, 1), op1))) 12309 { 12310 op0 = XEXP (op0, 0); 12311 op1 = tem; 12312 continue; 12313 } 12314 break; 12315 12316 case EQ: case NE: 12317 case UNEQ: case LTGT: 12318 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: 12319 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: 12320 case UNORDERED: case ORDERED: 12321 /* We can't do anything if OP0 is a condition code value, rather 12322 than an actual data value. */ 12323 if (const_op != 0 12324 || CC0_P (XEXP (op0, 0)) 12325 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) 12326 break; 12327 12328 /* Get the two operands being compared. */ 12329 if (GET_CODE (XEXP (op0, 0)) == COMPARE) 12330 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); 12331 else 12332 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); 12333 12334 /* Check for the cases where we simply want the result of the 12335 earlier test or the opposite of that result. */ 12336 if (code == NE || code == EQ 12337 || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE) 12338 && (code == LT || code == GE))) 12339 { 12340 enum rtx_code new_code; 12341 if (code == LT || code == NE) 12342 new_code = GET_CODE (op0); 12343 else 12344 new_code = reversed_comparison_code (op0, NULL); 12345 12346 if (new_code != UNKNOWN) 12347 { 12348 code = new_code; 12349 op0 = tem; 12350 op1 = tem1; 12351 continue; 12352 } 12353 } 12354 break; 12355 12356 case IOR: 12357 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero 12358 iff X <= 0. */ 12359 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS 12360 && XEXP (XEXP (op0, 0), 1) == constm1_rtx 12361 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 12362 { 12363 op0 = XEXP (op0, 1); 12364 code = (code == GE ? GT : LE); 12365 continue; 12366 } 12367 break; 12368 12369 case AND: 12370 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This 12371 will be converted to a ZERO_EXTRACT later. */ 12372 if (const_op == 0 && equality_comparison_p 12373 && GET_CODE (XEXP (op0, 0)) == ASHIFT 12374 && XEXP (XEXP (op0, 0), 0) == const1_rtx) 12375 { 12376 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1), 12377 XEXP (XEXP (op0, 0), 1)); 12378 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1); 12379 continue; 12380 } 12381 12382 /* If we are comparing (and (lshiftrt X C1) C2) for equality with 12383 zero and X is a comparison and C1 and C2 describe only bits set 12384 in STORE_FLAG_VALUE, we can compare with X. */ 12385 if (const_op == 0 && equality_comparison_p 12386 && mode_width <= HOST_BITS_PER_WIDE_INT 12387 && CONST_INT_P (XEXP (op0, 1)) 12388 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 12389 && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) 12390 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 12391 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) 12392 { 12393 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 12394 << INTVAL (XEXP (XEXP (op0, 0), 1))); 12395 if ((~STORE_FLAG_VALUE & mask) == 0 12396 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0)) 12397 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 12398 && COMPARISON_P (tem)))) 12399 { 12400 op0 = XEXP (XEXP (op0, 0), 0); 12401 continue; 12402 } 12403 } 12404 12405 /* If we are doing an equality comparison of an AND of a bit equal 12406 to the sign bit, replace this with a LT or GE comparison of 12407 the underlying value. */ 12408 if (equality_comparison_p 12409 && const_op == 0 12410 && CONST_INT_P (XEXP (op0, 1)) 12411 && mode_width <= HOST_BITS_PER_WIDE_INT 12412 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 12413 == HOST_WIDE_INT_1U << (mode_width - 1))) 12414 { 12415 op0 = XEXP (op0, 0); 12416 code = (code == EQ ? GE : LT); 12417 continue; 12418 } 12419 12420 /* If this AND operation is really a ZERO_EXTEND from a narrower 12421 mode, the constant fits within that mode, and this is either an 12422 equality or unsigned comparison, try to do this comparison in 12423 the narrower mode. 12424 12425 Note that in: 12426 12427 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0)) 12428 -> (ne:DI (reg:SI 4) (const_int 0)) 12429 12430 unless TRULY_NOOP_TRUNCATION allows it or the register is 12431 known to hold a value of the required mode the 12432 transformation is invalid. */ 12433 if ((equality_comparison_p || unsigned_comparison_p) 12434 && CONST_INT_P (XEXP (op0, 1)) 12435 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1)) 12436 & GET_MODE_MASK (mode)) 12437 + 1)) >= 0 12438 && const_op >> i == 0 12439 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) 12440 { 12441 op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0)); 12442 continue; 12443 } 12444 12445 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1 12446 fits in both M1 and M2 and the SUBREG is either paradoxical 12447 or represents the low part, permute the SUBREG and the AND 12448 and try again. */ 12449 if (GET_CODE (XEXP (op0, 0)) == SUBREG 12450 && CONST_INT_P (XEXP (op0, 1))) 12451 { 12452 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0))); 12453 unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1)); 12454 /* Require an integral mode, to avoid creating something like 12455 (AND:SF ...). */ 12456 if (SCALAR_INT_MODE_P (tmode) 12457 /* It is unsafe to commute the AND into the SUBREG if the 12458 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is 12459 not defined. As originally written the upper bits 12460 have a defined value due to the AND operation. 12461 However, if we commute the AND inside the SUBREG then 12462 they no longer have defined values and the meaning of 12463 the code has been changed. 12464 Also C1 should not change value in the smaller mode, 12465 see PR67028 (a positive C1 can become negative in the 12466 smaller mode, so that the AND does no longer mask the 12467 upper bits). */ 12468 && ((WORD_REGISTER_OPERATIONS 12469 && mode_width > GET_MODE_PRECISION (tmode) 12470 && mode_width <= BITS_PER_WORD 12471 && trunc_int_for_mode (c1, tmode) == (HOST_WIDE_INT) c1) 12472 || (mode_width <= GET_MODE_PRECISION (tmode) 12473 && subreg_lowpart_p (XEXP (op0, 0)))) 12474 && mode_width <= HOST_BITS_PER_WIDE_INT 12475 && HWI_COMPUTABLE_MODE_P (tmode) 12476 && (c1 & ~mask) == 0 12477 && (c1 & ~GET_MODE_MASK (tmode)) == 0 12478 && c1 != mask 12479 && c1 != GET_MODE_MASK (tmode)) 12480 { 12481 op0 = simplify_gen_binary (AND, tmode, 12482 SUBREG_REG (XEXP (op0, 0)), 12483 gen_int_mode (c1, tmode)); 12484 op0 = gen_lowpart (mode, op0); 12485 continue; 12486 } 12487 } 12488 12489 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */ 12490 if (const_op == 0 && equality_comparison_p 12491 && XEXP (op0, 1) == const1_rtx 12492 && GET_CODE (XEXP (op0, 0)) == NOT) 12493 { 12494 op0 = simplify_and_const_int (NULL_RTX, mode, 12495 XEXP (XEXP (op0, 0), 0), 1); 12496 code = (code == NE ? EQ : NE); 12497 continue; 12498 } 12499 12500 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to 12501 (eq (and (lshiftrt X) 1) 0). 12502 Also handle the case where (not X) is expressed using xor. */ 12503 if (const_op == 0 && equality_comparison_p 12504 && XEXP (op0, 1) == const1_rtx 12505 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT) 12506 { 12507 rtx shift_op = XEXP (XEXP (op0, 0), 0); 12508 rtx shift_count = XEXP (XEXP (op0, 0), 1); 12509 12510 if (GET_CODE (shift_op) == NOT 12511 || (GET_CODE (shift_op) == XOR 12512 && CONST_INT_P (XEXP (shift_op, 1)) 12513 && CONST_INT_P (shift_count) 12514 && HWI_COMPUTABLE_MODE_P (mode) 12515 && (UINTVAL (XEXP (shift_op, 1)) 12516 == HOST_WIDE_INT_1U 12517 << INTVAL (shift_count)))) 12518 { 12519 op0 12520 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count); 12521 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1); 12522 code = (code == NE ? EQ : NE); 12523 continue; 12524 } 12525 } 12526 break; 12527 12528 case ASHIFT: 12529 /* If we have (compare (ashift FOO N) (const_int C)) and 12530 the high order N bits of FOO (N+1 if an inequality comparison) 12531 are known to be zero, we can do this by comparing FOO with C 12532 shifted right N bits so long as the low-order N bits of C are 12533 zero. */ 12534 if (CONST_INT_P (XEXP (op0, 1)) 12535 && INTVAL (XEXP (op0, 1)) >= 0 12536 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) 12537 < HOST_BITS_PER_WIDE_INT) 12538 && (((unsigned HOST_WIDE_INT) const_op 12539 & ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1))) 12540 - 1)) == 0) 12541 && mode_width <= HOST_BITS_PER_WIDE_INT 12542 && (nonzero_bits (XEXP (op0, 0), mode) 12543 & ~(mask >> (INTVAL (XEXP (op0, 1)) 12544 + ! equality_comparison_p))) == 0) 12545 { 12546 /* We must perform a logical shift, not an arithmetic one, 12547 as we want the top N bits of C to be zero. */ 12548 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); 12549 12550 temp >>= INTVAL (XEXP (op0, 1)); 12551 op1 = gen_int_mode (temp, mode); 12552 op0 = XEXP (op0, 0); 12553 continue; 12554 } 12555 12556 /* If we are doing a sign bit comparison, it means we are testing 12557 a particular bit. Convert it to the appropriate AND. */ 12558 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1)) 12559 && mode_width <= HOST_BITS_PER_WIDE_INT) 12560 { 12561 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 12562 (HOST_WIDE_INT_1U 12563 << (mode_width - 1 12564 - INTVAL (XEXP (op0, 1))))); 12565 code = (code == LT ? NE : EQ); 12566 continue; 12567 } 12568 12569 /* If this an equality comparison with zero and we are shifting 12570 the low bit to the sign bit, we can convert this to an AND of the 12571 low-order bit. */ 12572 if (const_op == 0 && equality_comparison_p 12573 && CONST_INT_P (XEXP (op0, 1)) 12574 && UINTVAL (XEXP (op0, 1)) == mode_width - 1) 12575 { 12576 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1); 12577 continue; 12578 } 12579 break; 12580 12581 case ASHIFTRT: 12582 /* If this is an equality comparison with zero, we can do this 12583 as a logical shift, which might be much simpler. */ 12584 if (equality_comparison_p && const_op == 0 12585 && CONST_INT_P (XEXP (op0, 1))) 12586 { 12587 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, 12588 XEXP (op0, 0), 12589 INTVAL (XEXP (op0, 1))); 12590 continue; 12591 } 12592 12593 /* If OP0 is a sign extension and CODE is not an unsigned comparison, 12594 do the comparison in a narrower mode. */ 12595 if (! unsigned_comparison_p 12596 && CONST_INT_P (XEXP (op0, 1)) 12597 && GET_CODE (XEXP (op0, 0)) == ASHIFT 12598 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 12599 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 12600 MODE_INT, 1)) != BLKmode 12601 && (((unsigned HOST_WIDE_INT) const_op 12602 + (GET_MODE_MASK (tmode) >> 1) + 1) 12603 <= GET_MODE_MASK (tmode))) 12604 { 12605 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0)); 12606 continue; 12607 } 12608 12609 /* Likewise if OP0 is a PLUS of a sign extension with a 12610 constant, which is usually represented with the PLUS 12611 between the shifts. */ 12612 if (! unsigned_comparison_p 12613 && CONST_INT_P (XEXP (op0, 1)) 12614 && GET_CODE (XEXP (op0, 0)) == PLUS 12615 && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) 12616 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT 12617 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) 12618 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 12619 MODE_INT, 1)) != BLKmode 12620 && (((unsigned HOST_WIDE_INT) const_op 12621 + (GET_MODE_MASK (tmode) >> 1) + 1) 12622 <= GET_MODE_MASK (tmode))) 12623 { 12624 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); 12625 rtx add_const = XEXP (XEXP (op0, 0), 1); 12626 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0), 12627 add_const, XEXP (op0, 1)); 12628 12629 op0 = simplify_gen_binary (PLUS, tmode, 12630 gen_lowpart (tmode, inner), 12631 new_const); 12632 continue; 12633 } 12634 12635 /* FALLTHROUGH */ 12636 case LSHIFTRT: 12637 /* If we have (compare (xshiftrt FOO N) (const_int C)) and 12638 the low order N bits of FOO are known to be zero, we can do this 12639 by comparing FOO with C shifted left N bits so long as no 12640 overflow occurs. Even if the low order N bits of FOO aren't known 12641 to be zero, if the comparison is >= or < we can use the same 12642 optimization and for > or <= by setting all the low 12643 order N bits in the comparison constant. */ 12644 if (CONST_INT_P (XEXP (op0, 1)) 12645 && INTVAL (XEXP (op0, 1)) > 0 12646 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 12647 && mode_width <= HOST_BITS_PER_WIDE_INT 12648 && (((unsigned HOST_WIDE_INT) const_op 12649 + (GET_CODE (op0) != LSHIFTRT 12650 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) 12651 + 1) 12652 : 0)) 12653 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) 12654 { 12655 unsigned HOST_WIDE_INT low_bits 12656 = (nonzero_bits (XEXP (op0, 0), mode) 12657 & ((HOST_WIDE_INT_1U 12658 << INTVAL (XEXP (op0, 1))) - 1)); 12659 if (low_bits == 0 || !equality_comparison_p) 12660 { 12661 /* If the shift was logical, then we must make the condition 12662 unsigned. */ 12663 if (GET_CODE (op0) == LSHIFTRT) 12664 code = unsigned_condition (code); 12665 12666 const_op = (unsigned HOST_WIDE_INT) const_op 12667 << INTVAL (XEXP (op0, 1)); 12668 if (low_bits != 0 12669 && (code == GT || code == GTU 12670 || code == LE || code == LEU)) 12671 const_op 12672 |= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1); 12673 op1 = GEN_INT (const_op); 12674 op0 = XEXP (op0, 0); 12675 continue; 12676 } 12677 } 12678 12679 /* If we are using this shift to extract just the sign bit, we 12680 can replace this with an LT or GE comparison. */ 12681 if (const_op == 0 12682 && (equality_comparison_p || sign_bit_comparison_p) 12683 && CONST_INT_P (XEXP (op0, 1)) 12684 && UINTVAL (XEXP (op0, 1)) == mode_width - 1) 12685 { 12686 op0 = XEXP (op0, 0); 12687 code = (code == NE || code == GT ? LT : GE); 12688 continue; 12689 } 12690 break; 12691 12692 default: 12693 break; 12694 } 12695 12696 break; 12697 } 12698 12699 /* Now make any compound operations involved in this comparison. Then, 12700 check for an outmost SUBREG on OP0 that is not doing anything or is 12701 paradoxical. The latter transformation must only be performed when 12702 it is known that the "extra" bits will be the same in op0 and op1 or 12703 that they don't matter. There are three cases to consider: 12704 12705 1. SUBREG_REG (op0) is a register. In this case the bits are don't 12706 care bits and we can assume they have any convenient value. So 12707 making the transformation is safe. 12708 12709 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN. 12710 In this case the upper bits of op0 are undefined. We should not make 12711 the simplification in that case as we do not know the contents of 12712 those bits. 12713 12714 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN. 12715 In that case we know those bits are zeros or ones. We must also be 12716 sure that they are the same as the upper bits of op1. 12717 12718 We can never remove a SUBREG for a non-equality comparison because 12719 the sign bit is in a different place in the underlying object. */ 12720 12721 rtx_code op0_mco_code = SET; 12722 if (op1 == const0_rtx) 12723 op0_mco_code = code == NE || code == EQ ? EQ : COMPARE; 12724 12725 op0 = make_compound_operation (op0, op0_mco_code); 12726 op1 = make_compound_operation (op1, SET); 12727 12728 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 12729 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 12730 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT 12731 && (code == NE || code == EQ)) 12732 { 12733 if (paradoxical_subreg_p (op0)) 12734 { 12735 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't 12736 implemented. */ 12737 if (REG_P (SUBREG_REG (op0))) 12738 { 12739 op0 = SUBREG_REG (op0); 12740 op1 = gen_lowpart (GET_MODE (op0), op1); 12741 } 12742 } 12743 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) 12744 <= HOST_BITS_PER_WIDE_INT) 12745 && (nonzero_bits (SUBREG_REG (op0), 12746 GET_MODE (SUBREG_REG (op0))) 12747 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 12748 { 12749 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1); 12750 12751 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) 12752 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 12753 op0 = SUBREG_REG (op0), op1 = tem; 12754 } 12755 } 12756 12757 /* We now do the opposite procedure: Some machines don't have compare 12758 insns in all modes. If OP0's mode is an integer mode smaller than a 12759 word and we can't do a compare in that mode, see if there is a larger 12760 mode for which we can do the compare. There are a number of cases in 12761 which we can use the wider mode. */ 12762 12763 mode = GET_MODE (op0); 12764 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 12765 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 12766 && ! have_insn_for (COMPARE, mode)) 12767 for (tmode = GET_MODE_WIDER_MODE (mode); 12768 (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode)); 12769 tmode = GET_MODE_WIDER_MODE (tmode)) 12770 if (have_insn_for (COMPARE, tmode)) 12771 { 12772 int zero_extended; 12773 12774 /* If this is a test for negative, we can make an explicit 12775 test of the sign bit. Test this first so we can use 12776 a paradoxical subreg to extend OP0. */ 12777 12778 if (op1 == const0_rtx && (code == LT || code == GE) 12779 && HWI_COMPUTABLE_MODE_P (mode)) 12780 { 12781 unsigned HOST_WIDE_INT sign 12782 = HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1); 12783 op0 = simplify_gen_binary (AND, tmode, 12784 gen_lowpart (tmode, op0), 12785 gen_int_mode (sign, tmode)); 12786 code = (code == LT) ? NE : EQ; 12787 break; 12788 } 12789 12790 /* If the only nonzero bits in OP0 and OP1 are those in the 12791 narrower mode and this is an equality or unsigned comparison, 12792 we can use the wider mode. Similarly for sign-extended 12793 values, in which case it is true for all comparisons. */ 12794 zero_extended = ((code == EQ || code == NE 12795 || code == GEU || code == GTU 12796 || code == LEU || code == LTU) 12797 && (nonzero_bits (op0, tmode) 12798 & ~GET_MODE_MASK (mode)) == 0 12799 && ((CONST_INT_P (op1) 12800 || (nonzero_bits (op1, tmode) 12801 & ~GET_MODE_MASK (mode)) == 0))); 12802 12803 if (zero_extended 12804 || ((num_sign_bit_copies (op0, tmode) 12805 > (unsigned int) (GET_MODE_PRECISION (tmode) 12806 - GET_MODE_PRECISION (mode))) 12807 && (num_sign_bit_copies (op1, tmode) 12808 > (unsigned int) (GET_MODE_PRECISION (tmode) 12809 - GET_MODE_PRECISION (mode))))) 12810 { 12811 /* If OP0 is an AND and we don't have an AND in MODE either, 12812 make a new AND in the proper mode. */ 12813 if (GET_CODE (op0) == AND 12814 && !have_insn_for (AND, mode)) 12815 op0 = simplify_gen_binary (AND, tmode, 12816 gen_lowpart (tmode, 12817 XEXP (op0, 0)), 12818 gen_lowpart (tmode, 12819 XEXP (op0, 1))); 12820 else 12821 { 12822 if (zero_extended) 12823 { 12824 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode); 12825 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode); 12826 } 12827 else 12828 { 12829 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode); 12830 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode); 12831 } 12832 break; 12833 } 12834 } 12835 } 12836 12837 /* We may have changed the comparison operands. Re-canonicalize. */ 12838 if (swap_commutative_operands_p (op0, op1)) 12839 { 12840 std::swap (op0, op1); 12841 code = swap_condition (code); 12842 } 12843 12844 /* If this machine only supports a subset of valid comparisons, see if we 12845 can convert an unsupported one into a supported one. */ 12846 target_canonicalize_comparison (&code, &op0, &op1, 0); 12847 12848 *pop0 = op0; 12849 *pop1 = op1; 12850 12851 return code; 12852 } 12853 12854 /* Utility function for record_value_for_reg. Count number of 12855 rtxs in X. */ 12856 static int 12857 count_rtxs (rtx x) 12858 { 12859 enum rtx_code code = GET_CODE (x); 12860 const char *fmt; 12861 int i, j, ret = 1; 12862 12863 if (GET_RTX_CLASS (code) == RTX_BIN_ARITH 12864 || GET_RTX_CLASS (code) == RTX_COMM_ARITH) 12865 { 12866 rtx x0 = XEXP (x, 0); 12867 rtx x1 = XEXP (x, 1); 12868 12869 if (x0 == x1) 12870 return 1 + 2 * count_rtxs (x0); 12871 12872 if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH 12873 || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH) 12874 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 12875 return 2 + 2 * count_rtxs (x0) 12876 + count_rtxs (x == XEXP (x1, 0) 12877 ? XEXP (x1, 1) : XEXP (x1, 0)); 12878 12879 if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH 12880 || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH) 12881 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 12882 return 2 + 2 * count_rtxs (x1) 12883 + count_rtxs (x == XEXP (x0, 0) 12884 ? XEXP (x0, 1) : XEXP (x0, 0)); 12885 } 12886 12887 fmt = GET_RTX_FORMAT (code); 12888 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 12889 if (fmt[i] == 'e') 12890 ret += count_rtxs (XEXP (x, i)); 12891 else if (fmt[i] == 'E') 12892 for (j = 0; j < XVECLEN (x, i); j++) 12893 ret += count_rtxs (XVECEXP (x, i, j)); 12894 12895 return ret; 12896 } 12897 12898 /* Utility function for following routine. Called when X is part of a value 12899 being stored into last_set_value. Sets last_set_table_tick 12900 for each register mentioned. Similar to mention_regs in cse.c */ 12901 12902 static void 12903 update_table_tick (rtx x) 12904 { 12905 enum rtx_code code = GET_CODE (x); 12906 const char *fmt = GET_RTX_FORMAT (code); 12907 int i, j; 12908 12909 if (code == REG) 12910 { 12911 unsigned int regno = REGNO (x); 12912 unsigned int endregno = END_REGNO (x); 12913 unsigned int r; 12914 12915 for (r = regno; r < endregno; r++) 12916 { 12917 reg_stat_type *rsp = ®_stat[r]; 12918 rsp->last_set_table_tick = label_tick; 12919 } 12920 12921 return; 12922 } 12923 12924 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 12925 if (fmt[i] == 'e') 12926 { 12927 /* Check for identical subexpressions. If x contains 12928 identical subexpression we only have to traverse one of 12929 them. */ 12930 if (i == 0 && ARITHMETIC_P (x)) 12931 { 12932 /* Note that at this point x1 has already been 12933 processed. */ 12934 rtx x0 = XEXP (x, 0); 12935 rtx x1 = XEXP (x, 1); 12936 12937 /* If x0 and x1 are identical then there is no need to 12938 process x0. */ 12939 if (x0 == x1) 12940 break; 12941 12942 /* If x0 is identical to a subexpression of x1 then while 12943 processing x1, x0 has already been processed. Thus we 12944 are done with x. */ 12945 if (ARITHMETIC_P (x1) 12946 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 12947 break; 12948 12949 /* If x1 is identical to a subexpression of x0 then we 12950 still have to process the rest of x0. */ 12951 if (ARITHMETIC_P (x0) 12952 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 12953 { 12954 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0)); 12955 break; 12956 } 12957 } 12958 12959 update_table_tick (XEXP (x, i)); 12960 } 12961 else if (fmt[i] == 'E') 12962 for (j = 0; j < XVECLEN (x, i); j++) 12963 update_table_tick (XVECEXP (x, i, j)); 12964 } 12965 12966 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we 12967 are saying that the register is clobbered and we no longer know its 12968 value. If INSN is zero, don't update reg_stat[].last_set; this is 12969 only permitted with VALUE also zero and is used to invalidate the 12970 register. */ 12971 12972 static void 12973 record_value_for_reg (rtx reg, rtx_insn *insn, rtx value) 12974 { 12975 unsigned int regno = REGNO (reg); 12976 unsigned int endregno = END_REGNO (reg); 12977 unsigned int i; 12978 reg_stat_type *rsp; 12979 12980 /* If VALUE contains REG and we have a previous value for REG, substitute 12981 the previous value. */ 12982 if (value && insn && reg_overlap_mentioned_p (reg, value)) 12983 { 12984 rtx tem; 12985 12986 /* Set things up so get_last_value is allowed to see anything set up to 12987 our insn. */ 12988 subst_low_luid = DF_INSN_LUID (insn); 12989 tem = get_last_value (reg); 12990 12991 /* If TEM is simply a binary operation with two CLOBBERs as operands, 12992 it isn't going to be useful and will take a lot of time to process, 12993 so just use the CLOBBER. */ 12994 12995 if (tem) 12996 { 12997 if (ARITHMETIC_P (tem) 12998 && GET_CODE (XEXP (tem, 0)) == CLOBBER 12999 && GET_CODE (XEXP (tem, 1)) == CLOBBER) 13000 tem = XEXP (tem, 0); 13001 else if (count_occurrences (value, reg, 1) >= 2) 13002 { 13003 /* If there are two or more occurrences of REG in VALUE, 13004 prevent the value from growing too much. */ 13005 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL) 13006 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx); 13007 } 13008 13009 value = replace_rtx (copy_rtx (value), reg, tem); 13010 } 13011 } 13012 13013 /* For each register modified, show we don't know its value, that 13014 we don't know about its bitwise content, that its value has been 13015 updated, and that we don't know the location of the death of the 13016 register. */ 13017 for (i = regno; i < endregno; i++) 13018 { 13019 rsp = ®_stat[i]; 13020 13021 if (insn) 13022 rsp->last_set = insn; 13023 13024 rsp->last_set_value = 0; 13025 rsp->last_set_mode = VOIDmode; 13026 rsp->last_set_nonzero_bits = 0; 13027 rsp->last_set_sign_bit_copies = 0; 13028 rsp->last_death = 0; 13029 rsp->truncated_to_mode = VOIDmode; 13030 } 13031 13032 /* Mark registers that are being referenced in this value. */ 13033 if (value) 13034 update_table_tick (value); 13035 13036 /* Now update the status of each register being set. 13037 If someone is using this register in this block, set this register 13038 to invalid since we will get confused between the two lives in this 13039 basic block. This makes using this register always invalid. In cse, we 13040 scan the table to invalidate all entries using this register, but this 13041 is too much work for us. */ 13042 13043 for (i = regno; i < endregno; i++) 13044 { 13045 rsp = ®_stat[i]; 13046 rsp->last_set_label = label_tick; 13047 if (!insn 13048 || (value && rsp->last_set_table_tick >= label_tick_ebb_start)) 13049 rsp->last_set_invalid = 1; 13050 else 13051 rsp->last_set_invalid = 0; 13052 } 13053 13054 /* The value being assigned might refer to X (like in "x++;"). In that 13055 case, we must replace it with (clobber (const_int 0)) to prevent 13056 infinite loops. */ 13057 rsp = ®_stat[regno]; 13058 if (value && !get_last_value_validate (&value, insn, label_tick, 0)) 13059 { 13060 value = copy_rtx (value); 13061 if (!get_last_value_validate (&value, insn, label_tick, 1)) 13062 value = 0; 13063 } 13064 13065 /* For the main register being modified, update the value, the mode, the 13066 nonzero bits, and the number of sign bit copies. */ 13067 13068 rsp->last_set_value = value; 13069 13070 if (value) 13071 { 13072 machine_mode mode = GET_MODE (reg); 13073 subst_low_luid = DF_INSN_LUID (insn); 13074 rsp->last_set_mode = mode; 13075 if (GET_MODE_CLASS (mode) == MODE_INT 13076 && HWI_COMPUTABLE_MODE_P (mode)) 13077 mode = nonzero_bits_mode; 13078 rsp->last_set_nonzero_bits = nonzero_bits (value, mode); 13079 rsp->last_set_sign_bit_copies 13080 = num_sign_bit_copies (value, GET_MODE (reg)); 13081 } 13082 } 13083 13084 /* Called via note_stores from record_dead_and_set_regs to handle one 13085 SET or CLOBBER in an insn. DATA is the instruction in which the 13086 set is occurring. */ 13087 13088 static void 13089 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data) 13090 { 13091 rtx_insn *record_dead_insn = (rtx_insn *) data; 13092 13093 if (GET_CODE (dest) == SUBREG) 13094 dest = SUBREG_REG (dest); 13095 13096 if (!record_dead_insn) 13097 { 13098 if (REG_P (dest)) 13099 record_value_for_reg (dest, NULL, NULL_RTX); 13100 return; 13101 } 13102 13103 if (REG_P (dest)) 13104 { 13105 /* If we are setting the whole register, we know its value. Otherwise 13106 show that we don't know the value. We can handle a SUBREG if it's 13107 the low part, but we must be careful with paradoxical SUBREGs on 13108 RISC architectures because we cannot strip e.g. an extension around 13109 a load and record the naked load since the RTL middle-end considers 13110 that the upper bits are defined according to LOAD_EXTEND_OP. */ 13111 if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) 13112 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); 13113 else if (GET_CODE (setter) == SET 13114 && GET_CODE (SET_DEST (setter)) == SUBREG 13115 && SUBREG_REG (SET_DEST (setter)) == dest 13116 && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD 13117 && subreg_lowpart_p (SET_DEST (setter))) 13118 record_value_for_reg (dest, record_dead_insn, 13119 WORD_REGISTER_OPERATIONS 13120 && word_register_operation_p (SET_SRC (setter)) 13121 && paradoxical_subreg_p (SET_DEST (setter)) 13122 ? SET_SRC (setter) 13123 : gen_lowpart (GET_MODE (dest), 13124 SET_SRC (setter))); 13125 else 13126 record_value_for_reg (dest, record_dead_insn, NULL_RTX); 13127 } 13128 else if (MEM_P (dest) 13129 /* Ignore pushes, they clobber nothing. */ 13130 && ! push_operand (dest, GET_MODE (dest))) 13131 mem_last_set = DF_INSN_LUID (record_dead_insn); 13132 } 13133 13134 /* Update the records of when each REG was most recently set or killed 13135 for the things done by INSN. This is the last thing done in processing 13136 INSN in the combiner loop. 13137 13138 We update reg_stat[], in particular fields last_set, last_set_value, 13139 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies, 13140 last_death, and also the similar information mem_last_set (which insn 13141 most recently modified memory) and last_call_luid (which insn was the 13142 most recent subroutine call). */ 13143 13144 static void 13145 record_dead_and_set_regs (rtx_insn *insn) 13146 { 13147 rtx link; 13148 unsigned int i; 13149 13150 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 13151 { 13152 if (REG_NOTE_KIND (link) == REG_DEAD 13153 && REG_P (XEXP (link, 0))) 13154 { 13155 unsigned int regno = REGNO (XEXP (link, 0)); 13156 unsigned int endregno = END_REGNO (XEXP (link, 0)); 13157 13158 for (i = regno; i < endregno; i++) 13159 { 13160 reg_stat_type *rsp; 13161 13162 rsp = ®_stat[i]; 13163 rsp->last_death = insn; 13164 } 13165 } 13166 else if (REG_NOTE_KIND (link) == REG_INC) 13167 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); 13168 } 13169 13170 if (CALL_P (insn)) 13171 { 13172 hard_reg_set_iterator hrsi; 13173 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi) 13174 { 13175 reg_stat_type *rsp; 13176 13177 rsp = ®_stat[i]; 13178 rsp->last_set_invalid = 1; 13179 rsp->last_set = insn; 13180 rsp->last_set_value = 0; 13181 rsp->last_set_mode = VOIDmode; 13182 rsp->last_set_nonzero_bits = 0; 13183 rsp->last_set_sign_bit_copies = 0; 13184 rsp->last_death = 0; 13185 rsp->truncated_to_mode = VOIDmode; 13186 } 13187 13188 last_call_luid = mem_last_set = DF_INSN_LUID (insn); 13189 13190 /* We can't combine into a call pattern. Remember, though, that 13191 the return value register is set at this LUID. We could 13192 still replace a register with the return value from the 13193 wrong subroutine call! */ 13194 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX); 13195 } 13196 else 13197 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); 13198 } 13199 13200 /* If a SUBREG has the promoted bit set, it is in fact a property of the 13201 register present in the SUBREG, so for each such SUBREG go back and 13202 adjust nonzero and sign bit information of the registers that are 13203 known to have some zero/sign bits set. 13204 13205 This is needed because when combine blows the SUBREGs away, the 13206 information on zero/sign bits is lost and further combines can be 13207 missed because of that. */ 13208 13209 static void 13210 record_promoted_value (rtx_insn *insn, rtx subreg) 13211 { 13212 struct insn_link *links; 13213 rtx set; 13214 unsigned int regno = REGNO (SUBREG_REG (subreg)); 13215 machine_mode mode = GET_MODE (subreg); 13216 13217 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT) 13218 return; 13219 13220 for (links = LOG_LINKS (insn); links;) 13221 { 13222 reg_stat_type *rsp; 13223 13224 insn = links->insn; 13225 set = single_set (insn); 13226 13227 if (! set || !REG_P (SET_DEST (set)) 13228 || REGNO (SET_DEST (set)) != regno 13229 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) 13230 { 13231 links = links->next; 13232 continue; 13233 } 13234 13235 rsp = ®_stat[regno]; 13236 if (rsp->last_set == insn) 13237 { 13238 if (SUBREG_PROMOTED_UNSIGNED_P (subreg)) 13239 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode); 13240 } 13241 13242 if (REG_P (SET_SRC (set))) 13243 { 13244 regno = REGNO (SET_SRC (set)); 13245 links = LOG_LINKS (insn); 13246 } 13247 else 13248 break; 13249 } 13250 } 13251 13252 /* Check if X, a register, is known to contain a value already 13253 truncated to MODE. In this case we can use a subreg to refer to 13254 the truncated value even though in the generic case we would need 13255 an explicit truncation. */ 13256 13257 static bool 13258 reg_truncated_to_mode (machine_mode mode, const_rtx x) 13259 { 13260 reg_stat_type *rsp = ®_stat[REGNO (x)]; 13261 machine_mode truncated = rsp->truncated_to_mode; 13262 13263 if (truncated == 0 13264 || rsp->truncation_label < label_tick_ebb_start) 13265 return false; 13266 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode)) 13267 return true; 13268 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated)) 13269 return true; 13270 return false; 13271 } 13272 13273 /* If X is a hard reg or a subreg record the mode that the register is 13274 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able 13275 to turn a truncate into a subreg using this information. Return true 13276 if traversing X is complete. */ 13277 13278 static bool 13279 record_truncated_value (rtx x) 13280 { 13281 machine_mode truncated_mode; 13282 reg_stat_type *rsp; 13283 13284 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))) 13285 { 13286 machine_mode original_mode = GET_MODE (SUBREG_REG (x)); 13287 truncated_mode = GET_MODE (x); 13288 13289 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode)) 13290 return true; 13291 13292 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode)) 13293 return true; 13294 13295 x = SUBREG_REG (x); 13296 } 13297 /* ??? For hard-regs we now record everything. We might be able to 13298 optimize this using last_set_mode. */ 13299 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) 13300 truncated_mode = GET_MODE (x); 13301 else 13302 return false; 13303 13304 rsp = ®_stat[REGNO (x)]; 13305 if (rsp->truncated_to_mode == 0 13306 || rsp->truncation_label < label_tick_ebb_start 13307 || (GET_MODE_SIZE (truncated_mode) 13308 < GET_MODE_SIZE (rsp->truncated_to_mode))) 13309 { 13310 rsp->truncated_to_mode = truncated_mode; 13311 rsp->truncation_label = label_tick; 13312 } 13313 13314 return true; 13315 } 13316 13317 /* Callback for note_uses. Find hardregs and subregs of pseudos and 13318 the modes they are used in. This can help truning TRUNCATEs into 13319 SUBREGs. */ 13320 13321 static void 13322 record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED) 13323 { 13324 subrtx_var_iterator::array_type array; 13325 FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST) 13326 if (record_truncated_value (*iter)) 13327 iter.skip_subrtxes (); 13328 } 13329 13330 /* Scan X for promoted SUBREGs. For each one found, 13331 note what it implies to the registers used in it. */ 13332 13333 static void 13334 check_promoted_subreg (rtx_insn *insn, rtx x) 13335 { 13336 if (GET_CODE (x) == SUBREG 13337 && SUBREG_PROMOTED_VAR_P (x) 13338 && REG_P (SUBREG_REG (x))) 13339 record_promoted_value (insn, x); 13340 else 13341 { 13342 const char *format = GET_RTX_FORMAT (GET_CODE (x)); 13343 int i, j; 13344 13345 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) 13346 switch (format[i]) 13347 { 13348 case 'e': 13349 check_promoted_subreg (insn, XEXP (x, i)); 13350 break; 13351 case 'V': 13352 case 'E': 13353 if (XVEC (x, i) != 0) 13354 for (j = 0; j < XVECLEN (x, i); j++) 13355 check_promoted_subreg (insn, XVECEXP (x, i, j)); 13356 break; 13357 } 13358 } 13359 } 13360 13361 /* Verify that all the registers and memory references mentioned in *LOC are 13362 still valid. *LOC was part of a value set in INSN when label_tick was 13363 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace 13364 the invalid references with (clobber (const_int 0)) and return 1. This 13365 replacement is useful because we often can get useful information about 13366 the form of a value (e.g., if it was produced by a shift that always 13367 produces -1 or 0) even though we don't know exactly what registers it 13368 was produced from. */ 13369 13370 static int 13371 get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, int replace) 13372 { 13373 rtx x = *loc; 13374 const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); 13375 int len = GET_RTX_LENGTH (GET_CODE (x)); 13376 int i, j; 13377 13378 if (REG_P (x)) 13379 { 13380 unsigned int regno = REGNO (x); 13381 unsigned int endregno = END_REGNO (x); 13382 unsigned int j; 13383 13384 for (j = regno; j < endregno; j++) 13385 { 13386 reg_stat_type *rsp = ®_stat[j]; 13387 if (rsp->last_set_invalid 13388 /* If this is a pseudo-register that was only set once and not 13389 live at the beginning of the function, it is always valid. */ 13390 || (! (regno >= FIRST_PSEUDO_REGISTER 13391 && regno < reg_n_sets_max 13392 && REG_N_SETS (regno) == 1 13393 && (!REGNO_REG_SET_P 13394 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), 13395 regno))) 13396 && rsp->last_set_label > tick)) 13397 { 13398 if (replace) 13399 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 13400 return replace; 13401 } 13402 } 13403 13404 return 1; 13405 } 13406 /* If this is a memory reference, make sure that there were no stores after 13407 it that might have clobbered the value. We don't have alias info, so we 13408 assume any store invalidates it. Moreover, we only have local UIDs, so 13409 we also assume that there were stores in the intervening basic blocks. */ 13410 else if (MEM_P (x) && !MEM_READONLY_P (x) 13411 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set)) 13412 { 13413 if (replace) 13414 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 13415 return replace; 13416 } 13417 13418 for (i = 0; i < len; i++) 13419 { 13420 if (fmt[i] == 'e') 13421 { 13422 /* Check for identical subexpressions. If x contains 13423 identical subexpression we only have to traverse one of 13424 them. */ 13425 if (i == 1 && ARITHMETIC_P (x)) 13426 { 13427 /* Note that at this point x0 has already been checked 13428 and found valid. */ 13429 rtx x0 = XEXP (x, 0); 13430 rtx x1 = XEXP (x, 1); 13431 13432 /* If x0 and x1 are identical then x is also valid. */ 13433 if (x0 == x1) 13434 return 1; 13435 13436 /* If x1 is identical to a subexpression of x0 then 13437 while checking x0, x1 has already been checked. Thus 13438 it is valid and so as x. */ 13439 if (ARITHMETIC_P (x0) 13440 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 13441 return 1; 13442 13443 /* If x0 is identical to a subexpression of x1 then x is 13444 valid iff the rest of x1 is valid. */ 13445 if (ARITHMETIC_P (x1) 13446 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 13447 return 13448 get_last_value_validate (&XEXP (x1, 13449 x0 == XEXP (x1, 0) ? 1 : 0), 13450 insn, tick, replace); 13451 } 13452 13453 if (get_last_value_validate (&XEXP (x, i), insn, tick, 13454 replace) == 0) 13455 return 0; 13456 } 13457 else if (fmt[i] == 'E') 13458 for (j = 0; j < XVECLEN (x, i); j++) 13459 if (get_last_value_validate (&XVECEXP (x, i, j), 13460 insn, tick, replace) == 0) 13461 return 0; 13462 } 13463 13464 /* If we haven't found a reason for it to be invalid, it is valid. */ 13465 return 1; 13466 } 13467 13468 /* Get the last value assigned to X, if known. Some registers 13469 in the value may be replaced with (clobber (const_int 0)) if their value 13470 is known longer known reliably. */ 13471 13472 static rtx 13473 get_last_value (const_rtx x) 13474 { 13475 unsigned int regno; 13476 rtx value; 13477 reg_stat_type *rsp; 13478 13479 /* If this is a non-paradoxical SUBREG, get the value of its operand and 13480 then convert it to the desired mode. If this is a paradoxical SUBREG, 13481 we cannot predict what values the "extra" bits might have. */ 13482 if (GET_CODE (x) == SUBREG 13483 && subreg_lowpart_p (x) 13484 && !paradoxical_subreg_p (x) 13485 && (value = get_last_value (SUBREG_REG (x))) != 0) 13486 return gen_lowpart (GET_MODE (x), value); 13487 13488 if (!REG_P (x)) 13489 return 0; 13490 13491 regno = REGNO (x); 13492 rsp = ®_stat[regno]; 13493 value = rsp->last_set_value; 13494 13495 /* If we don't have a value, or if it isn't for this basic block and 13496 it's either a hard register, set more than once, or it's a live 13497 at the beginning of the function, return 0. 13498 13499 Because if it's not live at the beginning of the function then the reg 13500 is always set before being used (is never used without being set). 13501 And, if it's set only once, and it's always set before use, then all 13502 uses must have the same last value, even if it's not from this basic 13503 block. */ 13504 13505 if (value == 0 13506 || (rsp->last_set_label < label_tick_ebb_start 13507 && (regno < FIRST_PSEUDO_REGISTER 13508 || regno >= reg_n_sets_max 13509 || REG_N_SETS (regno) != 1 13510 || REGNO_REG_SET_P 13511 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno)))) 13512 return 0; 13513 13514 /* If the value was set in a later insn than the ones we are processing, 13515 we can't use it even if the register was only set once. */ 13516 if (rsp->last_set_label == label_tick 13517 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid) 13518 return 0; 13519 13520 /* If fewer bits were set than what we are asked for now, we cannot use 13521 the value. */ 13522 if (GET_MODE_PRECISION (rsp->last_set_mode) 13523 < GET_MODE_PRECISION (GET_MODE (x))) 13524 return 0; 13525 13526 /* If the value has all its registers valid, return it. */ 13527 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0)) 13528 return value; 13529 13530 /* Otherwise, make a copy and replace any invalid register with 13531 (clobber (const_int 0)). If that fails for some reason, return 0. */ 13532 13533 value = copy_rtx (value); 13534 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1)) 13535 return value; 13536 13537 return 0; 13538 } 13539 13540 /* Return nonzero if expression X refers to a REG or to memory 13541 that is set in an instruction more recent than FROM_LUID. */ 13542 13543 static int 13544 use_crosses_set_p (const_rtx x, int from_luid) 13545 { 13546 const char *fmt; 13547 int i; 13548 enum rtx_code code = GET_CODE (x); 13549 13550 if (code == REG) 13551 { 13552 unsigned int regno = REGNO (x); 13553 unsigned endreg = END_REGNO (x); 13554 13555 #ifdef PUSH_ROUNDING 13556 /* Don't allow uses of the stack pointer to be moved, 13557 because we don't know whether the move crosses a push insn. */ 13558 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) 13559 return 1; 13560 #endif 13561 for (; regno < endreg; regno++) 13562 { 13563 reg_stat_type *rsp = ®_stat[regno]; 13564 if (rsp->last_set 13565 && rsp->last_set_label == label_tick 13566 && DF_INSN_LUID (rsp->last_set) > from_luid) 13567 return 1; 13568 } 13569 return 0; 13570 } 13571 13572 if (code == MEM && mem_last_set > from_luid) 13573 return 1; 13574 13575 fmt = GET_RTX_FORMAT (code); 13576 13577 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 13578 { 13579 if (fmt[i] == 'E') 13580 { 13581 int j; 13582 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 13583 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid)) 13584 return 1; 13585 } 13586 else if (fmt[i] == 'e' 13587 && use_crosses_set_p (XEXP (x, i), from_luid)) 13588 return 1; 13589 } 13590 return 0; 13591 } 13592 13593 /* Define three variables used for communication between the following 13594 routines. */ 13595 13596 static unsigned int reg_dead_regno, reg_dead_endregno; 13597 static int reg_dead_flag; 13598 13599 /* Function called via note_stores from reg_dead_at_p. 13600 13601 If DEST is within [reg_dead_regno, reg_dead_endregno), set 13602 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ 13603 13604 static void 13605 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) 13606 { 13607 unsigned int regno, endregno; 13608 13609 if (!REG_P (dest)) 13610 return; 13611 13612 regno = REGNO (dest); 13613 endregno = END_REGNO (dest); 13614 if (reg_dead_endregno > regno && reg_dead_regno < endregno) 13615 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; 13616 } 13617 13618 /* Return nonzero if REG is known to be dead at INSN. 13619 13620 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER 13621 referencing REG, it is dead. If we hit a SET referencing REG, it is 13622 live. Otherwise, see if it is live or dead at the start of the basic 13623 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS 13624 must be assumed to be always live. */ 13625 13626 static int 13627 reg_dead_at_p (rtx reg, rtx_insn *insn) 13628 { 13629 basic_block block; 13630 unsigned int i; 13631 13632 /* Set variables for reg_dead_at_p_1. */ 13633 reg_dead_regno = REGNO (reg); 13634 reg_dead_endregno = END_REGNO (reg); 13635 13636 reg_dead_flag = 0; 13637 13638 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers 13639 we allow the machine description to decide whether use-and-clobber 13640 patterns are OK. */ 13641 if (reg_dead_regno < FIRST_PSEUDO_REGISTER) 13642 { 13643 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 13644 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i)) 13645 return 0; 13646 } 13647 13648 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or 13649 beginning of basic block. */ 13650 block = BLOCK_FOR_INSN (insn); 13651 for (;;) 13652 { 13653 if (INSN_P (insn)) 13654 { 13655 if (find_regno_note (insn, REG_UNUSED, reg_dead_regno)) 13656 return 1; 13657 13658 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); 13659 if (reg_dead_flag) 13660 return reg_dead_flag == 1 ? 1 : 0; 13661 13662 if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) 13663 return 1; 13664 } 13665 13666 if (insn == BB_HEAD (block)) 13667 break; 13668 13669 insn = PREV_INSN (insn); 13670 } 13671 13672 /* Look at live-in sets for the basic block that we were in. */ 13673 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 13674 if (REGNO_REG_SET_P (df_get_live_in (block), i)) 13675 return 0; 13676 13677 return 1; 13678 } 13679 13680 /* Note hard registers in X that are used. */ 13681 13682 static void 13683 mark_used_regs_combine (rtx x) 13684 { 13685 RTX_CODE code = GET_CODE (x); 13686 unsigned int regno; 13687 int i; 13688 13689 switch (code) 13690 { 13691 case LABEL_REF: 13692 case SYMBOL_REF: 13693 case CONST: 13694 CASE_CONST_ANY: 13695 case PC: 13696 case ADDR_VEC: 13697 case ADDR_DIFF_VEC: 13698 case ASM_INPUT: 13699 /* CC0 must die in the insn after it is set, so we don't need to take 13700 special note of it here. */ 13701 case CC0: 13702 return; 13703 13704 case CLOBBER: 13705 /* If we are clobbering a MEM, mark any hard registers inside the 13706 address as used. */ 13707 if (MEM_P (XEXP (x, 0))) 13708 mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); 13709 return; 13710 13711 case REG: 13712 regno = REGNO (x); 13713 /* A hard reg in a wide mode may really be multiple registers. 13714 If so, mark all of them just like the first. */ 13715 if (regno < FIRST_PSEUDO_REGISTER) 13716 { 13717 /* None of this applies to the stack, frame or arg pointers. */ 13718 if (regno == STACK_POINTER_REGNUM 13719 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER 13720 && regno == HARD_FRAME_POINTER_REGNUM) 13721 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 13722 && regno == ARG_POINTER_REGNUM && fixed_regs[regno]) 13723 || regno == FRAME_POINTER_REGNUM) 13724 return; 13725 13726 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno); 13727 } 13728 return; 13729 13730 case SET: 13731 { 13732 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in 13733 the address. */ 13734 rtx testreg = SET_DEST (x); 13735 13736 while (GET_CODE (testreg) == SUBREG 13737 || GET_CODE (testreg) == ZERO_EXTRACT 13738 || GET_CODE (testreg) == STRICT_LOW_PART) 13739 testreg = XEXP (testreg, 0); 13740 13741 if (MEM_P (testreg)) 13742 mark_used_regs_combine (XEXP (testreg, 0)); 13743 13744 mark_used_regs_combine (SET_SRC (x)); 13745 } 13746 return; 13747 13748 default: 13749 break; 13750 } 13751 13752 /* Recursively scan the operands of this expression. */ 13753 13754 { 13755 const char *fmt = GET_RTX_FORMAT (code); 13756 13757 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 13758 { 13759 if (fmt[i] == 'e') 13760 mark_used_regs_combine (XEXP (x, i)); 13761 else if (fmt[i] == 'E') 13762 { 13763 int j; 13764 13765 for (j = 0; j < XVECLEN (x, i); j++) 13766 mark_used_regs_combine (XVECEXP (x, i, j)); 13767 } 13768 } 13769 } 13770 } 13771 13772 /* Remove register number REGNO from the dead registers list of INSN. 13773 13774 Return the note used to record the death, if there was one. */ 13775 13776 rtx 13777 remove_death (unsigned int regno, rtx_insn *insn) 13778 { 13779 rtx note = find_regno_note (insn, REG_DEAD, regno); 13780 13781 if (note) 13782 remove_note (insn, note); 13783 13784 return note; 13785 } 13786 13787 /* For each register (hardware or pseudo) used within expression X, if its 13788 death is in an instruction with luid between FROM_LUID (inclusive) and 13789 TO_INSN (exclusive), put a REG_DEAD note for that register in the 13790 list headed by PNOTES. 13791 13792 That said, don't move registers killed by maybe_kill_insn. 13793 13794 This is done when X is being merged by combination into TO_INSN. These 13795 notes will then be distributed as needed. */ 13796 13797 static void 13798 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn, 13799 rtx *pnotes) 13800 { 13801 const char *fmt; 13802 int len, i; 13803 enum rtx_code code = GET_CODE (x); 13804 13805 if (code == REG) 13806 { 13807 unsigned int regno = REGNO (x); 13808 rtx_insn *where_dead = reg_stat[regno].last_death; 13809 13810 /* Don't move the register if it gets killed in between from and to. */ 13811 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) 13812 && ! reg_referenced_p (x, maybe_kill_insn)) 13813 return; 13814 13815 if (where_dead 13816 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn) 13817 && DF_INSN_LUID (where_dead) >= from_luid 13818 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn)) 13819 { 13820 rtx note = remove_death (regno, where_dead); 13821 13822 /* It is possible for the call above to return 0. This can occur 13823 when last_death points to I2 or I1 that we combined with. 13824 In that case make a new note. 13825 13826 We must also check for the case where X is a hard register 13827 and NOTE is a death note for a range of hard registers 13828 including X. In that case, we must put REG_DEAD notes for 13829 the remaining registers in place of NOTE. */ 13830 13831 if (note != 0 && regno < FIRST_PSEUDO_REGISTER 13832 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 13833 > GET_MODE_SIZE (GET_MODE (x)))) 13834 { 13835 unsigned int deadregno = REGNO (XEXP (note, 0)); 13836 unsigned int deadend = END_REGNO (XEXP (note, 0)); 13837 unsigned int ourend = END_REGNO (x); 13838 unsigned int i; 13839 13840 for (i = deadregno; i < deadend; i++) 13841 if (i < regno || i >= ourend) 13842 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]); 13843 } 13844 13845 /* If we didn't find any note, or if we found a REG_DEAD note that 13846 covers only part of the given reg, and we have a multi-reg hard 13847 register, then to be safe we must check for REG_DEAD notes 13848 for each register other than the first. They could have 13849 their own REG_DEAD notes lying around. */ 13850 else if ((note == 0 13851 || (note != 0 13852 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 13853 < GET_MODE_SIZE (GET_MODE (x))))) 13854 && regno < FIRST_PSEUDO_REGISTER 13855 && REG_NREGS (x) > 1) 13856 { 13857 unsigned int ourend = END_REGNO (x); 13858 unsigned int i, offset; 13859 rtx oldnotes = 0; 13860 13861 if (note) 13862 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))]; 13863 else 13864 offset = 1; 13865 13866 for (i = regno + offset; i < ourend; i++) 13867 move_deaths (regno_reg_rtx[i], 13868 maybe_kill_insn, from_luid, to_insn, &oldnotes); 13869 } 13870 13871 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) 13872 { 13873 XEXP (note, 1) = *pnotes; 13874 *pnotes = note; 13875 } 13876 else 13877 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes); 13878 } 13879 13880 return; 13881 } 13882 13883 else if (GET_CODE (x) == SET) 13884 { 13885 rtx dest = SET_DEST (x); 13886 13887 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes); 13888 13889 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG 13890 that accesses one word of a multi-word item, some 13891 piece of everything register in the expression is used by 13892 this insn, so remove any old death. */ 13893 /* ??? So why do we test for equality of the sizes? */ 13894 13895 if (GET_CODE (dest) == ZERO_EXTRACT 13896 || GET_CODE (dest) == STRICT_LOW_PART 13897 || (GET_CODE (dest) == SUBREG 13898 && (((GET_MODE_SIZE (GET_MODE (dest)) 13899 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 13900 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) 13901 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) 13902 { 13903 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes); 13904 return; 13905 } 13906 13907 /* If this is some other SUBREG, we know it replaces the entire 13908 value, so use that as the destination. */ 13909 if (GET_CODE (dest) == SUBREG) 13910 dest = SUBREG_REG (dest); 13911 13912 /* If this is a MEM, adjust deaths of anything used in the address. 13913 For a REG (the only other possibility), the entire value is 13914 being replaced so the old value is not used in this insn. */ 13915 13916 if (MEM_P (dest)) 13917 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid, 13918 to_insn, pnotes); 13919 return; 13920 } 13921 13922 else if (GET_CODE (x) == CLOBBER) 13923 return; 13924 13925 len = GET_RTX_LENGTH (code); 13926 fmt = GET_RTX_FORMAT (code); 13927 13928 for (i = 0; i < len; i++) 13929 { 13930 if (fmt[i] == 'E') 13931 { 13932 int j; 13933 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 13934 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid, 13935 to_insn, pnotes); 13936 } 13937 else if (fmt[i] == 'e') 13938 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes); 13939 } 13940 } 13941 13942 /* Return 1 if X is the target of a bit-field assignment in BODY, the 13943 pattern of an insn. X must be a REG. */ 13944 13945 static int 13946 reg_bitfield_target_p (rtx x, rtx body) 13947 { 13948 int i; 13949 13950 if (GET_CODE (body) == SET) 13951 { 13952 rtx dest = SET_DEST (body); 13953 rtx target; 13954 unsigned int regno, tregno, endregno, endtregno; 13955 13956 if (GET_CODE (dest) == ZERO_EXTRACT) 13957 target = XEXP (dest, 0); 13958 else if (GET_CODE (dest) == STRICT_LOW_PART) 13959 target = SUBREG_REG (XEXP (dest, 0)); 13960 else 13961 return 0; 13962 13963 if (GET_CODE (target) == SUBREG) 13964 target = SUBREG_REG (target); 13965 13966 if (!REG_P (target)) 13967 return 0; 13968 13969 tregno = REGNO (target), regno = REGNO (x); 13970 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) 13971 return target == x; 13972 13973 endtregno = end_hard_regno (GET_MODE (target), tregno); 13974 endregno = end_hard_regno (GET_MODE (x), regno); 13975 13976 return endregno > tregno && regno < endtregno; 13977 } 13978 13979 else if (GET_CODE (body) == PARALLEL) 13980 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 13981 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) 13982 return 1; 13983 13984 return 0; 13985 } 13986 13987 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them 13988 as appropriate. I3 and I2 are the insns resulting from the combination 13989 insns including FROM (I2 may be zero). 13990 13991 ELIM_I2 and ELIM_I1 are either zero or registers that we know will 13992 not need REG_DEAD notes because they are being substituted for. This 13993 saves searching in the most common cases. 13994 13995 Each note in the list is either ignored or placed on some insns, depending 13996 on the type of note. */ 13997 13998 static void 13999 distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2, 14000 rtx elim_i2, rtx elim_i1, rtx elim_i0) 14001 { 14002 rtx note, next_note; 14003 rtx tem_note; 14004 rtx_insn *tem_insn; 14005 14006 for (note = notes; note; note = next_note) 14007 { 14008 rtx_insn *place = 0, *place2 = 0; 14009 14010 next_note = XEXP (note, 1); 14011 switch (REG_NOTE_KIND (note)) 14012 { 14013 case REG_BR_PROB: 14014 case REG_BR_PRED: 14015 /* Doesn't matter much where we put this, as long as it's somewhere. 14016 It is preferable to keep these notes on branches, which is most 14017 likely to be i3. */ 14018 place = i3; 14019 break; 14020 14021 case REG_NON_LOCAL_GOTO: 14022 if (JUMP_P (i3)) 14023 place = i3; 14024 else 14025 { 14026 gcc_assert (i2 && JUMP_P (i2)); 14027 place = i2; 14028 } 14029 break; 14030 14031 case REG_EH_REGION: 14032 /* These notes must remain with the call or trapping instruction. */ 14033 if (CALL_P (i3)) 14034 place = i3; 14035 else if (i2 && CALL_P (i2)) 14036 place = i2; 14037 else 14038 { 14039 gcc_assert (cfun->can_throw_non_call_exceptions); 14040 if (may_trap_p (i3)) 14041 place = i3; 14042 else if (i2 && may_trap_p (i2)) 14043 place = i2; 14044 /* ??? Otherwise assume we've combined things such that we 14045 can now prove that the instructions can't trap. Drop the 14046 note in this case. */ 14047 } 14048 break; 14049 14050 case REG_ARGS_SIZE: 14051 /* ??? How to distribute between i3-i1. Assume i3 contains the 14052 entire adjustment. Assert i3 contains at least some adjust. */ 14053 if (!noop_move_p (i3)) 14054 { 14055 int old_size, args_size = INTVAL (XEXP (note, 0)); 14056 /* fixup_args_size_notes looks at REG_NORETURN note, 14057 so ensure the note is placed there first. */ 14058 if (CALL_P (i3)) 14059 { 14060 rtx *np; 14061 for (np = &next_note; *np; np = &XEXP (*np, 1)) 14062 if (REG_NOTE_KIND (*np) == REG_NORETURN) 14063 { 14064 rtx n = *np; 14065 *np = XEXP (n, 1); 14066 XEXP (n, 1) = REG_NOTES (i3); 14067 REG_NOTES (i3) = n; 14068 break; 14069 } 14070 } 14071 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size); 14072 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS 14073 REG_ARGS_SIZE note to all noreturn calls, allow that here. */ 14074 gcc_assert (old_size != args_size 14075 || (CALL_P (i3) 14076 && !ACCUMULATE_OUTGOING_ARGS 14077 && find_reg_note (i3, REG_NORETURN, NULL_RTX))); 14078 } 14079 break; 14080 14081 case REG_NORETURN: 14082 case REG_SETJMP: 14083 case REG_TM: 14084 case REG_CALL_DECL: 14085 /* These notes must remain with the call. It should not be 14086 possible for both I2 and I3 to be a call. */ 14087 if (CALL_P (i3)) 14088 place = i3; 14089 else 14090 { 14091 gcc_assert (i2 && CALL_P (i2)); 14092 place = i2; 14093 } 14094 break; 14095 14096 case REG_UNUSED: 14097 /* Any clobbers for i3 may still exist, and so we must process 14098 REG_UNUSED notes from that insn. 14099 14100 Any clobbers from i2 or i1 can only exist if they were added by 14101 recog_for_combine. In that case, recog_for_combine created the 14102 necessary REG_UNUSED notes. Trying to keep any original 14103 REG_UNUSED notes from these insns can cause incorrect output 14104 if it is for the same register as the original i3 dest. 14105 In that case, we will notice that the register is set in i3, 14106 and then add a REG_UNUSED note for the destination of i3, which 14107 is wrong. However, it is possible to have REG_UNUSED notes from 14108 i2 or i1 for register which were both used and clobbered, so 14109 we keep notes from i2 or i1 if they will turn into REG_DEAD 14110 notes. */ 14111 14112 /* If this register is set or clobbered in I3, put the note there 14113 unless there is one already. */ 14114 if (reg_set_p (XEXP (note, 0), PATTERN (i3))) 14115 { 14116 if (from_insn != i3) 14117 break; 14118 14119 if (! (REG_P (XEXP (note, 0)) 14120 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) 14121 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) 14122 place = i3; 14123 } 14124 /* Otherwise, if this register is used by I3, then this register 14125 now dies here, so we must put a REG_DEAD note here unless there 14126 is one already. */ 14127 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) 14128 && ! (REG_P (XEXP (note, 0)) 14129 ? find_regno_note (i3, REG_DEAD, 14130 REGNO (XEXP (note, 0))) 14131 : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) 14132 { 14133 PUT_REG_NOTE_KIND (note, REG_DEAD); 14134 place = i3; 14135 } 14136 break; 14137 14138 case REG_EQUAL: 14139 case REG_EQUIV: 14140 case REG_NOALIAS: 14141 /* These notes say something about results of an insn. We can 14142 only support them if they used to be on I3 in which case they 14143 remain on I3. Otherwise they are ignored. 14144 14145 If the note refers to an expression that is not a constant, we 14146 must also ignore the note since we cannot tell whether the 14147 equivalence is still true. It might be possible to do 14148 slightly better than this (we only have a problem if I2DEST 14149 or I1DEST is present in the expression), but it doesn't 14150 seem worth the trouble. */ 14151 14152 if (from_insn == i3 14153 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) 14154 place = i3; 14155 break; 14156 14157 case REG_INC: 14158 /* These notes say something about how a register is used. They must 14159 be present on any use of the register in I2 or I3. */ 14160 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) 14161 place = i3; 14162 14163 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) 14164 { 14165 if (place) 14166 place2 = i2; 14167 else 14168 place = i2; 14169 } 14170 break; 14171 14172 case REG_LABEL_TARGET: 14173 case REG_LABEL_OPERAND: 14174 /* This can show up in several ways -- either directly in the 14175 pattern, or hidden off in the constant pool with (or without?) 14176 a REG_EQUAL note. */ 14177 /* ??? Ignore the without-reg_equal-note problem for now. */ 14178 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) 14179 || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX)) 14180 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF 14181 && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))) 14182 place = i3; 14183 14184 if (i2 14185 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) 14186 || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX)) 14187 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF 14188 && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))) 14189 { 14190 if (place) 14191 place2 = i2; 14192 else 14193 place = i2; 14194 } 14195 14196 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note 14197 as a JUMP_LABEL or decrement LABEL_NUSES if it's already 14198 there. */ 14199 if (place && JUMP_P (place) 14200 && REG_NOTE_KIND (note) == REG_LABEL_TARGET 14201 && (JUMP_LABEL (place) == NULL 14202 || JUMP_LABEL (place) == XEXP (note, 0))) 14203 { 14204 rtx label = JUMP_LABEL (place); 14205 14206 if (!label) 14207 JUMP_LABEL (place) = XEXP (note, 0); 14208 else if (LABEL_P (label)) 14209 LABEL_NUSES (label)--; 14210 } 14211 14212 if (place2 && JUMP_P (place2) 14213 && REG_NOTE_KIND (note) == REG_LABEL_TARGET 14214 && (JUMP_LABEL (place2) == NULL 14215 || JUMP_LABEL (place2) == XEXP (note, 0))) 14216 { 14217 rtx label = JUMP_LABEL (place2); 14218 14219 if (!label) 14220 JUMP_LABEL (place2) = XEXP (note, 0); 14221 else if (LABEL_P (label)) 14222 LABEL_NUSES (label)--; 14223 place2 = 0; 14224 } 14225 break; 14226 14227 case REG_NONNEG: 14228 /* This note says something about the value of a register prior 14229 to the execution of an insn. It is too much trouble to see 14230 if the note is still correct in all situations. It is better 14231 to simply delete it. */ 14232 break; 14233 14234 case REG_DEAD: 14235 /* If we replaced the right hand side of FROM_INSN with a 14236 REG_EQUAL note, the original use of the dying register 14237 will not have been combined into I3 and I2. In such cases, 14238 FROM_INSN is guaranteed to be the first of the combined 14239 instructions, so we simply need to search back before 14240 FROM_INSN for the previous use or set of this register, 14241 then alter the notes there appropriately. 14242 14243 If the register is used as an input in I3, it dies there. 14244 Similarly for I2, if it is nonzero and adjacent to I3. 14245 14246 If the register is not used as an input in either I3 or I2 14247 and it is not one of the registers we were supposed to eliminate, 14248 there are two possibilities. We might have a non-adjacent I2 14249 or we might have somehow eliminated an additional register 14250 from a computation. For example, we might have had A & B where 14251 we discover that B will always be zero. In this case we will 14252 eliminate the reference to A. 14253 14254 In both cases, we must search to see if we can find a previous 14255 use of A and put the death note there. */ 14256 14257 if (from_insn 14258 && from_insn == i2mod 14259 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs)) 14260 tem_insn = from_insn; 14261 else 14262 { 14263 if (from_insn 14264 && CALL_P (from_insn) 14265 && find_reg_fusage (from_insn, USE, XEXP (note, 0))) 14266 place = from_insn; 14267 else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2))) 14268 { 14269 /* If the new I2 sets the same register that is marked 14270 dead in the note, we do not in general know where to 14271 put the note. One important case we _can_ handle is 14272 when the note comes from I3. */ 14273 if (from_insn == i3) 14274 place = i3; 14275 else 14276 break; 14277 } 14278 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) 14279 place = i3; 14280 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3 14281 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 14282 place = i2; 14283 else if ((rtx_equal_p (XEXP (note, 0), elim_i2) 14284 && !(i2mod 14285 && reg_overlap_mentioned_p (XEXP (note, 0), 14286 i2mod_old_rhs))) 14287 || rtx_equal_p (XEXP (note, 0), elim_i1) 14288 || rtx_equal_p (XEXP (note, 0), elim_i0)) 14289 break; 14290 tem_insn = i3; 14291 } 14292 14293 if (place == 0) 14294 { 14295 basic_block bb = this_basic_block; 14296 14297 for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn)) 14298 { 14299 if (!NONDEBUG_INSN_P (tem_insn)) 14300 { 14301 if (tem_insn == BB_HEAD (bb)) 14302 break; 14303 continue; 14304 } 14305 14306 /* If the register is being set at TEM_INSN, see if that is all 14307 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this 14308 into a REG_UNUSED note instead. Don't delete sets to 14309 global register vars. */ 14310 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER 14311 || !global_regs[REGNO (XEXP (note, 0))]) 14312 && reg_set_p (XEXP (note, 0), PATTERN (tem_insn))) 14313 { 14314 rtx set = single_set (tem_insn); 14315 rtx inner_dest = 0; 14316 rtx_insn *cc0_setter = NULL; 14317 14318 if (set != 0) 14319 for (inner_dest = SET_DEST (set); 14320 (GET_CODE (inner_dest) == STRICT_LOW_PART 14321 || GET_CODE (inner_dest) == SUBREG 14322 || GET_CODE (inner_dest) == ZERO_EXTRACT); 14323 inner_dest = XEXP (inner_dest, 0)) 14324 ; 14325 14326 /* Verify that it was the set, and not a clobber that 14327 modified the register. 14328 14329 CC0 targets must be careful to maintain setter/user 14330 pairs. If we cannot delete the setter due to side 14331 effects, mark the user with an UNUSED note instead 14332 of deleting it. */ 14333 14334 if (set != 0 && ! side_effects_p (SET_SRC (set)) 14335 && rtx_equal_p (XEXP (note, 0), inner_dest) 14336 && (!HAVE_cc0 14337 || (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) 14338 || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL 14339 && sets_cc0_p (PATTERN (cc0_setter)) > 0)))) 14340 { 14341 /* Move the notes and links of TEM_INSN elsewhere. 14342 This might delete other dead insns recursively. 14343 First set the pattern to something that won't use 14344 any register. */ 14345 rtx old_notes = REG_NOTES (tem_insn); 14346 14347 PATTERN (tem_insn) = pc_rtx; 14348 REG_NOTES (tem_insn) = NULL; 14349 14350 distribute_notes (old_notes, tem_insn, tem_insn, NULL, 14351 NULL_RTX, NULL_RTX, NULL_RTX); 14352 distribute_links (LOG_LINKS (tem_insn)); 14353 14354 unsigned int regno = REGNO (XEXP (note, 0)); 14355 reg_stat_type *rsp = ®_stat[regno]; 14356 if (rsp->last_set == tem_insn) 14357 record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX); 14358 14359 SET_INSN_DELETED (tem_insn); 14360 if (tem_insn == i2) 14361 i2 = NULL; 14362 14363 /* Delete the setter too. */ 14364 if (cc0_setter) 14365 { 14366 PATTERN (cc0_setter) = pc_rtx; 14367 old_notes = REG_NOTES (cc0_setter); 14368 REG_NOTES (cc0_setter) = NULL; 14369 14370 distribute_notes (old_notes, cc0_setter, 14371 cc0_setter, NULL, 14372 NULL_RTX, NULL_RTX, NULL_RTX); 14373 distribute_links (LOG_LINKS (cc0_setter)); 14374 14375 SET_INSN_DELETED (cc0_setter); 14376 if (cc0_setter == i2) 14377 i2 = NULL; 14378 } 14379 } 14380 else 14381 { 14382 PUT_REG_NOTE_KIND (note, REG_UNUSED); 14383 14384 /* If there isn't already a REG_UNUSED note, put one 14385 here. Do not place a REG_DEAD note, even if 14386 the register is also used here; that would not 14387 match the algorithm used in lifetime analysis 14388 and can cause the consistency check in the 14389 scheduler to fail. */ 14390 if (! find_regno_note (tem_insn, REG_UNUSED, 14391 REGNO (XEXP (note, 0)))) 14392 place = tem_insn; 14393 break; 14394 } 14395 } 14396 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn)) 14397 || (CALL_P (tem_insn) 14398 && find_reg_fusage (tem_insn, USE, XEXP (note, 0)))) 14399 { 14400 place = tem_insn; 14401 14402 /* If we are doing a 3->2 combination, and we have a 14403 register which formerly died in i3 and was not used 14404 by i2, which now no longer dies in i3 and is used in 14405 i2 but does not die in i2, and place is between i2 14406 and i3, then we may need to move a link from place to 14407 i2. */ 14408 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2) 14409 && from_insn 14410 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2) 14411 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 14412 { 14413 struct insn_link *links = LOG_LINKS (place); 14414 LOG_LINKS (place) = NULL; 14415 distribute_links (links); 14416 } 14417 break; 14418 } 14419 14420 if (tem_insn == BB_HEAD (bb)) 14421 break; 14422 } 14423 14424 } 14425 14426 /* If the register is set or already dead at PLACE, we needn't do 14427 anything with this note if it is still a REG_DEAD note. 14428 We check here if it is set at all, not if is it totally replaced, 14429 which is what `dead_or_set_p' checks, so also check for it being 14430 set partially. */ 14431 14432 if (place && REG_NOTE_KIND (note) == REG_DEAD) 14433 { 14434 unsigned int regno = REGNO (XEXP (note, 0)); 14435 reg_stat_type *rsp = ®_stat[regno]; 14436 14437 if (dead_or_set_p (place, XEXP (note, 0)) 14438 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) 14439 { 14440 /* Unless the register previously died in PLACE, clear 14441 last_death. [I no longer understand why this is 14442 being done.] */ 14443 if (rsp->last_death != place) 14444 rsp->last_death = 0; 14445 place = 0; 14446 } 14447 else 14448 rsp->last_death = place; 14449 14450 /* If this is a death note for a hard reg that is occupying 14451 multiple registers, ensure that we are still using all 14452 parts of the object. If we find a piece of the object 14453 that is unused, we must arrange for an appropriate REG_DEAD 14454 note to be added for it. However, we can't just emit a USE 14455 and tag the note to it, since the register might actually 14456 be dead; so we recourse, and the recursive call then finds 14457 the previous insn that used this register. */ 14458 14459 if (place && REG_NREGS (XEXP (note, 0)) > 1) 14460 { 14461 unsigned int endregno = END_REGNO (XEXP (note, 0)); 14462 bool all_used = true; 14463 unsigned int i; 14464 14465 for (i = regno; i < endregno; i++) 14466 if ((! refers_to_regno_p (i, PATTERN (place)) 14467 && ! find_regno_fusage (place, USE, i)) 14468 || dead_or_set_regno_p (place, i)) 14469 { 14470 all_used = false; 14471 break; 14472 } 14473 14474 if (! all_used) 14475 { 14476 /* Put only REG_DEAD notes for pieces that are 14477 not already dead or set. */ 14478 14479 for (i = regno; i < endregno; 14480 i += hard_regno_nregs[i][reg_raw_mode[i]]) 14481 { 14482 rtx piece = regno_reg_rtx[i]; 14483 basic_block bb = this_basic_block; 14484 14485 if (! dead_or_set_p (place, piece) 14486 && ! reg_bitfield_target_p (piece, 14487 PATTERN (place))) 14488 { 14489 rtx new_note = alloc_reg_note (REG_DEAD, piece, 14490 NULL_RTX); 14491 14492 distribute_notes (new_note, place, place, 14493 NULL, NULL_RTX, NULL_RTX, 14494 NULL_RTX); 14495 } 14496 else if (! refers_to_regno_p (i, PATTERN (place)) 14497 && ! find_regno_fusage (place, USE, i)) 14498 for (tem_insn = PREV_INSN (place); ; 14499 tem_insn = PREV_INSN (tem_insn)) 14500 { 14501 if (!NONDEBUG_INSN_P (tem_insn)) 14502 { 14503 if (tem_insn == BB_HEAD (bb)) 14504 break; 14505 continue; 14506 } 14507 if (dead_or_set_p (tem_insn, piece) 14508 || reg_bitfield_target_p (piece, 14509 PATTERN (tem_insn))) 14510 { 14511 add_reg_note (tem_insn, REG_UNUSED, piece); 14512 break; 14513 } 14514 } 14515 } 14516 14517 place = 0; 14518 } 14519 } 14520 } 14521 break; 14522 14523 default: 14524 /* Any other notes should not be present at this point in the 14525 compilation. */ 14526 gcc_unreachable (); 14527 } 14528 14529 if (place) 14530 { 14531 XEXP (note, 1) = REG_NOTES (place); 14532 REG_NOTES (place) = note; 14533 } 14534 14535 if (place2) 14536 add_shallow_copy_of_reg_note (place2, note); 14537 } 14538 } 14539 14540 /* Similarly to above, distribute the LOG_LINKS that used to be present on 14541 I3, I2, and I1 to new locations. This is also called to add a link 14542 pointing at I3 when I3's destination is changed. */ 14543 14544 static void 14545 distribute_links (struct insn_link *links) 14546 { 14547 struct insn_link *link, *next_link; 14548 14549 for (link = links; link; link = next_link) 14550 { 14551 rtx_insn *place = 0; 14552 rtx_insn *insn; 14553 rtx set, reg; 14554 14555 next_link = link->next; 14556 14557 /* If the insn that this link points to is a NOTE, ignore it. */ 14558 if (NOTE_P (link->insn)) 14559 continue; 14560 14561 set = 0; 14562 rtx pat = PATTERN (link->insn); 14563 if (GET_CODE (pat) == SET) 14564 set = pat; 14565 else if (GET_CODE (pat) == PARALLEL) 14566 { 14567 int i; 14568 for (i = 0; i < XVECLEN (pat, 0); i++) 14569 { 14570 set = XVECEXP (pat, 0, i); 14571 if (GET_CODE (set) != SET) 14572 continue; 14573 14574 reg = SET_DEST (set); 14575 while (GET_CODE (reg) == ZERO_EXTRACT 14576 || GET_CODE (reg) == STRICT_LOW_PART 14577 || GET_CODE (reg) == SUBREG) 14578 reg = XEXP (reg, 0); 14579 14580 if (!REG_P (reg)) 14581 continue; 14582 14583 if (REGNO (reg) == link->regno) 14584 break; 14585 } 14586 if (i == XVECLEN (pat, 0)) 14587 continue; 14588 } 14589 else 14590 continue; 14591 14592 reg = SET_DEST (set); 14593 14594 while (GET_CODE (reg) == ZERO_EXTRACT 14595 || GET_CODE (reg) == STRICT_LOW_PART 14596 || GET_CODE (reg) == SUBREG) 14597 reg = XEXP (reg, 0); 14598 14599 /* A LOG_LINK is defined as being placed on the first insn that uses 14600 a register and points to the insn that sets the register. Start 14601 searching at the next insn after the target of the link and stop 14602 when we reach a set of the register or the end of the basic block. 14603 14604 Note that this correctly handles the link that used to point from 14605 I3 to I2. Also note that not much searching is typically done here 14606 since most links don't point very far away. */ 14607 14608 for (insn = NEXT_INSN (link->insn); 14609 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 14610 || BB_HEAD (this_basic_block->next_bb) != insn)); 14611 insn = NEXT_INSN (insn)) 14612 if (DEBUG_INSN_P (insn)) 14613 continue; 14614 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) 14615 { 14616 if (reg_referenced_p (reg, PATTERN (insn))) 14617 place = insn; 14618 break; 14619 } 14620 else if (CALL_P (insn) 14621 && find_reg_fusage (insn, USE, reg)) 14622 { 14623 place = insn; 14624 break; 14625 } 14626 else if (INSN_P (insn) && reg_set_p (reg, insn)) 14627 break; 14628 14629 /* If we found a place to put the link, place it there unless there 14630 is already a link to the same insn as LINK at that point. */ 14631 14632 if (place) 14633 { 14634 struct insn_link *link2; 14635 14636 FOR_EACH_LOG_LINK (link2, place) 14637 if (link2->insn == link->insn && link2->regno == link->regno) 14638 break; 14639 14640 if (link2 == NULL) 14641 { 14642 link->next = LOG_LINKS (place); 14643 LOG_LINKS (place) = link; 14644 14645 /* Set added_links_insn to the earliest insn we added a 14646 link to. */ 14647 if (added_links_insn == 0 14648 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place)) 14649 added_links_insn = place; 14650 } 14651 } 14652 } 14653 } 14654 14655 /* Check for any register or memory mentioned in EQUIV that is not 14656 mentioned in EXPR. This is used to restrict EQUIV to "specializations" 14657 of EXPR where some registers may have been replaced by constants. */ 14658 14659 static bool 14660 unmentioned_reg_p (rtx equiv, rtx expr) 14661 { 14662 subrtx_iterator::array_type array; 14663 FOR_EACH_SUBRTX (iter, array, equiv, NONCONST) 14664 { 14665 const_rtx x = *iter; 14666 if ((REG_P (x) || MEM_P (x)) 14667 && !reg_mentioned_p (x, expr)) 14668 return true; 14669 } 14670 return false; 14671 } 14672 14673 DEBUG_FUNCTION void 14674 dump_combine_stats (FILE *file) 14675 { 14676 fprintf 14677 (file, 14678 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", 14679 combine_attempts, combine_merges, combine_extras, combine_successes); 14680 } 14681 14682 void 14683 dump_combine_total_stats (FILE *file) 14684 { 14685 fprintf 14686 (file, 14687 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", 14688 total_attempts, total_merges, total_extras, total_successes); 14689 } 14690 14691 /* Try combining insns through substitution. */ 14692 static unsigned int 14693 rest_of_handle_combine (void) 14694 { 14695 int rebuild_jump_labels_after_combine; 14696 14697 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN); 14698 df_note_add_problem (); 14699 df_analyze (); 14700 14701 regstat_init_n_sets_and_refs (); 14702 reg_n_sets_max = max_reg_num (); 14703 14704 rebuild_jump_labels_after_combine 14705 = combine_instructions (get_insns (), max_reg_num ()); 14706 14707 /* Combining insns may have turned an indirect jump into a 14708 direct jump. Rebuild the JUMP_LABEL fields of jumping 14709 instructions. */ 14710 if (rebuild_jump_labels_after_combine) 14711 { 14712 if (dom_info_available_p (CDI_DOMINATORS)) 14713 free_dominance_info (CDI_DOMINATORS); 14714 timevar_push (TV_JUMP); 14715 rebuild_jump_labels (get_insns ()); 14716 cleanup_cfg (0); 14717 timevar_pop (TV_JUMP); 14718 } 14719 14720 regstat_free_n_sets_and_refs (); 14721 return 0; 14722 } 14723 14724 namespace { 14725 14726 const pass_data pass_data_combine = 14727 { 14728 RTL_PASS, /* type */ 14729 "combine", /* name */ 14730 OPTGROUP_NONE, /* optinfo_flags */ 14731 TV_COMBINE, /* tv_id */ 14732 PROP_cfglayout, /* properties_required */ 14733 0, /* properties_provided */ 14734 0, /* properties_destroyed */ 14735 0, /* todo_flags_start */ 14736 TODO_df_finish, /* todo_flags_finish */ 14737 }; 14738 14739 class pass_combine : public rtl_opt_pass 14740 { 14741 public: 14742 pass_combine (gcc::context *ctxt) 14743 : rtl_opt_pass (pass_data_combine, ctxt) 14744 {} 14745 14746 /* opt_pass methods: */ 14747 virtual bool gate (function *) { return (optimize > 0); } 14748 virtual unsigned int execute (function *) 14749 { 14750 return rest_of_handle_combine (); 14751 } 14752 14753 }; // class pass_combine 14754 14755 } // anon namespace 14756 14757 rtl_opt_pass * 14758 make_pass_combine (gcc::context *ctxt) 14759 { 14760 return new pass_combine (ctxt); 14761 } 14762