1 /* Optimize by combining instructions for GNU compiler. 2 Copyright (C) 1987-2020 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 /* This module is essentially the "combiner" phase of the U. of Arizona 21 Portable Optimizer, but redone to work on our list-structured 22 representation for RTL instead of their string representation. 23 24 The LOG_LINKS of each insn identify the most recent assignment 25 to each REG used in the insn. It is a list of previous insns, 26 each of which contains a SET for a REG that is used in this insn 27 and not used or set in between. LOG_LINKs never cross basic blocks. 28 They were set up by the preceding pass (lifetime analysis). 29 30 We try to combine each pair of insns joined by a logical link. 31 We also try to combine triplets of insns A, B and C when C has 32 a link back to B and B has a link back to A. Likewise for a 33 small number of quadruplets of insns A, B, C and D for which 34 there's high likelihood of success. 35 36 LOG_LINKS does not have links for use of the CC0. They don't 37 need to, because the insn that sets the CC0 is always immediately 38 before the insn that tests it. So we always regard a branch 39 insn as having a logical link to the preceding insn. The same is true 40 for an insn explicitly using CC0. 41 42 We check (with modified_between_p) to avoid combining in such a way 43 as to move a computation to a place where its value would be different. 44 45 Combination is done by mathematically substituting the previous 46 insn(s) values for the regs they set into the expressions in 47 the later insns that refer to these regs. If the result is a valid insn 48 for our target machine, according to the machine description, 49 we install it, delete the earlier insns, and update the data flow 50 information (LOG_LINKS and REG_NOTES) for what we did. 51 52 There are a few exceptions where the dataflow information isn't 53 completely updated (however this is only a local issue since it is 54 regenerated before the next pass that uses it): 55 56 - reg_live_length is not updated 57 - reg_n_refs is not adjusted in the rare case when a register is 58 no longer required in a computation 59 - there are extremely rare cases (see distribute_notes) when a 60 REG_DEAD note is lost 61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be 62 removed because there is no way to know which register it was 63 linking 64 65 To simplify substitution, we combine only when the earlier insn(s) 66 consist of only a single assignment. To simplify updating afterward, 67 we never combine when a subroutine call appears in the middle. 68 69 Since we do not represent assignments to CC0 explicitly except when that 70 is all an insn does, there is no LOG_LINKS entry in an insn that uses 71 the condition code for the insn that set the condition code. 72 Fortunately, these two insns must be consecutive. 73 Therefore, every JUMP_INSN is taken to have an implicit logical link 74 to the preceding insn. This is not quite right, since non-jumps can 75 also use the condition code; but in practice such insns would not 76 combine anyway. */ 77 78 #include "config.h" 79 #include "system.h" 80 #include "coretypes.h" 81 #include "backend.h" 82 #include "target.h" 83 #include "rtl.h" 84 #include "tree.h" 85 #include "cfghooks.h" 86 #include "predict.h" 87 #include "df.h" 88 #include "memmodel.h" 89 #include "tm_p.h" 90 #include "optabs.h" 91 #include "regs.h" 92 #include "emit-rtl.h" 93 #include "recog.h" 94 #include "cgraph.h" 95 #include "stor-layout.h" 96 #include "cfgrtl.h" 97 #include "cfgcleanup.h" 98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ 99 #include "explow.h" 100 #include "insn-attr.h" 101 #include "rtlhooks-def.h" 102 #include "expr.h" 103 #include "tree-pass.h" 104 #include "valtrack.h" 105 #include "rtl-iter.h" 106 #include "print-rtl.h" 107 #include "function-abi.h" 108 109 /* Number of attempts to combine instructions in this function. */ 110 111 static int combine_attempts; 112 113 /* Number of attempts that got as far as substitution in this function. */ 114 115 static int combine_merges; 116 117 /* Number of instructions combined with added SETs in this function. */ 118 119 static int combine_extras; 120 121 /* Number of instructions combined in this function. */ 122 123 static int combine_successes; 124 125 /* Totals over entire compilation. */ 126 127 static int total_attempts, total_merges, total_extras, total_successes; 128 129 /* combine_instructions may try to replace the right hand side of the 130 second instruction with the value of an associated REG_EQUAL note 131 before throwing it at try_combine. That is problematic when there 132 is a REG_DEAD note for a register used in the old right hand side 133 and can cause distribute_notes to do wrong things. This is the 134 second instruction if it has been so modified, null otherwise. */ 135 136 static rtx_insn *i2mod; 137 138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */ 139 140 static rtx i2mod_old_rhs; 141 142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */ 143 144 static rtx i2mod_new_rhs; 145 146 struct reg_stat_type { 147 /* Record last point of death of (hard or pseudo) register n. */ 148 rtx_insn *last_death; 149 150 /* Record last point of modification of (hard or pseudo) register n. */ 151 rtx_insn *last_set; 152 153 /* The next group of fields allows the recording of the last value assigned 154 to (hard or pseudo) register n. We use this information to see if an 155 operation being processed is redundant given a prior operation performed 156 on the register. For example, an `and' with a constant is redundant if 157 all the zero bits are already known to be turned off. 158 159 We use an approach similar to that used by cse, but change it in the 160 following ways: 161 162 (1) We do not want to reinitialize at each label. 163 (2) It is useful, but not critical, to know the actual value assigned 164 to a register. Often just its form is helpful. 165 166 Therefore, we maintain the following fields: 167 168 last_set_value the last value assigned 169 last_set_label records the value of label_tick when the 170 register was assigned 171 last_set_table_tick records the value of label_tick when a 172 value using the register is assigned 173 last_set_invalid set to nonzero when it is not valid 174 to use the value of this register in some 175 register's value 176 177 To understand the usage of these tables, it is important to understand 178 the distinction between the value in last_set_value being valid and 179 the register being validly contained in some other expression in the 180 table. 181 182 (The next two parameters are out of date). 183 184 reg_stat[i].last_set_value is valid if it is nonzero, and either 185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick. 186 187 Register I may validly appear in any expression returned for the value 188 of another register if reg_n_sets[i] is 1. It may also appear in the 189 value for register J if reg_stat[j].last_set_invalid is zero, or 190 reg_stat[i].last_set_label < reg_stat[j].last_set_label. 191 192 If an expression is found in the table containing a register which may 193 not validly appear in an expression, the register is replaced by 194 something that won't match, (clobber (const_int 0)). */ 195 196 /* Record last value assigned to (hard or pseudo) register n. */ 197 198 rtx last_set_value; 199 200 /* Record the value of label_tick when an expression involving register n 201 is placed in last_set_value. */ 202 203 int last_set_table_tick; 204 205 /* Record the value of label_tick when the value for register n is placed in 206 last_set_value. */ 207 208 int last_set_label; 209 210 /* These fields are maintained in parallel with last_set_value and are 211 used to store the mode in which the register was last set, the bits 212 that were known to be zero when it was last set, and the number of 213 sign bits copies it was known to have when it was last set. */ 214 215 unsigned HOST_WIDE_INT last_set_nonzero_bits; 216 char last_set_sign_bit_copies; 217 ENUM_BITFIELD(machine_mode) last_set_mode : 8; 218 219 /* Set nonzero if references to register n in expressions should not be 220 used. last_set_invalid is set nonzero when this register is being 221 assigned to and last_set_table_tick == label_tick. */ 222 223 char last_set_invalid; 224 225 /* Some registers that are set more than once and used in more than one 226 basic block are nevertheless always set in similar ways. For example, 227 a QImode register may be loaded from memory in two places on a machine 228 where byte loads zero extend. 229 230 We record in the following fields if a register has some leading bits 231 that are always equal to the sign bit, and what we know about the 232 nonzero bits of a register, specifically which bits are known to be 233 zero. 234 235 If an entry is zero, it means that we don't know anything special. */ 236 237 unsigned char sign_bit_copies; 238 239 unsigned HOST_WIDE_INT nonzero_bits; 240 241 /* Record the value of the label_tick when the last truncation 242 happened. The field truncated_to_mode is only valid if 243 truncation_label == label_tick. */ 244 245 int truncation_label; 246 247 /* Record the last truncation seen for this register. If truncation 248 is not a nop to this mode we might be able to save an explicit 249 truncation if we know that value already contains a truncated 250 value. */ 251 252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8; 253 }; 254 255 256 static vec<reg_stat_type> reg_stat; 257 258 /* One plus the highest pseudo for which we track REG_N_SETS. 259 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once, 260 but during combine_split_insns new pseudos can be created. As we don't have 261 updated DF information in that case, it is hard to initialize the array 262 after growing. The combiner only cares about REG_N_SETS (regno) == 1, 263 so instead of growing the arrays, just assume all newly created pseudos 264 during combine might be set multiple times. */ 265 266 static unsigned int reg_n_sets_max; 267 268 /* Record the luid of the last insn that invalidated memory 269 (anything that writes memory, and subroutine calls, but not pushes). */ 270 271 static int mem_last_set; 272 273 /* Record the luid of the last CALL_INSN 274 so we can tell whether a potential combination crosses any calls. */ 275 276 static int last_call_luid; 277 278 /* When `subst' is called, this is the insn that is being modified 279 (by combining in a previous insn). The PATTERN of this insn 280 is still the old pattern partially modified and it should not be 281 looked at, but this may be used to examine the successors of the insn 282 to judge whether a simplification is valid. */ 283 284 static rtx_insn *subst_insn; 285 286 /* This is the lowest LUID that `subst' is currently dealing with. 287 get_last_value will not return a value if the register was set at or 288 after this LUID. If not for this mechanism, we could get confused if 289 I2 or I1 in try_combine were an insn that used the old value of a register 290 to obtain a new value. In that case, we might erroneously get the 291 new value of the register when we wanted the old one. */ 292 293 static int subst_low_luid; 294 295 /* This contains any hard registers that are used in newpat; reg_dead_at_p 296 must consider all these registers to be always live. */ 297 298 static HARD_REG_SET newpat_used_regs; 299 300 /* This is an insn to which a LOG_LINKS entry has been added. If this 301 insn is the earlier than I2 or I3, combine should rescan starting at 302 that location. */ 303 304 static rtx_insn *added_links_insn; 305 306 /* And similarly, for notes. */ 307 308 static rtx_insn *added_notes_insn; 309 310 /* Basic block in which we are performing combines. */ 311 static basic_block this_basic_block; 312 static bool optimize_this_for_speed_p; 313 314 315 /* Length of the currently allocated uid_insn_cost array. */ 316 317 static int max_uid_known; 318 319 /* The following array records the insn_cost for every insn 320 in the instruction stream. */ 321 322 static int *uid_insn_cost; 323 324 /* The following array records the LOG_LINKS for every insn in the 325 instruction stream as struct insn_link pointers. */ 326 327 struct insn_link { 328 rtx_insn *insn; 329 unsigned int regno; 330 struct insn_link *next; 331 }; 332 333 static struct insn_link **uid_log_links; 334 335 static inline int 336 insn_uid_check (const_rtx insn) 337 { 338 int uid = INSN_UID (insn); 339 gcc_checking_assert (uid <= max_uid_known); 340 return uid; 341 } 342 343 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)]) 344 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)]) 345 346 #define FOR_EACH_LOG_LINK(L, INSN) \ 347 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next) 348 349 /* Links for LOG_LINKS are allocated from this obstack. */ 350 351 static struct obstack insn_link_obstack; 352 353 /* Allocate a link. */ 354 355 static inline struct insn_link * 356 alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next) 357 { 358 struct insn_link *l 359 = (struct insn_link *) obstack_alloc (&insn_link_obstack, 360 sizeof (struct insn_link)); 361 l->insn = insn; 362 l->regno = regno; 363 l->next = next; 364 return l; 365 } 366 367 /* Incremented for each basic block. */ 368 369 static int label_tick; 370 371 /* Reset to label_tick for each extended basic block in scanning order. */ 372 373 static int label_tick_ebb_start; 374 375 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the 376 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ 377 378 static scalar_int_mode nonzero_bits_mode; 379 380 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can 381 be safely used. It is zero while computing them and after combine has 382 completed. This former test prevents propagating values based on 383 previously set values, which can be incorrect if a variable is modified 384 in a loop. */ 385 386 static int nonzero_sign_valid; 387 388 389 /* Record one modification to rtl structure 390 to be undone by storing old_contents into *where. */ 391 392 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS }; 393 394 struct undo 395 { 396 struct undo *next; 397 enum undo_kind kind; 398 union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents; 399 union { rtx *r; int *i; int regno; struct insn_link **l; } where; 400 }; 401 402 /* Record a bunch of changes to be undone, up to MAX_UNDO of them. 403 num_undo says how many are currently recorded. 404 405 other_insn is nonzero if we have modified some other insn in the process 406 of working on subst_insn. It must be verified too. */ 407 408 struct undobuf 409 { 410 struct undo *undos; 411 struct undo *frees; 412 rtx_insn *other_insn; 413 }; 414 415 static struct undobuf undobuf; 416 417 /* Number of times the pseudo being substituted for 418 was found and replaced. */ 419 420 static int n_occurrences; 421 422 static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode, 423 scalar_int_mode, 424 unsigned HOST_WIDE_INT *); 425 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode, 426 scalar_int_mode, 427 unsigned int *); 428 static void do_SUBST (rtx *, rtx); 429 static void do_SUBST_INT (int *, int); 430 static void init_reg_last (void); 431 static void setup_incoming_promotions (rtx_insn *); 432 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *); 433 static int cant_combine_insn_p (rtx_insn *); 434 static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *, 435 rtx_insn *, rtx_insn *, rtx *, rtx *); 436 static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *); 437 static int contains_muldiv (rtx); 438 static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *, 439 int *, rtx_insn *); 440 static void undo_all (void); 441 static void undo_commit (void); 442 static rtx *find_split_point (rtx *, rtx_insn *, bool); 443 static rtx subst (rtx, rtx, rtx, int, int, int); 444 static rtx combine_simplify_rtx (rtx, machine_mode, int, int); 445 static rtx simplify_if_then_else (rtx); 446 static rtx simplify_set (rtx); 447 static rtx simplify_logical (rtx); 448 static rtx expand_compound_operation (rtx); 449 static const_rtx expand_field_assignment (const_rtx); 450 static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, 451 rtx, unsigned HOST_WIDE_INT, int, int, int); 452 static int get_pos_from_mask (unsigned HOST_WIDE_INT, 453 unsigned HOST_WIDE_INT *); 454 static rtx canon_reg_for_combine (rtx, rtx); 455 static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode, 456 scalar_int_mode, unsigned HOST_WIDE_INT, int); 457 static rtx force_to_mode (rtx, machine_mode, 458 unsigned HOST_WIDE_INT, int); 459 static rtx if_then_else_cond (rtx, rtx *, rtx *); 460 static rtx known_cond (rtx, enum rtx_code, rtx, rtx); 461 static int rtx_equal_for_field_assignment_p (rtx, rtx, bool = false); 462 static rtx make_field_assignment (rtx); 463 static rtx apply_distributive_law (rtx); 464 static rtx distribute_and_simplify_rtx (rtx, int); 465 static rtx simplify_and_const_int_1 (scalar_int_mode, rtx, 466 unsigned HOST_WIDE_INT); 467 static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx, 468 unsigned HOST_WIDE_INT); 469 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code, 470 HOST_WIDE_INT, machine_mode, int *); 471 static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int); 472 static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx, 473 int); 474 static int recog_for_combine (rtx *, rtx_insn *, rtx *); 475 static rtx gen_lowpart_for_combine (machine_mode, rtx); 476 static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode, 477 rtx, rtx *); 478 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *); 479 static void update_table_tick (rtx); 480 static void record_value_for_reg (rtx, rtx_insn *, rtx); 481 static void check_promoted_subreg (rtx_insn *, rtx); 482 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *); 483 static void record_dead_and_set_regs (rtx_insn *); 484 static int get_last_value_validate (rtx *, rtx_insn *, int, int); 485 static rtx get_last_value (const_rtx); 486 static void reg_dead_at_p_1 (rtx, const_rtx, void *); 487 static int reg_dead_at_p (rtx, rtx_insn *); 488 static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *); 489 static int reg_bitfield_target_p (rtx, rtx); 490 static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx); 491 static void distribute_links (struct insn_link *); 492 static void mark_used_regs_combine (rtx); 493 static void record_promoted_value (rtx_insn *, rtx); 494 static bool unmentioned_reg_p (rtx, rtx); 495 static void record_truncated_values (rtx *, void *); 496 static bool reg_truncated_to_mode (machine_mode, const_rtx); 497 static rtx gen_lowpart_or_truncate (machine_mode, rtx); 498 499 500 /* It is not safe to use ordinary gen_lowpart in combine. 501 See comments in gen_lowpart_for_combine. */ 502 #undef RTL_HOOKS_GEN_LOWPART 503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine 504 505 /* Our implementation of gen_lowpart never emits a new pseudo. */ 506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT 507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine 508 509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS 510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine 511 512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES 513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine 514 515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE 516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode 517 518 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER; 519 520 521 /* Convenience wrapper for the canonicalize_comparison target hook. 522 Target hooks cannot use enum rtx_code. */ 523 static inline void 524 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1, 525 bool op0_preserve_value) 526 { 527 int code_int = (int)*code; 528 targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value); 529 *code = (enum rtx_code)code_int; 530 } 531 532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if 533 PATTERN cannot be split. Otherwise, it returns an insn sequence. 534 This is a wrapper around split_insns which ensures that the 535 reg_stat vector is made larger if the splitter creates a new 536 register. */ 537 538 static rtx_insn * 539 combine_split_insns (rtx pattern, rtx_insn *insn) 540 { 541 rtx_insn *ret; 542 unsigned int nregs; 543 544 ret = split_insns (pattern, insn); 545 nregs = max_reg_num (); 546 if (nregs > reg_stat.length ()) 547 reg_stat.safe_grow_cleared (nregs); 548 return ret; 549 } 550 551 /* This is used by find_single_use to locate an rtx in LOC that 552 contains exactly one use of DEST, which is typically either a REG 553 or CC0. It returns a pointer to the innermost rtx expression 554 containing DEST. Appearances of DEST that are being used to 555 totally replace it are not counted. */ 556 557 static rtx * 558 find_single_use_1 (rtx dest, rtx *loc) 559 { 560 rtx x = *loc; 561 enum rtx_code code = GET_CODE (x); 562 rtx *result = NULL; 563 rtx *this_result; 564 int i; 565 const char *fmt; 566 567 switch (code) 568 { 569 case CONST: 570 case LABEL_REF: 571 case SYMBOL_REF: 572 CASE_CONST_ANY: 573 case CLOBBER: 574 return 0; 575 576 case SET: 577 /* If the destination is anything other than CC0, PC, a REG or a SUBREG 578 of a REG that occupies all of the REG, the insn uses DEST if 579 it is mentioned in the destination or the source. Otherwise, we 580 need just check the source. */ 581 if (GET_CODE (SET_DEST (x)) != CC0 582 && GET_CODE (SET_DEST (x)) != PC 583 && !REG_P (SET_DEST (x)) 584 && ! (GET_CODE (SET_DEST (x)) == SUBREG 585 && REG_P (SUBREG_REG (SET_DEST (x))) 586 && !read_modify_subreg_p (SET_DEST (x)))) 587 break; 588 589 return find_single_use_1 (dest, &SET_SRC (x)); 590 591 case MEM: 592 case SUBREG: 593 return find_single_use_1 (dest, &XEXP (x, 0)); 594 595 default: 596 break; 597 } 598 599 /* If it wasn't one of the common cases above, check each expression and 600 vector of this code. Look for a unique usage of DEST. */ 601 602 fmt = GET_RTX_FORMAT (code); 603 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 604 { 605 if (fmt[i] == 'e') 606 { 607 if (dest == XEXP (x, i) 608 || (REG_P (dest) && REG_P (XEXP (x, i)) 609 && REGNO (dest) == REGNO (XEXP (x, i)))) 610 this_result = loc; 611 else 612 this_result = find_single_use_1 (dest, &XEXP (x, i)); 613 614 if (result == NULL) 615 result = this_result; 616 else if (this_result) 617 /* Duplicate usage. */ 618 return NULL; 619 } 620 else if (fmt[i] == 'E') 621 { 622 int j; 623 624 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 625 { 626 if (XVECEXP (x, i, j) == dest 627 || (REG_P (dest) 628 && REG_P (XVECEXP (x, i, j)) 629 && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) 630 this_result = loc; 631 else 632 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); 633 634 if (result == NULL) 635 result = this_result; 636 else if (this_result) 637 return NULL; 638 } 639 } 640 } 641 642 return result; 643 } 644 645 646 /* See if DEST, produced in INSN, is used only a single time in the 647 sequel. If so, return a pointer to the innermost rtx expression in which 648 it is used. 649 650 If PLOC is nonzero, *PLOC is set to the insn containing the single use. 651 652 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't 653 care about REG_DEAD notes or LOG_LINKS. 654 655 Otherwise, we find the single use by finding an insn that has a 656 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is 657 only referenced once in that insn, we know that it must be the first 658 and last insn referencing DEST. */ 659 660 static rtx * 661 find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc) 662 { 663 basic_block bb; 664 rtx_insn *next; 665 rtx *result; 666 struct insn_link *link; 667 668 if (dest == cc0_rtx) 669 { 670 next = NEXT_INSN (insn); 671 if (next == 0 672 || (!NONJUMP_INSN_P (next) && !JUMP_P (next))) 673 return 0; 674 675 result = find_single_use_1 (dest, &PATTERN (next)); 676 if (result && ploc) 677 *ploc = next; 678 return result; 679 } 680 681 if (!REG_P (dest)) 682 return 0; 683 684 bb = BLOCK_FOR_INSN (insn); 685 for (next = NEXT_INSN (insn); 686 next && BLOCK_FOR_INSN (next) == bb; 687 next = NEXT_INSN (next)) 688 if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest)) 689 { 690 FOR_EACH_LOG_LINK (link, next) 691 if (link->insn == insn && link->regno == REGNO (dest)) 692 break; 693 694 if (link) 695 { 696 result = find_single_use_1 (dest, &PATTERN (next)); 697 if (ploc) 698 *ploc = next; 699 return result; 700 } 701 } 702 703 return 0; 704 } 705 706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some 707 insn. The substitution can be undone by undo_all. If INTO is already 708 set to NEWVAL, do not record this change. Because computing NEWVAL might 709 also call SUBST, we have to compute it before we put anything into 710 the undo table. */ 711 712 static void 713 do_SUBST (rtx *into, rtx newval) 714 { 715 struct undo *buf; 716 rtx oldval = *into; 717 718 if (oldval == newval) 719 return; 720 721 /* We'd like to catch as many invalid transformations here as 722 possible. Unfortunately, there are way too many mode changes 723 that are perfectly valid, so we'd waste too much effort for 724 little gain doing the checks here. Focus on catching invalid 725 transformations involving integer constants. */ 726 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT 727 && CONST_INT_P (newval)) 728 { 729 /* Sanity check that we're replacing oldval with a CONST_INT 730 that is a valid sign-extension for the original mode. */ 731 gcc_assert (INTVAL (newval) 732 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval))); 733 734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a 735 CONST_INT is not valid, because after the replacement, the 736 original mode would be gone. Unfortunately, we can't tell 737 when do_SUBST is called to replace the operand thereof, so we 738 perform this test on oldval instead, checking whether an 739 invalid replacement took place before we got here. */ 740 gcc_assert (!(GET_CODE (oldval) == SUBREG 741 && CONST_INT_P (SUBREG_REG (oldval)))); 742 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND 743 && CONST_INT_P (XEXP (oldval, 0)))); 744 } 745 746 if (undobuf.frees) 747 buf = undobuf.frees, undobuf.frees = buf->next; 748 else 749 buf = XNEW (struct undo); 750 751 buf->kind = UNDO_RTX; 752 buf->where.r = into; 753 buf->old_contents.r = oldval; 754 *into = newval; 755 756 buf->next = undobuf.undos, undobuf.undos = buf; 757 } 758 759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL)) 760 761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution 762 for the value of a HOST_WIDE_INT value (including CONST_INT) is 763 not safe. */ 764 765 static void 766 do_SUBST_INT (int *into, int newval) 767 { 768 struct undo *buf; 769 int oldval = *into; 770 771 if (oldval == newval) 772 return; 773 774 if (undobuf.frees) 775 buf = undobuf.frees, undobuf.frees = buf->next; 776 else 777 buf = XNEW (struct undo); 778 779 buf->kind = UNDO_INT; 780 buf->where.i = into; 781 buf->old_contents.i = oldval; 782 *into = newval; 783 784 buf->next = undobuf.undos, undobuf.undos = buf; 785 } 786 787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL)) 788 789 /* Similar to SUBST, but just substitute the mode. This is used when 790 changing the mode of a pseudo-register, so that any other 791 references to the entry in the regno_reg_rtx array will change as 792 well. */ 793 794 static void 795 subst_mode (int regno, machine_mode newval) 796 { 797 struct undo *buf; 798 rtx reg = regno_reg_rtx[regno]; 799 machine_mode oldval = GET_MODE (reg); 800 801 if (oldval == newval) 802 return; 803 804 if (undobuf.frees) 805 buf = undobuf.frees, undobuf.frees = buf->next; 806 else 807 buf = XNEW (struct undo); 808 809 buf->kind = UNDO_MODE; 810 buf->where.regno = regno; 811 buf->old_contents.m = oldval; 812 adjust_reg_mode (reg, newval); 813 814 buf->next = undobuf.undos, undobuf.undos = buf; 815 } 816 817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */ 818 819 static void 820 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval) 821 { 822 struct undo *buf; 823 struct insn_link * oldval = *into; 824 825 if (oldval == newval) 826 return; 827 828 if (undobuf.frees) 829 buf = undobuf.frees, undobuf.frees = buf->next; 830 else 831 buf = XNEW (struct undo); 832 833 buf->kind = UNDO_LINKS; 834 buf->where.l = into; 835 buf->old_contents.l = oldval; 836 *into = newval; 837 838 buf->next = undobuf.undos, undobuf.undos = buf; 839 } 840 841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval) 842 843 /* Subroutine of try_combine. Determine whether the replacement patterns 844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost 845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note 846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and 847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost 848 of all the instructions can be estimated and the replacements are more 849 expensive than the original sequence. */ 850 851 static bool 852 combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3, 853 rtx newpat, rtx newi2pat, rtx newotherpat) 854 { 855 int i0_cost, i1_cost, i2_cost, i3_cost; 856 int new_i2_cost, new_i3_cost; 857 int old_cost, new_cost; 858 859 /* Lookup the original insn_costs. */ 860 i2_cost = INSN_COST (i2); 861 i3_cost = INSN_COST (i3); 862 863 if (i1) 864 { 865 i1_cost = INSN_COST (i1); 866 if (i0) 867 { 868 i0_cost = INSN_COST (i0); 869 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0 870 ? i0_cost + i1_cost + i2_cost + i3_cost : 0); 871 } 872 else 873 { 874 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0 875 ? i1_cost + i2_cost + i3_cost : 0); 876 i0_cost = 0; 877 } 878 } 879 else 880 { 881 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0; 882 i1_cost = i0_cost = 0; 883 } 884 885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice; 886 correct that. */ 887 if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2)) 888 old_cost -= i1_cost; 889 890 891 /* Calculate the replacement insn_costs. */ 892 rtx tmp = PATTERN (i3); 893 PATTERN (i3) = newpat; 894 int tmpi = INSN_CODE (i3); 895 INSN_CODE (i3) = -1; 896 new_i3_cost = insn_cost (i3, optimize_this_for_speed_p); 897 PATTERN (i3) = tmp; 898 INSN_CODE (i3) = tmpi; 899 if (newi2pat) 900 { 901 tmp = PATTERN (i2); 902 PATTERN (i2) = newi2pat; 903 tmpi = INSN_CODE (i2); 904 INSN_CODE (i2) = -1; 905 new_i2_cost = insn_cost (i2, optimize_this_for_speed_p); 906 PATTERN (i2) = tmp; 907 INSN_CODE (i2) = tmpi; 908 new_cost = (new_i2_cost > 0 && new_i3_cost > 0) 909 ? new_i2_cost + new_i3_cost : 0; 910 } 911 else 912 { 913 new_cost = new_i3_cost; 914 new_i2_cost = 0; 915 } 916 917 if (undobuf.other_insn) 918 { 919 int old_other_cost, new_other_cost; 920 921 old_other_cost = INSN_COST (undobuf.other_insn); 922 tmp = PATTERN (undobuf.other_insn); 923 PATTERN (undobuf.other_insn) = newotherpat; 924 tmpi = INSN_CODE (undobuf.other_insn); 925 INSN_CODE (undobuf.other_insn) = -1; 926 new_other_cost = insn_cost (undobuf.other_insn, 927 optimize_this_for_speed_p); 928 PATTERN (undobuf.other_insn) = tmp; 929 INSN_CODE (undobuf.other_insn) = tmpi; 930 if (old_other_cost > 0 && new_other_cost > 0) 931 { 932 old_cost += old_other_cost; 933 new_cost += new_other_cost; 934 } 935 else 936 old_cost = 0; 937 } 938 939 /* Disallow this combination if both new_cost and old_cost are greater than 940 zero, and new_cost is greater than old cost. */ 941 int reject = old_cost > 0 && new_cost > old_cost; 942 943 if (dump_file) 944 { 945 fprintf (dump_file, "%s combination of insns ", 946 reject ? "rejecting" : "allowing"); 947 if (i0) 948 fprintf (dump_file, "%d, ", INSN_UID (i0)); 949 if (i1 && INSN_UID (i1) != INSN_UID (i2)) 950 fprintf (dump_file, "%d, ", INSN_UID (i1)); 951 fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3)); 952 953 fprintf (dump_file, "original costs "); 954 if (i0) 955 fprintf (dump_file, "%d + ", i0_cost); 956 if (i1 && INSN_UID (i1) != INSN_UID (i2)) 957 fprintf (dump_file, "%d + ", i1_cost); 958 fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost); 959 960 if (newi2pat) 961 fprintf (dump_file, "replacement costs %d + %d = %d\n", 962 new_i2_cost, new_i3_cost, new_cost); 963 else 964 fprintf (dump_file, "replacement cost %d\n", new_cost); 965 } 966 967 if (reject) 968 return false; 969 970 /* Update the uid_insn_cost array with the replacement costs. */ 971 INSN_COST (i2) = new_i2_cost; 972 INSN_COST (i3) = new_i3_cost; 973 if (i1) 974 { 975 INSN_COST (i1) = 0; 976 if (i0) 977 INSN_COST (i0) = 0; 978 } 979 980 return true; 981 } 982 983 984 /* Delete any insns that copy a register to itself. 985 Return true if the CFG was changed. */ 986 987 static bool 988 delete_noop_moves (void) 989 { 990 rtx_insn *insn, *next; 991 basic_block bb; 992 993 bool edges_deleted = false; 994 995 FOR_EACH_BB_FN (bb, cfun) 996 { 997 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next) 998 { 999 next = NEXT_INSN (insn); 1000 if (INSN_P (insn) && noop_move_p (insn)) 1001 { 1002 if (dump_file) 1003 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn)); 1004 1005 edges_deleted |= delete_insn_and_edges (insn); 1006 } 1007 } 1008 } 1009 1010 return edges_deleted; 1011 } 1012 1013 1014 /* Return false if we do not want to (or cannot) combine DEF. */ 1015 static bool 1016 can_combine_def_p (df_ref def) 1017 { 1018 /* Do not consider if it is pre/post modification in MEM. */ 1019 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY) 1020 return false; 1021 1022 unsigned int regno = DF_REF_REGNO (def); 1023 1024 /* Do not combine frame pointer adjustments. */ 1025 if ((regno == FRAME_POINTER_REGNUM 1026 && (!reload_completed || frame_pointer_needed)) 1027 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER 1028 && regno == HARD_FRAME_POINTER_REGNUM 1029 && (!reload_completed || frame_pointer_needed)) 1030 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 1031 && regno == ARG_POINTER_REGNUM && fixed_regs[regno])) 1032 return false; 1033 1034 return true; 1035 } 1036 1037 /* Return false if we do not want to (or cannot) combine USE. */ 1038 static bool 1039 can_combine_use_p (df_ref use) 1040 { 1041 /* Do not consider the usage of the stack pointer by function call. */ 1042 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE) 1043 return false; 1044 1045 return true; 1046 } 1047 1048 /* Fill in log links field for all insns. */ 1049 1050 static void 1051 create_log_links (void) 1052 { 1053 basic_block bb; 1054 rtx_insn **next_use; 1055 rtx_insn *insn; 1056 df_ref def, use; 1057 1058 next_use = XCNEWVEC (rtx_insn *, max_reg_num ()); 1059 1060 /* Pass through each block from the end, recording the uses of each 1061 register and establishing log links when def is encountered. 1062 Note that we do not clear next_use array in order to save time, 1063 so we have to test whether the use is in the same basic block as def. 1064 1065 There are a few cases below when we do not consider the definition or 1066 usage -- these are taken from original flow.c did. Don't ask me why it is 1067 done this way; I don't know and if it works, I don't want to know. */ 1068 1069 FOR_EACH_BB_FN (bb, cfun) 1070 { 1071 FOR_BB_INSNS_REVERSE (bb, insn) 1072 { 1073 if (!NONDEBUG_INSN_P (insn)) 1074 continue; 1075 1076 /* Log links are created only once. */ 1077 gcc_assert (!LOG_LINKS (insn)); 1078 1079 FOR_EACH_INSN_DEF (def, insn) 1080 { 1081 unsigned int regno = DF_REF_REGNO (def); 1082 rtx_insn *use_insn; 1083 1084 if (!next_use[regno]) 1085 continue; 1086 1087 if (!can_combine_def_p (def)) 1088 continue; 1089 1090 use_insn = next_use[regno]; 1091 next_use[regno] = NULL; 1092 1093 if (BLOCK_FOR_INSN (use_insn) != bb) 1094 continue; 1095 1096 /* flow.c claimed: 1097 1098 We don't build a LOG_LINK for hard registers contained 1099 in ASM_OPERANDs. If these registers get replaced, 1100 we might wind up changing the semantics of the insn, 1101 even if reload can make what appear to be valid 1102 assignments later. */ 1103 if (regno < FIRST_PSEUDO_REGISTER 1104 && asm_noperands (PATTERN (use_insn)) >= 0) 1105 continue; 1106 1107 /* Don't add duplicate links between instructions. */ 1108 struct insn_link *links; 1109 FOR_EACH_LOG_LINK (links, use_insn) 1110 if (insn == links->insn && regno == links->regno) 1111 break; 1112 1113 if (!links) 1114 LOG_LINKS (use_insn) 1115 = alloc_insn_link (insn, regno, LOG_LINKS (use_insn)); 1116 } 1117 1118 FOR_EACH_INSN_USE (use, insn) 1119 if (can_combine_use_p (use)) 1120 next_use[DF_REF_REGNO (use)] = insn; 1121 } 1122 } 1123 1124 free (next_use); 1125 } 1126 1127 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return 1128 true if we found a LOG_LINK that proves that A feeds B. This only works 1129 if there are no instructions between A and B which could have a link 1130 depending on A, since in that case we would not record a link for B. 1131 We also check the implicit dependency created by a cc0 setter/user 1132 pair. */ 1133 1134 static bool 1135 insn_a_feeds_b (rtx_insn *a, rtx_insn *b) 1136 { 1137 struct insn_link *links; 1138 FOR_EACH_LOG_LINK (links, b) 1139 if (links->insn == a) 1140 return true; 1141 if (HAVE_cc0 && sets_cc0_p (a)) 1142 return true; 1143 return false; 1144 } 1145 1146 /* Main entry point for combiner. F is the first insn of the function. 1147 NREGS is the first unused pseudo-reg number. 1148 1149 Return nonzero if the CFG was changed (e.g. if the combiner has 1150 turned an indirect jump instruction into a direct jump). */ 1151 static int 1152 combine_instructions (rtx_insn *f, unsigned int nregs) 1153 { 1154 rtx_insn *insn, *next; 1155 rtx_insn *prev; 1156 struct insn_link *links, *nextlinks; 1157 rtx_insn *first; 1158 basic_block last_bb; 1159 1160 int new_direct_jump_p = 0; 1161 1162 for (first = f; first && !NONDEBUG_INSN_P (first); ) 1163 first = NEXT_INSN (first); 1164 if (!first) 1165 return 0; 1166 1167 combine_attempts = 0; 1168 combine_merges = 0; 1169 combine_extras = 0; 1170 combine_successes = 0; 1171 1172 rtl_hooks = combine_rtl_hooks; 1173 1174 reg_stat.safe_grow_cleared (nregs); 1175 1176 init_recog_no_volatile (); 1177 1178 /* Allocate array for insn info. */ 1179 max_uid_known = get_max_uid (); 1180 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1); 1181 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1); 1182 gcc_obstack_init (&insn_link_obstack); 1183 1184 nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require (); 1185 1186 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause 1187 problems when, for example, we have j <<= 1 in a loop. */ 1188 1189 nonzero_sign_valid = 0; 1190 label_tick = label_tick_ebb_start = 1; 1191 1192 /* Scan all SETs and see if we can deduce anything about what 1193 bits are known to be zero for some registers and how many copies 1194 of the sign bit are known to exist for those registers. 1195 1196 Also set any known values so that we can use it while searching 1197 for what bits are known to be set. */ 1198 1199 setup_incoming_promotions (first); 1200 /* Allow the entry block and the first block to fall into the same EBB. 1201 Conceptually the incoming promotions are assigned to the entry block. */ 1202 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun); 1203 1204 create_log_links (); 1205 FOR_EACH_BB_FN (this_basic_block, cfun) 1206 { 1207 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); 1208 last_call_luid = 0; 1209 mem_last_set = -1; 1210 1211 label_tick++; 1212 if (!single_pred_p (this_basic_block) 1213 || single_pred (this_basic_block) != last_bb) 1214 label_tick_ebb_start = label_tick; 1215 last_bb = this_basic_block; 1216 1217 FOR_BB_INSNS (this_basic_block, insn) 1218 if (INSN_P (insn) && BLOCK_FOR_INSN (insn)) 1219 { 1220 rtx links; 1221 1222 subst_low_luid = DF_INSN_LUID (insn); 1223 subst_insn = insn; 1224 1225 note_stores (insn, set_nonzero_bits_and_sign_copies, insn); 1226 record_dead_and_set_regs (insn); 1227 1228 if (AUTO_INC_DEC) 1229 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 1230 if (REG_NOTE_KIND (links) == REG_INC) 1231 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, 1232 insn); 1233 1234 /* Record the current insn_cost of this instruction. */ 1235 INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p); 1236 if (dump_file) 1237 { 1238 fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn)); 1239 dump_insn_slim (dump_file, insn); 1240 } 1241 } 1242 } 1243 1244 nonzero_sign_valid = 1; 1245 1246 /* Now scan all the insns in forward order. */ 1247 label_tick = label_tick_ebb_start = 1; 1248 init_reg_last (); 1249 setup_incoming_promotions (first); 1250 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun); 1251 int max_combine = param_max_combine_insns; 1252 1253 FOR_EACH_BB_FN (this_basic_block, cfun) 1254 { 1255 rtx_insn *last_combined_insn = NULL; 1256 1257 /* Ignore instruction combination in basic blocks that are going to 1258 be removed as unreachable anyway. See PR82386. */ 1259 if (EDGE_COUNT (this_basic_block->preds) == 0) 1260 continue; 1261 1262 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); 1263 last_call_luid = 0; 1264 mem_last_set = -1; 1265 1266 label_tick++; 1267 if (!single_pred_p (this_basic_block) 1268 || single_pred (this_basic_block) != last_bb) 1269 label_tick_ebb_start = label_tick; 1270 last_bb = this_basic_block; 1271 1272 rtl_profile_for_bb (this_basic_block); 1273 for (insn = BB_HEAD (this_basic_block); 1274 insn != NEXT_INSN (BB_END (this_basic_block)); 1275 insn = next ? next : NEXT_INSN (insn)) 1276 { 1277 next = 0; 1278 if (!NONDEBUG_INSN_P (insn)) 1279 continue; 1280 1281 while (last_combined_insn 1282 && (!NONDEBUG_INSN_P (last_combined_insn) 1283 || last_combined_insn->deleted ())) 1284 last_combined_insn = PREV_INSN (last_combined_insn); 1285 if (last_combined_insn == NULL_RTX 1286 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block 1287 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn)) 1288 last_combined_insn = insn; 1289 1290 /* See if we know about function return values before this 1291 insn based upon SUBREG flags. */ 1292 check_promoted_subreg (insn, PATTERN (insn)); 1293 1294 /* See if we can find hardregs and subreg of pseudos in 1295 narrower modes. This could help turning TRUNCATEs 1296 into SUBREGs. */ 1297 note_uses (&PATTERN (insn), record_truncated_values, NULL); 1298 1299 /* Try this insn with each insn it links back to. */ 1300 1301 FOR_EACH_LOG_LINK (links, insn) 1302 if ((next = try_combine (insn, links->insn, NULL, 1303 NULL, &new_direct_jump_p, 1304 last_combined_insn)) != 0) 1305 { 1306 statistics_counter_event (cfun, "two-insn combine", 1); 1307 goto retry; 1308 } 1309 1310 /* Try each sequence of three linked insns ending with this one. */ 1311 1312 if (max_combine >= 3) 1313 FOR_EACH_LOG_LINK (links, insn) 1314 { 1315 rtx_insn *link = links->insn; 1316 1317 /* If the linked insn has been replaced by a note, then there 1318 is no point in pursuing this chain any further. */ 1319 if (NOTE_P (link)) 1320 continue; 1321 1322 FOR_EACH_LOG_LINK (nextlinks, link) 1323 if ((next = try_combine (insn, link, nextlinks->insn, 1324 NULL, &new_direct_jump_p, 1325 last_combined_insn)) != 0) 1326 { 1327 statistics_counter_event (cfun, "three-insn combine", 1); 1328 goto retry; 1329 } 1330 } 1331 1332 /* Try to combine a jump insn that uses CC0 1333 with a preceding insn that sets CC0, and maybe with its 1334 logical predecessor as well. 1335 This is how we make decrement-and-branch insns. 1336 We need this special code because data flow connections 1337 via CC0 do not get entered in LOG_LINKS. */ 1338 1339 if (HAVE_cc0 1340 && JUMP_P (insn) 1341 && (prev = prev_nonnote_insn (insn)) != 0 1342 && NONJUMP_INSN_P (prev) 1343 && sets_cc0_p (PATTERN (prev))) 1344 { 1345 if ((next = try_combine (insn, prev, NULL, NULL, 1346 &new_direct_jump_p, 1347 last_combined_insn)) != 0) 1348 goto retry; 1349 1350 FOR_EACH_LOG_LINK (nextlinks, prev) 1351 if ((next = try_combine (insn, prev, nextlinks->insn, 1352 NULL, &new_direct_jump_p, 1353 last_combined_insn)) != 0) 1354 goto retry; 1355 } 1356 1357 /* Do the same for an insn that explicitly references CC0. */ 1358 if (HAVE_cc0 && NONJUMP_INSN_P (insn) 1359 && (prev = prev_nonnote_insn (insn)) != 0 1360 && NONJUMP_INSN_P (prev) 1361 && sets_cc0_p (PATTERN (prev)) 1362 && GET_CODE (PATTERN (insn)) == SET 1363 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) 1364 { 1365 if ((next = try_combine (insn, prev, NULL, NULL, 1366 &new_direct_jump_p, 1367 last_combined_insn)) != 0) 1368 goto retry; 1369 1370 FOR_EACH_LOG_LINK (nextlinks, prev) 1371 if ((next = try_combine (insn, prev, nextlinks->insn, 1372 NULL, &new_direct_jump_p, 1373 last_combined_insn)) != 0) 1374 goto retry; 1375 } 1376 1377 /* Finally, see if any of the insns that this insn links to 1378 explicitly references CC0. If so, try this insn, that insn, 1379 and its predecessor if it sets CC0. */ 1380 if (HAVE_cc0) 1381 { 1382 FOR_EACH_LOG_LINK (links, insn) 1383 if (NONJUMP_INSN_P (links->insn) 1384 && GET_CODE (PATTERN (links->insn)) == SET 1385 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn))) 1386 && (prev = prev_nonnote_insn (links->insn)) != 0 1387 && NONJUMP_INSN_P (prev) 1388 && sets_cc0_p (PATTERN (prev)) 1389 && (next = try_combine (insn, links->insn, 1390 prev, NULL, &new_direct_jump_p, 1391 last_combined_insn)) != 0) 1392 goto retry; 1393 } 1394 1395 /* Try combining an insn with two different insns whose results it 1396 uses. */ 1397 if (max_combine >= 3) 1398 FOR_EACH_LOG_LINK (links, insn) 1399 for (nextlinks = links->next; nextlinks; 1400 nextlinks = nextlinks->next) 1401 if ((next = try_combine (insn, links->insn, 1402 nextlinks->insn, NULL, 1403 &new_direct_jump_p, 1404 last_combined_insn)) != 0) 1405 1406 { 1407 statistics_counter_event (cfun, "three-insn combine", 1); 1408 goto retry; 1409 } 1410 1411 /* Try four-instruction combinations. */ 1412 if (max_combine >= 4) 1413 FOR_EACH_LOG_LINK (links, insn) 1414 { 1415 struct insn_link *next1; 1416 rtx_insn *link = links->insn; 1417 1418 /* If the linked insn has been replaced by a note, then there 1419 is no point in pursuing this chain any further. */ 1420 if (NOTE_P (link)) 1421 continue; 1422 1423 FOR_EACH_LOG_LINK (next1, link) 1424 { 1425 rtx_insn *link1 = next1->insn; 1426 if (NOTE_P (link1)) 1427 continue; 1428 /* I0 -> I1 -> I2 -> I3. */ 1429 FOR_EACH_LOG_LINK (nextlinks, link1) 1430 if ((next = try_combine (insn, link, link1, 1431 nextlinks->insn, 1432 &new_direct_jump_p, 1433 last_combined_insn)) != 0) 1434 { 1435 statistics_counter_event (cfun, "four-insn combine", 1); 1436 goto retry; 1437 } 1438 /* I0, I1 -> I2, I2 -> I3. */ 1439 for (nextlinks = next1->next; nextlinks; 1440 nextlinks = nextlinks->next) 1441 if ((next = try_combine (insn, link, link1, 1442 nextlinks->insn, 1443 &new_direct_jump_p, 1444 last_combined_insn)) != 0) 1445 { 1446 statistics_counter_event (cfun, "four-insn combine", 1); 1447 goto retry; 1448 } 1449 } 1450 1451 for (next1 = links->next; next1; next1 = next1->next) 1452 { 1453 rtx_insn *link1 = next1->insn; 1454 if (NOTE_P (link1)) 1455 continue; 1456 /* I0 -> I2; I1, I2 -> I3. */ 1457 FOR_EACH_LOG_LINK (nextlinks, link) 1458 if ((next = try_combine (insn, link, link1, 1459 nextlinks->insn, 1460 &new_direct_jump_p, 1461 last_combined_insn)) != 0) 1462 { 1463 statistics_counter_event (cfun, "four-insn combine", 1); 1464 goto retry; 1465 } 1466 /* I0 -> I1; I1, I2 -> I3. */ 1467 FOR_EACH_LOG_LINK (nextlinks, link1) 1468 if ((next = try_combine (insn, link, link1, 1469 nextlinks->insn, 1470 &new_direct_jump_p, 1471 last_combined_insn)) != 0) 1472 { 1473 statistics_counter_event (cfun, "four-insn combine", 1); 1474 goto retry; 1475 } 1476 } 1477 } 1478 1479 /* Try this insn with each REG_EQUAL note it links back to. */ 1480 FOR_EACH_LOG_LINK (links, insn) 1481 { 1482 rtx set, note; 1483 rtx_insn *temp = links->insn; 1484 if ((set = single_set (temp)) != 0 1485 && (note = find_reg_equal_equiv_note (temp)) != 0 1486 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST 1487 && ! side_effects_p (SET_SRC (set)) 1488 /* Avoid using a register that may already been marked 1489 dead by an earlier instruction. */ 1490 && ! unmentioned_reg_p (note, SET_SRC (set)) 1491 && (GET_MODE (note) == VOIDmode 1492 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set))) 1493 : (GET_MODE (SET_DEST (set)) == GET_MODE (note) 1494 && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT 1495 || (GET_MODE (XEXP (SET_DEST (set), 0)) 1496 == GET_MODE (note)))))) 1497 { 1498 /* Temporarily replace the set's source with the 1499 contents of the REG_EQUAL note. The insn will 1500 be deleted or recognized by try_combine. */ 1501 rtx orig_src = SET_SRC (set); 1502 rtx orig_dest = SET_DEST (set); 1503 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT) 1504 SET_DEST (set) = XEXP (SET_DEST (set), 0); 1505 SET_SRC (set) = note; 1506 i2mod = temp; 1507 i2mod_old_rhs = copy_rtx (orig_src); 1508 i2mod_new_rhs = copy_rtx (note); 1509 next = try_combine (insn, i2mod, NULL, NULL, 1510 &new_direct_jump_p, 1511 last_combined_insn); 1512 i2mod = NULL; 1513 if (next) 1514 { 1515 statistics_counter_event (cfun, "insn-with-note combine", 1); 1516 goto retry; 1517 } 1518 SET_SRC (set) = orig_src; 1519 SET_DEST (set) = orig_dest; 1520 } 1521 } 1522 1523 if (!NOTE_P (insn)) 1524 record_dead_and_set_regs (insn); 1525 1526 retry: 1527 ; 1528 } 1529 } 1530 1531 default_rtl_profile (); 1532 clear_bb_flags (); 1533 new_direct_jump_p |= purge_all_dead_edges (); 1534 new_direct_jump_p |= delete_noop_moves (); 1535 1536 /* Clean up. */ 1537 obstack_free (&insn_link_obstack, NULL); 1538 free (uid_log_links); 1539 free (uid_insn_cost); 1540 reg_stat.release (); 1541 1542 { 1543 struct undo *undo, *next; 1544 for (undo = undobuf.frees; undo; undo = next) 1545 { 1546 next = undo->next; 1547 free (undo); 1548 } 1549 undobuf.frees = 0; 1550 } 1551 1552 total_attempts += combine_attempts; 1553 total_merges += combine_merges; 1554 total_extras += combine_extras; 1555 total_successes += combine_successes; 1556 1557 nonzero_sign_valid = 0; 1558 rtl_hooks = general_rtl_hooks; 1559 1560 /* Make recognizer allow volatile MEMs again. */ 1561 init_recog (); 1562 1563 return new_direct_jump_p; 1564 } 1565 1566 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */ 1567 1568 static void 1569 init_reg_last (void) 1570 { 1571 unsigned int i; 1572 reg_stat_type *p; 1573 1574 FOR_EACH_VEC_ELT (reg_stat, i, p) 1575 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies)); 1576 } 1577 1578 /* Set up any promoted values for incoming argument registers. */ 1579 1580 static void 1581 setup_incoming_promotions (rtx_insn *first) 1582 { 1583 tree arg; 1584 bool strictly_local = false; 1585 1586 for (arg = DECL_ARGUMENTS (current_function_decl); arg; 1587 arg = DECL_CHAIN (arg)) 1588 { 1589 rtx x, reg = DECL_INCOMING_RTL (arg); 1590 int uns1, uns3; 1591 machine_mode mode1, mode2, mode3, mode4; 1592 1593 /* Only continue if the incoming argument is in a register. */ 1594 if (!REG_P (reg)) 1595 continue; 1596 1597 /* Determine, if possible, whether all call sites of the current 1598 function lie within the current compilation unit. (This does 1599 take into account the exporting of a function via taking its 1600 address, and so forth.) */ 1601 strictly_local 1602 = cgraph_node::local_info_node (current_function_decl)->local; 1603 1604 /* The mode and signedness of the argument before any promotions happen 1605 (equal to the mode of the pseudo holding it at that stage). */ 1606 mode1 = TYPE_MODE (TREE_TYPE (arg)); 1607 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg)); 1608 1609 /* The mode and signedness of the argument after any source language and 1610 TARGET_PROMOTE_PROTOTYPES-driven promotions. */ 1611 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg)); 1612 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg)); 1613 1614 /* The mode and signedness of the argument as it is actually passed, 1615 see assign_parm_setup_reg in function.c. */ 1616 mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3, 1617 TREE_TYPE (cfun->decl), 0); 1618 1619 /* The mode of the register in which the argument is being passed. */ 1620 mode4 = GET_MODE (reg); 1621 1622 /* Eliminate sign extensions in the callee when: 1623 (a) A mode promotion has occurred; */ 1624 if (mode1 == mode3) 1625 continue; 1626 /* (b) The mode of the register is the same as the mode of 1627 the argument as it is passed; */ 1628 if (mode3 != mode4) 1629 continue; 1630 /* (c) There's no language level extension; */ 1631 if (mode1 == mode2) 1632 ; 1633 /* (c.1) All callers are from the current compilation unit. If that's 1634 the case we don't have to rely on an ABI, we only have to know 1635 what we're generating right now, and we know that we will do the 1636 mode1 to mode2 promotion with the given sign. */ 1637 else if (!strictly_local) 1638 continue; 1639 /* (c.2) The combination of the two promotions is useful. This is 1640 true when the signs match, or if the first promotion is unsigned. 1641 In the later case, (sign_extend (zero_extend x)) is the same as 1642 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */ 1643 else if (uns1) 1644 uns3 = true; 1645 else if (uns3) 1646 continue; 1647 1648 /* Record that the value was promoted from mode1 to mode3, 1649 so that any sign extension at the head of the current 1650 function may be eliminated. */ 1651 x = gen_rtx_CLOBBER (mode1, const0_rtx); 1652 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x); 1653 record_value_for_reg (reg, first, x); 1654 } 1655 } 1656 1657 /* If MODE has a precision lower than PREC and SRC is a non-negative constant 1658 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits 1659 because some machines (maybe most) will actually do the sign-extension and 1660 this is the conservative approach. 1661 1662 ??? For 2.5, try to tighten up the MD files in this regard instead of this 1663 kludge. */ 1664 1665 static rtx 1666 sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec) 1667 { 1668 scalar_int_mode int_mode; 1669 if (CONST_INT_P (src) 1670 && is_a <scalar_int_mode> (mode, &int_mode) 1671 && GET_MODE_PRECISION (int_mode) < prec 1672 && INTVAL (src) > 0 1673 && val_signbit_known_set_p (int_mode, INTVAL (src))) 1674 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode)); 1675 1676 return src; 1677 } 1678 1679 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists) 1680 and SET. */ 1681 1682 static void 1683 update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set, 1684 rtx x) 1685 { 1686 rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX; 1687 unsigned HOST_WIDE_INT bits = 0; 1688 rtx reg_equal = NULL, src = SET_SRC (set); 1689 unsigned int num = 0; 1690 1691 if (reg_equal_note) 1692 reg_equal = XEXP (reg_equal_note, 0); 1693 1694 if (SHORT_IMMEDIATES_SIGN_EXTEND) 1695 { 1696 src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD); 1697 if (reg_equal) 1698 reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD); 1699 } 1700 1701 /* Don't call nonzero_bits if it cannot change anything. */ 1702 if (rsp->nonzero_bits != HOST_WIDE_INT_M1U) 1703 { 1704 machine_mode mode = GET_MODE (x); 1705 if (GET_MODE_CLASS (mode) == MODE_INT 1706 && HWI_COMPUTABLE_MODE_P (mode)) 1707 mode = nonzero_bits_mode; 1708 bits = nonzero_bits (src, mode); 1709 if (reg_equal && bits) 1710 bits &= nonzero_bits (reg_equal, mode); 1711 rsp->nonzero_bits |= bits; 1712 } 1713 1714 /* Don't call num_sign_bit_copies if it cannot change anything. */ 1715 if (rsp->sign_bit_copies != 1) 1716 { 1717 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); 1718 if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x)))) 1719 { 1720 unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x)); 1721 if (num == 0 || numeq > num) 1722 num = numeq; 1723 } 1724 if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies) 1725 rsp->sign_bit_copies = num; 1726 } 1727 } 1728 1729 /* Called via note_stores. If X is a pseudo that is narrower than 1730 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. 1731 1732 If we are setting only a portion of X and we can't figure out what 1733 portion, assume all bits will be used since we don't know what will 1734 be happening. 1735 1736 Similarly, set how many bits of X are known to be copies of the sign bit 1737 at all locations in the function. This is the smallest number implied 1738 by any set of X. */ 1739 1740 static void 1741 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data) 1742 { 1743 rtx_insn *insn = (rtx_insn *) data; 1744 scalar_int_mode mode; 1745 1746 if (REG_P (x) 1747 && REGNO (x) >= FIRST_PSEUDO_REGISTER 1748 /* If this register is undefined at the start of the file, we can't 1749 say what its contents were. */ 1750 && ! REGNO_REG_SET_P 1751 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x)) 1752 && is_a <scalar_int_mode> (GET_MODE (x), &mode) 1753 && HWI_COMPUTABLE_MODE_P (mode)) 1754 { 1755 reg_stat_type *rsp = ®_stat[REGNO (x)]; 1756 1757 if (set == 0 || GET_CODE (set) == CLOBBER) 1758 { 1759 rsp->nonzero_bits = GET_MODE_MASK (mode); 1760 rsp->sign_bit_copies = 1; 1761 return; 1762 } 1763 1764 /* If this register is being initialized using itself, and the 1765 register is uninitialized in this basic block, and there are 1766 no LOG_LINKS which set the register, then part of the 1767 register is uninitialized. In that case we can't assume 1768 anything about the number of nonzero bits. 1769 1770 ??? We could do better if we checked this in 1771 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we 1772 could avoid making assumptions about the insn which initially 1773 sets the register, while still using the information in other 1774 insns. We would have to be careful to check every insn 1775 involved in the combination. */ 1776 1777 if (insn 1778 && reg_referenced_p (x, PATTERN (insn)) 1779 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)), 1780 REGNO (x))) 1781 { 1782 struct insn_link *link; 1783 1784 FOR_EACH_LOG_LINK (link, insn) 1785 if (dead_or_set_p (link->insn, x)) 1786 break; 1787 if (!link) 1788 { 1789 rsp->nonzero_bits = GET_MODE_MASK (mode); 1790 rsp->sign_bit_copies = 1; 1791 return; 1792 } 1793 } 1794 1795 /* If this is a complex assignment, see if we can convert it into a 1796 simple assignment. */ 1797 set = expand_field_assignment (set); 1798 1799 /* If this is a simple assignment, or we have a paradoxical SUBREG, 1800 set what we know about X. */ 1801 1802 if (SET_DEST (set) == x 1803 || (paradoxical_subreg_p (SET_DEST (set)) 1804 && SUBREG_REG (SET_DEST (set)) == x)) 1805 update_rsp_from_reg_equal (rsp, insn, set, x); 1806 else 1807 { 1808 rsp->nonzero_bits = GET_MODE_MASK (mode); 1809 rsp->sign_bit_copies = 1; 1810 } 1811 } 1812 } 1813 1814 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are 1815 optionally insns that were previously combined into I3 or that will be 1816 combined into the merger of INSN and I3. The order is PRED, PRED2, 1817 INSN, SUCC, SUCC2, I3. 1818 1819 Return 0 if the combination is not allowed for any reason. 1820 1821 If the combination is allowed, *PDEST will be set to the single 1822 destination of INSN and *PSRC to the single source, and this function 1823 will return 1. */ 1824 1825 static int 1826 can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED, 1827 rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2, 1828 rtx *pdest, rtx *psrc) 1829 { 1830 int i; 1831 const_rtx set = 0; 1832 rtx src, dest; 1833 rtx_insn *p; 1834 rtx link; 1835 bool all_adjacent = true; 1836 int (*is_volatile_p) (const_rtx); 1837 1838 if (succ) 1839 { 1840 if (succ2) 1841 { 1842 if (next_active_insn (succ2) != i3) 1843 all_adjacent = false; 1844 if (next_active_insn (succ) != succ2) 1845 all_adjacent = false; 1846 } 1847 else if (next_active_insn (succ) != i3) 1848 all_adjacent = false; 1849 if (next_active_insn (insn) != succ) 1850 all_adjacent = false; 1851 } 1852 else if (next_active_insn (insn) != i3) 1853 all_adjacent = false; 1854 1855 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. 1856 or a PARALLEL consisting of such a SET and CLOBBERs. 1857 1858 If INSN has CLOBBER parallel parts, ignore them for our processing. 1859 By definition, these happen during the execution of the insn. When it 1860 is merged with another insn, all bets are off. If they are, in fact, 1861 needed and aren't also supplied in I3, they may be added by 1862 recog_for_combine. Otherwise, it won't match. 1863 1864 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED 1865 note. 1866 1867 Get the source and destination of INSN. If more than one, can't 1868 combine. */ 1869 1870 if (GET_CODE (PATTERN (insn)) == SET) 1871 set = PATTERN (insn); 1872 else if (GET_CODE (PATTERN (insn)) == PARALLEL 1873 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 1874 { 1875 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 1876 { 1877 rtx elt = XVECEXP (PATTERN (insn), 0, i); 1878 1879 switch (GET_CODE (elt)) 1880 { 1881 /* This is important to combine floating point insns 1882 for the SH4 port. */ 1883 case USE: 1884 /* Combining an isolated USE doesn't make sense. 1885 We depend here on combinable_i3pat to reject them. */ 1886 /* The code below this loop only verifies that the inputs of 1887 the SET in INSN do not change. We call reg_set_between_p 1888 to verify that the REG in the USE does not change between 1889 I3 and INSN. 1890 If the USE in INSN was for a pseudo register, the matching 1891 insn pattern will likely match any register; combining this 1892 with any other USE would only be safe if we knew that the 1893 used registers have identical values, or if there was 1894 something to tell them apart, e.g. different modes. For 1895 now, we forgo such complicated tests and simply disallow 1896 combining of USES of pseudo registers with any other USE. */ 1897 if (REG_P (XEXP (elt, 0)) 1898 && GET_CODE (PATTERN (i3)) == PARALLEL) 1899 { 1900 rtx i3pat = PATTERN (i3); 1901 int i = XVECLEN (i3pat, 0) - 1; 1902 unsigned int regno = REGNO (XEXP (elt, 0)); 1903 1904 do 1905 { 1906 rtx i3elt = XVECEXP (i3pat, 0, i); 1907 1908 if (GET_CODE (i3elt) == USE 1909 && REG_P (XEXP (i3elt, 0)) 1910 && (REGNO (XEXP (i3elt, 0)) == regno 1911 ? reg_set_between_p (XEXP (elt, 0), 1912 PREV_INSN (insn), i3) 1913 : regno >= FIRST_PSEUDO_REGISTER)) 1914 return 0; 1915 } 1916 while (--i >= 0); 1917 } 1918 break; 1919 1920 /* We can ignore CLOBBERs. */ 1921 case CLOBBER: 1922 break; 1923 1924 case SET: 1925 /* Ignore SETs whose result isn't used but not those that 1926 have side-effects. */ 1927 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) 1928 && insn_nothrow_p (insn) 1929 && !side_effects_p (elt)) 1930 break; 1931 1932 /* If we have already found a SET, this is a second one and 1933 so we cannot combine with this insn. */ 1934 if (set) 1935 return 0; 1936 1937 set = elt; 1938 break; 1939 1940 default: 1941 /* Anything else means we can't combine. */ 1942 return 0; 1943 } 1944 } 1945 1946 if (set == 0 1947 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, 1948 so don't do anything with it. */ 1949 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) 1950 return 0; 1951 } 1952 else 1953 return 0; 1954 1955 if (set == 0) 1956 return 0; 1957 1958 /* The simplification in expand_field_assignment may call back to 1959 get_last_value, so set safe guard here. */ 1960 subst_low_luid = DF_INSN_LUID (insn); 1961 1962 set = expand_field_assignment (set); 1963 src = SET_SRC (set), dest = SET_DEST (set); 1964 1965 /* Do not eliminate user-specified register if it is in an 1966 asm input because we may break the register asm usage defined 1967 in GCC manual if allow to do so. 1968 Be aware that this may cover more cases than we expect but this 1969 should be harmless. */ 1970 if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest) 1971 && extract_asm_operands (PATTERN (i3))) 1972 return 0; 1973 1974 /* Don't eliminate a store in the stack pointer. */ 1975 if (dest == stack_pointer_rtx 1976 /* Don't combine with an insn that sets a register to itself if it has 1977 a REG_EQUAL note. This may be part of a LIBCALL sequence. */ 1978 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 1979 /* Can't merge an ASM_OPERANDS. */ 1980 || GET_CODE (src) == ASM_OPERANDS 1981 /* Can't merge a function call. */ 1982 || GET_CODE (src) == CALL 1983 /* Don't eliminate a function call argument. */ 1984 || (CALL_P (i3) 1985 && (find_reg_fusage (i3, USE, dest) 1986 || (REG_P (dest) 1987 && REGNO (dest) < FIRST_PSEUDO_REGISTER 1988 && global_regs[REGNO (dest)]))) 1989 /* Don't substitute into an incremented register. */ 1990 || FIND_REG_INC_NOTE (i3, dest) 1991 || (succ && FIND_REG_INC_NOTE (succ, dest)) 1992 || (succ2 && FIND_REG_INC_NOTE (succ2, dest)) 1993 /* Don't substitute into a non-local goto, this confuses CFG. */ 1994 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX)) 1995 /* Make sure that DEST is not used after INSN but before SUCC, or 1996 after SUCC and before SUCC2, or after SUCC2 but before I3. */ 1997 || (!all_adjacent 1998 && ((succ2 1999 && (reg_used_between_p (dest, succ2, i3) 2000 || reg_used_between_p (dest, succ, succ2))) 2001 || (!succ2 && succ && reg_used_between_p (dest, succ, i3)) 2002 || (!succ2 && !succ && reg_used_between_p (dest, insn, i3)) 2003 || (succ 2004 /* SUCC and SUCC2 can be split halves from a PARALLEL; in 2005 that case SUCC is not in the insn stream, so use SUCC2 2006 instead for this test. */ 2007 && reg_used_between_p (dest, insn, 2008 succ2 2009 && INSN_UID (succ) == INSN_UID (succ2) 2010 ? succ2 : succ)))) 2011 /* Make sure that the value that is to be substituted for the register 2012 does not use any registers whose values alter in between. However, 2013 If the insns are adjacent, a use can't cross a set even though we 2014 think it might (this can happen for a sequence of insns each setting 2015 the same destination; last_set of that register might point to 2016 a NOTE). If INSN has a REG_EQUIV note, the register is always 2017 equivalent to the memory so the substitution is valid even if there 2018 are intervening stores. Also, don't move a volatile asm or 2019 UNSPEC_VOLATILE across any other insns. */ 2020 || (! all_adjacent 2021 && (((!MEM_P (src) 2022 || ! find_reg_note (insn, REG_EQUIV, src)) 2023 && modified_between_p (src, insn, i3)) 2024 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) 2025 || GET_CODE (src) == UNSPEC_VOLATILE)) 2026 /* Don't combine across a CALL_INSN, because that would possibly 2027 change whether the life span of some REGs crosses calls or not, 2028 and it is a pain to update that information. 2029 Exception: if source is a constant, moving it later can't hurt. 2030 Accept that as a special case. */ 2031 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src))) 2032 return 0; 2033 2034 /* DEST must either be a REG or CC0. */ 2035 if (REG_P (dest)) 2036 { 2037 /* If register alignment is being enforced for multi-word items in all 2038 cases except for parameters, it is possible to have a register copy 2039 insn referencing a hard register that is not allowed to contain the 2040 mode being copied and which would not be valid as an operand of most 2041 insns. Eliminate this problem by not combining with such an insn. 2042 2043 Also, on some machines we don't want to extend the life of a hard 2044 register. */ 2045 2046 if (REG_P (src) 2047 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER 2048 && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest))) 2049 /* Don't extend the life of a hard register unless it is 2050 user variable (if we have few registers) or it can't 2051 fit into the desired register (meaning something special 2052 is going on). 2053 Also avoid substituting a return register into I3, because 2054 reload can't handle a conflict with constraints of other 2055 inputs. */ 2056 || (REGNO (src) < FIRST_PSEUDO_REGISTER 2057 && !targetm.hard_regno_mode_ok (REGNO (src), 2058 GET_MODE (src))))) 2059 return 0; 2060 } 2061 else if (GET_CODE (dest) != CC0) 2062 return 0; 2063 2064 2065 if (GET_CODE (PATTERN (i3)) == PARALLEL) 2066 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) 2067 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER) 2068 { 2069 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0); 2070 2071 /* If the clobber represents an earlyclobber operand, we must not 2072 substitute an expression containing the clobbered register. 2073 As we do not analyze the constraint strings here, we have to 2074 make the conservative assumption. However, if the register is 2075 a fixed hard reg, the clobber cannot represent any operand; 2076 we leave it up to the machine description to either accept or 2077 reject use-and-clobber patterns. */ 2078 if (!REG_P (reg) 2079 || REGNO (reg) >= FIRST_PSEUDO_REGISTER 2080 || !fixed_regs[REGNO (reg)]) 2081 if (reg_overlap_mentioned_p (reg, src)) 2082 return 0; 2083 } 2084 2085 /* If INSN contains anything volatile, or is an `asm' (whether volatile 2086 or not), reject, unless nothing volatile comes between it and I3 */ 2087 2088 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) 2089 { 2090 /* Make sure neither succ nor succ2 contains a volatile reference. */ 2091 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2))) 2092 return 0; 2093 if (succ != 0 && volatile_refs_p (PATTERN (succ))) 2094 return 0; 2095 /* We'll check insns between INSN and I3 below. */ 2096 } 2097 2098 /* If INSN is an asm, and DEST is a hard register, reject, since it has 2099 to be an explicit register variable, and was chosen for a reason. */ 2100 2101 if (GET_CODE (src) == ASM_OPERANDS 2102 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER) 2103 return 0; 2104 2105 /* If INSN contains volatile references (specifically volatile MEMs), 2106 we cannot combine across any other volatile references. 2107 Even if INSN doesn't contain volatile references, any intervening 2108 volatile insn might affect machine state. */ 2109 2110 is_volatile_p = volatile_refs_p (PATTERN (insn)) 2111 ? volatile_refs_p 2112 : volatile_insn_p; 2113 2114 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 2115 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p))) 2116 return 0; 2117 2118 /* If INSN contains an autoincrement or autodecrement, make sure that 2119 register is not used between there and I3, and not already used in 2120 I3 either. Neither must it be used in PRED or SUCC, if they exist. 2121 Also insist that I3 not be a jump if using LRA; if it were one 2122 and the incremented register were spilled, we would lose. 2123 Reload handles this correctly. */ 2124 2125 if (AUTO_INC_DEC) 2126 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 2127 if (REG_NOTE_KIND (link) == REG_INC 2128 && ((JUMP_P (i3) && targetm.lra_p ()) 2129 || reg_used_between_p (XEXP (link, 0), insn, i3) 2130 || (pred != NULL_RTX 2131 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred))) 2132 || (pred2 != NULL_RTX 2133 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2))) 2134 || (succ != NULL_RTX 2135 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ))) 2136 || (succ2 != NULL_RTX 2137 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2))) 2138 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) 2139 return 0; 2140 2141 /* Don't combine an insn that follows a CC0-setting insn. 2142 An insn that uses CC0 must not be separated from the one that sets it. 2143 We do, however, allow I2 to follow a CC0-setting insn if that insn 2144 is passed as I1; in that case it will be deleted also. 2145 We also allow combining in this case if all the insns are adjacent 2146 because that would leave the two CC0 insns adjacent as well. 2147 It would be more logical to test whether CC0 occurs inside I1 or I2, 2148 but that would be much slower, and this ought to be equivalent. */ 2149 2150 if (HAVE_cc0) 2151 { 2152 p = prev_nonnote_insn (insn); 2153 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p)) 2154 && ! all_adjacent) 2155 return 0; 2156 } 2157 2158 /* If we get here, we have passed all the tests and the combination is 2159 to be allowed. */ 2160 2161 *pdest = dest; 2162 *psrc = src; 2163 2164 return 1; 2165 } 2166 2167 /* LOC is the location within I3 that contains its pattern or the component 2168 of a PARALLEL of the pattern. We validate that it is valid for combining. 2169 2170 One problem is if I3 modifies its output, as opposed to replacing it 2171 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as 2172 doing so would produce an insn that is not equivalent to the original insns. 2173 2174 Consider: 2175 2176 (set (reg:DI 101) (reg:DI 100)) 2177 (set (subreg:SI (reg:DI 101) 0) <foo>) 2178 2179 This is NOT equivalent to: 2180 2181 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) 2182 (set (reg:DI 101) (reg:DI 100))]) 2183 2184 Not only does this modify 100 (in which case it might still be valid 2185 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. 2186 2187 We can also run into a problem if I2 sets a register that I1 2188 uses and I1 gets directly substituted into I3 (not via I2). In that 2189 case, we would be getting the wrong value of I2DEST into I3, so we 2190 must reject the combination. This case occurs when I2 and I1 both 2191 feed into I3, rather than when I1 feeds into I2, which feeds into I3. 2192 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source 2193 of a SET must prevent combination from occurring. The same situation 2194 can occur for I0, in which case I0_NOT_IN_SRC is set. 2195 2196 Before doing the above check, we first try to expand a field assignment 2197 into a set of logical operations. 2198 2199 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which 2200 we place a register that is both set and used within I3. If more than one 2201 such register is detected, we fail. 2202 2203 Return 1 if the combination is valid, zero otherwise. */ 2204 2205 static int 2206 combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest, 2207 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed) 2208 { 2209 rtx x = *loc; 2210 2211 if (GET_CODE (x) == SET) 2212 { 2213 rtx set = x ; 2214 rtx dest = SET_DEST (set); 2215 rtx src = SET_SRC (set); 2216 rtx inner_dest = dest; 2217 rtx subdest; 2218 2219 while (GET_CODE (inner_dest) == STRICT_LOW_PART 2220 || GET_CODE (inner_dest) == SUBREG 2221 || GET_CODE (inner_dest) == ZERO_EXTRACT) 2222 inner_dest = XEXP (inner_dest, 0); 2223 2224 /* Check for the case where I3 modifies its output, as discussed 2225 above. We don't want to prevent pseudos from being combined 2226 into the address of a MEM, so only prevent the combination if 2227 i1 or i2 set the same MEM. */ 2228 if ((inner_dest != dest && 2229 (!MEM_P (inner_dest) 2230 || rtx_equal_p (i2dest, inner_dest) 2231 || (i1dest && rtx_equal_p (i1dest, inner_dest)) 2232 || (i0dest && rtx_equal_p (i0dest, inner_dest))) 2233 && (reg_overlap_mentioned_p (i2dest, inner_dest) 2234 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)) 2235 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest)))) 2236 2237 /* This is the same test done in can_combine_p except we can't test 2238 all_adjacent; we don't have to, since this instruction will stay 2239 in place, thus we are not considering increasing the lifetime of 2240 INNER_DEST. 2241 2242 Also, if this insn sets a function argument, combining it with 2243 something that might need a spill could clobber a previous 2244 function argument; the all_adjacent test in can_combine_p also 2245 checks this; here, we do a more specific test for this case. */ 2246 2247 || (REG_P (inner_dest) 2248 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 2249 && !targetm.hard_regno_mode_ok (REGNO (inner_dest), 2250 GET_MODE (inner_dest))) 2251 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)) 2252 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src))) 2253 return 0; 2254 2255 /* If DEST is used in I3, it is being killed in this insn, so 2256 record that for later. We have to consider paradoxical 2257 subregs here, since they kill the whole register, but we 2258 ignore partial subregs, STRICT_LOW_PART, etc. 2259 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the 2260 STACK_POINTER_REGNUM, since these are always considered to be 2261 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ 2262 subdest = dest; 2263 if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest)) 2264 subdest = SUBREG_REG (subdest); 2265 if (pi3dest_killed 2266 && REG_P (subdest) 2267 && reg_referenced_p (subdest, PATTERN (i3)) 2268 && REGNO (subdest) != FRAME_POINTER_REGNUM 2269 && (HARD_FRAME_POINTER_IS_FRAME_POINTER 2270 || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM) 2271 && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM 2272 || (REGNO (subdest) != ARG_POINTER_REGNUM 2273 || ! fixed_regs [REGNO (subdest)])) 2274 && REGNO (subdest) != STACK_POINTER_REGNUM) 2275 { 2276 if (*pi3dest_killed) 2277 return 0; 2278 2279 *pi3dest_killed = subdest; 2280 } 2281 } 2282 2283 else if (GET_CODE (x) == PARALLEL) 2284 { 2285 int i; 2286 2287 for (i = 0; i < XVECLEN (x, 0); i++) 2288 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest, 2289 i1_not_in_src, i0_not_in_src, pi3dest_killed)) 2290 return 0; 2291 } 2292 2293 return 1; 2294 } 2295 2296 /* Return 1 if X is an arithmetic expression that contains a multiplication 2297 and division. We don't count multiplications by powers of two here. */ 2298 2299 static int 2300 contains_muldiv (rtx x) 2301 { 2302 switch (GET_CODE (x)) 2303 { 2304 case MOD: case DIV: case UMOD: case UDIV: 2305 return 1; 2306 2307 case MULT: 2308 return ! (CONST_INT_P (XEXP (x, 1)) 2309 && pow2p_hwi (UINTVAL (XEXP (x, 1)))); 2310 default: 2311 if (BINARY_P (x)) 2312 return contains_muldiv (XEXP (x, 0)) 2313 || contains_muldiv (XEXP (x, 1)); 2314 2315 if (UNARY_P (x)) 2316 return contains_muldiv (XEXP (x, 0)); 2317 2318 return 0; 2319 } 2320 } 2321 2322 /* Determine whether INSN can be used in a combination. Return nonzero if 2323 not. This is used in try_combine to detect early some cases where we 2324 can't perform combinations. */ 2325 2326 static int 2327 cant_combine_insn_p (rtx_insn *insn) 2328 { 2329 rtx set; 2330 rtx src, dest; 2331 2332 /* If this isn't really an insn, we can't do anything. 2333 This can occur when flow deletes an insn that it has merged into an 2334 auto-increment address. */ 2335 if (!NONDEBUG_INSN_P (insn)) 2336 return 1; 2337 2338 /* Never combine loads and stores involving hard regs that are likely 2339 to be spilled. The register allocator can usually handle such 2340 reg-reg moves by tying. If we allow the combiner to make 2341 substitutions of likely-spilled regs, reload might die. 2342 As an exception, we allow combinations involving fixed regs; these are 2343 not available to the register allocator so there's no risk involved. */ 2344 2345 set = single_set (insn); 2346 if (! set) 2347 return 0; 2348 src = SET_SRC (set); 2349 dest = SET_DEST (set); 2350 if (GET_CODE (src) == SUBREG) 2351 src = SUBREG_REG (src); 2352 if (GET_CODE (dest) == SUBREG) 2353 dest = SUBREG_REG (dest); 2354 if (REG_P (src) && REG_P (dest) 2355 && ((HARD_REGISTER_P (src) 2356 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)) 2357 #ifdef LEAF_REGISTERS 2358 && ! LEAF_REGISTERS [REGNO (src)]) 2359 #else 2360 ) 2361 #endif 2362 || (HARD_REGISTER_P (dest) 2363 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest)) 2364 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest)))))) 2365 return 1; 2366 2367 return 0; 2368 } 2369 2370 struct likely_spilled_retval_info 2371 { 2372 unsigned regno, nregs; 2373 unsigned mask; 2374 }; 2375 2376 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask 2377 hard registers that are known to be written to / clobbered in full. */ 2378 static void 2379 likely_spilled_retval_1 (rtx x, const_rtx set, void *data) 2380 { 2381 struct likely_spilled_retval_info *const info = 2382 (struct likely_spilled_retval_info *) data; 2383 unsigned regno, nregs; 2384 unsigned new_mask; 2385 2386 if (!REG_P (XEXP (set, 0))) 2387 return; 2388 regno = REGNO (x); 2389 if (regno >= info->regno + info->nregs) 2390 return; 2391 nregs = REG_NREGS (x); 2392 if (regno + nregs <= info->regno) 2393 return; 2394 new_mask = (2U << (nregs - 1)) - 1; 2395 if (regno < info->regno) 2396 new_mask >>= info->regno - regno; 2397 else 2398 new_mask <<= regno - info->regno; 2399 info->mask &= ~new_mask; 2400 } 2401 2402 /* Return nonzero iff part of the return value is live during INSN, and 2403 it is likely spilled. This can happen when more than one insn is needed 2404 to copy the return value, e.g. when we consider to combine into the 2405 second copy insn for a complex value. */ 2406 2407 static int 2408 likely_spilled_retval_p (rtx_insn *insn) 2409 { 2410 rtx_insn *use = BB_END (this_basic_block); 2411 rtx reg; 2412 rtx_insn *p; 2413 unsigned regno, nregs; 2414 /* We assume here that no machine mode needs more than 2415 32 hard registers when the value overlaps with a register 2416 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */ 2417 unsigned mask; 2418 struct likely_spilled_retval_info info; 2419 2420 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use) 2421 return 0; 2422 reg = XEXP (PATTERN (use), 0); 2423 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg))) 2424 return 0; 2425 regno = REGNO (reg); 2426 nregs = REG_NREGS (reg); 2427 if (nregs == 1) 2428 return 0; 2429 mask = (2U << (nregs - 1)) - 1; 2430 2431 /* Disregard parts of the return value that are set later. */ 2432 info.regno = regno; 2433 info.nregs = nregs; 2434 info.mask = mask; 2435 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p)) 2436 if (INSN_P (p)) 2437 note_stores (p, likely_spilled_retval_1, &info); 2438 mask = info.mask; 2439 2440 /* Check if any of the (probably) live return value registers is 2441 likely spilled. */ 2442 nregs --; 2443 do 2444 { 2445 if ((mask & 1 << nregs) 2446 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs))) 2447 return 1; 2448 } while (nregs--); 2449 return 0; 2450 } 2451 2452 /* Adjust INSN after we made a change to its destination. 2453 2454 Changing the destination can invalidate notes that say something about 2455 the results of the insn and a LOG_LINK pointing to the insn. */ 2456 2457 static void 2458 adjust_for_new_dest (rtx_insn *insn) 2459 { 2460 /* For notes, be conservative and simply remove them. */ 2461 remove_reg_equal_equiv_notes (insn); 2462 2463 /* The new insn will have a destination that was previously the destination 2464 of an insn just above it. Call distribute_links to make a LOG_LINK from 2465 the next use of that destination. */ 2466 2467 rtx set = single_set (insn); 2468 gcc_assert (set); 2469 2470 rtx reg = SET_DEST (set); 2471 2472 while (GET_CODE (reg) == ZERO_EXTRACT 2473 || GET_CODE (reg) == STRICT_LOW_PART 2474 || GET_CODE (reg) == SUBREG) 2475 reg = XEXP (reg, 0); 2476 gcc_assert (REG_P (reg)); 2477 2478 distribute_links (alloc_insn_link (insn, REGNO (reg), NULL)); 2479 2480 df_insn_rescan (insn); 2481 } 2482 2483 /* Return TRUE if combine can reuse reg X in mode MODE. 2484 ADDED_SETS is nonzero if the original set is still required. */ 2485 static bool 2486 can_change_dest_mode (rtx x, int added_sets, machine_mode mode) 2487 { 2488 unsigned int regno; 2489 2490 if (!REG_P (x)) 2491 return false; 2492 2493 /* Don't change between modes with different underlying register sizes, 2494 since this could lead to invalid subregs. */ 2495 if (maybe_ne (REGMODE_NATURAL_SIZE (mode), 2496 REGMODE_NATURAL_SIZE (GET_MODE (x)))) 2497 return false; 2498 2499 regno = REGNO (x); 2500 /* Allow hard registers if the new mode is legal, and occupies no more 2501 registers than the old mode. */ 2502 if (regno < FIRST_PSEUDO_REGISTER) 2503 return (targetm.hard_regno_mode_ok (regno, mode) 2504 && REG_NREGS (x) >= hard_regno_nregs (regno, mode)); 2505 2506 /* Or a pseudo that is only used once. */ 2507 return (regno < reg_n_sets_max 2508 && REG_N_SETS (regno) == 1 2509 && !added_sets 2510 && !REG_USERVAR_P (x)); 2511 } 2512 2513 2514 /* Check whether X, the destination of a set, refers to part of 2515 the register specified by REG. */ 2516 2517 static bool 2518 reg_subword_p (rtx x, rtx reg) 2519 { 2520 /* Check that reg is an integer mode register. */ 2521 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) 2522 return false; 2523 2524 if (GET_CODE (x) == STRICT_LOW_PART 2525 || GET_CODE (x) == ZERO_EXTRACT) 2526 x = XEXP (x, 0); 2527 2528 return GET_CODE (x) == SUBREG 2529 && SUBREG_REG (x) == reg 2530 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT; 2531 } 2532 2533 /* Delete the unconditional jump INSN and adjust the CFG correspondingly. 2534 Note that the INSN should be deleted *after* removing dead edges, so 2535 that the kept edge is the fallthrough edge for a (set (pc) (pc)) 2536 but not for a (set (pc) (label_ref FOO)). */ 2537 2538 static void 2539 update_cfg_for_uncondjump (rtx_insn *insn) 2540 { 2541 basic_block bb = BLOCK_FOR_INSN (insn); 2542 gcc_assert (BB_END (bb) == insn); 2543 2544 purge_dead_edges (bb); 2545 2546 delete_insn (insn); 2547 if (EDGE_COUNT (bb->succs) == 1) 2548 { 2549 rtx_insn *insn; 2550 2551 single_succ_edge (bb)->flags |= EDGE_FALLTHRU; 2552 2553 /* Remove barriers from the footer if there are any. */ 2554 for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn)) 2555 if (BARRIER_P (insn)) 2556 { 2557 if (PREV_INSN (insn)) 2558 SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); 2559 else 2560 BB_FOOTER (bb) = NEXT_INSN (insn); 2561 if (NEXT_INSN (insn)) 2562 SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); 2563 } 2564 else if (LABEL_P (insn)) 2565 break; 2566 } 2567 } 2568 2569 /* Return whether PAT is a PARALLEL of exactly N register SETs followed 2570 by an arbitrary number of CLOBBERs. */ 2571 static bool 2572 is_parallel_of_n_reg_sets (rtx pat, int n) 2573 { 2574 if (GET_CODE (pat) != PARALLEL) 2575 return false; 2576 2577 int len = XVECLEN (pat, 0); 2578 if (len < n) 2579 return false; 2580 2581 int i; 2582 for (i = 0; i < n; i++) 2583 if (GET_CODE (XVECEXP (pat, 0, i)) != SET 2584 || !REG_P (SET_DEST (XVECEXP (pat, 0, i)))) 2585 return false; 2586 for ( ; i < len; i++) 2587 switch (GET_CODE (XVECEXP (pat, 0, i))) 2588 { 2589 case CLOBBER: 2590 if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 2591 return false; 2592 break; 2593 default: 2594 return false; 2595 } 2596 return true; 2597 } 2598 2599 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some 2600 CLOBBERs), can be split into individual SETs in that order, without 2601 changing semantics. */ 2602 static bool 2603 can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n) 2604 { 2605 if (!insn_nothrow_p (insn)) 2606 return false; 2607 2608 rtx pat = PATTERN (insn); 2609 2610 int i, j; 2611 for (i = 0; i < n; i++) 2612 { 2613 if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i)))) 2614 return false; 2615 2616 rtx reg = SET_DEST (XVECEXP (pat, 0, i)); 2617 2618 for (j = i + 1; j < n; j++) 2619 if (reg_referenced_p (reg, XVECEXP (pat, 0, j))) 2620 return false; 2621 } 2622 2623 return true; 2624 } 2625 2626 /* Return whether X is just a single set, with the source 2627 a general_operand. */ 2628 static bool 2629 is_just_move (rtx x) 2630 { 2631 if (INSN_P (x)) 2632 x = PATTERN (x); 2633 2634 return (GET_CODE (x) == SET && general_operand (SET_SRC (x), VOIDmode)); 2635 } 2636 2637 /* Callback function to count autoincs. */ 2638 2639 static int 2640 count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg) 2641 { 2642 (*((int *) arg))++; 2643 2644 return 0; 2645 } 2646 2647 /* Try to combine the insns I0, I1 and I2 into I3. 2648 Here I0, I1 and I2 appear earlier than I3. 2649 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into 2650 I3. 2651 2652 If we are combining more than two insns and the resulting insn is not 2653 recognized, try splitting it into two insns. If that happens, I2 and I3 2654 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE. 2655 Otherwise, I0, I1 and I2 are pseudo-deleted. 2656 2657 Return 0 if the combination does not work. Then nothing is changed. 2658 If we did the combination, return the insn at which combine should 2659 resume scanning. 2660 2661 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a 2662 new direct jump instruction. 2663 2664 LAST_COMBINED_INSN is either I3, or some insn after I3 that has 2665 been I3 passed to an earlier try_combine within the same basic 2666 block. */ 2667 2668 static rtx_insn * 2669 try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, 2670 int *new_direct_jump_p, rtx_insn *last_combined_insn) 2671 { 2672 /* New patterns for I3 and I2, respectively. */ 2673 rtx newpat, newi2pat = 0; 2674 rtvec newpat_vec_with_clobbers = 0; 2675 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0; 2676 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not 2677 dead. */ 2678 int added_sets_0, added_sets_1, added_sets_2; 2679 /* Total number of SETs to put into I3. */ 2680 int total_sets; 2681 /* Nonzero if I2's or I1's body now appears in I3. */ 2682 int i2_is_used = 0, i1_is_used = 0; 2683 /* INSN_CODEs for new I3, new I2, and user of condition code. */ 2684 int insn_code_number, i2_code_number = 0, other_code_number = 0; 2685 /* Contains I3 if the destination of I3 is used in its source, which means 2686 that the old life of I3 is being killed. If that usage is placed into 2687 I2 and not in I3, a REG_DEAD note must be made. */ 2688 rtx i3dest_killed = 0; 2689 /* SET_DEST and SET_SRC of I2, I1 and I0. */ 2690 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0; 2691 /* Copy of SET_SRC of I1 and I0, if needed. */ 2692 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0; 2693 /* Set if I2DEST was reused as a scratch register. */ 2694 bool i2scratch = false; 2695 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */ 2696 rtx i0pat = 0, i1pat = 0, i2pat = 0; 2697 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ 2698 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; 2699 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0; 2700 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0; 2701 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0; 2702 /* Notes that must be added to REG_NOTES in I3 and I2. */ 2703 rtx new_i3_notes, new_i2_notes; 2704 /* Notes that we substituted I3 into I2 instead of the normal case. */ 2705 int i3_subst_into_i2 = 0; 2706 /* Notes that I1, I2 or I3 is a MULT operation. */ 2707 int have_mult = 0; 2708 int swap_i2i3 = 0; 2709 int split_i2i3 = 0; 2710 int changed_i3_dest = 0; 2711 bool i2_was_move = false, i3_was_move = false; 2712 int n_auto_inc = 0; 2713 2714 int maxreg; 2715 rtx_insn *temp_insn; 2716 rtx temp_expr; 2717 struct insn_link *link; 2718 rtx other_pat = 0; 2719 rtx new_other_notes; 2720 int i; 2721 scalar_int_mode dest_mode, temp_mode; 2722 2723 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can 2724 never be). */ 2725 if (i1 == i2 || i0 == i2 || (i0 && i0 == i1)) 2726 return 0; 2727 2728 /* Only try four-insn combinations when there's high likelihood of 2729 success. Look for simple insns, such as loads of constants or 2730 binary operations involving a constant. */ 2731 if (i0) 2732 { 2733 int i; 2734 int ngood = 0; 2735 int nshift = 0; 2736 rtx set0, set3; 2737 2738 if (!flag_expensive_optimizations) 2739 return 0; 2740 2741 for (i = 0; i < 4; i++) 2742 { 2743 rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3; 2744 rtx set = single_set (insn); 2745 rtx src; 2746 if (!set) 2747 continue; 2748 src = SET_SRC (set); 2749 if (CONSTANT_P (src)) 2750 { 2751 ngood += 2; 2752 break; 2753 } 2754 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1))) 2755 ngood++; 2756 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT 2757 || GET_CODE (src) == LSHIFTRT) 2758 nshift++; 2759 } 2760 2761 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2 2762 are likely manipulating its value. Ideally we'll be able to combine 2763 all four insns into a bitfield insertion of some kind. 2764 2765 Note the source in I0 might be inside a sign/zero extension and the 2766 memory modes in I0 and I3 might be different. So extract the address 2767 from the destination of I3 and search for it in the source of I0. 2768 2769 In the event that there's a match but the source/dest do not actually 2770 refer to the same memory, the worst that happens is we try some 2771 combinations that we wouldn't have otherwise. */ 2772 if ((set0 = single_set (i0)) 2773 /* Ensure the source of SET0 is a MEM, possibly buried inside 2774 an extension. */ 2775 && (GET_CODE (SET_SRC (set0)) == MEM 2776 || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND 2777 || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND) 2778 && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM)) 2779 && (set3 = single_set (i3)) 2780 /* Ensure the destination of SET3 is a MEM. */ 2781 && GET_CODE (SET_DEST (set3)) == MEM 2782 /* Would it be better to extract the base address for the MEM 2783 in SET3 and look for that? I don't have cases where it matters 2784 but I could envision such cases. */ 2785 && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0))) 2786 ngood += 2; 2787 2788 if (ngood < 2 && nshift < 2) 2789 return 0; 2790 } 2791 2792 /* Exit early if one of the insns involved can't be used for 2793 combinations. */ 2794 if (CALL_P (i2) 2795 || (i1 && CALL_P (i1)) 2796 || (i0 && CALL_P (i0)) 2797 || cant_combine_insn_p (i3) 2798 || cant_combine_insn_p (i2) 2799 || (i1 && cant_combine_insn_p (i1)) 2800 || (i0 && cant_combine_insn_p (i0)) 2801 || likely_spilled_retval_p (i3)) 2802 return 0; 2803 2804 combine_attempts++; 2805 undobuf.other_insn = 0; 2806 2807 /* Reset the hard register usage information. */ 2808 CLEAR_HARD_REG_SET (newpat_used_regs); 2809 2810 if (dump_file && (dump_flags & TDF_DETAILS)) 2811 { 2812 if (i0) 2813 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n", 2814 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); 2815 else if (i1) 2816 fprintf (dump_file, "\nTrying %d, %d -> %d:\n", 2817 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); 2818 else 2819 fprintf (dump_file, "\nTrying %d -> %d:\n", 2820 INSN_UID (i2), INSN_UID (i3)); 2821 2822 if (i0) 2823 dump_insn_slim (dump_file, i0); 2824 if (i1) 2825 dump_insn_slim (dump_file, i1); 2826 dump_insn_slim (dump_file, i2); 2827 dump_insn_slim (dump_file, i3); 2828 } 2829 2830 /* If multiple insns feed into one of I2 or I3, they can be in any 2831 order. To simplify the code below, reorder them in sequence. */ 2832 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2)) 2833 std::swap (i0, i2); 2834 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1)) 2835 std::swap (i0, i1); 2836 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2)) 2837 std::swap (i1, i2); 2838 2839 added_links_insn = 0; 2840 added_notes_insn = 0; 2841 2842 /* First check for one important special case that the code below will 2843 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL 2844 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, 2845 we may be able to replace that destination with the destination of I3. 2846 This occurs in the common code where we compute both a quotient and 2847 remainder into a structure, in which case we want to do the computation 2848 directly into the structure to avoid register-register copies. 2849 2850 Note that this case handles both multiple sets in I2 and also cases 2851 where I2 has a number of CLOBBERs inside the PARALLEL. 2852 2853 We make very conservative checks below and only try to handle the 2854 most common cases of this. For example, we only handle the case 2855 where I2 and I3 are adjacent to avoid making difficult register 2856 usage tests. */ 2857 2858 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET 2859 && REG_P (SET_SRC (PATTERN (i3))) 2860 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 2861 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) 2862 && GET_CODE (PATTERN (i2)) == PARALLEL 2863 && ! side_effects_p (SET_DEST (PATTERN (i3))) 2864 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code 2865 below would need to check what is inside (and reg_overlap_mentioned_p 2866 doesn't support those codes anyway). Don't allow those destinations; 2867 the resulting insn isn't likely to be recognized anyway. */ 2868 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT 2869 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART 2870 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), 2871 SET_DEST (PATTERN (i3))) 2872 && next_active_insn (i2) == i3) 2873 { 2874 rtx p2 = PATTERN (i2); 2875 2876 /* Make sure that the destination of I3, 2877 which we are going to substitute into one output of I2, 2878 is not used within another output of I2. We must avoid making this: 2879 (parallel [(set (mem (reg 69)) ...) 2880 (set (reg 69) ...)]) 2881 which is not well-defined as to order of actions. 2882 (Besides, reload can't handle output reloads for this.) 2883 2884 The problem can also happen if the dest of I3 is a memory ref, 2885 if another dest in I2 is an indirect memory ref. 2886 2887 Neither can this PARALLEL be an asm. We do not allow combining 2888 that usually (see can_combine_p), so do not here either. */ 2889 bool ok = true; 2890 for (i = 0; ok && i < XVECLEN (p2, 0); i++) 2891 { 2892 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 2893 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 2894 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), 2895 SET_DEST (XVECEXP (p2, 0, i)))) 2896 ok = false; 2897 else if (GET_CODE (XVECEXP (p2, 0, i)) == SET 2898 && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS) 2899 ok = false; 2900 } 2901 2902 if (ok) 2903 for (i = 0; i < XVECLEN (p2, 0); i++) 2904 if (GET_CODE (XVECEXP (p2, 0, i)) == SET 2905 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) 2906 { 2907 combine_merges++; 2908 2909 subst_insn = i3; 2910 subst_low_luid = DF_INSN_LUID (i2); 2911 2912 added_sets_2 = added_sets_1 = added_sets_0 = 0; 2913 i2src = SET_SRC (XVECEXP (p2, 0, i)); 2914 i2dest = SET_DEST (XVECEXP (p2, 0, i)); 2915 i2dest_killed = dead_or_set_p (i2, i2dest); 2916 2917 /* Replace the dest in I2 with our dest and make the resulting 2918 insn the new pattern for I3. Then skip to where we validate 2919 the pattern. Everything was set up above. */ 2920 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3))); 2921 newpat = p2; 2922 i3_subst_into_i2 = 1; 2923 goto validate_replacement; 2924 } 2925 } 2926 2927 /* If I2 is setting a pseudo to a constant and I3 is setting some 2928 sub-part of it to another constant, merge them by making a new 2929 constant. */ 2930 if (i1 == 0 2931 && (temp_expr = single_set (i2)) != 0 2932 && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), &temp_mode) 2933 && CONST_SCALAR_INT_P (SET_SRC (temp_expr)) 2934 && GET_CODE (PATTERN (i3)) == SET 2935 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3))) 2936 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr))) 2937 { 2938 rtx dest = SET_DEST (PATTERN (i3)); 2939 rtx temp_dest = SET_DEST (temp_expr); 2940 int offset = -1; 2941 int width = 0; 2942 2943 if (GET_CODE (dest) == ZERO_EXTRACT) 2944 { 2945 if (CONST_INT_P (XEXP (dest, 1)) 2946 && CONST_INT_P (XEXP (dest, 2)) 2947 && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)), 2948 &dest_mode)) 2949 { 2950 width = INTVAL (XEXP (dest, 1)); 2951 offset = INTVAL (XEXP (dest, 2)); 2952 dest = XEXP (dest, 0); 2953 if (BITS_BIG_ENDIAN) 2954 offset = GET_MODE_PRECISION (dest_mode) - width - offset; 2955 } 2956 } 2957 else 2958 { 2959 if (GET_CODE (dest) == STRICT_LOW_PART) 2960 dest = XEXP (dest, 0); 2961 if (is_a <scalar_int_mode> (GET_MODE (dest), &dest_mode)) 2962 { 2963 width = GET_MODE_PRECISION (dest_mode); 2964 offset = 0; 2965 } 2966 } 2967 2968 if (offset >= 0) 2969 { 2970 /* If this is the low part, we're done. */ 2971 if (subreg_lowpart_p (dest)) 2972 ; 2973 /* Handle the case where inner is twice the size of outer. */ 2974 else if (GET_MODE_PRECISION (temp_mode) 2975 == 2 * GET_MODE_PRECISION (dest_mode)) 2976 offset += GET_MODE_PRECISION (dest_mode); 2977 /* Otherwise give up for now. */ 2978 else 2979 offset = -1; 2980 } 2981 2982 if (offset >= 0) 2983 { 2984 rtx inner = SET_SRC (PATTERN (i3)); 2985 rtx outer = SET_SRC (temp_expr); 2986 2987 wide_int o = wi::insert (rtx_mode_t (outer, temp_mode), 2988 rtx_mode_t (inner, dest_mode), 2989 offset, width); 2990 2991 combine_merges++; 2992 subst_insn = i3; 2993 subst_low_luid = DF_INSN_LUID (i2); 2994 added_sets_2 = added_sets_1 = added_sets_0 = 0; 2995 i2dest = temp_dest; 2996 i2dest_killed = dead_or_set_p (i2, i2dest); 2997 2998 /* Replace the source in I2 with the new constant and make the 2999 resulting insn the new pattern for I3. Then skip to where we 3000 validate the pattern. Everything was set up above. */ 3001 SUBST (SET_SRC (temp_expr), 3002 immed_wide_int_const (o, temp_mode)); 3003 3004 newpat = PATTERN (i2); 3005 3006 /* The dest of I3 has been replaced with the dest of I2. */ 3007 changed_i3_dest = 1; 3008 goto validate_replacement; 3009 } 3010 } 3011 3012 /* If we have no I1 and I2 looks like: 3013 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) 3014 (set Y OP)]) 3015 make up a dummy I1 that is 3016 (set Y OP) 3017 and change I2 to be 3018 (set (reg:CC X) (compare:CC Y (const_int 0))) 3019 3020 (We can ignore any trailing CLOBBERs.) 3021 3022 This undoes a previous combination and allows us to match a branch-and- 3023 decrement insn. */ 3024 3025 if (!HAVE_cc0 && i1 == 0 3026 && is_parallel_of_n_reg_sets (PATTERN (i2), 2) 3027 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) 3028 == MODE_CC) 3029 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE 3030 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx 3031 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), 3032 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))) 3033 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3) 3034 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)) 3035 { 3036 /* We make I1 with the same INSN_UID as I2. This gives it 3037 the same DF_INSN_LUID for value tracking. Our fake I1 will 3038 never appear in the insn stream so giving it the same INSN_UID 3039 as I2 will not cause a problem. */ 3040 3041 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2), 3042 XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2), 3043 -1, NULL_RTX); 3044 INSN_UID (i1) = INSN_UID (i2); 3045 3046 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); 3047 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), 3048 SET_DEST (PATTERN (i1))); 3049 unsigned int regno = REGNO (SET_DEST (PATTERN (i1))); 3050 SUBST_LINK (LOG_LINKS (i2), 3051 alloc_insn_link (i1, regno, LOG_LINKS (i2))); 3052 } 3053 3054 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs), 3055 make those two SETs separate I1 and I2 insns, and make an I0 that is 3056 the original I1. */ 3057 if (!HAVE_cc0 && i0 == 0 3058 && is_parallel_of_n_reg_sets (PATTERN (i2), 2) 3059 && can_split_parallel_of_n_reg_sets (i2, 2) 3060 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3) 3061 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3) 3062 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3) 3063 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)) 3064 { 3065 /* If there is no I1, there is no I0 either. */ 3066 i0 = i1; 3067 3068 /* We make I1 with the same INSN_UID as I2. This gives it 3069 the same DF_INSN_LUID for value tracking. Our fake I1 will 3070 never appear in the insn stream so giving it the same INSN_UID 3071 as I2 will not cause a problem. */ 3072 3073 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2), 3074 XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2), 3075 -1, NULL_RTX); 3076 INSN_UID (i1) = INSN_UID (i2); 3077 3078 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1)); 3079 } 3080 3081 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */ 3082 if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src)) 3083 { 3084 if (dump_file && (dump_flags & TDF_DETAILS)) 3085 fprintf (dump_file, "Can't combine i2 into i3\n"); 3086 undo_all (); 3087 return 0; 3088 } 3089 if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src)) 3090 { 3091 if (dump_file && (dump_flags & TDF_DETAILS)) 3092 fprintf (dump_file, "Can't combine i1 into i3\n"); 3093 undo_all (); 3094 return 0; 3095 } 3096 if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src)) 3097 { 3098 if (dump_file && (dump_flags & TDF_DETAILS)) 3099 fprintf (dump_file, "Can't combine i0 into i3\n"); 3100 undo_all (); 3101 return 0; 3102 } 3103 3104 /* Record whether i2 and i3 are trivial moves. */ 3105 i2_was_move = is_just_move (i2); 3106 i3_was_move = is_just_move (i3); 3107 3108 /* Record whether I2DEST is used in I2SRC and similarly for the other 3109 cases. Knowing this will help in register status updating below. */ 3110 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); 3111 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); 3112 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); 3113 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src); 3114 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src); 3115 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src); 3116 i2dest_killed = dead_or_set_p (i2, i2dest); 3117 i1dest_killed = i1 && dead_or_set_p (i1, i1dest); 3118 i0dest_killed = i0 && dead_or_set_p (i0, i0dest); 3119 3120 /* For the earlier insns, determine which of the subsequent ones they 3121 feed. */ 3122 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2); 3123 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1); 3124 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2) 3125 : (!reg_overlap_mentioned_p (i1dest, i0dest) 3126 && reg_overlap_mentioned_p (i0dest, i2src)))); 3127 3128 /* Ensure that I3's pattern can be the destination of combines. */ 3129 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest, 3130 i1 && i2dest_in_i1src && !i1_feeds_i2_n, 3131 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n) 3132 || (i1dest_in_i0src && !i0_feeds_i1_n)), 3133 &i3dest_killed)) 3134 { 3135 undo_all (); 3136 return 0; 3137 } 3138 3139 /* See if any of the insns is a MULT operation. Unless one is, we will 3140 reject a combination that is, since it must be slower. Be conservative 3141 here. */ 3142 if (GET_CODE (i2src) == MULT 3143 || (i1 != 0 && GET_CODE (i1src) == MULT) 3144 || (i0 != 0 && GET_CODE (i0src) == MULT) 3145 || (GET_CODE (PATTERN (i3)) == SET 3146 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) 3147 have_mult = 1; 3148 3149 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. 3150 We used to do this EXCEPT in one case: I3 has a post-inc in an 3151 output operand. However, that exception can give rise to insns like 3152 mov r3,(r3)+ 3153 which is a famous insn on the PDP-11 where the value of r3 used as the 3154 source was model-dependent. Avoid this sort of thing. */ 3155 3156 #if 0 3157 if (!(GET_CODE (PATTERN (i3)) == SET 3158 && REG_P (SET_SRC (PATTERN (i3))) 3159 && MEM_P (SET_DEST (PATTERN (i3))) 3160 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC 3161 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) 3162 /* It's not the exception. */ 3163 #endif 3164 if (AUTO_INC_DEC) 3165 { 3166 rtx link; 3167 for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) 3168 if (REG_NOTE_KIND (link) == REG_INC 3169 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) 3170 || (i1 != 0 3171 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) 3172 { 3173 undo_all (); 3174 return 0; 3175 } 3176 } 3177 3178 /* See if the SETs in I1 or I2 need to be kept around in the merged 3179 instruction: whenever the value set there is still needed past I3. 3180 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3. 3181 3182 For the SET in I1, we have two cases: if I1 and I2 independently feed 3183 into I3, the set in I1 needs to be kept around unless I1DEST dies 3184 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set 3185 in I1 needs to be kept around unless I1DEST dies or is set in either 3186 I2 or I3. The same considerations apply to I0. */ 3187 3188 added_sets_2 = !dead_or_set_p (i3, i2dest); 3189 3190 if (i1) 3191 added_sets_1 = !(dead_or_set_p (i3, i1dest) 3192 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest))); 3193 else 3194 added_sets_1 = 0; 3195 3196 if (i0) 3197 added_sets_0 = !(dead_or_set_p (i3, i0dest) 3198 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)) 3199 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) 3200 && dead_or_set_p (i2, i0dest))); 3201 else 3202 added_sets_0 = 0; 3203 3204 /* We are about to copy insns for the case where they need to be kept 3205 around. Check that they can be copied in the merged instruction. */ 3206 3207 if (targetm.cannot_copy_insn_p 3208 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2)) 3209 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1)) 3210 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0)))) 3211 { 3212 undo_all (); 3213 return 0; 3214 } 3215 3216 /* We cannot safely duplicate volatile references in any case. */ 3217 3218 if ((added_sets_2 && volatile_refs_p (PATTERN (i2))) 3219 || (added_sets_1 && volatile_refs_p (PATTERN (i1))) 3220 || (added_sets_0 && volatile_refs_p (PATTERN (i0)))) 3221 { 3222 undo_all (); 3223 return 0; 3224 } 3225 3226 /* Count how many auto_inc expressions there were in the original insns; 3227 we need to have the same number in the resulting patterns. */ 3228 3229 if (i0) 3230 for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc); 3231 if (i1) 3232 for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc); 3233 for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc); 3234 for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc); 3235 3236 /* If the set in I2 needs to be kept around, we must make a copy of 3237 PATTERN (I2), so that when we substitute I1SRC for I1DEST in 3238 PATTERN (I2), we are only substituting for the original I1DEST, not into 3239 an already-substituted copy. This also prevents making self-referential 3240 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to 3241 I2DEST. */ 3242 3243 if (added_sets_2) 3244 { 3245 if (GET_CODE (PATTERN (i2)) == PARALLEL) 3246 i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src)); 3247 else 3248 i2pat = copy_rtx (PATTERN (i2)); 3249 } 3250 3251 if (added_sets_1) 3252 { 3253 if (GET_CODE (PATTERN (i1)) == PARALLEL) 3254 i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src)); 3255 else 3256 i1pat = copy_rtx (PATTERN (i1)); 3257 } 3258 3259 if (added_sets_0) 3260 { 3261 if (GET_CODE (PATTERN (i0)) == PARALLEL) 3262 i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src)); 3263 else 3264 i0pat = copy_rtx (PATTERN (i0)); 3265 } 3266 3267 combine_merges++; 3268 3269 /* Substitute in the latest insn for the regs set by the earlier ones. */ 3270 3271 maxreg = max_reg_num (); 3272 3273 subst_insn = i3; 3274 3275 /* Many machines that don't use CC0 have insns that can both perform an 3276 arithmetic operation and set the condition code. These operations will 3277 be represented as a PARALLEL with the first element of the vector 3278 being a COMPARE of an arithmetic operation with the constant zero. 3279 The second element of the vector will set some pseudo to the result 3280 of the same arithmetic operation. If we simplify the COMPARE, we won't 3281 match such a pattern and so will generate an extra insn. Here we test 3282 for this case, where both the comparison and the operation result are 3283 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with 3284 I2SRC. Later we will make the PARALLEL that contains I2. */ 3285 3286 if (!HAVE_cc0 && i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET 3287 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE 3288 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1)) 3289 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) 3290 { 3291 rtx newpat_dest; 3292 rtx *cc_use_loc = NULL; 3293 rtx_insn *cc_use_insn = NULL; 3294 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1); 3295 machine_mode compare_mode, orig_compare_mode; 3296 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN; 3297 scalar_int_mode mode; 3298 3299 newpat = PATTERN (i3); 3300 newpat_dest = SET_DEST (newpat); 3301 compare_mode = orig_compare_mode = GET_MODE (newpat_dest); 3302 3303 if (undobuf.other_insn == 0 3304 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3, 3305 &cc_use_insn))) 3306 { 3307 compare_code = orig_compare_code = GET_CODE (*cc_use_loc); 3308 if (is_a <scalar_int_mode> (GET_MODE (i2dest), &mode)) 3309 compare_code = simplify_compare_const (compare_code, mode, 3310 op0, &op1); 3311 target_canonicalize_comparison (&compare_code, &op0, &op1, 1); 3312 } 3313 3314 /* Do the rest only if op1 is const0_rtx, which may be the 3315 result of simplification. */ 3316 if (op1 == const0_rtx) 3317 { 3318 /* If a single use of the CC is found, prepare to modify it 3319 when SELECT_CC_MODE returns a new CC-class mode, or when 3320 the above simplify_compare_const() returned a new comparison 3321 operator. undobuf.other_insn is assigned the CC use insn 3322 when modifying it. */ 3323 if (cc_use_loc) 3324 { 3325 #ifdef SELECT_CC_MODE 3326 machine_mode new_mode 3327 = SELECT_CC_MODE (compare_code, op0, op1); 3328 if (new_mode != orig_compare_mode 3329 && can_change_dest_mode (SET_DEST (newpat), 3330 added_sets_2, new_mode)) 3331 { 3332 unsigned int regno = REGNO (newpat_dest); 3333 compare_mode = new_mode; 3334 if (regno < FIRST_PSEUDO_REGISTER) 3335 newpat_dest = gen_rtx_REG (compare_mode, regno); 3336 else 3337 { 3338 subst_mode (regno, compare_mode); 3339 newpat_dest = regno_reg_rtx[regno]; 3340 } 3341 } 3342 #endif 3343 /* Cases for modifying the CC-using comparison. */ 3344 if (compare_code != orig_compare_code 3345 /* ??? Do we need to verify the zero rtx? */ 3346 && XEXP (*cc_use_loc, 1) == const0_rtx) 3347 { 3348 /* Replace cc_use_loc with entire new RTX. */ 3349 SUBST (*cc_use_loc, 3350 gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc), 3351 newpat_dest, const0_rtx)); 3352 undobuf.other_insn = cc_use_insn; 3353 } 3354 else if (compare_mode != orig_compare_mode) 3355 { 3356 /* Just replace the CC reg with a new mode. */ 3357 SUBST (XEXP (*cc_use_loc, 0), newpat_dest); 3358 undobuf.other_insn = cc_use_insn; 3359 } 3360 } 3361 3362 /* Now we modify the current newpat: 3363 First, SET_DEST(newpat) is updated if the CC mode has been 3364 altered. For targets without SELECT_CC_MODE, this should be 3365 optimized away. */ 3366 if (compare_mode != orig_compare_mode) 3367 SUBST (SET_DEST (newpat), newpat_dest); 3368 /* This is always done to propagate i2src into newpat. */ 3369 SUBST (SET_SRC (newpat), 3370 gen_rtx_COMPARE (compare_mode, op0, op1)); 3371 /* Create new version of i2pat if needed; the below PARALLEL 3372 creation needs this to work correctly. */ 3373 if (! rtx_equal_p (i2src, op0)) 3374 i2pat = gen_rtx_SET (i2dest, op0); 3375 i2_is_used = 1; 3376 } 3377 } 3378 3379 if (i2_is_used == 0) 3380 { 3381 /* It is possible that the source of I2 or I1 may be performing 3382 an unneeded operation, such as a ZERO_EXTEND of something 3383 that is known to have the high part zero. Handle that case 3384 by letting subst look at the inner insns. 3385 3386 Another way to do this would be to have a function that tries 3387 to simplify a single insn instead of merging two or more 3388 insns. We don't do this because of the potential of infinite 3389 loops and because of the potential extra memory required. 3390 However, doing it the way we are is a bit of a kludge and 3391 doesn't catch all cases. 3392 3393 But only do this if -fexpensive-optimizations since it slows 3394 things down and doesn't usually win. 3395 3396 This is not done in the COMPARE case above because the 3397 unmodified I2PAT is used in the PARALLEL and so a pattern 3398 with a modified I2SRC would not match. */ 3399 3400 if (flag_expensive_optimizations) 3401 { 3402 /* Pass pc_rtx so no substitutions are done, just 3403 simplifications. */ 3404 if (i1) 3405 { 3406 subst_low_luid = DF_INSN_LUID (i1); 3407 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0); 3408 } 3409 3410 subst_low_luid = DF_INSN_LUID (i2); 3411 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); 3412 } 3413 3414 n_occurrences = 0; /* `subst' counts here */ 3415 subst_low_luid = DF_INSN_LUID (i2); 3416 3417 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique 3418 copy of I2SRC each time we substitute it, in order to avoid creating 3419 self-referential RTL when we will be substituting I1SRC for I1DEST 3420 later. Likewise if I0 feeds into I2, either directly or indirectly 3421 through I1, and I0DEST is in I0SRC. */ 3422 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0, 3423 (i1_feeds_i2_n && i1dest_in_i1src) 3424 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) 3425 && i0dest_in_i0src)); 3426 substed_i2 = 1; 3427 3428 /* Record whether I2's body now appears within I3's body. */ 3429 i2_is_used = n_occurrences; 3430 } 3431 3432 /* If we already got a failure, don't try to do more. Otherwise, try to 3433 substitute I1 if we have it. */ 3434 3435 if (i1 && GET_CODE (newpat) != CLOBBER) 3436 { 3437 /* Before we can do this substitution, we must redo the test done 3438 above (see detailed comments there) that ensures I1DEST isn't 3439 mentioned in any SETs in NEWPAT that are field assignments. */ 3440 if (!combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX, 3441 0, 0, 0)) 3442 { 3443 undo_all (); 3444 return 0; 3445 } 3446 3447 n_occurrences = 0; 3448 subst_low_luid = DF_INSN_LUID (i1); 3449 3450 /* If the following substitution will modify I1SRC, make a copy of it 3451 for the case where it is substituted for I1DEST in I2PAT later. */ 3452 if (added_sets_2 && i1_feeds_i2_n) 3453 i1src_copy = copy_rtx (i1src); 3454 3455 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique 3456 copy of I1SRC each time we substitute it, in order to avoid creating 3457 self-referential RTL when we will be substituting I0SRC for I0DEST 3458 later. */ 3459 newpat = subst (newpat, i1dest, i1src, 0, 0, 3460 i0_feeds_i1_n && i0dest_in_i0src); 3461 substed_i1 = 1; 3462 3463 /* Record whether I1's body now appears within I3's body. */ 3464 i1_is_used = n_occurrences; 3465 } 3466 3467 /* Likewise for I0 if we have it. */ 3468 3469 if (i0 && GET_CODE (newpat) != CLOBBER) 3470 { 3471 if (!combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX, 3472 0, 0, 0)) 3473 { 3474 undo_all (); 3475 return 0; 3476 } 3477 3478 /* If the following substitution will modify I0SRC, make a copy of it 3479 for the case where it is substituted for I0DEST in I1PAT later. */ 3480 if (added_sets_1 && i0_feeds_i1_n) 3481 i0src_copy = copy_rtx (i0src); 3482 /* And a copy for I0DEST in I2PAT substitution. */ 3483 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n) 3484 || (i0_feeds_i2_n))) 3485 i0src_copy2 = copy_rtx (i0src); 3486 3487 n_occurrences = 0; 3488 subst_low_luid = DF_INSN_LUID (i0); 3489 newpat = subst (newpat, i0dest, i0src, 0, 0, 0); 3490 substed_i0 = 1; 3491 } 3492 3493 if (n_auto_inc) 3494 { 3495 int new_n_auto_inc = 0; 3496 for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc); 3497 3498 if (n_auto_inc != new_n_auto_inc) 3499 { 3500 if (dump_file && (dump_flags & TDF_DETAILS)) 3501 fprintf (dump_file, "Number of auto_inc expressions changed\n"); 3502 undo_all (); 3503 return 0; 3504 } 3505 } 3506 3507 /* Fail if an autoincrement side-effect has been duplicated. Be careful 3508 to count all the ways that I2SRC and I1SRC can be used. */ 3509 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 3510 && i2_is_used + added_sets_2 > 1) 3511 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 3512 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) 3513 > 1)) 3514 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0 3515 && (n_occurrences + added_sets_0 3516 + (added_sets_1 && i0_feeds_i1_n) 3517 + (added_sets_2 && i0_feeds_i2_n) 3518 > 1)) 3519 /* Fail if we tried to make a new register. */ 3520 || max_reg_num () != maxreg 3521 /* Fail if we couldn't do something and have a CLOBBER. */ 3522 || GET_CODE (newpat) == CLOBBER 3523 /* Fail if this new pattern is a MULT and we didn't have one before 3524 at the outer level. */ 3525 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT 3526 && ! have_mult)) 3527 { 3528 undo_all (); 3529 return 0; 3530 } 3531 3532 /* If the actions of the earlier insns must be kept 3533 in addition to substituting them into the latest one, 3534 we must make a new PARALLEL for the latest insn 3535 to hold additional the SETs. */ 3536 3537 if (added_sets_0 || added_sets_1 || added_sets_2) 3538 { 3539 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2; 3540 combine_extras++; 3541 3542 if (GET_CODE (newpat) == PARALLEL) 3543 { 3544 rtvec old = XVEC (newpat, 0); 3545 total_sets = XVECLEN (newpat, 0) + extra_sets; 3546 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 3547 memcpy (XVEC (newpat, 0)->elem, &old->elem[0], 3548 sizeof (old->elem[0]) * old->num_elem); 3549 } 3550 else 3551 { 3552 rtx old = newpat; 3553 total_sets = 1 + extra_sets; 3554 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 3555 XVECEXP (newpat, 0, 0) = old; 3556 } 3557 3558 if (added_sets_0) 3559 XVECEXP (newpat, 0, --total_sets) = i0pat; 3560 3561 if (added_sets_1) 3562 { 3563 rtx t = i1pat; 3564 if (i0_feeds_i1_n) 3565 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0); 3566 3567 XVECEXP (newpat, 0, --total_sets) = t; 3568 } 3569 if (added_sets_2) 3570 { 3571 rtx t = i2pat; 3572 if (i1_feeds_i2_n) 3573 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0, 3574 i0_feeds_i1_n && i0dest_in_i0src); 3575 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n) 3576 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0); 3577 3578 XVECEXP (newpat, 0, --total_sets) = t; 3579 } 3580 } 3581 3582 validate_replacement: 3583 3584 /* Note which hard regs this insn has as inputs. */ 3585 mark_used_regs_combine (newpat); 3586 3587 /* If recog_for_combine fails, it strips existing clobbers. If we'll 3588 consider splitting this pattern, we might need these clobbers. */ 3589 if (i1 && GET_CODE (newpat) == PARALLEL 3590 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER) 3591 { 3592 int len = XVECLEN (newpat, 0); 3593 3594 newpat_vec_with_clobbers = rtvec_alloc (len); 3595 for (i = 0; i < len; i++) 3596 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i); 3597 } 3598 3599 /* We have recognized nothing yet. */ 3600 insn_code_number = -1; 3601 3602 /* See if this is a PARALLEL of two SETs where one SET's destination is 3603 a register that is unused and this isn't marked as an instruction that 3604 might trap in an EH region. In that case, we just need the other SET. 3605 We prefer this over the PARALLEL. 3606 3607 This can occur when simplifying a divmod insn. We *must* test for this 3608 case here because the code below that splits two independent SETs doesn't 3609 handle this case correctly when it updates the register status. 3610 3611 It's pointless doing this if we originally had two sets, one from 3612 i3, and one from i2. Combining then splitting the parallel results 3613 in the original i2 again plus an invalid insn (which we delete). 3614 The net effect is only to move instructions around, which makes 3615 debug info less accurate. 3616 3617 If the remaining SET came from I2 its destination should not be used 3618 between I2 and I3. See PR82024. */ 3619 3620 if (!(added_sets_2 && i1 == 0) 3621 && is_parallel_of_n_reg_sets (newpat, 2) 3622 && asm_noperands (newpat) < 0) 3623 { 3624 rtx set0 = XVECEXP (newpat, 0, 0); 3625 rtx set1 = XVECEXP (newpat, 0, 1); 3626 rtx oldpat = newpat; 3627 3628 if (((REG_P (SET_DEST (set1)) 3629 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1))) 3630 || (GET_CODE (SET_DEST (set1)) == SUBREG 3631 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1))))) 3632 && insn_nothrow_p (i3) 3633 && !side_effects_p (SET_SRC (set1))) 3634 { 3635 newpat = set0; 3636 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3637 } 3638 3639 else if (((REG_P (SET_DEST (set0)) 3640 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0))) 3641 || (GET_CODE (SET_DEST (set0)) == SUBREG 3642 && find_reg_note (i3, REG_UNUSED, 3643 SUBREG_REG (SET_DEST (set0))))) 3644 && insn_nothrow_p (i3) 3645 && !side_effects_p (SET_SRC (set0))) 3646 { 3647 rtx dest = SET_DEST (set1); 3648 if (GET_CODE (dest) == SUBREG) 3649 dest = SUBREG_REG (dest); 3650 if (!reg_used_between_p (dest, i2, i3)) 3651 { 3652 newpat = set1; 3653 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3654 3655 if (insn_code_number >= 0) 3656 changed_i3_dest = 1; 3657 } 3658 } 3659 3660 if (insn_code_number < 0) 3661 newpat = oldpat; 3662 } 3663 3664 /* Is the result of combination a valid instruction? */ 3665 if (insn_code_number < 0) 3666 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3667 3668 /* If we were combining three insns and the result is a simple SET 3669 with no ASM_OPERANDS that wasn't recognized, try to split it into two 3670 insns. There are two ways to do this. It can be split using a 3671 machine-specific method (like when you have an addition of a large 3672 constant) or by combine in the function find_split_point. */ 3673 3674 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET 3675 && asm_noperands (newpat) < 0) 3676 { 3677 rtx parallel, *split; 3678 rtx_insn *m_split_insn; 3679 3680 /* See if the MD file can split NEWPAT. If it can't, see if letting it 3681 use I2DEST as a scratch register will help. In the latter case, 3682 convert I2DEST to the mode of the source of NEWPAT if we can. */ 3683 3684 m_split_insn = combine_split_insns (newpat, i3); 3685 3686 /* We can only use I2DEST as a scratch reg if it doesn't overlap any 3687 inputs of NEWPAT. */ 3688 3689 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be 3690 possible to try that as a scratch reg. This would require adding 3691 more code to make it work though. */ 3692 3693 if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat)) 3694 { 3695 machine_mode new_mode = GET_MODE (SET_DEST (newpat)); 3696 3697 /* ??? Reusing i2dest without resetting the reg_stat entry for it 3698 (temporarily, until we are committed to this instruction 3699 combination) does not work: for example, any call to nonzero_bits 3700 on the register (from a splitter in the MD file, for example) 3701 will get the old information, which is invalid. 3702 3703 Since nowadays we can create registers during combine just fine, 3704 we should just create a new one here, not reuse i2dest. */ 3705 3706 /* First try to split using the original register as a 3707 scratch register. */ 3708 parallel = gen_rtx_PARALLEL (VOIDmode, 3709 gen_rtvec (2, newpat, 3710 gen_rtx_CLOBBER (VOIDmode, 3711 i2dest))); 3712 m_split_insn = combine_split_insns (parallel, i3); 3713 3714 /* If that didn't work, try changing the mode of I2DEST if 3715 we can. */ 3716 if (m_split_insn == 0 3717 && new_mode != GET_MODE (i2dest) 3718 && new_mode != VOIDmode 3719 && can_change_dest_mode (i2dest, added_sets_2, new_mode)) 3720 { 3721 machine_mode old_mode = GET_MODE (i2dest); 3722 rtx ni2dest; 3723 3724 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) 3725 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest)); 3726 else 3727 { 3728 subst_mode (REGNO (i2dest), new_mode); 3729 ni2dest = regno_reg_rtx[REGNO (i2dest)]; 3730 } 3731 3732 parallel = (gen_rtx_PARALLEL 3733 (VOIDmode, 3734 gen_rtvec (2, newpat, 3735 gen_rtx_CLOBBER (VOIDmode, 3736 ni2dest)))); 3737 m_split_insn = combine_split_insns (parallel, i3); 3738 3739 if (m_split_insn == 0 3740 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 3741 { 3742 struct undo *buf; 3743 3744 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode); 3745 buf = undobuf.undos; 3746 undobuf.undos = buf->next; 3747 buf->next = undobuf.frees; 3748 undobuf.frees = buf; 3749 } 3750 } 3751 3752 i2scratch = m_split_insn != 0; 3753 } 3754 3755 /* If recog_for_combine has discarded clobbers, try to use them 3756 again for the split. */ 3757 if (m_split_insn == 0 && newpat_vec_with_clobbers) 3758 { 3759 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers); 3760 m_split_insn = combine_split_insns (parallel, i3); 3761 } 3762 3763 if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX) 3764 { 3765 rtx m_split_pat = PATTERN (m_split_insn); 3766 insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes); 3767 if (insn_code_number >= 0) 3768 newpat = m_split_pat; 3769 } 3770 else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX 3771 && (next_nonnote_nondebug_insn (i2) == i3 3772 || !modified_between_p (PATTERN (m_split_insn), i2, i3))) 3773 { 3774 rtx i2set, i3set; 3775 rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn)); 3776 newi2pat = PATTERN (m_split_insn); 3777 3778 i3set = single_set (NEXT_INSN (m_split_insn)); 3779 i2set = single_set (m_split_insn); 3780 3781 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3782 3783 /* If I2 or I3 has multiple SETs, we won't know how to track 3784 register status, so don't use these insns. If I2's destination 3785 is used between I2 and I3, we also can't use these insns. */ 3786 3787 if (i2_code_number >= 0 && i2set && i3set 3788 && (next_nonnote_nondebug_insn (i2) == i3 3789 || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) 3790 insn_code_number = recog_for_combine (&newi3pat, i3, 3791 &new_i3_notes); 3792 if (insn_code_number >= 0) 3793 newpat = newi3pat; 3794 3795 /* It is possible that both insns now set the destination of I3. 3796 If so, we must show an extra use of it. */ 3797 3798 if (insn_code_number >= 0) 3799 { 3800 rtx new_i3_dest = SET_DEST (i3set); 3801 rtx new_i2_dest = SET_DEST (i2set); 3802 3803 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT 3804 || GET_CODE (new_i3_dest) == STRICT_LOW_PART 3805 || GET_CODE (new_i3_dest) == SUBREG) 3806 new_i3_dest = XEXP (new_i3_dest, 0); 3807 3808 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT 3809 || GET_CODE (new_i2_dest) == STRICT_LOW_PART 3810 || GET_CODE (new_i2_dest) == SUBREG) 3811 new_i2_dest = XEXP (new_i2_dest, 0); 3812 3813 if (REG_P (new_i3_dest) 3814 && REG_P (new_i2_dest) 3815 && REGNO (new_i3_dest) == REGNO (new_i2_dest) 3816 && REGNO (new_i2_dest) < reg_n_sets_max) 3817 INC_REG_N_SETS (REGNO (new_i2_dest), 1); 3818 } 3819 } 3820 3821 /* If we can split it and use I2DEST, go ahead and see if that 3822 helps things be recognized. Verify that none of the registers 3823 are set between I2 and I3. */ 3824 if (insn_code_number < 0 3825 && (split = find_split_point (&newpat, i3, false)) != 0 3826 && (!HAVE_cc0 || REG_P (i2dest)) 3827 /* We need I2DEST in the proper mode. If it is a hard register 3828 or the only use of a pseudo, we can change its mode. 3829 Make sure we don't change a hard register to have a mode that 3830 isn't valid for it, or change the number of registers. */ 3831 && (GET_MODE (*split) == GET_MODE (i2dest) 3832 || GET_MODE (*split) == VOIDmode 3833 || can_change_dest_mode (i2dest, added_sets_2, 3834 GET_MODE (*split))) 3835 && (next_nonnote_nondebug_insn (i2) == i3 3836 || !modified_between_p (*split, i2, i3)) 3837 /* We can't overwrite I2DEST if its value is still used by 3838 NEWPAT. */ 3839 && ! reg_referenced_p (i2dest, newpat)) 3840 { 3841 rtx newdest = i2dest; 3842 enum rtx_code split_code = GET_CODE (*split); 3843 machine_mode split_mode = GET_MODE (*split); 3844 bool subst_done = false; 3845 newi2pat = NULL_RTX; 3846 3847 i2scratch = true; 3848 3849 /* *SPLIT may be part of I2SRC, so make sure we have the 3850 original expression around for later debug processing. 3851 We should not need I2SRC any more in other cases. */ 3852 if (MAY_HAVE_DEBUG_BIND_INSNS) 3853 i2src = copy_rtx (i2src); 3854 else 3855 i2src = NULL; 3856 3857 /* Get NEWDEST as a register in the proper mode. We have already 3858 validated that we can do this. */ 3859 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) 3860 { 3861 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) 3862 newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); 3863 else 3864 { 3865 subst_mode (REGNO (i2dest), split_mode); 3866 newdest = regno_reg_rtx[REGNO (i2dest)]; 3867 } 3868 } 3869 3870 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to 3871 an ASHIFT. This can occur if it was inside a PLUS and hence 3872 appeared to be a memory address. This is a kludge. */ 3873 if (split_code == MULT 3874 && CONST_INT_P (XEXP (*split, 1)) 3875 && INTVAL (XEXP (*split, 1)) > 0 3876 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0) 3877 { 3878 rtx i_rtx = gen_int_shift_amount (split_mode, i); 3879 SUBST (*split, gen_rtx_ASHIFT (split_mode, 3880 XEXP (*split, 0), i_rtx)); 3881 /* Update split_code because we may not have a multiply 3882 anymore. */ 3883 split_code = GET_CODE (*split); 3884 } 3885 3886 /* Similarly for (plus (mult FOO (const_int pow2))). */ 3887 if (split_code == PLUS 3888 && GET_CODE (XEXP (*split, 0)) == MULT 3889 && CONST_INT_P (XEXP (XEXP (*split, 0), 1)) 3890 && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0 3891 && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0) 3892 { 3893 rtx nsplit = XEXP (*split, 0); 3894 rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i); 3895 SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit), 3896 XEXP (nsplit, 0), 3897 i_rtx)); 3898 /* Update split_code because we may not have a multiply 3899 anymore. */ 3900 split_code = GET_CODE (*split); 3901 } 3902 3903 #ifdef INSN_SCHEDULING 3904 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should 3905 be written as a ZERO_EXTEND. */ 3906 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))) 3907 { 3908 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's 3909 what it really is. */ 3910 if (load_extend_op (GET_MODE (SUBREG_REG (*split))) 3911 == SIGN_EXTEND) 3912 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, 3913 SUBREG_REG (*split))); 3914 else 3915 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, 3916 SUBREG_REG (*split))); 3917 } 3918 #endif 3919 3920 /* Attempt to split binary operators using arithmetic identities. */ 3921 if (BINARY_P (SET_SRC (newpat)) 3922 && split_mode == GET_MODE (SET_SRC (newpat)) 3923 && ! side_effects_p (SET_SRC (newpat))) 3924 { 3925 rtx setsrc = SET_SRC (newpat); 3926 machine_mode mode = GET_MODE (setsrc); 3927 enum rtx_code code = GET_CODE (setsrc); 3928 rtx src_op0 = XEXP (setsrc, 0); 3929 rtx src_op1 = XEXP (setsrc, 1); 3930 3931 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */ 3932 if (rtx_equal_p (src_op0, src_op1)) 3933 { 3934 newi2pat = gen_rtx_SET (newdest, src_op0); 3935 SUBST (XEXP (setsrc, 0), newdest); 3936 SUBST (XEXP (setsrc, 1), newdest); 3937 subst_done = true; 3938 } 3939 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */ 3940 else if ((code == PLUS || code == MULT) 3941 && GET_CODE (src_op0) == code 3942 && GET_CODE (XEXP (src_op0, 0)) == code 3943 && (INTEGRAL_MODE_P (mode) 3944 || (FLOAT_MODE_P (mode) 3945 && flag_unsafe_math_optimizations))) 3946 { 3947 rtx p = XEXP (XEXP (src_op0, 0), 0); 3948 rtx q = XEXP (XEXP (src_op0, 0), 1); 3949 rtx r = XEXP (src_op0, 1); 3950 rtx s = src_op1; 3951 3952 /* Split both "((X op Y) op X) op Y" and 3953 "((X op Y) op Y) op X" as "T op T" where T is 3954 "X op Y". */ 3955 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s)) 3956 || (rtx_equal_p (p,s) && rtx_equal_p (q,r))) 3957 { 3958 newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0)); 3959 SUBST (XEXP (setsrc, 0), newdest); 3960 SUBST (XEXP (setsrc, 1), newdest); 3961 subst_done = true; 3962 } 3963 /* Split "((X op X) op Y) op Y)" as "T op T" where 3964 T is "X op Y". */ 3965 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s)) 3966 { 3967 rtx tmp = simplify_gen_binary (code, mode, p, r); 3968 newi2pat = gen_rtx_SET (newdest, tmp); 3969 SUBST (XEXP (setsrc, 0), newdest); 3970 SUBST (XEXP (setsrc, 1), newdest); 3971 subst_done = true; 3972 } 3973 } 3974 } 3975 3976 if (!subst_done) 3977 { 3978 newi2pat = gen_rtx_SET (newdest, *split); 3979 SUBST (*split, newdest); 3980 } 3981 3982 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3983 3984 /* recog_for_combine might have added CLOBBERs to newi2pat. 3985 Make sure NEWPAT does not depend on the clobbered regs. */ 3986 if (GET_CODE (newi2pat) == PARALLEL) 3987 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) 3988 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) 3989 { 3990 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); 3991 if (reg_overlap_mentioned_p (reg, newpat)) 3992 { 3993 undo_all (); 3994 return 0; 3995 } 3996 } 3997 3998 /* If the split point was a MULT and we didn't have one before, 3999 don't use one now. */ 4000 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) 4001 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 4002 } 4003 } 4004 4005 /* Check for a case where we loaded from memory in a narrow mode and 4006 then sign extended it, but we need both registers. In that case, 4007 we have a PARALLEL with both loads from the same memory location. 4008 We can split this into a load from memory followed by a register-register 4009 copy. This saves at least one insn, more if register allocation can 4010 eliminate the copy. 4011 4012 We cannot do this if the destination of the first assignment is a 4013 condition code register or cc0. We eliminate this case by making sure 4014 the SET_DEST and SET_SRC have the same mode. 4015 4016 We cannot do this if the destination of the second assignment is 4017 a register that we have already assumed is zero-extended. Similarly 4018 for a SUBREG of such a register. */ 4019 4020 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 4021 && GET_CODE (newpat) == PARALLEL 4022 && XVECLEN (newpat, 0) == 2 4023 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 4024 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND 4025 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) 4026 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) 4027 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 4028 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), 4029 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) 4030 && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3) 4031 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 4032 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 4033 && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)), 4034 (REG_P (temp_expr) 4035 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0 4036 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)), 4037 BITS_PER_WORD) 4038 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)), 4039 HOST_BITS_PER_INT) 4040 && (reg_stat[REGNO (temp_expr)].nonzero_bits 4041 != GET_MODE_MASK (word_mode)))) 4042 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG 4043 && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), 4044 (REG_P (temp_expr) 4045 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0 4046 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)), 4047 BITS_PER_WORD) 4048 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)), 4049 HOST_BITS_PER_INT) 4050 && (reg_stat[REGNO (temp_expr)].nonzero_bits 4051 != GET_MODE_MASK (word_mode))))) 4052 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), 4053 SET_SRC (XVECEXP (newpat, 0, 1))) 4054 && ! find_reg_note (i3, REG_UNUSED, 4055 SET_DEST (XVECEXP (newpat, 0, 0)))) 4056 { 4057 rtx ni2dest; 4058 4059 newi2pat = XVECEXP (newpat, 0, 0); 4060 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); 4061 newpat = XVECEXP (newpat, 0, 1); 4062 SUBST (SET_SRC (newpat), 4063 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest)); 4064 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 4065 4066 if (i2_code_number >= 0) 4067 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 4068 4069 if (insn_code_number >= 0) 4070 swap_i2i3 = 1; 4071 } 4072 4073 /* Similarly, check for a case where we have a PARALLEL of two independent 4074 SETs but we started with three insns. In this case, we can do the sets 4075 as two separate insns. This case occurs when some SET allows two 4076 other insns to combine, but the destination of that SET is still live. 4077 4078 Also do this if we started with two insns and (at least) one of the 4079 resulting sets is a noop; this noop will be deleted later. 4080 4081 Also do this if we started with two insns neither of which was a simple 4082 move. */ 4083 4084 else if (insn_code_number < 0 && asm_noperands (newpat) < 0 4085 && GET_CODE (newpat) == PARALLEL 4086 && XVECLEN (newpat, 0) == 2 4087 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 4088 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 4089 && (i1 4090 || set_noop_p (XVECEXP (newpat, 0, 0)) 4091 || set_noop_p (XVECEXP (newpat, 0, 1)) 4092 || (!i2_was_move && !i3_was_move)) 4093 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT 4094 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART 4095 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 4096 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 4097 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), 4098 XVECEXP (newpat, 0, 0)) 4099 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), 4100 XVECEXP (newpat, 0, 1)) 4101 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) 4102 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) 4103 { 4104 rtx set0 = XVECEXP (newpat, 0, 0); 4105 rtx set1 = XVECEXP (newpat, 0, 1); 4106 4107 /* Normally, it doesn't matter which of the two is done first, 4108 but the one that references cc0 can't be the second, and 4109 one which uses any regs/memory set in between i2 and i3 can't 4110 be first. The PARALLEL might also have been pre-existing in i3, 4111 so we need to make sure that we won't wrongly hoist a SET to i2 4112 that would conflict with a death note present in there, or would 4113 have its dest modified between i2 and i3. */ 4114 if (!modified_between_p (SET_SRC (set1), i2, i3) 4115 && !(REG_P (SET_DEST (set1)) 4116 && find_reg_note (i2, REG_DEAD, SET_DEST (set1))) 4117 && !(GET_CODE (SET_DEST (set1)) == SUBREG 4118 && find_reg_note (i2, REG_DEAD, 4119 SUBREG_REG (SET_DEST (set1)))) 4120 && !modified_between_p (SET_DEST (set1), i2, i3) 4121 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set0)) 4122 /* If I3 is a jump, ensure that set0 is a jump so that 4123 we do not create invalid RTL. */ 4124 && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx) 4125 ) 4126 { 4127 newi2pat = set1; 4128 newpat = set0; 4129 } 4130 else if (!modified_between_p (SET_SRC (set0), i2, i3) 4131 && !(REG_P (SET_DEST (set0)) 4132 && find_reg_note (i2, REG_DEAD, SET_DEST (set0))) 4133 && !(GET_CODE (SET_DEST (set0)) == SUBREG 4134 && find_reg_note (i2, REG_DEAD, 4135 SUBREG_REG (SET_DEST (set0)))) 4136 && !modified_between_p (SET_DEST (set0), i2, i3) 4137 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set1)) 4138 /* If I3 is a jump, ensure that set1 is a jump so that 4139 we do not create invalid RTL. */ 4140 && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx) 4141 ) 4142 { 4143 newi2pat = set0; 4144 newpat = set1; 4145 } 4146 else 4147 { 4148 undo_all (); 4149 return 0; 4150 } 4151 4152 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 4153 4154 if (i2_code_number >= 0) 4155 { 4156 /* recog_for_combine might have added CLOBBERs to newi2pat. 4157 Make sure NEWPAT does not depend on the clobbered regs. */ 4158 if (GET_CODE (newi2pat) == PARALLEL) 4159 { 4160 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) 4161 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) 4162 { 4163 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); 4164 if (reg_overlap_mentioned_p (reg, newpat)) 4165 { 4166 undo_all (); 4167 return 0; 4168 } 4169 } 4170 } 4171 4172 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 4173 4174 if (insn_code_number >= 0) 4175 split_i2i3 = 1; 4176 } 4177 } 4178 4179 /* If it still isn't recognized, fail and change things back the way they 4180 were. */ 4181 if ((insn_code_number < 0 4182 /* Is the result a reasonable ASM_OPERANDS? */ 4183 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) 4184 { 4185 undo_all (); 4186 return 0; 4187 } 4188 4189 /* If we had to change another insn, make sure it is valid also. */ 4190 if (undobuf.other_insn) 4191 { 4192 CLEAR_HARD_REG_SET (newpat_used_regs); 4193 4194 other_pat = PATTERN (undobuf.other_insn); 4195 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, 4196 &new_other_notes); 4197 4198 if (other_code_number < 0 && ! check_asm_operands (other_pat)) 4199 { 4200 undo_all (); 4201 return 0; 4202 } 4203 } 4204 4205 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether 4206 they are adjacent to each other or not. */ 4207 if (HAVE_cc0) 4208 { 4209 rtx_insn *p = prev_nonnote_insn (i3); 4210 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat 4211 && sets_cc0_p (newi2pat)) 4212 { 4213 undo_all (); 4214 return 0; 4215 } 4216 } 4217 4218 /* Only allow this combination if insn_cost reports that the 4219 replacement instructions are cheaper than the originals. */ 4220 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat)) 4221 { 4222 undo_all (); 4223 return 0; 4224 } 4225 4226 if (MAY_HAVE_DEBUG_BIND_INSNS) 4227 { 4228 struct undo *undo; 4229 4230 for (undo = undobuf.undos; undo; undo = undo->next) 4231 if (undo->kind == UNDO_MODE) 4232 { 4233 rtx reg = regno_reg_rtx[undo->where.regno]; 4234 machine_mode new_mode = GET_MODE (reg); 4235 machine_mode old_mode = undo->old_contents.m; 4236 4237 /* Temporarily revert mode back. */ 4238 adjust_reg_mode (reg, old_mode); 4239 4240 if (reg == i2dest && i2scratch) 4241 { 4242 /* If we used i2dest as a scratch register with a 4243 different mode, substitute it for the original 4244 i2src while its original mode is temporarily 4245 restored, and then clear i2scratch so that we don't 4246 do it again later. */ 4247 propagate_for_debug (i2, last_combined_insn, reg, i2src, 4248 this_basic_block); 4249 i2scratch = false; 4250 /* Put back the new mode. */ 4251 adjust_reg_mode (reg, new_mode); 4252 } 4253 else 4254 { 4255 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg)); 4256 rtx_insn *first, *last; 4257 4258 if (reg == i2dest) 4259 { 4260 first = i2; 4261 last = last_combined_insn; 4262 } 4263 else 4264 { 4265 first = i3; 4266 last = undobuf.other_insn; 4267 gcc_assert (last); 4268 if (DF_INSN_LUID (last) 4269 < DF_INSN_LUID (last_combined_insn)) 4270 last = last_combined_insn; 4271 } 4272 4273 /* We're dealing with a reg that changed mode but not 4274 meaning, so we want to turn it into a subreg for 4275 the new mode. However, because of REG sharing and 4276 because its mode had already changed, we have to do 4277 it in two steps. First, replace any debug uses of 4278 reg, with its original mode temporarily restored, 4279 with this copy we have created; then, replace the 4280 copy with the SUBREG of the original shared reg, 4281 once again changed to the new mode. */ 4282 propagate_for_debug (first, last, reg, tempreg, 4283 this_basic_block); 4284 adjust_reg_mode (reg, new_mode); 4285 propagate_for_debug (first, last, tempreg, 4286 lowpart_subreg (old_mode, reg, new_mode), 4287 this_basic_block); 4288 } 4289 } 4290 } 4291 4292 /* If we will be able to accept this, we have made a 4293 change to the destination of I3. This requires us to 4294 do a few adjustments. */ 4295 4296 if (changed_i3_dest) 4297 { 4298 PATTERN (i3) = newpat; 4299 adjust_for_new_dest (i3); 4300 } 4301 4302 /* We now know that we can do this combination. Merge the insns and 4303 update the status of registers and LOG_LINKS. */ 4304 4305 if (undobuf.other_insn) 4306 { 4307 rtx note, next; 4308 4309 PATTERN (undobuf.other_insn) = other_pat; 4310 4311 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED, 4312 ensure that they are still valid. Then add any non-duplicate 4313 notes added by recog_for_combine. */ 4314 for (note = REG_NOTES (undobuf.other_insn); note; note = next) 4315 { 4316 next = XEXP (note, 1); 4317 4318 if ((REG_NOTE_KIND (note) == REG_DEAD 4319 && !reg_referenced_p (XEXP (note, 0), 4320 PATTERN (undobuf.other_insn))) 4321 ||(REG_NOTE_KIND (note) == REG_UNUSED 4322 && !reg_set_p (XEXP (note, 0), 4323 PATTERN (undobuf.other_insn))) 4324 /* Simply drop equal note since it may be no longer valid 4325 for other_insn. It may be possible to record that CC 4326 register is changed and only discard those notes, but 4327 in practice it's unnecessary complication and doesn't 4328 give any meaningful improvement. 4329 4330 See PR78559. */ 4331 || REG_NOTE_KIND (note) == REG_EQUAL 4332 || REG_NOTE_KIND (note) == REG_EQUIV) 4333 remove_note (undobuf.other_insn, note); 4334 } 4335 4336 distribute_notes (new_other_notes, undobuf.other_insn, 4337 undobuf.other_insn, NULL, NULL_RTX, NULL_RTX, 4338 NULL_RTX); 4339 } 4340 4341 if (swap_i2i3) 4342 { 4343 /* I3 now uses what used to be its destination and which is now 4344 I2's destination. This requires us to do a few adjustments. */ 4345 PATTERN (i3) = newpat; 4346 adjust_for_new_dest (i3); 4347 } 4348 4349 if (swap_i2i3 || split_i2i3) 4350 { 4351 /* We might need a LOG_LINK from I3 to I2. But then we used to 4352 have one, so we still will. 4353 4354 However, some later insn might be using I2's dest and have 4355 a LOG_LINK pointing at I3. We should change it to point at 4356 I2 instead. */ 4357 4358 /* newi2pat is usually a SET here; however, recog_for_combine might 4359 have added some clobbers. */ 4360 rtx x = newi2pat; 4361 if (GET_CODE (x) == PARALLEL) 4362 x = XVECEXP (newi2pat, 0, 0); 4363 4364 if (REG_P (SET_DEST (x)) 4365 || (GET_CODE (SET_DEST (x)) == SUBREG 4366 && REG_P (SUBREG_REG (SET_DEST (x))))) 4367 { 4368 unsigned int regno = reg_or_subregno (SET_DEST (x)); 4369 4370 bool done = false; 4371 for (rtx_insn *insn = NEXT_INSN (i3); 4372 !done 4373 && insn 4374 && INSN_P (insn) 4375 && BLOCK_FOR_INSN (insn) == this_basic_block; 4376 insn = NEXT_INSN (insn)) 4377 { 4378 if (DEBUG_INSN_P (insn)) 4379 continue; 4380 struct insn_link *link; 4381 FOR_EACH_LOG_LINK (link, insn) 4382 if (link->insn == i3 && link->regno == regno) 4383 { 4384 link->insn = i2; 4385 done = true; 4386 break; 4387 } 4388 } 4389 } 4390 } 4391 4392 { 4393 rtx i3notes, i2notes, i1notes = 0, i0notes = 0; 4394 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0; 4395 rtx midnotes = 0; 4396 int from_luid; 4397 /* Compute which registers we expect to eliminate. newi2pat may be setting 4398 either i3dest or i2dest, so we must check it. */ 4399 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) 4400 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src 4401 || !i2dest_killed 4402 ? 0 : i2dest); 4403 /* For i1, we need to compute both local elimination and global 4404 elimination information with respect to newi2pat because i1dest 4405 may be the same as i3dest, in which case newi2pat may be setting 4406 i1dest. Global information is used when distributing REG_DEAD 4407 note for i2 and i3, in which case it does matter if newi2pat sets 4408 i1dest or not. 4409 4410 Local information is used when distributing REG_DEAD note for i1, 4411 in which case it doesn't matter if newi2pat sets i1dest or not. 4412 See PR62151, if we have four insns combination: 4413 i0: r0 <- i0src 4414 i1: r1 <- i1src (using r0) 4415 REG_DEAD (r0) 4416 i2: r0 <- i2src (using r1) 4417 i3: r3 <- i3src (using r0) 4418 ix: using r0 4419 From i1's point of view, r0 is eliminated, no matter if it is set 4420 by newi2pat or not. In other words, REG_DEAD info for r0 in i1 4421 should be discarded. 4422 4423 Note local information only affects cases in forms like "I1->I2->I3", 4424 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like 4425 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or 4426 i0dest anyway. */ 4427 rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src 4428 || !i1dest_killed 4429 ? 0 : i1dest); 4430 rtx elim_i1 = (local_elim_i1 == 0 4431 || (newi2pat && reg_set_p (i1dest, newi2pat)) 4432 ? 0 : i1dest); 4433 /* Same case as i1. */ 4434 rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed 4435 ? 0 : i0dest); 4436 rtx elim_i0 = (local_elim_i0 == 0 4437 || (newi2pat && reg_set_p (i0dest, newi2pat)) 4438 ? 0 : i0dest); 4439 4440 /* Get the old REG_NOTES and LOG_LINKS from all our insns and 4441 clear them. */ 4442 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); 4443 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); 4444 if (i1) 4445 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); 4446 if (i0) 4447 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0); 4448 4449 /* Ensure that we do not have something that should not be shared but 4450 occurs multiple times in the new insns. Check this by first 4451 resetting all the `used' flags and then copying anything is shared. */ 4452 4453 reset_used_flags (i3notes); 4454 reset_used_flags (i2notes); 4455 reset_used_flags (i1notes); 4456 reset_used_flags (i0notes); 4457 reset_used_flags (newpat); 4458 reset_used_flags (newi2pat); 4459 if (undobuf.other_insn) 4460 reset_used_flags (PATTERN (undobuf.other_insn)); 4461 4462 i3notes = copy_rtx_if_shared (i3notes); 4463 i2notes = copy_rtx_if_shared (i2notes); 4464 i1notes = copy_rtx_if_shared (i1notes); 4465 i0notes = copy_rtx_if_shared (i0notes); 4466 newpat = copy_rtx_if_shared (newpat); 4467 newi2pat = copy_rtx_if_shared (newi2pat); 4468 if (undobuf.other_insn) 4469 reset_used_flags (PATTERN (undobuf.other_insn)); 4470 4471 INSN_CODE (i3) = insn_code_number; 4472 PATTERN (i3) = newpat; 4473 4474 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3)) 4475 { 4476 for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link; 4477 link = XEXP (link, 1)) 4478 { 4479 if (substed_i2) 4480 { 4481 /* I2SRC must still be meaningful at this point. Some 4482 splitting operations can invalidate I2SRC, but those 4483 operations do not apply to calls. */ 4484 gcc_assert (i2src); 4485 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0), 4486 i2dest, i2src); 4487 } 4488 if (substed_i1) 4489 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0), 4490 i1dest, i1src); 4491 if (substed_i0) 4492 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0), 4493 i0dest, i0src); 4494 } 4495 } 4496 4497 if (undobuf.other_insn) 4498 INSN_CODE (undobuf.other_insn) = other_code_number; 4499 4500 /* We had one special case above where I2 had more than one set and 4501 we replaced a destination of one of those sets with the destination 4502 of I3. In that case, we have to update LOG_LINKS of insns later 4503 in this basic block. Note that this (expensive) case is rare. 4504 4505 Also, in this case, we must pretend that all REG_NOTEs for I2 4506 actually came from I3, so that REG_UNUSED notes from I2 will be 4507 properly handled. */ 4508 4509 if (i3_subst_into_i2) 4510 { 4511 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) 4512 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET 4513 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER) 4514 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) 4515 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest 4516 && ! find_reg_note (i2, REG_UNUSED, 4517 SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) 4518 for (temp_insn = NEXT_INSN (i2); 4519 temp_insn 4520 && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 4521 || BB_HEAD (this_basic_block) != temp_insn); 4522 temp_insn = NEXT_INSN (temp_insn)) 4523 if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn)) 4524 FOR_EACH_LOG_LINK (link, temp_insn) 4525 if (link->insn == i2) 4526 link->insn = i3; 4527 4528 if (i3notes) 4529 { 4530 rtx link = i3notes; 4531 while (XEXP (link, 1)) 4532 link = XEXP (link, 1); 4533 XEXP (link, 1) = i2notes; 4534 } 4535 else 4536 i3notes = i2notes; 4537 i2notes = 0; 4538 } 4539 4540 LOG_LINKS (i3) = NULL; 4541 REG_NOTES (i3) = 0; 4542 LOG_LINKS (i2) = NULL; 4543 REG_NOTES (i2) = 0; 4544 4545 if (newi2pat) 4546 { 4547 if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch) 4548 propagate_for_debug (i2, last_combined_insn, i2dest, i2src, 4549 this_basic_block); 4550 INSN_CODE (i2) = i2_code_number; 4551 PATTERN (i2) = newi2pat; 4552 } 4553 else 4554 { 4555 if (MAY_HAVE_DEBUG_BIND_INSNS && i2src) 4556 propagate_for_debug (i2, last_combined_insn, i2dest, i2src, 4557 this_basic_block); 4558 SET_INSN_DELETED (i2); 4559 } 4560 4561 if (i1) 4562 { 4563 LOG_LINKS (i1) = NULL; 4564 REG_NOTES (i1) = 0; 4565 if (MAY_HAVE_DEBUG_BIND_INSNS) 4566 propagate_for_debug (i1, last_combined_insn, i1dest, i1src, 4567 this_basic_block); 4568 SET_INSN_DELETED (i1); 4569 } 4570 4571 if (i0) 4572 { 4573 LOG_LINKS (i0) = NULL; 4574 REG_NOTES (i0) = 0; 4575 if (MAY_HAVE_DEBUG_BIND_INSNS) 4576 propagate_for_debug (i0, last_combined_insn, i0dest, i0src, 4577 this_basic_block); 4578 SET_INSN_DELETED (i0); 4579 } 4580 4581 /* Get death notes for everything that is now used in either I3 or 4582 I2 and used to die in a previous insn. If we built two new 4583 patterns, move from I1 to I2 then I2 to I3 so that we get the 4584 proper movement on registers that I2 modifies. */ 4585 4586 if (i0) 4587 from_luid = DF_INSN_LUID (i0); 4588 else if (i1) 4589 from_luid = DF_INSN_LUID (i1); 4590 else 4591 from_luid = DF_INSN_LUID (i2); 4592 if (newi2pat) 4593 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes); 4594 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes); 4595 4596 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 4597 if (i3notes) 4598 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL, 4599 elim_i2, elim_i1, elim_i0); 4600 if (i2notes) 4601 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL, 4602 elim_i2, elim_i1, elim_i0); 4603 if (i1notes) 4604 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL, 4605 elim_i2, local_elim_i1, local_elim_i0); 4606 if (i0notes) 4607 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL, 4608 elim_i2, elim_i1, local_elim_i0); 4609 if (midnotes) 4610 distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL, 4611 elim_i2, elim_i1, elim_i0); 4612 4613 /* Distribute any notes added to I2 or I3 by recog_for_combine. We 4614 know these are REG_UNUSED and want them to go to the desired insn, 4615 so we always pass it as i3. */ 4616 4617 if (newi2pat && new_i2_notes) 4618 distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX, 4619 NULL_RTX); 4620 4621 if (new_i3_notes) 4622 distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX, 4623 NULL_RTX); 4624 4625 /* If I3DEST was used in I3SRC, it really died in I3. We may need to 4626 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets 4627 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 4628 in that case, it might delete I2. Similarly for I2 and I1. 4629 Show an additional death due to the REG_DEAD note we make here. If 4630 we discard it in distribute_notes, we will decrement it again. */ 4631 4632 if (i3dest_killed) 4633 { 4634 rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX); 4635 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) 4636 distribute_notes (new_note, NULL, i2, NULL, elim_i2, 4637 elim_i1, elim_i0); 4638 else 4639 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4640 elim_i2, elim_i1, elim_i0); 4641 } 4642 4643 if (i2dest_in_i2src) 4644 { 4645 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX); 4646 if (newi2pat && reg_set_p (i2dest, newi2pat)) 4647 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, 4648 NULL_RTX, NULL_RTX); 4649 else 4650 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4651 NULL_RTX, NULL_RTX, NULL_RTX); 4652 } 4653 4654 if (i1dest_in_i1src) 4655 { 4656 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX); 4657 if (newi2pat && reg_set_p (i1dest, newi2pat)) 4658 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, 4659 NULL_RTX, NULL_RTX); 4660 else 4661 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4662 NULL_RTX, NULL_RTX, NULL_RTX); 4663 } 4664 4665 if (i0dest_in_i0src) 4666 { 4667 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX); 4668 if (newi2pat && reg_set_p (i0dest, newi2pat)) 4669 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, 4670 NULL_RTX, NULL_RTX); 4671 else 4672 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4673 NULL_RTX, NULL_RTX, NULL_RTX); 4674 } 4675 4676 distribute_links (i3links); 4677 distribute_links (i2links); 4678 distribute_links (i1links); 4679 distribute_links (i0links); 4680 4681 if (REG_P (i2dest)) 4682 { 4683 struct insn_link *link; 4684 rtx_insn *i2_insn = 0; 4685 rtx i2_val = 0, set; 4686 4687 /* The insn that used to set this register doesn't exist, and 4688 this life of the register may not exist either. See if one of 4689 I3's links points to an insn that sets I2DEST. If it does, 4690 that is now the last known value for I2DEST. If we don't update 4691 this and I2 set the register to a value that depended on its old 4692 contents, we will get confused. If this insn is used, thing 4693 will be set correctly in combine_instructions. */ 4694 FOR_EACH_LOG_LINK (link, i3) 4695 if ((set = single_set (link->insn)) != 0 4696 && rtx_equal_p (i2dest, SET_DEST (set))) 4697 i2_insn = link->insn, i2_val = SET_SRC (set); 4698 4699 record_value_for_reg (i2dest, i2_insn, i2_val); 4700 4701 /* If the reg formerly set in I2 died only once and that was in I3, 4702 zero its use count so it won't make `reload' do any work. */ 4703 if (! added_sets_2 4704 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) 4705 && ! i2dest_in_i2src 4706 && REGNO (i2dest) < reg_n_sets_max) 4707 INC_REG_N_SETS (REGNO (i2dest), -1); 4708 } 4709 4710 if (i1 && REG_P (i1dest)) 4711 { 4712 struct insn_link *link; 4713 rtx_insn *i1_insn = 0; 4714 rtx i1_val = 0, set; 4715 4716 FOR_EACH_LOG_LINK (link, i3) 4717 if ((set = single_set (link->insn)) != 0 4718 && rtx_equal_p (i1dest, SET_DEST (set))) 4719 i1_insn = link->insn, i1_val = SET_SRC (set); 4720 4721 record_value_for_reg (i1dest, i1_insn, i1_val); 4722 4723 if (! added_sets_1 4724 && ! i1dest_in_i1src 4725 && REGNO (i1dest) < reg_n_sets_max) 4726 INC_REG_N_SETS (REGNO (i1dest), -1); 4727 } 4728 4729 if (i0 && REG_P (i0dest)) 4730 { 4731 struct insn_link *link; 4732 rtx_insn *i0_insn = 0; 4733 rtx i0_val = 0, set; 4734 4735 FOR_EACH_LOG_LINK (link, i3) 4736 if ((set = single_set (link->insn)) != 0 4737 && rtx_equal_p (i0dest, SET_DEST (set))) 4738 i0_insn = link->insn, i0_val = SET_SRC (set); 4739 4740 record_value_for_reg (i0dest, i0_insn, i0_val); 4741 4742 if (! added_sets_0 4743 && ! i0dest_in_i0src 4744 && REGNO (i0dest) < reg_n_sets_max) 4745 INC_REG_N_SETS (REGNO (i0dest), -1); 4746 } 4747 4748 /* Update reg_stat[].nonzero_bits et al for any changes that may have 4749 been made to this insn. The order is important, because newi2pat 4750 can affect nonzero_bits of newpat. */ 4751 if (newi2pat) 4752 note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); 4753 note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); 4754 } 4755 4756 if (undobuf.other_insn != NULL_RTX) 4757 { 4758 if (dump_file) 4759 { 4760 fprintf (dump_file, "modifying other_insn "); 4761 dump_insn_slim (dump_file, undobuf.other_insn); 4762 } 4763 df_insn_rescan (undobuf.other_insn); 4764 } 4765 4766 if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED))) 4767 { 4768 if (dump_file) 4769 { 4770 fprintf (dump_file, "modifying insn i0 "); 4771 dump_insn_slim (dump_file, i0); 4772 } 4773 df_insn_rescan (i0); 4774 } 4775 4776 if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED))) 4777 { 4778 if (dump_file) 4779 { 4780 fprintf (dump_file, "modifying insn i1 "); 4781 dump_insn_slim (dump_file, i1); 4782 } 4783 df_insn_rescan (i1); 4784 } 4785 4786 if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED))) 4787 { 4788 if (dump_file) 4789 { 4790 fprintf (dump_file, "modifying insn i2 "); 4791 dump_insn_slim (dump_file, i2); 4792 } 4793 df_insn_rescan (i2); 4794 } 4795 4796 if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED))) 4797 { 4798 if (dump_file) 4799 { 4800 fprintf (dump_file, "modifying insn i3 "); 4801 dump_insn_slim (dump_file, i3); 4802 } 4803 df_insn_rescan (i3); 4804 } 4805 4806 /* Set new_direct_jump_p if a new return or simple jump instruction 4807 has been created. Adjust the CFG accordingly. */ 4808 if (returnjump_p (i3) || any_uncondjump_p (i3)) 4809 { 4810 *new_direct_jump_p = 1; 4811 mark_jump_label (PATTERN (i3), i3, 0); 4812 update_cfg_for_uncondjump (i3); 4813 } 4814 4815 if (undobuf.other_insn != NULL_RTX 4816 && (returnjump_p (undobuf.other_insn) 4817 || any_uncondjump_p (undobuf.other_insn))) 4818 { 4819 *new_direct_jump_p = 1; 4820 update_cfg_for_uncondjump (undobuf.other_insn); 4821 } 4822 4823 if (GET_CODE (PATTERN (i3)) == TRAP_IF 4824 && XEXP (PATTERN (i3), 0) == const1_rtx) 4825 { 4826 basic_block bb = BLOCK_FOR_INSN (i3); 4827 gcc_assert (bb); 4828 remove_edge (split_block (bb, i3)); 4829 emit_barrier_after_bb (bb); 4830 *new_direct_jump_p = 1; 4831 } 4832 4833 if (undobuf.other_insn 4834 && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF 4835 && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx) 4836 { 4837 basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn); 4838 gcc_assert (bb); 4839 remove_edge (split_block (bb, undobuf.other_insn)); 4840 emit_barrier_after_bb (bb); 4841 *new_direct_jump_p = 1; 4842 } 4843 4844 /* A noop might also need cleaning up of CFG, if it comes from the 4845 simplification of a jump. */ 4846 if (JUMP_P (i3) 4847 && GET_CODE (newpat) == SET 4848 && SET_SRC (newpat) == pc_rtx 4849 && SET_DEST (newpat) == pc_rtx) 4850 { 4851 *new_direct_jump_p = 1; 4852 update_cfg_for_uncondjump (i3); 4853 } 4854 4855 if (undobuf.other_insn != NULL_RTX 4856 && JUMP_P (undobuf.other_insn) 4857 && GET_CODE (PATTERN (undobuf.other_insn)) == SET 4858 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx 4859 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx) 4860 { 4861 *new_direct_jump_p = 1; 4862 update_cfg_for_uncondjump (undobuf.other_insn); 4863 } 4864 4865 combine_successes++; 4866 undo_commit (); 4867 4868 rtx_insn *ret = newi2pat ? i2 : i3; 4869 if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret)) 4870 ret = added_links_insn; 4871 if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret)) 4872 ret = added_notes_insn; 4873 4874 return ret; 4875 } 4876 4877 /* Get a marker for undoing to the current state. */ 4878 4879 static void * 4880 get_undo_marker (void) 4881 { 4882 return undobuf.undos; 4883 } 4884 4885 /* Undo the modifications up to the marker. */ 4886 4887 static void 4888 undo_to_marker (void *marker) 4889 { 4890 struct undo *undo, *next; 4891 4892 for (undo = undobuf.undos; undo != marker; undo = next) 4893 { 4894 gcc_assert (undo); 4895 4896 next = undo->next; 4897 switch (undo->kind) 4898 { 4899 case UNDO_RTX: 4900 *undo->where.r = undo->old_contents.r; 4901 break; 4902 case UNDO_INT: 4903 *undo->where.i = undo->old_contents.i; 4904 break; 4905 case UNDO_MODE: 4906 adjust_reg_mode (regno_reg_rtx[undo->where.regno], 4907 undo->old_contents.m); 4908 break; 4909 case UNDO_LINKS: 4910 *undo->where.l = undo->old_contents.l; 4911 break; 4912 default: 4913 gcc_unreachable (); 4914 } 4915 4916 undo->next = undobuf.frees; 4917 undobuf.frees = undo; 4918 } 4919 4920 undobuf.undos = (struct undo *) marker; 4921 } 4922 4923 /* Undo all the modifications recorded in undobuf. */ 4924 4925 static void 4926 undo_all (void) 4927 { 4928 undo_to_marker (0); 4929 } 4930 4931 /* We've committed to accepting the changes we made. Move all 4932 of the undos to the free list. */ 4933 4934 static void 4935 undo_commit (void) 4936 { 4937 struct undo *undo, *next; 4938 4939 for (undo = undobuf.undos; undo; undo = next) 4940 { 4941 next = undo->next; 4942 undo->next = undobuf.frees; 4943 undobuf.frees = undo; 4944 } 4945 undobuf.undos = 0; 4946 } 4947 4948 /* Find the innermost point within the rtx at LOC, possibly LOC itself, 4949 where we have an arithmetic expression and return that point. LOC will 4950 be inside INSN. 4951 4952 try_combine will call this function to see if an insn can be split into 4953 two insns. */ 4954 4955 static rtx * 4956 find_split_point (rtx *loc, rtx_insn *insn, bool set_src) 4957 { 4958 rtx x = *loc; 4959 enum rtx_code code = GET_CODE (x); 4960 rtx *split; 4961 unsigned HOST_WIDE_INT len = 0; 4962 HOST_WIDE_INT pos = 0; 4963 int unsignedp = 0; 4964 rtx inner = NULL_RTX; 4965 scalar_int_mode mode, inner_mode; 4966 4967 /* First special-case some codes. */ 4968 switch (code) 4969 { 4970 case SUBREG: 4971 #ifdef INSN_SCHEDULING 4972 /* If we are making a paradoxical SUBREG invalid, it becomes a split 4973 point. */ 4974 if (MEM_P (SUBREG_REG (x))) 4975 return loc; 4976 #endif 4977 return find_split_point (&SUBREG_REG (x), insn, false); 4978 4979 case MEM: 4980 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 4981 using LO_SUM and HIGH. */ 4982 if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST 4983 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)) 4984 { 4985 machine_mode address_mode = get_address_mode (x); 4986 4987 SUBST (XEXP (x, 0), 4988 gen_rtx_LO_SUM (address_mode, 4989 gen_rtx_HIGH (address_mode, XEXP (x, 0)), 4990 XEXP (x, 0))); 4991 return &XEXP (XEXP (x, 0), 0); 4992 } 4993 4994 /* If we have a PLUS whose second operand is a constant and the 4995 address is not valid, perhaps we can split it up using 4996 the machine-specific way to split large constants. We use 4997 the first pseudo-reg (one of the virtual regs) as a placeholder; 4998 it will not remain in the result. */ 4999 if (GET_CODE (XEXP (x, 0)) == PLUS 5000 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 5001 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), 5002 MEM_ADDR_SPACE (x))) 5003 { 5004 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; 5005 rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)), 5006 subst_insn); 5007 5008 /* This should have produced two insns, each of which sets our 5009 placeholder. If the source of the second is a valid address, 5010 we can put both sources together and make a split point 5011 in the middle. */ 5012 5013 if (seq 5014 && NEXT_INSN (seq) != NULL_RTX 5015 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX 5016 && NONJUMP_INSN_P (seq) 5017 && GET_CODE (PATTERN (seq)) == SET 5018 && SET_DEST (PATTERN (seq)) == reg 5019 && ! reg_mentioned_p (reg, 5020 SET_SRC (PATTERN (seq))) 5021 && NONJUMP_INSN_P (NEXT_INSN (seq)) 5022 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET 5023 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg 5024 && memory_address_addr_space_p 5025 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))), 5026 MEM_ADDR_SPACE (x))) 5027 { 5028 rtx src1 = SET_SRC (PATTERN (seq)); 5029 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq))); 5030 5031 /* Replace the placeholder in SRC2 with SRC1. If we can 5032 find where in SRC2 it was placed, that can become our 5033 split point and we can replace this address with SRC2. 5034 Just try two obvious places. */ 5035 5036 src2 = replace_rtx (src2, reg, src1); 5037 split = 0; 5038 if (XEXP (src2, 0) == src1) 5039 split = &XEXP (src2, 0); 5040 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' 5041 && XEXP (XEXP (src2, 0), 0) == src1) 5042 split = &XEXP (XEXP (src2, 0), 0); 5043 5044 if (split) 5045 { 5046 SUBST (XEXP (x, 0), src2); 5047 return split; 5048 } 5049 } 5050 5051 /* If that didn't work and we have a nested plus, like: 5052 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2 5053 is valid address, try to split (REG1 * CONST1). */ 5054 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS 5055 && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0)) 5056 && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1)) 5057 && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG 5058 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0), 5059 0), 0))))) 5060 { 5061 rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0); 5062 XEXP (XEXP (XEXP (x, 0), 0), 0) = reg; 5063 if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), 5064 MEM_ADDR_SPACE (x))) 5065 { 5066 XEXP (XEXP (XEXP (x, 0), 0), 0) = tem; 5067 return &XEXP (XEXP (XEXP (x, 0), 0), 0); 5068 } 5069 XEXP (XEXP (XEXP (x, 0), 0), 0) = tem; 5070 } 5071 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS 5072 && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0)) 5073 && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1)) 5074 && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG 5075 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0), 5076 0), 1))))) 5077 { 5078 rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1); 5079 XEXP (XEXP (XEXP (x, 0), 0), 1) = reg; 5080 if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), 5081 MEM_ADDR_SPACE (x))) 5082 { 5083 XEXP (XEXP (XEXP (x, 0), 0), 1) = tem; 5084 return &XEXP (XEXP (XEXP (x, 0), 0), 1); 5085 } 5086 XEXP (XEXP (XEXP (x, 0), 0), 1) = tem; 5087 } 5088 5089 /* If that didn't work, perhaps the first operand is complex and 5090 needs to be computed separately, so make a split point there. 5091 This will occur on machines that just support REG + CONST 5092 and have a constant moved through some previous computation. */ 5093 if (!OBJECT_P (XEXP (XEXP (x, 0), 0)) 5094 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 5095 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) 5096 return &XEXP (XEXP (x, 0), 0); 5097 } 5098 5099 /* If we have a PLUS whose first operand is complex, try computing it 5100 separately by making a split there. */ 5101 if (GET_CODE (XEXP (x, 0)) == PLUS 5102 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), 5103 MEM_ADDR_SPACE (x)) 5104 && ! OBJECT_P (XEXP (XEXP (x, 0), 0)) 5105 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 5106 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) 5107 return &XEXP (XEXP (x, 0), 0); 5108 break; 5109 5110 case SET: 5111 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a 5112 ZERO_EXTRACT, the most likely reason why this doesn't match is that 5113 we need to put the operand into a register. So split at that 5114 point. */ 5115 5116 if (SET_DEST (x) == cc0_rtx 5117 && GET_CODE (SET_SRC (x)) != COMPARE 5118 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT 5119 && !OBJECT_P (SET_SRC (x)) 5120 && ! (GET_CODE (SET_SRC (x)) == SUBREG 5121 && OBJECT_P (SUBREG_REG (SET_SRC (x))))) 5122 return &SET_SRC (x); 5123 5124 /* See if we can split SET_SRC as it stands. */ 5125 split = find_split_point (&SET_SRC (x), insn, true); 5126 if (split && split != &SET_SRC (x)) 5127 return split; 5128 5129 /* See if we can split SET_DEST as it stands. */ 5130 split = find_split_point (&SET_DEST (x), insn, false); 5131 if (split && split != &SET_DEST (x)) 5132 return split; 5133 5134 /* See if this is a bitfield assignment with everything constant. If 5135 so, this is an IOR of an AND, so split it into that. */ 5136 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 5137 && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)), 5138 &inner_mode) 5139 && HWI_COMPUTABLE_MODE_P (inner_mode) 5140 && CONST_INT_P (XEXP (SET_DEST (x), 1)) 5141 && CONST_INT_P (XEXP (SET_DEST (x), 2)) 5142 && CONST_INT_P (SET_SRC (x)) 5143 && ((INTVAL (XEXP (SET_DEST (x), 1)) 5144 + INTVAL (XEXP (SET_DEST (x), 2))) 5145 <= GET_MODE_PRECISION (inner_mode)) 5146 && ! side_effects_p (XEXP (SET_DEST (x), 0))) 5147 { 5148 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); 5149 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); 5150 rtx dest = XEXP (SET_DEST (x), 0); 5151 unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << len) - 1; 5152 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)) & mask; 5153 rtx or_mask; 5154 5155 if (BITS_BIG_ENDIAN) 5156 pos = GET_MODE_PRECISION (inner_mode) - len - pos; 5157 5158 or_mask = gen_int_mode (src << pos, inner_mode); 5159 if (src == mask) 5160 SUBST (SET_SRC (x), 5161 simplify_gen_binary (IOR, inner_mode, dest, or_mask)); 5162 else 5163 { 5164 rtx negmask = gen_int_mode (~(mask << pos), inner_mode); 5165 SUBST (SET_SRC (x), 5166 simplify_gen_binary (IOR, inner_mode, 5167 simplify_gen_binary (AND, inner_mode, 5168 dest, negmask), 5169 or_mask)); 5170 } 5171 5172 SUBST (SET_DEST (x), dest); 5173 5174 split = find_split_point (&SET_SRC (x), insn, true); 5175 if (split && split != &SET_SRC (x)) 5176 return split; 5177 } 5178 5179 /* Otherwise, see if this is an operation that we can split into two. 5180 If so, try to split that. */ 5181 code = GET_CODE (SET_SRC (x)); 5182 5183 switch (code) 5184 { 5185 case AND: 5186 /* If we are AND'ing with a large constant that is only a single 5187 bit and the result is only being used in a context where we 5188 need to know if it is zero or nonzero, replace it with a bit 5189 extraction. This will avoid the large constant, which might 5190 have taken more than one insn to make. If the constant were 5191 not a valid argument to the AND but took only one insn to make, 5192 this is no worse, but if it took more than one insn, it will 5193 be better. */ 5194 5195 if (CONST_INT_P (XEXP (SET_SRC (x), 1)) 5196 && REG_P (XEXP (SET_SRC (x), 0)) 5197 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7 5198 && REG_P (SET_DEST (x)) 5199 && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0 5200 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) 5201 && XEXP (*split, 0) == SET_DEST (x) 5202 && XEXP (*split, 1) == const0_rtx) 5203 { 5204 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), 5205 XEXP (SET_SRC (x), 0), 5206 pos, NULL_RTX, 1, 1, 0, 0); 5207 if (extraction != 0) 5208 { 5209 SUBST (SET_SRC (x), extraction); 5210 return find_split_point (loc, insn, false); 5211 } 5212 } 5213 break; 5214 5215 case NE: 5216 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X 5217 is known to be on, this can be converted into a NEG of a shift. */ 5218 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx 5219 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) 5220 && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0), 5221 GET_MODE (XEXP (SET_SRC (x), 5222 0))))) >= 1)) 5223 { 5224 machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); 5225 rtx pos_rtx = gen_int_shift_amount (mode, pos); 5226 SUBST (SET_SRC (x), 5227 gen_rtx_NEG (mode, 5228 gen_rtx_LSHIFTRT (mode, 5229 XEXP (SET_SRC (x), 0), 5230 pos_rtx))); 5231 5232 split = find_split_point (&SET_SRC (x), insn, true); 5233 if (split && split != &SET_SRC (x)) 5234 return split; 5235 } 5236 break; 5237 5238 case SIGN_EXTEND: 5239 inner = XEXP (SET_SRC (x), 0); 5240 5241 /* We can't optimize if either mode is a partial integer 5242 mode as we don't know how many bits are significant 5243 in those modes. */ 5244 if (!is_int_mode (GET_MODE (inner), &inner_mode) 5245 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) 5246 break; 5247 5248 pos = 0; 5249 len = GET_MODE_PRECISION (inner_mode); 5250 unsignedp = 0; 5251 break; 5252 5253 case SIGN_EXTRACT: 5254 case ZERO_EXTRACT: 5255 if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)), 5256 &inner_mode) 5257 && CONST_INT_P (XEXP (SET_SRC (x), 1)) 5258 && CONST_INT_P (XEXP (SET_SRC (x), 2))) 5259 { 5260 inner = XEXP (SET_SRC (x), 0); 5261 len = INTVAL (XEXP (SET_SRC (x), 1)); 5262 pos = INTVAL (XEXP (SET_SRC (x), 2)); 5263 5264 if (BITS_BIG_ENDIAN) 5265 pos = GET_MODE_PRECISION (inner_mode) - len - pos; 5266 unsignedp = (code == ZERO_EXTRACT); 5267 } 5268 break; 5269 5270 default: 5271 break; 5272 } 5273 5274 if (len 5275 && known_subrange_p (pos, len, 5276 0, GET_MODE_PRECISION (GET_MODE (inner))) 5277 && is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode)) 5278 { 5279 /* For unsigned, we have a choice of a shift followed by an 5280 AND or two shifts. Use two shifts for field sizes where the 5281 constant might be too large. We assume here that we can 5282 always at least get 8-bit constants in an AND insn, which is 5283 true for every current RISC. */ 5284 5285 if (unsignedp && len <= 8) 5286 { 5287 unsigned HOST_WIDE_INT mask 5288 = (HOST_WIDE_INT_1U << len) - 1; 5289 rtx pos_rtx = gen_int_shift_amount (mode, pos); 5290 SUBST (SET_SRC (x), 5291 gen_rtx_AND (mode, 5292 gen_rtx_LSHIFTRT 5293 (mode, gen_lowpart (mode, inner), pos_rtx), 5294 gen_int_mode (mask, mode))); 5295 5296 split = find_split_point (&SET_SRC (x), insn, true); 5297 if (split && split != &SET_SRC (x)) 5298 return split; 5299 } 5300 else 5301 { 5302 int left_bits = GET_MODE_PRECISION (mode) - len - pos; 5303 int right_bits = GET_MODE_PRECISION (mode) - len; 5304 SUBST (SET_SRC (x), 5305 gen_rtx_fmt_ee 5306 (unsignedp ? LSHIFTRT : ASHIFTRT, mode, 5307 gen_rtx_ASHIFT (mode, 5308 gen_lowpart (mode, inner), 5309 gen_int_shift_amount (mode, left_bits)), 5310 gen_int_shift_amount (mode, right_bits))); 5311 5312 split = find_split_point (&SET_SRC (x), insn, true); 5313 if (split && split != &SET_SRC (x)) 5314 return split; 5315 } 5316 } 5317 5318 /* See if this is a simple operation with a constant as the second 5319 operand. It might be that this constant is out of range and hence 5320 could be used as a split point. */ 5321 if (BINARY_P (SET_SRC (x)) 5322 && CONSTANT_P (XEXP (SET_SRC (x), 1)) 5323 && (OBJECT_P (XEXP (SET_SRC (x), 0)) 5324 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG 5325 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0)))))) 5326 return &XEXP (SET_SRC (x), 1); 5327 5328 /* Finally, see if this is a simple operation with its first operand 5329 not in a register. The operation might require this operand in a 5330 register, so return it as a split point. We can always do this 5331 because if the first operand were another operation, we would have 5332 already found it as a split point. */ 5333 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x))) 5334 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) 5335 return &XEXP (SET_SRC (x), 0); 5336 5337 return 0; 5338 5339 case AND: 5340 case IOR: 5341 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, 5342 it is better to write this as (not (ior A B)) so we can split it. 5343 Similarly for IOR. */ 5344 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) 5345 { 5346 SUBST (*loc, 5347 gen_rtx_NOT (GET_MODE (x), 5348 gen_rtx_fmt_ee (code == IOR ? AND : IOR, 5349 GET_MODE (x), 5350 XEXP (XEXP (x, 0), 0), 5351 XEXP (XEXP (x, 1), 0)))); 5352 return find_split_point (loc, insn, set_src); 5353 } 5354 5355 /* Many RISC machines have a large set of logical insns. If the 5356 second operand is a NOT, put it first so we will try to split the 5357 other operand first. */ 5358 if (GET_CODE (XEXP (x, 1)) == NOT) 5359 { 5360 rtx tem = XEXP (x, 0); 5361 SUBST (XEXP (x, 0), XEXP (x, 1)); 5362 SUBST (XEXP (x, 1), tem); 5363 } 5364 break; 5365 5366 case PLUS: 5367 case MINUS: 5368 /* Canonicalization can produce (minus A (mult B C)), where C is a 5369 constant. It may be better to try splitting (plus (mult B -C) A) 5370 instead if this isn't a multiply by a power of two. */ 5371 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT 5372 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 5373 && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1)))) 5374 { 5375 machine_mode mode = GET_MODE (x); 5376 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1)); 5377 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode); 5378 SUBST (*loc, gen_rtx_PLUS (mode, 5379 gen_rtx_MULT (mode, 5380 XEXP (XEXP (x, 1), 0), 5381 gen_int_mode (other_int, 5382 mode)), 5383 XEXP (x, 0))); 5384 return find_split_point (loc, insn, set_src); 5385 } 5386 5387 /* Split at a multiply-accumulate instruction. However if this is 5388 the SET_SRC, we likely do not have such an instruction and it's 5389 worthless to try this split. */ 5390 if (!set_src 5391 && (GET_CODE (XEXP (x, 0)) == MULT 5392 || (GET_CODE (XEXP (x, 0)) == ASHIFT 5393 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) 5394 return loc; 5395 5396 default: 5397 break; 5398 } 5399 5400 /* Otherwise, select our actions depending on our rtx class. */ 5401 switch (GET_RTX_CLASS (code)) 5402 { 5403 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ 5404 case RTX_TERNARY: 5405 split = find_split_point (&XEXP (x, 2), insn, false); 5406 if (split) 5407 return split; 5408 /* fall through */ 5409 case RTX_BIN_ARITH: 5410 case RTX_COMM_ARITH: 5411 case RTX_COMPARE: 5412 case RTX_COMM_COMPARE: 5413 split = find_split_point (&XEXP (x, 1), insn, false); 5414 if (split) 5415 return split; 5416 /* fall through */ 5417 case RTX_UNARY: 5418 /* Some machines have (and (shift ...) ...) insns. If X is not 5419 an AND, but XEXP (X, 0) is, use it as our split point. */ 5420 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) 5421 return &XEXP (x, 0); 5422 5423 split = find_split_point (&XEXP (x, 0), insn, false); 5424 if (split) 5425 return split; 5426 return loc; 5427 5428 default: 5429 /* Otherwise, we don't have a split point. */ 5430 return 0; 5431 } 5432 } 5433 5434 /* Throughout X, replace FROM with TO, and return the result. 5435 The result is TO if X is FROM; 5436 otherwise the result is X, but its contents may have been modified. 5437 If they were modified, a record was made in undobuf so that 5438 undo_all will (among other things) return X to its original state. 5439 5440 If the number of changes necessary is too much to record to undo, 5441 the excess changes are not made, so the result is invalid. 5442 The changes already made can still be undone. 5443 undobuf.num_undo is incremented for such changes, so by testing that 5444 the caller can tell whether the result is valid. 5445 5446 `n_occurrences' is incremented each time FROM is replaced. 5447 5448 IN_DEST is nonzero if we are processing the SET_DEST of a SET. 5449 5450 IN_COND is nonzero if we are at the top level of a condition. 5451 5452 UNIQUE_COPY is nonzero if each substitution must be unique. We do this 5453 by copying if `n_occurrences' is nonzero. */ 5454 5455 static rtx 5456 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy) 5457 { 5458 enum rtx_code code = GET_CODE (x); 5459 machine_mode op0_mode = VOIDmode; 5460 const char *fmt; 5461 int len, i; 5462 rtx new_rtx; 5463 5464 /* Two expressions are equal if they are identical copies of a shared 5465 RTX or if they are both registers with the same register number 5466 and mode. */ 5467 5468 #define COMBINE_RTX_EQUAL_P(X,Y) \ 5469 ((X) == (Y) \ 5470 || (REG_P (X) && REG_P (Y) \ 5471 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) 5472 5473 /* Do not substitute into clobbers of regs -- this will never result in 5474 valid RTL. */ 5475 if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0))) 5476 return x; 5477 5478 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) 5479 { 5480 n_occurrences++; 5481 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); 5482 } 5483 5484 /* If X and FROM are the same register but different modes, they 5485 will not have been seen as equal above. However, the log links code 5486 will make a LOG_LINKS entry for that case. If we do nothing, we 5487 will try to rerecognize our original insn and, when it succeeds, 5488 we will delete the feeding insn, which is incorrect. 5489 5490 So force this insn not to match in this (rare) case. */ 5491 if (! in_dest && code == REG && REG_P (from) 5492 && reg_overlap_mentioned_p (x, from)) 5493 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 5494 5495 /* If this is an object, we are done unless it is a MEM or LO_SUM, both 5496 of which may contain things that can be combined. */ 5497 if (code != MEM && code != LO_SUM && OBJECT_P (x)) 5498 return x; 5499 5500 /* It is possible to have a subexpression appear twice in the insn. 5501 Suppose that FROM is a register that appears within TO. 5502 Then, after that subexpression has been scanned once by `subst', 5503 the second time it is scanned, TO may be found. If we were 5504 to scan TO here, we would find FROM within it and create a 5505 self-referent rtl structure which is completely wrong. */ 5506 if (COMBINE_RTX_EQUAL_P (x, to)) 5507 return to; 5508 5509 /* Parallel asm_operands need special attention because all of the 5510 inputs are shared across the arms. Furthermore, unsharing the 5511 rtl results in recognition failures. Failure to handle this case 5512 specially can result in circular rtl. 5513 5514 Solve this by doing a normal pass across the first entry of the 5515 parallel, and only processing the SET_DESTs of the subsequent 5516 entries. Ug. */ 5517 5518 if (code == PARALLEL 5519 && GET_CODE (XVECEXP (x, 0, 0)) == SET 5520 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) 5521 { 5522 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy); 5523 5524 /* If this substitution failed, this whole thing fails. */ 5525 if (GET_CODE (new_rtx) == CLOBBER 5526 && XEXP (new_rtx, 0) == const0_rtx) 5527 return new_rtx; 5528 5529 SUBST (XVECEXP (x, 0, 0), new_rtx); 5530 5531 for (i = XVECLEN (x, 0) - 1; i >= 1; i--) 5532 { 5533 rtx dest = SET_DEST (XVECEXP (x, 0, i)); 5534 5535 if (!REG_P (dest) 5536 && GET_CODE (dest) != CC0 5537 && GET_CODE (dest) != PC) 5538 { 5539 new_rtx = subst (dest, from, to, 0, 0, unique_copy); 5540 5541 /* If this substitution failed, this whole thing fails. */ 5542 if (GET_CODE (new_rtx) == CLOBBER 5543 && XEXP (new_rtx, 0) == const0_rtx) 5544 return new_rtx; 5545 5546 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx); 5547 } 5548 } 5549 } 5550 else 5551 { 5552 len = GET_RTX_LENGTH (code); 5553 fmt = GET_RTX_FORMAT (code); 5554 5555 /* We don't need to process a SET_DEST that is a register, CC0, 5556 or PC, so set up to skip this common case. All other cases 5557 where we want to suppress replacing something inside a 5558 SET_SRC are handled via the IN_DEST operand. */ 5559 if (code == SET 5560 && (REG_P (SET_DEST (x)) 5561 || GET_CODE (SET_DEST (x)) == CC0 5562 || GET_CODE (SET_DEST (x)) == PC)) 5563 fmt = "ie"; 5564 5565 /* Trying to simplify the operands of a widening MULT is not likely 5566 to create RTL matching a machine insn. */ 5567 if (code == MULT 5568 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 5569 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) 5570 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND 5571 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND) 5572 && REG_P (XEXP (XEXP (x, 0), 0)) 5573 && REG_P (XEXP (XEXP (x, 1), 0)) 5574 && from == to) 5575 return x; 5576 5577 5578 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a 5579 constant. */ 5580 if (fmt[0] == 'e') 5581 op0_mode = GET_MODE (XEXP (x, 0)); 5582 5583 for (i = 0; i < len; i++) 5584 { 5585 if (fmt[i] == 'E') 5586 { 5587 int j; 5588 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 5589 { 5590 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) 5591 { 5592 new_rtx = (unique_copy && n_occurrences 5593 ? copy_rtx (to) : to); 5594 n_occurrences++; 5595 } 5596 else 5597 { 5598 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0, 5599 unique_copy); 5600 5601 /* If this substitution failed, this whole thing 5602 fails. */ 5603 if (GET_CODE (new_rtx) == CLOBBER 5604 && XEXP (new_rtx, 0) == const0_rtx) 5605 return new_rtx; 5606 } 5607 5608 SUBST (XVECEXP (x, i, j), new_rtx); 5609 } 5610 } 5611 else if (fmt[i] == 'e') 5612 { 5613 /* If this is a register being set, ignore it. */ 5614 new_rtx = XEXP (x, i); 5615 if (in_dest 5616 && i == 0 5617 && (((code == SUBREG || code == ZERO_EXTRACT) 5618 && REG_P (new_rtx)) 5619 || code == STRICT_LOW_PART)) 5620 ; 5621 5622 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) 5623 { 5624 /* In general, don't install a subreg involving two 5625 modes not tieable. It can worsen register 5626 allocation, and can even make invalid reload 5627 insns, since the reg inside may need to be copied 5628 from in the outside mode, and that may be invalid 5629 if it is an fp reg copied in integer mode. 5630 5631 We allow two exceptions to this: It is valid if 5632 it is inside another SUBREG and the mode of that 5633 SUBREG and the mode of the inside of TO is 5634 tieable and it is valid if X is a SET that copies 5635 FROM to CC0. */ 5636 5637 if (GET_CODE (to) == SUBREG 5638 && !targetm.modes_tieable_p (GET_MODE (to), 5639 GET_MODE (SUBREG_REG (to))) 5640 && ! (code == SUBREG 5641 && (targetm.modes_tieable_p 5642 (GET_MODE (x), GET_MODE (SUBREG_REG (to))))) 5643 && (!HAVE_cc0 5644 || (! (code == SET 5645 && i == 1 5646 && XEXP (x, 0) == cc0_rtx)))) 5647 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 5648 5649 if (code == SUBREG 5650 && REG_P (to) 5651 && REGNO (to) < FIRST_PSEUDO_REGISTER 5652 && simplify_subreg_regno (REGNO (to), GET_MODE (to), 5653 SUBREG_BYTE (x), 5654 GET_MODE (x)) < 0) 5655 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 5656 5657 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to); 5658 n_occurrences++; 5659 } 5660 else 5661 /* If we are in a SET_DEST, suppress most cases unless we 5662 have gone inside a MEM, in which case we want to 5663 simplify the address. We assume here that things that 5664 are actually part of the destination have their inner 5665 parts in the first expression. This is true for SUBREG, 5666 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only 5667 things aside from REG and MEM that should appear in a 5668 SET_DEST. */ 5669 new_rtx = subst (XEXP (x, i), from, to, 5670 (((in_dest 5671 && (code == SUBREG || code == STRICT_LOW_PART 5672 || code == ZERO_EXTRACT)) 5673 || code == SET) 5674 && i == 0), 5675 code == IF_THEN_ELSE && i == 0, 5676 unique_copy); 5677 5678 /* If we found that we will have to reject this combination, 5679 indicate that by returning the CLOBBER ourselves, rather than 5680 an expression containing it. This will speed things up as 5681 well as prevent accidents where two CLOBBERs are considered 5682 to be equal, thus producing an incorrect simplification. */ 5683 5684 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx) 5685 return new_rtx; 5686 5687 if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx)) 5688 { 5689 machine_mode mode = GET_MODE (x); 5690 5691 x = simplify_subreg (GET_MODE (x), new_rtx, 5692 GET_MODE (SUBREG_REG (x)), 5693 SUBREG_BYTE (x)); 5694 if (! x) 5695 x = gen_rtx_CLOBBER (mode, const0_rtx); 5696 } 5697 else if (CONST_SCALAR_INT_P (new_rtx) 5698 && (GET_CODE (x) == ZERO_EXTEND 5699 || GET_CODE (x) == SIGN_EXTEND 5700 || GET_CODE (x) == FLOAT 5701 || GET_CODE (x) == UNSIGNED_FLOAT)) 5702 { 5703 x = simplify_unary_operation (GET_CODE (x), GET_MODE (x), 5704 new_rtx, 5705 GET_MODE (XEXP (x, 0))); 5706 if (!x) 5707 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 5708 } 5709 /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY 5710 etc. arguments, otherwise we can ICE before trying to recog 5711 it. See PR104446. */ 5712 else if (CONST_SCALAR_INT_P (new_rtx) 5713 && GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC) 5714 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 5715 else 5716 SUBST (XEXP (x, i), new_rtx); 5717 } 5718 } 5719 } 5720 5721 /* Check if we are loading something from the constant pool via float 5722 extension; in this case we would undo compress_float_constant 5723 optimization and degenerate constant load to an immediate value. */ 5724 if (GET_CODE (x) == FLOAT_EXTEND 5725 && MEM_P (XEXP (x, 0)) 5726 && MEM_READONLY_P (XEXP (x, 0))) 5727 { 5728 rtx tmp = avoid_constant_pool_reference (x); 5729 if (x != tmp) 5730 return x; 5731 } 5732 5733 /* Try to simplify X. If the simplification changed the code, it is likely 5734 that further simplification will help, so loop, but limit the number 5735 of repetitions that will be performed. */ 5736 5737 for (i = 0; i < 4; i++) 5738 { 5739 /* If X is sufficiently simple, don't bother trying to do anything 5740 with it. */ 5741 if (code != CONST_INT && code != REG && code != CLOBBER) 5742 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond); 5743 5744 if (GET_CODE (x) == code) 5745 break; 5746 5747 code = GET_CODE (x); 5748 5749 /* We no longer know the original mode of operand 0 since we 5750 have changed the form of X) */ 5751 op0_mode = VOIDmode; 5752 } 5753 5754 return x; 5755 } 5756 5757 /* If X is a commutative operation whose operands are not in the canonical 5758 order, use substitutions to swap them. */ 5759 5760 static void 5761 maybe_swap_commutative_operands (rtx x) 5762 { 5763 if (COMMUTATIVE_ARITH_P (x) 5764 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 5765 { 5766 rtx temp = XEXP (x, 0); 5767 SUBST (XEXP (x, 0), XEXP (x, 1)); 5768 SUBST (XEXP (x, 1), temp); 5769 } 5770 } 5771 5772 /* Simplify X, a piece of RTL. We just operate on the expression at the 5773 outer level; call `subst' to simplify recursively. Return the new 5774 expression. 5775 5776 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero 5777 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level 5778 of a condition. */ 5779 5780 static rtx 5781 combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest, 5782 int in_cond) 5783 { 5784 enum rtx_code code = GET_CODE (x); 5785 machine_mode mode = GET_MODE (x); 5786 scalar_int_mode int_mode; 5787 rtx temp; 5788 int i; 5789 5790 /* If this is a commutative operation, put a constant last and a complex 5791 expression first. We don't need to do this for comparisons here. */ 5792 maybe_swap_commutative_operands (x); 5793 5794 /* Try to fold this expression in case we have constants that weren't 5795 present before. */ 5796 temp = 0; 5797 switch (GET_RTX_CLASS (code)) 5798 { 5799 case RTX_UNARY: 5800 if (op0_mode == VOIDmode) 5801 op0_mode = GET_MODE (XEXP (x, 0)); 5802 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); 5803 break; 5804 case RTX_COMPARE: 5805 case RTX_COMM_COMPARE: 5806 { 5807 machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); 5808 if (cmp_mode == VOIDmode) 5809 { 5810 cmp_mode = GET_MODE (XEXP (x, 1)); 5811 if (cmp_mode == VOIDmode) 5812 cmp_mode = op0_mode; 5813 } 5814 temp = simplify_relational_operation (code, mode, cmp_mode, 5815 XEXP (x, 0), XEXP (x, 1)); 5816 } 5817 break; 5818 case RTX_COMM_ARITH: 5819 case RTX_BIN_ARITH: 5820 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); 5821 break; 5822 case RTX_BITFIELD_OPS: 5823 case RTX_TERNARY: 5824 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), 5825 XEXP (x, 1), XEXP (x, 2)); 5826 break; 5827 default: 5828 break; 5829 } 5830 5831 if (temp) 5832 { 5833 x = temp; 5834 code = GET_CODE (temp); 5835 op0_mode = VOIDmode; 5836 mode = GET_MODE (temp); 5837 } 5838 5839 /* If this is a simple operation applied to an IF_THEN_ELSE, try 5840 applying it to the arms of the IF_THEN_ELSE. This often simplifies 5841 things. Check for cases where both arms are testing the same 5842 condition. 5843 5844 Don't do anything if all operands are very simple. */ 5845 5846 if ((BINARY_P (x) 5847 && ((!OBJECT_P (XEXP (x, 0)) 5848 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 5849 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))) 5850 || (!OBJECT_P (XEXP (x, 1)) 5851 && ! (GET_CODE (XEXP (x, 1)) == SUBREG 5852 && OBJECT_P (SUBREG_REG (XEXP (x, 1))))))) 5853 || (UNARY_P (x) 5854 && (!OBJECT_P (XEXP (x, 0)) 5855 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 5856 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))))) 5857 { 5858 rtx cond, true_rtx, false_rtx; 5859 5860 cond = if_then_else_cond (x, &true_rtx, &false_rtx); 5861 if (cond != 0 5862 /* If everything is a comparison, what we have is highly unlikely 5863 to be simpler, so don't use it. */ 5864 && ! (COMPARISON_P (x) 5865 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))) 5866 /* Similarly, if we end up with one of the expressions the same 5867 as the original, it is certainly not simpler. */ 5868 && ! rtx_equal_p (x, true_rtx) 5869 && ! rtx_equal_p (x, false_rtx)) 5870 { 5871 rtx cop1 = const0_rtx; 5872 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); 5873 5874 if (cond_code == NE && COMPARISON_P (cond)) 5875 return x; 5876 5877 /* Simplify the alternative arms; this may collapse the true and 5878 false arms to store-flag values. Be careful to use copy_rtx 5879 here since true_rtx or false_rtx might share RTL with x as a 5880 result of the if_then_else_cond call above. */ 5881 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0); 5882 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0); 5883 5884 /* If true_rtx and false_rtx are not general_operands, an if_then_else 5885 is unlikely to be simpler. */ 5886 if (general_operand (true_rtx, VOIDmode) 5887 && general_operand (false_rtx, VOIDmode)) 5888 { 5889 enum rtx_code reversed; 5890 5891 /* Restarting if we generate a store-flag expression will cause 5892 us to loop. Just drop through in this case. */ 5893 5894 /* If the result values are STORE_FLAG_VALUE and zero, we can 5895 just make the comparison operation. */ 5896 if (true_rtx == const_true_rtx && false_rtx == const0_rtx) 5897 x = simplify_gen_relational (cond_code, mode, VOIDmode, 5898 cond, cop1); 5899 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx 5900 && ((reversed = reversed_comparison_code_parts 5901 (cond_code, cond, cop1, NULL)) 5902 != UNKNOWN)) 5903 x = simplify_gen_relational (reversed, mode, VOIDmode, 5904 cond, cop1); 5905 5906 /* Likewise, we can make the negate of a comparison operation 5907 if the result values are - STORE_FLAG_VALUE and zero. */ 5908 else if (CONST_INT_P (true_rtx) 5909 && INTVAL (true_rtx) == - STORE_FLAG_VALUE 5910 && false_rtx == const0_rtx) 5911 x = simplify_gen_unary (NEG, mode, 5912 simplify_gen_relational (cond_code, 5913 mode, VOIDmode, 5914 cond, cop1), 5915 mode); 5916 else if (CONST_INT_P (false_rtx) 5917 && INTVAL (false_rtx) == - STORE_FLAG_VALUE 5918 && true_rtx == const0_rtx 5919 && ((reversed = reversed_comparison_code_parts 5920 (cond_code, cond, cop1, NULL)) 5921 != UNKNOWN)) 5922 x = simplify_gen_unary (NEG, mode, 5923 simplify_gen_relational (reversed, 5924 mode, VOIDmode, 5925 cond, cop1), 5926 mode); 5927 5928 code = GET_CODE (x); 5929 op0_mode = VOIDmode; 5930 } 5931 } 5932 } 5933 5934 /* First see if we can apply the inverse distributive law. */ 5935 if (code == PLUS || code == MINUS 5936 || code == AND || code == IOR || code == XOR) 5937 { 5938 x = apply_distributive_law (x); 5939 code = GET_CODE (x); 5940 op0_mode = VOIDmode; 5941 } 5942 5943 /* If CODE is an associative operation not otherwise handled, see if we 5944 can associate some operands. This can win if they are constants or 5945 if they are logically related (i.e. (a & b) & a). */ 5946 if ((code == PLUS || code == MINUS || code == MULT || code == DIV 5947 || code == AND || code == IOR || code == XOR 5948 || code == SMAX || code == SMIN || code == UMAX || code == UMIN) 5949 && ((INTEGRAL_MODE_P (mode) && code != DIV) 5950 || (flag_associative_math && FLOAT_MODE_P (mode)))) 5951 { 5952 if (GET_CODE (XEXP (x, 0)) == code) 5953 { 5954 rtx other = XEXP (XEXP (x, 0), 0); 5955 rtx inner_op0 = XEXP (XEXP (x, 0), 1); 5956 rtx inner_op1 = XEXP (x, 1); 5957 rtx inner; 5958 5959 /* Make sure we pass the constant operand if any as the second 5960 one if this is a commutative operation. */ 5961 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x)) 5962 std::swap (inner_op0, inner_op1); 5963 inner = simplify_binary_operation (code == MINUS ? PLUS 5964 : code == DIV ? MULT 5965 : code, 5966 mode, inner_op0, inner_op1); 5967 5968 /* For commutative operations, try the other pair if that one 5969 didn't simplify. */ 5970 if (inner == 0 && COMMUTATIVE_ARITH_P (x)) 5971 { 5972 other = XEXP (XEXP (x, 0), 1); 5973 inner = simplify_binary_operation (code, mode, 5974 XEXP (XEXP (x, 0), 0), 5975 XEXP (x, 1)); 5976 } 5977 5978 if (inner) 5979 return simplify_gen_binary (code, mode, other, inner); 5980 } 5981 } 5982 5983 /* A little bit of algebraic simplification here. */ 5984 switch (code) 5985 { 5986 case MEM: 5987 /* Ensure that our address has any ASHIFTs converted to MULT in case 5988 address-recognizing predicates are called later. */ 5989 temp = make_compound_operation (XEXP (x, 0), MEM); 5990 SUBST (XEXP (x, 0), temp); 5991 break; 5992 5993 case SUBREG: 5994 if (op0_mode == VOIDmode) 5995 op0_mode = GET_MODE (SUBREG_REG (x)); 5996 5997 /* See if this can be moved to simplify_subreg. */ 5998 if (CONSTANT_P (SUBREG_REG (x)) 5999 && known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x)) 6000 /* Don't call gen_lowpart if the inner mode 6001 is VOIDmode and we cannot simplify it, as SUBREG without 6002 inner mode is invalid. */ 6003 && (GET_MODE (SUBREG_REG (x)) != VOIDmode 6004 || gen_lowpart_common (mode, SUBREG_REG (x)))) 6005 return gen_lowpart (mode, SUBREG_REG (x)); 6006 6007 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) 6008 break; 6009 { 6010 rtx temp; 6011 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, 6012 SUBREG_BYTE (x)); 6013 if (temp) 6014 return temp; 6015 6016 /* If op is known to have all lower bits zero, the result is zero. */ 6017 scalar_int_mode int_mode, int_op0_mode; 6018 if (!in_dest 6019 && is_a <scalar_int_mode> (mode, &int_mode) 6020 && is_a <scalar_int_mode> (op0_mode, &int_op0_mode) 6021 && (GET_MODE_PRECISION (int_mode) 6022 < GET_MODE_PRECISION (int_op0_mode)) 6023 && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode), 6024 SUBREG_BYTE (x)) 6025 && HWI_COMPUTABLE_MODE_P (int_op0_mode) 6026 && ((nonzero_bits (SUBREG_REG (x), int_op0_mode) 6027 & GET_MODE_MASK (int_mode)) == 0) 6028 && !side_effects_p (SUBREG_REG (x))) 6029 return CONST0_RTX (int_mode); 6030 } 6031 6032 /* Don't change the mode of the MEM if that would change the meaning 6033 of the address. */ 6034 if (MEM_P (SUBREG_REG (x)) 6035 && (MEM_VOLATILE_P (SUBREG_REG (x)) 6036 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0), 6037 MEM_ADDR_SPACE (SUBREG_REG (x))))) 6038 return gen_rtx_CLOBBER (mode, const0_rtx); 6039 6040 /* Note that we cannot do any narrowing for non-constants since 6041 we might have been counting on using the fact that some bits were 6042 zero. We now do this in the SET. */ 6043 6044 break; 6045 6046 case NEG: 6047 temp = expand_compound_operation (XEXP (x, 0)); 6048 6049 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be 6050 replaced by (lshiftrt X C). This will convert 6051 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ 6052 6053 if (GET_CODE (temp) == ASHIFTRT 6054 && CONST_INT_P (XEXP (temp, 1)) 6055 && INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1) 6056 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0), 6057 INTVAL (XEXP (temp, 1))); 6058 6059 /* If X has only a single bit that might be nonzero, say, bit I, convert 6060 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of 6061 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to 6062 (sign_extract X 1 Y). But only do this if TEMP isn't a register 6063 or a SUBREG of one since we'd be making the expression more 6064 complex if it was just a register. */ 6065 6066 if (!REG_P (temp) 6067 && ! (GET_CODE (temp) == SUBREG 6068 && REG_P (SUBREG_REG (temp))) 6069 && is_a <scalar_int_mode> (mode, &int_mode) 6070 && (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0) 6071 { 6072 rtx temp1 = simplify_shift_const 6073 (NULL_RTX, ASHIFTRT, int_mode, 6074 simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp, 6075 GET_MODE_PRECISION (int_mode) - 1 - i), 6076 GET_MODE_PRECISION (int_mode) - 1 - i); 6077 6078 /* If all we did was surround TEMP with the two shifts, we 6079 haven't improved anything, so don't use it. Otherwise, 6080 we are better off with TEMP1. */ 6081 if (GET_CODE (temp1) != ASHIFTRT 6082 || GET_CODE (XEXP (temp1, 0)) != ASHIFT 6083 || XEXP (XEXP (temp1, 0), 0) != temp) 6084 return temp1; 6085 } 6086 break; 6087 6088 case TRUNCATE: 6089 /* We can't handle truncation to a partial integer mode here 6090 because we don't know the real bitsize of the partial 6091 integer mode. */ 6092 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) 6093 break; 6094 6095 if (HWI_COMPUTABLE_MODE_P (mode)) 6096 SUBST (XEXP (x, 0), 6097 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), 6098 GET_MODE_MASK (mode), 0)); 6099 6100 /* We can truncate a constant value and return it. */ 6101 { 6102 poly_int64 c; 6103 if (poly_int_rtx_p (XEXP (x, 0), &c)) 6104 return gen_int_mode (c, mode); 6105 } 6106 6107 /* Similarly to what we do in simplify-rtx.c, a truncate of a register 6108 whose value is a comparison can be replaced with a subreg if 6109 STORE_FLAG_VALUE permits. */ 6110 if (HWI_COMPUTABLE_MODE_P (mode) 6111 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 6112 && (temp = get_last_value (XEXP (x, 0))) 6113 && COMPARISON_P (temp)) 6114 return gen_lowpart (mode, XEXP (x, 0)); 6115 break; 6116 6117 case CONST: 6118 /* (const (const X)) can become (const X). Do it this way rather than 6119 returning the inner CONST since CONST can be shared with a 6120 REG_EQUAL note. */ 6121 if (GET_CODE (XEXP (x, 0)) == CONST) 6122 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 6123 break; 6124 6125 case LO_SUM: 6126 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we 6127 can add in an offset. find_split_point will split this address up 6128 again if it doesn't match. */ 6129 if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH 6130 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) 6131 return XEXP (x, 1); 6132 break; 6133 6134 case PLUS: 6135 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) 6136 when c is (const_int (pow2 + 1) / 2) is a sign extension of a 6137 bit-field and can be replaced by either a sign_extend or a 6138 sign_extract. The `and' may be a zero_extend and the two 6139 <c>, -<c> constants may be reversed. */ 6140 if (GET_CODE (XEXP (x, 0)) == XOR 6141 && is_a <scalar_int_mode> (mode, &int_mode) 6142 && CONST_INT_P (XEXP (x, 1)) 6143 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 6144 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) 6145 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 6146 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0) 6147 && HWI_COMPUTABLE_MODE_P (int_mode) 6148 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND 6149 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1)) 6150 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) 6151 == (HOST_WIDE_INT_1U << (i + 1)) - 1)) 6152 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND 6153 && known_eq ((GET_MODE_PRECISION 6154 (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))), 6155 (unsigned int) i + 1)))) 6156 return simplify_shift_const 6157 (NULL_RTX, ASHIFTRT, int_mode, 6158 simplify_shift_const (NULL_RTX, ASHIFT, int_mode, 6159 XEXP (XEXP (XEXP (x, 0), 0), 0), 6160 GET_MODE_PRECISION (int_mode) - (i + 1)), 6161 GET_MODE_PRECISION (int_mode) - (i + 1)); 6162 6163 /* If only the low-order bit of X is possibly nonzero, (plus x -1) 6164 can become (ashiftrt (ashift (xor x 1) C) C) where C is 6165 the bitsize of the mode - 1. This allows simplification of 6166 "a = (b & 8) == 0;" */ 6167 if (XEXP (x, 1) == constm1_rtx 6168 && !REG_P (XEXP (x, 0)) 6169 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 6170 && REG_P (SUBREG_REG (XEXP (x, 0)))) 6171 && is_a <scalar_int_mode> (mode, &int_mode) 6172 && nonzero_bits (XEXP (x, 0), int_mode) == 1) 6173 return simplify_shift_const 6174 (NULL_RTX, ASHIFTRT, int_mode, 6175 simplify_shift_const (NULL_RTX, ASHIFT, int_mode, 6176 gen_rtx_XOR (int_mode, XEXP (x, 0), 6177 const1_rtx), 6178 GET_MODE_PRECISION (int_mode) - 1), 6179 GET_MODE_PRECISION (int_mode) - 1); 6180 6181 /* If we are adding two things that have no bits in common, convert 6182 the addition into an IOR. This will often be further simplified, 6183 for example in cases like ((a & 1) + (a & 2)), which can 6184 become a & 3. */ 6185 6186 if (HWI_COMPUTABLE_MODE_P (mode) 6187 && (nonzero_bits (XEXP (x, 0), mode) 6188 & nonzero_bits (XEXP (x, 1), mode)) == 0) 6189 { 6190 /* Try to simplify the expression further. */ 6191 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 6192 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0); 6193 6194 /* If we could, great. If not, do not go ahead with the IOR 6195 replacement, since PLUS appears in many special purpose 6196 address arithmetic instructions. */ 6197 if (GET_CODE (temp) != CLOBBER 6198 && (GET_CODE (temp) != IOR 6199 || ((XEXP (temp, 0) != XEXP (x, 0) 6200 || XEXP (temp, 1) != XEXP (x, 1)) 6201 && (XEXP (temp, 0) != XEXP (x, 1) 6202 || XEXP (temp, 1) != XEXP (x, 0))))) 6203 return temp; 6204 } 6205 6206 /* Canonicalize x + x into x << 1. */ 6207 if (GET_MODE_CLASS (mode) == MODE_INT 6208 && rtx_equal_p (XEXP (x, 0), XEXP (x, 1)) 6209 && !side_effects_p (XEXP (x, 0))) 6210 return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx); 6211 6212 break; 6213 6214 case MINUS: 6215 /* (minus <foo> (and <foo> (const_int -pow2))) becomes 6216 (and <foo> (const_int pow2-1)) */ 6217 if (is_a <scalar_int_mode> (mode, &int_mode) 6218 && GET_CODE (XEXP (x, 1)) == AND 6219 && CONST_INT_P (XEXP (XEXP (x, 1), 1)) 6220 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1))) 6221 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 6222 return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0), 6223 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); 6224 break; 6225 6226 case MULT: 6227 /* If we have (mult (plus A B) C), apply the distributive law and then 6228 the inverse distributive law to see if things simplify. This 6229 occurs mostly in addresses, often when unrolling loops. */ 6230 6231 if (GET_CODE (XEXP (x, 0)) == PLUS) 6232 { 6233 rtx result = distribute_and_simplify_rtx (x, 0); 6234 if (result) 6235 return result; 6236 } 6237 6238 /* Try simplify a*(b/c) as (a*b)/c. */ 6239 if (FLOAT_MODE_P (mode) && flag_associative_math 6240 && GET_CODE (XEXP (x, 0)) == DIV) 6241 { 6242 rtx tem = simplify_binary_operation (MULT, mode, 6243 XEXP (XEXP (x, 0), 0), 6244 XEXP (x, 1)); 6245 if (tem) 6246 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); 6247 } 6248 break; 6249 6250 case UDIV: 6251 /* If this is a divide by a power of two, treat it as a shift if 6252 its first operand is a shift. */ 6253 if (is_a <scalar_int_mode> (mode, &int_mode) 6254 && CONST_INT_P (XEXP (x, 1)) 6255 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0 6256 && (GET_CODE (XEXP (x, 0)) == ASHIFT 6257 || GET_CODE (XEXP (x, 0)) == LSHIFTRT 6258 || GET_CODE (XEXP (x, 0)) == ASHIFTRT 6259 || GET_CODE (XEXP (x, 0)) == ROTATE 6260 || GET_CODE (XEXP (x, 0)) == ROTATERT)) 6261 return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode, 6262 XEXP (x, 0), i); 6263 break; 6264 6265 case EQ: case NE: 6266 case GT: case GTU: case GE: case GEU: 6267 case LT: case LTU: case LE: case LEU: 6268 case UNEQ: case LTGT: 6269 case UNGT: case UNGE: 6270 case UNLT: case UNLE: 6271 case UNORDERED: case ORDERED: 6272 /* If the first operand is a condition code, we can't do anything 6273 with it. */ 6274 if (GET_CODE (XEXP (x, 0)) == COMPARE 6275 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC 6276 && ! CC0_P (XEXP (x, 0)))) 6277 { 6278 rtx op0 = XEXP (x, 0); 6279 rtx op1 = XEXP (x, 1); 6280 enum rtx_code new_code; 6281 6282 if (GET_CODE (op0) == COMPARE) 6283 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 6284 6285 /* Simplify our comparison, if possible. */ 6286 new_code = simplify_comparison (code, &op0, &op1); 6287 6288 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X 6289 if only the low-order bit is possibly nonzero in X (such as when 6290 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to 6291 (xor X 1) or (minus 1 X); we use the former. Finally, if X is 6292 known to be either 0 or -1, NE becomes a NEG and EQ becomes 6293 (plus X 1). 6294 6295 Remove any ZERO_EXTRACT we made when thinking this was a 6296 comparison. It may now be simpler to use, e.g., an AND. If a 6297 ZERO_EXTRACT is indeed appropriate, it will be placed back by 6298 the call to make_compound_operation in the SET case. 6299 6300 Don't apply these optimizations if the caller would 6301 prefer a comparison rather than a value. 6302 E.g., for the condition in an IF_THEN_ELSE most targets need 6303 an explicit comparison. */ 6304 6305 if (in_cond) 6306 ; 6307 6308 else if (STORE_FLAG_VALUE == 1 6309 && new_code == NE 6310 && is_int_mode (mode, &int_mode) 6311 && op1 == const0_rtx 6312 && int_mode == GET_MODE (op0) 6313 && nonzero_bits (op0, int_mode) == 1) 6314 return gen_lowpart (int_mode, 6315 expand_compound_operation (op0)); 6316 6317 else if (STORE_FLAG_VALUE == 1 6318 && new_code == NE 6319 && is_int_mode (mode, &int_mode) 6320 && op1 == const0_rtx 6321 && int_mode == GET_MODE (op0) 6322 && (num_sign_bit_copies (op0, int_mode) 6323 == GET_MODE_PRECISION (int_mode))) 6324 { 6325 op0 = expand_compound_operation (op0); 6326 return simplify_gen_unary (NEG, int_mode, 6327 gen_lowpart (int_mode, op0), 6328 int_mode); 6329 } 6330 6331 else if (STORE_FLAG_VALUE == 1 6332 && new_code == EQ 6333 && is_int_mode (mode, &int_mode) 6334 && op1 == const0_rtx 6335 && int_mode == GET_MODE (op0) 6336 && nonzero_bits (op0, int_mode) == 1) 6337 { 6338 op0 = expand_compound_operation (op0); 6339 return simplify_gen_binary (XOR, int_mode, 6340 gen_lowpart (int_mode, op0), 6341 const1_rtx); 6342 } 6343 6344 else if (STORE_FLAG_VALUE == 1 6345 && new_code == EQ 6346 && is_int_mode (mode, &int_mode) 6347 && op1 == const0_rtx 6348 && int_mode == GET_MODE (op0) 6349 && (num_sign_bit_copies (op0, int_mode) 6350 == GET_MODE_PRECISION (int_mode))) 6351 { 6352 op0 = expand_compound_operation (op0); 6353 return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1); 6354 } 6355 6356 /* If STORE_FLAG_VALUE is -1, we have cases similar to 6357 those above. */ 6358 if (in_cond) 6359 ; 6360 6361 else if (STORE_FLAG_VALUE == -1 6362 && new_code == NE 6363 && is_int_mode (mode, &int_mode) 6364 && op1 == const0_rtx 6365 && int_mode == GET_MODE (op0) 6366 && (num_sign_bit_copies (op0, int_mode) 6367 == GET_MODE_PRECISION (int_mode))) 6368 return gen_lowpart (int_mode, expand_compound_operation (op0)); 6369 6370 else if (STORE_FLAG_VALUE == -1 6371 && new_code == NE 6372 && is_int_mode (mode, &int_mode) 6373 && op1 == const0_rtx 6374 && int_mode == GET_MODE (op0) 6375 && nonzero_bits (op0, int_mode) == 1) 6376 { 6377 op0 = expand_compound_operation (op0); 6378 return simplify_gen_unary (NEG, int_mode, 6379 gen_lowpart (int_mode, op0), 6380 int_mode); 6381 } 6382 6383 else if (STORE_FLAG_VALUE == -1 6384 && new_code == EQ 6385 && is_int_mode (mode, &int_mode) 6386 && op1 == const0_rtx 6387 && int_mode == GET_MODE (op0) 6388 && (num_sign_bit_copies (op0, int_mode) 6389 == GET_MODE_PRECISION (int_mode))) 6390 { 6391 op0 = expand_compound_operation (op0); 6392 return simplify_gen_unary (NOT, int_mode, 6393 gen_lowpart (int_mode, op0), 6394 int_mode); 6395 } 6396 6397 /* If X is 0/1, (eq X 0) is X-1. */ 6398 else if (STORE_FLAG_VALUE == -1 6399 && new_code == EQ 6400 && is_int_mode (mode, &int_mode) 6401 && op1 == const0_rtx 6402 && int_mode == GET_MODE (op0) 6403 && nonzero_bits (op0, int_mode) == 1) 6404 { 6405 op0 = expand_compound_operation (op0); 6406 return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1); 6407 } 6408 6409 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just 6410 one bit that might be nonzero, we can convert (ne x 0) to 6411 (ashift x c) where C puts the bit in the sign bit. Remove any 6412 AND with STORE_FLAG_VALUE when we are done, since we are only 6413 going to test the sign bit. */ 6414 if (new_code == NE 6415 && is_int_mode (mode, &int_mode) 6416 && HWI_COMPUTABLE_MODE_P (int_mode) 6417 && val_signbit_p (int_mode, STORE_FLAG_VALUE) 6418 && op1 == const0_rtx 6419 && int_mode == GET_MODE (op0) 6420 && (i = exact_log2 (nonzero_bits (op0, int_mode))) >= 0) 6421 { 6422 x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode, 6423 expand_compound_operation (op0), 6424 GET_MODE_PRECISION (int_mode) - 1 - i); 6425 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) 6426 return XEXP (x, 0); 6427 else 6428 return x; 6429 } 6430 6431 /* If the code changed, return a whole new comparison. 6432 We also need to avoid using SUBST in cases where 6433 simplify_comparison has widened a comparison with a CONST_INT, 6434 since in that case the wider CONST_INT may fail the sanity 6435 checks in do_SUBST. */ 6436 if (new_code != code 6437 || (CONST_INT_P (op1) 6438 && GET_MODE (op0) != GET_MODE (XEXP (x, 0)) 6439 && GET_MODE (op0) != GET_MODE (XEXP (x, 1)))) 6440 return gen_rtx_fmt_ee (new_code, mode, op0, op1); 6441 6442 /* Otherwise, keep this operation, but maybe change its operands. 6443 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ 6444 SUBST (XEXP (x, 0), op0); 6445 SUBST (XEXP (x, 1), op1); 6446 } 6447 break; 6448 6449 case IF_THEN_ELSE: 6450 return simplify_if_then_else (x); 6451 6452 case ZERO_EXTRACT: 6453 case SIGN_EXTRACT: 6454 case ZERO_EXTEND: 6455 case SIGN_EXTEND: 6456 /* If we are processing SET_DEST, we are done. */ 6457 if (in_dest) 6458 return x; 6459 6460 return expand_compound_operation (x); 6461 6462 case SET: 6463 return simplify_set (x); 6464 6465 case AND: 6466 case IOR: 6467 return simplify_logical (x); 6468 6469 case ASHIFT: 6470 case LSHIFTRT: 6471 case ASHIFTRT: 6472 case ROTATE: 6473 case ROTATERT: 6474 /* If this is a shift by a constant amount, simplify it. */ 6475 if (CONST_INT_P (XEXP (x, 1))) 6476 return simplify_shift_const (x, code, mode, XEXP (x, 0), 6477 INTVAL (XEXP (x, 1))); 6478 6479 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1))) 6480 SUBST (XEXP (x, 1), 6481 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)), 6482 (HOST_WIDE_INT_1U 6483 << exact_log2 (GET_MODE_UNIT_BITSIZE 6484 (GET_MODE (x)))) 6485 - 1, 6486 0)); 6487 break; 6488 6489 default: 6490 break; 6491 } 6492 6493 return x; 6494 } 6495 6496 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ 6497 6498 static rtx 6499 simplify_if_then_else (rtx x) 6500 { 6501 machine_mode mode = GET_MODE (x); 6502 rtx cond = XEXP (x, 0); 6503 rtx true_rtx = XEXP (x, 1); 6504 rtx false_rtx = XEXP (x, 2); 6505 enum rtx_code true_code = GET_CODE (cond); 6506 int comparison_p = COMPARISON_P (cond); 6507 rtx temp; 6508 int i; 6509 enum rtx_code false_code; 6510 rtx reversed; 6511 scalar_int_mode int_mode, inner_mode; 6512 6513 /* Simplify storing of the truth value. */ 6514 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) 6515 return simplify_gen_relational (true_code, mode, VOIDmode, 6516 XEXP (cond, 0), XEXP (cond, 1)); 6517 6518 /* Also when the truth value has to be reversed. */ 6519 if (comparison_p 6520 && true_rtx == const0_rtx && false_rtx == const_true_rtx 6521 && (reversed = reversed_comparison (cond, mode))) 6522 return reversed; 6523 6524 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used 6525 in it is being compared against certain values. Get the true and false 6526 comparisons and see if that says anything about the value of each arm. */ 6527 6528 if (comparison_p 6529 && ((false_code = reversed_comparison_code (cond, NULL)) 6530 != UNKNOWN) 6531 && REG_P (XEXP (cond, 0))) 6532 { 6533 HOST_WIDE_INT nzb; 6534 rtx from = XEXP (cond, 0); 6535 rtx true_val = XEXP (cond, 1); 6536 rtx false_val = true_val; 6537 int swapped = 0; 6538 6539 /* If FALSE_CODE is EQ, swap the codes and arms. */ 6540 6541 if (false_code == EQ) 6542 { 6543 swapped = 1, true_code = EQ, false_code = NE; 6544 std::swap (true_rtx, false_rtx); 6545 } 6546 6547 scalar_int_mode from_mode; 6548 if (is_a <scalar_int_mode> (GET_MODE (from), &from_mode)) 6549 { 6550 /* If we are comparing against zero and the expression being 6551 tested has only a single bit that might be nonzero, that is 6552 its value when it is not equal to zero. Similarly if it is 6553 known to be -1 or 0. */ 6554 if (true_code == EQ 6555 && true_val == const0_rtx 6556 && pow2p_hwi (nzb = nonzero_bits (from, from_mode))) 6557 { 6558 false_code = EQ; 6559 false_val = gen_int_mode (nzb, from_mode); 6560 } 6561 else if (true_code == EQ 6562 && true_val == const0_rtx 6563 && (num_sign_bit_copies (from, from_mode) 6564 == GET_MODE_PRECISION (from_mode))) 6565 { 6566 false_code = EQ; 6567 false_val = constm1_rtx; 6568 } 6569 } 6570 6571 /* Now simplify an arm if we know the value of the register in the 6572 branch and it is used in the arm. Be careful due to the potential 6573 of locally-shared RTL. */ 6574 6575 if (reg_mentioned_p (from, true_rtx)) 6576 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, 6577 from, true_val), 6578 pc_rtx, pc_rtx, 0, 0, 0); 6579 if (reg_mentioned_p (from, false_rtx)) 6580 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, 6581 from, false_val), 6582 pc_rtx, pc_rtx, 0, 0, 0); 6583 6584 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); 6585 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); 6586 6587 true_rtx = XEXP (x, 1); 6588 false_rtx = XEXP (x, 2); 6589 true_code = GET_CODE (cond); 6590 } 6591 6592 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be 6593 reversed, do so to avoid needing two sets of patterns for 6594 subtract-and-branch insns. Similarly if we have a constant in the true 6595 arm, the false arm is the same as the first operand of the comparison, or 6596 the false arm is more complicated than the true arm. */ 6597 6598 if (comparison_p 6599 && reversed_comparison_code (cond, NULL) != UNKNOWN 6600 && (true_rtx == pc_rtx 6601 || (CONSTANT_P (true_rtx) 6602 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx) 6603 || true_rtx == const0_rtx 6604 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx)) 6605 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx)) 6606 && !OBJECT_P (false_rtx)) 6607 || reg_mentioned_p (true_rtx, false_rtx) 6608 || rtx_equal_p (false_rtx, XEXP (cond, 0)))) 6609 { 6610 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond))); 6611 SUBST (XEXP (x, 1), false_rtx); 6612 SUBST (XEXP (x, 2), true_rtx); 6613 6614 std::swap (true_rtx, false_rtx); 6615 cond = XEXP (x, 0); 6616 6617 /* It is possible that the conditional has been simplified out. */ 6618 true_code = GET_CODE (cond); 6619 comparison_p = COMPARISON_P (cond); 6620 } 6621 6622 /* If the two arms are identical, we don't need the comparison. */ 6623 6624 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) 6625 return true_rtx; 6626 6627 /* Convert a == b ? b : a to "a". */ 6628 if (true_code == EQ && ! side_effects_p (cond) 6629 && !HONOR_NANS (mode) 6630 && rtx_equal_p (XEXP (cond, 0), false_rtx) 6631 && rtx_equal_p (XEXP (cond, 1), true_rtx)) 6632 return false_rtx; 6633 else if (true_code == NE && ! side_effects_p (cond) 6634 && !HONOR_NANS (mode) 6635 && rtx_equal_p (XEXP (cond, 0), true_rtx) 6636 && rtx_equal_p (XEXP (cond, 1), false_rtx)) 6637 return true_rtx; 6638 6639 /* Look for cases where we have (abs x) or (neg (abs X)). */ 6640 6641 if (GET_MODE_CLASS (mode) == MODE_INT 6642 && comparison_p 6643 && XEXP (cond, 1) == const0_rtx 6644 && GET_CODE (false_rtx) == NEG 6645 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) 6646 && rtx_equal_p (true_rtx, XEXP (cond, 0)) 6647 && ! side_effects_p (true_rtx)) 6648 switch (true_code) 6649 { 6650 case GT: 6651 case GE: 6652 return simplify_gen_unary (ABS, mode, true_rtx, mode); 6653 case LT: 6654 case LE: 6655 return 6656 simplify_gen_unary (NEG, mode, 6657 simplify_gen_unary (ABS, mode, true_rtx, mode), 6658 mode); 6659 default: 6660 break; 6661 } 6662 6663 /* Look for MIN or MAX. */ 6664 6665 if ((! FLOAT_MODE_P (mode) 6666 || (flag_unsafe_math_optimizations 6667 && !HONOR_NANS (mode) 6668 && !HONOR_SIGNED_ZEROS (mode))) 6669 && comparison_p 6670 && rtx_equal_p (XEXP (cond, 0), true_rtx) 6671 && rtx_equal_p (XEXP (cond, 1), false_rtx) 6672 && ! side_effects_p (cond)) 6673 switch (true_code) 6674 { 6675 case GE: 6676 case GT: 6677 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx); 6678 case LE: 6679 case LT: 6680 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx); 6681 case GEU: 6682 case GTU: 6683 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx); 6684 case LEU: 6685 case LTU: 6686 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx); 6687 default: 6688 break; 6689 } 6690 6691 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its 6692 second operand is zero, this can be done as (OP Z (mult COND C2)) where 6693 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or 6694 SIGN_EXTEND as long as Z is already extended (so we don't destroy it). 6695 We can do this kind of thing in some cases when STORE_FLAG_VALUE is 6696 neither 1 or -1, but it isn't worth checking for. */ 6697 6698 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 6699 && comparison_p 6700 && is_int_mode (mode, &int_mode) 6701 && ! side_effects_p (x)) 6702 { 6703 rtx t = make_compound_operation (true_rtx, SET); 6704 rtx f = make_compound_operation (false_rtx, SET); 6705 rtx cond_op0 = XEXP (cond, 0); 6706 rtx cond_op1 = XEXP (cond, 1); 6707 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; 6708 scalar_int_mode m = int_mode; 6709 rtx z = 0, c1 = NULL_RTX; 6710 6711 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS 6712 || GET_CODE (t) == IOR || GET_CODE (t) == XOR 6713 || GET_CODE (t) == ASHIFT 6714 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) 6715 && rtx_equal_p (XEXP (t, 0), f)) 6716 c1 = XEXP (t, 1), op = GET_CODE (t), z = f; 6717 6718 /* If an identity-zero op is commutative, check whether there 6719 would be a match if we swapped the operands. */ 6720 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR 6721 || GET_CODE (t) == XOR) 6722 && rtx_equal_p (XEXP (t, 1), f)) 6723 c1 = XEXP (t, 0), op = GET_CODE (t), z = f; 6724 else if (GET_CODE (t) == SIGN_EXTEND 6725 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode) 6726 && (GET_CODE (XEXP (t, 0)) == PLUS 6727 || GET_CODE (XEXP (t, 0)) == MINUS 6728 || GET_CODE (XEXP (t, 0)) == IOR 6729 || GET_CODE (XEXP (t, 0)) == XOR 6730 || GET_CODE (XEXP (t, 0)) == ASHIFT 6731 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 6732 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 6733 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 6734 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 6735 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 6736 && (num_sign_bit_copies (f, GET_MODE (f)) 6737 > (unsigned int) 6738 (GET_MODE_PRECISION (int_mode) 6739 - GET_MODE_PRECISION (inner_mode)))) 6740 { 6741 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 6742 extend_op = SIGN_EXTEND; 6743 m = inner_mode; 6744 } 6745 else if (GET_CODE (t) == SIGN_EXTEND 6746 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode) 6747 && (GET_CODE (XEXP (t, 0)) == PLUS 6748 || GET_CODE (XEXP (t, 0)) == IOR 6749 || GET_CODE (XEXP (t, 0)) == XOR) 6750 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 6751 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 6752 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 6753 && (num_sign_bit_copies (f, GET_MODE (f)) 6754 > (unsigned int) 6755 (GET_MODE_PRECISION (int_mode) 6756 - GET_MODE_PRECISION (inner_mode)))) 6757 { 6758 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 6759 extend_op = SIGN_EXTEND; 6760 m = inner_mode; 6761 } 6762 else if (GET_CODE (t) == ZERO_EXTEND 6763 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode) 6764 && (GET_CODE (XEXP (t, 0)) == PLUS 6765 || GET_CODE (XEXP (t, 0)) == MINUS 6766 || GET_CODE (XEXP (t, 0)) == IOR 6767 || GET_CODE (XEXP (t, 0)) == XOR 6768 || GET_CODE (XEXP (t, 0)) == ASHIFT 6769 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 6770 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 6771 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 6772 && HWI_COMPUTABLE_MODE_P (int_mode) 6773 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 6774 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 6775 && ((nonzero_bits (f, GET_MODE (f)) 6776 & ~GET_MODE_MASK (inner_mode)) 6777 == 0)) 6778 { 6779 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 6780 extend_op = ZERO_EXTEND; 6781 m = inner_mode; 6782 } 6783 else if (GET_CODE (t) == ZERO_EXTEND 6784 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode) 6785 && (GET_CODE (XEXP (t, 0)) == PLUS 6786 || GET_CODE (XEXP (t, 0)) == IOR 6787 || GET_CODE (XEXP (t, 0)) == XOR) 6788 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 6789 && HWI_COMPUTABLE_MODE_P (int_mode) 6790 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 6791 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 6792 && ((nonzero_bits (f, GET_MODE (f)) 6793 & ~GET_MODE_MASK (inner_mode)) 6794 == 0)) 6795 { 6796 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 6797 extend_op = ZERO_EXTEND; 6798 m = inner_mode; 6799 } 6800 6801 if (z) 6802 { 6803 machine_mode cm = m; 6804 if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT) 6805 && GET_MODE (c1) != VOIDmode) 6806 cm = GET_MODE (c1); 6807 temp = subst (simplify_gen_relational (true_code, cm, VOIDmode, 6808 cond_op0, cond_op1), 6809 pc_rtx, pc_rtx, 0, 0, 0); 6810 temp = simplify_gen_binary (MULT, cm, temp, 6811 simplify_gen_binary (MULT, cm, c1, 6812 const_true_rtx)); 6813 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0); 6814 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); 6815 6816 if (extend_op != UNKNOWN) 6817 temp = simplify_gen_unary (extend_op, int_mode, temp, m); 6818 6819 return temp; 6820 } 6821 } 6822 6823 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or 6824 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the 6825 negation of a single bit, we can convert this operation to a shift. We 6826 can actually do this more generally, but it doesn't seem worth it. */ 6827 6828 if (true_code == NE 6829 && is_a <scalar_int_mode> (mode, &int_mode) 6830 && XEXP (cond, 1) == const0_rtx 6831 && false_rtx == const0_rtx 6832 && CONST_INT_P (true_rtx) 6833 && ((nonzero_bits (XEXP (cond, 0), int_mode) == 1 6834 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0) 6835 || ((num_sign_bit_copies (XEXP (cond, 0), int_mode) 6836 == GET_MODE_PRECISION (int_mode)) 6837 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0))) 6838 return 6839 simplify_shift_const (NULL_RTX, ASHIFT, int_mode, 6840 gen_lowpart (int_mode, XEXP (cond, 0)), i); 6841 6842 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only 6843 non-zero bit in A is C1. */ 6844 if (true_code == NE && XEXP (cond, 1) == const0_rtx 6845 && false_rtx == const0_rtx && CONST_INT_P (true_rtx) 6846 && is_a <scalar_int_mode> (mode, &int_mode) 6847 && is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), &inner_mode) 6848 && (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode)) 6849 == nonzero_bits (XEXP (cond, 0), inner_mode) 6850 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0) 6851 { 6852 rtx val = XEXP (cond, 0); 6853 if (inner_mode == int_mode) 6854 return val; 6855 else if (GET_MODE_PRECISION (inner_mode) < GET_MODE_PRECISION (int_mode)) 6856 return simplify_gen_unary (ZERO_EXTEND, int_mode, val, inner_mode); 6857 } 6858 6859 return x; 6860 } 6861 6862 /* Simplify X, a SET expression. Return the new expression. */ 6863 6864 static rtx 6865 simplify_set (rtx x) 6866 { 6867 rtx src = SET_SRC (x); 6868 rtx dest = SET_DEST (x); 6869 machine_mode mode 6870 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); 6871 rtx_insn *other_insn; 6872 rtx *cc_use; 6873 scalar_int_mode int_mode; 6874 6875 /* (set (pc) (return)) gets written as (return). */ 6876 if (GET_CODE (dest) == PC && ANY_RETURN_P (src)) 6877 return src; 6878 6879 /* Now that we know for sure which bits of SRC we are using, see if we can 6880 simplify the expression for the object knowing that we only need the 6881 low-order bits. */ 6882 6883 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode)) 6884 { 6885 src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, 0); 6886 SUBST (SET_SRC (x), src); 6887 } 6888 6889 /* If we are setting CC0 or if the source is a COMPARE, look for the use of 6890 the comparison result and try to simplify it unless we already have used 6891 undobuf.other_insn. */ 6892 if ((GET_MODE_CLASS (mode) == MODE_CC 6893 || GET_CODE (src) == COMPARE 6894 || CC0_P (dest)) 6895 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 6896 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) 6897 && COMPARISON_P (*cc_use) 6898 && rtx_equal_p (XEXP (*cc_use, 0), dest)) 6899 { 6900 enum rtx_code old_code = GET_CODE (*cc_use); 6901 enum rtx_code new_code; 6902 rtx op0, op1, tmp; 6903 int other_changed = 0; 6904 rtx inner_compare = NULL_RTX; 6905 machine_mode compare_mode = GET_MODE (dest); 6906 6907 if (GET_CODE (src) == COMPARE) 6908 { 6909 op0 = XEXP (src, 0), op1 = XEXP (src, 1); 6910 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) 6911 { 6912 inner_compare = op0; 6913 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1); 6914 } 6915 } 6916 else 6917 op0 = src, op1 = CONST0_RTX (GET_MODE (src)); 6918 6919 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode, 6920 op0, op1); 6921 if (!tmp) 6922 new_code = old_code; 6923 else if (!CONSTANT_P (tmp)) 6924 { 6925 new_code = GET_CODE (tmp); 6926 op0 = XEXP (tmp, 0); 6927 op1 = XEXP (tmp, 1); 6928 } 6929 else 6930 { 6931 rtx pat = PATTERN (other_insn); 6932 undobuf.other_insn = other_insn; 6933 SUBST (*cc_use, tmp); 6934 6935 /* Attempt to simplify CC user. */ 6936 if (GET_CODE (pat) == SET) 6937 { 6938 rtx new_rtx = simplify_rtx (SET_SRC (pat)); 6939 if (new_rtx != NULL_RTX) 6940 SUBST (SET_SRC (pat), new_rtx); 6941 } 6942 6943 /* Convert X into a no-op move. */ 6944 SUBST (SET_DEST (x), pc_rtx); 6945 SUBST (SET_SRC (x), pc_rtx); 6946 return x; 6947 } 6948 6949 /* Simplify our comparison, if possible. */ 6950 new_code = simplify_comparison (new_code, &op0, &op1); 6951 6952 #ifdef SELECT_CC_MODE 6953 /* If this machine has CC modes other than CCmode, check to see if we 6954 need to use a different CC mode here. */ 6955 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) 6956 compare_mode = GET_MODE (op0); 6957 else if (inner_compare 6958 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC 6959 && new_code == old_code 6960 && op0 == XEXP (inner_compare, 0) 6961 && op1 == XEXP (inner_compare, 1)) 6962 compare_mode = GET_MODE (inner_compare); 6963 else 6964 compare_mode = SELECT_CC_MODE (new_code, op0, op1); 6965 6966 /* If the mode changed, we have to change SET_DEST, the mode in the 6967 compare, and the mode in the place SET_DEST is used. If SET_DEST is 6968 a hard register, just build new versions with the proper mode. If it 6969 is a pseudo, we lose unless it is only time we set the pseudo, in 6970 which case we can safely change its mode. */ 6971 if (!HAVE_cc0 && compare_mode != GET_MODE (dest)) 6972 { 6973 if (can_change_dest_mode (dest, 0, compare_mode)) 6974 { 6975 unsigned int regno = REGNO (dest); 6976 rtx new_dest; 6977 6978 if (regno < FIRST_PSEUDO_REGISTER) 6979 new_dest = gen_rtx_REG (compare_mode, regno); 6980 else 6981 { 6982 subst_mode (regno, compare_mode); 6983 new_dest = regno_reg_rtx[regno]; 6984 } 6985 6986 SUBST (SET_DEST (x), new_dest); 6987 SUBST (XEXP (*cc_use, 0), new_dest); 6988 other_changed = 1; 6989 6990 dest = new_dest; 6991 } 6992 } 6993 #endif /* SELECT_CC_MODE */ 6994 6995 /* If the code changed, we have to build a new comparison in 6996 undobuf.other_insn. */ 6997 if (new_code != old_code) 6998 { 6999 int other_changed_previously = other_changed; 7000 unsigned HOST_WIDE_INT mask; 7001 rtx old_cc_use = *cc_use; 7002 7003 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), 7004 dest, const0_rtx)); 7005 other_changed = 1; 7006 7007 /* If the only change we made was to change an EQ into an NE or 7008 vice versa, OP0 has only one bit that might be nonzero, and OP1 7009 is zero, check if changing the user of the condition code will 7010 produce a valid insn. If it won't, we can keep the original code 7011 in that insn by surrounding our operation with an XOR. */ 7012 7013 if (((old_code == NE && new_code == EQ) 7014 || (old_code == EQ && new_code == NE)) 7015 && ! other_changed_previously && op1 == const0_rtx 7016 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0)) 7017 && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0)))) 7018 { 7019 rtx pat = PATTERN (other_insn), note = 0; 7020 7021 if ((recog_for_combine (&pat, other_insn, ¬e) < 0 7022 && ! check_asm_operands (pat))) 7023 { 7024 *cc_use = old_cc_use; 7025 other_changed = 0; 7026 7027 op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0, 7028 gen_int_mode (mask, 7029 GET_MODE (op0))); 7030 } 7031 } 7032 } 7033 7034 if (other_changed) 7035 undobuf.other_insn = other_insn; 7036 7037 /* Don't generate a compare of a CC with 0, just use that CC. */ 7038 if (GET_MODE (op0) == compare_mode && op1 == const0_rtx) 7039 { 7040 SUBST (SET_SRC (x), op0); 7041 src = SET_SRC (x); 7042 } 7043 /* Otherwise, if we didn't previously have the same COMPARE we 7044 want, create it from scratch. */ 7045 else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode 7046 || XEXP (src, 0) != op0 || XEXP (src, 1) != op1) 7047 { 7048 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); 7049 src = SET_SRC (x); 7050 } 7051 } 7052 else 7053 { 7054 /* Get SET_SRC in a form where we have placed back any 7055 compound expressions. Then do the checks below. */ 7056 src = make_compound_operation (src, SET); 7057 SUBST (SET_SRC (x), src); 7058 } 7059 7060 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, 7061 and X being a REG or (subreg (reg)), we may be able to convert this to 7062 (set (subreg:m2 x) (op)). 7063 7064 We can always do this if M1 is narrower than M2 because that means that 7065 we only care about the low bits of the result. 7066 7067 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot 7068 perform a narrower operation than requested since the high-order bits will 7069 be undefined. On machine where it is defined, this transformation is safe 7070 as long as M1 and M2 have the same number of words. */ 7071 7072 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 7073 && !OBJECT_P (SUBREG_REG (src)) 7074 && (known_equal_after_align_up 7075 (GET_MODE_SIZE (GET_MODE (src)), 7076 GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))), 7077 UNITS_PER_WORD)) 7078 && (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (src)) 7079 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER 7080 && !REG_CAN_CHANGE_MODE_P (REGNO (dest), 7081 GET_MODE (SUBREG_REG (src)), 7082 GET_MODE (src))) 7083 && (REG_P (dest) 7084 || (GET_CODE (dest) == SUBREG 7085 && REG_P (SUBREG_REG (dest))))) 7086 { 7087 SUBST (SET_DEST (x), 7088 gen_lowpart (GET_MODE (SUBREG_REG (src)), 7089 dest)); 7090 SUBST (SET_SRC (x), SUBREG_REG (src)); 7091 7092 src = SET_SRC (x), dest = SET_DEST (x); 7093 } 7094 7095 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg 7096 in SRC. */ 7097 if (dest == cc0_rtx 7098 && partial_subreg_p (src) 7099 && subreg_lowpart_p (src)) 7100 { 7101 rtx inner = SUBREG_REG (src); 7102 machine_mode inner_mode = GET_MODE (inner); 7103 7104 /* Here we make sure that we don't have a sign bit on. */ 7105 if (val_signbit_known_clear_p (GET_MODE (src), 7106 nonzero_bits (inner, inner_mode))) 7107 { 7108 SUBST (SET_SRC (x), inner); 7109 src = SET_SRC (x); 7110 } 7111 } 7112 7113 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this 7114 would require a paradoxical subreg. Replace the subreg with a 7115 zero_extend to avoid the reload that would otherwise be required. 7116 Don't do this unless we have a scalar integer mode, otherwise the 7117 transformation is incorrect. */ 7118 7119 enum rtx_code extend_op; 7120 if (paradoxical_subreg_p (src) 7121 && MEM_P (SUBREG_REG (src)) 7122 && SCALAR_INT_MODE_P (GET_MODE (src)) 7123 && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN) 7124 { 7125 SUBST (SET_SRC (x), 7126 gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src))); 7127 7128 src = SET_SRC (x); 7129 } 7130 7131 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we 7132 are comparing an item known to be 0 or -1 against 0, use a logical 7133 operation instead. Check for one of the arms being an IOR of the other 7134 arm with some value. We compute three terms to be IOR'ed together. In 7135 practice, at most two will be nonzero. Then we do the IOR's. */ 7136 7137 if (GET_CODE (dest) != PC 7138 && GET_CODE (src) == IF_THEN_ELSE 7139 && is_int_mode (GET_MODE (src), &int_mode) 7140 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) 7141 && XEXP (XEXP (src, 0), 1) == const0_rtx 7142 && int_mode == GET_MODE (XEXP (XEXP (src, 0), 0)) 7143 && (!HAVE_conditional_move 7144 || ! can_conditionally_move_p (int_mode)) 7145 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode) 7146 == GET_MODE_PRECISION (int_mode)) 7147 && ! side_effects_p (src)) 7148 { 7149 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE 7150 ? XEXP (src, 1) : XEXP (src, 2)); 7151 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE 7152 ? XEXP (src, 2) : XEXP (src, 1)); 7153 rtx term1 = const0_rtx, term2, term3; 7154 7155 if (GET_CODE (true_rtx) == IOR 7156 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) 7157 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx; 7158 else if (GET_CODE (true_rtx) == IOR 7159 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) 7160 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx; 7161 else if (GET_CODE (false_rtx) == IOR 7162 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) 7163 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx; 7164 else if (GET_CODE (false_rtx) == IOR 7165 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) 7166 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx; 7167 7168 term2 = simplify_gen_binary (AND, int_mode, 7169 XEXP (XEXP (src, 0), 0), true_rtx); 7170 term3 = simplify_gen_binary (AND, int_mode, 7171 simplify_gen_unary (NOT, int_mode, 7172 XEXP (XEXP (src, 0), 0), 7173 int_mode), 7174 false_rtx); 7175 7176 SUBST (SET_SRC (x), 7177 simplify_gen_binary (IOR, int_mode, 7178 simplify_gen_binary (IOR, int_mode, 7179 term1, term2), 7180 term3)); 7181 7182 src = SET_SRC (x); 7183 } 7184 7185 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this 7186 whole thing fail. */ 7187 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) 7188 return src; 7189 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) 7190 return dest; 7191 else 7192 /* Convert this into a field assignment operation, if possible. */ 7193 return make_field_assignment (x); 7194 } 7195 7196 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified 7197 result. */ 7198 7199 static rtx 7200 simplify_logical (rtx x) 7201 { 7202 rtx op0 = XEXP (x, 0); 7203 rtx op1 = XEXP (x, 1); 7204 scalar_int_mode mode; 7205 7206 switch (GET_CODE (x)) 7207 { 7208 case AND: 7209 /* We can call simplify_and_const_int only if we don't lose 7210 any (sign) bits when converting INTVAL (op1) to 7211 "unsigned HOST_WIDE_INT". */ 7212 if (is_a <scalar_int_mode> (GET_MODE (x), &mode) 7213 && CONST_INT_P (op1) 7214 && (HWI_COMPUTABLE_MODE_P (mode) 7215 || INTVAL (op1) > 0)) 7216 { 7217 x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); 7218 if (GET_CODE (x) != AND) 7219 return x; 7220 7221 op0 = XEXP (x, 0); 7222 op1 = XEXP (x, 1); 7223 } 7224 7225 /* If we have any of (and (ior A B) C) or (and (xor A B) C), 7226 apply the distributive law and then the inverse distributive 7227 law to see if things simplify. */ 7228 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) 7229 { 7230 rtx result = distribute_and_simplify_rtx (x, 0); 7231 if (result) 7232 return result; 7233 } 7234 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) 7235 { 7236 rtx result = distribute_and_simplify_rtx (x, 1); 7237 if (result) 7238 return result; 7239 } 7240 break; 7241 7242 case IOR: 7243 /* If we have (ior (and A B) C), apply the distributive law and then 7244 the inverse distributive law to see if things simplify. */ 7245 7246 if (GET_CODE (op0) == AND) 7247 { 7248 rtx result = distribute_and_simplify_rtx (x, 0); 7249 if (result) 7250 return result; 7251 } 7252 7253 if (GET_CODE (op1) == AND) 7254 { 7255 rtx result = distribute_and_simplify_rtx (x, 1); 7256 if (result) 7257 return result; 7258 } 7259 break; 7260 7261 default: 7262 gcc_unreachable (); 7263 } 7264 7265 return x; 7266 } 7267 7268 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound 7269 operations" because they can be replaced with two more basic operations. 7270 ZERO_EXTEND is also considered "compound" because it can be replaced with 7271 an AND operation, which is simpler, though only one operation. 7272 7273 The function expand_compound_operation is called with an rtx expression 7274 and will convert it to the appropriate shifts and AND operations, 7275 simplifying at each stage. 7276 7277 The function make_compound_operation is called to convert an expression 7278 consisting of shifts and ANDs into the equivalent compound expression. 7279 It is the inverse of this function, loosely speaking. */ 7280 7281 static rtx 7282 expand_compound_operation (rtx x) 7283 { 7284 unsigned HOST_WIDE_INT pos = 0, len; 7285 int unsignedp = 0; 7286 unsigned int modewidth; 7287 rtx tem; 7288 scalar_int_mode inner_mode; 7289 7290 switch (GET_CODE (x)) 7291 { 7292 case ZERO_EXTEND: 7293 unsignedp = 1; 7294 /* FALLTHRU */ 7295 case SIGN_EXTEND: 7296 /* We can't necessarily use a const_int for a multiword mode; 7297 it depends on implicitly extending the value. 7298 Since we don't know the right way to extend it, 7299 we can't tell whether the implicit way is right. 7300 7301 Even for a mode that is no wider than a const_int, 7302 we can't win, because we need to sign extend one of its bits through 7303 the rest of it, and we don't know which bit. */ 7304 if (CONST_INT_P (XEXP (x, 0))) 7305 return x; 7306 7307 /* Reject modes that aren't scalar integers because turning vector 7308 or complex modes into shifts causes problems. */ 7309 if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode)) 7310 return x; 7311 7312 /* Return if (subreg:MODE FROM 0) is not a safe replacement for 7313 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM 7314 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be 7315 reloaded. If not for that, MEM's would very rarely be safe. 7316 7317 Reject modes bigger than a word, because we might not be able 7318 to reference a two-register group starting with an arbitrary register 7319 (and currently gen_lowpart might crash for a SUBREG). */ 7320 7321 if (GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) 7322 return x; 7323 7324 len = GET_MODE_PRECISION (inner_mode); 7325 /* If the inner object has VOIDmode (the only way this can happen 7326 is if it is an ASM_OPERANDS), we can't do anything since we don't 7327 know how much masking to do. */ 7328 if (len == 0) 7329 return x; 7330 7331 break; 7332 7333 case ZERO_EXTRACT: 7334 unsignedp = 1; 7335 7336 /* fall through */ 7337 7338 case SIGN_EXTRACT: 7339 /* If the operand is a CLOBBER, just return it. */ 7340 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 7341 return XEXP (x, 0); 7342 7343 if (!CONST_INT_P (XEXP (x, 1)) 7344 || !CONST_INT_P (XEXP (x, 2))) 7345 return x; 7346 7347 /* Reject modes that aren't scalar integers because turning vector 7348 or complex modes into shifts causes problems. */ 7349 if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode)) 7350 return x; 7351 7352 len = INTVAL (XEXP (x, 1)); 7353 pos = INTVAL (XEXP (x, 2)); 7354 7355 /* This should stay within the object being extracted, fail otherwise. */ 7356 if (len + pos > GET_MODE_PRECISION (inner_mode)) 7357 return x; 7358 7359 if (BITS_BIG_ENDIAN) 7360 pos = GET_MODE_PRECISION (inner_mode) - len - pos; 7361 7362 break; 7363 7364 default: 7365 return x; 7366 } 7367 7368 /* We've rejected non-scalar operations by now. */ 7369 scalar_int_mode mode = as_a <scalar_int_mode> (GET_MODE (x)); 7370 7371 /* Convert sign extension to zero extension, if we know that the high 7372 bit is not set, as this is easier to optimize. It will be converted 7373 back to cheaper alternative in make_extraction. */ 7374 if (GET_CODE (x) == SIGN_EXTEND 7375 && HWI_COMPUTABLE_MODE_P (mode) 7376 && ((nonzero_bits (XEXP (x, 0), inner_mode) 7377 & ~(((unsigned HOST_WIDE_INT) GET_MODE_MASK (inner_mode)) >> 1)) 7378 == 0)) 7379 { 7380 rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0)); 7381 rtx temp2 = expand_compound_operation (temp); 7382 7383 /* Make sure this is a profitable operation. */ 7384 if (set_src_cost (x, mode, optimize_this_for_speed_p) 7385 > set_src_cost (temp2, mode, optimize_this_for_speed_p)) 7386 return temp2; 7387 else if (set_src_cost (x, mode, optimize_this_for_speed_p) 7388 > set_src_cost (temp, mode, optimize_this_for_speed_p)) 7389 return temp; 7390 else 7391 return x; 7392 } 7393 7394 /* We can optimize some special cases of ZERO_EXTEND. */ 7395 if (GET_CODE (x) == ZERO_EXTEND) 7396 { 7397 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we 7398 know that the last value didn't have any inappropriate bits 7399 set. */ 7400 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 7401 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode 7402 && HWI_COMPUTABLE_MODE_P (mode) 7403 && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) 7404 & ~GET_MODE_MASK (inner_mode)) == 0) 7405 return XEXP (XEXP (x, 0), 0); 7406 7407 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 7408 if (GET_CODE (XEXP (x, 0)) == SUBREG 7409 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode 7410 && subreg_lowpart_p (XEXP (x, 0)) 7411 && HWI_COMPUTABLE_MODE_P (mode) 7412 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), mode) 7413 & ~GET_MODE_MASK (inner_mode)) == 0) 7414 return SUBREG_REG (XEXP (x, 0)); 7415 7416 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo 7417 is a comparison and STORE_FLAG_VALUE permits. This is like 7418 the first case, but it works even when MODE is larger 7419 than HOST_WIDE_INT. */ 7420 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 7421 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode 7422 && COMPARISON_P (XEXP (XEXP (x, 0), 0)) 7423 && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT 7424 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0) 7425 return XEXP (XEXP (x, 0), 0); 7426 7427 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 7428 if (GET_CODE (XEXP (x, 0)) == SUBREG 7429 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode 7430 && subreg_lowpart_p (XEXP (x, 0)) 7431 && COMPARISON_P (SUBREG_REG (XEXP (x, 0))) 7432 && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT 7433 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0) 7434 return SUBREG_REG (XEXP (x, 0)); 7435 7436 } 7437 7438 /* If we reach here, we want to return a pair of shifts. The inner 7439 shift is a left shift of BITSIZE - POS - LEN bits. The outer 7440 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or 7441 logical depending on the value of UNSIGNEDP. 7442 7443 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be 7444 converted into an AND of a shift. 7445 7446 We must check for the case where the left shift would have a negative 7447 count. This can happen in a case like (x >> 31) & 255 on machines 7448 that can't shift by a constant. On those machines, we would first 7449 combine the shift with the AND to produce a variable-position 7450 extraction. Then the constant of 31 would be substituted in 7451 to produce such a position. */ 7452 7453 modewidth = GET_MODE_PRECISION (mode); 7454 if (modewidth >= pos + len) 7455 { 7456 tem = gen_lowpart (mode, XEXP (x, 0)); 7457 if (!tem || GET_CODE (tem) == CLOBBER) 7458 return x; 7459 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode, 7460 tem, modewidth - pos - len); 7461 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, 7462 mode, tem, modewidth - len); 7463 } 7464 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) 7465 { 7466 tem = simplify_shift_const (NULL_RTX, LSHIFTRT, inner_mode, 7467 XEXP (x, 0), pos); 7468 tem = gen_lowpart (mode, tem); 7469 if (!tem || GET_CODE (tem) == CLOBBER) 7470 return x; 7471 tem = simplify_and_const_int (NULL_RTX, mode, tem, 7472 (HOST_WIDE_INT_1U << len) - 1); 7473 } 7474 else 7475 /* Any other cases we can't handle. */ 7476 return x; 7477 7478 /* If we couldn't do this for some reason, return the original 7479 expression. */ 7480 if (GET_CODE (tem) == CLOBBER) 7481 return x; 7482 7483 return tem; 7484 } 7485 7486 /* X is a SET which contains an assignment of one object into 7487 a part of another (such as a bit-field assignment, STRICT_LOW_PART, 7488 or certain SUBREGS). If possible, convert it into a series of 7489 logical operations. 7490 7491 We half-heartedly support variable positions, but do not at all 7492 support variable lengths. */ 7493 7494 static const_rtx 7495 expand_field_assignment (const_rtx x) 7496 { 7497 rtx inner; 7498 rtx pos; /* Always counts from low bit. */ 7499 int len, inner_len; 7500 rtx mask, cleared, masked; 7501 scalar_int_mode compute_mode; 7502 7503 /* Loop until we find something we can't simplify. */ 7504 while (1) 7505 { 7506 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART 7507 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) 7508 { 7509 rtx x0 = XEXP (SET_DEST (x), 0); 7510 if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len)) 7511 break; 7512 inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); 7513 pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)), 7514 MAX_MODE_INT); 7515 } 7516 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 7517 && CONST_INT_P (XEXP (SET_DEST (x), 1))) 7518 { 7519 inner = XEXP (SET_DEST (x), 0); 7520 if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (&inner_len)) 7521 break; 7522 7523 len = INTVAL (XEXP (SET_DEST (x), 1)); 7524 pos = XEXP (SET_DEST (x), 2); 7525 7526 /* A constant position should stay within the width of INNER. */ 7527 if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len) 7528 break; 7529 7530 if (BITS_BIG_ENDIAN) 7531 { 7532 if (CONST_INT_P (pos)) 7533 pos = GEN_INT (inner_len - len - INTVAL (pos)); 7534 else if (GET_CODE (pos) == MINUS 7535 && CONST_INT_P (XEXP (pos, 1)) 7536 && INTVAL (XEXP (pos, 1)) == inner_len - len) 7537 /* If position is ADJUST - X, new position is X. */ 7538 pos = XEXP (pos, 0); 7539 else 7540 pos = simplify_gen_binary (MINUS, GET_MODE (pos), 7541 gen_int_mode (inner_len - len, 7542 GET_MODE (pos)), 7543 pos); 7544 } 7545 } 7546 7547 /* If the destination is a subreg that overwrites the whole of the inner 7548 register, we can move the subreg to the source. */ 7549 else if (GET_CODE (SET_DEST (x)) == SUBREG 7550 /* We need SUBREGs to compute nonzero_bits properly. */ 7551 && nonzero_sign_valid 7552 && !read_modify_subreg_p (SET_DEST (x))) 7553 { 7554 x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)), 7555 gen_lowpart 7556 (GET_MODE (SUBREG_REG (SET_DEST (x))), 7557 SET_SRC (x))); 7558 continue; 7559 } 7560 else 7561 break; 7562 7563 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 7564 inner = SUBREG_REG (inner); 7565 7566 /* Don't attempt bitwise arithmetic on non scalar integer modes. */ 7567 if (!is_a <scalar_int_mode> (GET_MODE (inner), &compute_mode)) 7568 { 7569 /* Don't do anything for vector or complex integral types. */ 7570 if (! FLOAT_MODE_P (GET_MODE (inner))) 7571 break; 7572 7573 /* Try to find an integral mode to pun with. */ 7574 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner)), 0) 7575 .exists (&compute_mode)) 7576 break; 7577 7578 inner = gen_lowpart (compute_mode, inner); 7579 } 7580 7581 /* Compute a mask of LEN bits, if we can do this on the host machine. */ 7582 if (len >= HOST_BITS_PER_WIDE_INT) 7583 break; 7584 7585 /* Don't try to compute in too wide unsupported modes. */ 7586 if (!targetm.scalar_mode_supported_p (compute_mode)) 7587 break; 7588 7589 /* Now compute the equivalent expression. Make a copy of INNER 7590 for the SET_DEST in case it is a MEM into which we will substitute; 7591 we don't want shared RTL in that case. */ 7592 mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1, 7593 compute_mode); 7594 cleared = simplify_gen_binary (AND, compute_mode, 7595 simplify_gen_unary (NOT, compute_mode, 7596 simplify_gen_binary (ASHIFT, 7597 compute_mode, 7598 mask, pos), 7599 compute_mode), 7600 inner); 7601 masked = simplify_gen_binary (ASHIFT, compute_mode, 7602 simplify_gen_binary ( 7603 AND, compute_mode, 7604 gen_lowpart (compute_mode, SET_SRC (x)), 7605 mask), 7606 pos); 7607 7608 x = gen_rtx_SET (copy_rtx (inner), 7609 simplify_gen_binary (IOR, compute_mode, 7610 cleared, masked)); 7611 } 7612 7613 return x; 7614 } 7615 7616 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, 7617 it is an RTX that represents the (variable) starting position; otherwise, 7618 POS is the (constant) starting bit position. Both are counted from the LSB. 7619 7620 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one. 7621 7622 IN_DEST is nonzero if this is a reference in the destination of a SET. 7623 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, 7624 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will 7625 be used. 7626 7627 IN_COMPARE is nonzero if we are in a COMPARE. This means that a 7628 ZERO_EXTRACT should be built even for bits starting at bit 0. 7629 7630 MODE is the desired mode of the result (if IN_DEST == 0). 7631 7632 The result is an RTX for the extraction or NULL_RTX if the target 7633 can't handle it. */ 7634 7635 static rtx 7636 make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos, 7637 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp, 7638 int in_dest, int in_compare) 7639 { 7640 /* This mode describes the size of the storage area 7641 to fetch the overall value from. Within that, we 7642 ignore the POS lowest bits, etc. */ 7643 machine_mode is_mode = GET_MODE (inner); 7644 machine_mode inner_mode; 7645 scalar_int_mode wanted_inner_mode; 7646 scalar_int_mode wanted_inner_reg_mode = word_mode; 7647 scalar_int_mode pos_mode = word_mode; 7648 machine_mode extraction_mode = word_mode; 7649 rtx new_rtx = 0; 7650 rtx orig_pos_rtx = pos_rtx; 7651 HOST_WIDE_INT orig_pos; 7652 7653 if (pos_rtx && CONST_INT_P (pos_rtx)) 7654 pos = INTVAL (pos_rtx), pos_rtx = 0; 7655 7656 if (GET_CODE (inner) == SUBREG 7657 && subreg_lowpart_p (inner) 7658 && (paradoxical_subreg_p (inner) 7659 /* If trying or potentionally trying to extract 7660 bits outside of is_mode, don't look through 7661 non-paradoxical SUBREGs. See PR82192. */ 7662 || (pos_rtx == NULL_RTX 7663 && known_le (pos + len, GET_MODE_PRECISION (is_mode))))) 7664 { 7665 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), 7666 consider just the QI as the memory to extract from. 7667 The subreg adds or removes high bits; its mode is 7668 irrelevant to the meaning of this extraction, 7669 since POS and LEN count from the lsb. */ 7670 if (MEM_P (SUBREG_REG (inner))) 7671 is_mode = GET_MODE (SUBREG_REG (inner)); 7672 inner = SUBREG_REG (inner); 7673 } 7674 else if (GET_CODE (inner) == ASHIFT 7675 && CONST_INT_P (XEXP (inner, 1)) 7676 && pos_rtx == 0 && pos == 0 7677 && len > UINTVAL (XEXP (inner, 1))) 7678 { 7679 /* We're extracting the least significant bits of an rtx 7680 (ashift X (const_int C)), where LEN > C. Extract the 7681 least significant (LEN - C) bits of X, giving an rtx 7682 whose mode is MODE, then shift it left C times. */ 7683 new_rtx = make_extraction (mode, XEXP (inner, 0), 7684 0, 0, len - INTVAL (XEXP (inner, 1)), 7685 unsignedp, in_dest, in_compare); 7686 if (new_rtx != 0) 7687 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1)); 7688 } 7689 else if (GET_CODE (inner) == TRUNCATE 7690 /* If trying or potentionally trying to extract 7691 bits outside of is_mode, don't look through 7692 TRUNCATE. See PR82192. */ 7693 && pos_rtx == NULL_RTX 7694 && known_le (pos + len, GET_MODE_PRECISION (is_mode))) 7695 inner = XEXP (inner, 0); 7696 7697 inner_mode = GET_MODE (inner); 7698 7699 /* See if this can be done without an extraction. We never can if the 7700 width of the field is not the same as that of some integer mode. For 7701 registers, we can only avoid the extraction if the position is at the 7702 low-order bit and this is either not in the destination or we have the 7703 appropriate STRICT_LOW_PART operation available. 7704 7705 For MEM, we can avoid an extract if the field starts on an appropriate 7706 boundary and we can change the mode of the memory reference. */ 7707 7708 scalar_int_mode tmode; 7709 if (int_mode_for_size (len, 1).exists (&tmode) 7710 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 7711 && !MEM_P (inner) 7712 && (pos == 0 || REG_P (inner)) 7713 && (inner_mode == tmode 7714 || !REG_P (inner) 7715 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode) 7716 || reg_truncated_to_mode (tmode, inner)) 7717 && (! in_dest 7718 || (REG_P (inner) 7719 && have_insn_for (STRICT_LOW_PART, tmode)))) 7720 || (MEM_P (inner) && pos_rtx == 0 7721 && (pos 7722 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) 7723 : BITS_PER_UNIT)) == 0 7724 /* We can't do this if we are widening INNER_MODE (it 7725 may not be aligned, for one thing). */ 7726 && !paradoxical_subreg_p (tmode, inner_mode) 7727 && known_le (pos + len, GET_MODE_PRECISION (is_mode)) 7728 && (inner_mode == tmode 7729 || (! mode_dependent_address_p (XEXP (inner, 0), 7730 MEM_ADDR_SPACE (inner)) 7731 && ! MEM_VOLATILE_P (inner)))))) 7732 { 7733 /* If INNER is a MEM, make a new MEM that encompasses just the desired 7734 field. If the original and current mode are the same, we need not 7735 adjust the offset. Otherwise, we do if bytes big endian. 7736 7737 If INNER is not a MEM, get a piece consisting of just the field 7738 of interest (in this case POS % BITS_PER_WORD must be 0). */ 7739 7740 if (MEM_P (inner)) 7741 { 7742 poly_int64 offset; 7743 7744 /* POS counts from lsb, but make OFFSET count in memory order. */ 7745 if (BYTES_BIG_ENDIAN) 7746 offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode) 7747 - len - pos); 7748 else 7749 offset = pos / BITS_PER_UNIT; 7750 7751 new_rtx = adjust_address_nv (inner, tmode, offset); 7752 } 7753 else if (REG_P (inner)) 7754 { 7755 if (tmode != inner_mode) 7756 { 7757 /* We can't call gen_lowpart in a DEST since we 7758 always want a SUBREG (see below) and it would sometimes 7759 return a new hard register. */ 7760 if (pos || in_dest) 7761 { 7762 poly_uint64 offset 7763 = subreg_offset_from_lsb (tmode, inner_mode, pos); 7764 7765 /* Avoid creating invalid subregs, for example when 7766 simplifying (x>>32)&255. */ 7767 if (!validate_subreg (tmode, inner_mode, inner, offset)) 7768 return NULL_RTX; 7769 7770 new_rtx = gen_rtx_SUBREG (tmode, inner, offset); 7771 } 7772 else 7773 new_rtx = gen_lowpart (tmode, inner); 7774 } 7775 else 7776 new_rtx = inner; 7777 } 7778 else 7779 new_rtx = force_to_mode (inner, tmode, 7780 len >= HOST_BITS_PER_WIDE_INT 7781 ? HOST_WIDE_INT_M1U 7782 : (HOST_WIDE_INT_1U << len) - 1, 0); 7783 7784 /* If this extraction is going into the destination of a SET, 7785 make a STRICT_LOW_PART unless we made a MEM. */ 7786 7787 if (in_dest) 7788 return (MEM_P (new_rtx) ? new_rtx 7789 : (GET_CODE (new_rtx) != SUBREG 7790 ? gen_rtx_CLOBBER (tmode, const0_rtx) 7791 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx))); 7792 7793 if (mode == tmode) 7794 return new_rtx; 7795 7796 if (CONST_SCALAR_INT_P (new_rtx)) 7797 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 7798 mode, new_rtx, tmode); 7799 7800 /* If we know that no extraneous bits are set, and that the high 7801 bit is not set, convert the extraction to the cheaper of 7802 sign and zero extension, that are equivalent in these cases. */ 7803 if (flag_expensive_optimizations 7804 && (HWI_COMPUTABLE_MODE_P (tmode) 7805 && ((nonzero_bits (new_rtx, tmode) 7806 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1)) 7807 == 0))) 7808 { 7809 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx); 7810 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx); 7811 7812 /* Prefer ZERO_EXTENSION, since it gives more information to 7813 backends. */ 7814 if (set_src_cost (temp, mode, optimize_this_for_speed_p) 7815 <= set_src_cost (temp1, mode, optimize_this_for_speed_p)) 7816 return temp; 7817 return temp1; 7818 } 7819 7820 /* Otherwise, sign- or zero-extend unless we already are in the 7821 proper mode. */ 7822 7823 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 7824 mode, new_rtx)); 7825 } 7826 7827 /* Unless this is a COMPARE or we have a funny memory reference, 7828 don't do anything with zero-extending field extracts starting at 7829 the low-order bit since they are simple AND operations. */ 7830 if (pos_rtx == 0 && pos == 0 && ! in_dest 7831 && ! in_compare && unsignedp) 7832 return 0; 7833 7834 /* Unless INNER is not MEM, reject this if we would be spanning bytes or 7835 if the position is not a constant and the length is not 1. In all 7836 other cases, we would only be going outside our object in cases when 7837 an original shift would have been undefined. */ 7838 if (MEM_P (inner) 7839 && ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode))) 7840 || (pos_rtx != 0 && len != 1))) 7841 return 0; 7842 7843 enum extraction_pattern pattern = (in_dest ? EP_insv 7844 : unsignedp ? EP_extzv : EP_extv); 7845 7846 /* If INNER is not from memory, we want it to have the mode of a register 7847 extraction pattern's structure operand, or word_mode if there is no 7848 such pattern. The same applies to extraction_mode and pos_mode 7849 and their respective operands. 7850 7851 For memory, assume that the desired extraction_mode and pos_mode 7852 are the same as for a register operation, since at present we don't 7853 have named patterns for aligned memory structures. */ 7854 class extraction_insn insn; 7855 unsigned int inner_size; 7856 if (GET_MODE_BITSIZE (inner_mode).is_constant (&inner_size) 7857 && get_best_reg_extraction_insn (&insn, pattern, inner_size, mode)) 7858 { 7859 wanted_inner_reg_mode = insn.struct_mode.require (); 7860 pos_mode = insn.pos_mode; 7861 extraction_mode = insn.field_mode; 7862 } 7863 7864 /* Never narrow an object, since that might not be safe. */ 7865 7866 if (mode != VOIDmode 7867 && partial_subreg_p (extraction_mode, mode)) 7868 extraction_mode = mode; 7869 7870 /* Punt if len is too large for extraction_mode. */ 7871 if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode))) 7872 return NULL_RTX; 7873 7874 if (!MEM_P (inner)) 7875 wanted_inner_mode = wanted_inner_reg_mode; 7876 else 7877 { 7878 /* Be careful not to go beyond the extracted object and maintain the 7879 natural alignment of the memory. */ 7880 wanted_inner_mode = smallest_int_mode_for_size (len); 7881 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len 7882 > GET_MODE_BITSIZE (wanted_inner_mode)) 7883 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode).require (); 7884 } 7885 7886 orig_pos = pos; 7887 7888 if (BITS_BIG_ENDIAN) 7889 { 7890 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to 7891 BITS_BIG_ENDIAN style. If position is constant, compute new 7892 position. Otherwise, build subtraction. 7893 Note that POS is relative to the mode of the original argument. 7894 If it's a MEM we need to recompute POS relative to that. 7895 However, if we're extracting from (or inserting into) a register, 7896 we want to recompute POS relative to wanted_inner_mode. */ 7897 int width; 7898 if (!MEM_P (inner)) 7899 width = GET_MODE_BITSIZE (wanted_inner_mode); 7900 else if (!GET_MODE_BITSIZE (is_mode).is_constant (&width)) 7901 return NULL_RTX; 7902 7903 if (pos_rtx == 0) 7904 pos = width - len - pos; 7905 else 7906 pos_rtx 7907 = gen_rtx_MINUS (GET_MODE (pos_rtx), 7908 gen_int_mode (width - len, GET_MODE (pos_rtx)), 7909 pos_rtx); 7910 /* POS may be less than 0 now, but we check for that below. 7911 Note that it can only be less than 0 if !MEM_P (inner). */ 7912 } 7913 7914 /* If INNER has a wider mode, and this is a constant extraction, try to 7915 make it smaller and adjust the byte to point to the byte containing 7916 the value. */ 7917 if (wanted_inner_mode != VOIDmode 7918 && inner_mode != wanted_inner_mode 7919 && ! pos_rtx 7920 && partial_subreg_p (wanted_inner_mode, is_mode) 7921 && MEM_P (inner) 7922 && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner)) 7923 && ! MEM_VOLATILE_P (inner)) 7924 { 7925 poly_int64 offset = 0; 7926 7927 /* The computations below will be correct if the machine is big 7928 endian in both bits and bytes or little endian in bits and bytes. 7929 If it is mixed, we must adjust. */ 7930 7931 /* If bytes are big endian and we had a paradoxical SUBREG, we must 7932 adjust OFFSET to compensate. */ 7933 if (BYTES_BIG_ENDIAN 7934 && paradoxical_subreg_p (is_mode, inner_mode)) 7935 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); 7936 7937 /* We can now move to the desired byte. */ 7938 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode)) 7939 * GET_MODE_SIZE (wanted_inner_mode); 7940 pos %= GET_MODE_BITSIZE (wanted_inner_mode); 7941 7942 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN 7943 && is_mode != wanted_inner_mode) 7944 offset = (GET_MODE_SIZE (is_mode) 7945 - GET_MODE_SIZE (wanted_inner_mode) - offset); 7946 7947 inner = adjust_address_nv (inner, wanted_inner_mode, offset); 7948 } 7949 7950 /* If INNER is not memory, get it into the proper mode. If we are changing 7951 its mode, POS must be a constant and smaller than the size of the new 7952 mode. */ 7953 else if (!MEM_P (inner)) 7954 { 7955 /* On the LHS, don't create paradoxical subregs implicitely truncating 7956 the register unless TARGET_TRULY_NOOP_TRUNCATION. */ 7957 if (in_dest 7958 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner), 7959 wanted_inner_mode)) 7960 return NULL_RTX; 7961 7962 if (GET_MODE (inner) != wanted_inner_mode 7963 && (pos_rtx != 0 7964 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) 7965 return NULL_RTX; 7966 7967 if (orig_pos < 0) 7968 return NULL_RTX; 7969 7970 inner = force_to_mode (inner, wanted_inner_mode, 7971 pos_rtx 7972 || len + orig_pos >= HOST_BITS_PER_WIDE_INT 7973 ? HOST_WIDE_INT_M1U 7974 : (((HOST_WIDE_INT_1U << len) - 1) 7975 << orig_pos), 7976 0); 7977 } 7978 7979 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we 7980 have to zero extend. Otherwise, we can just use a SUBREG. 7981 7982 We dealt with constant rtxes earlier, so pos_rtx cannot 7983 have VOIDmode at this point. */ 7984 if (pos_rtx != 0 7985 && (GET_MODE_SIZE (pos_mode) 7986 > GET_MODE_SIZE (as_a <scalar_int_mode> (GET_MODE (pos_rtx))))) 7987 { 7988 rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx, 7989 GET_MODE (pos_rtx)); 7990 7991 /* If we know that no extraneous bits are set, and that the high 7992 bit is not set, convert extraction to cheaper one - either 7993 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these 7994 cases. */ 7995 if (flag_expensive_optimizations 7996 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx)) 7997 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) 7998 & ~(((unsigned HOST_WIDE_INT) 7999 GET_MODE_MASK (GET_MODE (pos_rtx))) 8000 >> 1)) 8001 == 0))) 8002 { 8003 rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx, 8004 GET_MODE (pos_rtx)); 8005 8006 /* Prefer ZERO_EXTENSION, since it gives more information to 8007 backends. */ 8008 if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p) 8009 < set_src_cost (temp, pos_mode, optimize_this_for_speed_p)) 8010 temp = temp1; 8011 } 8012 pos_rtx = temp; 8013 } 8014 8015 /* Make POS_RTX unless we already have it and it is correct. If we don't 8016 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must 8017 be a CONST_INT. */ 8018 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) 8019 pos_rtx = orig_pos_rtx; 8020 8021 else if (pos_rtx == 0) 8022 pos_rtx = GEN_INT (pos); 8023 8024 /* Make the required operation. See if we can use existing rtx. */ 8025 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, 8026 extraction_mode, inner, GEN_INT (len), pos_rtx); 8027 if (! in_dest) 8028 new_rtx = gen_lowpart (mode, new_rtx); 8029 8030 return new_rtx; 8031 } 8032 8033 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that 8034 can be commuted with any other operations in X. Return X without 8035 that shift if so. */ 8036 8037 static rtx 8038 extract_left_shift (scalar_int_mode mode, rtx x, int count) 8039 { 8040 enum rtx_code code = GET_CODE (x); 8041 rtx tem; 8042 8043 switch (code) 8044 { 8045 case ASHIFT: 8046 /* This is the shift itself. If it is wide enough, we will return 8047 either the value being shifted if the shift count is equal to 8048 COUNT or a shift for the difference. */ 8049 if (CONST_INT_P (XEXP (x, 1)) 8050 && INTVAL (XEXP (x, 1)) >= count) 8051 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), 8052 INTVAL (XEXP (x, 1)) - count); 8053 break; 8054 8055 case NEG: case NOT: 8056 if ((tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0) 8057 return simplify_gen_unary (code, mode, tem, mode); 8058 8059 break; 8060 8061 case PLUS: case IOR: case XOR: case AND: 8062 /* If we can safely shift this constant and we find the inner shift, 8063 make a new operation. */ 8064 if (CONST_INT_P (XEXP (x, 1)) 8065 && (UINTVAL (XEXP (x, 1)) 8066 & (((HOST_WIDE_INT_1U << count)) - 1)) == 0 8067 && (tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0) 8068 { 8069 HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count; 8070 return simplify_gen_binary (code, mode, tem, 8071 gen_int_mode (val, mode)); 8072 } 8073 break; 8074 8075 default: 8076 break; 8077 } 8078 8079 return 0; 8080 } 8081 8082 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current 8083 level of the expression and MODE is its mode. IN_CODE is as for 8084 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE 8085 that should be used when recursing on operands of *X_PTR. 8086 8087 There are two possible actions: 8088 8089 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE 8090 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value. 8091 8092 - Return a new rtx, which the caller returns directly. */ 8093 8094 static rtx 8095 make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr, 8096 enum rtx_code in_code, 8097 enum rtx_code *next_code_ptr) 8098 { 8099 rtx x = *x_ptr; 8100 enum rtx_code next_code = *next_code_ptr; 8101 enum rtx_code code = GET_CODE (x); 8102 int mode_width = GET_MODE_PRECISION (mode); 8103 rtx rhs, lhs; 8104 rtx new_rtx = 0; 8105 int i; 8106 rtx tem; 8107 scalar_int_mode inner_mode; 8108 bool equality_comparison = false; 8109 8110 if (in_code == EQ) 8111 { 8112 equality_comparison = true; 8113 in_code = COMPARE; 8114 } 8115 8116 /* Process depending on the code of this operation. If NEW is set 8117 nonzero, it will be returned. */ 8118 8119 switch (code) 8120 { 8121 case ASHIFT: 8122 /* Convert shifts by constants into multiplications if inside 8123 an address. */ 8124 if (in_code == MEM && CONST_INT_P (XEXP (x, 1)) 8125 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 8126 && INTVAL (XEXP (x, 1)) >= 0) 8127 { 8128 HOST_WIDE_INT count = INTVAL (XEXP (x, 1)); 8129 HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count; 8130 8131 new_rtx = make_compound_operation (XEXP (x, 0), next_code); 8132 if (GET_CODE (new_rtx) == NEG) 8133 { 8134 new_rtx = XEXP (new_rtx, 0); 8135 multval = -multval; 8136 } 8137 multval = trunc_int_for_mode (multval, mode); 8138 new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode)); 8139 } 8140 break; 8141 8142 case PLUS: 8143 lhs = XEXP (x, 0); 8144 rhs = XEXP (x, 1); 8145 lhs = make_compound_operation (lhs, next_code); 8146 rhs = make_compound_operation (rhs, next_code); 8147 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG) 8148 { 8149 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0), 8150 XEXP (lhs, 1)); 8151 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem); 8152 } 8153 else if (GET_CODE (lhs) == MULT 8154 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0)) 8155 { 8156 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0), 8157 simplify_gen_unary (NEG, mode, 8158 XEXP (lhs, 1), 8159 mode)); 8160 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem); 8161 } 8162 else 8163 { 8164 SUBST (XEXP (x, 0), lhs); 8165 SUBST (XEXP (x, 1), rhs); 8166 } 8167 maybe_swap_commutative_operands (x); 8168 return x; 8169 8170 case MINUS: 8171 lhs = XEXP (x, 0); 8172 rhs = XEXP (x, 1); 8173 lhs = make_compound_operation (lhs, next_code); 8174 rhs = make_compound_operation (rhs, next_code); 8175 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG) 8176 { 8177 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0), 8178 XEXP (rhs, 1)); 8179 return simplify_gen_binary (PLUS, mode, tem, lhs); 8180 } 8181 else if (GET_CODE (rhs) == MULT 8182 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0)) 8183 { 8184 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0), 8185 simplify_gen_unary (NEG, mode, 8186 XEXP (rhs, 1), 8187 mode)); 8188 return simplify_gen_binary (PLUS, mode, tem, lhs); 8189 } 8190 else 8191 { 8192 SUBST (XEXP (x, 0), lhs); 8193 SUBST (XEXP (x, 1), rhs); 8194 return x; 8195 } 8196 8197 case AND: 8198 /* If the second operand is not a constant, we can't do anything 8199 with it. */ 8200 if (!CONST_INT_P (XEXP (x, 1))) 8201 break; 8202 8203 /* If the constant is a power of two minus one and the first operand 8204 is a logical right shift, make an extraction. */ 8205 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 8206 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 8207 { 8208 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 8209 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), 8210 i, 1, 0, in_code == COMPARE); 8211 } 8212 8213 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ 8214 else if (GET_CODE (XEXP (x, 0)) == SUBREG 8215 && subreg_lowpart_p (XEXP (x, 0)) 8216 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))), 8217 &inner_mode) 8218 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT 8219 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 8220 { 8221 rtx inner_x0 = SUBREG_REG (XEXP (x, 0)); 8222 new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code); 8223 new_rtx = make_extraction (inner_mode, new_rtx, 0, 8224 XEXP (inner_x0, 1), 8225 i, 1, 0, in_code == COMPARE); 8226 8227 /* If we narrowed the mode when dropping the subreg, then we lose. */ 8228 if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)) 8229 new_rtx = NULL; 8230 8231 /* If that didn't give anything, see if the AND simplifies on 8232 its own. */ 8233 if (!new_rtx && i >= 0) 8234 { 8235 new_rtx = make_compound_operation (XEXP (x, 0), next_code); 8236 new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i, 1, 8237 0, in_code == COMPARE); 8238 } 8239 } 8240 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ 8241 else if ((GET_CODE (XEXP (x, 0)) == XOR 8242 || GET_CODE (XEXP (x, 0)) == IOR) 8243 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT 8244 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT 8245 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 8246 { 8247 /* Apply the distributive law, and then try to make extractions. */ 8248 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, 8249 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), 8250 XEXP (x, 1)), 8251 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), 8252 XEXP (x, 1))); 8253 new_rtx = make_compound_operation (new_rtx, in_code); 8254 } 8255 8256 /* If we are have (and (rotate X C) M) and C is larger than the number 8257 of bits in M, this is an extraction. */ 8258 8259 else if (GET_CODE (XEXP (x, 0)) == ROTATE 8260 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 8261 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0 8262 && i <= INTVAL (XEXP (XEXP (x, 0), 1))) 8263 { 8264 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 8265 new_rtx = make_extraction (mode, new_rtx, 8266 (GET_MODE_PRECISION (mode) 8267 - INTVAL (XEXP (XEXP (x, 0), 1))), 8268 NULL_RTX, i, 1, 0, in_code == COMPARE); 8269 } 8270 8271 /* On machines without logical shifts, if the operand of the AND is 8272 a logical shift and our mask turns off all the propagated sign 8273 bits, we can replace the logical shift with an arithmetic shift. */ 8274 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 8275 && !have_insn_for (LSHIFTRT, mode) 8276 && have_insn_for (ASHIFTRT, mode) 8277 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 8278 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 8279 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 8280 && mode_width <= HOST_BITS_PER_WIDE_INT) 8281 { 8282 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 8283 8284 mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); 8285 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) 8286 SUBST (XEXP (x, 0), 8287 gen_rtx_ASHIFTRT (mode, 8288 make_compound_operation (XEXP (XEXP (x, 8289 0), 8290 0), 8291 next_code), 8292 XEXP (XEXP (x, 0), 1))); 8293 } 8294 8295 /* If the constant is one less than a power of two, this might be 8296 representable by an extraction even if no shift is present. 8297 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless 8298 we are in a COMPARE. */ 8299 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 8300 new_rtx = make_extraction (mode, 8301 make_compound_operation (XEXP (x, 0), 8302 next_code), 8303 0, NULL_RTX, i, 1, 0, in_code == COMPARE); 8304 8305 /* If we are in a comparison and this is an AND with a power of two, 8306 convert this into the appropriate bit extract. */ 8307 else if (in_code == COMPARE 8308 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0 8309 && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1)) 8310 new_rtx = make_extraction (mode, 8311 make_compound_operation (XEXP (x, 0), 8312 next_code), 8313 i, NULL_RTX, 1, 1, 0, 1); 8314 8315 /* If the one operand is a paradoxical subreg of a register or memory and 8316 the constant (limited to the smaller mode) has only zero bits where 8317 the sub expression has known zero bits, this can be expressed as 8318 a zero_extend. */ 8319 else if (GET_CODE (XEXP (x, 0)) == SUBREG) 8320 { 8321 rtx sub; 8322 8323 sub = XEXP (XEXP (x, 0), 0); 8324 machine_mode sub_mode = GET_MODE (sub); 8325 int sub_width; 8326 if ((REG_P (sub) || MEM_P (sub)) 8327 && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width) 8328 && sub_width < mode_width) 8329 { 8330 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode); 8331 unsigned HOST_WIDE_INT mask; 8332 8333 /* original AND constant with all the known zero bits set */ 8334 mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode)); 8335 if ((mask & mode_mask) == mode_mask) 8336 { 8337 new_rtx = make_compound_operation (sub, next_code); 8338 new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width, 8339 1, 0, in_code == COMPARE); 8340 } 8341 } 8342 } 8343 8344 break; 8345 8346 case LSHIFTRT: 8347 /* If the sign bit is known to be zero, replace this with an 8348 arithmetic shift. */ 8349 if (have_insn_for (ASHIFTRT, mode) 8350 && ! have_insn_for (LSHIFTRT, mode) 8351 && mode_width <= HOST_BITS_PER_WIDE_INT 8352 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) 8353 { 8354 new_rtx = gen_rtx_ASHIFTRT (mode, 8355 make_compound_operation (XEXP (x, 0), 8356 next_code), 8357 XEXP (x, 1)); 8358 break; 8359 } 8360 8361 /* fall through */ 8362 8363 case ASHIFTRT: 8364 lhs = XEXP (x, 0); 8365 rhs = XEXP (x, 1); 8366 8367 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, 8368 this is a SIGN_EXTRACT. */ 8369 if (CONST_INT_P (rhs) 8370 && GET_CODE (lhs) == ASHIFT 8371 && CONST_INT_P (XEXP (lhs, 1)) 8372 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)) 8373 && INTVAL (XEXP (lhs, 1)) >= 0 8374 && INTVAL (rhs) < mode_width) 8375 { 8376 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code); 8377 new_rtx = make_extraction (mode, new_rtx, 8378 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), 8379 NULL_RTX, mode_width - INTVAL (rhs), 8380 code == LSHIFTRT, 0, in_code == COMPARE); 8381 break; 8382 } 8383 8384 /* See if we have operations between an ASHIFTRT and an ASHIFT. 8385 If so, try to merge the shifts into a SIGN_EXTEND. We could 8386 also do this for some cases of SIGN_EXTRACT, but it doesn't 8387 seem worth the effort; the case checked for occurs on Alpha. */ 8388 8389 if (!OBJECT_P (lhs) 8390 && ! (GET_CODE (lhs) == SUBREG 8391 && (OBJECT_P (SUBREG_REG (lhs)))) 8392 && CONST_INT_P (rhs) 8393 && INTVAL (rhs) >= 0 8394 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT 8395 && INTVAL (rhs) < mode_width 8396 && (new_rtx = extract_left_shift (mode, lhs, INTVAL (rhs))) != 0) 8397 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, 8398 next_code), 8399 0, NULL_RTX, mode_width - INTVAL (rhs), 8400 code == LSHIFTRT, 0, in_code == COMPARE); 8401 8402 break; 8403 8404 case SUBREG: 8405 /* Call ourselves recursively on the inner expression. If we are 8406 narrowing the object and it has a different RTL code from 8407 what it originally did, do this SUBREG as a force_to_mode. */ 8408 { 8409 rtx inner = SUBREG_REG (x), simplified; 8410 enum rtx_code subreg_code = in_code; 8411 8412 /* If the SUBREG is masking of a logical right shift, 8413 make an extraction. */ 8414 if (GET_CODE (inner) == LSHIFTRT 8415 && is_a <scalar_int_mode> (GET_MODE (inner), &inner_mode) 8416 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (inner_mode) 8417 && CONST_INT_P (XEXP (inner, 1)) 8418 && UINTVAL (XEXP (inner, 1)) < GET_MODE_PRECISION (inner_mode) 8419 && subreg_lowpart_p (x)) 8420 { 8421 new_rtx = make_compound_operation (XEXP (inner, 0), next_code); 8422 int width = GET_MODE_PRECISION (inner_mode) 8423 - INTVAL (XEXP (inner, 1)); 8424 if (width > mode_width) 8425 width = mode_width; 8426 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (inner, 1), 8427 width, 1, 0, in_code == COMPARE); 8428 break; 8429 } 8430 8431 /* If in_code is COMPARE, it isn't always safe to pass it through 8432 to the recursive make_compound_operation call. */ 8433 if (subreg_code == COMPARE 8434 && (!subreg_lowpart_p (x) 8435 || GET_CODE (inner) == SUBREG 8436 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0) 8437 is (const_int 0), rather than 8438 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). 8439 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0) 8440 for non-equality comparisons against 0 is not equivalent 8441 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */ 8442 || (GET_CODE (inner) == AND 8443 && CONST_INT_P (XEXP (inner, 1)) 8444 && partial_subreg_p (x) 8445 && exact_log2 (UINTVAL (XEXP (inner, 1))) 8446 >= GET_MODE_BITSIZE (mode) - 1))) 8447 subreg_code = SET; 8448 8449 tem = make_compound_operation (inner, subreg_code); 8450 8451 simplified 8452 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x)); 8453 if (simplified) 8454 tem = simplified; 8455 8456 if (GET_CODE (tem) != GET_CODE (inner) 8457 && partial_subreg_p (x) 8458 && subreg_lowpart_p (x)) 8459 { 8460 rtx newer 8461 = force_to_mode (tem, mode, HOST_WIDE_INT_M1U, 0); 8462 8463 /* If we have something other than a SUBREG, we might have 8464 done an expansion, so rerun ourselves. */ 8465 if (GET_CODE (newer) != SUBREG) 8466 newer = make_compound_operation (newer, in_code); 8467 8468 /* force_to_mode can expand compounds. If it just re-expanded 8469 the compound, use gen_lowpart to convert to the desired 8470 mode. */ 8471 if (rtx_equal_p (newer, x) 8472 /* Likewise if it re-expanded the compound only partially. 8473 This happens for SUBREG of ZERO_EXTRACT if they extract 8474 the same number of bits. */ 8475 || (GET_CODE (newer) == SUBREG 8476 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT 8477 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT) 8478 && GET_CODE (inner) == AND 8479 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0)))) 8480 return gen_lowpart (GET_MODE (x), tem); 8481 8482 return newer; 8483 } 8484 8485 if (simplified) 8486 return tem; 8487 } 8488 break; 8489 8490 default: 8491 break; 8492 } 8493 8494 if (new_rtx) 8495 *x_ptr = gen_lowpart (mode, new_rtx); 8496 *next_code_ptr = next_code; 8497 return NULL_RTX; 8498 } 8499 8500 /* Look at the expression rooted at X. Look for expressions 8501 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. 8502 Form these expressions. 8503 8504 Return the new rtx, usually just X. 8505 8506 Also, for machines like the VAX that don't have logical shift insns, 8507 try to convert logical to arithmetic shift operations in cases where 8508 they are equivalent. This undoes the canonicalizations to logical 8509 shifts done elsewhere. 8510 8511 We try, as much as possible, to re-use rtl expressions to save memory. 8512 8513 IN_CODE says what kind of expression we are processing. Normally, it is 8514 SET. In a memory address it is MEM. When processing the arguments of 8515 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more 8516 precisely it is an equality comparison against zero. */ 8517 8518 rtx 8519 make_compound_operation (rtx x, enum rtx_code in_code) 8520 { 8521 enum rtx_code code = GET_CODE (x); 8522 const char *fmt; 8523 int i, j; 8524 enum rtx_code next_code; 8525 rtx new_rtx, tem; 8526 8527 /* Select the code to be used in recursive calls. Once we are inside an 8528 address, we stay there. If we have a comparison, set to COMPARE, 8529 but once inside, go back to our default of SET. */ 8530 8531 next_code = (code == MEM ? MEM 8532 : ((code == COMPARE || COMPARISON_P (x)) 8533 && XEXP (x, 1) == const0_rtx) ? COMPARE 8534 : in_code == COMPARE || in_code == EQ ? SET : in_code); 8535 8536 scalar_int_mode mode; 8537 if (is_a <scalar_int_mode> (GET_MODE (x), &mode)) 8538 { 8539 rtx new_rtx = make_compound_operation_int (mode, &x, in_code, 8540 &next_code); 8541 if (new_rtx) 8542 return new_rtx; 8543 code = GET_CODE (x); 8544 } 8545 8546 /* Now recursively process each operand of this operation. We need to 8547 handle ZERO_EXTEND specially so that we don't lose track of the 8548 inner mode. */ 8549 if (code == ZERO_EXTEND) 8550 { 8551 new_rtx = make_compound_operation (XEXP (x, 0), next_code); 8552 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x), 8553 new_rtx, GET_MODE (XEXP (x, 0))); 8554 if (tem) 8555 return tem; 8556 SUBST (XEXP (x, 0), new_rtx); 8557 return x; 8558 } 8559 8560 fmt = GET_RTX_FORMAT (code); 8561 for (i = 0; i < GET_RTX_LENGTH (code); i++) 8562 if (fmt[i] == 'e') 8563 { 8564 new_rtx = make_compound_operation (XEXP (x, i), next_code); 8565 SUBST (XEXP (x, i), new_rtx); 8566 } 8567 else if (fmt[i] == 'E') 8568 for (j = 0; j < XVECLEN (x, i); j++) 8569 { 8570 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code); 8571 SUBST (XVECEXP (x, i, j), new_rtx); 8572 } 8573 8574 maybe_swap_commutative_operands (x); 8575 return x; 8576 } 8577 8578 /* Given M see if it is a value that would select a field of bits 8579 within an item, but not the entire word. Return -1 if not. 8580 Otherwise, return the starting position of the field, where 0 is the 8581 low-order bit. 8582 8583 *PLEN is set to the length of the field. */ 8584 8585 static int 8586 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen) 8587 { 8588 /* Get the bit number of the first 1 bit from the right, -1 if none. */ 8589 int pos = m ? ctz_hwi (m) : -1; 8590 int len = 0; 8591 8592 if (pos >= 0) 8593 /* Now shift off the low-order zero bits and see if we have a 8594 power of two minus 1. */ 8595 len = exact_log2 ((m >> pos) + 1); 8596 8597 if (len <= 0) 8598 pos = -1; 8599 8600 *plen = len; 8601 return pos; 8602 } 8603 8604 /* If X refers to a register that equals REG in value, replace these 8605 references with REG. */ 8606 static rtx 8607 canon_reg_for_combine (rtx x, rtx reg) 8608 { 8609 rtx op0, op1, op2; 8610 const char *fmt; 8611 int i; 8612 bool copied; 8613 8614 enum rtx_code code = GET_CODE (x); 8615 switch (GET_RTX_CLASS (code)) 8616 { 8617 case RTX_UNARY: 8618 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8619 if (op0 != XEXP (x, 0)) 8620 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0, 8621 GET_MODE (reg)); 8622 break; 8623 8624 case RTX_BIN_ARITH: 8625 case RTX_COMM_ARITH: 8626 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8627 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 8628 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 8629 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); 8630 break; 8631 8632 case RTX_COMPARE: 8633 case RTX_COMM_COMPARE: 8634 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8635 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 8636 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 8637 return simplify_gen_relational (GET_CODE (x), GET_MODE (x), 8638 GET_MODE (op0), op0, op1); 8639 break; 8640 8641 case RTX_TERNARY: 8642 case RTX_BITFIELD_OPS: 8643 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8644 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 8645 op2 = canon_reg_for_combine (XEXP (x, 2), reg); 8646 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2)) 8647 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x), 8648 GET_MODE (op0), op0, op1, op2); 8649 /* FALLTHRU */ 8650 8651 case RTX_OBJ: 8652 if (REG_P (x)) 8653 { 8654 if (rtx_equal_p (get_last_value (reg), x) 8655 || rtx_equal_p (reg, get_last_value (x))) 8656 return reg; 8657 else 8658 break; 8659 } 8660 8661 /* fall through */ 8662 8663 default: 8664 fmt = GET_RTX_FORMAT (code); 8665 copied = false; 8666 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 8667 if (fmt[i] == 'e') 8668 { 8669 rtx op = canon_reg_for_combine (XEXP (x, i), reg); 8670 if (op != XEXP (x, i)) 8671 { 8672 if (!copied) 8673 { 8674 copied = true; 8675 x = copy_rtx (x); 8676 } 8677 XEXP (x, i) = op; 8678 } 8679 } 8680 else if (fmt[i] == 'E') 8681 { 8682 int j; 8683 for (j = 0; j < XVECLEN (x, i); j++) 8684 { 8685 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg); 8686 if (op != XVECEXP (x, i, j)) 8687 { 8688 if (!copied) 8689 { 8690 copied = true; 8691 x = copy_rtx (x); 8692 } 8693 XVECEXP (x, i, j) = op; 8694 } 8695 } 8696 } 8697 8698 break; 8699 } 8700 8701 return x; 8702 } 8703 8704 /* Return X converted to MODE. If the value is already truncated to 8705 MODE we can just return a subreg even though in the general case we 8706 would need an explicit truncation. */ 8707 8708 static rtx 8709 gen_lowpart_or_truncate (machine_mode mode, rtx x) 8710 { 8711 if (!CONST_INT_P (x) 8712 && partial_subreg_p (mode, GET_MODE (x)) 8713 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x)) 8714 && !(REG_P (x) && reg_truncated_to_mode (mode, x))) 8715 { 8716 /* Bit-cast X into an integer mode. */ 8717 if (!SCALAR_INT_MODE_P (GET_MODE (x))) 8718 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)).require (), x); 8719 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode).require (), 8720 x, GET_MODE (x)); 8721 } 8722 8723 return gen_lowpart (mode, x); 8724 } 8725 8726 /* See if X can be simplified knowing that we will only refer to it in 8727 MODE and will only refer to those bits that are nonzero in MASK. 8728 If other bits are being computed or if masking operations are done 8729 that select a superset of the bits in MASK, they can sometimes be 8730 ignored. 8731 8732 Return a possibly simplified expression, but always convert X to 8733 MODE. If X is a CONST_INT, AND the CONST_INT with MASK. 8734 8735 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK 8736 are all off in X. This is used when X will be complemented, by either 8737 NOT, NEG, or XOR. */ 8738 8739 static rtx 8740 force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask, 8741 int just_select) 8742 { 8743 enum rtx_code code = GET_CODE (x); 8744 int next_select = just_select || code == XOR || code == NOT || code == NEG; 8745 machine_mode op_mode; 8746 unsigned HOST_WIDE_INT nonzero; 8747 8748 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the 8749 code below will do the wrong thing since the mode of such an 8750 expression is VOIDmode. 8751 8752 Also do nothing if X is a CLOBBER; this can happen if X was 8753 the return value from a call to gen_lowpart. */ 8754 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) 8755 return x; 8756 8757 /* We want to perform the operation in its present mode unless we know 8758 that the operation is valid in MODE, in which case we do the operation 8759 in MODE. */ 8760 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) 8761 && have_insn_for (code, mode)) 8762 ? mode : GET_MODE (x)); 8763 8764 /* It is not valid to do a right-shift in a narrower mode 8765 than the one it came in with. */ 8766 if ((code == LSHIFTRT || code == ASHIFTRT) 8767 && partial_subreg_p (mode, GET_MODE (x))) 8768 op_mode = GET_MODE (x); 8769 8770 /* Truncate MASK to fit OP_MODE. */ 8771 if (op_mode) 8772 mask &= GET_MODE_MASK (op_mode); 8773 8774 /* Determine what bits of X are guaranteed to be (non)zero. */ 8775 nonzero = nonzero_bits (x, mode); 8776 8777 /* If none of the bits in X are needed, return a zero. */ 8778 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x)) 8779 x = const0_rtx; 8780 8781 /* If X is a CONST_INT, return a new one. Do this here since the 8782 test below will fail. */ 8783 if (CONST_INT_P (x)) 8784 { 8785 if (SCALAR_INT_MODE_P (mode)) 8786 return gen_int_mode (INTVAL (x) & mask, mode); 8787 else 8788 { 8789 x = GEN_INT (INTVAL (x) & mask); 8790 return gen_lowpart_common (mode, x); 8791 } 8792 } 8793 8794 /* If X is narrower than MODE and we want all the bits in X's mode, just 8795 get X in the proper mode. */ 8796 if (paradoxical_subreg_p (mode, GET_MODE (x)) 8797 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) 8798 return gen_lowpart (mode, x); 8799 8800 /* We can ignore the effect of a SUBREG if it narrows the mode or 8801 if the constant masks to zero all the bits the mode doesn't have. */ 8802 if (GET_CODE (x) == SUBREG 8803 && subreg_lowpart_p (x) 8804 && (partial_subreg_p (x) 8805 || (mask 8806 & GET_MODE_MASK (GET_MODE (x)) 8807 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)) 8808 return force_to_mode (SUBREG_REG (x), mode, mask, next_select); 8809 8810 scalar_int_mode int_mode, xmode; 8811 if (is_a <scalar_int_mode> (mode, &int_mode) 8812 && is_a <scalar_int_mode> (GET_MODE (x), &xmode)) 8813 /* OP_MODE is either MODE or XMODE, so it must be a scalar 8814 integer too. */ 8815 return force_int_to_mode (x, int_mode, xmode, 8816 as_a <scalar_int_mode> (op_mode), 8817 mask, just_select); 8818 8819 return gen_lowpart_or_truncate (mode, x); 8820 } 8821 8822 /* Subroutine of force_to_mode that handles cases in which both X and 8823 the result are scalar integers. MODE is the mode of the result, 8824 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE 8825 is preferred for simplified versions of X. The other arguments 8826 are as for force_to_mode. */ 8827 8828 static rtx 8829 force_int_to_mode (rtx x, scalar_int_mode mode, scalar_int_mode xmode, 8830 scalar_int_mode op_mode, unsigned HOST_WIDE_INT mask, 8831 int just_select) 8832 { 8833 enum rtx_code code = GET_CODE (x); 8834 int next_select = just_select || code == XOR || code == NOT || code == NEG; 8835 unsigned HOST_WIDE_INT fuller_mask; 8836 rtx op0, op1, temp; 8837 poly_int64 const_op0; 8838 8839 /* When we have an arithmetic operation, or a shift whose count we 8840 do not know, we need to assume that all bits up to the highest-order 8841 bit in MASK will be needed. This is how we form such a mask. */ 8842 if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1))) 8843 fuller_mask = HOST_WIDE_INT_M1U; 8844 else 8845 fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (mask) + 1)) 8846 - 1); 8847 8848 switch (code) 8849 { 8850 case CLOBBER: 8851 /* If X is a (clobber (const_int)), return it since we know we are 8852 generating something that won't match. */ 8853 return x; 8854 8855 case SIGN_EXTEND: 8856 case ZERO_EXTEND: 8857 case ZERO_EXTRACT: 8858 case SIGN_EXTRACT: 8859 x = expand_compound_operation (x); 8860 if (GET_CODE (x) != code) 8861 return force_to_mode (x, mode, mask, next_select); 8862 break; 8863 8864 case TRUNCATE: 8865 /* Similarly for a truncate. */ 8866 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 8867 8868 case AND: 8869 /* If this is an AND with a constant, convert it into an AND 8870 whose constant is the AND of that constant with MASK. If it 8871 remains an AND of MASK, delete it since it is redundant. */ 8872 8873 if (CONST_INT_P (XEXP (x, 1))) 8874 { 8875 x = simplify_and_const_int (x, op_mode, XEXP (x, 0), 8876 mask & INTVAL (XEXP (x, 1))); 8877 xmode = op_mode; 8878 8879 /* If X is still an AND, see if it is an AND with a mask that 8880 is just some low-order bits. If so, and it is MASK, we don't 8881 need it. */ 8882 8883 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1)) 8884 && (INTVAL (XEXP (x, 1)) & GET_MODE_MASK (xmode)) == mask) 8885 x = XEXP (x, 0); 8886 8887 /* If it remains an AND, try making another AND with the bits 8888 in the mode mask that aren't in MASK turned on. If the 8889 constant in the AND is wide enough, this might make a 8890 cheaper constant. */ 8891 8892 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1)) 8893 && GET_MODE_MASK (xmode) != mask 8894 && HWI_COMPUTABLE_MODE_P (xmode)) 8895 { 8896 unsigned HOST_WIDE_INT cval 8897 = UINTVAL (XEXP (x, 1)) | (GET_MODE_MASK (xmode) & ~mask); 8898 rtx y; 8899 8900 y = simplify_gen_binary (AND, xmode, XEXP (x, 0), 8901 gen_int_mode (cval, xmode)); 8902 if (set_src_cost (y, xmode, optimize_this_for_speed_p) 8903 < set_src_cost (x, xmode, optimize_this_for_speed_p)) 8904 x = y; 8905 } 8906 8907 break; 8908 } 8909 8910 goto binop; 8911 8912 case PLUS: 8913 /* In (and (plus FOO C1) M), if M is a mask that just turns off 8914 low-order bits (as in an alignment operation) and FOO is already 8915 aligned to that boundary, mask C1 to that boundary as well. 8916 This may eliminate that PLUS and, later, the AND. */ 8917 8918 { 8919 unsigned int width = GET_MODE_PRECISION (mode); 8920 unsigned HOST_WIDE_INT smask = mask; 8921 8922 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative 8923 number, sign extend it. */ 8924 8925 if (width < HOST_BITS_PER_WIDE_INT 8926 && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0) 8927 smask |= HOST_WIDE_INT_M1U << width; 8928 8929 if (CONST_INT_P (XEXP (x, 1)) 8930 && pow2p_hwi (- smask) 8931 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 8932 && (INTVAL (XEXP (x, 1)) & ~smask) != 0) 8933 return force_to_mode (plus_constant (xmode, XEXP (x, 0), 8934 (INTVAL (XEXP (x, 1)) & smask)), 8935 mode, smask, next_select); 8936 } 8937 8938 /* fall through */ 8939 8940 case MULT: 8941 /* Substituting into the operands of a widening MULT is not likely to 8942 create RTL matching a machine insn. */ 8943 if (code == MULT 8944 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 8945 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) 8946 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND 8947 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND) 8948 && REG_P (XEXP (XEXP (x, 0), 0)) 8949 && REG_P (XEXP (XEXP (x, 1), 0))) 8950 return gen_lowpart_or_truncate (mode, x); 8951 8952 /* For PLUS, MINUS and MULT, we need any bits less significant than the 8953 most significant bit in MASK since carries from those bits will 8954 affect the bits we are interested in. */ 8955 mask = fuller_mask; 8956 goto binop; 8957 8958 case MINUS: 8959 /* If X is (minus C Y) where C's least set bit is larger than any bit 8960 in the mask, then we may replace with (neg Y). */ 8961 if (poly_int_rtx_p (XEXP (x, 0), &const_op0) 8962 && known_alignment (poly_uint64 (const_op0)) > mask) 8963 { 8964 x = simplify_gen_unary (NEG, xmode, XEXP (x, 1), xmode); 8965 return force_to_mode (x, mode, mask, next_select); 8966 } 8967 8968 /* Similarly, if C contains every bit in the fuller_mask, then we may 8969 replace with (not Y). */ 8970 if (CONST_INT_P (XEXP (x, 0)) 8971 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0)))) 8972 { 8973 x = simplify_gen_unary (NOT, xmode, XEXP (x, 1), xmode); 8974 return force_to_mode (x, mode, mask, next_select); 8975 } 8976 8977 mask = fuller_mask; 8978 goto binop; 8979 8980 case IOR: 8981 case XOR: 8982 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and 8983 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) 8984 operation which may be a bitfield extraction. Ensure that the 8985 constant we form is not wider than the mode of X. */ 8986 8987 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 8988 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 8989 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 8990 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 8991 && CONST_INT_P (XEXP (x, 1)) 8992 && ((INTVAL (XEXP (XEXP (x, 0), 1)) 8993 + floor_log2 (INTVAL (XEXP (x, 1)))) 8994 < GET_MODE_PRECISION (xmode)) 8995 && (UINTVAL (XEXP (x, 1)) 8996 & ~nonzero_bits (XEXP (x, 0), xmode)) == 0) 8997 { 8998 temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask) 8999 << INTVAL (XEXP (XEXP (x, 0), 1)), 9000 xmode); 9001 temp = simplify_gen_binary (GET_CODE (x), xmode, 9002 XEXP (XEXP (x, 0), 0), temp); 9003 x = simplify_gen_binary (LSHIFTRT, xmode, temp, 9004 XEXP (XEXP (x, 0), 1)); 9005 return force_to_mode (x, mode, mask, next_select); 9006 } 9007 9008 binop: 9009 /* For most binary operations, just propagate into the operation and 9010 change the mode if we have an operation of that mode. */ 9011 9012 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select); 9013 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select); 9014 9015 /* If we ended up truncating both operands, truncate the result of the 9016 operation instead. */ 9017 if (GET_CODE (op0) == TRUNCATE 9018 && GET_CODE (op1) == TRUNCATE) 9019 { 9020 op0 = XEXP (op0, 0); 9021 op1 = XEXP (op1, 0); 9022 } 9023 9024 op0 = gen_lowpart_or_truncate (op_mode, op0); 9025 op1 = gen_lowpart_or_truncate (op_mode, op1); 9026 9027 if (op_mode != xmode || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 9028 { 9029 x = simplify_gen_binary (code, op_mode, op0, op1); 9030 xmode = op_mode; 9031 } 9032 break; 9033 9034 case ASHIFT: 9035 /* For left shifts, do the same, but just for the first operand. 9036 However, we cannot do anything with shifts where we cannot 9037 guarantee that the counts are smaller than the size of the mode 9038 because such a count will have a different meaning in a 9039 wider mode. */ 9040 9041 if (! (CONST_INT_P (XEXP (x, 1)) 9042 && INTVAL (XEXP (x, 1)) >= 0 9043 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode)) 9044 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode 9045 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) 9046 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode)))) 9047 break; 9048 9049 /* If the shift count is a constant and we can do arithmetic in 9050 the mode of the shift, refine which bits we need. Otherwise, use the 9051 conservative form of the mask. */ 9052 if (CONST_INT_P (XEXP (x, 1)) 9053 && INTVAL (XEXP (x, 1)) >= 0 9054 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode) 9055 && HWI_COMPUTABLE_MODE_P (op_mode)) 9056 mask >>= INTVAL (XEXP (x, 1)); 9057 else 9058 mask = fuller_mask; 9059 9060 op0 = gen_lowpart_or_truncate (op_mode, 9061 force_to_mode (XEXP (x, 0), mode, 9062 mask, next_select)); 9063 9064 if (op_mode != xmode || op0 != XEXP (x, 0)) 9065 { 9066 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1)); 9067 xmode = op_mode; 9068 } 9069 break; 9070 9071 case LSHIFTRT: 9072 /* Here we can only do something if the shift count is a constant, 9073 this shift constant is valid for the host, and we can do arithmetic 9074 in OP_MODE. */ 9075 9076 if (CONST_INT_P (XEXP (x, 1)) 9077 && INTVAL (XEXP (x, 1)) >= 0 9078 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 9079 && HWI_COMPUTABLE_MODE_P (op_mode)) 9080 { 9081 rtx inner = XEXP (x, 0); 9082 unsigned HOST_WIDE_INT inner_mask; 9083 9084 /* Select the mask of the bits we need for the shift operand. */ 9085 inner_mask = mask << INTVAL (XEXP (x, 1)); 9086 9087 /* We can only change the mode of the shift if we can do arithmetic 9088 in the mode of the shift and INNER_MASK is no wider than the 9089 width of X's mode. */ 9090 if ((inner_mask & ~GET_MODE_MASK (xmode)) != 0) 9091 op_mode = xmode; 9092 9093 inner = force_to_mode (inner, op_mode, inner_mask, next_select); 9094 9095 if (xmode != op_mode || inner != XEXP (x, 0)) 9096 { 9097 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); 9098 xmode = op_mode; 9099 } 9100 } 9101 9102 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the 9103 shift and AND produces only copies of the sign bit (C2 is one less 9104 than a power of two), we can do this with just a shift. */ 9105 9106 if (GET_CODE (x) == LSHIFTRT 9107 && CONST_INT_P (XEXP (x, 1)) 9108 /* The shift puts one of the sign bit copies in the least significant 9109 bit. */ 9110 && ((INTVAL (XEXP (x, 1)) 9111 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) 9112 >= GET_MODE_PRECISION (xmode)) 9113 && pow2p_hwi (mask + 1) 9114 /* Number of bits left after the shift must be more than the mask 9115 needs. */ 9116 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) 9117 <= GET_MODE_PRECISION (xmode)) 9118 /* Must be more sign bit copies than the mask needs. */ 9119 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 9120 >= exact_log2 (mask + 1))) 9121 { 9122 int nbits = GET_MODE_PRECISION (xmode) - exact_log2 (mask + 1); 9123 x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0), 9124 gen_int_shift_amount (xmode, nbits)); 9125 } 9126 goto shiftrt; 9127 9128 case ASHIFTRT: 9129 /* If we are just looking for the sign bit, we don't need this shift at 9130 all, even if it has a variable count. */ 9131 if (val_signbit_p (xmode, mask)) 9132 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 9133 9134 /* If this is a shift by a constant, get a mask that contains those bits 9135 that are not copies of the sign bit. We then have two cases: If 9136 MASK only includes those bits, this can be a logical shift, which may 9137 allow simplifications. If MASK is a single-bit field not within 9138 those bits, we are requesting a copy of the sign bit and hence can 9139 shift the sign bit to the appropriate location. */ 9140 9141 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0 9142 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 9143 { 9144 unsigned HOST_WIDE_INT nonzero; 9145 int i; 9146 9147 /* If the considered data is wider than HOST_WIDE_INT, we can't 9148 represent a mask for all its bits in a single scalar. 9149 But we only care about the lower bits, so calculate these. */ 9150 9151 if (GET_MODE_PRECISION (xmode) > HOST_BITS_PER_WIDE_INT) 9152 { 9153 nonzero = HOST_WIDE_INT_M1U; 9154 9155 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 9156 is the number of bits a full-width mask would have set. 9157 We need only shift if these are fewer than nonzero can 9158 hold. If not, we must keep all bits set in nonzero. */ 9159 9160 if (GET_MODE_PRECISION (xmode) - INTVAL (XEXP (x, 1)) 9161 < HOST_BITS_PER_WIDE_INT) 9162 nonzero >>= INTVAL (XEXP (x, 1)) 9163 + HOST_BITS_PER_WIDE_INT 9164 - GET_MODE_PRECISION (xmode); 9165 } 9166 else 9167 { 9168 nonzero = GET_MODE_MASK (xmode); 9169 nonzero >>= INTVAL (XEXP (x, 1)); 9170 } 9171 9172 if ((mask & ~nonzero) == 0) 9173 { 9174 x = simplify_shift_const (NULL_RTX, LSHIFTRT, xmode, 9175 XEXP (x, 0), INTVAL (XEXP (x, 1))); 9176 if (GET_CODE (x) != ASHIFTRT) 9177 return force_to_mode (x, mode, mask, next_select); 9178 } 9179 9180 else if ((i = exact_log2 (mask)) >= 0) 9181 { 9182 x = simplify_shift_const 9183 (NULL_RTX, LSHIFTRT, xmode, XEXP (x, 0), 9184 GET_MODE_PRECISION (xmode) - 1 - i); 9185 9186 if (GET_CODE (x) != ASHIFTRT) 9187 return force_to_mode (x, mode, mask, next_select); 9188 } 9189 } 9190 9191 /* If MASK is 1, convert this to an LSHIFTRT. This can be done 9192 even if the shift count isn't a constant. */ 9193 if (mask == 1) 9194 x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0), XEXP (x, 1)); 9195 9196 shiftrt: 9197 9198 /* If this is a zero- or sign-extension operation that just affects bits 9199 we don't care about, remove it. Be sure the call above returned 9200 something that is still a shift. */ 9201 9202 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) 9203 && CONST_INT_P (XEXP (x, 1)) 9204 && INTVAL (XEXP (x, 1)) >= 0 9205 && (INTVAL (XEXP (x, 1)) 9206 <= GET_MODE_PRECISION (xmode) - (floor_log2 (mask) + 1)) 9207 && GET_CODE (XEXP (x, 0)) == ASHIFT 9208 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1)) 9209 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, 9210 next_select); 9211 9212 break; 9213 9214 case ROTATE: 9215 case ROTATERT: 9216 /* If the shift count is constant and we can do computations 9217 in the mode of X, compute where the bits we care about are. 9218 Otherwise, we can't do anything. Don't change the mode of 9219 the shift or propagate MODE into the shift, though. */ 9220 if (CONST_INT_P (XEXP (x, 1)) 9221 && INTVAL (XEXP (x, 1)) >= 0) 9222 { 9223 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, 9224 xmode, gen_int_mode (mask, xmode), 9225 XEXP (x, 1)); 9226 if (temp && CONST_INT_P (temp)) 9227 x = simplify_gen_binary (code, xmode, 9228 force_to_mode (XEXP (x, 0), xmode, 9229 INTVAL (temp), next_select), 9230 XEXP (x, 1)); 9231 } 9232 break; 9233 9234 case NEG: 9235 /* If we just want the low-order bit, the NEG isn't needed since it 9236 won't change the low-order bit. */ 9237 if (mask == 1) 9238 return force_to_mode (XEXP (x, 0), mode, mask, just_select); 9239 9240 /* We need any bits less significant than the most significant bit in 9241 MASK since carries from those bits will affect the bits we are 9242 interested in. */ 9243 mask = fuller_mask; 9244 goto unop; 9245 9246 case NOT: 9247 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the 9248 same as the XOR case above. Ensure that the constant we form is not 9249 wider than the mode of X. */ 9250 9251 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 9252 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 9253 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 9254 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) 9255 < GET_MODE_PRECISION (xmode)) 9256 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) 9257 { 9258 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), xmode); 9259 temp = simplify_gen_binary (XOR, xmode, XEXP (XEXP (x, 0), 0), temp); 9260 x = simplify_gen_binary (LSHIFTRT, xmode, 9261 temp, XEXP (XEXP (x, 0), 1)); 9262 9263 return force_to_mode (x, mode, mask, next_select); 9264 } 9265 9266 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must 9267 use the full mask inside the NOT. */ 9268 mask = fuller_mask; 9269 9270 unop: 9271 op0 = gen_lowpart_or_truncate (op_mode, 9272 force_to_mode (XEXP (x, 0), mode, mask, 9273 next_select)); 9274 if (op_mode != xmode || op0 != XEXP (x, 0)) 9275 { 9276 x = simplify_gen_unary (code, op_mode, op0, op_mode); 9277 xmode = op_mode; 9278 } 9279 break; 9280 9281 case NE: 9282 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included 9283 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, 9284 which is equal to STORE_FLAG_VALUE. */ 9285 if ((mask & ~STORE_FLAG_VALUE) == 0 9286 && XEXP (x, 1) == const0_rtx 9287 && GET_MODE (XEXP (x, 0)) == mode 9288 && pow2p_hwi (nonzero_bits (XEXP (x, 0), mode)) 9289 && (nonzero_bits (XEXP (x, 0), mode) 9290 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE)) 9291 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 9292 9293 break; 9294 9295 case IF_THEN_ELSE: 9296 /* We have no way of knowing if the IF_THEN_ELSE can itself be 9297 written in a narrower mode. We play it safe and do not do so. */ 9298 9299 op0 = gen_lowpart_or_truncate (xmode, 9300 force_to_mode (XEXP (x, 1), mode, 9301 mask, next_select)); 9302 op1 = gen_lowpart_or_truncate (xmode, 9303 force_to_mode (XEXP (x, 2), mode, 9304 mask, next_select)); 9305 if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2)) 9306 x = simplify_gen_ternary (IF_THEN_ELSE, xmode, 9307 GET_MODE (XEXP (x, 0)), XEXP (x, 0), 9308 op0, op1); 9309 break; 9310 9311 default: 9312 break; 9313 } 9314 9315 /* Ensure we return a value of the proper mode. */ 9316 return gen_lowpart_or_truncate (mode, x); 9317 } 9318 9319 /* Return nonzero if X is an expression that has one of two values depending on 9320 whether some other value is zero or nonzero. In that case, we return the 9321 value that is being tested, *PTRUE is set to the value if the rtx being 9322 returned has a nonzero value, and *PFALSE is set to the other alternative. 9323 9324 If we return zero, we set *PTRUE and *PFALSE to X. */ 9325 9326 static rtx 9327 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse) 9328 { 9329 machine_mode mode = GET_MODE (x); 9330 enum rtx_code code = GET_CODE (x); 9331 rtx cond0, cond1, true0, true1, false0, false1; 9332 unsigned HOST_WIDE_INT nz; 9333 scalar_int_mode int_mode; 9334 9335 /* If we are comparing a value against zero, we are done. */ 9336 if ((code == NE || code == EQ) 9337 && XEXP (x, 1) == const0_rtx) 9338 { 9339 *ptrue = (code == NE) ? const_true_rtx : const0_rtx; 9340 *pfalse = (code == NE) ? const0_rtx : const_true_rtx; 9341 return XEXP (x, 0); 9342 } 9343 9344 /* If this is a unary operation whose operand has one of two values, apply 9345 our opcode to compute those values. */ 9346 else if (UNARY_P (x) 9347 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) 9348 { 9349 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); 9350 *pfalse = simplify_gen_unary (code, mode, false0, 9351 GET_MODE (XEXP (x, 0))); 9352 return cond0; 9353 } 9354 9355 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would 9356 make can't possibly match and would suppress other optimizations. */ 9357 else if (code == COMPARE) 9358 ; 9359 9360 /* If this is a binary operation, see if either side has only one of two 9361 values. If either one does or if both do and they are conditional on 9362 the same value, compute the new true and false values. */ 9363 else if (BINARY_P (x)) 9364 { 9365 rtx op0 = XEXP (x, 0); 9366 rtx op1 = XEXP (x, 1); 9367 cond0 = if_then_else_cond (op0, &true0, &false0); 9368 cond1 = if_then_else_cond (op1, &true1, &false1); 9369 9370 if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)) 9371 && (REG_P (op0) || REG_P (op1))) 9372 { 9373 /* Try to enable a simplification by undoing work done by 9374 if_then_else_cond if it converted a REG into something more 9375 complex. */ 9376 if (REG_P (op0)) 9377 { 9378 cond0 = 0; 9379 true0 = false0 = op0; 9380 } 9381 else 9382 { 9383 cond1 = 0; 9384 true1 = false1 = op1; 9385 } 9386 } 9387 9388 if ((cond0 != 0 || cond1 != 0) 9389 && ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))) 9390 { 9391 /* If if_then_else_cond returned zero, then true/false are the 9392 same rtl. We must copy one of them to prevent invalid rtl 9393 sharing. */ 9394 if (cond0 == 0) 9395 true0 = copy_rtx (true0); 9396 else if (cond1 == 0) 9397 true1 = copy_rtx (true1); 9398 9399 if (COMPARISON_P (x)) 9400 { 9401 *ptrue = simplify_gen_relational (code, mode, VOIDmode, 9402 true0, true1); 9403 *pfalse = simplify_gen_relational (code, mode, VOIDmode, 9404 false0, false1); 9405 } 9406 else 9407 { 9408 *ptrue = simplify_gen_binary (code, mode, true0, true1); 9409 *pfalse = simplify_gen_binary (code, mode, false0, false1); 9410 } 9411 9412 return cond0 ? cond0 : cond1; 9413 } 9414 9415 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the 9416 operands is zero when the other is nonzero, and vice-versa, 9417 and STORE_FLAG_VALUE is 1 or -1. */ 9418 9419 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 9420 && (code == PLUS || code == IOR || code == XOR || code == MINUS 9421 || code == UMAX) 9422 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 9423 { 9424 rtx op0 = XEXP (XEXP (x, 0), 1); 9425 rtx op1 = XEXP (XEXP (x, 1), 1); 9426 9427 cond0 = XEXP (XEXP (x, 0), 0); 9428 cond1 = XEXP (XEXP (x, 1), 0); 9429 9430 if (COMPARISON_P (cond0) 9431 && COMPARISON_P (cond1) 9432 && SCALAR_INT_MODE_P (mode) 9433 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) 9434 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 9435 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 9436 || ((swap_condition (GET_CODE (cond0)) 9437 == reversed_comparison_code (cond1, NULL)) 9438 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 9439 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 9440 && ! side_effects_p (x)) 9441 { 9442 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx); 9443 *pfalse = simplify_gen_binary (MULT, mode, 9444 (code == MINUS 9445 ? simplify_gen_unary (NEG, mode, 9446 op1, mode) 9447 : op1), 9448 const_true_rtx); 9449 return cond0; 9450 } 9451 } 9452 9453 /* Similarly for MULT, AND and UMIN, except that for these the result 9454 is always zero. */ 9455 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 9456 && (code == MULT || code == AND || code == UMIN) 9457 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 9458 { 9459 cond0 = XEXP (XEXP (x, 0), 0); 9460 cond1 = XEXP (XEXP (x, 1), 0); 9461 9462 if (COMPARISON_P (cond0) 9463 && COMPARISON_P (cond1) 9464 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) 9465 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 9466 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 9467 || ((swap_condition (GET_CODE (cond0)) 9468 == reversed_comparison_code (cond1, NULL)) 9469 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 9470 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 9471 && ! side_effects_p (x)) 9472 { 9473 *ptrue = *pfalse = const0_rtx; 9474 return cond0; 9475 } 9476 } 9477 } 9478 9479 else if (code == IF_THEN_ELSE) 9480 { 9481 /* If we have IF_THEN_ELSE already, extract the condition and 9482 canonicalize it if it is NE or EQ. */ 9483 cond0 = XEXP (x, 0); 9484 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); 9485 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) 9486 return XEXP (cond0, 0); 9487 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) 9488 { 9489 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); 9490 return XEXP (cond0, 0); 9491 } 9492 else 9493 return cond0; 9494 } 9495 9496 /* If X is a SUBREG, we can narrow both the true and false values 9497 if the inner expression, if there is a condition. */ 9498 else if (code == SUBREG 9499 && (cond0 = if_then_else_cond (SUBREG_REG (x), &true0, 9500 &false0)) != 0) 9501 { 9502 true0 = simplify_gen_subreg (mode, true0, 9503 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 9504 false0 = simplify_gen_subreg (mode, false0, 9505 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 9506 if (true0 && false0) 9507 { 9508 *ptrue = true0; 9509 *pfalse = false0; 9510 return cond0; 9511 } 9512 } 9513 9514 /* If X is a constant, this isn't special and will cause confusions 9515 if we treat it as such. Likewise if it is equivalent to a constant. */ 9516 else if (CONSTANT_P (x) 9517 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) 9518 ; 9519 9520 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that 9521 will be least confusing to the rest of the compiler. */ 9522 else if (mode == BImode) 9523 { 9524 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; 9525 return x; 9526 } 9527 9528 /* If X is known to be either 0 or -1, those are the true and 9529 false values when testing X. */ 9530 else if (x == constm1_rtx || x == const0_rtx 9531 || (is_a <scalar_int_mode> (mode, &int_mode) 9532 && (num_sign_bit_copies (x, int_mode) 9533 == GET_MODE_PRECISION (int_mode)))) 9534 { 9535 *ptrue = constm1_rtx, *pfalse = const0_rtx; 9536 return x; 9537 } 9538 9539 /* Likewise for 0 or a single bit. */ 9540 else if (HWI_COMPUTABLE_MODE_P (mode) 9541 && pow2p_hwi (nz = nonzero_bits (x, mode))) 9542 { 9543 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx; 9544 return x; 9545 } 9546 9547 /* Otherwise fail; show no condition with true and false values the same. */ 9548 *ptrue = *pfalse = x; 9549 return 0; 9550 } 9551 9552 /* Return the value of expression X given the fact that condition COND 9553 is known to be true when applied to REG as its first operand and VAL 9554 as its second. X is known to not be shared and so can be modified in 9555 place. 9556 9557 We only handle the simplest cases, and specifically those cases that 9558 arise with IF_THEN_ELSE expressions. */ 9559 9560 static rtx 9561 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val) 9562 { 9563 enum rtx_code code = GET_CODE (x); 9564 const char *fmt; 9565 int i, j; 9566 9567 if (side_effects_p (x)) 9568 return x; 9569 9570 /* If either operand of the condition is a floating point value, 9571 then we have to avoid collapsing an EQ comparison. */ 9572 if (cond == EQ 9573 && rtx_equal_p (x, reg) 9574 && ! FLOAT_MODE_P (GET_MODE (x)) 9575 && ! FLOAT_MODE_P (GET_MODE (val))) 9576 return val; 9577 9578 if (cond == UNEQ && rtx_equal_p (x, reg)) 9579 return val; 9580 9581 /* If X is (abs REG) and we know something about REG's relationship 9582 with zero, we may be able to simplify this. */ 9583 9584 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) 9585 switch (cond) 9586 { 9587 case GE: case GT: case EQ: 9588 return XEXP (x, 0); 9589 case LT: case LE: 9590 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), 9591 XEXP (x, 0), 9592 GET_MODE (XEXP (x, 0))); 9593 default: 9594 break; 9595 } 9596 9597 /* The only other cases we handle are MIN, MAX, and comparisons if the 9598 operands are the same as REG and VAL. */ 9599 9600 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x)) 9601 { 9602 if (rtx_equal_p (XEXP (x, 0), val)) 9603 { 9604 std::swap (val, reg); 9605 cond = swap_condition (cond); 9606 } 9607 9608 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) 9609 { 9610 if (COMPARISON_P (x)) 9611 { 9612 if (comparison_dominates_p (cond, code)) 9613 return VECTOR_MODE_P (GET_MODE (x)) ? x : const_true_rtx; 9614 9615 code = reversed_comparison_code (x, NULL); 9616 if (code != UNKNOWN 9617 && comparison_dominates_p (cond, code)) 9618 return CONST0_RTX (GET_MODE (x)); 9619 else 9620 return x; 9621 } 9622 else if (code == SMAX || code == SMIN 9623 || code == UMIN || code == UMAX) 9624 { 9625 int unsignedp = (code == UMIN || code == UMAX); 9626 9627 /* Do not reverse the condition when it is NE or EQ. 9628 This is because we cannot conclude anything about 9629 the value of 'SMAX (x, y)' when x is not equal to y, 9630 but we can when x equals y. */ 9631 if ((code == SMAX || code == UMAX) 9632 && ! (cond == EQ || cond == NE)) 9633 cond = reverse_condition (cond); 9634 9635 switch (cond) 9636 { 9637 case GE: case GT: 9638 return unsignedp ? x : XEXP (x, 1); 9639 case LE: case LT: 9640 return unsignedp ? x : XEXP (x, 0); 9641 case GEU: case GTU: 9642 return unsignedp ? XEXP (x, 1) : x; 9643 case LEU: case LTU: 9644 return unsignedp ? XEXP (x, 0) : x; 9645 default: 9646 break; 9647 } 9648 } 9649 } 9650 } 9651 else if (code == SUBREG) 9652 { 9653 machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); 9654 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val); 9655 9656 if (SUBREG_REG (x) != r) 9657 { 9658 /* We must simplify subreg here, before we lose track of the 9659 original inner_mode. */ 9660 new_rtx = simplify_subreg (GET_MODE (x), r, 9661 inner_mode, SUBREG_BYTE (x)); 9662 if (new_rtx) 9663 return new_rtx; 9664 else 9665 SUBST (SUBREG_REG (x), r); 9666 } 9667 9668 return x; 9669 } 9670 /* We don't have to handle SIGN_EXTEND here, because even in the 9671 case of replacing something with a modeless CONST_INT, a 9672 CONST_INT is already (supposed to be) a valid sign extension for 9673 its narrower mode, which implies it's already properly 9674 sign-extended for the wider mode. Now, for ZERO_EXTEND, the 9675 story is different. */ 9676 else if (code == ZERO_EXTEND) 9677 { 9678 machine_mode inner_mode = GET_MODE (XEXP (x, 0)); 9679 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val); 9680 9681 if (XEXP (x, 0) != r) 9682 { 9683 /* We must simplify the zero_extend here, before we lose 9684 track of the original inner_mode. */ 9685 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), 9686 r, inner_mode); 9687 if (new_rtx) 9688 return new_rtx; 9689 else 9690 SUBST (XEXP (x, 0), r); 9691 } 9692 9693 return x; 9694 } 9695 9696 fmt = GET_RTX_FORMAT (code); 9697 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 9698 { 9699 if (fmt[i] == 'e') 9700 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); 9701 else if (fmt[i] == 'E') 9702 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 9703 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), 9704 cond, reg, val)); 9705 } 9706 9707 return x; 9708 } 9709 9710 /* See if X and Y are equal for the purposes of seeing if we can rewrite an 9711 assignment as a field assignment. */ 9712 9713 static int 9714 rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x) 9715 { 9716 if (widen_x && GET_MODE (x) != GET_MODE (y)) 9717 { 9718 if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (y))) 9719 return 0; 9720 if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN) 9721 return 0; 9722 x = adjust_address_nv (x, GET_MODE (y), 9723 byte_lowpart_offset (GET_MODE (y), 9724 GET_MODE (x))); 9725 } 9726 9727 if (x == y || rtx_equal_p (x, y)) 9728 return 1; 9729 9730 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) 9731 return 0; 9732 9733 /* Check for a paradoxical SUBREG of a MEM compared with the MEM. 9734 Note that all SUBREGs of MEM are paradoxical; otherwise they 9735 would have been rewritten. */ 9736 if (MEM_P (x) && GET_CODE (y) == SUBREG 9737 && MEM_P (SUBREG_REG (y)) 9738 && rtx_equal_p (SUBREG_REG (y), 9739 gen_lowpart (GET_MODE (SUBREG_REG (y)), x))) 9740 return 1; 9741 9742 if (MEM_P (y) && GET_CODE (x) == SUBREG 9743 && MEM_P (SUBREG_REG (x)) 9744 && rtx_equal_p (SUBREG_REG (x), 9745 gen_lowpart (GET_MODE (SUBREG_REG (x)), y))) 9746 return 1; 9747 9748 /* We used to see if get_last_value of X and Y were the same but that's 9749 not correct. In one direction, we'll cause the assignment to have 9750 the wrong destination and in the case, we'll import a register into this 9751 insn that might have already have been dead. So fail if none of the 9752 above cases are true. */ 9753 return 0; 9754 } 9755 9756 /* See if X, a SET operation, can be rewritten as a bit-field assignment. 9757 Return that assignment if so. 9758 9759 We only handle the most common cases. */ 9760 9761 static rtx 9762 make_field_assignment (rtx x) 9763 { 9764 rtx dest = SET_DEST (x); 9765 rtx src = SET_SRC (x); 9766 rtx assign; 9767 rtx rhs, lhs; 9768 HOST_WIDE_INT c1; 9769 HOST_WIDE_INT pos; 9770 unsigned HOST_WIDE_INT len; 9771 rtx other; 9772 9773 /* All the rules in this function are specific to scalar integers. */ 9774 scalar_int_mode mode; 9775 if (!is_a <scalar_int_mode> (GET_MODE (dest), &mode)) 9776 return x; 9777 9778 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is 9779 a clear of a one-bit field. We will have changed it to 9780 (and (rotate (const_int -2) POS) DEST), so check for that. Also check 9781 for a SUBREG. */ 9782 9783 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE 9784 && CONST_INT_P (XEXP (XEXP (src, 0), 0)) 9785 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 9786 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 9787 { 9788 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 9789 1, 1, 1, 0); 9790 if (assign != 0) 9791 return gen_rtx_SET (assign, const0_rtx); 9792 return x; 9793 } 9794 9795 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG 9796 && subreg_lowpart_p (XEXP (src, 0)) 9797 && partial_subreg_p (XEXP (src, 0)) 9798 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE 9799 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) 9800 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 9801 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 9802 { 9803 assign = make_extraction (VOIDmode, dest, 0, 9804 XEXP (SUBREG_REG (XEXP (src, 0)), 1), 9805 1, 1, 1, 0); 9806 if (assign != 0) 9807 return gen_rtx_SET (assign, const0_rtx); 9808 return x; 9809 } 9810 9811 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a 9812 one-bit field. */ 9813 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT 9814 && XEXP (XEXP (src, 0), 0) == const1_rtx 9815 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 9816 { 9817 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 9818 1, 1, 1, 0); 9819 if (assign != 0) 9820 return gen_rtx_SET (assign, const1_rtx); 9821 return x; 9822 } 9823 9824 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the 9825 SRC is an AND with all bits of that field set, then we can discard 9826 the AND. */ 9827 if (GET_CODE (dest) == ZERO_EXTRACT 9828 && CONST_INT_P (XEXP (dest, 1)) 9829 && GET_CODE (src) == AND 9830 && CONST_INT_P (XEXP (src, 1))) 9831 { 9832 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1)); 9833 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1)); 9834 unsigned HOST_WIDE_INT ze_mask; 9835 9836 if (width >= HOST_BITS_PER_WIDE_INT) 9837 ze_mask = -1; 9838 else 9839 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; 9840 9841 /* Complete overlap. We can remove the source AND. */ 9842 if ((and_mask & ze_mask) == ze_mask) 9843 return gen_rtx_SET (dest, XEXP (src, 0)); 9844 9845 /* Partial overlap. We can reduce the source AND. */ 9846 if ((and_mask & ze_mask) != and_mask) 9847 { 9848 src = gen_rtx_AND (mode, XEXP (src, 0), 9849 gen_int_mode (and_mask & ze_mask, mode)); 9850 return gen_rtx_SET (dest, src); 9851 } 9852 } 9853 9854 /* The other case we handle is assignments into a constant-position 9855 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents 9856 a mask that has all one bits except for a group of zero bits and 9857 OTHER is known to have zeros where C1 has ones, this is such an 9858 assignment. Compute the position and length from C1. Shift OTHER 9859 to the appropriate position, force it to the required mode, and 9860 make the extraction. Check for the AND in both operands. */ 9861 9862 /* One or more SUBREGs might obscure the constant-position field 9863 assignment. The first one we are likely to encounter is an outer 9864 narrowing SUBREG, which we can just strip for the purposes of 9865 identifying the constant-field assignment. */ 9866 scalar_int_mode src_mode = mode; 9867 if (GET_CODE (src) == SUBREG 9868 && subreg_lowpart_p (src) 9869 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode)) 9870 src = SUBREG_REG (src); 9871 9872 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) 9873 return x; 9874 9875 rhs = expand_compound_operation (XEXP (src, 0)); 9876 lhs = expand_compound_operation (XEXP (src, 1)); 9877 9878 if (GET_CODE (rhs) == AND 9879 && CONST_INT_P (XEXP (rhs, 1)) 9880 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) 9881 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 9882 /* The second SUBREG that might get in the way is a paradoxical 9883 SUBREG around the first operand of the AND. We want to 9884 pretend the operand is as wide as the destination here. We 9885 do this by adjusting the MEM to wider mode for the sole 9886 purpose of the call to rtx_equal_for_field_assignment_p. Also 9887 note this trick only works for MEMs. */ 9888 else if (GET_CODE (rhs) == AND 9889 && paradoxical_subreg_p (XEXP (rhs, 0)) 9890 && MEM_P (SUBREG_REG (XEXP (rhs, 0))) 9891 && CONST_INT_P (XEXP (rhs, 1)) 9892 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)), 9893 dest, true)) 9894 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 9895 else if (GET_CODE (lhs) == AND 9896 && CONST_INT_P (XEXP (lhs, 1)) 9897 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) 9898 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 9899 /* The second SUBREG that might get in the way is a paradoxical 9900 SUBREG around the first operand of the AND. We want to 9901 pretend the operand is as wide as the destination here. We 9902 do this by adjusting the MEM to wider mode for the sole 9903 purpose of the call to rtx_equal_for_field_assignment_p. Also 9904 note this trick only works for MEMs. */ 9905 else if (GET_CODE (lhs) == AND 9906 && paradoxical_subreg_p (XEXP (lhs, 0)) 9907 && MEM_P (SUBREG_REG (XEXP (lhs, 0))) 9908 && CONST_INT_P (XEXP (lhs, 1)) 9909 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)), 9910 dest, true)) 9911 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 9912 else 9913 return x; 9914 9915 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (mode), &len); 9916 if (pos < 0 9917 || pos + len > GET_MODE_PRECISION (mode) 9918 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT 9919 || (c1 & nonzero_bits (other, mode)) != 0) 9920 return x; 9921 9922 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); 9923 if (assign == 0) 9924 return x; 9925 9926 /* The mode to use for the source is the mode of the assignment, or of 9927 what is inside a possible STRICT_LOW_PART. */ 9928 machine_mode new_mode = (GET_CODE (assign) == STRICT_LOW_PART 9929 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); 9930 9931 /* Shift OTHER right POS places and make it the source, restricting it 9932 to the proper length and mode. */ 9933 9934 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT, 9935 src_mode, other, pos), 9936 dest); 9937 src = force_to_mode (src, new_mode, 9938 len >= HOST_BITS_PER_WIDE_INT 9939 ? HOST_WIDE_INT_M1U 9940 : (HOST_WIDE_INT_1U << len) - 1, 9941 0); 9942 9943 /* If SRC is masked by an AND that does not make a difference in 9944 the value being stored, strip it. */ 9945 if (GET_CODE (assign) == ZERO_EXTRACT 9946 && CONST_INT_P (XEXP (assign, 1)) 9947 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT 9948 && GET_CODE (src) == AND 9949 && CONST_INT_P (XEXP (src, 1)) 9950 && UINTVAL (XEXP (src, 1)) 9951 == (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1) 9952 src = XEXP (src, 0); 9953 9954 return gen_rtx_SET (assign, src); 9955 } 9956 9957 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) 9958 if so. */ 9959 9960 static rtx 9961 apply_distributive_law (rtx x) 9962 { 9963 enum rtx_code code = GET_CODE (x); 9964 enum rtx_code inner_code; 9965 rtx lhs, rhs, other; 9966 rtx tem; 9967 9968 /* Distributivity is not true for floating point as it can change the 9969 value. So we don't do it unless -funsafe-math-optimizations. */ 9970 if (FLOAT_MODE_P (GET_MODE (x)) 9971 && ! flag_unsafe_math_optimizations) 9972 return x; 9973 9974 /* The outer operation can only be one of the following: */ 9975 if (code != IOR && code != AND && code != XOR 9976 && code != PLUS && code != MINUS) 9977 return x; 9978 9979 lhs = XEXP (x, 0); 9980 rhs = XEXP (x, 1); 9981 9982 /* If either operand is a primitive we can't do anything, so get out 9983 fast. */ 9984 if (OBJECT_P (lhs) || OBJECT_P (rhs)) 9985 return x; 9986 9987 lhs = expand_compound_operation (lhs); 9988 rhs = expand_compound_operation (rhs); 9989 inner_code = GET_CODE (lhs); 9990 if (inner_code != GET_CODE (rhs)) 9991 return x; 9992 9993 /* See if the inner and outer operations distribute. */ 9994 switch (inner_code) 9995 { 9996 case LSHIFTRT: 9997 case ASHIFTRT: 9998 case AND: 9999 case IOR: 10000 /* These all distribute except over PLUS. */ 10001 if (code == PLUS || code == MINUS) 10002 return x; 10003 break; 10004 10005 case MULT: 10006 if (code != PLUS && code != MINUS) 10007 return x; 10008 break; 10009 10010 case ASHIFT: 10011 /* This is also a multiply, so it distributes over everything. */ 10012 break; 10013 10014 /* This used to handle SUBREG, but this turned out to be counter- 10015 productive, since (subreg (op ...)) usually is not handled by 10016 insn patterns, and this "optimization" therefore transformed 10017 recognizable patterns into unrecognizable ones. Therefore the 10018 SUBREG case was removed from here. 10019 10020 It is possible that distributing SUBREG over arithmetic operations 10021 leads to an intermediate result than can then be optimized further, 10022 e.g. by moving the outer SUBREG to the other side of a SET as done 10023 in simplify_set. This seems to have been the original intent of 10024 handling SUBREGs here. 10025 10026 However, with current GCC this does not appear to actually happen, 10027 at least on major platforms. If some case is found where removing 10028 the SUBREG case here prevents follow-on optimizations, distributing 10029 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */ 10030 10031 default: 10032 return x; 10033 } 10034 10035 /* Set LHS and RHS to the inner operands (A and B in the example 10036 above) and set OTHER to the common operand (C in the example). 10037 There is only one way to do this unless the inner operation is 10038 commutative. */ 10039 if (COMMUTATIVE_ARITH_P (lhs) 10040 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) 10041 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); 10042 else if (COMMUTATIVE_ARITH_P (lhs) 10043 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) 10044 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); 10045 else if (COMMUTATIVE_ARITH_P (lhs) 10046 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) 10047 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); 10048 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) 10049 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); 10050 else 10051 return x; 10052 10053 /* Form the new inner operation, seeing if it simplifies first. */ 10054 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs); 10055 10056 /* There is one exception to the general way of distributing: 10057 (a | c) ^ (b | c) -> (a ^ b) & ~c */ 10058 if (code == XOR && inner_code == IOR) 10059 { 10060 inner_code = AND; 10061 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); 10062 } 10063 10064 /* We may be able to continuing distributing the result, so call 10065 ourselves recursively on the inner operation before forming the 10066 outer operation, which we return. */ 10067 return simplify_gen_binary (inner_code, GET_MODE (x), 10068 apply_distributive_law (tem), other); 10069 } 10070 10071 /* See if X is of the form (* (+ A B) C), and if so convert to 10072 (+ (* A C) (* B C)) and try to simplify. 10073 10074 Most of the time, this results in no change. However, if some of 10075 the operands are the same or inverses of each other, simplifications 10076 will result. 10077 10078 For example, (and (ior A B) (not B)) can occur as the result of 10079 expanding a bit field assignment. When we apply the distributive 10080 law to this, we get (ior (and (A (not B))) (and (B (not B)))), 10081 which then simplifies to (and (A (not B))). 10082 10083 Note that no checks happen on the validity of applying the inverse 10084 distributive law. This is pointless since we can do it in the 10085 few places where this routine is called. 10086 10087 N is the index of the term that is decomposed (the arithmetic operation, 10088 i.e. (+ A B) in the first example above). !N is the index of the term that 10089 is distributed, i.e. of C in the first example above. */ 10090 static rtx 10091 distribute_and_simplify_rtx (rtx x, int n) 10092 { 10093 machine_mode mode; 10094 enum rtx_code outer_code, inner_code; 10095 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp; 10096 10097 /* Distributivity is not true for floating point as it can change the 10098 value. So we don't do it unless -funsafe-math-optimizations. */ 10099 if (FLOAT_MODE_P (GET_MODE (x)) 10100 && ! flag_unsafe_math_optimizations) 10101 return NULL_RTX; 10102 10103 decomposed = XEXP (x, n); 10104 if (!ARITHMETIC_P (decomposed)) 10105 return NULL_RTX; 10106 10107 mode = GET_MODE (x); 10108 outer_code = GET_CODE (x); 10109 distributed = XEXP (x, !n); 10110 10111 inner_code = GET_CODE (decomposed); 10112 inner_op0 = XEXP (decomposed, 0); 10113 inner_op1 = XEXP (decomposed, 1); 10114 10115 /* Special case (and (xor B C) (not A)), which is equivalent to 10116 (xor (ior A B) (ior A C)) */ 10117 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT) 10118 { 10119 distributed = XEXP (distributed, 0); 10120 outer_code = IOR; 10121 } 10122 10123 if (n == 0) 10124 { 10125 /* Distribute the second term. */ 10126 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed); 10127 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed); 10128 } 10129 else 10130 { 10131 /* Distribute the first term. */ 10132 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0); 10133 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1); 10134 } 10135 10136 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode, 10137 new_op0, new_op1)); 10138 if (GET_CODE (tmp) != outer_code 10139 && (set_src_cost (tmp, mode, optimize_this_for_speed_p) 10140 < set_src_cost (x, mode, optimize_this_for_speed_p))) 10141 return tmp; 10142 10143 return NULL_RTX; 10144 } 10145 10146 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done 10147 in MODE. Return an equivalent form, if different from (and VAROP 10148 (const_int CONSTOP)). Otherwise, return NULL_RTX. */ 10149 10150 static rtx 10151 simplify_and_const_int_1 (scalar_int_mode mode, rtx varop, 10152 unsigned HOST_WIDE_INT constop) 10153 { 10154 unsigned HOST_WIDE_INT nonzero; 10155 unsigned HOST_WIDE_INT orig_constop; 10156 rtx orig_varop; 10157 int i; 10158 10159 orig_varop = varop; 10160 orig_constop = constop; 10161 if (GET_CODE (varop) == CLOBBER) 10162 return NULL_RTX; 10163 10164 /* Simplify VAROP knowing that we will be only looking at some of the 10165 bits in it. 10166 10167 Note by passing in CONSTOP, we guarantee that the bits not set in 10168 CONSTOP are not significant and will never be examined. We must 10169 ensure that is the case by explicitly masking out those bits 10170 before returning. */ 10171 varop = force_to_mode (varop, mode, constop, 0); 10172 10173 /* If VAROP is a CLOBBER, we will fail so return it. */ 10174 if (GET_CODE (varop) == CLOBBER) 10175 return varop; 10176 10177 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP 10178 to VAROP and return the new constant. */ 10179 if (CONST_INT_P (varop)) 10180 return gen_int_mode (INTVAL (varop) & constop, mode); 10181 10182 /* See what bits may be nonzero in VAROP. Unlike the general case of 10183 a call to nonzero_bits, here we don't care about bits outside 10184 MODE. */ 10185 10186 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); 10187 10188 /* Turn off all bits in the constant that are known to already be zero. 10189 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS 10190 which is tested below. */ 10191 10192 constop &= nonzero; 10193 10194 /* If we don't have any bits left, return zero. */ 10195 if (constop == 0 && !side_effects_p (varop)) 10196 return const0_rtx; 10197 10198 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is 10199 a power of two, we can replace this with an ASHIFT. */ 10200 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 10201 && (i = exact_log2 (constop)) >= 0) 10202 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); 10203 10204 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR 10205 or XOR, then try to apply the distributive law. This may eliminate 10206 operations if either branch can be simplified because of the AND. 10207 It may also make some cases more complex, but those cases probably 10208 won't match a pattern either with or without this. */ 10209 10210 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) 10211 { 10212 scalar_int_mode varop_mode = as_a <scalar_int_mode> (GET_MODE (varop)); 10213 return 10214 gen_lowpart 10215 (mode, 10216 apply_distributive_law 10217 (simplify_gen_binary (GET_CODE (varop), varop_mode, 10218 simplify_and_const_int (NULL_RTX, varop_mode, 10219 XEXP (varop, 0), 10220 constop), 10221 simplify_and_const_int (NULL_RTX, varop_mode, 10222 XEXP (varop, 1), 10223 constop)))); 10224 } 10225 10226 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute 10227 the AND and see if one of the operands simplifies to zero. If so, we 10228 may eliminate it. */ 10229 10230 if (GET_CODE (varop) == PLUS 10231 && pow2p_hwi (constop + 1)) 10232 { 10233 rtx o0, o1; 10234 10235 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); 10236 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); 10237 if (o0 == const0_rtx) 10238 return o1; 10239 if (o1 == const0_rtx) 10240 return o0; 10241 } 10242 10243 /* Make a SUBREG if necessary. If we can't make it, fail. */ 10244 varop = gen_lowpart (mode, varop); 10245 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) 10246 return NULL_RTX; 10247 10248 /* If we are only masking insignificant bits, return VAROP. */ 10249 if (constop == nonzero) 10250 return varop; 10251 10252 if (varop == orig_varop && constop == orig_constop) 10253 return NULL_RTX; 10254 10255 /* Otherwise, return an AND. */ 10256 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode)); 10257 } 10258 10259 10260 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done 10261 in MODE. 10262 10263 Return an equivalent form, if different from X. Otherwise, return X. If 10264 X is zero, we are to always construct the equivalent form. */ 10265 10266 static rtx 10267 simplify_and_const_int (rtx x, scalar_int_mode mode, rtx varop, 10268 unsigned HOST_WIDE_INT constop) 10269 { 10270 rtx tem = simplify_and_const_int_1 (mode, varop, constop); 10271 if (tem) 10272 return tem; 10273 10274 if (!x) 10275 x = simplify_gen_binary (AND, GET_MODE (varop), varop, 10276 gen_int_mode (constop, mode)); 10277 if (GET_MODE (x) != mode) 10278 x = gen_lowpart (mode, x); 10279 return x; 10280 } 10281 10282 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero. 10283 We don't care about bits outside of those defined in MODE. 10284 We DO care about all the bits in MODE, even if XMODE is smaller than MODE. 10285 10286 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 10287 a shift, AND, or zero_extract, we can do better. */ 10288 10289 static rtx 10290 reg_nonzero_bits_for_combine (const_rtx x, scalar_int_mode xmode, 10291 scalar_int_mode mode, 10292 unsigned HOST_WIDE_INT *nonzero) 10293 { 10294 rtx tem; 10295 reg_stat_type *rsp; 10296 10297 /* If X is a register whose nonzero bits value is current, use it. 10298 Otherwise, if X is a register whose value we can find, use that 10299 value. Otherwise, use the previously-computed global nonzero bits 10300 for this register. */ 10301 10302 rsp = ®_stat[REGNO (x)]; 10303 if (rsp->last_set_value != 0 10304 && (rsp->last_set_mode == mode 10305 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 10306 && GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT 10307 && GET_MODE_CLASS (mode) == MODE_INT)) 10308 && ((rsp->last_set_label >= label_tick_ebb_start 10309 && rsp->last_set_label < label_tick) 10310 || (rsp->last_set_label == label_tick 10311 && DF_INSN_LUID (rsp->last_set) < subst_low_luid) 10312 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 10313 && REGNO (x) < reg_n_sets_max 10314 && REG_N_SETS (REGNO (x)) == 1 10315 && !REGNO_REG_SET_P 10316 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), 10317 REGNO (x))))) 10318 { 10319 /* Note that, even if the precision of last_set_mode is lower than that 10320 of mode, record_value_for_reg invoked nonzero_bits on the register 10321 with nonzero_bits_mode (because last_set_mode is necessarily integral 10322 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode 10323 are all valid, hence in mode too since nonzero_bits_mode is defined 10324 to the largest HWI_COMPUTABLE_MODE_P mode. */ 10325 *nonzero &= rsp->last_set_nonzero_bits; 10326 return NULL; 10327 } 10328 10329 tem = get_last_value (x); 10330 if (tem) 10331 { 10332 if (SHORT_IMMEDIATES_SIGN_EXTEND) 10333 tem = sign_extend_short_imm (tem, xmode, GET_MODE_PRECISION (mode)); 10334 10335 return tem; 10336 } 10337 10338 if (nonzero_sign_valid && rsp->nonzero_bits) 10339 { 10340 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits; 10341 10342 if (GET_MODE_PRECISION (xmode) < GET_MODE_PRECISION (mode)) 10343 /* We don't know anything about the upper bits. */ 10344 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (xmode); 10345 10346 *nonzero &= mask; 10347 } 10348 10349 return NULL; 10350 } 10351 10352 /* Given a reg X of mode XMODE, return the number of bits at the high-order 10353 end of X that are known to be equal to the sign bit. X will be used 10354 in mode MODE; the returned value will always be between 1 and the 10355 number of bits in MODE. */ 10356 10357 static rtx 10358 reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode, 10359 scalar_int_mode mode, 10360 unsigned int *result) 10361 { 10362 rtx tem; 10363 reg_stat_type *rsp; 10364 10365 rsp = ®_stat[REGNO (x)]; 10366 if (rsp->last_set_value != 0 10367 && rsp->last_set_mode == mode 10368 && ((rsp->last_set_label >= label_tick_ebb_start 10369 && rsp->last_set_label < label_tick) 10370 || (rsp->last_set_label == label_tick 10371 && DF_INSN_LUID (rsp->last_set) < subst_low_luid) 10372 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 10373 && REGNO (x) < reg_n_sets_max 10374 && REG_N_SETS (REGNO (x)) == 1 10375 && !REGNO_REG_SET_P 10376 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), 10377 REGNO (x))))) 10378 { 10379 *result = rsp->last_set_sign_bit_copies; 10380 return NULL; 10381 } 10382 10383 tem = get_last_value (x); 10384 if (tem != 0) 10385 return tem; 10386 10387 if (nonzero_sign_valid && rsp->sign_bit_copies != 0 10388 && GET_MODE_PRECISION (xmode) == GET_MODE_PRECISION (mode)) 10389 *result = rsp->sign_bit_copies; 10390 10391 return NULL; 10392 } 10393 10394 /* Return the number of "extended" bits there are in X, when interpreted 10395 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For 10396 unsigned quantities, this is the number of high-order zero bits. 10397 For signed quantities, this is the number of copies of the sign bit 10398 minus 1. In both case, this function returns the number of "spare" 10399 bits. For example, if two quantities for which this function returns 10400 at least 1 are added, the addition is known not to overflow. 10401 10402 This function will always return 0 unless called during combine, which 10403 implies that it must be called from a define_split. */ 10404 10405 unsigned int 10406 extended_count (const_rtx x, machine_mode mode, int unsignedp) 10407 { 10408 if (nonzero_sign_valid == 0) 10409 return 0; 10410 10411 scalar_int_mode int_mode; 10412 return (unsignedp 10413 ? (is_a <scalar_int_mode> (mode, &int_mode) 10414 && HWI_COMPUTABLE_MODE_P (int_mode) 10415 ? (unsigned int) (GET_MODE_PRECISION (int_mode) - 1 10416 - floor_log2 (nonzero_bits (x, int_mode))) 10417 : 0) 10418 : num_sign_bit_copies (x, mode) - 1); 10419 } 10420 10421 /* This function is called from `simplify_shift_const' to merge two 10422 outer operations. Specifically, we have already found that we need 10423 to perform operation *POP0 with constant *PCONST0 at the outermost 10424 position. We would now like to also perform OP1 with constant CONST1 10425 (with *POP0 being done last). 10426 10427 Return 1 if we can do the operation and update *POP0 and *PCONST0 with 10428 the resulting operation. *PCOMP_P is set to 1 if we would need to 10429 complement the innermost operand, otherwise it is unchanged. 10430 10431 MODE is the mode in which the operation will be done. No bits outside 10432 the width of this mode matter. It is assumed that the width of this mode 10433 is smaller than or equal to HOST_BITS_PER_WIDE_INT. 10434 10435 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, 10436 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper 10437 result is simply *PCONST0. 10438 10439 If the resulting operation cannot be expressed as one operation, we 10440 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ 10441 10442 static int 10443 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p) 10444 { 10445 enum rtx_code op0 = *pop0; 10446 HOST_WIDE_INT const0 = *pconst0; 10447 10448 const0 &= GET_MODE_MASK (mode); 10449 const1 &= GET_MODE_MASK (mode); 10450 10451 /* If OP0 is an AND, clear unimportant bits in CONST1. */ 10452 if (op0 == AND) 10453 const1 &= const0; 10454 10455 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or 10456 if OP0 is SET. */ 10457 10458 if (op1 == UNKNOWN || op0 == SET) 10459 return 1; 10460 10461 else if (op0 == UNKNOWN) 10462 op0 = op1, const0 = const1; 10463 10464 else if (op0 == op1) 10465 { 10466 switch (op0) 10467 { 10468 case AND: 10469 const0 &= const1; 10470 break; 10471 case IOR: 10472 const0 |= const1; 10473 break; 10474 case XOR: 10475 const0 ^= const1; 10476 break; 10477 case PLUS: 10478 const0 += const1; 10479 break; 10480 case NEG: 10481 op0 = UNKNOWN; 10482 break; 10483 default: 10484 break; 10485 } 10486 } 10487 10488 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ 10489 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) 10490 return 0; 10491 10492 /* If the two constants aren't the same, we can't do anything. The 10493 remaining six cases can all be done. */ 10494 else if (const0 != const1) 10495 return 0; 10496 10497 else 10498 switch (op0) 10499 { 10500 case IOR: 10501 if (op1 == AND) 10502 /* (a & b) | b == b */ 10503 op0 = SET; 10504 else /* op1 == XOR */ 10505 /* (a ^ b) | b == a | b */ 10506 {;} 10507 break; 10508 10509 case XOR: 10510 if (op1 == AND) 10511 /* (a & b) ^ b == (~a) & b */ 10512 op0 = AND, *pcomp_p = 1; 10513 else /* op1 == IOR */ 10514 /* (a | b) ^ b == a & ~b */ 10515 op0 = AND, const0 = ~const0; 10516 break; 10517 10518 case AND: 10519 if (op1 == IOR) 10520 /* (a | b) & b == b */ 10521 op0 = SET; 10522 else /* op1 == XOR */ 10523 /* (a ^ b) & b) == (~a) & b */ 10524 *pcomp_p = 1; 10525 break; 10526 default: 10527 break; 10528 } 10529 10530 /* Check for NO-OP cases. */ 10531 const0 &= GET_MODE_MASK (mode); 10532 if (const0 == 0 10533 && (op0 == IOR || op0 == XOR || op0 == PLUS)) 10534 op0 = UNKNOWN; 10535 else if (const0 == 0 && op0 == AND) 10536 op0 = SET; 10537 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) 10538 && op0 == AND) 10539 op0 = UNKNOWN; 10540 10541 *pop0 = op0; 10542 10543 /* ??? Slightly redundant with the above mask, but not entirely. 10544 Moving this above means we'd have to sign-extend the mode mask 10545 for the final test. */ 10546 if (op0 != UNKNOWN && op0 != NEG) 10547 *pconst0 = trunc_int_for_mode (const0, mode); 10548 10549 return 1; 10550 } 10551 10552 /* A helper to simplify_shift_const_1 to determine the mode we can perform 10553 the shift in. The original shift operation CODE is performed on OP in 10554 ORIG_MODE. Return the wider mode MODE if we can perform the operation 10555 in that mode. Return ORIG_MODE otherwise. We can also assume that the 10556 result of the shift is subject to operation OUTER_CODE with operand 10557 OUTER_CONST. */ 10558 10559 static scalar_int_mode 10560 try_widen_shift_mode (enum rtx_code code, rtx op, int count, 10561 scalar_int_mode orig_mode, scalar_int_mode mode, 10562 enum rtx_code outer_code, HOST_WIDE_INT outer_const) 10563 { 10564 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode)); 10565 10566 /* In general we can't perform in wider mode for right shift and rotate. */ 10567 switch (code) 10568 { 10569 case ASHIFTRT: 10570 /* We can still widen if the bits brought in from the left are identical 10571 to the sign bit of ORIG_MODE. */ 10572 if (num_sign_bit_copies (op, mode) 10573 > (unsigned) (GET_MODE_PRECISION (mode) 10574 - GET_MODE_PRECISION (orig_mode))) 10575 return mode; 10576 return orig_mode; 10577 10578 case LSHIFTRT: 10579 /* Similarly here but with zero bits. */ 10580 if (HWI_COMPUTABLE_MODE_P (mode) 10581 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0) 10582 return mode; 10583 10584 /* We can also widen if the bits brought in will be masked off. This 10585 operation is performed in ORIG_MODE. */ 10586 if (outer_code == AND) 10587 { 10588 int care_bits = low_bitmask_len (orig_mode, outer_const); 10589 10590 if (care_bits >= 0 10591 && GET_MODE_PRECISION (orig_mode) - care_bits >= count) 10592 return mode; 10593 } 10594 /* fall through */ 10595 10596 case ROTATE: 10597 return orig_mode; 10598 10599 case ROTATERT: 10600 gcc_unreachable (); 10601 10602 default: 10603 return mode; 10604 } 10605 } 10606 10607 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind 10608 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX 10609 if we cannot simplify it. Otherwise, return a simplified value. 10610 10611 The shift is normally computed in the widest mode we find in VAROP, as 10612 long as it isn't a different number of words than RESULT_MODE. Exceptions 10613 are ASHIFTRT and ROTATE, which are always done in their original mode. */ 10614 10615 static rtx 10616 simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode, 10617 rtx varop, int orig_count) 10618 { 10619 enum rtx_code orig_code = code; 10620 rtx orig_varop = varop; 10621 int count, log2; 10622 machine_mode mode = result_mode; 10623 machine_mode shift_mode; 10624 scalar_int_mode tmode, inner_mode, int_mode, int_varop_mode, int_result_mode; 10625 /* We form (outer_op (code varop count) (outer_const)). */ 10626 enum rtx_code outer_op = UNKNOWN; 10627 HOST_WIDE_INT outer_const = 0; 10628 int complement_p = 0; 10629 rtx new_rtx, x; 10630 10631 /* Make sure and truncate the "natural" shift on the way in. We don't 10632 want to do this inside the loop as it makes it more difficult to 10633 combine shifts. */ 10634 if (SHIFT_COUNT_TRUNCATED) 10635 orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1; 10636 10637 /* If we were given an invalid count, don't do anything except exactly 10638 what was requested. */ 10639 10640 if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode)) 10641 return NULL_RTX; 10642 10643 count = orig_count; 10644 10645 /* Unless one of the branches of the `if' in this loop does a `continue', 10646 we will `break' the loop after the `if'. */ 10647 10648 while (count != 0) 10649 { 10650 /* If we have an operand of (clobber (const_int 0)), fail. */ 10651 if (GET_CODE (varop) == CLOBBER) 10652 return NULL_RTX; 10653 10654 /* Convert ROTATERT to ROTATE. */ 10655 if (code == ROTATERT) 10656 { 10657 unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode); 10658 code = ROTATE; 10659 count = bitsize - count; 10660 } 10661 10662 shift_mode = result_mode; 10663 if (shift_mode != mode) 10664 { 10665 /* We only change the modes of scalar shifts. */ 10666 int_mode = as_a <scalar_int_mode> (mode); 10667 int_result_mode = as_a <scalar_int_mode> (result_mode); 10668 shift_mode = try_widen_shift_mode (code, varop, count, 10669 int_result_mode, int_mode, 10670 outer_op, outer_const); 10671 } 10672 10673 scalar_int_mode shift_unit_mode 10674 = as_a <scalar_int_mode> (GET_MODE_INNER (shift_mode)); 10675 10676 /* Handle cases where the count is greater than the size of the mode 10677 minus 1. For ASHIFT, use the size minus one as the count (this can 10678 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, 10679 take the count modulo the size. For other shifts, the result is 10680 zero. 10681 10682 Since these shifts are being produced by the compiler by combining 10683 multiple operations, each of which are defined, we know what the 10684 result is supposed to be. */ 10685 10686 if (count > (GET_MODE_PRECISION (shift_unit_mode) - 1)) 10687 { 10688 if (code == ASHIFTRT) 10689 count = GET_MODE_PRECISION (shift_unit_mode) - 1; 10690 else if (code == ROTATE || code == ROTATERT) 10691 count %= GET_MODE_PRECISION (shift_unit_mode); 10692 else 10693 { 10694 /* We can't simply return zero because there may be an 10695 outer op. */ 10696 varop = const0_rtx; 10697 count = 0; 10698 break; 10699 } 10700 } 10701 10702 /* If we discovered we had to complement VAROP, leave. Making a NOT 10703 here would cause an infinite loop. */ 10704 if (complement_p) 10705 break; 10706 10707 if (shift_mode == shift_unit_mode) 10708 { 10709 /* An arithmetic right shift of a quantity known to be -1 or 0 10710 is a no-op. */ 10711 if (code == ASHIFTRT 10712 && (num_sign_bit_copies (varop, shift_unit_mode) 10713 == GET_MODE_PRECISION (shift_unit_mode))) 10714 { 10715 count = 0; 10716 break; 10717 } 10718 10719 /* If we are doing an arithmetic right shift and discarding all but 10720 the sign bit copies, this is equivalent to doing a shift by the 10721 bitsize minus one. Convert it into that shift because it will 10722 often allow other simplifications. */ 10723 10724 if (code == ASHIFTRT 10725 && (count + num_sign_bit_copies (varop, shift_unit_mode) 10726 >= GET_MODE_PRECISION (shift_unit_mode))) 10727 count = GET_MODE_PRECISION (shift_unit_mode) - 1; 10728 10729 /* We simplify the tests below and elsewhere by converting 10730 ASHIFTRT to LSHIFTRT if we know the sign bit is clear. 10731 `make_compound_operation' will convert it to an ASHIFTRT for 10732 those machines (such as VAX) that don't have an LSHIFTRT. */ 10733 if (code == ASHIFTRT 10734 && HWI_COMPUTABLE_MODE_P (shift_unit_mode) 10735 && val_signbit_known_clear_p (shift_unit_mode, 10736 nonzero_bits (varop, 10737 shift_unit_mode))) 10738 code = LSHIFTRT; 10739 10740 if (((code == LSHIFTRT 10741 && HWI_COMPUTABLE_MODE_P (shift_unit_mode) 10742 && !(nonzero_bits (varop, shift_unit_mode) >> count)) 10743 || (code == ASHIFT 10744 && HWI_COMPUTABLE_MODE_P (shift_unit_mode) 10745 && !((nonzero_bits (varop, shift_unit_mode) << count) 10746 & GET_MODE_MASK (shift_unit_mode)))) 10747 && !side_effects_p (varop)) 10748 varop = const0_rtx; 10749 } 10750 10751 switch (GET_CODE (varop)) 10752 { 10753 case SIGN_EXTEND: 10754 case ZERO_EXTEND: 10755 case SIGN_EXTRACT: 10756 case ZERO_EXTRACT: 10757 new_rtx = expand_compound_operation (varop); 10758 if (new_rtx != varop) 10759 { 10760 varop = new_rtx; 10761 continue; 10762 } 10763 break; 10764 10765 case MEM: 10766 /* The following rules apply only to scalars. */ 10767 if (shift_mode != shift_unit_mode) 10768 break; 10769 int_mode = as_a <scalar_int_mode> (mode); 10770 10771 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH 10772 minus the width of a smaller mode, we can do this with a 10773 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ 10774 if ((code == ASHIFTRT || code == LSHIFTRT) 10775 && ! mode_dependent_address_p (XEXP (varop, 0), 10776 MEM_ADDR_SPACE (varop)) 10777 && ! MEM_VOLATILE_P (varop) 10778 && (int_mode_for_size (GET_MODE_BITSIZE (int_mode) - count, 1) 10779 .exists (&tmode))) 10780 { 10781 new_rtx = adjust_address_nv (varop, tmode, 10782 BYTES_BIG_ENDIAN ? 0 10783 : count / BITS_PER_UNIT); 10784 10785 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND 10786 : ZERO_EXTEND, int_mode, new_rtx); 10787 count = 0; 10788 continue; 10789 } 10790 break; 10791 10792 case SUBREG: 10793 /* The following rules apply only to scalars. */ 10794 if (shift_mode != shift_unit_mode) 10795 break; 10796 int_mode = as_a <scalar_int_mode> (mode); 10797 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop)); 10798 10799 /* If VAROP is a SUBREG, strip it as long as the inner operand has 10800 the same number of words as what we've seen so far. Then store 10801 the widest mode in MODE. */ 10802 if (subreg_lowpart_p (varop) 10803 && is_int_mode (GET_MODE (SUBREG_REG (varop)), &inner_mode) 10804 && GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_varop_mode) 10805 && (CEIL (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD) 10806 == CEIL (GET_MODE_SIZE (int_mode), UNITS_PER_WORD)) 10807 && GET_MODE_CLASS (int_varop_mode) == MODE_INT) 10808 { 10809 varop = SUBREG_REG (varop); 10810 if (GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_mode)) 10811 mode = inner_mode; 10812 continue; 10813 } 10814 break; 10815 10816 case MULT: 10817 /* Some machines use MULT instead of ASHIFT because MULT 10818 is cheaper. But it is still better on those machines to 10819 merge two shifts into one. */ 10820 if (CONST_INT_P (XEXP (varop, 1)) 10821 && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0) 10822 { 10823 rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2); 10824 varop = simplify_gen_binary (ASHIFT, GET_MODE (varop), 10825 XEXP (varop, 0), log2_rtx); 10826 continue; 10827 } 10828 break; 10829 10830 case UDIV: 10831 /* Similar, for when divides are cheaper. */ 10832 if (CONST_INT_P (XEXP (varop, 1)) 10833 && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0) 10834 { 10835 rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2); 10836 varop = simplify_gen_binary (LSHIFTRT, GET_MODE (varop), 10837 XEXP (varop, 0), log2_rtx); 10838 continue; 10839 } 10840 break; 10841 10842 case ASHIFTRT: 10843 /* If we are extracting just the sign bit of an arithmetic 10844 right shift, that shift is not needed. However, the sign 10845 bit of a wider mode may be different from what would be 10846 interpreted as the sign bit in a narrower mode, so, if 10847 the result is narrower, don't discard the shift. */ 10848 if (code == LSHIFTRT 10849 && count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1) 10850 && (GET_MODE_UNIT_BITSIZE (result_mode) 10851 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop)))) 10852 { 10853 varop = XEXP (varop, 0); 10854 continue; 10855 } 10856 10857 /* fall through */ 10858 10859 case LSHIFTRT: 10860 case ASHIFT: 10861 case ROTATE: 10862 /* The following rules apply only to scalars. */ 10863 if (shift_mode != shift_unit_mode) 10864 break; 10865 int_mode = as_a <scalar_int_mode> (mode); 10866 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop)); 10867 int_result_mode = as_a <scalar_int_mode> (result_mode); 10868 10869 /* Here we have two nested shifts. The result is usually the 10870 AND of a new shift with a mask. We compute the result below. */ 10871 if (CONST_INT_P (XEXP (varop, 1)) 10872 && INTVAL (XEXP (varop, 1)) >= 0 10873 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (int_varop_mode) 10874 && HWI_COMPUTABLE_MODE_P (int_result_mode) 10875 && HWI_COMPUTABLE_MODE_P (int_mode)) 10876 { 10877 enum rtx_code first_code = GET_CODE (varop); 10878 unsigned int first_count = INTVAL (XEXP (varop, 1)); 10879 unsigned HOST_WIDE_INT mask; 10880 rtx mask_rtx; 10881 10882 /* We have one common special case. We can't do any merging if 10883 the inner code is an ASHIFTRT of a smaller mode. However, if 10884 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) 10885 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), 10886 we can convert it to 10887 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1). 10888 This simplifies certain SIGN_EXTEND operations. */ 10889 if (code == ASHIFT && first_code == ASHIFTRT 10890 && count == (GET_MODE_PRECISION (int_result_mode) 10891 - GET_MODE_PRECISION (int_varop_mode))) 10892 { 10893 /* C3 has the low-order C1 bits zero. */ 10894 10895 mask = GET_MODE_MASK (int_mode) 10896 & ~((HOST_WIDE_INT_1U << first_count) - 1); 10897 10898 varop = simplify_and_const_int (NULL_RTX, int_result_mode, 10899 XEXP (varop, 0), mask); 10900 varop = simplify_shift_const (NULL_RTX, ASHIFT, 10901 int_result_mode, varop, count); 10902 count = first_count; 10903 code = ASHIFTRT; 10904 continue; 10905 } 10906 10907 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more 10908 than C1 high-order bits equal to the sign bit, we can convert 10909 this to either an ASHIFT or an ASHIFTRT depending on the 10910 two counts. 10911 10912 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */ 10913 10914 if (code == ASHIFTRT && first_code == ASHIFT 10915 && int_varop_mode == shift_unit_mode 10916 && (num_sign_bit_copies (XEXP (varop, 0), shift_unit_mode) 10917 > first_count)) 10918 { 10919 varop = XEXP (varop, 0); 10920 count -= first_count; 10921 if (count < 0) 10922 { 10923 count = -count; 10924 code = ASHIFT; 10925 } 10926 10927 continue; 10928 } 10929 10930 /* There are some cases we can't do. If CODE is ASHIFTRT, 10931 we can only do this if FIRST_CODE is also ASHIFTRT. 10932 10933 We can't do the case when CODE is ROTATE and FIRST_CODE is 10934 ASHIFTRT. 10935 10936 If the mode of this shift is not the mode of the outer shift, 10937 we can't do this if either shift is a right shift or ROTATE. 10938 10939 Finally, we can't do any of these if the mode is too wide 10940 unless the codes are the same. 10941 10942 Handle the case where the shift codes are the same 10943 first. */ 10944 10945 if (code == first_code) 10946 { 10947 if (int_varop_mode != int_result_mode 10948 && (code == ASHIFTRT || code == LSHIFTRT 10949 || code == ROTATE)) 10950 break; 10951 10952 count += first_count; 10953 varop = XEXP (varop, 0); 10954 continue; 10955 } 10956 10957 if (code == ASHIFTRT 10958 || (code == ROTATE && first_code == ASHIFTRT) 10959 || GET_MODE_PRECISION (int_mode) > HOST_BITS_PER_WIDE_INT 10960 || (int_varop_mode != int_result_mode 10961 && (first_code == ASHIFTRT || first_code == LSHIFTRT 10962 || first_code == ROTATE 10963 || code == ROTATE))) 10964 break; 10965 10966 /* To compute the mask to apply after the shift, shift the 10967 nonzero bits of the inner shift the same way the 10968 outer shift will. */ 10969 10970 mask_rtx = gen_int_mode (nonzero_bits (varop, int_varop_mode), 10971 int_result_mode); 10972 rtx count_rtx = gen_int_shift_amount (int_result_mode, count); 10973 mask_rtx 10974 = simplify_const_binary_operation (code, int_result_mode, 10975 mask_rtx, count_rtx); 10976 10977 /* Give up if we can't compute an outer operation to use. */ 10978 if (mask_rtx == 0 10979 || !CONST_INT_P (mask_rtx) 10980 || ! merge_outer_ops (&outer_op, &outer_const, AND, 10981 INTVAL (mask_rtx), 10982 int_result_mode, &complement_p)) 10983 break; 10984 10985 /* If the shifts are in the same direction, we add the 10986 counts. Otherwise, we subtract them. */ 10987 if ((code == ASHIFTRT || code == LSHIFTRT) 10988 == (first_code == ASHIFTRT || first_code == LSHIFTRT)) 10989 count += first_count; 10990 else 10991 count -= first_count; 10992 10993 /* If COUNT is positive, the new shift is usually CODE, 10994 except for the two exceptions below, in which case it is 10995 FIRST_CODE. If the count is negative, FIRST_CODE should 10996 always be used */ 10997 if (count > 0 10998 && ((first_code == ROTATE && code == ASHIFT) 10999 || (first_code == ASHIFTRT && code == LSHIFTRT))) 11000 code = first_code; 11001 else if (count < 0) 11002 code = first_code, count = -count; 11003 11004 varop = XEXP (varop, 0); 11005 continue; 11006 } 11007 11008 /* If we have (A << B << C) for any shift, we can convert this to 11009 (A << C << B). This wins if A is a constant. Only try this if 11010 B is not a constant. */ 11011 11012 else if (GET_CODE (varop) == code 11013 && CONST_INT_P (XEXP (varop, 0)) 11014 && !CONST_INT_P (XEXP (varop, 1))) 11015 { 11016 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make 11017 sure the result will be masked. See PR70222. */ 11018 if (code == LSHIFTRT 11019 && int_mode != int_result_mode 11020 && !merge_outer_ops (&outer_op, &outer_const, AND, 11021 GET_MODE_MASK (int_result_mode) 11022 >> orig_count, int_result_mode, 11023 &complement_p)) 11024 break; 11025 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing 11026 up outer sign extension (often left and right shift) is 11027 hardly more efficient than the original. See PR70429. 11028 Similarly punt for rotates with different modes. 11029 See PR97386. */ 11030 if ((code == ASHIFTRT || code == ROTATE) 11031 && int_mode != int_result_mode) 11032 break; 11033 11034 rtx count_rtx = gen_int_shift_amount (int_result_mode, count); 11035 rtx new_rtx = simplify_const_binary_operation (code, int_mode, 11036 XEXP (varop, 0), 11037 count_rtx); 11038 varop = gen_rtx_fmt_ee (code, int_mode, new_rtx, XEXP (varop, 1)); 11039 count = 0; 11040 continue; 11041 } 11042 break; 11043 11044 case NOT: 11045 /* The following rules apply only to scalars. */ 11046 if (shift_mode != shift_unit_mode) 11047 break; 11048 11049 /* Make this fit the case below. */ 11050 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx); 11051 continue; 11052 11053 case IOR: 11054 case AND: 11055 case XOR: 11056 /* The following rules apply only to scalars. */ 11057 if (shift_mode != shift_unit_mode) 11058 break; 11059 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop)); 11060 int_result_mode = as_a <scalar_int_mode> (result_mode); 11061 11062 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) 11063 with C the size of VAROP - 1 and the shift is logical if 11064 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 11065 we have an (le X 0) operation. If we have an arithmetic shift 11066 and STORE_FLAG_VALUE is 1 or we have a logical shift with 11067 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ 11068 11069 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS 11070 && XEXP (XEXP (varop, 0), 1) == constm1_rtx 11071 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 11072 && (code == LSHIFTRT || code == ASHIFTRT) 11073 && count == (GET_MODE_PRECISION (int_varop_mode) - 1) 11074 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 11075 { 11076 count = 0; 11077 varop = gen_rtx_LE (int_varop_mode, XEXP (varop, 1), 11078 const0_rtx); 11079 11080 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 11081 varop = gen_rtx_NEG (int_varop_mode, varop); 11082 11083 continue; 11084 } 11085 11086 /* If we have (shift (logical)), move the logical to the outside 11087 to allow it to possibly combine with another logical and the 11088 shift to combine with another shift. This also canonicalizes to 11089 what a ZERO_EXTRACT looks like. Also, some machines have 11090 (and (shift)) insns. */ 11091 11092 if (CONST_INT_P (XEXP (varop, 1)) 11093 /* We can't do this if we have (ashiftrt (xor)) and the 11094 constant has its sign bit set in shift_unit_mode with 11095 shift_unit_mode wider than result_mode. */ 11096 && !(code == ASHIFTRT && GET_CODE (varop) == XOR 11097 && int_result_mode != shift_unit_mode 11098 && trunc_int_for_mode (INTVAL (XEXP (varop, 1)), 11099 shift_unit_mode) < 0) 11100 && (new_rtx = simplify_const_binary_operation 11101 (code, int_result_mode, 11102 gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode), 11103 gen_int_shift_amount (int_result_mode, count))) != 0 11104 && CONST_INT_P (new_rtx) 11105 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), 11106 INTVAL (new_rtx), int_result_mode, 11107 &complement_p)) 11108 { 11109 varop = XEXP (varop, 0); 11110 continue; 11111 } 11112 11113 /* If we can't do that, try to simplify the shift in each arm of the 11114 logical expression, make a new logical expression, and apply 11115 the inverse distributive law. This also can't be done for 11116 (ashiftrt (xor)) where we've widened the shift and the constant 11117 changes the sign bit. */ 11118 if (CONST_INT_P (XEXP (varop, 1)) 11119 && !(code == ASHIFTRT && GET_CODE (varop) == XOR 11120 && int_result_mode != shift_unit_mode 11121 && trunc_int_for_mode (INTVAL (XEXP (varop, 1)), 11122 shift_unit_mode) < 0)) 11123 { 11124 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode, 11125 XEXP (varop, 0), count); 11126 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode, 11127 XEXP (varop, 1), count); 11128 11129 varop = simplify_gen_binary (GET_CODE (varop), shift_unit_mode, 11130 lhs, rhs); 11131 varop = apply_distributive_law (varop); 11132 11133 count = 0; 11134 continue; 11135 } 11136 break; 11137 11138 case EQ: 11139 /* The following rules apply only to scalars. */ 11140 if (shift_mode != shift_unit_mode) 11141 break; 11142 int_result_mode = as_a <scalar_int_mode> (result_mode); 11143 11144 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE 11145 says that the sign bit can be tested, FOO has mode MODE, C is 11146 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit 11147 that may be nonzero. */ 11148 if (code == LSHIFTRT 11149 && XEXP (varop, 1) == const0_rtx 11150 && GET_MODE (XEXP (varop, 0)) == int_result_mode 11151 && count == (GET_MODE_PRECISION (int_result_mode) - 1) 11152 && HWI_COMPUTABLE_MODE_P (int_result_mode) 11153 && STORE_FLAG_VALUE == -1 11154 && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1 11155 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, 11156 int_result_mode, &complement_p)) 11157 { 11158 varop = XEXP (varop, 0); 11159 count = 0; 11160 continue; 11161 } 11162 break; 11163 11164 case NEG: 11165 /* The following rules apply only to scalars. */ 11166 if (shift_mode != shift_unit_mode) 11167 break; 11168 int_result_mode = as_a <scalar_int_mode> (result_mode); 11169 11170 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less 11171 than the number of bits in the mode is equivalent to A. */ 11172 if (code == LSHIFTRT 11173 && count == (GET_MODE_PRECISION (int_result_mode) - 1) 11174 && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1) 11175 { 11176 varop = XEXP (varop, 0); 11177 count = 0; 11178 continue; 11179 } 11180 11181 /* NEG commutes with ASHIFT since it is multiplication. Move the 11182 NEG outside to allow shifts to combine. */ 11183 if (code == ASHIFT 11184 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, 11185 int_result_mode, &complement_p)) 11186 { 11187 varop = XEXP (varop, 0); 11188 continue; 11189 } 11190 break; 11191 11192 case PLUS: 11193 /* The following rules apply only to scalars. */ 11194 if (shift_mode != shift_unit_mode) 11195 break; 11196 int_result_mode = as_a <scalar_int_mode> (result_mode); 11197 11198 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C 11199 is one less than the number of bits in the mode is 11200 equivalent to (xor A 1). */ 11201 if (code == LSHIFTRT 11202 && count == (GET_MODE_PRECISION (int_result_mode) - 1) 11203 && XEXP (varop, 1) == constm1_rtx 11204 && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1 11205 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, 11206 int_result_mode, &complement_p)) 11207 { 11208 count = 0; 11209 varop = XEXP (varop, 0); 11210 continue; 11211 } 11212 11213 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits 11214 that might be nonzero in BAR are those being shifted out and those 11215 bits are known zero in FOO, we can replace the PLUS with FOO. 11216 Similarly in the other operand order. This code occurs when 11217 we are computing the size of a variable-size array. */ 11218 11219 if ((code == ASHIFTRT || code == LSHIFTRT) 11220 && count < HOST_BITS_PER_WIDE_INT 11221 && nonzero_bits (XEXP (varop, 1), int_result_mode) >> count == 0 11222 && (nonzero_bits (XEXP (varop, 1), int_result_mode) 11223 & nonzero_bits (XEXP (varop, 0), int_result_mode)) == 0) 11224 { 11225 varop = XEXP (varop, 0); 11226 continue; 11227 } 11228 else if ((code == ASHIFTRT || code == LSHIFTRT) 11229 && count < HOST_BITS_PER_WIDE_INT 11230 && HWI_COMPUTABLE_MODE_P (int_result_mode) 11231 && (nonzero_bits (XEXP (varop, 0), int_result_mode) 11232 >> count) == 0 11233 && (nonzero_bits (XEXP (varop, 0), int_result_mode) 11234 & nonzero_bits (XEXP (varop, 1), int_result_mode)) == 0) 11235 { 11236 varop = XEXP (varop, 1); 11237 continue; 11238 } 11239 11240 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ 11241 if (code == ASHIFT 11242 && CONST_INT_P (XEXP (varop, 1)) 11243 && (new_rtx = simplify_const_binary_operation 11244 (ASHIFT, int_result_mode, 11245 gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode), 11246 gen_int_shift_amount (int_result_mode, count))) != 0 11247 && CONST_INT_P (new_rtx) 11248 && merge_outer_ops (&outer_op, &outer_const, PLUS, 11249 INTVAL (new_rtx), int_result_mode, 11250 &complement_p)) 11251 { 11252 varop = XEXP (varop, 0); 11253 continue; 11254 } 11255 11256 /* Check for 'PLUS signbit', which is the canonical form of 'XOR 11257 signbit', and attempt to change the PLUS to an XOR and move it to 11258 the outer operation as is done above in the AND/IOR/XOR case 11259 leg for shift(logical). See details in logical handling above 11260 for reasoning in doing so. */ 11261 if (code == LSHIFTRT 11262 && CONST_INT_P (XEXP (varop, 1)) 11263 && mode_signbit_p (int_result_mode, XEXP (varop, 1)) 11264 && (new_rtx = simplify_const_binary_operation 11265 (code, int_result_mode, 11266 gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode), 11267 gen_int_shift_amount (int_result_mode, count))) != 0 11268 && CONST_INT_P (new_rtx) 11269 && merge_outer_ops (&outer_op, &outer_const, XOR, 11270 INTVAL (new_rtx), int_result_mode, 11271 &complement_p)) 11272 { 11273 varop = XEXP (varop, 0); 11274 continue; 11275 } 11276 11277 break; 11278 11279 case MINUS: 11280 /* The following rules apply only to scalars. */ 11281 if (shift_mode != shift_unit_mode) 11282 break; 11283 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop)); 11284 11285 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) 11286 with C the size of VAROP - 1 and the shift is logical if 11287 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 11288 we have a (gt X 0) operation. If the shift is arithmetic with 11289 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, 11290 we have a (neg (gt X 0)) operation. */ 11291 11292 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 11293 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT 11294 && count == (GET_MODE_PRECISION (int_varop_mode) - 1) 11295 && (code == LSHIFTRT || code == ASHIFTRT) 11296 && CONST_INT_P (XEXP (XEXP (varop, 0), 1)) 11297 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count 11298 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 11299 { 11300 count = 0; 11301 varop = gen_rtx_GT (int_varop_mode, XEXP (varop, 1), 11302 const0_rtx); 11303 11304 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 11305 varop = gen_rtx_NEG (int_varop_mode, varop); 11306 11307 continue; 11308 } 11309 break; 11310 11311 case TRUNCATE: 11312 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) 11313 if the truncate does not affect the value. */ 11314 if (code == LSHIFTRT 11315 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT 11316 && CONST_INT_P (XEXP (XEXP (varop, 0), 1)) 11317 && (INTVAL (XEXP (XEXP (varop, 0), 1)) 11318 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0))) 11319 - GET_MODE_UNIT_PRECISION (GET_MODE (varop))))) 11320 { 11321 rtx varop_inner = XEXP (varop, 0); 11322 int new_count = count + INTVAL (XEXP (varop_inner, 1)); 11323 rtx new_count_rtx = gen_int_shift_amount (GET_MODE (varop_inner), 11324 new_count); 11325 varop_inner = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), 11326 XEXP (varop_inner, 0), 11327 new_count_rtx); 11328 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); 11329 count = 0; 11330 continue; 11331 } 11332 break; 11333 11334 default: 11335 break; 11336 } 11337 11338 break; 11339 } 11340 11341 shift_mode = result_mode; 11342 if (shift_mode != mode) 11343 { 11344 /* We only change the modes of scalar shifts. */ 11345 int_mode = as_a <scalar_int_mode> (mode); 11346 int_result_mode = as_a <scalar_int_mode> (result_mode); 11347 shift_mode = try_widen_shift_mode (code, varop, count, int_result_mode, 11348 int_mode, outer_op, outer_const); 11349 } 11350 11351 /* We have now finished analyzing the shift. The result should be 11352 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If 11353 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied 11354 to the result of the shift. OUTER_CONST is the relevant constant, 11355 but we must turn off all bits turned off in the shift. */ 11356 11357 if (outer_op == UNKNOWN 11358 && orig_code == code && orig_count == count 11359 && varop == orig_varop 11360 && shift_mode == GET_MODE (varop)) 11361 return NULL_RTX; 11362 11363 /* Make a SUBREG if necessary. If we can't make it, fail. */ 11364 varop = gen_lowpart (shift_mode, varop); 11365 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) 11366 return NULL_RTX; 11367 11368 /* If we have an outer operation and we just made a shift, it is 11369 possible that we could have simplified the shift were it not 11370 for the outer operation. So try to do the simplification 11371 recursively. */ 11372 11373 if (outer_op != UNKNOWN) 11374 x = simplify_shift_const_1 (code, shift_mode, varop, count); 11375 else 11376 x = NULL_RTX; 11377 11378 if (x == NULL_RTX) 11379 x = simplify_gen_binary (code, shift_mode, varop, 11380 gen_int_shift_amount (shift_mode, count)); 11381 11382 /* If we were doing an LSHIFTRT in a wider mode than it was originally, 11383 turn off all the bits that the shift would have turned off. */ 11384 if (orig_code == LSHIFTRT && result_mode != shift_mode) 11385 /* We only change the modes of scalar shifts. */ 11386 x = simplify_and_const_int (NULL_RTX, as_a <scalar_int_mode> (shift_mode), 11387 x, GET_MODE_MASK (result_mode) >> orig_count); 11388 11389 /* Do the remainder of the processing in RESULT_MODE. */ 11390 x = gen_lowpart_or_truncate (result_mode, x); 11391 11392 /* If COMPLEMENT_P is set, we have to complement X before doing the outer 11393 operation. */ 11394 if (complement_p) 11395 x = simplify_gen_unary (NOT, result_mode, x, result_mode); 11396 11397 if (outer_op != UNKNOWN) 11398 { 11399 int_result_mode = as_a <scalar_int_mode> (result_mode); 11400 11401 if (GET_RTX_CLASS (outer_op) != RTX_UNARY 11402 && GET_MODE_PRECISION (int_result_mode) < HOST_BITS_PER_WIDE_INT) 11403 outer_const = trunc_int_for_mode (outer_const, int_result_mode); 11404 11405 if (outer_op == AND) 11406 x = simplify_and_const_int (NULL_RTX, int_result_mode, x, outer_const); 11407 else if (outer_op == SET) 11408 { 11409 /* This means that we have determined that the result is 11410 equivalent to a constant. This should be rare. */ 11411 if (!side_effects_p (x)) 11412 x = GEN_INT (outer_const); 11413 } 11414 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY) 11415 x = simplify_gen_unary (outer_op, int_result_mode, x, int_result_mode); 11416 else 11417 x = simplify_gen_binary (outer_op, int_result_mode, x, 11418 GEN_INT (outer_const)); 11419 } 11420 11421 return x; 11422 } 11423 11424 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 11425 The result of the shift is RESULT_MODE. If we cannot simplify it, 11426 return X or, if it is NULL, synthesize the expression with 11427 simplify_gen_binary. Otherwise, return a simplified value. 11428 11429 The shift is normally computed in the widest mode we find in VAROP, as 11430 long as it isn't a different number of words than RESULT_MODE. Exceptions 11431 are ASHIFTRT and ROTATE, which are always done in their original mode. */ 11432 11433 static rtx 11434 simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode, 11435 rtx varop, int count) 11436 { 11437 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count); 11438 if (tem) 11439 return tem; 11440 11441 if (!x) 11442 x = simplify_gen_binary (code, GET_MODE (varop), varop, 11443 gen_int_shift_amount (GET_MODE (varop), count)); 11444 if (GET_MODE (x) != result_mode) 11445 x = gen_lowpart (result_mode, x); 11446 return x; 11447 } 11448 11449 11450 /* A subroutine of recog_for_combine. See there for arguments and 11451 return value. */ 11452 11453 static int 11454 recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) 11455 { 11456 rtx pat = *pnewpat; 11457 rtx pat_without_clobbers; 11458 int insn_code_number; 11459 int num_clobbers_to_add = 0; 11460 int i; 11461 rtx notes = NULL_RTX; 11462 rtx old_notes, old_pat; 11463 int old_icode; 11464 11465 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER 11466 we use to indicate that something didn't match. If we find such a 11467 thing, force rejection. */ 11468 if (GET_CODE (pat) == PARALLEL) 11469 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 11470 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER 11471 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 11472 return -1; 11473 11474 old_pat = PATTERN (insn); 11475 old_notes = REG_NOTES (insn); 11476 PATTERN (insn) = pat; 11477 REG_NOTES (insn) = NULL_RTX; 11478 11479 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 11480 if (dump_file && (dump_flags & TDF_DETAILS)) 11481 { 11482 if (insn_code_number < 0) 11483 fputs ("Failed to match this instruction:\n", dump_file); 11484 else 11485 fputs ("Successfully matched this instruction:\n", dump_file); 11486 print_rtl_single (dump_file, pat); 11487 } 11488 11489 /* If it isn't, there is the possibility that we previously had an insn 11490 that clobbered some register as a side effect, but the combined 11491 insn doesn't need to do that. So try once more without the clobbers 11492 unless this represents an ASM insn. */ 11493 11494 if (insn_code_number < 0 && ! check_asm_operands (pat) 11495 && GET_CODE (pat) == PARALLEL) 11496 { 11497 int pos; 11498 11499 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) 11500 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 11501 { 11502 if (i != pos) 11503 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); 11504 pos++; 11505 } 11506 11507 SUBST_INT (XVECLEN (pat, 0), pos); 11508 11509 if (pos == 1) 11510 pat = XVECEXP (pat, 0, 0); 11511 11512 PATTERN (insn) = pat; 11513 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 11514 if (dump_file && (dump_flags & TDF_DETAILS)) 11515 { 11516 if (insn_code_number < 0) 11517 fputs ("Failed to match this instruction:\n", dump_file); 11518 else 11519 fputs ("Successfully matched this instruction:\n", dump_file); 11520 print_rtl_single (dump_file, pat); 11521 } 11522 } 11523 11524 pat_without_clobbers = pat; 11525 11526 PATTERN (insn) = old_pat; 11527 REG_NOTES (insn) = old_notes; 11528 11529 /* Recognize all noop sets, these will be killed by followup pass. */ 11530 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) 11531 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; 11532 11533 /* If we had any clobbers to add, make a new pattern than contains 11534 them. Then check to make sure that all of them are dead. */ 11535 if (num_clobbers_to_add) 11536 { 11537 rtx newpat = gen_rtx_PARALLEL (VOIDmode, 11538 rtvec_alloc (GET_CODE (pat) == PARALLEL 11539 ? (XVECLEN (pat, 0) 11540 + num_clobbers_to_add) 11541 : num_clobbers_to_add + 1)); 11542 11543 if (GET_CODE (pat) == PARALLEL) 11544 for (i = 0; i < XVECLEN (pat, 0); i++) 11545 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); 11546 else 11547 XVECEXP (newpat, 0, 0) = pat; 11548 11549 add_clobbers (newpat, insn_code_number); 11550 11551 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; 11552 i < XVECLEN (newpat, 0); i++) 11553 { 11554 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)) 11555 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) 11556 return -1; 11557 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH) 11558 { 11559 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))); 11560 notes = alloc_reg_note (REG_UNUSED, 11561 XEXP (XVECEXP (newpat, 0, i), 0), notes); 11562 } 11563 } 11564 pat = newpat; 11565 } 11566 11567 if (insn_code_number >= 0 11568 && insn_code_number != NOOP_MOVE_INSN_CODE) 11569 { 11570 old_pat = PATTERN (insn); 11571 old_notes = REG_NOTES (insn); 11572 old_icode = INSN_CODE (insn); 11573 PATTERN (insn) = pat; 11574 REG_NOTES (insn) = notes; 11575 INSN_CODE (insn) = insn_code_number; 11576 11577 /* Allow targets to reject combined insn. */ 11578 if (!targetm.legitimate_combined_insn (insn)) 11579 { 11580 if (dump_file && (dump_flags & TDF_DETAILS)) 11581 fputs ("Instruction not appropriate for target.", 11582 dump_file); 11583 11584 /* Callers expect recog_for_combine to strip 11585 clobbers from the pattern on failure. */ 11586 pat = pat_without_clobbers; 11587 notes = NULL_RTX; 11588 11589 insn_code_number = -1; 11590 } 11591 11592 PATTERN (insn) = old_pat; 11593 REG_NOTES (insn) = old_notes; 11594 INSN_CODE (insn) = old_icode; 11595 } 11596 11597 *pnewpat = pat; 11598 *pnotes = notes; 11599 11600 return insn_code_number; 11601 } 11602 11603 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be 11604 expressed as an AND and maybe an LSHIFTRT, to that formulation. 11605 Return whether anything was so changed. */ 11606 11607 static bool 11608 change_zero_ext (rtx pat) 11609 { 11610 bool changed = false; 11611 rtx *src = &SET_SRC (pat); 11612 11613 subrtx_ptr_iterator::array_type array; 11614 FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST) 11615 { 11616 rtx x = **iter; 11617 scalar_int_mode mode, inner_mode; 11618 if (!is_a <scalar_int_mode> (GET_MODE (x), &mode)) 11619 continue; 11620 int size; 11621 11622 if (GET_CODE (x) == ZERO_EXTRACT 11623 && CONST_INT_P (XEXP (x, 1)) 11624 && CONST_INT_P (XEXP (x, 2)) 11625 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode) 11626 && GET_MODE_PRECISION (inner_mode) <= GET_MODE_PRECISION (mode)) 11627 { 11628 size = INTVAL (XEXP (x, 1)); 11629 11630 int start = INTVAL (XEXP (x, 2)); 11631 if (BITS_BIG_ENDIAN) 11632 start = GET_MODE_PRECISION (inner_mode) - size - start; 11633 11634 if (start != 0) 11635 x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0), 11636 gen_int_shift_amount (inner_mode, start)); 11637 else 11638 x = XEXP (x, 0); 11639 11640 if (mode != inner_mode) 11641 { 11642 if (REG_P (x) && HARD_REGISTER_P (x) 11643 && !can_change_dest_mode (x, 0, mode)) 11644 continue; 11645 11646 x = gen_lowpart_SUBREG (mode, x); 11647 } 11648 } 11649 else if (GET_CODE (x) == ZERO_EXTEND 11650 && GET_CODE (XEXP (x, 0)) == SUBREG 11651 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0)))) 11652 && !paradoxical_subreg_p (XEXP (x, 0)) 11653 && subreg_lowpart_p (XEXP (x, 0))) 11654 { 11655 inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0))); 11656 size = GET_MODE_PRECISION (inner_mode); 11657 x = SUBREG_REG (XEXP (x, 0)); 11658 if (GET_MODE (x) != mode) 11659 { 11660 if (REG_P (x) && HARD_REGISTER_P (x) 11661 && !can_change_dest_mode (x, 0, mode)) 11662 continue; 11663 11664 x = gen_lowpart_SUBREG (mode, x); 11665 } 11666 } 11667 else if (GET_CODE (x) == ZERO_EXTEND 11668 && REG_P (XEXP (x, 0)) 11669 && HARD_REGISTER_P (XEXP (x, 0)) 11670 && can_change_dest_mode (XEXP (x, 0), 0, mode)) 11671 { 11672 inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0))); 11673 size = GET_MODE_PRECISION (inner_mode); 11674 x = gen_rtx_REG (mode, REGNO (XEXP (x, 0))); 11675 } 11676 else 11677 continue; 11678 11679 if (!(GET_CODE (x) == LSHIFTRT 11680 && CONST_INT_P (XEXP (x, 1)) 11681 && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode))) 11682 { 11683 wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode)); 11684 x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode)); 11685 } 11686 11687 SUBST (**iter, x); 11688 changed = true; 11689 } 11690 11691 if (changed) 11692 FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST) 11693 maybe_swap_commutative_operands (**iter); 11694 11695 rtx *dst = &SET_DEST (pat); 11696 scalar_int_mode mode; 11697 if (GET_CODE (*dst) == ZERO_EXTRACT 11698 && REG_P (XEXP (*dst, 0)) 11699 && is_a <scalar_int_mode> (GET_MODE (XEXP (*dst, 0)), &mode) 11700 && CONST_INT_P (XEXP (*dst, 1)) 11701 && CONST_INT_P (XEXP (*dst, 2))) 11702 { 11703 rtx reg = XEXP (*dst, 0); 11704 int width = INTVAL (XEXP (*dst, 1)); 11705 int offset = INTVAL (XEXP (*dst, 2)); 11706 int reg_width = GET_MODE_PRECISION (mode); 11707 if (BITS_BIG_ENDIAN) 11708 offset = reg_width - width - offset; 11709 11710 rtx x, y, z, w; 11711 wide_int mask = wi::shifted_mask (offset, width, true, reg_width); 11712 wide_int mask2 = wi::shifted_mask (offset, width, false, reg_width); 11713 x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode)); 11714 if (offset) 11715 y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset)); 11716 else 11717 y = SET_SRC (pat); 11718 z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode)); 11719 w = gen_rtx_IOR (mode, x, z); 11720 SUBST (SET_DEST (pat), reg); 11721 SUBST (SET_SRC (pat), w); 11722 11723 changed = true; 11724 } 11725 11726 return changed; 11727 } 11728 11729 /* Like recog, but we receive the address of a pointer to a new pattern. 11730 We try to match the rtx that the pointer points to. 11731 If that fails, we may try to modify or replace the pattern, 11732 storing the replacement into the same pointer object. 11733 11734 Modifications include deletion or addition of CLOBBERs. If the 11735 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT 11736 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that 11737 (and undo if that fails). 11738 11739 PNOTES is a pointer to a location where any REG_UNUSED notes added for 11740 the CLOBBERs are placed. 11741 11742 The value is the final insn code from the pattern ultimately matched, 11743 or -1. */ 11744 11745 static int 11746 recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) 11747 { 11748 rtx pat = *pnewpat; 11749 int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes); 11750 if (insn_code_number >= 0 || check_asm_operands (pat)) 11751 return insn_code_number; 11752 11753 void *marker = get_undo_marker (); 11754 bool changed = false; 11755 11756 if (GET_CODE (pat) == SET) 11757 changed = change_zero_ext (pat); 11758 else if (GET_CODE (pat) == PARALLEL) 11759 { 11760 int i; 11761 for (i = 0; i < XVECLEN (pat, 0); i++) 11762 { 11763 rtx set = XVECEXP (pat, 0, i); 11764 if (GET_CODE (set) == SET) 11765 changed |= change_zero_ext (set); 11766 } 11767 } 11768 11769 if (changed) 11770 { 11771 insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes); 11772 11773 if (insn_code_number < 0) 11774 undo_to_marker (marker); 11775 } 11776 11777 return insn_code_number; 11778 } 11779 11780 /* Like gen_lowpart_general but for use by combine. In combine it 11781 is not possible to create any new pseudoregs. However, it is 11782 safe to create invalid memory addresses, because combine will 11783 try to recognize them and all they will do is make the combine 11784 attempt fail. 11785 11786 If for some reason this cannot do its job, an rtx 11787 (clobber (const_int 0)) is returned. 11788 An insn containing that will not be recognized. */ 11789 11790 static rtx 11791 gen_lowpart_for_combine (machine_mode omode, rtx x) 11792 { 11793 machine_mode imode = GET_MODE (x); 11794 rtx result; 11795 11796 if (omode == imode) 11797 return x; 11798 11799 /* We can only support MODE being wider than a word if X is a 11800 constant integer or has a mode the same size. */ 11801 if (maybe_gt (GET_MODE_SIZE (omode), UNITS_PER_WORD) 11802 && ! (CONST_SCALAR_INT_P (x) 11803 || known_eq (GET_MODE_SIZE (imode), GET_MODE_SIZE (omode)))) 11804 goto fail; 11805 11806 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart 11807 won't know what to do. So we will strip off the SUBREG here and 11808 process normally. */ 11809 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) 11810 { 11811 x = SUBREG_REG (x); 11812 11813 /* For use in case we fall down into the address adjustments 11814 further below, we need to adjust the known mode and size of 11815 x; imode and isize, since we just adjusted x. */ 11816 imode = GET_MODE (x); 11817 11818 if (imode == omode) 11819 return x; 11820 } 11821 11822 result = gen_lowpart_common (omode, x); 11823 11824 if (result) 11825 return result; 11826 11827 if (MEM_P (x)) 11828 { 11829 /* Refuse to work on a volatile memory ref or one with a mode-dependent 11830 address. */ 11831 if (MEM_VOLATILE_P (x) 11832 || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x))) 11833 goto fail; 11834 11835 /* If we want to refer to something bigger than the original memref, 11836 generate a paradoxical subreg instead. That will force a reload 11837 of the original memref X. */ 11838 if (paradoxical_subreg_p (omode, imode)) 11839 return gen_rtx_SUBREG (omode, x, 0); 11840 11841 poly_int64 offset = byte_lowpart_offset (omode, imode); 11842 return adjust_address_nv (x, omode, offset); 11843 } 11844 11845 /* If X is a comparison operator, rewrite it in a new mode. This 11846 probably won't match, but may allow further simplifications. */ 11847 else if (COMPARISON_P (x) 11848 && SCALAR_INT_MODE_P (imode) 11849 && SCALAR_INT_MODE_P (omode)) 11850 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1)); 11851 11852 /* If we couldn't simplify X any other way, just enclose it in a 11853 SUBREG. Normally, this SUBREG won't match, but some patterns may 11854 include an explicit SUBREG or we may simplify it further in combine. */ 11855 else 11856 { 11857 rtx res; 11858 11859 if (imode == VOIDmode) 11860 { 11861 imode = int_mode_for_mode (omode).require (); 11862 x = gen_lowpart_common (imode, x); 11863 if (x == NULL) 11864 goto fail; 11865 } 11866 res = lowpart_subreg (omode, x, imode); 11867 if (res) 11868 return res; 11869 } 11870 11871 fail: 11872 return gen_rtx_CLOBBER (omode, const0_rtx); 11873 } 11874 11875 /* Try to simplify a comparison between OP0 and a constant OP1, 11876 where CODE is the comparison code that will be tested, into a 11877 (CODE OP0 const0_rtx) form. 11878 11879 The result is a possibly different comparison code to use. 11880 *POP1 may be updated. */ 11881 11882 static enum rtx_code 11883 simplify_compare_const (enum rtx_code code, machine_mode mode, 11884 rtx op0, rtx *pop1) 11885 { 11886 scalar_int_mode int_mode; 11887 HOST_WIDE_INT const_op = INTVAL (*pop1); 11888 11889 /* Get the constant we are comparing against and turn off all bits 11890 not on in our mode. */ 11891 if (mode != VOIDmode) 11892 const_op = trunc_int_for_mode (const_op, mode); 11893 11894 /* If we are comparing against a constant power of two and the value 11895 being compared can only have that single bit nonzero (e.g., it was 11896 `and'ed with that bit), we can replace this with a comparison 11897 with zero. */ 11898 if (const_op 11899 && (code == EQ || code == NE || code == GE || code == GEU 11900 || code == LT || code == LTU) 11901 && is_a <scalar_int_mode> (mode, &int_mode) 11902 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT 11903 && pow2p_hwi (const_op & GET_MODE_MASK (int_mode)) 11904 && (nonzero_bits (op0, int_mode) 11905 == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (int_mode)))) 11906 { 11907 code = (code == EQ || code == GE || code == GEU ? NE : EQ); 11908 const_op = 0; 11909 } 11910 11911 /* Similarly, if we are comparing a value known to be either -1 or 11912 0 with -1, change it to the opposite comparison against zero. */ 11913 if (const_op == -1 11914 && (code == EQ || code == NE || code == GT || code == LE 11915 || code == GEU || code == LTU) 11916 && is_a <scalar_int_mode> (mode, &int_mode) 11917 && num_sign_bit_copies (op0, int_mode) == GET_MODE_PRECISION (int_mode)) 11918 { 11919 code = (code == EQ || code == LE || code == GEU ? NE : EQ); 11920 const_op = 0; 11921 } 11922 11923 /* Do some canonicalizations based on the comparison code. We prefer 11924 comparisons against zero and then prefer equality comparisons. 11925 If we can reduce the size of a constant, we will do that too. */ 11926 switch (code) 11927 { 11928 case LT: 11929 /* < C is equivalent to <= (C - 1) */ 11930 if (const_op > 0) 11931 { 11932 const_op -= 1; 11933 code = LE; 11934 /* ... fall through to LE case below. */ 11935 gcc_fallthrough (); 11936 } 11937 else 11938 break; 11939 11940 case LE: 11941 /* <= C is equivalent to < (C + 1); we do this for C < 0 */ 11942 if (const_op < 0) 11943 { 11944 const_op += 1; 11945 code = LT; 11946 } 11947 11948 /* If we are doing a <= 0 comparison on a value known to have 11949 a zero sign bit, we can replace this with == 0. */ 11950 else if (const_op == 0 11951 && is_a <scalar_int_mode> (mode, &int_mode) 11952 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT 11953 && (nonzero_bits (op0, int_mode) 11954 & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1))) 11955 == 0) 11956 code = EQ; 11957 break; 11958 11959 case GE: 11960 /* >= C is equivalent to > (C - 1). */ 11961 if (const_op > 0) 11962 { 11963 const_op -= 1; 11964 code = GT; 11965 /* ... fall through to GT below. */ 11966 gcc_fallthrough (); 11967 } 11968 else 11969 break; 11970 11971 case GT: 11972 /* > C is equivalent to >= (C + 1); we do this for C < 0. */ 11973 if (const_op < 0) 11974 { 11975 const_op += 1; 11976 code = GE; 11977 } 11978 11979 /* If we are doing a > 0 comparison on a value known to have 11980 a zero sign bit, we can replace this with != 0. */ 11981 else if (const_op == 0 11982 && is_a <scalar_int_mode> (mode, &int_mode) 11983 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT 11984 && (nonzero_bits (op0, int_mode) 11985 & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1))) 11986 == 0) 11987 code = NE; 11988 break; 11989 11990 case LTU: 11991 /* < C is equivalent to <= (C - 1). */ 11992 if (const_op > 0) 11993 { 11994 const_op -= 1; 11995 code = LEU; 11996 /* ... fall through ... */ 11997 gcc_fallthrough (); 11998 } 11999 /* (unsigned) < 0x80000000 is equivalent to >= 0. */ 12000 else if (is_a <scalar_int_mode> (mode, &int_mode) 12001 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT 12002 && ((unsigned HOST_WIDE_INT) const_op 12003 == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1))) 12004 { 12005 const_op = 0; 12006 code = GE; 12007 break; 12008 } 12009 else 12010 break; 12011 12012 case LEU: 12013 /* unsigned <= 0 is equivalent to == 0 */ 12014 if (const_op == 0) 12015 code = EQ; 12016 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ 12017 else if (is_a <scalar_int_mode> (mode, &int_mode) 12018 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT 12019 && ((unsigned HOST_WIDE_INT) const_op 12020 == ((HOST_WIDE_INT_1U 12021 << (GET_MODE_PRECISION (int_mode) - 1)) - 1))) 12022 { 12023 const_op = 0; 12024 code = GE; 12025 } 12026 break; 12027 12028 case GEU: 12029 /* >= C is equivalent to > (C - 1). */ 12030 if (const_op > 1) 12031 { 12032 const_op -= 1; 12033 code = GTU; 12034 /* ... fall through ... */ 12035 gcc_fallthrough (); 12036 } 12037 12038 /* (unsigned) >= 0x80000000 is equivalent to < 0. */ 12039 else if (is_a <scalar_int_mode> (mode, &int_mode) 12040 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT 12041 && ((unsigned HOST_WIDE_INT) const_op 12042 == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1))) 12043 { 12044 const_op = 0; 12045 code = LT; 12046 break; 12047 } 12048 else 12049 break; 12050 12051 case GTU: 12052 /* unsigned > 0 is equivalent to != 0 */ 12053 if (const_op == 0) 12054 code = NE; 12055 /* (unsigned) > 0x7fffffff is equivalent to < 0. */ 12056 else if (is_a <scalar_int_mode> (mode, &int_mode) 12057 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT 12058 && ((unsigned HOST_WIDE_INT) const_op 12059 == (HOST_WIDE_INT_1U 12060 << (GET_MODE_PRECISION (int_mode) - 1)) - 1)) 12061 { 12062 const_op = 0; 12063 code = LT; 12064 } 12065 break; 12066 12067 default: 12068 break; 12069 } 12070 12071 *pop1 = GEN_INT (const_op); 12072 return code; 12073 } 12074 12075 /* Simplify a comparison between *POP0 and *POP1 where CODE is the 12076 comparison code that will be tested. 12077 12078 The result is a possibly different comparison code to use. *POP0 and 12079 *POP1 may be updated. 12080 12081 It is possible that we might detect that a comparison is either always 12082 true or always false. However, we do not perform general constant 12083 folding in combine, so this knowledge isn't useful. Such tautologies 12084 should have been detected earlier. Hence we ignore all such cases. */ 12085 12086 static enum rtx_code 12087 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) 12088 { 12089 rtx op0 = *pop0; 12090 rtx op1 = *pop1; 12091 rtx tem, tem1; 12092 int i; 12093 scalar_int_mode mode, inner_mode, tmode; 12094 opt_scalar_int_mode tmode_iter; 12095 12096 /* Try a few ways of applying the same transformation to both operands. */ 12097 while (1) 12098 { 12099 /* The test below this one won't handle SIGN_EXTENDs on these machines, 12100 so check specially. */ 12101 if (!WORD_REGISTER_OPERATIONS 12102 && code != GTU && code != GEU && code != LTU && code != LEU 12103 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT 12104 && GET_CODE (XEXP (op0, 0)) == ASHIFT 12105 && GET_CODE (XEXP (op1, 0)) == ASHIFT 12106 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG 12107 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG 12108 && is_a <scalar_int_mode> (GET_MODE (op0), &mode) 12109 && (is_a <scalar_int_mode> 12110 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode)) 12111 && inner_mode == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))) 12112 && CONST_INT_P (XEXP (op0, 1)) 12113 && XEXP (op0, 1) == XEXP (op1, 1) 12114 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 12115 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1) 12116 && (INTVAL (XEXP (op0, 1)) 12117 == (GET_MODE_PRECISION (mode) 12118 - GET_MODE_PRECISION (inner_mode)))) 12119 { 12120 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); 12121 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); 12122 } 12123 12124 /* If both operands are the same constant shift, see if we can ignore the 12125 shift. We can if the shift is a rotate or if the bits shifted out of 12126 this shift are known to be zero for both inputs and if the type of 12127 comparison is compatible with the shift. */ 12128 if (GET_CODE (op0) == GET_CODE (op1) 12129 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0)) 12130 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) 12131 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) 12132 && (code != GT && code != LT && code != GE && code != LE)) 12133 || (GET_CODE (op0) == ASHIFTRT 12134 && (code != GTU && code != LTU 12135 && code != GEU && code != LEU))) 12136 && CONST_INT_P (XEXP (op0, 1)) 12137 && INTVAL (XEXP (op0, 1)) >= 0 12138 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 12139 && XEXP (op0, 1) == XEXP (op1, 1)) 12140 { 12141 machine_mode mode = GET_MODE (op0); 12142 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 12143 int shift_count = INTVAL (XEXP (op0, 1)); 12144 12145 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) 12146 mask &= (mask >> shift_count) << shift_count; 12147 else if (GET_CODE (op0) == ASHIFT) 12148 mask = (mask & (mask << shift_count)) >> shift_count; 12149 12150 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 12151 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) 12152 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); 12153 else 12154 break; 12155 } 12156 12157 /* If both operands are AND's of a paradoxical SUBREG by constant, the 12158 SUBREGs are of the same mode, and, in both cases, the AND would 12159 be redundant if the comparison was done in the narrower mode, 12160 do the comparison in the narrower mode (e.g., we are AND'ing with 1 12161 and the operand's possibly nonzero bits are 0xffffff01; in that case 12162 if we only care about QImode, we don't need the AND). This case 12163 occurs if the output mode of an scc insn is not SImode and 12164 STORE_FLAG_VALUE == 1 (e.g., the 386). 12165 12166 Similarly, check for a case where the AND's are ZERO_EXTEND 12167 operations from some narrower mode even though a SUBREG is not 12168 present. */ 12169 12170 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND 12171 && CONST_INT_P (XEXP (op0, 1)) 12172 && CONST_INT_P (XEXP (op1, 1))) 12173 { 12174 rtx inner_op0 = XEXP (op0, 0); 12175 rtx inner_op1 = XEXP (op1, 0); 12176 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); 12177 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); 12178 int changed = 0; 12179 12180 if (paradoxical_subreg_p (inner_op0) 12181 && GET_CODE (inner_op1) == SUBREG 12182 && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0))) 12183 && (GET_MODE (SUBREG_REG (inner_op0)) 12184 == GET_MODE (SUBREG_REG (inner_op1))) 12185 && ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), 12186 GET_MODE (SUBREG_REG (inner_op0)))) == 0 12187 && ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), 12188 GET_MODE (SUBREG_REG (inner_op1)))) == 0) 12189 { 12190 op0 = SUBREG_REG (inner_op0); 12191 op1 = SUBREG_REG (inner_op1); 12192 12193 /* The resulting comparison is always unsigned since we masked 12194 off the original sign bit. */ 12195 code = unsigned_condition (code); 12196 12197 changed = 1; 12198 } 12199 12200 else if (c0 == c1) 12201 FOR_EACH_MODE_UNTIL (tmode, 12202 as_a <scalar_int_mode> (GET_MODE (op0))) 12203 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) 12204 { 12205 op0 = gen_lowpart_or_truncate (tmode, inner_op0); 12206 op1 = gen_lowpart_or_truncate (tmode, inner_op1); 12207 code = unsigned_condition (code); 12208 changed = 1; 12209 break; 12210 } 12211 12212 if (! changed) 12213 break; 12214 } 12215 12216 /* If both operands are NOT, we can strip off the outer operation 12217 and adjust the comparison code for swapped operands; similarly for 12218 NEG, except that this must be an equality comparison. */ 12219 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) 12220 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG 12221 && (code == EQ || code == NE))) 12222 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); 12223 12224 else 12225 break; 12226 } 12227 12228 /* If the first operand is a constant, swap the operands and adjust the 12229 comparison code appropriately, but don't do this if the second operand 12230 is already a constant integer. */ 12231 if (swap_commutative_operands_p (op0, op1)) 12232 { 12233 std::swap (op0, op1); 12234 code = swap_condition (code); 12235 } 12236 12237 /* We now enter a loop during which we will try to simplify the comparison. 12238 For the most part, we only are concerned with comparisons with zero, 12239 but some things may really be comparisons with zero but not start 12240 out looking that way. */ 12241 12242 while (CONST_INT_P (op1)) 12243 { 12244 machine_mode raw_mode = GET_MODE (op0); 12245 scalar_int_mode int_mode; 12246 int equality_comparison_p; 12247 int sign_bit_comparison_p; 12248 int unsigned_comparison_p; 12249 HOST_WIDE_INT const_op; 12250 12251 /* We only want to handle integral modes. This catches VOIDmode, 12252 CCmode, and the floating-point modes. An exception is that we 12253 can handle VOIDmode if OP0 is a COMPARE or a comparison 12254 operation. */ 12255 12256 if (GET_MODE_CLASS (raw_mode) != MODE_INT 12257 && ! (raw_mode == VOIDmode 12258 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0)))) 12259 break; 12260 12261 /* Try to simplify the compare to constant, possibly changing the 12262 comparison op, and/or changing op1 to zero. */ 12263 code = simplify_compare_const (code, raw_mode, op0, &op1); 12264 const_op = INTVAL (op1); 12265 12266 /* Compute some predicates to simplify code below. */ 12267 12268 equality_comparison_p = (code == EQ || code == NE); 12269 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); 12270 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU 12271 || code == GEU); 12272 12273 /* If this is a sign bit comparison and we can do arithmetic in 12274 MODE, say that we will only be needing the sign bit of OP0. */ 12275 if (sign_bit_comparison_p 12276 && is_a <scalar_int_mode> (raw_mode, &int_mode) 12277 && HWI_COMPUTABLE_MODE_P (int_mode)) 12278 op0 = force_to_mode (op0, int_mode, 12279 HOST_WIDE_INT_1U 12280 << (GET_MODE_PRECISION (int_mode) - 1), 12281 0); 12282 12283 if (COMPARISON_P (op0)) 12284 { 12285 /* We can't do anything if OP0 is a condition code value, rather 12286 than an actual data value. */ 12287 if (const_op != 0 12288 || CC0_P (XEXP (op0, 0)) 12289 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) 12290 break; 12291 12292 /* Get the two operands being compared. */ 12293 if (GET_CODE (XEXP (op0, 0)) == COMPARE) 12294 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); 12295 else 12296 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); 12297 12298 /* Check for the cases where we simply want the result of the 12299 earlier test or the opposite of that result. */ 12300 if (code == NE || code == EQ 12301 || (val_signbit_known_set_p (raw_mode, STORE_FLAG_VALUE) 12302 && (code == LT || code == GE))) 12303 { 12304 enum rtx_code new_code; 12305 if (code == LT || code == NE) 12306 new_code = GET_CODE (op0); 12307 else 12308 new_code = reversed_comparison_code (op0, NULL); 12309 12310 if (new_code != UNKNOWN) 12311 { 12312 code = new_code; 12313 op0 = tem; 12314 op1 = tem1; 12315 continue; 12316 } 12317 } 12318 break; 12319 } 12320 12321 if (raw_mode == VOIDmode) 12322 break; 12323 scalar_int_mode mode = as_a <scalar_int_mode> (raw_mode); 12324 12325 /* Now try cases based on the opcode of OP0. If none of the cases 12326 does a "continue", we exit this loop immediately after the 12327 switch. */ 12328 12329 unsigned int mode_width = GET_MODE_PRECISION (mode); 12330 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 12331 switch (GET_CODE (op0)) 12332 { 12333 case ZERO_EXTRACT: 12334 /* If we are extracting a single bit from a variable position in 12335 a constant that has only a single bit set and are comparing it 12336 with zero, we can convert this into an equality comparison 12337 between the position and the location of the single bit. */ 12338 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might 12339 have already reduced the shift count modulo the word size. */ 12340 if (!SHIFT_COUNT_TRUNCATED 12341 && CONST_INT_P (XEXP (op0, 0)) 12342 && XEXP (op0, 1) == const1_rtx 12343 && equality_comparison_p && const_op == 0 12344 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0) 12345 { 12346 if (BITS_BIG_ENDIAN) 12347 i = BITS_PER_WORD - 1 - i; 12348 12349 op0 = XEXP (op0, 2); 12350 op1 = GEN_INT (i); 12351 const_op = i; 12352 12353 /* Result is nonzero iff shift count is equal to I. */ 12354 code = reverse_condition (code); 12355 continue; 12356 } 12357 12358 /* fall through */ 12359 12360 case SIGN_EXTRACT: 12361 tem = expand_compound_operation (op0); 12362 if (tem != op0) 12363 { 12364 op0 = tem; 12365 continue; 12366 } 12367 break; 12368 12369 case NOT: 12370 /* If testing for equality, we can take the NOT of the constant. */ 12371 if (equality_comparison_p 12372 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) 12373 { 12374 op0 = XEXP (op0, 0); 12375 op1 = tem; 12376 continue; 12377 } 12378 12379 /* If just looking at the sign bit, reverse the sense of the 12380 comparison. */ 12381 if (sign_bit_comparison_p) 12382 { 12383 op0 = XEXP (op0, 0); 12384 code = (code == GE ? LT : GE); 12385 continue; 12386 } 12387 break; 12388 12389 case NEG: 12390 /* If testing for equality, we can take the NEG of the constant. */ 12391 if (equality_comparison_p 12392 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) 12393 { 12394 op0 = XEXP (op0, 0); 12395 op1 = tem; 12396 continue; 12397 } 12398 12399 /* The remaining cases only apply to comparisons with zero. */ 12400 if (const_op != 0) 12401 break; 12402 12403 /* When X is ABS or is known positive, 12404 (neg X) is < 0 if and only if X != 0. */ 12405 12406 if (sign_bit_comparison_p 12407 && (GET_CODE (XEXP (op0, 0)) == ABS 12408 || (mode_width <= HOST_BITS_PER_WIDE_INT 12409 && (nonzero_bits (XEXP (op0, 0), mode) 12410 & (HOST_WIDE_INT_1U << (mode_width - 1))) 12411 == 0))) 12412 { 12413 op0 = XEXP (op0, 0); 12414 code = (code == LT ? NE : EQ); 12415 continue; 12416 } 12417 12418 /* If we have NEG of something whose two high-order bits are the 12419 same, we know that "(-a) < 0" is equivalent to "a > 0". */ 12420 if (num_sign_bit_copies (op0, mode) >= 2) 12421 { 12422 op0 = XEXP (op0, 0); 12423 code = swap_condition (code); 12424 continue; 12425 } 12426 break; 12427 12428 case ROTATE: 12429 /* If we are testing equality and our count is a constant, we 12430 can perform the inverse operation on our RHS. */ 12431 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1)) 12432 && (tem = simplify_binary_operation (ROTATERT, mode, 12433 op1, XEXP (op0, 1))) != 0) 12434 { 12435 op0 = XEXP (op0, 0); 12436 op1 = tem; 12437 continue; 12438 } 12439 12440 /* If we are doing a < 0 or >= 0 comparison, it means we are testing 12441 a particular bit. Convert it to an AND of a constant of that 12442 bit. This will be converted into a ZERO_EXTRACT. */ 12443 if (const_op == 0 && sign_bit_comparison_p 12444 && CONST_INT_P (XEXP (op0, 1)) 12445 && mode_width <= HOST_BITS_PER_WIDE_INT 12446 && UINTVAL (XEXP (op0, 1)) < mode_width) 12447 { 12448 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 12449 (HOST_WIDE_INT_1U 12450 << (mode_width - 1 12451 - INTVAL (XEXP (op0, 1))))); 12452 code = (code == LT ? NE : EQ); 12453 continue; 12454 } 12455 12456 /* Fall through. */ 12457 12458 case ABS: 12459 /* ABS is ignorable inside an equality comparison with zero. */ 12460 if (const_op == 0 && equality_comparison_p) 12461 { 12462 op0 = XEXP (op0, 0); 12463 continue; 12464 } 12465 break; 12466 12467 case SIGN_EXTEND: 12468 /* Can simplify (compare (zero/sign_extend FOO) CONST) to 12469 (compare FOO CONST) if CONST fits in FOO's mode and we 12470 are either testing inequality or have an unsigned 12471 comparison with ZERO_EXTEND or a signed comparison with 12472 SIGN_EXTEND. But don't do it if we don't have a compare 12473 insn of the given mode, since we'd have to revert it 12474 later on, and then we wouldn't know whether to sign- or 12475 zero-extend. */ 12476 if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode) 12477 && ! unsigned_comparison_p 12478 && HWI_COMPUTABLE_MODE_P (mode) 12479 && trunc_int_for_mode (const_op, mode) == const_op 12480 && have_insn_for (COMPARE, mode)) 12481 { 12482 op0 = XEXP (op0, 0); 12483 continue; 12484 } 12485 break; 12486 12487 case SUBREG: 12488 /* Check for the case where we are comparing A - C1 with C2, that is 12489 12490 (subreg:MODE (plus (A) (-C1))) op (C2) 12491 12492 with C1 a constant, and try to lift the SUBREG, i.e. to do the 12493 comparison in the wider mode. One of the following two conditions 12494 must be true in order for this to be valid: 12495 12496 1. The mode extension results in the same bit pattern being added 12497 on both sides and the comparison is equality or unsigned. As 12498 C2 has been truncated to fit in MODE, the pattern can only be 12499 all 0s or all 1s. 12500 12501 2. The mode extension results in the sign bit being copied on 12502 each side. 12503 12504 The difficulty here is that we have predicates for A but not for 12505 (A - C1) so we need to check that C1 is within proper bounds so 12506 as to perturbate A as little as possible. */ 12507 12508 if (mode_width <= HOST_BITS_PER_WIDE_INT 12509 && subreg_lowpart_p (op0) 12510 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)), 12511 &inner_mode) 12512 && GET_MODE_PRECISION (inner_mode) > mode_width 12513 && GET_CODE (SUBREG_REG (op0)) == PLUS 12514 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1))) 12515 { 12516 rtx a = XEXP (SUBREG_REG (op0), 0); 12517 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1)); 12518 12519 if ((c1 > 0 12520 && (unsigned HOST_WIDE_INT) c1 12521 < HOST_WIDE_INT_1U << (mode_width - 1) 12522 && (equality_comparison_p || unsigned_comparison_p) 12523 /* (A - C1) zero-extends if it is positive and sign-extends 12524 if it is negative, C2 both zero- and sign-extends. */ 12525 && (((nonzero_bits (a, inner_mode) 12526 & ~GET_MODE_MASK (mode)) == 0 12527 && const_op >= 0) 12528 /* (A - C1) sign-extends if it is positive and 1-extends 12529 if it is negative, C2 both sign- and 1-extends. */ 12530 || (num_sign_bit_copies (a, inner_mode) 12531 > (unsigned int) (GET_MODE_PRECISION (inner_mode) 12532 - mode_width) 12533 && const_op < 0))) 12534 || ((unsigned HOST_WIDE_INT) c1 12535 < HOST_WIDE_INT_1U << (mode_width - 2) 12536 /* (A - C1) always sign-extends, like C2. */ 12537 && num_sign_bit_copies (a, inner_mode) 12538 > (unsigned int) (GET_MODE_PRECISION (inner_mode) 12539 - (mode_width - 1)))) 12540 { 12541 op0 = SUBREG_REG (op0); 12542 continue; 12543 } 12544 } 12545 12546 /* If the inner mode is narrower and we are extracting the low part, 12547 we can treat the SUBREG as if it were a ZERO_EXTEND. */ 12548 if (paradoxical_subreg_p (op0)) 12549 ; 12550 else if (subreg_lowpart_p (op0) 12551 && GET_MODE_CLASS (mode) == MODE_INT 12552 && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode) 12553 && (code == NE || code == EQ) 12554 && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT 12555 && !paradoxical_subreg_p (op0) 12556 && (nonzero_bits (SUBREG_REG (op0), inner_mode) 12557 & ~GET_MODE_MASK (mode)) == 0) 12558 { 12559 /* Remove outer subregs that don't do anything. */ 12560 tem = gen_lowpart (inner_mode, op1); 12561 12562 if ((nonzero_bits (tem, inner_mode) 12563 & ~GET_MODE_MASK (mode)) == 0) 12564 { 12565 op0 = SUBREG_REG (op0); 12566 op1 = tem; 12567 continue; 12568 } 12569 break; 12570 } 12571 else 12572 break; 12573 12574 /* FALLTHROUGH */ 12575 12576 case ZERO_EXTEND: 12577 if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode) 12578 && (unsigned_comparison_p || equality_comparison_p) 12579 && HWI_COMPUTABLE_MODE_P (mode) 12580 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode) 12581 && const_op >= 0 12582 && have_insn_for (COMPARE, mode)) 12583 { 12584 op0 = XEXP (op0, 0); 12585 continue; 12586 } 12587 break; 12588 12589 case PLUS: 12590 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do 12591 this for equality comparisons due to pathological cases involving 12592 overflows. */ 12593 if (equality_comparison_p 12594 && (tem = simplify_binary_operation (MINUS, mode, 12595 op1, XEXP (op0, 1))) != 0) 12596 { 12597 op0 = XEXP (op0, 0); 12598 op1 = tem; 12599 continue; 12600 } 12601 12602 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ 12603 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx 12604 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) 12605 { 12606 op0 = XEXP (XEXP (op0, 0), 0); 12607 code = (code == LT ? EQ : NE); 12608 continue; 12609 } 12610 break; 12611 12612 case MINUS: 12613 /* We used to optimize signed comparisons against zero, but that 12614 was incorrect. Unsigned comparisons against zero (GTU, LEU) 12615 arrive here as equality comparisons, or (GEU, LTU) are 12616 optimized away. No need to special-case them. */ 12617 12618 /* (eq (minus A B) C) -> (eq A (plus B C)) or 12619 (eq B (minus A C)), whichever simplifies. We can only do 12620 this for equality comparisons due to pathological cases involving 12621 overflows. */ 12622 if (equality_comparison_p 12623 && (tem = simplify_binary_operation (PLUS, mode, 12624 XEXP (op0, 1), op1)) != 0) 12625 { 12626 op0 = XEXP (op0, 0); 12627 op1 = tem; 12628 continue; 12629 } 12630 12631 if (equality_comparison_p 12632 && (tem = simplify_binary_operation (MINUS, mode, 12633 XEXP (op0, 0), op1)) != 0) 12634 { 12635 op0 = XEXP (op0, 1); 12636 op1 = tem; 12637 continue; 12638 } 12639 12640 /* The sign bit of (minus (ashiftrt X C) X), where C is the number 12641 of bits in X minus 1, is one iff X > 0. */ 12642 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT 12643 && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) 12644 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 12645 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 12646 { 12647 op0 = XEXP (op0, 1); 12648 code = (code == GE ? LE : GT); 12649 continue; 12650 } 12651 break; 12652 12653 case XOR: 12654 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification 12655 if C is zero or B is a constant. */ 12656 if (equality_comparison_p 12657 && (tem = simplify_binary_operation (XOR, mode, 12658 XEXP (op0, 1), op1)) != 0) 12659 { 12660 op0 = XEXP (op0, 0); 12661 op1 = tem; 12662 continue; 12663 } 12664 break; 12665 12666 12667 case IOR: 12668 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero 12669 iff X <= 0. */ 12670 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS 12671 && XEXP (XEXP (op0, 0), 1) == constm1_rtx 12672 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 12673 { 12674 op0 = XEXP (op0, 1); 12675 code = (code == GE ? GT : LE); 12676 continue; 12677 } 12678 break; 12679 12680 case AND: 12681 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This 12682 will be converted to a ZERO_EXTRACT later. */ 12683 if (const_op == 0 && equality_comparison_p 12684 && GET_CODE (XEXP (op0, 0)) == ASHIFT 12685 && XEXP (XEXP (op0, 0), 0) == const1_rtx) 12686 { 12687 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1), 12688 XEXP (XEXP (op0, 0), 1)); 12689 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1); 12690 continue; 12691 } 12692 12693 /* If we are comparing (and (lshiftrt X C1) C2) for equality with 12694 zero and X is a comparison and C1 and C2 describe only bits set 12695 in STORE_FLAG_VALUE, we can compare with X. */ 12696 if (const_op == 0 && equality_comparison_p 12697 && mode_width <= HOST_BITS_PER_WIDE_INT 12698 && CONST_INT_P (XEXP (op0, 1)) 12699 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 12700 && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) 12701 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 12702 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) 12703 { 12704 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 12705 << INTVAL (XEXP (XEXP (op0, 0), 1))); 12706 if ((~STORE_FLAG_VALUE & mask) == 0 12707 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0)) 12708 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 12709 && COMPARISON_P (tem)))) 12710 { 12711 op0 = XEXP (XEXP (op0, 0), 0); 12712 continue; 12713 } 12714 } 12715 12716 /* If we are doing an equality comparison of an AND of a bit equal 12717 to the sign bit, replace this with a LT or GE comparison of 12718 the underlying value. */ 12719 if (equality_comparison_p 12720 && const_op == 0 12721 && CONST_INT_P (XEXP (op0, 1)) 12722 && mode_width <= HOST_BITS_PER_WIDE_INT 12723 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 12724 == HOST_WIDE_INT_1U << (mode_width - 1))) 12725 { 12726 op0 = XEXP (op0, 0); 12727 code = (code == EQ ? GE : LT); 12728 continue; 12729 } 12730 12731 /* If this AND operation is really a ZERO_EXTEND from a narrower 12732 mode, the constant fits within that mode, and this is either an 12733 equality or unsigned comparison, try to do this comparison in 12734 the narrower mode. 12735 12736 Note that in: 12737 12738 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0)) 12739 -> (ne:DI (reg:SI 4) (const_int 0)) 12740 12741 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is 12742 known to hold a value of the required mode the 12743 transformation is invalid. */ 12744 if ((equality_comparison_p || unsigned_comparison_p) 12745 && CONST_INT_P (XEXP (op0, 1)) 12746 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1)) 12747 & GET_MODE_MASK (mode)) 12748 + 1)) >= 0 12749 && const_op >> i == 0 12750 && int_mode_for_size (i, 1).exists (&tmode)) 12751 { 12752 op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0)); 12753 continue; 12754 } 12755 12756 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1 12757 fits in both M1 and M2 and the SUBREG is either paradoxical 12758 or represents the low part, permute the SUBREG and the AND 12759 and try again. */ 12760 if (GET_CODE (XEXP (op0, 0)) == SUBREG 12761 && CONST_INT_P (XEXP (op0, 1))) 12762 { 12763 unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1)); 12764 /* Require an integral mode, to avoid creating something like 12765 (AND:SF ...). */ 12766 if ((is_a <scalar_int_mode> 12767 (GET_MODE (SUBREG_REG (XEXP (op0, 0))), &tmode)) 12768 /* It is unsafe to commute the AND into the SUBREG if the 12769 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is 12770 not defined. As originally written the upper bits 12771 have a defined value due to the AND operation. 12772 However, if we commute the AND inside the SUBREG then 12773 they no longer have defined values and the meaning of 12774 the code has been changed. 12775 Also C1 should not change value in the smaller mode, 12776 see PR67028 (a positive C1 can become negative in the 12777 smaller mode, so that the AND does no longer mask the 12778 upper bits). */ 12779 && ((WORD_REGISTER_OPERATIONS 12780 && mode_width > GET_MODE_PRECISION (tmode) 12781 && mode_width <= BITS_PER_WORD 12782 && trunc_int_for_mode (c1, tmode) == (HOST_WIDE_INT) c1) 12783 || (mode_width <= GET_MODE_PRECISION (tmode) 12784 && subreg_lowpart_p (XEXP (op0, 0)))) 12785 && mode_width <= HOST_BITS_PER_WIDE_INT 12786 && HWI_COMPUTABLE_MODE_P (tmode) 12787 && (c1 & ~mask) == 0 12788 && (c1 & ~GET_MODE_MASK (tmode)) == 0 12789 && c1 != mask 12790 && c1 != GET_MODE_MASK (tmode)) 12791 { 12792 op0 = simplify_gen_binary (AND, tmode, 12793 SUBREG_REG (XEXP (op0, 0)), 12794 gen_int_mode (c1, tmode)); 12795 op0 = gen_lowpart (mode, op0); 12796 continue; 12797 } 12798 } 12799 12800 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */ 12801 if (const_op == 0 && equality_comparison_p 12802 && XEXP (op0, 1) == const1_rtx 12803 && GET_CODE (XEXP (op0, 0)) == NOT) 12804 { 12805 op0 = simplify_and_const_int (NULL_RTX, mode, 12806 XEXP (XEXP (op0, 0), 0), 1); 12807 code = (code == NE ? EQ : NE); 12808 continue; 12809 } 12810 12811 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to 12812 (eq (and (lshiftrt X) 1) 0). 12813 Also handle the case where (not X) is expressed using xor. */ 12814 if (const_op == 0 && equality_comparison_p 12815 && XEXP (op0, 1) == const1_rtx 12816 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT) 12817 { 12818 rtx shift_op = XEXP (XEXP (op0, 0), 0); 12819 rtx shift_count = XEXP (XEXP (op0, 0), 1); 12820 12821 if (GET_CODE (shift_op) == NOT 12822 || (GET_CODE (shift_op) == XOR 12823 && CONST_INT_P (XEXP (shift_op, 1)) 12824 && CONST_INT_P (shift_count) 12825 && HWI_COMPUTABLE_MODE_P (mode) 12826 && (UINTVAL (XEXP (shift_op, 1)) 12827 == HOST_WIDE_INT_1U 12828 << INTVAL (shift_count)))) 12829 { 12830 op0 12831 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count); 12832 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1); 12833 code = (code == NE ? EQ : NE); 12834 continue; 12835 } 12836 } 12837 break; 12838 12839 case ASHIFT: 12840 /* If we have (compare (ashift FOO N) (const_int C)) and 12841 the high order N bits of FOO (N+1 if an inequality comparison) 12842 are known to be zero, we can do this by comparing FOO with C 12843 shifted right N bits so long as the low-order N bits of C are 12844 zero. */ 12845 if (CONST_INT_P (XEXP (op0, 1)) 12846 && INTVAL (XEXP (op0, 1)) >= 0 12847 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) 12848 < HOST_BITS_PER_WIDE_INT) 12849 && (((unsigned HOST_WIDE_INT) const_op 12850 & ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1))) 12851 - 1)) == 0) 12852 && mode_width <= HOST_BITS_PER_WIDE_INT 12853 && (nonzero_bits (XEXP (op0, 0), mode) 12854 & ~(mask >> (INTVAL (XEXP (op0, 1)) 12855 + ! equality_comparison_p))) == 0) 12856 { 12857 /* We must perform a logical shift, not an arithmetic one, 12858 as we want the top N bits of C to be zero. */ 12859 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); 12860 12861 temp >>= INTVAL (XEXP (op0, 1)); 12862 op1 = gen_int_mode (temp, mode); 12863 op0 = XEXP (op0, 0); 12864 continue; 12865 } 12866 12867 /* If we are doing a sign bit comparison, it means we are testing 12868 a particular bit. Convert it to the appropriate AND. */ 12869 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1)) 12870 && mode_width <= HOST_BITS_PER_WIDE_INT) 12871 { 12872 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 12873 (HOST_WIDE_INT_1U 12874 << (mode_width - 1 12875 - INTVAL (XEXP (op0, 1))))); 12876 code = (code == LT ? NE : EQ); 12877 continue; 12878 } 12879 12880 /* If this an equality comparison with zero and we are shifting 12881 the low bit to the sign bit, we can convert this to an AND of the 12882 low-order bit. */ 12883 if (const_op == 0 && equality_comparison_p 12884 && CONST_INT_P (XEXP (op0, 1)) 12885 && UINTVAL (XEXP (op0, 1)) == mode_width - 1) 12886 { 12887 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1); 12888 continue; 12889 } 12890 break; 12891 12892 case ASHIFTRT: 12893 /* If this is an equality comparison with zero, we can do this 12894 as a logical shift, which might be much simpler. */ 12895 if (equality_comparison_p && const_op == 0 12896 && CONST_INT_P (XEXP (op0, 1))) 12897 { 12898 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, 12899 XEXP (op0, 0), 12900 INTVAL (XEXP (op0, 1))); 12901 continue; 12902 } 12903 12904 /* If OP0 is a sign extension and CODE is not an unsigned comparison, 12905 do the comparison in a narrower mode. */ 12906 if (! unsigned_comparison_p 12907 && CONST_INT_P (XEXP (op0, 1)) 12908 && GET_CODE (XEXP (op0, 0)) == ASHIFT 12909 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 12910 && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1) 12911 .exists (&tmode)) 12912 && (((unsigned HOST_WIDE_INT) const_op 12913 + (GET_MODE_MASK (tmode) >> 1) + 1) 12914 <= GET_MODE_MASK (tmode))) 12915 { 12916 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0)); 12917 continue; 12918 } 12919 12920 /* Likewise if OP0 is a PLUS of a sign extension with a 12921 constant, which is usually represented with the PLUS 12922 between the shifts. */ 12923 if (! unsigned_comparison_p 12924 && CONST_INT_P (XEXP (op0, 1)) 12925 && GET_CODE (XEXP (op0, 0)) == PLUS 12926 && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) 12927 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT 12928 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) 12929 && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1) 12930 .exists (&tmode)) 12931 && (((unsigned HOST_WIDE_INT) const_op 12932 + (GET_MODE_MASK (tmode) >> 1) + 1) 12933 <= GET_MODE_MASK (tmode))) 12934 { 12935 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); 12936 rtx add_const = XEXP (XEXP (op0, 0), 1); 12937 rtx new_const = simplify_gen_binary (ASHIFTRT, mode, 12938 add_const, XEXP (op0, 1)); 12939 12940 op0 = simplify_gen_binary (PLUS, tmode, 12941 gen_lowpart (tmode, inner), 12942 new_const); 12943 continue; 12944 } 12945 12946 /* FALLTHROUGH */ 12947 case LSHIFTRT: 12948 /* If we have (compare (xshiftrt FOO N) (const_int C)) and 12949 the low order N bits of FOO are known to be zero, we can do this 12950 by comparing FOO with C shifted left N bits so long as no 12951 overflow occurs. Even if the low order N bits of FOO aren't known 12952 to be zero, if the comparison is >= or < we can use the same 12953 optimization and for > or <= by setting all the low 12954 order N bits in the comparison constant. */ 12955 if (CONST_INT_P (XEXP (op0, 1)) 12956 && INTVAL (XEXP (op0, 1)) > 0 12957 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 12958 && mode_width <= HOST_BITS_PER_WIDE_INT 12959 && (((unsigned HOST_WIDE_INT) const_op 12960 + (GET_CODE (op0) != LSHIFTRT 12961 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) 12962 + 1) 12963 : 0)) 12964 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) 12965 { 12966 unsigned HOST_WIDE_INT low_bits 12967 = (nonzero_bits (XEXP (op0, 0), mode) 12968 & ((HOST_WIDE_INT_1U 12969 << INTVAL (XEXP (op0, 1))) - 1)); 12970 if (low_bits == 0 || !equality_comparison_p) 12971 { 12972 /* If the shift was logical, then we must make the condition 12973 unsigned. */ 12974 if (GET_CODE (op0) == LSHIFTRT) 12975 code = unsigned_condition (code); 12976 12977 const_op = (unsigned HOST_WIDE_INT) const_op 12978 << INTVAL (XEXP (op0, 1)); 12979 if (low_bits != 0 12980 && (code == GT || code == GTU 12981 || code == LE || code == LEU)) 12982 const_op 12983 |= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1); 12984 op1 = GEN_INT (const_op); 12985 op0 = XEXP (op0, 0); 12986 continue; 12987 } 12988 } 12989 12990 /* If we are using this shift to extract just the sign bit, we 12991 can replace this with an LT or GE comparison. */ 12992 if (const_op == 0 12993 && (equality_comparison_p || sign_bit_comparison_p) 12994 && CONST_INT_P (XEXP (op0, 1)) 12995 && UINTVAL (XEXP (op0, 1)) == mode_width - 1) 12996 { 12997 op0 = XEXP (op0, 0); 12998 code = (code == NE || code == GT ? LT : GE); 12999 continue; 13000 } 13001 break; 13002 13003 default: 13004 break; 13005 } 13006 13007 break; 13008 } 13009 13010 /* Now make any compound operations involved in this comparison. Then, 13011 check for an outmost SUBREG on OP0 that is not doing anything or is 13012 paradoxical. The latter transformation must only be performed when 13013 it is known that the "extra" bits will be the same in op0 and op1 or 13014 that they don't matter. There are three cases to consider: 13015 13016 1. SUBREG_REG (op0) is a register. In this case the bits are don't 13017 care bits and we can assume they have any convenient value. So 13018 making the transformation is safe. 13019 13020 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN. 13021 In this case the upper bits of op0 are undefined. We should not make 13022 the simplification in that case as we do not know the contents of 13023 those bits. 13024 13025 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN. 13026 In that case we know those bits are zeros or ones. We must also be 13027 sure that they are the same as the upper bits of op1. 13028 13029 We can never remove a SUBREG for a non-equality comparison because 13030 the sign bit is in a different place in the underlying object. */ 13031 13032 rtx_code op0_mco_code = SET; 13033 if (op1 == const0_rtx) 13034 op0_mco_code = code == NE || code == EQ ? EQ : COMPARE; 13035 13036 op0 = make_compound_operation (op0, op0_mco_code); 13037 op1 = make_compound_operation (op1, SET); 13038 13039 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 13040 && is_int_mode (GET_MODE (op0), &mode) 13041 && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode) 13042 && (code == NE || code == EQ)) 13043 { 13044 if (paradoxical_subreg_p (op0)) 13045 { 13046 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't 13047 implemented. */ 13048 if (REG_P (SUBREG_REG (op0))) 13049 { 13050 op0 = SUBREG_REG (op0); 13051 op1 = gen_lowpart (inner_mode, op1); 13052 } 13053 } 13054 else if (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT 13055 && (nonzero_bits (SUBREG_REG (op0), inner_mode) 13056 & ~GET_MODE_MASK (mode)) == 0) 13057 { 13058 tem = gen_lowpart (inner_mode, op1); 13059 13060 if ((nonzero_bits (tem, inner_mode) & ~GET_MODE_MASK (mode)) == 0) 13061 op0 = SUBREG_REG (op0), op1 = tem; 13062 } 13063 } 13064 13065 /* We now do the opposite procedure: Some machines don't have compare 13066 insns in all modes. If OP0's mode is an integer mode smaller than a 13067 word and we can't do a compare in that mode, see if there is a larger 13068 mode for which we can do the compare. There are a number of cases in 13069 which we can use the wider mode. */ 13070 13071 if (is_int_mode (GET_MODE (op0), &mode) 13072 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 13073 && ! have_insn_for (COMPARE, mode)) 13074 FOR_EACH_WIDER_MODE (tmode_iter, mode) 13075 { 13076 tmode = tmode_iter.require (); 13077 if (!HWI_COMPUTABLE_MODE_P (tmode)) 13078 break; 13079 if (have_insn_for (COMPARE, tmode)) 13080 { 13081 int zero_extended; 13082 13083 /* If this is a test for negative, we can make an explicit 13084 test of the sign bit. Test this first so we can use 13085 a paradoxical subreg to extend OP0. */ 13086 13087 if (op1 == const0_rtx && (code == LT || code == GE) 13088 && HWI_COMPUTABLE_MODE_P (mode)) 13089 { 13090 unsigned HOST_WIDE_INT sign 13091 = HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1); 13092 op0 = simplify_gen_binary (AND, tmode, 13093 gen_lowpart (tmode, op0), 13094 gen_int_mode (sign, tmode)); 13095 code = (code == LT) ? NE : EQ; 13096 break; 13097 } 13098 13099 /* If the only nonzero bits in OP0 and OP1 are those in the 13100 narrower mode and this is an equality or unsigned comparison, 13101 we can use the wider mode. Similarly for sign-extended 13102 values, in which case it is true for all comparisons. */ 13103 zero_extended = ((code == EQ || code == NE 13104 || code == GEU || code == GTU 13105 || code == LEU || code == LTU) 13106 && (nonzero_bits (op0, tmode) 13107 & ~GET_MODE_MASK (mode)) == 0 13108 && ((CONST_INT_P (op1) 13109 || (nonzero_bits (op1, tmode) 13110 & ~GET_MODE_MASK (mode)) == 0))); 13111 13112 if (zero_extended 13113 || ((num_sign_bit_copies (op0, tmode) 13114 > (unsigned int) (GET_MODE_PRECISION (tmode) 13115 - GET_MODE_PRECISION (mode))) 13116 && (num_sign_bit_copies (op1, tmode) 13117 > (unsigned int) (GET_MODE_PRECISION (tmode) 13118 - GET_MODE_PRECISION (mode))))) 13119 { 13120 /* If OP0 is an AND and we don't have an AND in MODE either, 13121 make a new AND in the proper mode. */ 13122 if (GET_CODE (op0) == AND 13123 && !have_insn_for (AND, mode)) 13124 op0 = simplify_gen_binary (AND, tmode, 13125 gen_lowpart (tmode, 13126 XEXP (op0, 0)), 13127 gen_lowpart (tmode, 13128 XEXP (op0, 1))); 13129 else 13130 { 13131 if (zero_extended) 13132 { 13133 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, 13134 op0, mode); 13135 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, 13136 op1, mode); 13137 } 13138 else 13139 { 13140 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, 13141 op0, mode); 13142 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, 13143 op1, mode); 13144 } 13145 break; 13146 } 13147 } 13148 } 13149 } 13150 13151 /* We may have changed the comparison operands. Re-canonicalize. */ 13152 if (swap_commutative_operands_p (op0, op1)) 13153 { 13154 std::swap (op0, op1); 13155 code = swap_condition (code); 13156 } 13157 13158 /* If this machine only supports a subset of valid comparisons, see if we 13159 can convert an unsupported one into a supported one. */ 13160 target_canonicalize_comparison (&code, &op0, &op1, 0); 13161 13162 *pop0 = op0; 13163 *pop1 = op1; 13164 13165 return code; 13166 } 13167 13168 /* Utility function for record_value_for_reg. Count number of 13169 rtxs in X. */ 13170 static int 13171 count_rtxs (rtx x) 13172 { 13173 enum rtx_code code = GET_CODE (x); 13174 const char *fmt; 13175 int i, j, ret = 1; 13176 13177 if (GET_RTX_CLASS (code) == RTX_BIN_ARITH 13178 || GET_RTX_CLASS (code) == RTX_COMM_ARITH) 13179 { 13180 rtx x0 = XEXP (x, 0); 13181 rtx x1 = XEXP (x, 1); 13182 13183 if (x0 == x1) 13184 return 1 + 2 * count_rtxs (x0); 13185 13186 if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH 13187 || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH) 13188 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 13189 return 2 + 2 * count_rtxs (x0) 13190 + count_rtxs (x == XEXP (x1, 0) 13191 ? XEXP (x1, 1) : XEXP (x1, 0)); 13192 13193 if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH 13194 || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH) 13195 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 13196 return 2 + 2 * count_rtxs (x1) 13197 + count_rtxs (x == XEXP (x0, 0) 13198 ? XEXP (x0, 1) : XEXP (x0, 0)); 13199 } 13200 13201 fmt = GET_RTX_FORMAT (code); 13202 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 13203 if (fmt[i] == 'e') 13204 ret += count_rtxs (XEXP (x, i)); 13205 else if (fmt[i] == 'E') 13206 for (j = 0; j < XVECLEN (x, i); j++) 13207 ret += count_rtxs (XVECEXP (x, i, j)); 13208 13209 return ret; 13210 } 13211 13212 /* Utility function for following routine. Called when X is part of a value 13213 being stored into last_set_value. Sets last_set_table_tick 13214 for each register mentioned. Similar to mention_regs in cse.c */ 13215 13216 static void 13217 update_table_tick (rtx x) 13218 { 13219 enum rtx_code code = GET_CODE (x); 13220 const char *fmt = GET_RTX_FORMAT (code); 13221 int i, j; 13222 13223 if (code == REG) 13224 { 13225 unsigned int regno = REGNO (x); 13226 unsigned int endregno = END_REGNO (x); 13227 unsigned int r; 13228 13229 for (r = regno; r < endregno; r++) 13230 { 13231 reg_stat_type *rsp = ®_stat[r]; 13232 rsp->last_set_table_tick = label_tick; 13233 } 13234 13235 return; 13236 } 13237 13238 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 13239 if (fmt[i] == 'e') 13240 { 13241 /* Check for identical subexpressions. If x contains 13242 identical subexpression we only have to traverse one of 13243 them. */ 13244 if (i == 0 && ARITHMETIC_P (x)) 13245 { 13246 /* Note that at this point x1 has already been 13247 processed. */ 13248 rtx x0 = XEXP (x, 0); 13249 rtx x1 = XEXP (x, 1); 13250 13251 /* If x0 and x1 are identical then there is no need to 13252 process x0. */ 13253 if (x0 == x1) 13254 break; 13255 13256 /* If x0 is identical to a subexpression of x1 then while 13257 processing x1, x0 has already been processed. Thus we 13258 are done with x. */ 13259 if (ARITHMETIC_P (x1) 13260 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 13261 break; 13262 13263 /* If x1 is identical to a subexpression of x0 then we 13264 still have to process the rest of x0. */ 13265 if (ARITHMETIC_P (x0) 13266 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 13267 { 13268 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0)); 13269 break; 13270 } 13271 } 13272 13273 update_table_tick (XEXP (x, i)); 13274 } 13275 else if (fmt[i] == 'E') 13276 for (j = 0; j < XVECLEN (x, i); j++) 13277 update_table_tick (XVECEXP (x, i, j)); 13278 } 13279 13280 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we 13281 are saying that the register is clobbered and we no longer know its 13282 value. If INSN is zero, don't update reg_stat[].last_set; this is 13283 only permitted with VALUE also zero and is used to invalidate the 13284 register. */ 13285 13286 static void 13287 record_value_for_reg (rtx reg, rtx_insn *insn, rtx value) 13288 { 13289 unsigned int regno = REGNO (reg); 13290 unsigned int endregno = END_REGNO (reg); 13291 unsigned int i; 13292 reg_stat_type *rsp; 13293 13294 /* If VALUE contains REG and we have a previous value for REG, substitute 13295 the previous value. */ 13296 if (value && insn && reg_overlap_mentioned_p (reg, value)) 13297 { 13298 rtx tem; 13299 13300 /* Set things up so get_last_value is allowed to see anything set up to 13301 our insn. */ 13302 subst_low_luid = DF_INSN_LUID (insn); 13303 tem = get_last_value (reg); 13304 13305 /* If TEM is simply a binary operation with two CLOBBERs as operands, 13306 it isn't going to be useful and will take a lot of time to process, 13307 so just use the CLOBBER. */ 13308 13309 if (tem) 13310 { 13311 if (ARITHMETIC_P (tem) 13312 && GET_CODE (XEXP (tem, 0)) == CLOBBER 13313 && GET_CODE (XEXP (tem, 1)) == CLOBBER) 13314 tem = XEXP (tem, 0); 13315 else if (count_occurrences (value, reg, 1) >= 2) 13316 { 13317 /* If there are two or more occurrences of REG in VALUE, 13318 prevent the value from growing too much. */ 13319 if (count_rtxs (tem) > param_max_last_value_rtl) 13320 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx); 13321 } 13322 13323 value = replace_rtx (copy_rtx (value), reg, tem); 13324 } 13325 } 13326 13327 /* For each register modified, show we don't know its value, that 13328 we don't know about its bitwise content, that its value has been 13329 updated, and that we don't know the location of the death of the 13330 register. */ 13331 for (i = regno; i < endregno; i++) 13332 { 13333 rsp = ®_stat[i]; 13334 13335 if (insn) 13336 rsp->last_set = insn; 13337 13338 rsp->last_set_value = 0; 13339 rsp->last_set_mode = VOIDmode; 13340 rsp->last_set_nonzero_bits = 0; 13341 rsp->last_set_sign_bit_copies = 0; 13342 rsp->last_death = 0; 13343 rsp->truncated_to_mode = VOIDmode; 13344 } 13345 13346 /* Mark registers that are being referenced in this value. */ 13347 if (value) 13348 update_table_tick (value); 13349 13350 /* Now update the status of each register being set. 13351 If someone is using this register in this block, set this register 13352 to invalid since we will get confused between the two lives in this 13353 basic block. This makes using this register always invalid. In cse, we 13354 scan the table to invalidate all entries using this register, but this 13355 is too much work for us. */ 13356 13357 for (i = regno; i < endregno; i++) 13358 { 13359 rsp = ®_stat[i]; 13360 rsp->last_set_label = label_tick; 13361 if (!insn 13362 || (value && rsp->last_set_table_tick >= label_tick_ebb_start)) 13363 rsp->last_set_invalid = 1; 13364 else 13365 rsp->last_set_invalid = 0; 13366 } 13367 13368 /* The value being assigned might refer to X (like in "x++;"). In that 13369 case, we must replace it with (clobber (const_int 0)) to prevent 13370 infinite loops. */ 13371 rsp = ®_stat[regno]; 13372 if (value && !get_last_value_validate (&value, insn, label_tick, 0)) 13373 { 13374 value = copy_rtx (value); 13375 if (!get_last_value_validate (&value, insn, label_tick, 1)) 13376 value = 0; 13377 } 13378 13379 /* For the main register being modified, update the value, the mode, the 13380 nonzero bits, and the number of sign bit copies. */ 13381 13382 rsp->last_set_value = value; 13383 13384 if (value) 13385 { 13386 machine_mode mode = GET_MODE (reg); 13387 subst_low_luid = DF_INSN_LUID (insn); 13388 rsp->last_set_mode = mode; 13389 if (GET_MODE_CLASS (mode) == MODE_INT 13390 && HWI_COMPUTABLE_MODE_P (mode)) 13391 mode = nonzero_bits_mode; 13392 rsp->last_set_nonzero_bits = nonzero_bits (value, mode); 13393 rsp->last_set_sign_bit_copies 13394 = num_sign_bit_copies (value, GET_MODE (reg)); 13395 } 13396 } 13397 13398 /* Called via note_stores from record_dead_and_set_regs to handle one 13399 SET or CLOBBER in an insn. DATA is the instruction in which the 13400 set is occurring. */ 13401 13402 static void 13403 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data) 13404 { 13405 rtx_insn *record_dead_insn = (rtx_insn *) data; 13406 13407 if (GET_CODE (dest) == SUBREG) 13408 dest = SUBREG_REG (dest); 13409 13410 if (!record_dead_insn) 13411 { 13412 if (REG_P (dest)) 13413 record_value_for_reg (dest, NULL, NULL_RTX); 13414 return; 13415 } 13416 13417 if (REG_P (dest)) 13418 { 13419 /* If we are setting the whole register, we know its value. Otherwise 13420 show that we don't know the value. We can handle a SUBREG if it's 13421 the low part, but we must be careful with paradoxical SUBREGs on 13422 RISC architectures because we cannot strip e.g. an extension around 13423 a load and record the naked load since the RTL middle-end considers 13424 that the upper bits are defined according to LOAD_EXTEND_OP. */ 13425 if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) 13426 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); 13427 else if (GET_CODE (setter) == SET 13428 && GET_CODE (SET_DEST (setter)) == SUBREG 13429 && SUBREG_REG (SET_DEST (setter)) == dest 13430 && known_le (GET_MODE_PRECISION (GET_MODE (dest)), 13431 BITS_PER_WORD) 13432 && subreg_lowpart_p (SET_DEST (setter))) 13433 record_value_for_reg (dest, record_dead_insn, 13434 WORD_REGISTER_OPERATIONS 13435 && word_register_operation_p (SET_SRC (setter)) 13436 && paradoxical_subreg_p (SET_DEST (setter)) 13437 ? SET_SRC (setter) 13438 : gen_lowpart (GET_MODE (dest), 13439 SET_SRC (setter))); 13440 else 13441 record_value_for_reg (dest, record_dead_insn, NULL_RTX); 13442 } 13443 else if (MEM_P (dest) 13444 /* Ignore pushes, they clobber nothing. */ 13445 && ! push_operand (dest, GET_MODE (dest))) 13446 mem_last_set = DF_INSN_LUID (record_dead_insn); 13447 } 13448 13449 /* Update the records of when each REG was most recently set or killed 13450 for the things done by INSN. This is the last thing done in processing 13451 INSN in the combiner loop. 13452 13453 We update reg_stat[], in particular fields last_set, last_set_value, 13454 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies, 13455 last_death, and also the similar information mem_last_set (which insn 13456 most recently modified memory) and last_call_luid (which insn was the 13457 most recent subroutine call). */ 13458 13459 static void 13460 record_dead_and_set_regs (rtx_insn *insn) 13461 { 13462 rtx link; 13463 unsigned int i; 13464 13465 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 13466 { 13467 if (REG_NOTE_KIND (link) == REG_DEAD 13468 && REG_P (XEXP (link, 0))) 13469 { 13470 unsigned int regno = REGNO (XEXP (link, 0)); 13471 unsigned int endregno = END_REGNO (XEXP (link, 0)); 13472 13473 for (i = regno; i < endregno; i++) 13474 { 13475 reg_stat_type *rsp; 13476 13477 rsp = ®_stat[i]; 13478 rsp->last_death = insn; 13479 } 13480 } 13481 else if (REG_NOTE_KIND (link) == REG_INC) 13482 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); 13483 } 13484 13485 if (CALL_P (insn)) 13486 { 13487 HARD_REG_SET callee_clobbers 13488 = insn_callee_abi (insn).full_and_partial_reg_clobbers (); 13489 hard_reg_set_iterator hrsi; 13490 EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, i, hrsi) 13491 { 13492 reg_stat_type *rsp; 13493 13494 /* ??? We could try to preserve some information from the last 13495 set of register I if the call doesn't actually clobber 13496 (reg:last_set_mode I), which might be true for ABIs with 13497 partial clobbers. However, it would be difficult to 13498 update last_set_nonzero_bits and last_sign_bit_copies 13499 to account for the part of I that actually was clobbered. 13500 It wouldn't help much anyway, since we rarely see this 13501 situation before RA. */ 13502 rsp = ®_stat[i]; 13503 rsp->last_set_invalid = 1; 13504 rsp->last_set = insn; 13505 rsp->last_set_value = 0; 13506 rsp->last_set_mode = VOIDmode; 13507 rsp->last_set_nonzero_bits = 0; 13508 rsp->last_set_sign_bit_copies = 0; 13509 rsp->last_death = 0; 13510 rsp->truncated_to_mode = VOIDmode; 13511 } 13512 13513 last_call_luid = mem_last_set = DF_INSN_LUID (insn); 13514 13515 /* We can't combine into a call pattern. Remember, though, that 13516 the return value register is set at this LUID. We could 13517 still replace a register with the return value from the 13518 wrong subroutine call! */ 13519 note_stores (insn, record_dead_and_set_regs_1, NULL_RTX); 13520 } 13521 else 13522 note_stores (insn, record_dead_and_set_regs_1, insn); 13523 } 13524 13525 /* If a SUBREG has the promoted bit set, it is in fact a property of the 13526 register present in the SUBREG, so for each such SUBREG go back and 13527 adjust nonzero and sign bit information of the registers that are 13528 known to have some zero/sign bits set. 13529 13530 This is needed because when combine blows the SUBREGs away, the 13531 information on zero/sign bits is lost and further combines can be 13532 missed because of that. */ 13533 13534 static void 13535 record_promoted_value (rtx_insn *insn, rtx subreg) 13536 { 13537 struct insn_link *links; 13538 rtx set; 13539 unsigned int regno = REGNO (SUBREG_REG (subreg)); 13540 machine_mode mode = GET_MODE (subreg); 13541 13542 if (!HWI_COMPUTABLE_MODE_P (mode)) 13543 return; 13544 13545 for (links = LOG_LINKS (insn); links;) 13546 { 13547 reg_stat_type *rsp; 13548 13549 insn = links->insn; 13550 set = single_set (insn); 13551 13552 if (! set || !REG_P (SET_DEST (set)) 13553 || REGNO (SET_DEST (set)) != regno 13554 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) 13555 { 13556 links = links->next; 13557 continue; 13558 } 13559 13560 rsp = ®_stat[regno]; 13561 if (rsp->last_set == insn) 13562 { 13563 if (SUBREG_PROMOTED_UNSIGNED_P (subreg)) 13564 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode); 13565 } 13566 13567 if (REG_P (SET_SRC (set))) 13568 { 13569 regno = REGNO (SET_SRC (set)); 13570 links = LOG_LINKS (insn); 13571 } 13572 else 13573 break; 13574 } 13575 } 13576 13577 /* Check if X, a register, is known to contain a value already 13578 truncated to MODE. In this case we can use a subreg to refer to 13579 the truncated value even though in the generic case we would need 13580 an explicit truncation. */ 13581 13582 static bool 13583 reg_truncated_to_mode (machine_mode mode, const_rtx x) 13584 { 13585 reg_stat_type *rsp = ®_stat[REGNO (x)]; 13586 machine_mode truncated = rsp->truncated_to_mode; 13587 13588 if (truncated == 0 13589 || rsp->truncation_label < label_tick_ebb_start) 13590 return false; 13591 if (!partial_subreg_p (mode, truncated)) 13592 return true; 13593 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated)) 13594 return true; 13595 return false; 13596 } 13597 13598 /* If X is a hard reg or a subreg record the mode that the register is 13599 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be 13600 able to turn a truncate into a subreg using this information. Return true 13601 if traversing X is complete. */ 13602 13603 static bool 13604 record_truncated_value (rtx x) 13605 { 13606 machine_mode truncated_mode; 13607 reg_stat_type *rsp; 13608 13609 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))) 13610 { 13611 machine_mode original_mode = GET_MODE (SUBREG_REG (x)); 13612 truncated_mode = GET_MODE (x); 13613 13614 if (!partial_subreg_p (truncated_mode, original_mode)) 13615 return true; 13616 13617 truncated_mode = GET_MODE (x); 13618 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode)) 13619 return true; 13620 13621 x = SUBREG_REG (x); 13622 } 13623 /* ??? For hard-regs we now record everything. We might be able to 13624 optimize this using last_set_mode. */ 13625 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) 13626 truncated_mode = GET_MODE (x); 13627 else 13628 return false; 13629 13630 rsp = ®_stat[REGNO (x)]; 13631 if (rsp->truncated_to_mode == 0 13632 || rsp->truncation_label < label_tick_ebb_start 13633 || partial_subreg_p (truncated_mode, rsp->truncated_to_mode)) 13634 { 13635 rsp->truncated_to_mode = truncated_mode; 13636 rsp->truncation_label = label_tick; 13637 } 13638 13639 return true; 13640 } 13641 13642 /* Callback for note_uses. Find hardregs and subregs of pseudos and 13643 the modes they are used in. This can help truning TRUNCATEs into 13644 SUBREGs. */ 13645 13646 static void 13647 record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED) 13648 { 13649 subrtx_var_iterator::array_type array; 13650 FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST) 13651 if (record_truncated_value (*iter)) 13652 iter.skip_subrtxes (); 13653 } 13654 13655 /* Scan X for promoted SUBREGs. For each one found, 13656 note what it implies to the registers used in it. */ 13657 13658 static void 13659 check_promoted_subreg (rtx_insn *insn, rtx x) 13660 { 13661 if (GET_CODE (x) == SUBREG 13662 && SUBREG_PROMOTED_VAR_P (x) 13663 && REG_P (SUBREG_REG (x))) 13664 record_promoted_value (insn, x); 13665 else 13666 { 13667 const char *format = GET_RTX_FORMAT (GET_CODE (x)); 13668 int i, j; 13669 13670 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) 13671 switch (format[i]) 13672 { 13673 case 'e': 13674 check_promoted_subreg (insn, XEXP (x, i)); 13675 break; 13676 case 'V': 13677 case 'E': 13678 if (XVEC (x, i) != 0) 13679 for (j = 0; j < XVECLEN (x, i); j++) 13680 check_promoted_subreg (insn, XVECEXP (x, i, j)); 13681 break; 13682 } 13683 } 13684 } 13685 13686 /* Verify that all the registers and memory references mentioned in *LOC are 13687 still valid. *LOC was part of a value set in INSN when label_tick was 13688 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace 13689 the invalid references with (clobber (const_int 0)) and return 1. This 13690 replacement is useful because we often can get useful information about 13691 the form of a value (e.g., if it was produced by a shift that always 13692 produces -1 or 0) even though we don't know exactly what registers it 13693 was produced from. */ 13694 13695 static int 13696 get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, int replace) 13697 { 13698 rtx x = *loc; 13699 const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); 13700 int len = GET_RTX_LENGTH (GET_CODE (x)); 13701 int i, j; 13702 13703 if (REG_P (x)) 13704 { 13705 unsigned int regno = REGNO (x); 13706 unsigned int endregno = END_REGNO (x); 13707 unsigned int j; 13708 13709 for (j = regno; j < endregno; j++) 13710 { 13711 reg_stat_type *rsp = ®_stat[j]; 13712 if (rsp->last_set_invalid 13713 /* If this is a pseudo-register that was only set once and not 13714 live at the beginning of the function, it is always valid. */ 13715 || (! (regno >= FIRST_PSEUDO_REGISTER 13716 && regno < reg_n_sets_max 13717 && REG_N_SETS (regno) == 1 13718 && (!REGNO_REG_SET_P 13719 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), 13720 regno))) 13721 && rsp->last_set_label > tick)) 13722 { 13723 if (replace) 13724 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 13725 return replace; 13726 } 13727 } 13728 13729 return 1; 13730 } 13731 /* If this is a memory reference, make sure that there were no stores after 13732 it that might have clobbered the value. We don't have alias info, so we 13733 assume any store invalidates it. Moreover, we only have local UIDs, so 13734 we also assume that there were stores in the intervening basic blocks. */ 13735 else if (MEM_P (x) && !MEM_READONLY_P (x) 13736 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set)) 13737 { 13738 if (replace) 13739 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 13740 return replace; 13741 } 13742 13743 for (i = 0; i < len; i++) 13744 { 13745 if (fmt[i] == 'e') 13746 { 13747 /* Check for identical subexpressions. If x contains 13748 identical subexpression we only have to traverse one of 13749 them. */ 13750 if (i == 1 && ARITHMETIC_P (x)) 13751 { 13752 /* Note that at this point x0 has already been checked 13753 and found valid. */ 13754 rtx x0 = XEXP (x, 0); 13755 rtx x1 = XEXP (x, 1); 13756 13757 /* If x0 and x1 are identical then x is also valid. */ 13758 if (x0 == x1) 13759 return 1; 13760 13761 /* If x1 is identical to a subexpression of x0 then 13762 while checking x0, x1 has already been checked. Thus 13763 it is valid and so as x. */ 13764 if (ARITHMETIC_P (x0) 13765 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 13766 return 1; 13767 13768 /* If x0 is identical to a subexpression of x1 then x is 13769 valid iff the rest of x1 is valid. */ 13770 if (ARITHMETIC_P (x1) 13771 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 13772 return 13773 get_last_value_validate (&XEXP (x1, 13774 x0 == XEXP (x1, 0) ? 1 : 0), 13775 insn, tick, replace); 13776 } 13777 13778 if (get_last_value_validate (&XEXP (x, i), insn, tick, 13779 replace) == 0) 13780 return 0; 13781 } 13782 else if (fmt[i] == 'E') 13783 for (j = 0; j < XVECLEN (x, i); j++) 13784 if (get_last_value_validate (&XVECEXP (x, i, j), 13785 insn, tick, replace) == 0) 13786 return 0; 13787 } 13788 13789 /* If we haven't found a reason for it to be invalid, it is valid. */ 13790 return 1; 13791 } 13792 13793 /* Get the last value assigned to X, if known. Some registers 13794 in the value may be replaced with (clobber (const_int 0)) if their value 13795 is known longer known reliably. */ 13796 13797 static rtx 13798 get_last_value (const_rtx x) 13799 { 13800 unsigned int regno; 13801 rtx value; 13802 reg_stat_type *rsp; 13803 13804 /* If this is a non-paradoxical SUBREG, get the value of its operand and 13805 then convert it to the desired mode. If this is a paradoxical SUBREG, 13806 we cannot predict what values the "extra" bits might have. */ 13807 if (GET_CODE (x) == SUBREG 13808 && subreg_lowpart_p (x) 13809 && !paradoxical_subreg_p (x) 13810 && (value = get_last_value (SUBREG_REG (x))) != 0) 13811 return gen_lowpart (GET_MODE (x), value); 13812 13813 if (!REG_P (x)) 13814 return 0; 13815 13816 regno = REGNO (x); 13817 rsp = ®_stat[regno]; 13818 value = rsp->last_set_value; 13819 13820 /* If we don't have a value, or if it isn't for this basic block and 13821 it's either a hard register, set more than once, or it's a live 13822 at the beginning of the function, return 0. 13823 13824 Because if it's not live at the beginning of the function then the reg 13825 is always set before being used (is never used without being set). 13826 And, if it's set only once, and it's always set before use, then all 13827 uses must have the same last value, even if it's not from this basic 13828 block. */ 13829 13830 if (value == 0 13831 || (rsp->last_set_label < label_tick_ebb_start 13832 && (regno < FIRST_PSEUDO_REGISTER 13833 || regno >= reg_n_sets_max 13834 || REG_N_SETS (regno) != 1 13835 || REGNO_REG_SET_P 13836 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno)))) 13837 return 0; 13838 13839 /* If the value was set in a later insn than the ones we are processing, 13840 we can't use it even if the register was only set once. */ 13841 if (rsp->last_set_label == label_tick 13842 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid) 13843 return 0; 13844 13845 /* If fewer bits were set than what we are asked for now, we cannot use 13846 the value. */ 13847 if (maybe_lt (GET_MODE_PRECISION (rsp->last_set_mode), 13848 GET_MODE_PRECISION (GET_MODE (x)))) 13849 return 0; 13850 13851 /* If the value has all its registers valid, return it. */ 13852 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0)) 13853 return value; 13854 13855 /* Otherwise, make a copy and replace any invalid register with 13856 (clobber (const_int 0)). If that fails for some reason, return 0. */ 13857 13858 value = copy_rtx (value); 13859 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1)) 13860 return value; 13861 13862 return 0; 13863 } 13864 13865 /* Define three variables used for communication between the following 13866 routines. */ 13867 13868 static unsigned int reg_dead_regno, reg_dead_endregno; 13869 static int reg_dead_flag; 13870 rtx reg_dead_reg; 13871 13872 /* Function called via note_stores from reg_dead_at_p. 13873 13874 If DEST is within [reg_dead_regno, reg_dead_endregno), set 13875 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ 13876 13877 static void 13878 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) 13879 { 13880 unsigned int regno, endregno; 13881 13882 if (!REG_P (dest)) 13883 return; 13884 13885 regno = REGNO (dest); 13886 endregno = END_REGNO (dest); 13887 if (reg_dead_endregno > regno && reg_dead_regno < endregno) 13888 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; 13889 } 13890 13891 /* Return nonzero if REG is known to be dead at INSN. 13892 13893 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER 13894 referencing REG, it is dead. If we hit a SET referencing REG, it is 13895 live. Otherwise, see if it is live or dead at the start of the basic 13896 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS 13897 must be assumed to be always live. */ 13898 13899 static int 13900 reg_dead_at_p (rtx reg, rtx_insn *insn) 13901 { 13902 basic_block block; 13903 unsigned int i; 13904 13905 /* Set variables for reg_dead_at_p_1. */ 13906 reg_dead_regno = REGNO (reg); 13907 reg_dead_endregno = END_REGNO (reg); 13908 reg_dead_reg = reg; 13909 13910 reg_dead_flag = 0; 13911 13912 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers 13913 we allow the machine description to decide whether use-and-clobber 13914 patterns are OK. */ 13915 if (reg_dead_regno < FIRST_PSEUDO_REGISTER) 13916 { 13917 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 13918 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i)) 13919 return 0; 13920 } 13921 13922 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or 13923 beginning of basic block. */ 13924 block = BLOCK_FOR_INSN (insn); 13925 for (;;) 13926 { 13927 if (INSN_P (insn)) 13928 { 13929 if (find_regno_note (insn, REG_UNUSED, reg_dead_regno)) 13930 return 1; 13931 13932 note_stores (insn, reg_dead_at_p_1, NULL); 13933 if (reg_dead_flag) 13934 return reg_dead_flag == 1 ? 1 : 0; 13935 13936 if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) 13937 return 1; 13938 } 13939 13940 if (insn == BB_HEAD (block)) 13941 break; 13942 13943 insn = PREV_INSN (insn); 13944 } 13945 13946 /* Look at live-in sets for the basic block that we were in. */ 13947 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 13948 if (REGNO_REG_SET_P (df_get_live_in (block), i)) 13949 return 0; 13950 13951 return 1; 13952 } 13953 13954 /* Note hard registers in X that are used. */ 13955 13956 static void 13957 mark_used_regs_combine (rtx x) 13958 { 13959 RTX_CODE code = GET_CODE (x); 13960 unsigned int regno; 13961 int i; 13962 13963 switch (code) 13964 { 13965 case LABEL_REF: 13966 case SYMBOL_REF: 13967 case CONST: 13968 CASE_CONST_ANY: 13969 case PC: 13970 case ADDR_VEC: 13971 case ADDR_DIFF_VEC: 13972 case ASM_INPUT: 13973 /* CC0 must die in the insn after it is set, so we don't need to take 13974 special note of it here. */ 13975 case CC0: 13976 return; 13977 13978 case CLOBBER: 13979 /* If we are clobbering a MEM, mark any hard registers inside the 13980 address as used. */ 13981 if (MEM_P (XEXP (x, 0))) 13982 mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); 13983 return; 13984 13985 case REG: 13986 regno = REGNO (x); 13987 /* A hard reg in a wide mode may really be multiple registers. 13988 If so, mark all of them just like the first. */ 13989 if (regno < FIRST_PSEUDO_REGISTER) 13990 { 13991 /* None of this applies to the stack, frame or arg pointers. */ 13992 if (regno == STACK_POINTER_REGNUM 13993 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER 13994 && regno == HARD_FRAME_POINTER_REGNUM) 13995 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 13996 && regno == ARG_POINTER_REGNUM && fixed_regs[regno]) 13997 || regno == FRAME_POINTER_REGNUM) 13998 return; 13999 14000 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno); 14001 } 14002 return; 14003 14004 case SET: 14005 { 14006 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in 14007 the address. */ 14008 rtx testreg = SET_DEST (x); 14009 14010 while (GET_CODE (testreg) == SUBREG 14011 || GET_CODE (testreg) == ZERO_EXTRACT 14012 || GET_CODE (testreg) == STRICT_LOW_PART) 14013 testreg = XEXP (testreg, 0); 14014 14015 if (MEM_P (testreg)) 14016 mark_used_regs_combine (XEXP (testreg, 0)); 14017 14018 mark_used_regs_combine (SET_SRC (x)); 14019 } 14020 return; 14021 14022 default: 14023 break; 14024 } 14025 14026 /* Recursively scan the operands of this expression. */ 14027 14028 { 14029 const char *fmt = GET_RTX_FORMAT (code); 14030 14031 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 14032 { 14033 if (fmt[i] == 'e') 14034 mark_used_regs_combine (XEXP (x, i)); 14035 else if (fmt[i] == 'E') 14036 { 14037 int j; 14038 14039 for (j = 0; j < XVECLEN (x, i); j++) 14040 mark_used_regs_combine (XVECEXP (x, i, j)); 14041 } 14042 } 14043 } 14044 } 14045 14046 /* Remove register number REGNO from the dead registers list of INSN. 14047 14048 Return the note used to record the death, if there was one. */ 14049 14050 rtx 14051 remove_death (unsigned int regno, rtx_insn *insn) 14052 { 14053 rtx note = find_regno_note (insn, REG_DEAD, regno); 14054 14055 if (note) 14056 remove_note (insn, note); 14057 14058 return note; 14059 } 14060 14061 /* For each register (hardware or pseudo) used within expression X, if its 14062 death is in an instruction with luid between FROM_LUID (inclusive) and 14063 TO_INSN (exclusive), put a REG_DEAD note for that register in the 14064 list headed by PNOTES. 14065 14066 That said, don't move registers killed by maybe_kill_insn. 14067 14068 This is done when X is being merged by combination into TO_INSN. These 14069 notes will then be distributed as needed. */ 14070 14071 static void 14072 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn, 14073 rtx *pnotes) 14074 { 14075 const char *fmt; 14076 int len, i; 14077 enum rtx_code code = GET_CODE (x); 14078 14079 if (code == REG) 14080 { 14081 unsigned int regno = REGNO (x); 14082 rtx_insn *where_dead = reg_stat[regno].last_death; 14083 14084 /* If we do not know where the register died, it may still die between 14085 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */ 14086 if (!where_dead || DF_INSN_LUID (where_dead) >= DF_INSN_LUID (to_insn)) 14087 { 14088 rtx_insn *insn = prev_real_nondebug_insn (to_insn); 14089 while (insn 14090 && BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (to_insn) 14091 && DF_INSN_LUID (insn) >= from_luid) 14092 { 14093 if (dead_or_set_regno_p (insn, regno)) 14094 { 14095 if (find_regno_note (insn, REG_DEAD, regno)) 14096 where_dead = insn; 14097 break; 14098 } 14099 14100 insn = prev_real_nondebug_insn (insn); 14101 } 14102 } 14103 14104 /* Don't move the register if it gets killed in between from and to. */ 14105 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) 14106 && ! reg_referenced_p (x, maybe_kill_insn)) 14107 return; 14108 14109 if (where_dead 14110 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn) 14111 && DF_INSN_LUID (where_dead) >= from_luid 14112 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn)) 14113 { 14114 rtx note = remove_death (regno, where_dead); 14115 14116 /* It is possible for the call above to return 0. This can occur 14117 when last_death points to I2 or I1 that we combined with. 14118 In that case make a new note. 14119 14120 We must also check for the case where X is a hard register 14121 and NOTE is a death note for a range of hard registers 14122 including X. In that case, we must put REG_DEAD notes for 14123 the remaining registers in place of NOTE. */ 14124 14125 if (note != 0 && regno < FIRST_PSEUDO_REGISTER 14126 && partial_subreg_p (GET_MODE (x), GET_MODE (XEXP (note, 0)))) 14127 { 14128 unsigned int deadregno = REGNO (XEXP (note, 0)); 14129 unsigned int deadend = END_REGNO (XEXP (note, 0)); 14130 unsigned int ourend = END_REGNO (x); 14131 unsigned int i; 14132 14133 for (i = deadregno; i < deadend; i++) 14134 if (i < regno || i >= ourend) 14135 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]); 14136 } 14137 14138 /* If we didn't find any note, or if we found a REG_DEAD note that 14139 covers only part of the given reg, and we have a multi-reg hard 14140 register, then to be safe we must check for REG_DEAD notes 14141 for each register other than the first. They could have 14142 their own REG_DEAD notes lying around. */ 14143 else if ((note == 0 14144 || (note != 0 14145 && partial_subreg_p (GET_MODE (XEXP (note, 0)), 14146 GET_MODE (x)))) 14147 && regno < FIRST_PSEUDO_REGISTER 14148 && REG_NREGS (x) > 1) 14149 { 14150 unsigned int ourend = END_REGNO (x); 14151 unsigned int i, offset; 14152 rtx oldnotes = 0; 14153 14154 if (note) 14155 offset = hard_regno_nregs (regno, GET_MODE (XEXP (note, 0))); 14156 else 14157 offset = 1; 14158 14159 for (i = regno + offset; i < ourend; i++) 14160 move_deaths (regno_reg_rtx[i], 14161 maybe_kill_insn, from_luid, to_insn, &oldnotes); 14162 } 14163 14164 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) 14165 { 14166 XEXP (note, 1) = *pnotes; 14167 *pnotes = note; 14168 } 14169 else 14170 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes); 14171 } 14172 14173 return; 14174 } 14175 14176 else if (GET_CODE (x) == SET) 14177 { 14178 rtx dest = SET_DEST (x); 14179 14180 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes); 14181 14182 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG 14183 that accesses one word of a multi-word item, some 14184 piece of everything register in the expression is used by 14185 this insn, so remove any old death. */ 14186 /* ??? So why do we test for equality of the sizes? */ 14187 14188 if (GET_CODE (dest) == ZERO_EXTRACT 14189 || GET_CODE (dest) == STRICT_LOW_PART 14190 || (GET_CODE (dest) == SUBREG 14191 && !read_modify_subreg_p (dest))) 14192 { 14193 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes); 14194 return; 14195 } 14196 14197 /* If this is some other SUBREG, we know it replaces the entire 14198 value, so use that as the destination. */ 14199 if (GET_CODE (dest) == SUBREG) 14200 dest = SUBREG_REG (dest); 14201 14202 /* If this is a MEM, adjust deaths of anything used in the address. 14203 For a REG (the only other possibility), the entire value is 14204 being replaced so the old value is not used in this insn. */ 14205 14206 if (MEM_P (dest)) 14207 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid, 14208 to_insn, pnotes); 14209 return; 14210 } 14211 14212 else if (GET_CODE (x) == CLOBBER) 14213 return; 14214 14215 len = GET_RTX_LENGTH (code); 14216 fmt = GET_RTX_FORMAT (code); 14217 14218 for (i = 0; i < len; i++) 14219 { 14220 if (fmt[i] == 'E') 14221 { 14222 int j; 14223 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 14224 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid, 14225 to_insn, pnotes); 14226 } 14227 else if (fmt[i] == 'e') 14228 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes); 14229 } 14230 } 14231 14232 /* Return 1 if X is the target of a bit-field assignment in BODY, the 14233 pattern of an insn. X must be a REG. */ 14234 14235 static int 14236 reg_bitfield_target_p (rtx x, rtx body) 14237 { 14238 int i; 14239 14240 if (GET_CODE (body) == SET) 14241 { 14242 rtx dest = SET_DEST (body); 14243 rtx target; 14244 unsigned int regno, tregno, endregno, endtregno; 14245 14246 if (GET_CODE (dest) == ZERO_EXTRACT) 14247 target = XEXP (dest, 0); 14248 else if (GET_CODE (dest) == STRICT_LOW_PART) 14249 target = SUBREG_REG (XEXP (dest, 0)); 14250 else 14251 return 0; 14252 14253 if (GET_CODE (target) == SUBREG) 14254 target = SUBREG_REG (target); 14255 14256 if (!REG_P (target)) 14257 return 0; 14258 14259 tregno = REGNO (target), regno = REGNO (x); 14260 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) 14261 return target == x; 14262 14263 endtregno = end_hard_regno (GET_MODE (target), tregno); 14264 endregno = end_hard_regno (GET_MODE (x), regno); 14265 14266 return endregno > tregno && regno < endtregno; 14267 } 14268 14269 else if (GET_CODE (body) == PARALLEL) 14270 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 14271 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) 14272 return 1; 14273 14274 return 0; 14275 } 14276 14277 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them 14278 as appropriate. I3 and I2 are the insns resulting from the combination 14279 insns including FROM (I2 may be zero). 14280 14281 ELIM_I2 and ELIM_I1 are either zero or registers that we know will 14282 not need REG_DEAD notes because they are being substituted for. This 14283 saves searching in the most common cases. 14284 14285 Each note in the list is either ignored or placed on some insns, depending 14286 on the type of note. */ 14287 14288 static void 14289 distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2, 14290 rtx elim_i2, rtx elim_i1, rtx elim_i0) 14291 { 14292 rtx note, next_note; 14293 rtx tem_note; 14294 rtx_insn *tem_insn; 14295 14296 for (note = notes; note; note = next_note) 14297 { 14298 rtx_insn *place = 0, *place2 = 0; 14299 14300 next_note = XEXP (note, 1); 14301 switch (REG_NOTE_KIND (note)) 14302 { 14303 case REG_BR_PROB: 14304 case REG_BR_PRED: 14305 /* Doesn't matter much where we put this, as long as it's somewhere. 14306 It is preferable to keep these notes on branches, which is most 14307 likely to be i3. */ 14308 place = i3; 14309 break; 14310 14311 case REG_NON_LOCAL_GOTO: 14312 if (JUMP_P (i3)) 14313 place = i3; 14314 else 14315 { 14316 gcc_assert (i2 && JUMP_P (i2)); 14317 place = i2; 14318 } 14319 break; 14320 14321 case REG_EH_REGION: 14322 /* These notes must remain with the call or trapping instruction. */ 14323 if (CALL_P (i3)) 14324 place = i3; 14325 else if (i2 && CALL_P (i2)) 14326 place = i2; 14327 else 14328 { 14329 gcc_assert (cfun->can_throw_non_call_exceptions); 14330 if (may_trap_p (i3)) 14331 place = i3; 14332 else if (i2 && may_trap_p (i2)) 14333 place = i2; 14334 /* ??? Otherwise assume we've combined things such that we 14335 can now prove that the instructions can't trap. Drop the 14336 note in this case. */ 14337 } 14338 break; 14339 14340 case REG_ARGS_SIZE: 14341 /* ??? How to distribute between i3-i1. Assume i3 contains the 14342 entire adjustment. Assert i3 contains at least some adjust. */ 14343 if (!noop_move_p (i3)) 14344 { 14345 poly_int64 old_size, args_size = get_args_size (note); 14346 /* fixup_args_size_notes looks at REG_NORETURN note, 14347 so ensure the note is placed there first. */ 14348 if (CALL_P (i3)) 14349 { 14350 rtx *np; 14351 for (np = &next_note; *np; np = &XEXP (*np, 1)) 14352 if (REG_NOTE_KIND (*np) == REG_NORETURN) 14353 { 14354 rtx n = *np; 14355 *np = XEXP (n, 1); 14356 XEXP (n, 1) = REG_NOTES (i3); 14357 REG_NOTES (i3) = n; 14358 break; 14359 } 14360 } 14361 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size); 14362 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS 14363 REG_ARGS_SIZE note to all noreturn calls, allow that here. */ 14364 gcc_assert (maybe_ne (old_size, args_size) 14365 || (CALL_P (i3) 14366 && !ACCUMULATE_OUTGOING_ARGS 14367 && find_reg_note (i3, REG_NORETURN, NULL_RTX))); 14368 } 14369 break; 14370 14371 case REG_NORETURN: 14372 case REG_SETJMP: 14373 case REG_TM: 14374 case REG_CALL_DECL: 14375 case REG_CALL_NOCF_CHECK: 14376 /* These notes must remain with the call. It should not be 14377 possible for both I2 and I3 to be a call. */ 14378 if (CALL_P (i3)) 14379 place = i3; 14380 else 14381 { 14382 gcc_assert (i2 && CALL_P (i2)); 14383 place = i2; 14384 } 14385 break; 14386 14387 case REG_UNUSED: 14388 /* Any clobbers for i3 may still exist, and so we must process 14389 REG_UNUSED notes from that insn. 14390 14391 Any clobbers from i2 or i1 can only exist if they were added by 14392 recog_for_combine. In that case, recog_for_combine created the 14393 necessary REG_UNUSED notes. Trying to keep any original 14394 REG_UNUSED notes from these insns can cause incorrect output 14395 if it is for the same register as the original i3 dest. 14396 In that case, we will notice that the register is set in i3, 14397 and then add a REG_UNUSED note for the destination of i3, which 14398 is wrong. However, it is possible to have REG_UNUSED notes from 14399 i2 or i1 for register which were both used and clobbered, so 14400 we keep notes from i2 or i1 if they will turn into REG_DEAD 14401 notes. */ 14402 14403 /* If this register is set or clobbered between FROM_INSN and I3, 14404 we should not create a note for it. */ 14405 if (reg_set_between_p (XEXP (note, 0), from_insn, i3)) 14406 break; 14407 14408 /* If this register is set or clobbered in I3, put the note there 14409 unless there is one already. */ 14410 if (reg_set_p (XEXP (note, 0), PATTERN (i3))) 14411 { 14412 if (from_insn != i3) 14413 break; 14414 14415 if (! (REG_P (XEXP (note, 0)) 14416 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) 14417 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) 14418 place = i3; 14419 } 14420 /* Otherwise, if this register is used by I3, then this register 14421 now dies here, so we must put a REG_DEAD note here unless there 14422 is one already. */ 14423 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) 14424 && ! (REG_P (XEXP (note, 0)) 14425 ? find_regno_note (i3, REG_DEAD, 14426 REGNO (XEXP (note, 0))) 14427 : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) 14428 { 14429 PUT_REG_NOTE_KIND (note, REG_DEAD); 14430 place = i3; 14431 } 14432 14433 /* A SET or CLOBBER of the REG_UNUSED reg has been removed, 14434 but we can't tell which at this point. We must reset any 14435 expectations we had about the value that was previously 14436 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS 14437 and, if appropriate, restore its previous value, but we 14438 don't have enough information for that at this point. */ 14439 else 14440 { 14441 record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX); 14442 14443 /* Otherwise, if this register is now referenced in i2 14444 then the register used to be modified in one of the 14445 original insns. If it was i3 (say, in an unused 14446 parallel), it's now completely gone, so the note can 14447 be discarded. But if it was modified in i2, i1 or i0 14448 and we still reference it in i2, then we're 14449 referencing the previous value, and since the 14450 register was modified and REG_UNUSED, we know that 14451 the previous value is now dead. So, if we only 14452 reference the register in i2, we change the note to 14453 REG_DEAD, to reflect the previous value. However, if 14454 we're also setting or clobbering the register as 14455 scratch, we know (because the register was not 14456 referenced in i3) that it's unused, just as it was 14457 unused before, and we place the note in i2. */ 14458 if (from_insn != i3 && i2 && INSN_P (i2) 14459 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 14460 { 14461 if (!reg_set_p (XEXP (note, 0), PATTERN (i2))) 14462 PUT_REG_NOTE_KIND (note, REG_DEAD); 14463 if (! (REG_P (XEXP (note, 0)) 14464 ? find_regno_note (i2, REG_NOTE_KIND (note), 14465 REGNO (XEXP (note, 0))) 14466 : find_reg_note (i2, REG_NOTE_KIND (note), 14467 XEXP (note, 0)))) 14468 place = i2; 14469 } 14470 } 14471 14472 break; 14473 14474 case REG_EQUAL: 14475 case REG_EQUIV: 14476 case REG_NOALIAS: 14477 /* These notes say something about results of an insn. We can 14478 only support them if they used to be on I3 in which case they 14479 remain on I3. Otherwise they are ignored. 14480 14481 If the note refers to an expression that is not a constant, we 14482 must also ignore the note since we cannot tell whether the 14483 equivalence is still true. It might be possible to do 14484 slightly better than this (we only have a problem if I2DEST 14485 or I1DEST is present in the expression), but it doesn't 14486 seem worth the trouble. */ 14487 14488 if (from_insn == i3 14489 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) 14490 place = i3; 14491 break; 14492 14493 case REG_INC: 14494 /* These notes say something about how a register is used. They must 14495 be present on any use of the register in I2 or I3. */ 14496 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) 14497 place = i3; 14498 14499 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) 14500 { 14501 if (place) 14502 place2 = i2; 14503 else 14504 place = i2; 14505 } 14506 break; 14507 14508 case REG_LABEL_TARGET: 14509 case REG_LABEL_OPERAND: 14510 /* This can show up in several ways -- either directly in the 14511 pattern, or hidden off in the constant pool with (or without?) 14512 a REG_EQUAL note. */ 14513 /* ??? Ignore the without-reg_equal-note problem for now. */ 14514 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) 14515 || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX)) 14516 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF 14517 && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))) 14518 place = i3; 14519 14520 if (i2 14521 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) 14522 || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX)) 14523 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF 14524 && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))) 14525 { 14526 if (place) 14527 place2 = i2; 14528 else 14529 place = i2; 14530 } 14531 14532 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note 14533 as a JUMP_LABEL or decrement LABEL_NUSES if it's already 14534 there. */ 14535 if (place && JUMP_P (place) 14536 && REG_NOTE_KIND (note) == REG_LABEL_TARGET 14537 && (JUMP_LABEL (place) == NULL 14538 || JUMP_LABEL (place) == XEXP (note, 0))) 14539 { 14540 rtx label = JUMP_LABEL (place); 14541 14542 if (!label) 14543 JUMP_LABEL (place) = XEXP (note, 0); 14544 else if (LABEL_P (label)) 14545 LABEL_NUSES (label)--; 14546 } 14547 14548 if (place2 && JUMP_P (place2) 14549 && REG_NOTE_KIND (note) == REG_LABEL_TARGET 14550 && (JUMP_LABEL (place2) == NULL 14551 || JUMP_LABEL (place2) == XEXP (note, 0))) 14552 { 14553 rtx label = JUMP_LABEL (place2); 14554 14555 if (!label) 14556 JUMP_LABEL (place2) = XEXP (note, 0); 14557 else if (LABEL_P (label)) 14558 LABEL_NUSES (label)--; 14559 place2 = 0; 14560 } 14561 break; 14562 14563 case REG_NONNEG: 14564 /* This note says something about the value of a register prior 14565 to the execution of an insn. It is too much trouble to see 14566 if the note is still correct in all situations. It is better 14567 to simply delete it. */ 14568 break; 14569 14570 case REG_DEAD: 14571 /* If we replaced the right hand side of FROM_INSN with a 14572 REG_EQUAL note, the original use of the dying register 14573 will not have been combined into I3 and I2. In such cases, 14574 FROM_INSN is guaranteed to be the first of the combined 14575 instructions, so we simply need to search back before 14576 FROM_INSN for the previous use or set of this register, 14577 then alter the notes there appropriately. 14578 14579 If the register is used as an input in I3, it dies there. 14580 Similarly for I2, if it is nonzero and adjacent to I3. 14581 14582 If the register is not used as an input in either I3 or I2 14583 and it is not one of the registers we were supposed to eliminate, 14584 there are two possibilities. We might have a non-adjacent I2 14585 or we might have somehow eliminated an additional register 14586 from a computation. For example, we might have had A & B where 14587 we discover that B will always be zero. In this case we will 14588 eliminate the reference to A. 14589 14590 In both cases, we must search to see if we can find a previous 14591 use of A and put the death note there. */ 14592 14593 if (from_insn 14594 && from_insn == i2mod 14595 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs)) 14596 tem_insn = from_insn; 14597 else 14598 { 14599 if (from_insn 14600 && CALL_P (from_insn) 14601 && find_reg_fusage (from_insn, USE, XEXP (note, 0))) 14602 place = from_insn; 14603 else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2))) 14604 { 14605 /* If the new I2 sets the same register that is marked 14606 dead in the note, we do not in general know where to 14607 put the note. One important case we _can_ handle is 14608 when the note comes from I3. */ 14609 if (from_insn == i3) 14610 place = i3; 14611 else 14612 break; 14613 } 14614 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) 14615 place = i3; 14616 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3 14617 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 14618 place = i2; 14619 else if ((rtx_equal_p (XEXP (note, 0), elim_i2) 14620 && !(i2mod 14621 && reg_overlap_mentioned_p (XEXP (note, 0), 14622 i2mod_old_rhs))) 14623 || rtx_equal_p (XEXP (note, 0), elim_i1) 14624 || rtx_equal_p (XEXP (note, 0), elim_i0)) 14625 break; 14626 tem_insn = i3; 14627 } 14628 14629 if (place == 0) 14630 { 14631 basic_block bb = this_basic_block; 14632 14633 for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn)) 14634 { 14635 if (!NONDEBUG_INSN_P (tem_insn)) 14636 { 14637 if (tem_insn == BB_HEAD (bb)) 14638 break; 14639 continue; 14640 } 14641 14642 /* If the register is being set at TEM_INSN, see if that is all 14643 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this 14644 into a REG_UNUSED note instead. Don't delete sets to 14645 global register vars. */ 14646 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER 14647 || !global_regs[REGNO (XEXP (note, 0))]) 14648 && reg_set_p (XEXP (note, 0), PATTERN (tem_insn))) 14649 { 14650 rtx set = single_set (tem_insn); 14651 rtx inner_dest = 0; 14652 rtx_insn *cc0_setter = NULL; 14653 14654 if (set != 0) 14655 for (inner_dest = SET_DEST (set); 14656 (GET_CODE (inner_dest) == STRICT_LOW_PART 14657 || GET_CODE (inner_dest) == SUBREG 14658 || GET_CODE (inner_dest) == ZERO_EXTRACT); 14659 inner_dest = XEXP (inner_dest, 0)) 14660 ; 14661 14662 /* Verify that it was the set, and not a clobber that 14663 modified the register. 14664 14665 CC0 targets must be careful to maintain setter/user 14666 pairs. If we cannot delete the setter due to side 14667 effects, mark the user with an UNUSED note instead 14668 of deleting it. */ 14669 14670 if (set != 0 && ! side_effects_p (SET_SRC (set)) 14671 && rtx_equal_p (XEXP (note, 0), inner_dest) 14672 && (!HAVE_cc0 14673 || (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) 14674 || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL 14675 && sets_cc0_p (PATTERN (cc0_setter)) > 0)))) 14676 { 14677 /* Move the notes and links of TEM_INSN elsewhere. 14678 This might delete other dead insns recursively. 14679 First set the pattern to something that won't use 14680 any register. */ 14681 rtx old_notes = REG_NOTES (tem_insn); 14682 14683 PATTERN (tem_insn) = pc_rtx; 14684 REG_NOTES (tem_insn) = NULL; 14685 14686 distribute_notes (old_notes, tem_insn, tem_insn, NULL, 14687 NULL_RTX, NULL_RTX, NULL_RTX); 14688 distribute_links (LOG_LINKS (tem_insn)); 14689 14690 unsigned int regno = REGNO (XEXP (note, 0)); 14691 reg_stat_type *rsp = ®_stat[regno]; 14692 if (rsp->last_set == tem_insn) 14693 record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX); 14694 14695 SET_INSN_DELETED (tem_insn); 14696 if (tem_insn == i2) 14697 i2 = NULL; 14698 14699 /* Delete the setter too. */ 14700 if (cc0_setter) 14701 { 14702 PATTERN (cc0_setter) = pc_rtx; 14703 old_notes = REG_NOTES (cc0_setter); 14704 REG_NOTES (cc0_setter) = NULL; 14705 14706 distribute_notes (old_notes, cc0_setter, 14707 cc0_setter, NULL, 14708 NULL_RTX, NULL_RTX, NULL_RTX); 14709 distribute_links (LOG_LINKS (cc0_setter)); 14710 14711 SET_INSN_DELETED (cc0_setter); 14712 if (cc0_setter == i2) 14713 i2 = NULL; 14714 } 14715 } 14716 else 14717 { 14718 PUT_REG_NOTE_KIND (note, REG_UNUSED); 14719 14720 /* If there isn't already a REG_UNUSED note, put one 14721 here. Do not place a REG_DEAD note, even if 14722 the register is also used here; that would not 14723 match the algorithm used in lifetime analysis 14724 and can cause the consistency check in the 14725 scheduler to fail. */ 14726 if (! find_regno_note (tem_insn, REG_UNUSED, 14727 REGNO (XEXP (note, 0)))) 14728 place = tem_insn; 14729 break; 14730 } 14731 } 14732 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn)) 14733 || (CALL_P (tem_insn) 14734 && find_reg_fusage (tem_insn, USE, XEXP (note, 0)))) 14735 { 14736 place = tem_insn; 14737 14738 /* If we are doing a 3->2 combination, and we have a 14739 register which formerly died in i3 and was not used 14740 by i2, which now no longer dies in i3 and is used in 14741 i2 but does not die in i2, and place is between i2 14742 and i3, then we may need to move a link from place to 14743 i2. */ 14744 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2) 14745 && from_insn 14746 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2) 14747 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 14748 { 14749 struct insn_link *links = LOG_LINKS (place); 14750 LOG_LINKS (place) = NULL; 14751 distribute_links (links); 14752 } 14753 break; 14754 } 14755 14756 if (tem_insn == BB_HEAD (bb)) 14757 break; 14758 } 14759 14760 } 14761 14762 /* If the register is set or already dead at PLACE, we needn't do 14763 anything with this note if it is still a REG_DEAD note. 14764 We check here if it is set at all, not if is it totally replaced, 14765 which is what `dead_or_set_p' checks, so also check for it being 14766 set partially. */ 14767 14768 if (place && REG_NOTE_KIND (note) == REG_DEAD) 14769 { 14770 unsigned int regno = REGNO (XEXP (note, 0)); 14771 reg_stat_type *rsp = ®_stat[regno]; 14772 14773 if (dead_or_set_p (place, XEXP (note, 0)) 14774 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) 14775 { 14776 /* Unless the register previously died in PLACE, clear 14777 last_death. [I no longer understand why this is 14778 being done.] */ 14779 if (rsp->last_death != place) 14780 rsp->last_death = 0; 14781 place = 0; 14782 } 14783 else 14784 rsp->last_death = place; 14785 14786 /* If this is a death note for a hard reg that is occupying 14787 multiple registers, ensure that we are still using all 14788 parts of the object. If we find a piece of the object 14789 that is unused, we must arrange for an appropriate REG_DEAD 14790 note to be added for it. However, we can't just emit a USE 14791 and tag the note to it, since the register might actually 14792 be dead; so we recourse, and the recursive call then finds 14793 the previous insn that used this register. */ 14794 14795 if (place && REG_NREGS (XEXP (note, 0)) > 1) 14796 { 14797 unsigned int endregno = END_REGNO (XEXP (note, 0)); 14798 bool all_used = true; 14799 unsigned int i; 14800 14801 for (i = regno; i < endregno; i++) 14802 if ((! refers_to_regno_p (i, PATTERN (place)) 14803 && ! find_regno_fusage (place, USE, i)) 14804 || dead_or_set_regno_p (place, i)) 14805 { 14806 all_used = false; 14807 break; 14808 } 14809 14810 if (! all_used) 14811 { 14812 /* Put only REG_DEAD notes for pieces that are 14813 not already dead or set. */ 14814 14815 for (i = regno; i < endregno; 14816 i += hard_regno_nregs (i, reg_raw_mode[i])) 14817 { 14818 rtx piece = regno_reg_rtx[i]; 14819 basic_block bb = this_basic_block; 14820 14821 if (! dead_or_set_p (place, piece) 14822 && ! reg_bitfield_target_p (piece, 14823 PATTERN (place))) 14824 { 14825 rtx new_note = alloc_reg_note (REG_DEAD, piece, 14826 NULL_RTX); 14827 14828 distribute_notes (new_note, place, place, 14829 NULL, NULL_RTX, NULL_RTX, 14830 NULL_RTX); 14831 } 14832 else if (! refers_to_regno_p (i, PATTERN (place)) 14833 && ! find_regno_fusage (place, USE, i)) 14834 for (tem_insn = PREV_INSN (place); ; 14835 tem_insn = PREV_INSN (tem_insn)) 14836 { 14837 if (!NONDEBUG_INSN_P (tem_insn)) 14838 { 14839 if (tem_insn == BB_HEAD (bb)) 14840 break; 14841 continue; 14842 } 14843 if (dead_or_set_p (tem_insn, piece) 14844 || reg_bitfield_target_p (piece, 14845 PATTERN (tem_insn))) 14846 { 14847 add_reg_note (tem_insn, REG_UNUSED, piece); 14848 break; 14849 } 14850 } 14851 } 14852 14853 place = 0; 14854 } 14855 } 14856 } 14857 break; 14858 14859 default: 14860 /* Any other notes should not be present at this point in the 14861 compilation. */ 14862 gcc_unreachable (); 14863 } 14864 14865 if (place) 14866 { 14867 XEXP (note, 1) = REG_NOTES (place); 14868 REG_NOTES (place) = note; 14869 14870 /* Set added_notes_insn to the earliest insn we added a note to. */ 14871 if (added_notes_insn == 0 14872 || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place)) 14873 added_notes_insn = place; 14874 } 14875 14876 if (place2) 14877 { 14878 add_shallow_copy_of_reg_note (place2, note); 14879 14880 /* Set added_notes_insn to the earliest insn we added a note to. */ 14881 if (added_notes_insn == 0 14882 || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place2)) 14883 added_notes_insn = place2; 14884 } 14885 } 14886 } 14887 14888 /* Similarly to above, distribute the LOG_LINKS that used to be present on 14889 I3, I2, and I1 to new locations. This is also called to add a link 14890 pointing at I3 when I3's destination is changed. */ 14891 14892 static void 14893 distribute_links (struct insn_link *links) 14894 { 14895 struct insn_link *link, *next_link; 14896 14897 for (link = links; link; link = next_link) 14898 { 14899 rtx_insn *place = 0; 14900 rtx_insn *insn; 14901 rtx set, reg; 14902 14903 next_link = link->next; 14904 14905 /* If the insn that this link points to is a NOTE, ignore it. */ 14906 if (NOTE_P (link->insn)) 14907 continue; 14908 14909 set = 0; 14910 rtx pat = PATTERN (link->insn); 14911 if (GET_CODE (pat) == SET) 14912 set = pat; 14913 else if (GET_CODE (pat) == PARALLEL) 14914 { 14915 int i; 14916 for (i = 0; i < XVECLEN (pat, 0); i++) 14917 { 14918 set = XVECEXP (pat, 0, i); 14919 if (GET_CODE (set) != SET) 14920 continue; 14921 14922 reg = SET_DEST (set); 14923 while (GET_CODE (reg) == ZERO_EXTRACT 14924 || GET_CODE (reg) == STRICT_LOW_PART 14925 || GET_CODE (reg) == SUBREG) 14926 reg = XEXP (reg, 0); 14927 14928 if (!REG_P (reg)) 14929 continue; 14930 14931 if (REGNO (reg) == link->regno) 14932 break; 14933 } 14934 if (i == XVECLEN (pat, 0)) 14935 continue; 14936 } 14937 else 14938 continue; 14939 14940 reg = SET_DEST (set); 14941 14942 while (GET_CODE (reg) == ZERO_EXTRACT 14943 || GET_CODE (reg) == STRICT_LOW_PART 14944 || GET_CODE (reg) == SUBREG) 14945 reg = XEXP (reg, 0); 14946 14947 if (reg == pc_rtx) 14948 continue; 14949 14950 /* A LOG_LINK is defined as being placed on the first insn that uses 14951 a register and points to the insn that sets the register. Start 14952 searching at the next insn after the target of the link and stop 14953 when we reach a set of the register or the end of the basic block. 14954 14955 Note that this correctly handles the link that used to point from 14956 I3 to I2. Also note that not much searching is typically done here 14957 since most links don't point very far away. */ 14958 14959 for (insn = NEXT_INSN (link->insn); 14960 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 14961 || BB_HEAD (this_basic_block->next_bb) != insn)); 14962 insn = NEXT_INSN (insn)) 14963 if (DEBUG_INSN_P (insn)) 14964 continue; 14965 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) 14966 { 14967 if (reg_referenced_p (reg, PATTERN (insn))) 14968 place = insn; 14969 break; 14970 } 14971 else if (CALL_P (insn) 14972 && find_reg_fusage (insn, USE, reg)) 14973 { 14974 place = insn; 14975 break; 14976 } 14977 else if (INSN_P (insn) && reg_set_p (reg, insn)) 14978 break; 14979 14980 /* If we found a place to put the link, place it there unless there 14981 is already a link to the same insn as LINK at that point. */ 14982 14983 if (place) 14984 { 14985 struct insn_link *link2; 14986 14987 FOR_EACH_LOG_LINK (link2, place) 14988 if (link2->insn == link->insn && link2->regno == link->regno) 14989 break; 14990 14991 if (link2 == NULL) 14992 { 14993 link->next = LOG_LINKS (place); 14994 LOG_LINKS (place) = link; 14995 14996 /* Set added_links_insn to the earliest insn we added a 14997 link to. */ 14998 if (added_links_insn == 0 14999 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place)) 15000 added_links_insn = place; 15001 } 15002 } 15003 } 15004 } 15005 15006 /* Check for any register or memory mentioned in EQUIV that is not 15007 mentioned in EXPR. This is used to restrict EQUIV to "specializations" 15008 of EXPR where some registers may have been replaced by constants. */ 15009 15010 static bool 15011 unmentioned_reg_p (rtx equiv, rtx expr) 15012 { 15013 subrtx_iterator::array_type array; 15014 FOR_EACH_SUBRTX (iter, array, equiv, NONCONST) 15015 { 15016 const_rtx x = *iter; 15017 if ((REG_P (x) || MEM_P (x)) 15018 && !reg_mentioned_p (x, expr)) 15019 return true; 15020 } 15021 return false; 15022 } 15023 15024 DEBUG_FUNCTION void 15025 dump_combine_stats (FILE *file) 15026 { 15027 fprintf 15028 (file, 15029 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", 15030 combine_attempts, combine_merges, combine_extras, combine_successes); 15031 } 15032 15033 void 15034 dump_combine_total_stats (FILE *file) 15035 { 15036 fprintf 15037 (file, 15038 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", 15039 total_attempts, total_merges, total_extras, total_successes); 15040 } 15041 15042 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because 15043 the reg-to-reg copy can usefully combine with later instructions, but we 15044 do not want to combine the hard reg into later instructions, for that 15045 restricts register allocation. */ 15046 static void 15047 make_more_copies (void) 15048 { 15049 basic_block bb; 15050 15051 FOR_EACH_BB_FN (bb, cfun) 15052 { 15053 rtx_insn *insn; 15054 15055 FOR_BB_INSNS (bb, insn) 15056 { 15057 if (!NONDEBUG_INSN_P (insn)) 15058 continue; 15059 15060 rtx set = single_set (insn); 15061 if (!set) 15062 continue; 15063 15064 rtx dest = SET_DEST (set); 15065 if (!(REG_P (dest) && !HARD_REGISTER_P (dest))) 15066 continue; 15067 15068 rtx src = SET_SRC (set); 15069 if (!(REG_P (src) && HARD_REGISTER_P (src))) 15070 continue; 15071 if (TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))) 15072 continue; 15073 15074 rtx new_reg = gen_reg_rtx (GET_MODE (dest)); 15075 rtx_insn *new_insn = gen_move_insn (new_reg, src); 15076 SET_SRC (set) = new_reg; 15077 emit_insn_before (new_insn, insn); 15078 df_insn_rescan (insn); 15079 } 15080 } 15081 } 15082 15083 /* Try combining insns through substitution. */ 15084 static unsigned int 15085 rest_of_handle_combine (void) 15086 { 15087 make_more_copies (); 15088 15089 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN); 15090 df_note_add_problem (); 15091 df_analyze (); 15092 15093 regstat_init_n_sets_and_refs (); 15094 reg_n_sets_max = max_reg_num (); 15095 15096 int rebuild_jump_labels_after_combine 15097 = combine_instructions (get_insns (), max_reg_num ()); 15098 15099 /* Combining insns may have turned an indirect jump into a 15100 direct jump. Rebuild the JUMP_LABEL fields of jumping 15101 instructions. */ 15102 if (rebuild_jump_labels_after_combine) 15103 { 15104 if (dom_info_available_p (CDI_DOMINATORS)) 15105 free_dominance_info (CDI_DOMINATORS); 15106 timevar_push (TV_JUMP); 15107 rebuild_jump_labels (get_insns ()); 15108 cleanup_cfg (0); 15109 timevar_pop (TV_JUMP); 15110 } 15111 15112 regstat_free_n_sets_and_refs (); 15113 return 0; 15114 } 15115 15116 namespace { 15117 15118 const pass_data pass_data_combine = 15119 { 15120 RTL_PASS, /* type */ 15121 "combine", /* name */ 15122 OPTGROUP_NONE, /* optinfo_flags */ 15123 TV_COMBINE, /* tv_id */ 15124 PROP_cfglayout, /* properties_required */ 15125 0, /* properties_provided */ 15126 0, /* properties_destroyed */ 15127 0, /* todo_flags_start */ 15128 TODO_df_finish, /* todo_flags_finish */ 15129 }; 15130 15131 class pass_combine : public rtl_opt_pass 15132 { 15133 public: 15134 pass_combine (gcc::context *ctxt) 15135 : rtl_opt_pass (pass_data_combine, ctxt) 15136 {} 15137 15138 /* opt_pass methods: */ 15139 virtual bool gate (function *) { return (optimize > 0); } 15140 virtual unsigned int execute (function *) 15141 { 15142 return rest_of_handle_combine (); 15143 } 15144 15145 }; // class pass_combine 15146 15147 } // anon namespace 15148 15149 rtl_opt_pass * 15150 make_pass_combine (gcc::context *ctxt) 15151 { 15152 return new pass_combine (ctxt); 15153 } 15154