1 /* Optimize by combining instructions for GNU compiler. 2 Copyright (C) 1987-2015 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 /* This module is essentially the "combiner" phase of the U. of Arizona 21 Portable Optimizer, but redone to work on our list-structured 22 representation for RTL instead of their string representation. 23 24 The LOG_LINKS of each insn identify the most recent assignment 25 to each REG used in the insn. It is a list of previous insns, 26 each of which contains a SET for a REG that is used in this insn 27 and not used or set in between. LOG_LINKs never cross basic blocks. 28 They were set up by the preceding pass (lifetime analysis). 29 30 We try to combine each pair of insns joined by a logical link. 31 We also try to combine triplets of insns A, B and C when C has 32 a link back to B and B has a link back to A. Likewise for a 33 small number of quadruplets of insns A, B, C and D for which 34 there's high likelihood of of success. 35 36 LOG_LINKS does not have links for use of the CC0. They don't 37 need to, because the insn that sets the CC0 is always immediately 38 before the insn that tests it. So we always regard a branch 39 insn as having a logical link to the preceding insn. The same is true 40 for an insn explicitly using CC0. 41 42 We check (with use_crosses_set_p) to avoid combining in such a way 43 as to move a computation to a place where its value would be different. 44 45 Combination is done by mathematically substituting the previous 46 insn(s) values for the regs they set into the expressions in 47 the later insns that refer to these regs. If the result is a valid insn 48 for our target machine, according to the machine description, 49 we install it, delete the earlier insns, and update the data flow 50 information (LOG_LINKS and REG_NOTES) for what we did. 51 52 There are a few exceptions where the dataflow information isn't 53 completely updated (however this is only a local issue since it is 54 regenerated before the next pass that uses it): 55 56 - reg_live_length is not updated 57 - reg_n_refs is not adjusted in the rare case when a register is 58 no longer required in a computation 59 - there are extremely rare cases (see distribute_notes) when a 60 REG_DEAD note is lost 61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be 62 removed because there is no way to know which register it was 63 linking 64 65 To simplify substitution, we combine only when the earlier insn(s) 66 consist of only a single assignment. To simplify updating afterward, 67 we never combine when a subroutine call appears in the middle. 68 69 Since we do not represent assignments to CC0 explicitly except when that 70 is all an insn does, there is no LOG_LINKS entry in an insn that uses 71 the condition code for the insn that set the condition code. 72 Fortunately, these two insns must be consecutive. 73 Therefore, every JUMP_INSN is taken to have an implicit logical link 74 to the preceding insn. This is not quite right, since non-jumps can 75 also use the condition code; but in practice such insns would not 76 combine anyway. */ 77 78 #include "config.h" 79 #include "system.h" 80 #include "coretypes.h" 81 #include "tm.h" 82 #include "rtl.h" 83 #include "hash-set.h" 84 #include "machmode.h" 85 #include "vec.h" 86 #include "double-int.h" 87 #include "input.h" 88 #include "alias.h" 89 #include "symtab.h" 90 #include "wide-int.h" 91 #include "inchash.h" 92 #include "tree.h" 93 #include "stor-layout.h" 94 #include "tm_p.h" 95 #include "flags.h" 96 #include "regs.h" 97 #include "hard-reg-set.h" 98 #include "predict.h" 99 #include "function.h" 100 #include "dominance.h" 101 #include "cfg.h" 102 #include "cfgrtl.h" 103 #include "cfgcleanup.h" 104 #include "basic-block.h" 105 #include "insn-config.h" 106 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ 107 #include "hashtab.h" 108 #include "statistics.h" 109 #include "real.h" 110 #include "fixed-value.h" 111 #include "expmed.h" 112 #include "dojump.h" 113 #include "explow.h" 114 #include "calls.h" 115 #include "emit-rtl.h" 116 #include "varasm.h" 117 #include "stmt.h" 118 #include "expr.h" 119 #include "insn-attr.h" 120 #include "recog.h" 121 #include "diagnostic-core.h" 122 #include "target.h" 123 #include "insn-codes.h" 124 #include "optabs.h" 125 #include "rtlhooks-def.h" 126 #include "params.h" 127 #include "tree-pass.h" 128 #include "df.h" 129 #include "valtrack.h" 130 #include "hash-map.h" 131 #include "is-a.h" 132 #include "plugin-api.h" 133 #include "ipa-ref.h" 134 #include "cgraph.h" 135 #include "obstack.h" 136 #include "rtl-iter.h" 137 138 /* Number of attempts to combine instructions in this function. */ 139 140 static int combine_attempts; 141 142 /* Number of attempts that got as far as substitution in this function. */ 143 144 static int combine_merges; 145 146 /* Number of instructions combined with added SETs in this function. */ 147 148 static int combine_extras; 149 150 /* Number of instructions combined in this function. */ 151 152 static int combine_successes; 153 154 /* Totals over entire compilation. */ 155 156 static int total_attempts, total_merges, total_extras, total_successes; 157 158 /* combine_instructions may try to replace the right hand side of the 159 second instruction with the value of an associated REG_EQUAL note 160 before throwing it at try_combine. That is problematic when there 161 is a REG_DEAD note for a register used in the old right hand side 162 and can cause distribute_notes to do wrong things. This is the 163 second instruction if it has been so modified, null otherwise. */ 164 165 static rtx_insn *i2mod; 166 167 /* When I2MOD is nonnull, this is a copy of the old right hand side. */ 168 169 static rtx i2mod_old_rhs; 170 171 /* When I2MOD is nonnull, this is a copy of the new right hand side. */ 172 173 static rtx i2mod_new_rhs; 174 175 typedef struct reg_stat_struct { 176 /* Record last point of death of (hard or pseudo) register n. */ 177 rtx_insn *last_death; 178 179 /* Record last point of modification of (hard or pseudo) register n. */ 180 rtx_insn *last_set; 181 182 /* The next group of fields allows the recording of the last value assigned 183 to (hard or pseudo) register n. We use this information to see if an 184 operation being processed is redundant given a prior operation performed 185 on the register. For example, an `and' with a constant is redundant if 186 all the zero bits are already known to be turned off. 187 188 We use an approach similar to that used by cse, but change it in the 189 following ways: 190 191 (1) We do not want to reinitialize at each label. 192 (2) It is useful, but not critical, to know the actual value assigned 193 to a register. Often just its form is helpful. 194 195 Therefore, we maintain the following fields: 196 197 last_set_value the last value assigned 198 last_set_label records the value of label_tick when the 199 register was assigned 200 last_set_table_tick records the value of label_tick when a 201 value using the register is assigned 202 last_set_invalid set to nonzero when it is not valid 203 to use the value of this register in some 204 register's value 205 206 To understand the usage of these tables, it is important to understand 207 the distinction between the value in last_set_value being valid and 208 the register being validly contained in some other expression in the 209 table. 210 211 (The next two parameters are out of date). 212 213 reg_stat[i].last_set_value is valid if it is nonzero, and either 214 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick. 215 216 Register I may validly appear in any expression returned for the value 217 of another register if reg_n_sets[i] is 1. It may also appear in the 218 value for register J if reg_stat[j].last_set_invalid is zero, or 219 reg_stat[i].last_set_label < reg_stat[j].last_set_label. 220 221 If an expression is found in the table containing a register which may 222 not validly appear in an expression, the register is replaced by 223 something that won't match, (clobber (const_int 0)). */ 224 225 /* Record last value assigned to (hard or pseudo) register n. */ 226 227 rtx last_set_value; 228 229 /* Record the value of label_tick when an expression involving register n 230 is placed in last_set_value. */ 231 232 int last_set_table_tick; 233 234 /* Record the value of label_tick when the value for register n is placed in 235 last_set_value. */ 236 237 int last_set_label; 238 239 /* These fields are maintained in parallel with last_set_value and are 240 used to store the mode in which the register was last set, the bits 241 that were known to be zero when it was last set, and the number of 242 sign bits copies it was known to have when it was last set. */ 243 244 unsigned HOST_WIDE_INT last_set_nonzero_bits; 245 char last_set_sign_bit_copies; 246 ENUM_BITFIELD(machine_mode) last_set_mode : 8; 247 248 /* Set nonzero if references to register n in expressions should not be 249 used. last_set_invalid is set nonzero when this register is being 250 assigned to and last_set_table_tick == label_tick. */ 251 252 char last_set_invalid; 253 254 /* Some registers that are set more than once and used in more than one 255 basic block are nevertheless always set in similar ways. For example, 256 a QImode register may be loaded from memory in two places on a machine 257 where byte loads zero extend. 258 259 We record in the following fields if a register has some leading bits 260 that are always equal to the sign bit, and what we know about the 261 nonzero bits of a register, specifically which bits are known to be 262 zero. 263 264 If an entry is zero, it means that we don't know anything special. */ 265 266 unsigned char sign_bit_copies; 267 268 unsigned HOST_WIDE_INT nonzero_bits; 269 270 /* Record the value of the label_tick when the last truncation 271 happened. The field truncated_to_mode is only valid if 272 truncation_label == label_tick. */ 273 274 int truncation_label; 275 276 /* Record the last truncation seen for this register. If truncation 277 is not a nop to this mode we might be able to save an explicit 278 truncation if we know that value already contains a truncated 279 value. */ 280 281 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8; 282 } reg_stat_type; 283 284 285 static vec<reg_stat_type> reg_stat; 286 287 /* One plus the highest pseudo for which we track REG_N_SETS. 288 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once, 289 but during combine_split_insns new pseudos can be created. As we don't have 290 updated DF information in that case, it is hard to initialize the array 291 after growing. The combiner only cares about REG_N_SETS (regno) == 1, 292 so instead of growing the arrays, just assume all newly created pseudos 293 during combine might be set multiple times. */ 294 295 static unsigned int reg_n_sets_max; 296 297 /* Record the luid of the last insn that invalidated memory 298 (anything that writes memory, and subroutine calls, but not pushes). */ 299 300 static int mem_last_set; 301 302 /* Record the luid of the last CALL_INSN 303 so we can tell whether a potential combination crosses any calls. */ 304 305 static int last_call_luid; 306 307 /* When `subst' is called, this is the insn that is being modified 308 (by combining in a previous insn). The PATTERN of this insn 309 is still the old pattern partially modified and it should not be 310 looked at, but this may be used to examine the successors of the insn 311 to judge whether a simplification is valid. */ 312 313 static rtx_insn *subst_insn; 314 315 /* This is the lowest LUID that `subst' is currently dealing with. 316 get_last_value will not return a value if the register was set at or 317 after this LUID. If not for this mechanism, we could get confused if 318 I2 or I1 in try_combine were an insn that used the old value of a register 319 to obtain a new value. In that case, we might erroneously get the 320 new value of the register when we wanted the old one. */ 321 322 static int subst_low_luid; 323 324 /* This contains any hard registers that are used in newpat; reg_dead_at_p 325 must consider all these registers to be always live. */ 326 327 static HARD_REG_SET newpat_used_regs; 328 329 /* This is an insn to which a LOG_LINKS entry has been added. If this 330 insn is the earlier than I2 or I3, combine should rescan starting at 331 that location. */ 332 333 static rtx_insn *added_links_insn; 334 335 /* Basic block in which we are performing combines. */ 336 static basic_block this_basic_block; 337 static bool optimize_this_for_speed_p; 338 339 340 /* Length of the currently allocated uid_insn_cost array. */ 341 342 static int max_uid_known; 343 344 /* The following array records the insn_rtx_cost for every insn 345 in the instruction stream. */ 346 347 static int *uid_insn_cost; 348 349 /* The following array records the LOG_LINKS for every insn in the 350 instruction stream as struct insn_link pointers. */ 351 352 struct insn_link { 353 rtx_insn *insn; 354 unsigned int regno; 355 struct insn_link *next; 356 }; 357 358 static struct insn_link **uid_log_links; 359 360 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)]) 361 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)]) 362 363 #define FOR_EACH_LOG_LINK(L, INSN) \ 364 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next) 365 366 /* Links for LOG_LINKS are allocated from this obstack. */ 367 368 static struct obstack insn_link_obstack; 369 370 /* Allocate a link. */ 371 372 static inline struct insn_link * 373 alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next) 374 { 375 struct insn_link *l 376 = (struct insn_link *) obstack_alloc (&insn_link_obstack, 377 sizeof (struct insn_link)); 378 l->insn = insn; 379 l->regno = regno; 380 l->next = next; 381 return l; 382 } 383 384 /* Incremented for each basic block. */ 385 386 static int label_tick; 387 388 /* Reset to label_tick for each extended basic block in scanning order. */ 389 390 static int label_tick_ebb_start; 391 392 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the 393 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ 394 395 static machine_mode nonzero_bits_mode; 396 397 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can 398 be safely used. It is zero while computing them and after combine has 399 completed. This former test prevents propagating values based on 400 previously set values, which can be incorrect if a variable is modified 401 in a loop. */ 402 403 static int nonzero_sign_valid; 404 405 406 /* Record one modification to rtl structure 407 to be undone by storing old_contents into *where. */ 408 409 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS }; 410 411 struct undo 412 { 413 struct undo *next; 414 enum undo_kind kind; 415 union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents; 416 union { rtx *r; int *i; struct insn_link **l; } where; 417 }; 418 419 /* Record a bunch of changes to be undone, up to MAX_UNDO of them. 420 num_undo says how many are currently recorded. 421 422 other_insn is nonzero if we have modified some other insn in the process 423 of working on subst_insn. It must be verified too. */ 424 425 struct undobuf 426 { 427 struct undo *undos; 428 struct undo *frees; 429 rtx_insn *other_insn; 430 }; 431 432 static struct undobuf undobuf; 433 434 /* Number of times the pseudo being substituted for 435 was found and replaced. */ 436 437 static int n_occurrences; 438 439 static rtx reg_nonzero_bits_for_combine (const_rtx, machine_mode, const_rtx, 440 machine_mode, 441 unsigned HOST_WIDE_INT, 442 unsigned HOST_WIDE_INT *); 443 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, machine_mode, const_rtx, 444 machine_mode, 445 unsigned int, unsigned int *); 446 static void do_SUBST (rtx *, rtx); 447 static void do_SUBST_INT (int *, int); 448 static void init_reg_last (void); 449 static void setup_incoming_promotions (rtx_insn *); 450 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *); 451 static int cant_combine_insn_p (rtx_insn *); 452 static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *, 453 rtx_insn *, rtx_insn *, rtx *, rtx *); 454 static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *); 455 static int contains_muldiv (rtx); 456 static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *, 457 int *, rtx_insn *); 458 static void undo_all (void); 459 static void undo_commit (void); 460 static rtx *find_split_point (rtx *, rtx_insn *, bool); 461 static rtx subst (rtx, rtx, rtx, int, int, int); 462 static rtx combine_simplify_rtx (rtx, machine_mode, int, int); 463 static rtx simplify_if_then_else (rtx); 464 static rtx simplify_set (rtx); 465 static rtx simplify_logical (rtx); 466 static rtx expand_compound_operation (rtx); 467 static const_rtx expand_field_assignment (const_rtx); 468 static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, 469 rtx, unsigned HOST_WIDE_INT, int, int, int); 470 static rtx extract_left_shift (rtx, int); 471 static int get_pos_from_mask (unsigned HOST_WIDE_INT, 472 unsigned HOST_WIDE_INT *); 473 static rtx canon_reg_for_combine (rtx, rtx); 474 static rtx force_to_mode (rtx, machine_mode, 475 unsigned HOST_WIDE_INT, int); 476 static rtx if_then_else_cond (rtx, rtx *, rtx *); 477 static rtx known_cond (rtx, enum rtx_code, rtx, rtx); 478 static int rtx_equal_for_field_assignment_p (rtx, rtx, bool = false); 479 static rtx make_field_assignment (rtx); 480 static rtx apply_distributive_law (rtx); 481 static rtx distribute_and_simplify_rtx (rtx, int); 482 static rtx simplify_and_const_int_1 (machine_mode, rtx, 483 unsigned HOST_WIDE_INT); 484 static rtx simplify_and_const_int (rtx, machine_mode, rtx, 485 unsigned HOST_WIDE_INT); 486 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code, 487 HOST_WIDE_INT, machine_mode, int *); 488 static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int); 489 static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx, 490 int); 491 static int recog_for_combine (rtx *, rtx_insn *, rtx *); 492 static rtx gen_lowpart_for_combine (machine_mode, rtx); 493 static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode, 494 rtx, rtx *); 495 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *); 496 static void update_table_tick (rtx); 497 static void record_value_for_reg (rtx, rtx_insn *, rtx); 498 static void check_promoted_subreg (rtx_insn *, rtx); 499 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *); 500 static void record_dead_and_set_regs (rtx_insn *); 501 static int get_last_value_validate (rtx *, rtx_insn *, int, int); 502 static rtx get_last_value (const_rtx); 503 static int use_crosses_set_p (const_rtx, int); 504 static void reg_dead_at_p_1 (rtx, const_rtx, void *); 505 static int reg_dead_at_p (rtx, rtx_insn *); 506 static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *); 507 static int reg_bitfield_target_p (rtx, rtx); 508 static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx); 509 static void distribute_links (struct insn_link *); 510 static void mark_used_regs_combine (rtx); 511 static void record_promoted_value (rtx_insn *, rtx); 512 static bool unmentioned_reg_p (rtx, rtx); 513 static void record_truncated_values (rtx *, void *); 514 static bool reg_truncated_to_mode (machine_mode, const_rtx); 515 static rtx gen_lowpart_or_truncate (machine_mode, rtx); 516 517 518 /* It is not safe to use ordinary gen_lowpart in combine. 519 See comments in gen_lowpart_for_combine. */ 520 #undef RTL_HOOKS_GEN_LOWPART 521 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine 522 523 /* Our implementation of gen_lowpart never emits a new pseudo. */ 524 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT 525 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine 526 527 #undef RTL_HOOKS_REG_NONZERO_REG_BITS 528 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine 529 530 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES 531 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine 532 533 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE 534 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode 535 536 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER; 537 538 539 /* Convenience wrapper for the canonicalize_comparison target hook. 540 Target hooks cannot use enum rtx_code. */ 541 static inline void 542 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1, 543 bool op0_preserve_value) 544 { 545 int code_int = (int)*code; 546 targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value); 547 *code = (enum rtx_code)code_int; 548 } 549 550 /* Try to split PATTERN found in INSN. This returns NULL_RTX if 551 PATTERN can not be split. Otherwise, it returns an insn sequence. 552 This is a wrapper around split_insns which ensures that the 553 reg_stat vector is made larger if the splitter creates a new 554 register. */ 555 556 static rtx_insn * 557 combine_split_insns (rtx pattern, rtx insn) 558 { 559 rtx_insn *ret; 560 unsigned int nregs; 561 562 ret = safe_as_a <rtx_insn *> (split_insns (pattern, insn)); 563 nregs = max_reg_num (); 564 if (nregs > reg_stat.length ()) 565 reg_stat.safe_grow_cleared (nregs); 566 return ret; 567 } 568 569 /* This is used by find_single_use to locate an rtx in LOC that 570 contains exactly one use of DEST, which is typically either a REG 571 or CC0. It returns a pointer to the innermost rtx expression 572 containing DEST. Appearances of DEST that are being used to 573 totally replace it are not counted. */ 574 575 static rtx * 576 find_single_use_1 (rtx dest, rtx *loc) 577 { 578 rtx x = *loc; 579 enum rtx_code code = GET_CODE (x); 580 rtx *result = NULL; 581 rtx *this_result; 582 int i; 583 const char *fmt; 584 585 switch (code) 586 { 587 case CONST: 588 case LABEL_REF: 589 case SYMBOL_REF: 590 CASE_CONST_ANY: 591 case CLOBBER: 592 return 0; 593 594 case SET: 595 /* If the destination is anything other than CC0, PC, a REG or a SUBREG 596 of a REG that occupies all of the REG, the insn uses DEST if 597 it is mentioned in the destination or the source. Otherwise, we 598 need just check the source. */ 599 if (GET_CODE (SET_DEST (x)) != CC0 600 && GET_CODE (SET_DEST (x)) != PC 601 && !REG_P (SET_DEST (x)) 602 && ! (GET_CODE (SET_DEST (x)) == SUBREG 603 && REG_P (SUBREG_REG (SET_DEST (x))) 604 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 605 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 606 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 607 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) 608 break; 609 610 return find_single_use_1 (dest, &SET_SRC (x)); 611 612 case MEM: 613 case SUBREG: 614 return find_single_use_1 (dest, &XEXP (x, 0)); 615 616 default: 617 break; 618 } 619 620 /* If it wasn't one of the common cases above, check each expression and 621 vector of this code. Look for a unique usage of DEST. */ 622 623 fmt = GET_RTX_FORMAT (code); 624 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 625 { 626 if (fmt[i] == 'e') 627 { 628 if (dest == XEXP (x, i) 629 || (REG_P (dest) && REG_P (XEXP (x, i)) 630 && REGNO (dest) == REGNO (XEXP (x, i)))) 631 this_result = loc; 632 else 633 this_result = find_single_use_1 (dest, &XEXP (x, i)); 634 635 if (result == NULL) 636 result = this_result; 637 else if (this_result) 638 /* Duplicate usage. */ 639 return NULL; 640 } 641 else if (fmt[i] == 'E') 642 { 643 int j; 644 645 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 646 { 647 if (XVECEXP (x, i, j) == dest 648 || (REG_P (dest) 649 && REG_P (XVECEXP (x, i, j)) 650 && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) 651 this_result = loc; 652 else 653 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); 654 655 if (result == NULL) 656 result = this_result; 657 else if (this_result) 658 return NULL; 659 } 660 } 661 } 662 663 return result; 664 } 665 666 667 /* See if DEST, produced in INSN, is used only a single time in the 668 sequel. If so, return a pointer to the innermost rtx expression in which 669 it is used. 670 671 If PLOC is nonzero, *PLOC is set to the insn containing the single use. 672 673 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't 674 care about REG_DEAD notes or LOG_LINKS. 675 676 Otherwise, we find the single use by finding an insn that has a 677 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is 678 only referenced once in that insn, we know that it must be the first 679 and last insn referencing DEST. */ 680 681 static rtx * 682 find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc) 683 { 684 basic_block bb; 685 rtx_insn *next; 686 rtx *result; 687 struct insn_link *link; 688 689 #ifdef HAVE_cc0 690 if (dest == cc0_rtx) 691 { 692 next = NEXT_INSN (insn); 693 if (next == 0 694 || (!NONJUMP_INSN_P (next) && !JUMP_P (next))) 695 return 0; 696 697 result = find_single_use_1 (dest, &PATTERN (next)); 698 if (result && ploc) 699 *ploc = next; 700 return result; 701 } 702 #endif 703 704 if (!REG_P (dest)) 705 return 0; 706 707 bb = BLOCK_FOR_INSN (insn); 708 for (next = NEXT_INSN (insn); 709 next && BLOCK_FOR_INSN (next) == bb; 710 next = NEXT_INSN (next)) 711 if (INSN_P (next) && dead_or_set_p (next, dest)) 712 { 713 FOR_EACH_LOG_LINK (link, next) 714 if (link->insn == insn && link->regno == REGNO (dest)) 715 break; 716 717 if (link) 718 { 719 result = find_single_use_1 (dest, &PATTERN (next)); 720 if (ploc) 721 *ploc = next; 722 return result; 723 } 724 } 725 726 return 0; 727 } 728 729 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some 730 insn. The substitution can be undone by undo_all. If INTO is already 731 set to NEWVAL, do not record this change. Because computing NEWVAL might 732 also call SUBST, we have to compute it before we put anything into 733 the undo table. */ 734 735 static void 736 do_SUBST (rtx *into, rtx newval) 737 { 738 struct undo *buf; 739 rtx oldval = *into; 740 741 if (oldval == newval) 742 return; 743 744 /* We'd like to catch as many invalid transformations here as 745 possible. Unfortunately, there are way too many mode changes 746 that are perfectly valid, so we'd waste too much effort for 747 little gain doing the checks here. Focus on catching invalid 748 transformations involving integer constants. */ 749 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT 750 && CONST_INT_P (newval)) 751 { 752 /* Sanity check that we're replacing oldval with a CONST_INT 753 that is a valid sign-extension for the original mode. */ 754 gcc_assert (INTVAL (newval) 755 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval))); 756 757 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a 758 CONST_INT is not valid, because after the replacement, the 759 original mode would be gone. Unfortunately, we can't tell 760 when do_SUBST is called to replace the operand thereof, so we 761 perform this test on oldval instead, checking whether an 762 invalid replacement took place before we got here. */ 763 gcc_assert (!(GET_CODE (oldval) == SUBREG 764 && CONST_INT_P (SUBREG_REG (oldval)))); 765 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND 766 && CONST_INT_P (XEXP (oldval, 0)))); 767 } 768 769 if (undobuf.frees) 770 buf = undobuf.frees, undobuf.frees = buf->next; 771 else 772 buf = XNEW (struct undo); 773 774 buf->kind = UNDO_RTX; 775 buf->where.r = into; 776 buf->old_contents.r = oldval; 777 *into = newval; 778 779 buf->next = undobuf.undos, undobuf.undos = buf; 780 } 781 782 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL)) 783 784 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution 785 for the value of a HOST_WIDE_INT value (including CONST_INT) is 786 not safe. */ 787 788 static void 789 do_SUBST_INT (int *into, int newval) 790 { 791 struct undo *buf; 792 int oldval = *into; 793 794 if (oldval == newval) 795 return; 796 797 if (undobuf.frees) 798 buf = undobuf.frees, undobuf.frees = buf->next; 799 else 800 buf = XNEW (struct undo); 801 802 buf->kind = UNDO_INT; 803 buf->where.i = into; 804 buf->old_contents.i = oldval; 805 *into = newval; 806 807 buf->next = undobuf.undos, undobuf.undos = buf; 808 } 809 810 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL)) 811 812 /* Similar to SUBST, but just substitute the mode. This is used when 813 changing the mode of a pseudo-register, so that any other 814 references to the entry in the regno_reg_rtx array will change as 815 well. */ 816 817 static void 818 do_SUBST_MODE (rtx *into, machine_mode newval) 819 { 820 struct undo *buf; 821 machine_mode oldval = GET_MODE (*into); 822 823 if (oldval == newval) 824 return; 825 826 if (undobuf.frees) 827 buf = undobuf.frees, undobuf.frees = buf->next; 828 else 829 buf = XNEW (struct undo); 830 831 buf->kind = UNDO_MODE; 832 buf->where.r = into; 833 buf->old_contents.m = oldval; 834 adjust_reg_mode (*into, newval); 835 836 buf->next = undobuf.undos, undobuf.undos = buf; 837 } 838 839 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL)) 840 841 #ifndef HAVE_cc0 842 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */ 843 844 static void 845 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval) 846 { 847 struct undo *buf; 848 struct insn_link * oldval = *into; 849 850 if (oldval == newval) 851 return; 852 853 if (undobuf.frees) 854 buf = undobuf.frees, undobuf.frees = buf->next; 855 else 856 buf = XNEW (struct undo); 857 858 buf->kind = UNDO_LINKS; 859 buf->where.l = into; 860 buf->old_contents.l = oldval; 861 *into = newval; 862 863 buf->next = undobuf.undos, undobuf.undos = buf; 864 } 865 866 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval) 867 #endif 868 869 /* Subroutine of try_combine. Determine whether the replacement patterns 870 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost 871 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note 872 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and 873 undobuf.other_insn may also both be NULL_RTX. Return false if the cost 874 of all the instructions can be estimated and the replacements are more 875 expensive than the original sequence. */ 876 877 static bool 878 combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3, 879 rtx newpat, rtx newi2pat, rtx newotherpat) 880 { 881 int i0_cost, i1_cost, i2_cost, i3_cost; 882 int new_i2_cost, new_i3_cost; 883 int old_cost, new_cost; 884 885 /* Lookup the original insn_rtx_costs. */ 886 i2_cost = INSN_COST (i2); 887 i3_cost = INSN_COST (i3); 888 889 if (i1) 890 { 891 i1_cost = INSN_COST (i1); 892 if (i0) 893 { 894 i0_cost = INSN_COST (i0); 895 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0 896 ? i0_cost + i1_cost + i2_cost + i3_cost : 0); 897 } 898 else 899 { 900 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0 901 ? i1_cost + i2_cost + i3_cost : 0); 902 i0_cost = 0; 903 } 904 } 905 else 906 { 907 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0; 908 i1_cost = i0_cost = 0; 909 } 910 911 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice; 912 correct that. */ 913 if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2)) 914 old_cost -= i1_cost; 915 916 917 /* Calculate the replacement insn_rtx_costs. */ 918 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p); 919 if (newi2pat) 920 { 921 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p); 922 new_cost = (new_i2_cost > 0 && new_i3_cost > 0) 923 ? new_i2_cost + new_i3_cost : 0; 924 } 925 else 926 { 927 new_cost = new_i3_cost; 928 new_i2_cost = 0; 929 } 930 931 if (undobuf.other_insn) 932 { 933 int old_other_cost, new_other_cost; 934 935 old_other_cost = INSN_COST (undobuf.other_insn); 936 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p); 937 if (old_other_cost > 0 && new_other_cost > 0) 938 { 939 old_cost += old_other_cost; 940 new_cost += new_other_cost; 941 } 942 else 943 old_cost = 0; 944 } 945 946 /* Disallow this combination if both new_cost and old_cost are greater than 947 zero, and new_cost is greater than old cost. */ 948 int reject = old_cost > 0 && new_cost > old_cost; 949 950 if (dump_file) 951 { 952 fprintf (dump_file, "%s combination of insns ", 953 reject ? "rejecting" : "allowing"); 954 if (i0) 955 fprintf (dump_file, "%d, ", INSN_UID (i0)); 956 if (i1 && INSN_UID (i1) != INSN_UID (i2)) 957 fprintf (dump_file, "%d, ", INSN_UID (i1)); 958 fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3)); 959 960 fprintf (dump_file, "original costs "); 961 if (i0) 962 fprintf (dump_file, "%d + ", i0_cost); 963 if (i1 && INSN_UID (i1) != INSN_UID (i2)) 964 fprintf (dump_file, "%d + ", i1_cost); 965 fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost); 966 967 if (newi2pat) 968 fprintf (dump_file, "replacement costs %d + %d = %d\n", 969 new_i2_cost, new_i3_cost, new_cost); 970 else 971 fprintf (dump_file, "replacement cost %d\n", new_cost); 972 } 973 974 if (reject) 975 return false; 976 977 /* Update the uid_insn_cost array with the replacement costs. */ 978 INSN_COST (i2) = new_i2_cost; 979 INSN_COST (i3) = new_i3_cost; 980 if (i1) 981 { 982 INSN_COST (i1) = 0; 983 if (i0) 984 INSN_COST (i0) = 0; 985 } 986 987 return true; 988 } 989 990 991 /* Delete any insns that copy a register to itself. */ 992 993 static void 994 delete_noop_moves (void) 995 { 996 rtx_insn *insn, *next; 997 basic_block bb; 998 999 FOR_EACH_BB_FN (bb, cfun) 1000 { 1001 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next) 1002 { 1003 next = NEXT_INSN (insn); 1004 if (INSN_P (insn) && noop_move_p (insn)) 1005 { 1006 if (dump_file) 1007 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn)); 1008 1009 delete_insn_and_edges (insn); 1010 } 1011 } 1012 } 1013 } 1014 1015 1016 /* Return false if we do not want to (or cannot) combine DEF. */ 1017 static bool 1018 can_combine_def_p (df_ref def) 1019 { 1020 /* Do not consider if it is pre/post modification in MEM. */ 1021 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY) 1022 return false; 1023 1024 unsigned int regno = DF_REF_REGNO (def); 1025 1026 /* Do not combine frame pointer adjustments. */ 1027 if ((regno == FRAME_POINTER_REGNUM 1028 && (!reload_completed || frame_pointer_needed)) 1029 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER 1030 || (regno == HARD_FRAME_POINTER_REGNUM 1031 && (!reload_completed || frame_pointer_needed)) 1032 #endif 1033 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 1034 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) 1035 #endif 1036 ) 1037 return false; 1038 1039 return true; 1040 } 1041 1042 /* Return false if we do not want to (or cannot) combine USE. */ 1043 static bool 1044 can_combine_use_p (df_ref use) 1045 { 1046 /* Do not consider the usage of the stack pointer by function call. */ 1047 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE) 1048 return false; 1049 1050 return true; 1051 } 1052 1053 /* Fill in log links field for all insns. */ 1054 1055 static void 1056 create_log_links (void) 1057 { 1058 basic_block bb; 1059 rtx_insn **next_use; 1060 rtx_insn *insn; 1061 df_ref def, use; 1062 1063 next_use = XCNEWVEC (rtx_insn *, max_reg_num ()); 1064 1065 /* Pass through each block from the end, recording the uses of each 1066 register and establishing log links when def is encountered. 1067 Note that we do not clear next_use array in order to save time, 1068 so we have to test whether the use is in the same basic block as def. 1069 1070 There are a few cases below when we do not consider the definition or 1071 usage -- these are taken from original flow.c did. Don't ask me why it is 1072 done this way; I don't know and if it works, I don't want to know. */ 1073 1074 FOR_EACH_BB_FN (bb, cfun) 1075 { 1076 FOR_BB_INSNS_REVERSE (bb, insn) 1077 { 1078 if (!NONDEBUG_INSN_P (insn)) 1079 continue; 1080 1081 /* Log links are created only once. */ 1082 gcc_assert (!LOG_LINKS (insn)); 1083 1084 FOR_EACH_INSN_DEF (def, insn) 1085 { 1086 unsigned int regno = DF_REF_REGNO (def); 1087 rtx_insn *use_insn; 1088 1089 if (!next_use[regno]) 1090 continue; 1091 1092 if (!can_combine_def_p (def)) 1093 continue; 1094 1095 use_insn = next_use[regno]; 1096 next_use[regno] = NULL; 1097 1098 if (BLOCK_FOR_INSN (use_insn) != bb) 1099 continue; 1100 1101 /* flow.c claimed: 1102 1103 We don't build a LOG_LINK for hard registers contained 1104 in ASM_OPERANDs. If these registers get replaced, 1105 we might wind up changing the semantics of the insn, 1106 even if reload can make what appear to be valid 1107 assignments later. */ 1108 if (regno < FIRST_PSEUDO_REGISTER 1109 && asm_noperands (PATTERN (use_insn)) >= 0) 1110 continue; 1111 1112 /* Don't add duplicate links between instructions. */ 1113 struct insn_link *links; 1114 FOR_EACH_LOG_LINK (links, use_insn) 1115 if (insn == links->insn && regno == links->regno) 1116 break; 1117 1118 if (!links) 1119 LOG_LINKS (use_insn) 1120 = alloc_insn_link (insn, regno, LOG_LINKS (use_insn)); 1121 } 1122 1123 FOR_EACH_INSN_USE (use, insn) 1124 if (can_combine_use_p (use)) 1125 next_use[DF_REF_REGNO (use)] = insn; 1126 } 1127 } 1128 1129 free (next_use); 1130 } 1131 1132 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return 1133 true if we found a LOG_LINK that proves that A feeds B. This only works 1134 if there are no instructions between A and B which could have a link 1135 depending on A, since in that case we would not record a link for B. 1136 We also check the implicit dependency created by a cc0 setter/user 1137 pair. */ 1138 1139 static bool 1140 insn_a_feeds_b (rtx_insn *a, rtx_insn *b) 1141 { 1142 struct insn_link *links; 1143 FOR_EACH_LOG_LINK (links, b) 1144 if (links->insn == a) 1145 return true; 1146 #ifdef HAVE_cc0 1147 if (sets_cc0_p (a)) 1148 return true; 1149 #endif 1150 return false; 1151 } 1152 1153 /* Main entry point for combiner. F is the first insn of the function. 1154 NREGS is the first unused pseudo-reg number. 1155 1156 Return nonzero if the combiner has turned an indirect jump 1157 instruction into a direct jump. */ 1158 static int 1159 combine_instructions (rtx_insn *f, unsigned int nregs) 1160 { 1161 rtx_insn *insn, *next; 1162 #ifdef HAVE_cc0 1163 rtx_insn *prev; 1164 #endif 1165 struct insn_link *links, *nextlinks; 1166 rtx_insn *first; 1167 basic_block last_bb; 1168 1169 int new_direct_jump_p = 0; 1170 1171 for (first = f; first && !INSN_P (first); ) 1172 first = NEXT_INSN (first); 1173 if (!first) 1174 return 0; 1175 1176 combine_attempts = 0; 1177 combine_merges = 0; 1178 combine_extras = 0; 1179 combine_successes = 0; 1180 1181 rtl_hooks = combine_rtl_hooks; 1182 1183 reg_stat.safe_grow_cleared (nregs); 1184 1185 init_recog_no_volatile (); 1186 1187 /* Allocate array for insn info. */ 1188 max_uid_known = get_max_uid (); 1189 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1); 1190 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1); 1191 gcc_obstack_init (&insn_link_obstack); 1192 1193 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); 1194 1195 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause 1196 problems when, for example, we have j <<= 1 in a loop. */ 1197 1198 nonzero_sign_valid = 0; 1199 label_tick = label_tick_ebb_start = 1; 1200 1201 /* Scan all SETs and see if we can deduce anything about what 1202 bits are known to be zero for some registers and how many copies 1203 of the sign bit are known to exist for those registers. 1204 1205 Also set any known values so that we can use it while searching 1206 for what bits are known to be set. */ 1207 1208 setup_incoming_promotions (first); 1209 /* Allow the entry block and the first block to fall into the same EBB. 1210 Conceptually the incoming promotions are assigned to the entry block. */ 1211 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun); 1212 1213 create_log_links (); 1214 FOR_EACH_BB_FN (this_basic_block, cfun) 1215 { 1216 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); 1217 last_call_luid = 0; 1218 mem_last_set = -1; 1219 1220 label_tick++; 1221 if (!single_pred_p (this_basic_block) 1222 || single_pred (this_basic_block) != last_bb) 1223 label_tick_ebb_start = label_tick; 1224 last_bb = this_basic_block; 1225 1226 FOR_BB_INSNS (this_basic_block, insn) 1227 if (INSN_P (insn) && BLOCK_FOR_INSN (insn)) 1228 { 1229 #ifdef AUTO_INC_DEC 1230 rtx links; 1231 #endif 1232 1233 subst_low_luid = DF_INSN_LUID (insn); 1234 subst_insn = insn; 1235 1236 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, 1237 insn); 1238 record_dead_and_set_regs (insn); 1239 1240 #ifdef AUTO_INC_DEC 1241 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 1242 if (REG_NOTE_KIND (links) == REG_INC) 1243 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, 1244 insn); 1245 #endif 1246 1247 /* Record the current insn_rtx_cost of this instruction. */ 1248 if (NONJUMP_INSN_P (insn)) 1249 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn), 1250 optimize_this_for_speed_p); 1251 if (dump_file) 1252 fprintf (dump_file, "insn_cost %d: %d\n", 1253 INSN_UID (insn), INSN_COST (insn)); 1254 } 1255 } 1256 1257 nonzero_sign_valid = 1; 1258 1259 /* Now scan all the insns in forward order. */ 1260 label_tick = label_tick_ebb_start = 1; 1261 init_reg_last (); 1262 setup_incoming_promotions (first); 1263 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun); 1264 int max_combine = PARAM_VALUE (PARAM_MAX_COMBINE_INSNS); 1265 1266 FOR_EACH_BB_FN (this_basic_block, cfun) 1267 { 1268 rtx_insn *last_combined_insn = NULL; 1269 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block); 1270 last_call_luid = 0; 1271 mem_last_set = -1; 1272 1273 label_tick++; 1274 if (!single_pred_p (this_basic_block) 1275 || single_pred (this_basic_block) != last_bb) 1276 label_tick_ebb_start = label_tick; 1277 last_bb = this_basic_block; 1278 1279 rtl_profile_for_bb (this_basic_block); 1280 for (insn = BB_HEAD (this_basic_block); 1281 insn != NEXT_INSN (BB_END (this_basic_block)); 1282 insn = next ? next : NEXT_INSN (insn)) 1283 { 1284 next = 0; 1285 if (!NONDEBUG_INSN_P (insn)) 1286 continue; 1287 1288 while (last_combined_insn 1289 && last_combined_insn->deleted ()) 1290 last_combined_insn = PREV_INSN (last_combined_insn); 1291 if (last_combined_insn == NULL_RTX 1292 || BARRIER_P (last_combined_insn) 1293 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block 1294 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn)) 1295 last_combined_insn = insn; 1296 1297 /* See if we know about function return values before this 1298 insn based upon SUBREG flags. */ 1299 check_promoted_subreg (insn, PATTERN (insn)); 1300 1301 /* See if we can find hardregs and subreg of pseudos in 1302 narrower modes. This could help turning TRUNCATEs 1303 into SUBREGs. */ 1304 note_uses (&PATTERN (insn), record_truncated_values, NULL); 1305 1306 /* Try this insn with each insn it links back to. */ 1307 1308 FOR_EACH_LOG_LINK (links, insn) 1309 if ((next = try_combine (insn, links->insn, NULL, 1310 NULL, &new_direct_jump_p, 1311 last_combined_insn)) != 0) 1312 { 1313 statistics_counter_event (cfun, "two-insn combine", 1); 1314 goto retry; 1315 } 1316 1317 /* Try each sequence of three linked insns ending with this one. */ 1318 1319 if (max_combine >= 3) 1320 FOR_EACH_LOG_LINK (links, insn) 1321 { 1322 rtx_insn *link = links->insn; 1323 1324 /* If the linked insn has been replaced by a note, then there 1325 is no point in pursuing this chain any further. */ 1326 if (NOTE_P (link)) 1327 continue; 1328 1329 FOR_EACH_LOG_LINK (nextlinks, link) 1330 if ((next = try_combine (insn, link, nextlinks->insn, 1331 NULL, &new_direct_jump_p, 1332 last_combined_insn)) != 0) 1333 { 1334 statistics_counter_event (cfun, "three-insn combine", 1); 1335 goto retry; 1336 } 1337 } 1338 1339 #ifdef HAVE_cc0 1340 /* Try to combine a jump insn that uses CC0 1341 with a preceding insn that sets CC0, and maybe with its 1342 logical predecessor as well. 1343 This is how we make decrement-and-branch insns. 1344 We need this special code because data flow connections 1345 via CC0 do not get entered in LOG_LINKS. */ 1346 1347 if (JUMP_P (insn) 1348 && (prev = prev_nonnote_insn (insn)) != 0 1349 && NONJUMP_INSN_P (prev) 1350 && sets_cc0_p (PATTERN (prev))) 1351 { 1352 if ((next = try_combine (insn, prev, NULL, NULL, 1353 &new_direct_jump_p, 1354 last_combined_insn)) != 0) 1355 goto retry; 1356 1357 FOR_EACH_LOG_LINK (nextlinks, prev) 1358 if ((next = try_combine (insn, prev, nextlinks->insn, 1359 NULL, &new_direct_jump_p, 1360 last_combined_insn)) != 0) 1361 goto retry; 1362 } 1363 1364 /* Do the same for an insn that explicitly references CC0. */ 1365 if (NONJUMP_INSN_P (insn) 1366 && (prev = prev_nonnote_insn (insn)) != 0 1367 && NONJUMP_INSN_P (prev) 1368 && sets_cc0_p (PATTERN (prev)) 1369 && GET_CODE (PATTERN (insn)) == SET 1370 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) 1371 { 1372 if ((next = try_combine (insn, prev, NULL, NULL, 1373 &new_direct_jump_p, 1374 last_combined_insn)) != 0) 1375 goto retry; 1376 1377 FOR_EACH_LOG_LINK (nextlinks, prev) 1378 if ((next = try_combine (insn, prev, nextlinks->insn, 1379 NULL, &new_direct_jump_p, 1380 last_combined_insn)) != 0) 1381 goto retry; 1382 } 1383 1384 /* Finally, see if any of the insns that this insn links to 1385 explicitly references CC0. If so, try this insn, that insn, 1386 and its predecessor if it sets CC0. */ 1387 FOR_EACH_LOG_LINK (links, insn) 1388 if (NONJUMP_INSN_P (links->insn) 1389 && GET_CODE (PATTERN (links->insn)) == SET 1390 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn))) 1391 && (prev = prev_nonnote_insn (links->insn)) != 0 1392 && NONJUMP_INSN_P (prev) 1393 && sets_cc0_p (PATTERN (prev)) 1394 && (next = try_combine (insn, links->insn, 1395 prev, NULL, &new_direct_jump_p, 1396 last_combined_insn)) != 0) 1397 goto retry; 1398 #endif 1399 1400 /* Try combining an insn with two different insns whose results it 1401 uses. */ 1402 if (max_combine >= 3) 1403 FOR_EACH_LOG_LINK (links, insn) 1404 for (nextlinks = links->next; nextlinks; 1405 nextlinks = nextlinks->next) 1406 if ((next = try_combine (insn, links->insn, 1407 nextlinks->insn, NULL, 1408 &new_direct_jump_p, 1409 last_combined_insn)) != 0) 1410 1411 { 1412 statistics_counter_event (cfun, "three-insn combine", 1); 1413 goto retry; 1414 } 1415 1416 /* Try four-instruction combinations. */ 1417 if (max_combine >= 4) 1418 FOR_EACH_LOG_LINK (links, insn) 1419 { 1420 struct insn_link *next1; 1421 rtx_insn *link = links->insn; 1422 1423 /* If the linked insn has been replaced by a note, then there 1424 is no point in pursuing this chain any further. */ 1425 if (NOTE_P (link)) 1426 continue; 1427 1428 FOR_EACH_LOG_LINK (next1, link) 1429 { 1430 rtx_insn *link1 = next1->insn; 1431 if (NOTE_P (link1)) 1432 continue; 1433 /* I0 -> I1 -> I2 -> I3. */ 1434 FOR_EACH_LOG_LINK (nextlinks, link1) 1435 if ((next = try_combine (insn, link, link1, 1436 nextlinks->insn, 1437 &new_direct_jump_p, 1438 last_combined_insn)) != 0) 1439 { 1440 statistics_counter_event (cfun, "four-insn combine", 1); 1441 goto retry; 1442 } 1443 /* I0, I1 -> I2, I2 -> I3. */ 1444 for (nextlinks = next1->next; nextlinks; 1445 nextlinks = nextlinks->next) 1446 if ((next = try_combine (insn, link, link1, 1447 nextlinks->insn, 1448 &new_direct_jump_p, 1449 last_combined_insn)) != 0) 1450 { 1451 statistics_counter_event (cfun, "four-insn combine", 1); 1452 goto retry; 1453 } 1454 } 1455 1456 for (next1 = links->next; next1; next1 = next1->next) 1457 { 1458 rtx_insn *link1 = next1->insn; 1459 if (NOTE_P (link1)) 1460 continue; 1461 /* I0 -> I2; I1, I2 -> I3. */ 1462 FOR_EACH_LOG_LINK (nextlinks, link) 1463 if ((next = try_combine (insn, link, link1, 1464 nextlinks->insn, 1465 &new_direct_jump_p, 1466 last_combined_insn)) != 0) 1467 { 1468 statistics_counter_event (cfun, "four-insn combine", 1); 1469 goto retry; 1470 } 1471 /* I0 -> I1; I1, I2 -> I3. */ 1472 FOR_EACH_LOG_LINK (nextlinks, link1) 1473 if ((next = try_combine (insn, link, link1, 1474 nextlinks->insn, 1475 &new_direct_jump_p, 1476 last_combined_insn)) != 0) 1477 { 1478 statistics_counter_event (cfun, "four-insn combine", 1); 1479 goto retry; 1480 } 1481 } 1482 } 1483 1484 /* Try this insn with each REG_EQUAL note it links back to. */ 1485 FOR_EACH_LOG_LINK (links, insn) 1486 { 1487 rtx set, note; 1488 rtx_insn *temp = links->insn; 1489 if ((set = single_set (temp)) != 0 1490 && (note = find_reg_equal_equiv_note (temp)) != 0 1491 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST 1492 /* Avoid using a register that may already been marked 1493 dead by an earlier instruction. */ 1494 && ! unmentioned_reg_p (note, SET_SRC (set)) 1495 && (GET_MODE (note) == VOIDmode 1496 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set))) 1497 : GET_MODE (SET_DEST (set)) == GET_MODE (note))) 1498 { 1499 /* Temporarily replace the set's source with the 1500 contents of the REG_EQUAL note. The insn will 1501 be deleted or recognized by try_combine. */ 1502 rtx orig = SET_SRC (set); 1503 SET_SRC (set) = note; 1504 i2mod = temp; 1505 i2mod_old_rhs = copy_rtx (orig); 1506 i2mod_new_rhs = copy_rtx (note); 1507 next = try_combine (insn, i2mod, NULL, NULL, 1508 &new_direct_jump_p, 1509 last_combined_insn); 1510 i2mod = NULL; 1511 if (next) 1512 { 1513 statistics_counter_event (cfun, "insn-with-note combine", 1); 1514 goto retry; 1515 } 1516 SET_SRC (set) = orig; 1517 } 1518 } 1519 1520 if (!NOTE_P (insn)) 1521 record_dead_and_set_regs (insn); 1522 1523 retry: 1524 ; 1525 } 1526 } 1527 1528 default_rtl_profile (); 1529 clear_bb_flags (); 1530 new_direct_jump_p |= purge_all_dead_edges (); 1531 delete_noop_moves (); 1532 1533 /* Clean up. */ 1534 obstack_free (&insn_link_obstack, NULL); 1535 free (uid_log_links); 1536 free (uid_insn_cost); 1537 reg_stat.release (); 1538 1539 { 1540 struct undo *undo, *next; 1541 for (undo = undobuf.frees; undo; undo = next) 1542 { 1543 next = undo->next; 1544 free (undo); 1545 } 1546 undobuf.frees = 0; 1547 } 1548 1549 total_attempts += combine_attempts; 1550 total_merges += combine_merges; 1551 total_extras += combine_extras; 1552 total_successes += combine_successes; 1553 1554 nonzero_sign_valid = 0; 1555 rtl_hooks = general_rtl_hooks; 1556 1557 /* Make recognizer allow volatile MEMs again. */ 1558 init_recog (); 1559 1560 return new_direct_jump_p; 1561 } 1562 1563 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */ 1564 1565 static void 1566 init_reg_last (void) 1567 { 1568 unsigned int i; 1569 reg_stat_type *p; 1570 1571 FOR_EACH_VEC_ELT (reg_stat, i, p) 1572 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies)); 1573 } 1574 1575 /* Set up any promoted values for incoming argument registers. */ 1576 1577 static void 1578 setup_incoming_promotions (rtx_insn *first) 1579 { 1580 tree arg; 1581 bool strictly_local = false; 1582 1583 for (arg = DECL_ARGUMENTS (current_function_decl); arg; 1584 arg = DECL_CHAIN (arg)) 1585 { 1586 rtx x, reg = DECL_INCOMING_RTL (arg); 1587 int uns1, uns3; 1588 machine_mode mode1, mode2, mode3, mode4; 1589 1590 /* Only continue if the incoming argument is in a register. */ 1591 if (!REG_P (reg)) 1592 continue; 1593 1594 /* Determine, if possible, whether all call sites of the current 1595 function lie within the current compilation unit. (This does 1596 take into account the exporting of a function via taking its 1597 address, and so forth.) */ 1598 strictly_local = cgraph_node::local_info (current_function_decl)->local; 1599 1600 /* The mode and signedness of the argument before any promotions happen 1601 (equal to the mode of the pseudo holding it at that stage). */ 1602 mode1 = TYPE_MODE (TREE_TYPE (arg)); 1603 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg)); 1604 1605 /* The mode and signedness of the argument after any source language and 1606 TARGET_PROMOTE_PROTOTYPES-driven promotions. */ 1607 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg)); 1608 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg)); 1609 1610 /* The mode and signedness of the argument as it is actually passed, 1611 see assign_parm_setup_reg in function.c. */ 1612 mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3, 1613 TREE_TYPE (cfun->decl), 0); 1614 1615 /* The mode of the register in which the argument is being passed. */ 1616 mode4 = GET_MODE (reg); 1617 1618 /* Eliminate sign extensions in the callee when: 1619 (a) A mode promotion has occurred; */ 1620 if (mode1 == mode3) 1621 continue; 1622 /* (b) The mode of the register is the same as the mode of 1623 the argument as it is passed; */ 1624 if (mode3 != mode4) 1625 continue; 1626 /* (c) There's no language level extension; */ 1627 if (mode1 == mode2) 1628 ; 1629 /* (c.1) All callers are from the current compilation unit. If that's 1630 the case we don't have to rely on an ABI, we only have to know 1631 what we're generating right now, and we know that we will do the 1632 mode1 to mode2 promotion with the given sign. */ 1633 else if (!strictly_local) 1634 continue; 1635 /* (c.2) The combination of the two promotions is useful. This is 1636 true when the signs match, or if the first promotion is unsigned. 1637 In the later case, (sign_extend (zero_extend x)) is the same as 1638 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */ 1639 else if (uns1) 1640 uns3 = true; 1641 else if (uns3) 1642 continue; 1643 1644 /* Record that the value was promoted from mode1 to mode3, 1645 so that any sign extension at the head of the current 1646 function may be eliminated. */ 1647 x = gen_rtx_CLOBBER (mode1, const0_rtx); 1648 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x); 1649 record_value_for_reg (reg, first, x); 1650 } 1651 } 1652 1653 /* Called via note_stores. If X is a pseudo that is narrower than 1654 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. 1655 1656 If we are setting only a portion of X and we can't figure out what 1657 portion, assume all bits will be used since we don't know what will 1658 be happening. 1659 1660 Similarly, set how many bits of X are known to be copies of the sign bit 1661 at all locations in the function. This is the smallest number implied 1662 by any set of X. */ 1663 1664 static void 1665 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data) 1666 { 1667 rtx_insn *insn = (rtx_insn *) data; 1668 unsigned int num; 1669 1670 if (REG_P (x) 1671 && REGNO (x) >= FIRST_PSEUDO_REGISTER 1672 /* If this register is undefined at the start of the file, we can't 1673 say what its contents were. */ 1674 && ! REGNO_REG_SET_P 1675 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x)) 1676 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))) 1677 { 1678 reg_stat_type *rsp = ®_stat[REGNO (x)]; 1679 1680 if (set == 0 || GET_CODE (set) == CLOBBER) 1681 { 1682 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); 1683 rsp->sign_bit_copies = 1; 1684 return; 1685 } 1686 1687 /* If this register is being initialized using itself, and the 1688 register is uninitialized in this basic block, and there are 1689 no LOG_LINKS which set the register, then part of the 1690 register is uninitialized. In that case we can't assume 1691 anything about the number of nonzero bits. 1692 1693 ??? We could do better if we checked this in 1694 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we 1695 could avoid making assumptions about the insn which initially 1696 sets the register, while still using the information in other 1697 insns. We would have to be careful to check every insn 1698 involved in the combination. */ 1699 1700 if (insn 1701 && reg_referenced_p (x, PATTERN (insn)) 1702 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)), 1703 REGNO (x))) 1704 { 1705 struct insn_link *link; 1706 1707 FOR_EACH_LOG_LINK (link, insn) 1708 if (dead_or_set_p (link->insn, x)) 1709 break; 1710 if (!link) 1711 { 1712 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); 1713 rsp->sign_bit_copies = 1; 1714 return; 1715 } 1716 } 1717 1718 /* If this is a complex assignment, see if we can convert it into a 1719 simple assignment. */ 1720 set = expand_field_assignment (set); 1721 1722 /* If this is a simple assignment, or we have a paradoxical SUBREG, 1723 set what we know about X. */ 1724 1725 if (SET_DEST (set) == x 1726 || (paradoxical_subreg_p (SET_DEST (set)) 1727 && SUBREG_REG (SET_DEST (set)) == x)) 1728 { 1729 rtx src = SET_SRC (set); 1730 1731 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND 1732 /* If X is narrower than a word and SRC is a non-negative 1733 constant that would appear negative in the mode of X, 1734 sign-extend it for use in reg_stat[].nonzero_bits because some 1735 machines (maybe most) will actually do the sign-extension 1736 and this is the conservative approach. 1737 1738 ??? For 2.5, try to tighten up the MD files in this regard 1739 instead of this kludge. */ 1740 1741 if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD 1742 && CONST_INT_P (src) 1743 && INTVAL (src) > 0 1744 && val_signbit_known_set_p (GET_MODE (x), INTVAL (src))) 1745 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x))); 1746 #endif 1747 1748 /* Don't call nonzero_bits if it cannot change anything. */ 1749 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0) 1750 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode); 1751 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); 1752 if (rsp->sign_bit_copies == 0 1753 || rsp->sign_bit_copies > num) 1754 rsp->sign_bit_copies = num; 1755 } 1756 else 1757 { 1758 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x)); 1759 rsp->sign_bit_copies = 1; 1760 } 1761 } 1762 } 1763 1764 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are 1765 optionally insns that were previously combined into I3 or that will be 1766 combined into the merger of INSN and I3. The order is PRED, PRED2, 1767 INSN, SUCC, SUCC2, I3. 1768 1769 Return 0 if the combination is not allowed for any reason. 1770 1771 If the combination is allowed, *PDEST will be set to the single 1772 destination of INSN and *PSRC to the single source, and this function 1773 will return 1. */ 1774 1775 static int 1776 can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED, 1777 rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2, 1778 rtx *pdest, rtx *psrc) 1779 { 1780 int i; 1781 const_rtx set = 0; 1782 rtx src, dest; 1783 rtx_insn *p; 1784 #ifdef AUTO_INC_DEC 1785 rtx link; 1786 #endif 1787 bool all_adjacent = true; 1788 int (*is_volatile_p) (const_rtx); 1789 1790 if (succ) 1791 { 1792 if (succ2) 1793 { 1794 if (next_active_insn (succ2) != i3) 1795 all_adjacent = false; 1796 if (next_active_insn (succ) != succ2) 1797 all_adjacent = false; 1798 } 1799 else if (next_active_insn (succ) != i3) 1800 all_adjacent = false; 1801 if (next_active_insn (insn) != succ) 1802 all_adjacent = false; 1803 } 1804 else if (next_active_insn (insn) != i3) 1805 all_adjacent = false; 1806 1807 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. 1808 or a PARALLEL consisting of such a SET and CLOBBERs. 1809 1810 If INSN has CLOBBER parallel parts, ignore them for our processing. 1811 By definition, these happen during the execution of the insn. When it 1812 is merged with another insn, all bets are off. If they are, in fact, 1813 needed and aren't also supplied in I3, they may be added by 1814 recog_for_combine. Otherwise, it won't match. 1815 1816 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED 1817 note. 1818 1819 Get the source and destination of INSN. If more than one, can't 1820 combine. */ 1821 1822 if (GET_CODE (PATTERN (insn)) == SET) 1823 set = PATTERN (insn); 1824 else if (GET_CODE (PATTERN (insn)) == PARALLEL 1825 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 1826 { 1827 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 1828 { 1829 rtx elt = XVECEXP (PATTERN (insn), 0, i); 1830 1831 switch (GET_CODE (elt)) 1832 { 1833 /* This is important to combine floating point insns 1834 for the SH4 port. */ 1835 case USE: 1836 /* Combining an isolated USE doesn't make sense. 1837 We depend here on combinable_i3pat to reject them. */ 1838 /* The code below this loop only verifies that the inputs of 1839 the SET in INSN do not change. We call reg_set_between_p 1840 to verify that the REG in the USE does not change between 1841 I3 and INSN. 1842 If the USE in INSN was for a pseudo register, the matching 1843 insn pattern will likely match any register; combining this 1844 with any other USE would only be safe if we knew that the 1845 used registers have identical values, or if there was 1846 something to tell them apart, e.g. different modes. For 1847 now, we forgo such complicated tests and simply disallow 1848 combining of USES of pseudo registers with any other USE. */ 1849 if (REG_P (XEXP (elt, 0)) 1850 && GET_CODE (PATTERN (i3)) == PARALLEL) 1851 { 1852 rtx i3pat = PATTERN (i3); 1853 int i = XVECLEN (i3pat, 0) - 1; 1854 unsigned int regno = REGNO (XEXP (elt, 0)); 1855 1856 do 1857 { 1858 rtx i3elt = XVECEXP (i3pat, 0, i); 1859 1860 if (GET_CODE (i3elt) == USE 1861 && REG_P (XEXP (i3elt, 0)) 1862 && (REGNO (XEXP (i3elt, 0)) == regno 1863 ? reg_set_between_p (XEXP (elt, 0), 1864 PREV_INSN (insn), i3) 1865 : regno >= FIRST_PSEUDO_REGISTER)) 1866 return 0; 1867 } 1868 while (--i >= 0); 1869 } 1870 break; 1871 1872 /* We can ignore CLOBBERs. */ 1873 case CLOBBER: 1874 break; 1875 1876 case SET: 1877 /* Ignore SETs whose result isn't used but not those that 1878 have side-effects. */ 1879 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) 1880 && insn_nothrow_p (insn) 1881 && !side_effects_p (elt)) 1882 break; 1883 1884 /* If we have already found a SET, this is a second one and 1885 so we cannot combine with this insn. */ 1886 if (set) 1887 return 0; 1888 1889 set = elt; 1890 break; 1891 1892 default: 1893 /* Anything else means we can't combine. */ 1894 return 0; 1895 } 1896 } 1897 1898 if (set == 0 1899 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, 1900 so don't do anything with it. */ 1901 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) 1902 return 0; 1903 } 1904 else 1905 return 0; 1906 1907 if (set == 0) 1908 return 0; 1909 1910 /* The simplification in expand_field_assignment may call back to 1911 get_last_value, so set safe guard here. */ 1912 subst_low_luid = DF_INSN_LUID (insn); 1913 1914 set = expand_field_assignment (set); 1915 src = SET_SRC (set), dest = SET_DEST (set); 1916 1917 /* Don't eliminate a store in the stack pointer. */ 1918 if (dest == stack_pointer_rtx 1919 /* Don't combine with an insn that sets a register to itself if it has 1920 a REG_EQUAL note. This may be part of a LIBCALL sequence. */ 1921 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 1922 /* Can't merge an ASM_OPERANDS. */ 1923 || GET_CODE (src) == ASM_OPERANDS 1924 /* Can't merge a function call. */ 1925 || GET_CODE (src) == CALL 1926 /* Don't eliminate a function call argument. */ 1927 || (CALL_P (i3) 1928 && (find_reg_fusage (i3, USE, dest) 1929 || (REG_P (dest) 1930 && REGNO (dest) < FIRST_PSEUDO_REGISTER 1931 && global_regs[REGNO (dest)]))) 1932 /* Don't substitute into an incremented register. */ 1933 || FIND_REG_INC_NOTE (i3, dest) 1934 || (succ && FIND_REG_INC_NOTE (succ, dest)) 1935 || (succ2 && FIND_REG_INC_NOTE (succ2, dest)) 1936 /* Don't substitute into a non-local goto, this confuses CFG. */ 1937 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX)) 1938 /* Make sure that DEST is not used after SUCC but before I3. */ 1939 || (!all_adjacent 1940 && ((succ2 1941 && (reg_used_between_p (dest, succ2, i3) 1942 || reg_used_between_p (dest, succ, succ2))) 1943 || (!succ2 && succ && reg_used_between_p (dest, succ, i3)))) 1944 /* Make sure that the value that is to be substituted for the register 1945 does not use any registers whose values alter in between. However, 1946 If the insns are adjacent, a use can't cross a set even though we 1947 think it might (this can happen for a sequence of insns each setting 1948 the same destination; last_set of that register might point to 1949 a NOTE). If INSN has a REG_EQUIV note, the register is always 1950 equivalent to the memory so the substitution is valid even if there 1951 are intervening stores. Also, don't move a volatile asm or 1952 UNSPEC_VOLATILE across any other insns. */ 1953 || (! all_adjacent 1954 && (((!MEM_P (src) 1955 || ! find_reg_note (insn, REG_EQUIV, src)) 1956 && use_crosses_set_p (src, DF_INSN_LUID (insn))) 1957 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) 1958 || GET_CODE (src) == UNSPEC_VOLATILE)) 1959 /* Don't combine across a CALL_INSN, because that would possibly 1960 change whether the life span of some REGs crosses calls or not, 1961 and it is a pain to update that information. 1962 Exception: if source is a constant, moving it later can't hurt. 1963 Accept that as a special case. */ 1964 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src))) 1965 return 0; 1966 1967 /* DEST must either be a REG or CC0. */ 1968 if (REG_P (dest)) 1969 { 1970 /* If register alignment is being enforced for multi-word items in all 1971 cases except for parameters, it is possible to have a register copy 1972 insn referencing a hard register that is not allowed to contain the 1973 mode being copied and which would not be valid as an operand of most 1974 insns. Eliminate this problem by not combining with such an insn. 1975 1976 Also, on some machines we don't want to extend the life of a hard 1977 register. */ 1978 1979 if (REG_P (src) 1980 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER 1981 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) 1982 /* Don't extend the life of a hard register unless it is 1983 user variable (if we have few registers) or it can't 1984 fit into the desired register (meaning something special 1985 is going on). 1986 Also avoid substituting a return register into I3, because 1987 reload can't handle a conflict with constraints of other 1988 inputs. */ 1989 || (REGNO (src) < FIRST_PSEUDO_REGISTER 1990 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) 1991 return 0; 1992 } 1993 else if (GET_CODE (dest) != CC0) 1994 return 0; 1995 1996 1997 if (GET_CODE (PATTERN (i3)) == PARALLEL) 1998 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) 1999 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER) 2000 { 2001 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0); 2002 2003 /* If the clobber represents an earlyclobber operand, we must not 2004 substitute an expression containing the clobbered register. 2005 As we do not analyze the constraint strings here, we have to 2006 make the conservative assumption. However, if the register is 2007 a fixed hard reg, the clobber cannot represent any operand; 2008 we leave it up to the machine description to either accept or 2009 reject use-and-clobber patterns. */ 2010 if (!REG_P (reg) 2011 || REGNO (reg) >= FIRST_PSEUDO_REGISTER 2012 || !fixed_regs[REGNO (reg)]) 2013 if (reg_overlap_mentioned_p (reg, src)) 2014 return 0; 2015 } 2016 2017 /* If INSN contains anything volatile, or is an `asm' (whether volatile 2018 or not), reject, unless nothing volatile comes between it and I3 */ 2019 2020 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) 2021 { 2022 /* Make sure neither succ nor succ2 contains a volatile reference. */ 2023 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2))) 2024 return 0; 2025 if (succ != 0 && volatile_refs_p (PATTERN (succ))) 2026 return 0; 2027 /* We'll check insns between INSN and I3 below. */ 2028 } 2029 2030 /* If INSN is an asm, and DEST is a hard register, reject, since it has 2031 to be an explicit register variable, and was chosen for a reason. */ 2032 2033 if (GET_CODE (src) == ASM_OPERANDS 2034 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER) 2035 return 0; 2036 2037 /* If INSN contains volatile references (specifically volatile MEMs), 2038 we cannot combine across any other volatile references. 2039 Even if INSN doesn't contain volatile references, any intervening 2040 volatile insn might affect machine state. */ 2041 2042 is_volatile_p = volatile_refs_p (PATTERN (insn)) 2043 ? volatile_refs_p 2044 : volatile_insn_p; 2045 2046 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 2047 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p))) 2048 return 0; 2049 2050 /* If INSN contains an autoincrement or autodecrement, make sure that 2051 register is not used between there and I3, and not already used in 2052 I3 either. Neither must it be used in PRED or SUCC, if they exist. 2053 Also insist that I3 not be a jump; if it were one 2054 and the incremented register were spilled, we would lose. */ 2055 2056 #ifdef AUTO_INC_DEC 2057 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 2058 if (REG_NOTE_KIND (link) == REG_INC 2059 && (JUMP_P (i3) 2060 || reg_used_between_p (XEXP (link, 0), insn, i3) 2061 || (pred != NULL_RTX 2062 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred))) 2063 || (pred2 != NULL_RTX 2064 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2))) 2065 || (succ != NULL_RTX 2066 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ))) 2067 || (succ2 != NULL_RTX 2068 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2))) 2069 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) 2070 return 0; 2071 #endif 2072 2073 #ifdef HAVE_cc0 2074 /* Don't combine an insn that follows a CC0-setting insn. 2075 An insn that uses CC0 must not be separated from the one that sets it. 2076 We do, however, allow I2 to follow a CC0-setting insn if that insn 2077 is passed as I1; in that case it will be deleted also. 2078 We also allow combining in this case if all the insns are adjacent 2079 because that would leave the two CC0 insns adjacent as well. 2080 It would be more logical to test whether CC0 occurs inside I1 or I2, 2081 but that would be much slower, and this ought to be equivalent. */ 2082 2083 p = prev_nonnote_insn (insn); 2084 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p)) 2085 && ! all_adjacent) 2086 return 0; 2087 #endif 2088 2089 /* If we get here, we have passed all the tests and the combination is 2090 to be allowed. */ 2091 2092 *pdest = dest; 2093 *psrc = src; 2094 2095 return 1; 2096 } 2097 2098 /* LOC is the location within I3 that contains its pattern or the component 2099 of a PARALLEL of the pattern. We validate that it is valid for combining. 2100 2101 One problem is if I3 modifies its output, as opposed to replacing it 2102 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as 2103 doing so would produce an insn that is not equivalent to the original insns. 2104 2105 Consider: 2106 2107 (set (reg:DI 101) (reg:DI 100)) 2108 (set (subreg:SI (reg:DI 101) 0) <foo>) 2109 2110 This is NOT equivalent to: 2111 2112 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) 2113 (set (reg:DI 101) (reg:DI 100))]) 2114 2115 Not only does this modify 100 (in which case it might still be valid 2116 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. 2117 2118 We can also run into a problem if I2 sets a register that I1 2119 uses and I1 gets directly substituted into I3 (not via I2). In that 2120 case, we would be getting the wrong value of I2DEST into I3, so we 2121 must reject the combination. This case occurs when I2 and I1 both 2122 feed into I3, rather than when I1 feeds into I2, which feeds into I3. 2123 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source 2124 of a SET must prevent combination from occurring. The same situation 2125 can occur for I0, in which case I0_NOT_IN_SRC is set. 2126 2127 Before doing the above check, we first try to expand a field assignment 2128 into a set of logical operations. 2129 2130 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which 2131 we place a register that is both set and used within I3. If more than one 2132 such register is detected, we fail. 2133 2134 Return 1 if the combination is valid, zero otherwise. */ 2135 2136 static int 2137 combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest, 2138 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed) 2139 { 2140 rtx x = *loc; 2141 2142 if (GET_CODE (x) == SET) 2143 { 2144 rtx set = x ; 2145 rtx dest = SET_DEST (set); 2146 rtx src = SET_SRC (set); 2147 rtx inner_dest = dest; 2148 rtx subdest; 2149 2150 while (GET_CODE (inner_dest) == STRICT_LOW_PART 2151 || GET_CODE (inner_dest) == SUBREG 2152 || GET_CODE (inner_dest) == ZERO_EXTRACT) 2153 inner_dest = XEXP (inner_dest, 0); 2154 2155 /* Check for the case where I3 modifies its output, as discussed 2156 above. We don't want to prevent pseudos from being combined 2157 into the address of a MEM, so only prevent the combination if 2158 i1 or i2 set the same MEM. */ 2159 if ((inner_dest != dest && 2160 (!MEM_P (inner_dest) 2161 || rtx_equal_p (i2dest, inner_dest) 2162 || (i1dest && rtx_equal_p (i1dest, inner_dest)) 2163 || (i0dest && rtx_equal_p (i0dest, inner_dest))) 2164 && (reg_overlap_mentioned_p (i2dest, inner_dest) 2165 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)) 2166 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest)))) 2167 2168 /* This is the same test done in can_combine_p except we can't test 2169 all_adjacent; we don't have to, since this instruction will stay 2170 in place, thus we are not considering increasing the lifetime of 2171 INNER_DEST. 2172 2173 Also, if this insn sets a function argument, combining it with 2174 something that might need a spill could clobber a previous 2175 function argument; the all_adjacent test in can_combine_p also 2176 checks this; here, we do a more specific test for this case. */ 2177 2178 || (REG_P (inner_dest) 2179 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 2180 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), 2181 GET_MODE (inner_dest)))) 2182 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)) 2183 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src))) 2184 return 0; 2185 2186 /* If DEST is used in I3, it is being killed in this insn, so 2187 record that for later. We have to consider paradoxical 2188 subregs here, since they kill the whole register, but we 2189 ignore partial subregs, STRICT_LOW_PART, etc. 2190 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the 2191 STACK_POINTER_REGNUM, since these are always considered to be 2192 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ 2193 subdest = dest; 2194 if (GET_CODE (subdest) == SUBREG 2195 && (GET_MODE_SIZE (GET_MODE (subdest)) 2196 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest))))) 2197 subdest = SUBREG_REG (subdest); 2198 if (pi3dest_killed 2199 && REG_P (subdest) 2200 && reg_referenced_p (subdest, PATTERN (i3)) 2201 && REGNO (subdest) != FRAME_POINTER_REGNUM 2202 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER 2203 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM 2204 #endif 2205 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 2206 && (REGNO (subdest) != ARG_POINTER_REGNUM 2207 || ! fixed_regs [REGNO (subdest)]) 2208 #endif 2209 && REGNO (subdest) != STACK_POINTER_REGNUM) 2210 { 2211 if (*pi3dest_killed) 2212 return 0; 2213 2214 *pi3dest_killed = subdest; 2215 } 2216 } 2217 2218 else if (GET_CODE (x) == PARALLEL) 2219 { 2220 int i; 2221 2222 for (i = 0; i < XVECLEN (x, 0); i++) 2223 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest, 2224 i1_not_in_src, i0_not_in_src, pi3dest_killed)) 2225 return 0; 2226 } 2227 2228 return 1; 2229 } 2230 2231 /* Return 1 if X is an arithmetic expression that contains a multiplication 2232 and division. We don't count multiplications by powers of two here. */ 2233 2234 static int 2235 contains_muldiv (rtx x) 2236 { 2237 switch (GET_CODE (x)) 2238 { 2239 case MOD: case DIV: case UMOD: case UDIV: 2240 return 1; 2241 2242 case MULT: 2243 return ! (CONST_INT_P (XEXP (x, 1)) 2244 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0); 2245 default: 2246 if (BINARY_P (x)) 2247 return contains_muldiv (XEXP (x, 0)) 2248 || contains_muldiv (XEXP (x, 1)); 2249 2250 if (UNARY_P (x)) 2251 return contains_muldiv (XEXP (x, 0)); 2252 2253 return 0; 2254 } 2255 } 2256 2257 /* Determine whether INSN can be used in a combination. Return nonzero if 2258 not. This is used in try_combine to detect early some cases where we 2259 can't perform combinations. */ 2260 2261 static int 2262 cant_combine_insn_p (rtx_insn *insn) 2263 { 2264 rtx set; 2265 rtx src, dest; 2266 2267 /* If this isn't really an insn, we can't do anything. 2268 This can occur when flow deletes an insn that it has merged into an 2269 auto-increment address. */ 2270 if (! INSN_P (insn)) 2271 return 1; 2272 2273 /* Never combine loads and stores involving hard regs that are likely 2274 to be spilled. The register allocator can usually handle such 2275 reg-reg moves by tying. If we allow the combiner to make 2276 substitutions of likely-spilled regs, reload might die. 2277 As an exception, we allow combinations involving fixed regs; these are 2278 not available to the register allocator so there's no risk involved. */ 2279 2280 set = single_set (insn); 2281 if (! set) 2282 return 0; 2283 src = SET_SRC (set); 2284 dest = SET_DEST (set); 2285 if (GET_CODE (src) == SUBREG) 2286 src = SUBREG_REG (src); 2287 if (GET_CODE (dest) == SUBREG) 2288 dest = SUBREG_REG (dest); 2289 if (REG_P (src) && REG_P (dest) 2290 && ((HARD_REGISTER_P (src) 2291 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)) 2292 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src)))) 2293 || (HARD_REGISTER_P (dest) 2294 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest)) 2295 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest)))))) 2296 return 1; 2297 2298 return 0; 2299 } 2300 2301 struct likely_spilled_retval_info 2302 { 2303 unsigned regno, nregs; 2304 unsigned mask; 2305 }; 2306 2307 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask 2308 hard registers that are known to be written to / clobbered in full. */ 2309 static void 2310 likely_spilled_retval_1 (rtx x, const_rtx set, void *data) 2311 { 2312 struct likely_spilled_retval_info *const info = 2313 (struct likely_spilled_retval_info *) data; 2314 unsigned regno, nregs; 2315 unsigned new_mask; 2316 2317 if (!REG_P (XEXP (set, 0))) 2318 return; 2319 regno = REGNO (x); 2320 if (regno >= info->regno + info->nregs) 2321 return; 2322 nregs = hard_regno_nregs[regno][GET_MODE (x)]; 2323 if (regno + nregs <= info->regno) 2324 return; 2325 new_mask = (2U << (nregs - 1)) - 1; 2326 if (regno < info->regno) 2327 new_mask >>= info->regno - regno; 2328 else 2329 new_mask <<= regno - info->regno; 2330 info->mask &= ~new_mask; 2331 } 2332 2333 /* Return nonzero iff part of the return value is live during INSN, and 2334 it is likely spilled. This can happen when more than one insn is needed 2335 to copy the return value, e.g. when we consider to combine into the 2336 second copy insn for a complex value. */ 2337 2338 static int 2339 likely_spilled_retval_p (rtx_insn *insn) 2340 { 2341 rtx_insn *use = BB_END (this_basic_block); 2342 rtx reg; 2343 rtx_insn *p; 2344 unsigned regno, nregs; 2345 /* We assume here that no machine mode needs more than 2346 32 hard registers when the value overlaps with a register 2347 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */ 2348 unsigned mask; 2349 struct likely_spilled_retval_info info; 2350 2351 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use) 2352 return 0; 2353 reg = XEXP (PATTERN (use), 0); 2354 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg))) 2355 return 0; 2356 regno = REGNO (reg); 2357 nregs = hard_regno_nregs[regno][GET_MODE (reg)]; 2358 if (nregs == 1) 2359 return 0; 2360 mask = (2U << (nregs - 1)) - 1; 2361 2362 /* Disregard parts of the return value that are set later. */ 2363 info.regno = regno; 2364 info.nregs = nregs; 2365 info.mask = mask; 2366 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p)) 2367 if (INSN_P (p)) 2368 note_stores (PATTERN (p), likely_spilled_retval_1, &info); 2369 mask = info.mask; 2370 2371 /* Check if any of the (probably) live return value registers is 2372 likely spilled. */ 2373 nregs --; 2374 do 2375 { 2376 if ((mask & 1 << nregs) 2377 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs))) 2378 return 1; 2379 } while (nregs--); 2380 return 0; 2381 } 2382 2383 /* Adjust INSN after we made a change to its destination. 2384 2385 Changing the destination can invalidate notes that say something about 2386 the results of the insn and a LOG_LINK pointing to the insn. */ 2387 2388 static void 2389 adjust_for_new_dest (rtx_insn *insn) 2390 { 2391 /* For notes, be conservative and simply remove them. */ 2392 remove_reg_equal_equiv_notes (insn); 2393 2394 /* The new insn will have a destination that was previously the destination 2395 of an insn just above it. Call distribute_links to make a LOG_LINK from 2396 the next use of that destination. */ 2397 2398 rtx set = single_set (insn); 2399 gcc_assert (set); 2400 2401 rtx reg = SET_DEST (set); 2402 2403 while (GET_CODE (reg) == ZERO_EXTRACT 2404 || GET_CODE (reg) == STRICT_LOW_PART 2405 || GET_CODE (reg) == SUBREG) 2406 reg = XEXP (reg, 0); 2407 gcc_assert (REG_P (reg)); 2408 2409 distribute_links (alloc_insn_link (insn, REGNO (reg), NULL)); 2410 2411 df_insn_rescan (insn); 2412 } 2413 2414 /* Return TRUE if combine can reuse reg X in mode MODE. 2415 ADDED_SETS is nonzero if the original set is still required. */ 2416 static bool 2417 can_change_dest_mode (rtx x, int added_sets, machine_mode mode) 2418 { 2419 unsigned int regno; 2420 2421 if (!REG_P (x)) 2422 return false; 2423 2424 regno = REGNO (x); 2425 /* Allow hard registers if the new mode is legal, and occupies no more 2426 registers than the old mode. */ 2427 if (regno < FIRST_PSEUDO_REGISTER) 2428 return (HARD_REGNO_MODE_OK (regno, mode) 2429 && (hard_regno_nregs[regno][GET_MODE (x)] 2430 >= hard_regno_nregs[regno][mode])); 2431 2432 /* Or a pseudo that is only used once. */ 2433 return (regno < reg_n_sets_max 2434 && REG_N_SETS (regno) == 1 2435 && !added_sets 2436 && !REG_USERVAR_P (x)); 2437 } 2438 2439 2440 /* Check whether X, the destination of a set, refers to part of 2441 the register specified by REG. */ 2442 2443 static bool 2444 reg_subword_p (rtx x, rtx reg) 2445 { 2446 /* Check that reg is an integer mode register. */ 2447 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) 2448 return false; 2449 2450 if (GET_CODE (x) == STRICT_LOW_PART 2451 || GET_CODE (x) == ZERO_EXTRACT) 2452 x = XEXP (x, 0); 2453 2454 return GET_CODE (x) == SUBREG 2455 && SUBREG_REG (x) == reg 2456 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT; 2457 } 2458 2459 /* Delete the unconditional jump INSN and adjust the CFG correspondingly. 2460 Note that the INSN should be deleted *after* removing dead edges, so 2461 that the kept edge is the fallthrough edge for a (set (pc) (pc)) 2462 but not for a (set (pc) (label_ref FOO)). */ 2463 2464 static void 2465 update_cfg_for_uncondjump (rtx_insn *insn) 2466 { 2467 basic_block bb = BLOCK_FOR_INSN (insn); 2468 gcc_assert (BB_END (bb) == insn); 2469 2470 purge_dead_edges (bb); 2471 2472 delete_insn (insn); 2473 if (EDGE_COUNT (bb->succs) == 1) 2474 { 2475 rtx_insn *insn; 2476 2477 single_succ_edge (bb)->flags |= EDGE_FALLTHRU; 2478 2479 /* Remove barriers from the footer if there are any. */ 2480 for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn)) 2481 if (BARRIER_P (insn)) 2482 { 2483 if (PREV_INSN (insn)) 2484 SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); 2485 else 2486 BB_FOOTER (bb) = NEXT_INSN (insn); 2487 if (NEXT_INSN (insn)) 2488 SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); 2489 } 2490 else if (LABEL_P (insn)) 2491 break; 2492 } 2493 } 2494 2495 /* Return whether PAT is a PARALLEL of exactly N register SETs followed 2496 by an arbitrary number of CLOBBERs. */ 2497 static bool 2498 is_parallel_of_n_reg_sets (rtx pat, int n) 2499 { 2500 if (GET_CODE (pat) != PARALLEL) 2501 return false; 2502 2503 int len = XVECLEN (pat, 0); 2504 if (len < n) 2505 return false; 2506 2507 int i; 2508 for (i = 0; i < n; i++) 2509 if (GET_CODE (XVECEXP (pat, 0, i)) != SET 2510 || !REG_P (SET_DEST (XVECEXP (pat, 0, i)))) 2511 return false; 2512 for ( ; i < len; i++) 2513 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 2514 return false; 2515 2516 return true; 2517 } 2518 2519 #ifndef HAVE_cc0 2520 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some 2521 CLOBBERs), can be split into individual SETs in that order, without 2522 changing semantics. */ 2523 static bool 2524 can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n) 2525 { 2526 if (!insn_nothrow_p (insn)) 2527 return false; 2528 2529 rtx pat = PATTERN (insn); 2530 2531 int i, j; 2532 for (i = 0; i < n; i++) 2533 { 2534 if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i)))) 2535 return false; 2536 2537 rtx reg = SET_DEST (XVECEXP (pat, 0, i)); 2538 2539 for (j = i + 1; j < n; j++) 2540 if (reg_referenced_p (reg, XVECEXP (pat, 0, j))) 2541 return false; 2542 } 2543 2544 return true; 2545 } 2546 #endif 2547 2548 /* Try to combine the insns I0, I1 and I2 into I3. 2549 Here I0, I1 and I2 appear earlier than I3. 2550 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into 2551 I3. 2552 2553 If we are combining more than two insns and the resulting insn is not 2554 recognized, try splitting it into two insns. If that happens, I2 and I3 2555 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE. 2556 Otherwise, I0, I1 and I2 are pseudo-deleted. 2557 2558 Return 0 if the combination does not work. Then nothing is changed. 2559 If we did the combination, return the insn at which combine should 2560 resume scanning. 2561 2562 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a 2563 new direct jump instruction. 2564 2565 LAST_COMBINED_INSN is either I3, or some insn after I3 that has 2566 been I3 passed to an earlier try_combine within the same basic 2567 block. */ 2568 2569 static rtx_insn * 2570 try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, 2571 int *new_direct_jump_p, rtx_insn *last_combined_insn) 2572 { 2573 /* New patterns for I3 and I2, respectively. */ 2574 rtx newpat, newi2pat = 0; 2575 rtvec newpat_vec_with_clobbers = 0; 2576 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0; 2577 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not 2578 dead. */ 2579 int added_sets_0, added_sets_1, added_sets_2; 2580 /* Total number of SETs to put into I3. */ 2581 int total_sets; 2582 /* Nonzero if I2's or I1's body now appears in I3. */ 2583 int i2_is_used = 0, i1_is_used = 0; 2584 /* INSN_CODEs for new I3, new I2, and user of condition code. */ 2585 int insn_code_number, i2_code_number = 0, other_code_number = 0; 2586 /* Contains I3 if the destination of I3 is used in its source, which means 2587 that the old life of I3 is being killed. If that usage is placed into 2588 I2 and not in I3, a REG_DEAD note must be made. */ 2589 rtx i3dest_killed = 0; 2590 /* SET_DEST and SET_SRC of I2, I1 and I0. */ 2591 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0; 2592 /* Copy of SET_SRC of I1 and I0, if needed. */ 2593 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0; 2594 /* Set if I2DEST was reused as a scratch register. */ 2595 bool i2scratch = false; 2596 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */ 2597 rtx i0pat = 0, i1pat = 0, i2pat = 0; 2598 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ 2599 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; 2600 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0; 2601 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0; 2602 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0; 2603 /* Notes that must be added to REG_NOTES in I3 and I2. */ 2604 rtx new_i3_notes, new_i2_notes; 2605 /* Notes that we substituted I3 into I2 instead of the normal case. */ 2606 int i3_subst_into_i2 = 0; 2607 /* Notes that I1, I2 or I3 is a MULT operation. */ 2608 int have_mult = 0; 2609 int swap_i2i3 = 0; 2610 int changed_i3_dest = 0; 2611 2612 int maxreg; 2613 rtx_insn *temp_insn; 2614 rtx temp_expr; 2615 struct insn_link *link; 2616 rtx other_pat = 0; 2617 rtx new_other_notes; 2618 int i; 2619 2620 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can 2621 never be). */ 2622 if (i1 == i2 || i0 == i2 || (i0 && i0 == i1)) 2623 return 0; 2624 2625 /* Only try four-insn combinations when there's high likelihood of 2626 success. Look for simple insns, such as loads of constants or 2627 binary operations involving a constant. */ 2628 if (i0) 2629 { 2630 int i; 2631 int ngood = 0; 2632 int nshift = 0; 2633 rtx set0, set3; 2634 2635 if (!flag_expensive_optimizations) 2636 return 0; 2637 2638 for (i = 0; i < 4; i++) 2639 { 2640 rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3; 2641 rtx set = single_set (insn); 2642 rtx src; 2643 if (!set) 2644 continue; 2645 src = SET_SRC (set); 2646 if (CONSTANT_P (src)) 2647 { 2648 ngood += 2; 2649 break; 2650 } 2651 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1))) 2652 ngood++; 2653 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT 2654 || GET_CODE (src) == LSHIFTRT) 2655 nshift++; 2656 } 2657 2658 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2 2659 are likely manipulating its value. Ideally we'll be able to combine 2660 all four insns into a bitfield insertion of some kind. 2661 2662 Note the source in I0 might be inside a sign/zero extension and the 2663 memory modes in I0 and I3 might be different. So extract the address 2664 from the destination of I3 and search for it in the source of I0. 2665 2666 In the event that there's a match but the source/dest do not actually 2667 refer to the same memory, the worst that happens is we try some 2668 combinations that we wouldn't have otherwise. */ 2669 if ((set0 = single_set (i0)) 2670 /* Ensure the source of SET0 is a MEM, possibly buried inside 2671 an extension. */ 2672 && (GET_CODE (SET_SRC (set0)) == MEM 2673 || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND 2674 || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND) 2675 && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM)) 2676 && (set3 = single_set (i3)) 2677 /* Ensure the destination of SET3 is a MEM. */ 2678 && GET_CODE (SET_DEST (set3)) == MEM 2679 /* Would it be better to extract the base address for the MEM 2680 in SET3 and look for that? I don't have cases where it matters 2681 but I could envision such cases. */ 2682 && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0))) 2683 ngood += 2; 2684 2685 if (ngood < 2 && nshift < 2) 2686 return 0; 2687 } 2688 2689 /* Exit early if one of the insns involved can't be used for 2690 combinations. */ 2691 if (CALL_P (i2) 2692 || (i1 && CALL_P (i1)) 2693 || (i0 && CALL_P (i0)) 2694 || cant_combine_insn_p (i3) 2695 || cant_combine_insn_p (i2) 2696 || (i1 && cant_combine_insn_p (i1)) 2697 || (i0 && cant_combine_insn_p (i0)) 2698 || likely_spilled_retval_p (i3)) 2699 return 0; 2700 2701 combine_attempts++; 2702 undobuf.other_insn = 0; 2703 2704 /* Reset the hard register usage information. */ 2705 CLEAR_HARD_REG_SET (newpat_used_regs); 2706 2707 if (dump_file && (dump_flags & TDF_DETAILS)) 2708 { 2709 if (i0) 2710 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n", 2711 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); 2712 else if (i1) 2713 fprintf (dump_file, "\nTrying %d, %d -> %d:\n", 2714 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); 2715 else 2716 fprintf (dump_file, "\nTrying %d -> %d:\n", 2717 INSN_UID (i2), INSN_UID (i3)); 2718 } 2719 2720 /* If multiple insns feed into one of I2 or I3, they can be in any 2721 order. To simplify the code below, reorder them in sequence. */ 2722 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2)) 2723 temp_insn = i2, i2 = i0, i0 = temp_insn; 2724 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1)) 2725 temp_insn = i1, i1 = i0, i0 = temp_insn; 2726 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2)) 2727 temp_insn = i1, i1 = i2, i2 = temp_insn; 2728 2729 added_links_insn = 0; 2730 2731 /* First check for one important special case that the code below will 2732 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL 2733 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, 2734 we may be able to replace that destination with the destination of I3. 2735 This occurs in the common code where we compute both a quotient and 2736 remainder into a structure, in which case we want to do the computation 2737 directly into the structure to avoid register-register copies. 2738 2739 Note that this case handles both multiple sets in I2 and also cases 2740 where I2 has a number of CLOBBERs inside the PARALLEL. 2741 2742 We make very conservative checks below and only try to handle the 2743 most common cases of this. For example, we only handle the case 2744 where I2 and I3 are adjacent to avoid making difficult register 2745 usage tests. */ 2746 2747 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET 2748 && REG_P (SET_SRC (PATTERN (i3))) 2749 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 2750 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) 2751 && GET_CODE (PATTERN (i2)) == PARALLEL 2752 && ! side_effects_p (SET_DEST (PATTERN (i3))) 2753 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code 2754 below would need to check what is inside (and reg_overlap_mentioned_p 2755 doesn't support those codes anyway). Don't allow those destinations; 2756 the resulting insn isn't likely to be recognized anyway. */ 2757 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT 2758 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART 2759 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), 2760 SET_DEST (PATTERN (i3))) 2761 && next_active_insn (i2) == i3) 2762 { 2763 rtx p2 = PATTERN (i2); 2764 2765 /* Make sure that the destination of I3, 2766 which we are going to substitute into one output of I2, 2767 is not used within another output of I2. We must avoid making this: 2768 (parallel [(set (mem (reg 69)) ...) 2769 (set (reg 69) ...)]) 2770 which is not well-defined as to order of actions. 2771 (Besides, reload can't handle output reloads for this.) 2772 2773 The problem can also happen if the dest of I3 is a memory ref, 2774 if another dest in I2 is an indirect memory ref. */ 2775 for (i = 0; i < XVECLEN (p2, 0); i++) 2776 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 2777 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 2778 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), 2779 SET_DEST (XVECEXP (p2, 0, i)))) 2780 break; 2781 2782 /* Make sure this PARALLEL is not an asm. We do not allow combining 2783 that usually (see can_combine_p), so do not here either. */ 2784 for (i = 0; i < XVECLEN (p2, 0); i++) 2785 if (GET_CODE (XVECEXP (p2, 0, i)) == SET 2786 && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS) 2787 break; 2788 2789 if (i == XVECLEN (p2, 0)) 2790 for (i = 0; i < XVECLEN (p2, 0); i++) 2791 if (GET_CODE (XVECEXP (p2, 0, i)) == SET 2792 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) 2793 { 2794 combine_merges++; 2795 2796 subst_insn = i3; 2797 subst_low_luid = DF_INSN_LUID (i2); 2798 2799 added_sets_2 = added_sets_1 = added_sets_0 = 0; 2800 i2src = SET_SRC (XVECEXP (p2, 0, i)); 2801 i2dest = SET_DEST (XVECEXP (p2, 0, i)); 2802 i2dest_killed = dead_or_set_p (i2, i2dest); 2803 2804 /* Replace the dest in I2 with our dest and make the resulting 2805 insn the new pattern for I3. Then skip to where we validate 2806 the pattern. Everything was set up above. */ 2807 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3))); 2808 newpat = p2; 2809 i3_subst_into_i2 = 1; 2810 goto validate_replacement; 2811 } 2812 } 2813 2814 /* If I2 is setting a pseudo to a constant and I3 is setting some 2815 sub-part of it to another constant, merge them by making a new 2816 constant. */ 2817 if (i1 == 0 2818 && (temp_expr = single_set (i2)) != 0 2819 && CONST_SCALAR_INT_P (SET_SRC (temp_expr)) 2820 && GET_CODE (PATTERN (i3)) == SET 2821 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3))) 2822 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr))) 2823 { 2824 rtx dest = SET_DEST (PATTERN (i3)); 2825 int offset = -1; 2826 int width = 0; 2827 2828 if (GET_CODE (dest) == ZERO_EXTRACT) 2829 { 2830 if (CONST_INT_P (XEXP (dest, 1)) 2831 && CONST_INT_P (XEXP (dest, 2))) 2832 { 2833 width = INTVAL (XEXP (dest, 1)); 2834 offset = INTVAL (XEXP (dest, 2)); 2835 dest = XEXP (dest, 0); 2836 if (BITS_BIG_ENDIAN) 2837 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset; 2838 } 2839 } 2840 else 2841 { 2842 if (GET_CODE (dest) == STRICT_LOW_PART) 2843 dest = XEXP (dest, 0); 2844 width = GET_MODE_PRECISION (GET_MODE (dest)); 2845 offset = 0; 2846 } 2847 2848 if (offset >= 0) 2849 { 2850 /* If this is the low part, we're done. */ 2851 if (subreg_lowpart_p (dest)) 2852 ; 2853 /* Handle the case where inner is twice the size of outer. */ 2854 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr))) 2855 == 2 * GET_MODE_PRECISION (GET_MODE (dest))) 2856 offset += GET_MODE_PRECISION (GET_MODE (dest)); 2857 /* Otherwise give up for now. */ 2858 else 2859 offset = -1; 2860 } 2861 2862 if (offset >= 0) 2863 { 2864 rtx inner = SET_SRC (PATTERN (i3)); 2865 rtx outer = SET_SRC (temp_expr); 2866 2867 wide_int o 2868 = wi::insert (std::make_pair (outer, GET_MODE (SET_DEST (temp_expr))), 2869 std::make_pair (inner, GET_MODE (dest)), 2870 offset, width); 2871 2872 combine_merges++; 2873 subst_insn = i3; 2874 subst_low_luid = DF_INSN_LUID (i2); 2875 added_sets_2 = added_sets_1 = added_sets_0 = 0; 2876 i2dest = SET_DEST (temp_expr); 2877 i2dest_killed = dead_or_set_p (i2, i2dest); 2878 2879 /* Replace the source in I2 with the new constant and make the 2880 resulting insn the new pattern for I3. Then skip to where we 2881 validate the pattern. Everything was set up above. */ 2882 SUBST (SET_SRC (temp_expr), 2883 immed_wide_int_const (o, GET_MODE (SET_DEST (temp_expr)))); 2884 2885 newpat = PATTERN (i2); 2886 2887 /* The dest of I3 has been replaced with the dest of I2. */ 2888 changed_i3_dest = 1; 2889 goto validate_replacement; 2890 } 2891 } 2892 2893 #ifndef HAVE_cc0 2894 /* If we have no I1 and I2 looks like: 2895 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) 2896 (set Y OP)]) 2897 make up a dummy I1 that is 2898 (set Y OP) 2899 and change I2 to be 2900 (set (reg:CC X) (compare:CC Y (const_int 0))) 2901 2902 (We can ignore any trailing CLOBBERs.) 2903 2904 This undoes a previous combination and allows us to match a branch-and- 2905 decrement insn. */ 2906 2907 if (i1 == 0 2908 && is_parallel_of_n_reg_sets (PATTERN (i2), 2) 2909 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) 2910 == MODE_CC) 2911 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE 2912 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx 2913 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), 2914 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))) 2915 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3) 2916 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)) 2917 { 2918 /* We make I1 with the same INSN_UID as I2. This gives it 2919 the same DF_INSN_LUID for value tracking. Our fake I1 will 2920 never appear in the insn stream so giving it the same INSN_UID 2921 as I2 will not cause a problem. */ 2922 2923 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2), 2924 XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2), 2925 -1, NULL_RTX); 2926 INSN_UID (i1) = INSN_UID (i2); 2927 2928 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); 2929 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), 2930 SET_DEST (PATTERN (i1))); 2931 unsigned int regno = REGNO (SET_DEST (PATTERN (i1))); 2932 SUBST_LINK (LOG_LINKS (i2), 2933 alloc_insn_link (i1, regno, LOG_LINKS (i2))); 2934 } 2935 2936 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs), 2937 make those two SETs separate I1 and I2 insns, and make an I0 that is 2938 the original I1. */ 2939 if (i0 == 0 2940 && is_parallel_of_n_reg_sets (PATTERN (i2), 2) 2941 && can_split_parallel_of_n_reg_sets (i2, 2) 2942 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3) 2943 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)) 2944 { 2945 /* If there is no I1, there is no I0 either. */ 2946 i0 = i1; 2947 2948 /* We make I1 with the same INSN_UID as I2. This gives it 2949 the same DF_INSN_LUID for value tracking. Our fake I1 will 2950 never appear in the insn stream so giving it the same INSN_UID 2951 as I2 will not cause a problem. */ 2952 2953 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2), 2954 XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2), 2955 -1, NULL_RTX); 2956 INSN_UID (i1) = INSN_UID (i2); 2957 2958 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1)); 2959 } 2960 #endif 2961 2962 /* Verify that I2 and I1 are valid for combining. */ 2963 if (! can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src) 2964 || (i1 && ! can_combine_p (i1, i3, i0, NULL, i2, NULL, 2965 &i1dest, &i1src)) 2966 || (i0 && ! can_combine_p (i0, i3, NULL, NULL, i1, i2, 2967 &i0dest, &i0src))) 2968 { 2969 undo_all (); 2970 return 0; 2971 } 2972 2973 /* Record whether I2DEST is used in I2SRC and similarly for the other 2974 cases. Knowing this will help in register status updating below. */ 2975 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); 2976 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); 2977 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); 2978 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src); 2979 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src); 2980 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src); 2981 i2dest_killed = dead_or_set_p (i2, i2dest); 2982 i1dest_killed = i1 && dead_or_set_p (i1, i1dest); 2983 i0dest_killed = i0 && dead_or_set_p (i0, i0dest); 2984 2985 /* For the earlier insns, determine which of the subsequent ones they 2986 feed. */ 2987 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2); 2988 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1); 2989 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2) 2990 : (!reg_overlap_mentioned_p (i1dest, i0dest) 2991 && reg_overlap_mentioned_p (i0dest, i2src)))); 2992 2993 /* Ensure that I3's pattern can be the destination of combines. */ 2994 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest, 2995 i1 && i2dest_in_i1src && !i1_feeds_i2_n, 2996 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n) 2997 || (i1dest_in_i0src && !i0_feeds_i1_n)), 2998 &i3dest_killed)) 2999 { 3000 undo_all (); 3001 return 0; 3002 } 3003 3004 /* See if any of the insns is a MULT operation. Unless one is, we will 3005 reject a combination that is, since it must be slower. Be conservative 3006 here. */ 3007 if (GET_CODE (i2src) == MULT 3008 || (i1 != 0 && GET_CODE (i1src) == MULT) 3009 || (i0 != 0 && GET_CODE (i0src) == MULT) 3010 || (GET_CODE (PATTERN (i3)) == SET 3011 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) 3012 have_mult = 1; 3013 3014 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. 3015 We used to do this EXCEPT in one case: I3 has a post-inc in an 3016 output operand. However, that exception can give rise to insns like 3017 mov r3,(r3)+ 3018 which is a famous insn on the PDP-11 where the value of r3 used as the 3019 source was model-dependent. Avoid this sort of thing. */ 3020 3021 #if 0 3022 if (!(GET_CODE (PATTERN (i3)) == SET 3023 && REG_P (SET_SRC (PATTERN (i3))) 3024 && MEM_P (SET_DEST (PATTERN (i3))) 3025 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC 3026 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) 3027 /* It's not the exception. */ 3028 #endif 3029 #ifdef AUTO_INC_DEC 3030 { 3031 rtx link; 3032 for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) 3033 if (REG_NOTE_KIND (link) == REG_INC 3034 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) 3035 || (i1 != 0 3036 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) 3037 { 3038 undo_all (); 3039 return 0; 3040 } 3041 } 3042 #endif 3043 3044 /* See if the SETs in I1 or I2 need to be kept around in the merged 3045 instruction: whenever the value set there is still needed past I3. 3046 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3. 3047 3048 For the SET in I1, we have two cases: if I1 and I2 independently feed 3049 into I3, the set in I1 needs to be kept around unless I1DEST dies 3050 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set 3051 in I1 needs to be kept around unless I1DEST dies or is set in either 3052 I2 or I3. The same considerations apply to I0. */ 3053 3054 added_sets_2 = !dead_or_set_p (i3, i2dest); 3055 3056 if (i1) 3057 added_sets_1 = !(dead_or_set_p (i3, i1dest) 3058 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest))); 3059 else 3060 added_sets_1 = 0; 3061 3062 if (i0) 3063 added_sets_0 = !(dead_or_set_p (i3, i0dest) 3064 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)) 3065 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) 3066 && dead_or_set_p (i2, i0dest))); 3067 else 3068 added_sets_0 = 0; 3069 3070 /* We are about to copy insns for the case where they need to be kept 3071 around. Check that they can be copied in the merged instruction. */ 3072 3073 if (targetm.cannot_copy_insn_p 3074 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2)) 3075 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1)) 3076 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0)))) 3077 { 3078 undo_all (); 3079 return 0; 3080 } 3081 3082 /* If the set in I2 needs to be kept around, we must make a copy of 3083 PATTERN (I2), so that when we substitute I1SRC for I1DEST in 3084 PATTERN (I2), we are only substituting for the original I1DEST, not into 3085 an already-substituted copy. This also prevents making self-referential 3086 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to 3087 I2DEST. */ 3088 3089 if (added_sets_2) 3090 { 3091 if (GET_CODE (PATTERN (i2)) == PARALLEL) 3092 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src)); 3093 else 3094 i2pat = copy_rtx (PATTERN (i2)); 3095 } 3096 3097 if (added_sets_1) 3098 { 3099 if (GET_CODE (PATTERN (i1)) == PARALLEL) 3100 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src)); 3101 else 3102 i1pat = copy_rtx (PATTERN (i1)); 3103 } 3104 3105 if (added_sets_0) 3106 { 3107 if (GET_CODE (PATTERN (i0)) == PARALLEL) 3108 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src)); 3109 else 3110 i0pat = copy_rtx (PATTERN (i0)); 3111 } 3112 3113 combine_merges++; 3114 3115 /* Substitute in the latest insn for the regs set by the earlier ones. */ 3116 3117 maxreg = max_reg_num (); 3118 3119 subst_insn = i3; 3120 3121 #ifndef HAVE_cc0 3122 /* Many machines that don't use CC0 have insns that can both perform an 3123 arithmetic operation and set the condition code. These operations will 3124 be represented as a PARALLEL with the first element of the vector 3125 being a COMPARE of an arithmetic operation with the constant zero. 3126 The second element of the vector will set some pseudo to the result 3127 of the same arithmetic operation. If we simplify the COMPARE, we won't 3128 match such a pattern and so will generate an extra insn. Here we test 3129 for this case, where both the comparison and the operation result are 3130 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with 3131 I2SRC. Later we will make the PARALLEL that contains I2. */ 3132 3133 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET 3134 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE 3135 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1)) 3136 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) 3137 { 3138 rtx newpat_dest; 3139 rtx *cc_use_loc = NULL; 3140 rtx_insn *cc_use_insn = NULL; 3141 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1); 3142 machine_mode compare_mode, orig_compare_mode; 3143 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN; 3144 3145 newpat = PATTERN (i3); 3146 newpat_dest = SET_DEST (newpat); 3147 compare_mode = orig_compare_mode = GET_MODE (newpat_dest); 3148 3149 if (undobuf.other_insn == 0 3150 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3, 3151 &cc_use_insn))) 3152 { 3153 compare_code = orig_compare_code = GET_CODE (*cc_use_loc); 3154 compare_code = simplify_compare_const (compare_code, 3155 GET_MODE (i2dest), op0, &op1); 3156 target_canonicalize_comparison (&compare_code, &op0, &op1, 1); 3157 } 3158 3159 /* Do the rest only if op1 is const0_rtx, which may be the 3160 result of simplification. */ 3161 if (op1 == const0_rtx) 3162 { 3163 /* If a single use of the CC is found, prepare to modify it 3164 when SELECT_CC_MODE returns a new CC-class mode, or when 3165 the above simplify_compare_const() returned a new comparison 3166 operator. undobuf.other_insn is assigned the CC use insn 3167 when modifying it. */ 3168 if (cc_use_loc) 3169 { 3170 #ifdef SELECT_CC_MODE 3171 machine_mode new_mode 3172 = SELECT_CC_MODE (compare_code, op0, op1); 3173 if (new_mode != orig_compare_mode 3174 && can_change_dest_mode (SET_DEST (newpat), 3175 added_sets_2, new_mode)) 3176 { 3177 unsigned int regno = REGNO (newpat_dest); 3178 compare_mode = new_mode; 3179 if (regno < FIRST_PSEUDO_REGISTER) 3180 newpat_dest = gen_rtx_REG (compare_mode, regno); 3181 else 3182 { 3183 SUBST_MODE (regno_reg_rtx[regno], compare_mode); 3184 newpat_dest = regno_reg_rtx[regno]; 3185 } 3186 } 3187 #endif 3188 /* Cases for modifying the CC-using comparison. */ 3189 if (compare_code != orig_compare_code 3190 /* ??? Do we need to verify the zero rtx? */ 3191 && XEXP (*cc_use_loc, 1) == const0_rtx) 3192 { 3193 /* Replace cc_use_loc with entire new RTX. */ 3194 SUBST (*cc_use_loc, 3195 gen_rtx_fmt_ee (compare_code, compare_mode, 3196 newpat_dest, const0_rtx)); 3197 undobuf.other_insn = cc_use_insn; 3198 } 3199 else if (compare_mode != orig_compare_mode) 3200 { 3201 /* Just replace the CC reg with a new mode. */ 3202 SUBST (XEXP (*cc_use_loc, 0), newpat_dest); 3203 undobuf.other_insn = cc_use_insn; 3204 } 3205 } 3206 3207 /* Now we modify the current newpat: 3208 First, SET_DEST(newpat) is updated if the CC mode has been 3209 altered. For targets without SELECT_CC_MODE, this should be 3210 optimized away. */ 3211 if (compare_mode != orig_compare_mode) 3212 SUBST (SET_DEST (newpat), newpat_dest); 3213 /* This is always done to propagate i2src into newpat. */ 3214 SUBST (SET_SRC (newpat), 3215 gen_rtx_COMPARE (compare_mode, op0, op1)); 3216 /* Create new version of i2pat if needed; the below PARALLEL 3217 creation needs this to work correctly. */ 3218 if (! rtx_equal_p (i2src, op0)) 3219 i2pat = gen_rtx_SET (VOIDmode, i2dest, op0); 3220 i2_is_used = 1; 3221 } 3222 } 3223 #endif 3224 3225 if (i2_is_used == 0) 3226 { 3227 /* It is possible that the source of I2 or I1 may be performing 3228 an unneeded operation, such as a ZERO_EXTEND of something 3229 that is known to have the high part zero. Handle that case 3230 by letting subst look at the inner insns. 3231 3232 Another way to do this would be to have a function that tries 3233 to simplify a single insn instead of merging two or more 3234 insns. We don't do this because of the potential of infinite 3235 loops and because of the potential extra memory required. 3236 However, doing it the way we are is a bit of a kludge and 3237 doesn't catch all cases. 3238 3239 But only do this if -fexpensive-optimizations since it slows 3240 things down and doesn't usually win. 3241 3242 This is not done in the COMPARE case above because the 3243 unmodified I2PAT is used in the PARALLEL and so a pattern 3244 with a modified I2SRC would not match. */ 3245 3246 if (flag_expensive_optimizations) 3247 { 3248 /* Pass pc_rtx so no substitutions are done, just 3249 simplifications. */ 3250 if (i1) 3251 { 3252 subst_low_luid = DF_INSN_LUID (i1); 3253 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0); 3254 } 3255 3256 subst_low_luid = DF_INSN_LUID (i2); 3257 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); 3258 } 3259 3260 n_occurrences = 0; /* `subst' counts here */ 3261 subst_low_luid = DF_INSN_LUID (i2); 3262 3263 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique 3264 copy of I2SRC each time we substitute it, in order to avoid creating 3265 self-referential RTL when we will be substituting I1SRC for I1DEST 3266 later. Likewise if I0 feeds into I2, either directly or indirectly 3267 through I1, and I0DEST is in I0SRC. */ 3268 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0, 3269 (i1_feeds_i2_n && i1dest_in_i1src) 3270 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) 3271 && i0dest_in_i0src)); 3272 substed_i2 = 1; 3273 3274 /* Record whether I2's body now appears within I3's body. */ 3275 i2_is_used = n_occurrences; 3276 } 3277 3278 /* If we already got a failure, don't try to do more. Otherwise, try to 3279 substitute I1 if we have it. */ 3280 3281 if (i1 && GET_CODE (newpat) != CLOBBER) 3282 { 3283 /* Check that an autoincrement side-effect on I1 has not been lost. 3284 This happens if I1DEST is mentioned in I2 and dies there, and 3285 has disappeared from the new pattern. */ 3286 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 3287 && i1_feeds_i2_n 3288 && dead_or_set_p (i2, i1dest) 3289 && !reg_overlap_mentioned_p (i1dest, newpat)) 3290 /* Before we can do this substitution, we must redo the test done 3291 above (see detailed comments there) that ensures I1DEST isn't 3292 mentioned in any SETs in NEWPAT that are field assignments. */ 3293 || !combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX, 3294 0, 0, 0)) 3295 { 3296 undo_all (); 3297 return 0; 3298 } 3299 3300 n_occurrences = 0; 3301 subst_low_luid = DF_INSN_LUID (i1); 3302 3303 /* If the following substitution will modify I1SRC, make a copy of it 3304 for the case where it is substituted for I1DEST in I2PAT later. */ 3305 if (added_sets_2 && i1_feeds_i2_n) 3306 i1src_copy = copy_rtx (i1src); 3307 3308 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique 3309 copy of I1SRC each time we substitute it, in order to avoid creating 3310 self-referential RTL when we will be substituting I0SRC for I0DEST 3311 later. */ 3312 newpat = subst (newpat, i1dest, i1src, 0, 0, 3313 i0_feeds_i1_n && i0dest_in_i0src); 3314 substed_i1 = 1; 3315 3316 /* Record whether I1's body now appears within I3's body. */ 3317 i1_is_used = n_occurrences; 3318 } 3319 3320 /* Likewise for I0 if we have it. */ 3321 3322 if (i0 && GET_CODE (newpat) != CLOBBER) 3323 { 3324 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0 3325 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest)) 3326 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))) 3327 && !reg_overlap_mentioned_p (i0dest, newpat)) 3328 || !combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX, 3329 0, 0, 0)) 3330 { 3331 undo_all (); 3332 return 0; 3333 } 3334 3335 /* If the following substitution will modify I0SRC, make a copy of it 3336 for the case where it is substituted for I0DEST in I1PAT later. */ 3337 if (added_sets_1 && i0_feeds_i1_n) 3338 i0src_copy = copy_rtx (i0src); 3339 /* And a copy for I0DEST in I2PAT substitution. */ 3340 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n) 3341 || (i0_feeds_i2_n))) 3342 i0src_copy2 = copy_rtx (i0src); 3343 3344 n_occurrences = 0; 3345 subst_low_luid = DF_INSN_LUID (i0); 3346 newpat = subst (newpat, i0dest, i0src, 0, 0, 0); 3347 substed_i0 = 1; 3348 } 3349 3350 /* Fail if an autoincrement side-effect has been duplicated. Be careful 3351 to count all the ways that I2SRC and I1SRC can be used. */ 3352 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 3353 && i2_is_used + added_sets_2 > 1) 3354 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 3355 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) 3356 > 1)) 3357 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0 3358 && (n_occurrences + added_sets_0 3359 + (added_sets_1 && i0_feeds_i1_n) 3360 + (added_sets_2 && i0_feeds_i2_n) 3361 > 1)) 3362 /* Fail if we tried to make a new register. */ 3363 || max_reg_num () != maxreg 3364 /* Fail if we couldn't do something and have a CLOBBER. */ 3365 || GET_CODE (newpat) == CLOBBER 3366 /* Fail if this new pattern is a MULT and we didn't have one before 3367 at the outer level. */ 3368 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT 3369 && ! have_mult)) 3370 { 3371 undo_all (); 3372 return 0; 3373 } 3374 3375 /* If the actions of the earlier insns must be kept 3376 in addition to substituting them into the latest one, 3377 we must make a new PARALLEL for the latest insn 3378 to hold additional the SETs. */ 3379 3380 if (added_sets_0 || added_sets_1 || added_sets_2) 3381 { 3382 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2; 3383 combine_extras++; 3384 3385 if (GET_CODE (newpat) == PARALLEL) 3386 { 3387 rtvec old = XVEC (newpat, 0); 3388 total_sets = XVECLEN (newpat, 0) + extra_sets; 3389 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 3390 memcpy (XVEC (newpat, 0)->elem, &old->elem[0], 3391 sizeof (old->elem[0]) * old->num_elem); 3392 } 3393 else 3394 { 3395 rtx old = newpat; 3396 total_sets = 1 + extra_sets; 3397 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 3398 XVECEXP (newpat, 0, 0) = old; 3399 } 3400 3401 if (added_sets_0) 3402 XVECEXP (newpat, 0, --total_sets) = i0pat; 3403 3404 if (added_sets_1) 3405 { 3406 rtx t = i1pat; 3407 if (i0_feeds_i1_n) 3408 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0); 3409 3410 XVECEXP (newpat, 0, --total_sets) = t; 3411 } 3412 if (added_sets_2) 3413 { 3414 rtx t = i2pat; 3415 if (i1_feeds_i2_n) 3416 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0, 3417 i0_feeds_i1_n && i0dest_in_i0src); 3418 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n) 3419 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0); 3420 3421 XVECEXP (newpat, 0, --total_sets) = t; 3422 } 3423 } 3424 3425 validate_replacement: 3426 3427 /* Note which hard regs this insn has as inputs. */ 3428 mark_used_regs_combine (newpat); 3429 3430 /* If recog_for_combine fails, it strips existing clobbers. If we'll 3431 consider splitting this pattern, we might need these clobbers. */ 3432 if (i1 && GET_CODE (newpat) == PARALLEL 3433 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER) 3434 { 3435 int len = XVECLEN (newpat, 0); 3436 3437 newpat_vec_with_clobbers = rtvec_alloc (len); 3438 for (i = 0; i < len; i++) 3439 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i); 3440 } 3441 3442 /* We have recognized nothing yet. */ 3443 insn_code_number = -1; 3444 3445 /* See if this is a PARALLEL of two SETs where one SET's destination is 3446 a register that is unused and this isn't marked as an instruction that 3447 might trap in an EH region. In that case, we just need the other SET. 3448 We prefer this over the PARALLEL. 3449 3450 This can occur when simplifying a divmod insn. We *must* test for this 3451 case here because the code below that splits two independent SETs doesn't 3452 handle this case correctly when it updates the register status. 3453 3454 It's pointless doing this if we originally had two sets, one from 3455 i3, and one from i2. Combining then splitting the parallel results 3456 in the original i2 again plus an invalid insn (which we delete). 3457 The net effect is only to move instructions around, which makes 3458 debug info less accurate. */ 3459 3460 if (!(added_sets_2 && i1 == 0) 3461 && is_parallel_of_n_reg_sets (newpat, 2) 3462 && asm_noperands (newpat) < 0) 3463 { 3464 rtx set0 = XVECEXP (newpat, 0, 0); 3465 rtx set1 = XVECEXP (newpat, 0, 1); 3466 rtx oldpat = newpat; 3467 3468 if (((REG_P (SET_DEST (set1)) 3469 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1))) 3470 || (GET_CODE (SET_DEST (set1)) == SUBREG 3471 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1))))) 3472 && insn_nothrow_p (i3) 3473 && !side_effects_p (SET_SRC (set1))) 3474 { 3475 newpat = set0; 3476 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3477 } 3478 3479 else if (((REG_P (SET_DEST (set0)) 3480 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0))) 3481 || (GET_CODE (SET_DEST (set0)) == SUBREG 3482 && find_reg_note (i3, REG_UNUSED, 3483 SUBREG_REG (SET_DEST (set0))))) 3484 && insn_nothrow_p (i3) 3485 && !side_effects_p (SET_SRC (set0))) 3486 { 3487 newpat = set1; 3488 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3489 3490 if (insn_code_number >= 0) 3491 changed_i3_dest = 1; 3492 } 3493 3494 if (insn_code_number < 0) 3495 newpat = oldpat; 3496 } 3497 3498 /* Is the result of combination a valid instruction? */ 3499 if (insn_code_number < 0) 3500 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3501 3502 /* If we were combining three insns and the result is a simple SET 3503 with no ASM_OPERANDS that wasn't recognized, try to split it into two 3504 insns. There are two ways to do this. It can be split using a 3505 machine-specific method (like when you have an addition of a large 3506 constant) or by combine in the function find_split_point. */ 3507 3508 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET 3509 && asm_noperands (newpat) < 0) 3510 { 3511 rtx parallel, *split; 3512 rtx_insn *m_split_insn; 3513 3514 /* See if the MD file can split NEWPAT. If it can't, see if letting it 3515 use I2DEST as a scratch register will help. In the latter case, 3516 convert I2DEST to the mode of the source of NEWPAT if we can. */ 3517 3518 m_split_insn = combine_split_insns (newpat, i3); 3519 3520 /* We can only use I2DEST as a scratch reg if it doesn't overlap any 3521 inputs of NEWPAT. */ 3522 3523 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be 3524 possible to try that as a scratch reg. This would require adding 3525 more code to make it work though. */ 3526 3527 if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat)) 3528 { 3529 machine_mode new_mode = GET_MODE (SET_DEST (newpat)); 3530 3531 /* First try to split using the original register as a 3532 scratch register. */ 3533 parallel = gen_rtx_PARALLEL (VOIDmode, 3534 gen_rtvec (2, newpat, 3535 gen_rtx_CLOBBER (VOIDmode, 3536 i2dest))); 3537 m_split_insn = combine_split_insns (parallel, i3); 3538 3539 /* If that didn't work, try changing the mode of I2DEST if 3540 we can. */ 3541 if (m_split_insn == 0 3542 && new_mode != GET_MODE (i2dest) 3543 && new_mode != VOIDmode 3544 && can_change_dest_mode (i2dest, added_sets_2, new_mode)) 3545 { 3546 machine_mode old_mode = GET_MODE (i2dest); 3547 rtx ni2dest; 3548 3549 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) 3550 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest)); 3551 else 3552 { 3553 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode); 3554 ni2dest = regno_reg_rtx[REGNO (i2dest)]; 3555 } 3556 3557 parallel = (gen_rtx_PARALLEL 3558 (VOIDmode, 3559 gen_rtvec (2, newpat, 3560 gen_rtx_CLOBBER (VOIDmode, 3561 ni2dest)))); 3562 m_split_insn = combine_split_insns (parallel, i3); 3563 3564 if (m_split_insn == 0 3565 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 3566 { 3567 struct undo *buf; 3568 3569 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode); 3570 buf = undobuf.undos; 3571 undobuf.undos = buf->next; 3572 buf->next = undobuf.frees; 3573 undobuf.frees = buf; 3574 } 3575 } 3576 3577 i2scratch = m_split_insn != 0; 3578 } 3579 3580 /* If recog_for_combine has discarded clobbers, try to use them 3581 again for the split. */ 3582 if (m_split_insn == 0 && newpat_vec_with_clobbers) 3583 { 3584 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers); 3585 m_split_insn = combine_split_insns (parallel, i3); 3586 } 3587 3588 if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX) 3589 { 3590 rtx m_split_pat = PATTERN (m_split_insn); 3591 insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes); 3592 if (insn_code_number >= 0) 3593 newpat = m_split_pat; 3594 } 3595 else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX 3596 && (next_nonnote_nondebug_insn (i2) == i3 3597 || ! use_crosses_set_p (PATTERN (m_split_insn), DF_INSN_LUID (i2)))) 3598 { 3599 rtx i2set, i3set; 3600 rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn)); 3601 newi2pat = PATTERN (m_split_insn); 3602 3603 i3set = single_set (NEXT_INSN (m_split_insn)); 3604 i2set = single_set (m_split_insn); 3605 3606 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3607 3608 /* If I2 or I3 has multiple SETs, we won't know how to track 3609 register status, so don't use these insns. If I2's destination 3610 is used between I2 and I3, we also can't use these insns. */ 3611 3612 if (i2_code_number >= 0 && i2set && i3set 3613 && (next_nonnote_nondebug_insn (i2) == i3 3614 || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) 3615 insn_code_number = recog_for_combine (&newi3pat, i3, 3616 &new_i3_notes); 3617 if (insn_code_number >= 0) 3618 newpat = newi3pat; 3619 3620 /* It is possible that both insns now set the destination of I3. 3621 If so, we must show an extra use of it. */ 3622 3623 if (insn_code_number >= 0) 3624 { 3625 rtx new_i3_dest = SET_DEST (i3set); 3626 rtx new_i2_dest = SET_DEST (i2set); 3627 3628 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT 3629 || GET_CODE (new_i3_dest) == STRICT_LOW_PART 3630 || GET_CODE (new_i3_dest) == SUBREG) 3631 new_i3_dest = XEXP (new_i3_dest, 0); 3632 3633 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT 3634 || GET_CODE (new_i2_dest) == STRICT_LOW_PART 3635 || GET_CODE (new_i2_dest) == SUBREG) 3636 new_i2_dest = XEXP (new_i2_dest, 0); 3637 3638 if (REG_P (new_i3_dest) 3639 && REG_P (new_i2_dest) 3640 && REGNO (new_i3_dest) == REGNO (new_i2_dest) 3641 && REGNO (new_i2_dest) < reg_n_sets_max) 3642 INC_REG_N_SETS (REGNO (new_i2_dest), 1); 3643 } 3644 } 3645 3646 /* If we can split it and use I2DEST, go ahead and see if that 3647 helps things be recognized. Verify that none of the registers 3648 are set between I2 and I3. */ 3649 if (insn_code_number < 0 3650 && (split = find_split_point (&newpat, i3, false)) != 0 3651 #ifdef HAVE_cc0 3652 && REG_P (i2dest) 3653 #endif 3654 /* We need I2DEST in the proper mode. If it is a hard register 3655 or the only use of a pseudo, we can change its mode. 3656 Make sure we don't change a hard register to have a mode that 3657 isn't valid for it, or change the number of registers. */ 3658 && (GET_MODE (*split) == GET_MODE (i2dest) 3659 || GET_MODE (*split) == VOIDmode 3660 || can_change_dest_mode (i2dest, added_sets_2, 3661 GET_MODE (*split))) 3662 && (next_nonnote_nondebug_insn (i2) == i3 3663 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2))) 3664 /* We can't overwrite I2DEST if its value is still used by 3665 NEWPAT. */ 3666 && ! reg_referenced_p (i2dest, newpat)) 3667 { 3668 rtx newdest = i2dest; 3669 enum rtx_code split_code = GET_CODE (*split); 3670 machine_mode split_mode = GET_MODE (*split); 3671 bool subst_done = false; 3672 newi2pat = NULL_RTX; 3673 3674 i2scratch = true; 3675 3676 /* *SPLIT may be part of I2SRC, so make sure we have the 3677 original expression around for later debug processing. 3678 We should not need I2SRC any more in other cases. */ 3679 if (MAY_HAVE_DEBUG_INSNS) 3680 i2src = copy_rtx (i2src); 3681 else 3682 i2src = NULL; 3683 3684 /* Get NEWDEST as a register in the proper mode. We have already 3685 validated that we can do this. */ 3686 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) 3687 { 3688 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) 3689 newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); 3690 else 3691 { 3692 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode); 3693 newdest = regno_reg_rtx[REGNO (i2dest)]; 3694 } 3695 } 3696 3697 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to 3698 an ASHIFT. This can occur if it was inside a PLUS and hence 3699 appeared to be a memory address. This is a kludge. */ 3700 if (split_code == MULT 3701 && CONST_INT_P (XEXP (*split, 1)) 3702 && INTVAL (XEXP (*split, 1)) > 0 3703 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0) 3704 { 3705 SUBST (*split, gen_rtx_ASHIFT (split_mode, 3706 XEXP (*split, 0), GEN_INT (i))); 3707 /* Update split_code because we may not have a multiply 3708 anymore. */ 3709 split_code = GET_CODE (*split); 3710 } 3711 3712 #ifdef INSN_SCHEDULING 3713 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should 3714 be written as a ZERO_EXTEND. */ 3715 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))) 3716 { 3717 #ifdef LOAD_EXTEND_OP 3718 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's 3719 what it really is. */ 3720 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split))) 3721 == SIGN_EXTEND) 3722 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, 3723 SUBREG_REG (*split))); 3724 else 3725 #endif 3726 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, 3727 SUBREG_REG (*split))); 3728 } 3729 #endif 3730 3731 /* Attempt to split binary operators using arithmetic identities. */ 3732 if (BINARY_P (SET_SRC (newpat)) 3733 && split_mode == GET_MODE (SET_SRC (newpat)) 3734 && ! side_effects_p (SET_SRC (newpat))) 3735 { 3736 rtx setsrc = SET_SRC (newpat); 3737 machine_mode mode = GET_MODE (setsrc); 3738 enum rtx_code code = GET_CODE (setsrc); 3739 rtx src_op0 = XEXP (setsrc, 0); 3740 rtx src_op1 = XEXP (setsrc, 1); 3741 3742 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */ 3743 if (rtx_equal_p (src_op0, src_op1)) 3744 { 3745 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0); 3746 SUBST (XEXP (setsrc, 0), newdest); 3747 SUBST (XEXP (setsrc, 1), newdest); 3748 subst_done = true; 3749 } 3750 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */ 3751 else if ((code == PLUS || code == MULT) 3752 && GET_CODE (src_op0) == code 3753 && GET_CODE (XEXP (src_op0, 0)) == code 3754 && (INTEGRAL_MODE_P (mode) 3755 || (FLOAT_MODE_P (mode) 3756 && flag_unsafe_math_optimizations))) 3757 { 3758 rtx p = XEXP (XEXP (src_op0, 0), 0); 3759 rtx q = XEXP (XEXP (src_op0, 0), 1); 3760 rtx r = XEXP (src_op0, 1); 3761 rtx s = src_op1; 3762 3763 /* Split both "((X op Y) op X) op Y" and 3764 "((X op Y) op Y) op X" as "T op T" where T is 3765 "X op Y". */ 3766 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s)) 3767 || (rtx_equal_p (p,s) && rtx_equal_p (q,r))) 3768 { 3769 newi2pat = gen_rtx_SET (VOIDmode, newdest, 3770 XEXP (src_op0, 0)); 3771 SUBST (XEXP (setsrc, 0), newdest); 3772 SUBST (XEXP (setsrc, 1), newdest); 3773 subst_done = true; 3774 } 3775 /* Split "((X op X) op Y) op Y)" as "T op T" where 3776 T is "X op Y". */ 3777 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s)) 3778 { 3779 rtx tmp = simplify_gen_binary (code, mode, p, r); 3780 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp); 3781 SUBST (XEXP (setsrc, 0), newdest); 3782 SUBST (XEXP (setsrc, 1), newdest); 3783 subst_done = true; 3784 } 3785 } 3786 } 3787 3788 if (!subst_done) 3789 { 3790 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split); 3791 SUBST (*split, newdest); 3792 } 3793 3794 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3795 3796 /* recog_for_combine might have added CLOBBERs to newi2pat. 3797 Make sure NEWPAT does not depend on the clobbered regs. */ 3798 if (GET_CODE (newi2pat) == PARALLEL) 3799 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) 3800 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) 3801 { 3802 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); 3803 if (reg_overlap_mentioned_p (reg, newpat)) 3804 { 3805 undo_all (); 3806 return 0; 3807 } 3808 } 3809 3810 /* If the split point was a MULT and we didn't have one before, 3811 don't use one now. */ 3812 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) 3813 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3814 } 3815 } 3816 3817 /* Check for a case where we loaded from memory in a narrow mode and 3818 then sign extended it, but we need both registers. In that case, 3819 we have a PARALLEL with both loads from the same memory location. 3820 We can split this into a load from memory followed by a register-register 3821 copy. This saves at least one insn, more if register allocation can 3822 eliminate the copy. 3823 3824 We cannot do this if the destination of the first assignment is a 3825 condition code register or cc0. We eliminate this case by making sure 3826 the SET_DEST and SET_SRC have the same mode. 3827 3828 We cannot do this if the destination of the second assignment is 3829 a register that we have already assumed is zero-extended. Similarly 3830 for a SUBREG of such a register. */ 3831 3832 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 3833 && GET_CODE (newpat) == PARALLEL 3834 && XVECLEN (newpat, 0) == 2 3835 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 3836 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND 3837 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) 3838 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) 3839 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 3840 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), 3841 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) 3842 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 3843 DF_INSN_LUID (i2)) 3844 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 3845 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 3846 && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)), 3847 (REG_P (temp_expr) 3848 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0 3849 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD 3850 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT 3851 && (reg_stat[REGNO (temp_expr)].nonzero_bits 3852 != GET_MODE_MASK (word_mode)))) 3853 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG 3854 && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), 3855 (REG_P (temp_expr) 3856 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0 3857 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD 3858 && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT 3859 && (reg_stat[REGNO (temp_expr)].nonzero_bits 3860 != GET_MODE_MASK (word_mode))))) 3861 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), 3862 SET_SRC (XVECEXP (newpat, 0, 1))) 3863 && ! find_reg_note (i3, REG_UNUSED, 3864 SET_DEST (XVECEXP (newpat, 0, 0)))) 3865 { 3866 rtx ni2dest; 3867 3868 newi2pat = XVECEXP (newpat, 0, 0); 3869 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); 3870 newpat = XVECEXP (newpat, 0, 1); 3871 SUBST (SET_SRC (newpat), 3872 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest)); 3873 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3874 3875 if (i2_code_number >= 0) 3876 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3877 3878 if (insn_code_number >= 0) 3879 swap_i2i3 = 1; 3880 } 3881 3882 /* Similarly, check for a case where we have a PARALLEL of two independent 3883 SETs but we started with three insns. In this case, we can do the sets 3884 as two separate insns. This case occurs when some SET allows two 3885 other insns to combine, but the destination of that SET is still live. 3886 3887 Also do this if we started with two insns and (at least) one of the 3888 resulting sets is a noop; this noop will be deleted later. */ 3889 3890 else if (insn_code_number < 0 && asm_noperands (newpat) < 0 3891 && GET_CODE (newpat) == PARALLEL 3892 && XVECLEN (newpat, 0) == 2 3893 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 3894 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 3895 && (i1 || set_noop_p (XVECEXP (newpat, 0, 0)) 3896 || set_noop_p (XVECEXP (newpat, 0, 1))) 3897 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT 3898 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART 3899 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 3900 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 3901 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), 3902 XVECEXP (newpat, 0, 0)) 3903 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), 3904 XVECEXP (newpat, 0, 1)) 3905 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) 3906 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) 3907 { 3908 rtx set0 = XVECEXP (newpat, 0, 0); 3909 rtx set1 = XVECEXP (newpat, 0, 1); 3910 3911 /* Normally, it doesn't matter which of the two is done first, 3912 but the one that references cc0 can't be the second, and 3913 one which uses any regs/memory set in between i2 and i3 can't 3914 be first. The PARALLEL might also have been pre-existing in i3, 3915 so we need to make sure that we won't wrongly hoist a SET to i2 3916 that would conflict with a death note present in there. */ 3917 if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2)) 3918 && !(REG_P (SET_DEST (set1)) 3919 && find_reg_note (i2, REG_DEAD, SET_DEST (set1))) 3920 && !(GET_CODE (SET_DEST (set1)) == SUBREG 3921 && find_reg_note (i2, REG_DEAD, 3922 SUBREG_REG (SET_DEST (set1)))) 3923 #ifdef HAVE_cc0 3924 && !reg_referenced_p (cc0_rtx, set0) 3925 #endif 3926 /* If I3 is a jump, ensure that set0 is a jump so that 3927 we do not create invalid RTL. */ 3928 && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx) 3929 ) 3930 { 3931 newi2pat = set1; 3932 newpat = set0; 3933 } 3934 else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2)) 3935 && !(REG_P (SET_DEST (set0)) 3936 && find_reg_note (i2, REG_DEAD, SET_DEST (set0))) 3937 && !(GET_CODE (SET_DEST (set0)) == SUBREG 3938 && find_reg_note (i2, REG_DEAD, 3939 SUBREG_REG (SET_DEST (set0)))) 3940 #ifdef HAVE_cc0 3941 && !reg_referenced_p (cc0_rtx, set1) 3942 #endif 3943 /* If I3 is a jump, ensure that set1 is a jump so that 3944 we do not create invalid RTL. */ 3945 && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx) 3946 ) 3947 { 3948 newi2pat = set0; 3949 newpat = set1; 3950 } 3951 else 3952 { 3953 undo_all (); 3954 return 0; 3955 } 3956 3957 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 3958 3959 if (i2_code_number >= 0) 3960 { 3961 /* recog_for_combine might have added CLOBBERs to newi2pat. 3962 Make sure NEWPAT does not depend on the clobbered regs. */ 3963 if (GET_CODE (newi2pat) == PARALLEL) 3964 { 3965 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) 3966 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) 3967 { 3968 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); 3969 if (reg_overlap_mentioned_p (reg, newpat)) 3970 { 3971 undo_all (); 3972 return 0; 3973 } 3974 } 3975 } 3976 3977 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 3978 } 3979 } 3980 3981 /* If it still isn't recognized, fail and change things back the way they 3982 were. */ 3983 if ((insn_code_number < 0 3984 /* Is the result a reasonable ASM_OPERANDS? */ 3985 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) 3986 { 3987 undo_all (); 3988 return 0; 3989 } 3990 3991 /* If we had to change another insn, make sure it is valid also. */ 3992 if (undobuf.other_insn) 3993 { 3994 CLEAR_HARD_REG_SET (newpat_used_regs); 3995 3996 other_pat = PATTERN (undobuf.other_insn); 3997 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, 3998 &new_other_notes); 3999 4000 if (other_code_number < 0 && ! check_asm_operands (other_pat)) 4001 { 4002 undo_all (); 4003 return 0; 4004 } 4005 } 4006 4007 #ifdef HAVE_cc0 4008 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether 4009 they are adjacent to each other or not. */ 4010 { 4011 rtx_insn *p = prev_nonnote_insn (i3); 4012 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat 4013 && sets_cc0_p (newi2pat)) 4014 { 4015 undo_all (); 4016 return 0; 4017 } 4018 } 4019 #endif 4020 4021 /* Only allow this combination if insn_rtx_costs reports that the 4022 replacement instructions are cheaper than the originals. */ 4023 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat)) 4024 { 4025 undo_all (); 4026 return 0; 4027 } 4028 4029 if (MAY_HAVE_DEBUG_INSNS) 4030 { 4031 struct undo *undo; 4032 4033 for (undo = undobuf.undos; undo; undo = undo->next) 4034 if (undo->kind == UNDO_MODE) 4035 { 4036 rtx reg = *undo->where.r; 4037 machine_mode new_mode = GET_MODE (reg); 4038 machine_mode old_mode = undo->old_contents.m; 4039 4040 /* Temporarily revert mode back. */ 4041 adjust_reg_mode (reg, old_mode); 4042 4043 if (reg == i2dest && i2scratch) 4044 { 4045 /* If we used i2dest as a scratch register with a 4046 different mode, substitute it for the original 4047 i2src while its original mode is temporarily 4048 restored, and then clear i2scratch so that we don't 4049 do it again later. */ 4050 propagate_for_debug (i2, last_combined_insn, reg, i2src, 4051 this_basic_block); 4052 i2scratch = false; 4053 /* Put back the new mode. */ 4054 adjust_reg_mode (reg, new_mode); 4055 } 4056 else 4057 { 4058 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg)); 4059 rtx_insn *first, *last; 4060 4061 if (reg == i2dest) 4062 { 4063 first = i2; 4064 last = last_combined_insn; 4065 } 4066 else 4067 { 4068 first = i3; 4069 last = undobuf.other_insn; 4070 gcc_assert (last); 4071 if (DF_INSN_LUID (last) 4072 < DF_INSN_LUID (last_combined_insn)) 4073 last = last_combined_insn; 4074 } 4075 4076 /* We're dealing with a reg that changed mode but not 4077 meaning, so we want to turn it into a subreg for 4078 the new mode. However, because of REG sharing and 4079 because its mode had already changed, we have to do 4080 it in two steps. First, replace any debug uses of 4081 reg, with its original mode temporarily restored, 4082 with this copy we have created; then, replace the 4083 copy with the SUBREG of the original shared reg, 4084 once again changed to the new mode. */ 4085 propagate_for_debug (first, last, reg, tempreg, 4086 this_basic_block); 4087 adjust_reg_mode (reg, new_mode); 4088 propagate_for_debug (first, last, tempreg, 4089 lowpart_subreg (old_mode, reg, new_mode), 4090 this_basic_block); 4091 } 4092 } 4093 } 4094 4095 /* If we will be able to accept this, we have made a 4096 change to the destination of I3. This requires us to 4097 do a few adjustments. */ 4098 4099 if (changed_i3_dest) 4100 { 4101 PATTERN (i3) = newpat; 4102 adjust_for_new_dest (i3); 4103 } 4104 4105 /* We now know that we can do this combination. Merge the insns and 4106 update the status of registers and LOG_LINKS. */ 4107 4108 if (undobuf.other_insn) 4109 { 4110 rtx note, next; 4111 4112 PATTERN (undobuf.other_insn) = other_pat; 4113 4114 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED, 4115 ensure that they are still valid. Then add any non-duplicate 4116 notes added by recog_for_combine. */ 4117 for (note = REG_NOTES (undobuf.other_insn); note; note = next) 4118 { 4119 next = XEXP (note, 1); 4120 4121 if ((REG_NOTE_KIND (note) == REG_DEAD 4122 && !reg_referenced_p (XEXP (note, 0), 4123 PATTERN (undobuf.other_insn))) 4124 ||(REG_NOTE_KIND (note) == REG_UNUSED 4125 && !reg_set_p (XEXP (note, 0), 4126 PATTERN (undobuf.other_insn)))) 4127 remove_note (undobuf.other_insn, note); 4128 } 4129 4130 distribute_notes (new_other_notes, undobuf.other_insn, 4131 undobuf.other_insn, NULL, NULL_RTX, NULL_RTX, 4132 NULL_RTX); 4133 } 4134 4135 if (swap_i2i3) 4136 { 4137 rtx_insn *insn; 4138 struct insn_link *link; 4139 rtx ni2dest; 4140 4141 /* I3 now uses what used to be its destination and which is now 4142 I2's destination. This requires us to do a few adjustments. */ 4143 PATTERN (i3) = newpat; 4144 adjust_for_new_dest (i3); 4145 4146 /* We need a LOG_LINK from I3 to I2. But we used to have one, 4147 so we still will. 4148 4149 However, some later insn might be using I2's dest and have 4150 a LOG_LINK pointing at I3. We must remove this link. 4151 The simplest way to remove the link is to point it at I1, 4152 which we know will be a NOTE. */ 4153 4154 /* newi2pat is usually a SET here; however, recog_for_combine might 4155 have added some clobbers. */ 4156 if (GET_CODE (newi2pat) == PARALLEL) 4157 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0)); 4158 else 4159 ni2dest = SET_DEST (newi2pat); 4160 4161 for (insn = NEXT_INSN (i3); 4162 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 4163 || insn != BB_HEAD (this_basic_block->next_bb)); 4164 insn = NEXT_INSN (insn)) 4165 { 4166 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn))) 4167 { 4168 FOR_EACH_LOG_LINK (link, insn) 4169 if (link->insn == i3) 4170 link->insn = i1; 4171 4172 break; 4173 } 4174 } 4175 } 4176 4177 { 4178 rtx i3notes, i2notes, i1notes = 0, i0notes = 0; 4179 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0; 4180 rtx midnotes = 0; 4181 int from_luid; 4182 /* Compute which registers we expect to eliminate. newi2pat may be setting 4183 either i3dest or i2dest, so we must check it. */ 4184 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) 4185 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src 4186 || !i2dest_killed 4187 ? 0 : i2dest); 4188 /* For i1, we need to compute both local elimination and global 4189 elimination information with respect to newi2pat because i1dest 4190 may be the same as i3dest, in which case newi2pat may be setting 4191 i1dest. Global information is used when distributing REG_DEAD 4192 note for i2 and i3, in which case it does matter if newi2pat sets 4193 i1dest or not. 4194 4195 Local information is used when distributing REG_DEAD note for i1, 4196 in which case it doesn't matter if newi2pat sets i1dest or not. 4197 See PR62151, if we have four insns combination: 4198 i0: r0 <- i0src 4199 i1: r1 <- i1src (using r0) 4200 REG_DEAD (r0) 4201 i2: r0 <- i2src (using r1) 4202 i3: r3 <- i3src (using r0) 4203 ix: using r0 4204 From i1's point of view, r0 is eliminated, no matter if it is set 4205 by newi2pat or not. In other words, REG_DEAD info for r0 in i1 4206 should be discarded. 4207 4208 Note local information only affects cases in forms like "I1->I2->I3", 4209 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like 4210 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or 4211 i0dest anyway. */ 4212 rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src 4213 || !i1dest_killed 4214 ? 0 : i1dest); 4215 rtx elim_i1 = (local_elim_i1 == 0 4216 || (newi2pat && reg_set_p (i1dest, newi2pat)) 4217 ? 0 : i1dest); 4218 /* Same case as i1. */ 4219 rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed 4220 ? 0 : i0dest); 4221 rtx elim_i0 = (local_elim_i0 == 0 4222 || (newi2pat && reg_set_p (i0dest, newi2pat)) 4223 ? 0 : i0dest); 4224 4225 /* Get the old REG_NOTES and LOG_LINKS from all our insns and 4226 clear them. */ 4227 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); 4228 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); 4229 if (i1) 4230 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); 4231 if (i0) 4232 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0); 4233 4234 /* Ensure that we do not have something that should not be shared but 4235 occurs multiple times in the new insns. Check this by first 4236 resetting all the `used' flags and then copying anything is shared. */ 4237 4238 reset_used_flags (i3notes); 4239 reset_used_flags (i2notes); 4240 reset_used_flags (i1notes); 4241 reset_used_flags (i0notes); 4242 reset_used_flags (newpat); 4243 reset_used_flags (newi2pat); 4244 if (undobuf.other_insn) 4245 reset_used_flags (PATTERN (undobuf.other_insn)); 4246 4247 i3notes = copy_rtx_if_shared (i3notes); 4248 i2notes = copy_rtx_if_shared (i2notes); 4249 i1notes = copy_rtx_if_shared (i1notes); 4250 i0notes = copy_rtx_if_shared (i0notes); 4251 newpat = copy_rtx_if_shared (newpat); 4252 newi2pat = copy_rtx_if_shared (newi2pat); 4253 if (undobuf.other_insn) 4254 reset_used_flags (PATTERN (undobuf.other_insn)); 4255 4256 INSN_CODE (i3) = insn_code_number; 4257 PATTERN (i3) = newpat; 4258 4259 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3)) 4260 { 4261 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3); 4262 4263 reset_used_flags (call_usage); 4264 call_usage = copy_rtx (call_usage); 4265 4266 if (substed_i2) 4267 { 4268 /* I2SRC must still be meaningful at this point. Some splitting 4269 operations can invalidate I2SRC, but those operations do not 4270 apply to calls. */ 4271 gcc_assert (i2src); 4272 replace_rtx (call_usage, i2dest, i2src); 4273 } 4274 4275 if (substed_i1) 4276 replace_rtx (call_usage, i1dest, i1src); 4277 if (substed_i0) 4278 replace_rtx (call_usage, i0dest, i0src); 4279 4280 CALL_INSN_FUNCTION_USAGE (i3) = call_usage; 4281 } 4282 4283 if (undobuf.other_insn) 4284 INSN_CODE (undobuf.other_insn) = other_code_number; 4285 4286 /* We had one special case above where I2 had more than one set and 4287 we replaced a destination of one of those sets with the destination 4288 of I3. In that case, we have to update LOG_LINKS of insns later 4289 in this basic block. Note that this (expensive) case is rare. 4290 4291 Also, in this case, we must pretend that all REG_NOTEs for I2 4292 actually came from I3, so that REG_UNUSED notes from I2 will be 4293 properly handled. */ 4294 4295 if (i3_subst_into_i2) 4296 { 4297 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) 4298 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET 4299 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER) 4300 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) 4301 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest 4302 && ! find_reg_note (i2, REG_UNUSED, 4303 SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) 4304 for (temp_insn = NEXT_INSN (i2); 4305 temp_insn 4306 && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 4307 || BB_HEAD (this_basic_block) != temp_insn); 4308 temp_insn = NEXT_INSN (temp_insn)) 4309 if (temp_insn != i3 && INSN_P (temp_insn)) 4310 FOR_EACH_LOG_LINK (link, temp_insn) 4311 if (link->insn == i2) 4312 link->insn = i3; 4313 4314 if (i3notes) 4315 { 4316 rtx link = i3notes; 4317 while (XEXP (link, 1)) 4318 link = XEXP (link, 1); 4319 XEXP (link, 1) = i2notes; 4320 } 4321 else 4322 i3notes = i2notes; 4323 i2notes = 0; 4324 } 4325 4326 LOG_LINKS (i3) = NULL; 4327 REG_NOTES (i3) = 0; 4328 LOG_LINKS (i2) = NULL; 4329 REG_NOTES (i2) = 0; 4330 4331 if (newi2pat) 4332 { 4333 if (MAY_HAVE_DEBUG_INSNS && i2scratch) 4334 propagate_for_debug (i2, last_combined_insn, i2dest, i2src, 4335 this_basic_block); 4336 INSN_CODE (i2) = i2_code_number; 4337 PATTERN (i2) = newi2pat; 4338 } 4339 else 4340 { 4341 if (MAY_HAVE_DEBUG_INSNS && i2src) 4342 propagate_for_debug (i2, last_combined_insn, i2dest, i2src, 4343 this_basic_block); 4344 SET_INSN_DELETED (i2); 4345 } 4346 4347 if (i1) 4348 { 4349 LOG_LINKS (i1) = NULL; 4350 REG_NOTES (i1) = 0; 4351 if (MAY_HAVE_DEBUG_INSNS) 4352 propagate_for_debug (i1, last_combined_insn, i1dest, i1src, 4353 this_basic_block); 4354 SET_INSN_DELETED (i1); 4355 } 4356 4357 if (i0) 4358 { 4359 LOG_LINKS (i0) = NULL; 4360 REG_NOTES (i0) = 0; 4361 if (MAY_HAVE_DEBUG_INSNS) 4362 propagate_for_debug (i0, last_combined_insn, i0dest, i0src, 4363 this_basic_block); 4364 SET_INSN_DELETED (i0); 4365 } 4366 4367 /* Get death notes for everything that is now used in either I3 or 4368 I2 and used to die in a previous insn. If we built two new 4369 patterns, move from I1 to I2 then I2 to I3 so that we get the 4370 proper movement on registers that I2 modifies. */ 4371 4372 if (i0) 4373 from_luid = DF_INSN_LUID (i0); 4374 else if (i1) 4375 from_luid = DF_INSN_LUID (i1); 4376 else 4377 from_luid = DF_INSN_LUID (i2); 4378 if (newi2pat) 4379 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes); 4380 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes); 4381 4382 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 4383 if (i3notes) 4384 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL, 4385 elim_i2, elim_i1, elim_i0); 4386 if (i2notes) 4387 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL, 4388 elim_i2, elim_i1, elim_i0); 4389 if (i1notes) 4390 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL, 4391 elim_i2, local_elim_i1, local_elim_i0); 4392 if (i0notes) 4393 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL, 4394 elim_i2, elim_i1, local_elim_i0); 4395 if (midnotes) 4396 distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL, 4397 elim_i2, elim_i1, elim_i0); 4398 4399 /* Distribute any notes added to I2 or I3 by recog_for_combine. We 4400 know these are REG_UNUSED and want them to go to the desired insn, 4401 so we always pass it as i3. */ 4402 4403 if (newi2pat && new_i2_notes) 4404 distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX, 4405 NULL_RTX); 4406 4407 if (new_i3_notes) 4408 distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX, 4409 NULL_RTX); 4410 4411 /* If I3DEST was used in I3SRC, it really died in I3. We may need to 4412 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets 4413 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 4414 in that case, it might delete I2. Similarly for I2 and I1. 4415 Show an additional death due to the REG_DEAD note we make here. If 4416 we discard it in distribute_notes, we will decrement it again. */ 4417 4418 if (i3dest_killed) 4419 { 4420 rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX); 4421 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) 4422 distribute_notes (new_note, NULL, i2, NULL, elim_i2, 4423 elim_i1, elim_i0); 4424 else 4425 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4426 elim_i2, elim_i1, elim_i0); 4427 } 4428 4429 if (i2dest_in_i2src) 4430 { 4431 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX); 4432 if (newi2pat && reg_set_p (i2dest, newi2pat)) 4433 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, 4434 NULL_RTX, NULL_RTX); 4435 else 4436 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4437 NULL_RTX, NULL_RTX, NULL_RTX); 4438 } 4439 4440 if (i1dest_in_i1src) 4441 { 4442 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX); 4443 if (newi2pat && reg_set_p (i1dest, newi2pat)) 4444 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, 4445 NULL_RTX, NULL_RTX); 4446 else 4447 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4448 NULL_RTX, NULL_RTX, NULL_RTX); 4449 } 4450 4451 if (i0dest_in_i0src) 4452 { 4453 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX); 4454 if (newi2pat && reg_set_p (i0dest, newi2pat)) 4455 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX, 4456 NULL_RTX, NULL_RTX); 4457 else 4458 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL, 4459 NULL_RTX, NULL_RTX, NULL_RTX); 4460 } 4461 4462 distribute_links (i3links); 4463 distribute_links (i2links); 4464 distribute_links (i1links); 4465 distribute_links (i0links); 4466 4467 if (REG_P (i2dest)) 4468 { 4469 struct insn_link *link; 4470 rtx_insn *i2_insn = 0; 4471 rtx i2_val = 0, set; 4472 4473 /* The insn that used to set this register doesn't exist, and 4474 this life of the register may not exist either. See if one of 4475 I3's links points to an insn that sets I2DEST. If it does, 4476 that is now the last known value for I2DEST. If we don't update 4477 this and I2 set the register to a value that depended on its old 4478 contents, we will get confused. If this insn is used, thing 4479 will be set correctly in combine_instructions. */ 4480 FOR_EACH_LOG_LINK (link, i3) 4481 if ((set = single_set (link->insn)) != 0 4482 && rtx_equal_p (i2dest, SET_DEST (set))) 4483 i2_insn = link->insn, i2_val = SET_SRC (set); 4484 4485 record_value_for_reg (i2dest, i2_insn, i2_val); 4486 4487 /* If the reg formerly set in I2 died only once and that was in I3, 4488 zero its use count so it won't make `reload' do any work. */ 4489 if (! added_sets_2 4490 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) 4491 && ! i2dest_in_i2src 4492 && REGNO (i2dest) < reg_n_sets_max) 4493 INC_REG_N_SETS (REGNO (i2dest), -1); 4494 } 4495 4496 if (i1 && REG_P (i1dest)) 4497 { 4498 struct insn_link *link; 4499 rtx_insn *i1_insn = 0; 4500 rtx i1_val = 0, set; 4501 4502 FOR_EACH_LOG_LINK (link, i3) 4503 if ((set = single_set (link->insn)) != 0 4504 && rtx_equal_p (i1dest, SET_DEST (set))) 4505 i1_insn = link->insn, i1_val = SET_SRC (set); 4506 4507 record_value_for_reg (i1dest, i1_insn, i1_val); 4508 4509 if (! added_sets_1 4510 && ! i1dest_in_i1src 4511 && REGNO (i1dest) < reg_n_sets_max) 4512 INC_REG_N_SETS (REGNO (i1dest), -1); 4513 } 4514 4515 if (i0 && REG_P (i0dest)) 4516 { 4517 struct insn_link *link; 4518 rtx_insn *i0_insn = 0; 4519 rtx i0_val = 0, set; 4520 4521 FOR_EACH_LOG_LINK (link, i3) 4522 if ((set = single_set (link->insn)) != 0 4523 && rtx_equal_p (i0dest, SET_DEST (set))) 4524 i0_insn = link->insn, i0_val = SET_SRC (set); 4525 4526 record_value_for_reg (i0dest, i0_insn, i0_val); 4527 4528 if (! added_sets_0 4529 && ! i0dest_in_i0src 4530 && REGNO (i0dest) < reg_n_sets_max) 4531 INC_REG_N_SETS (REGNO (i0dest), -1); 4532 } 4533 4534 /* Update reg_stat[].nonzero_bits et al for any changes that may have 4535 been made to this insn. The order is important, because newi2pat 4536 can affect nonzero_bits of newpat. */ 4537 if (newi2pat) 4538 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); 4539 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); 4540 } 4541 4542 if (undobuf.other_insn != NULL_RTX) 4543 { 4544 if (dump_file) 4545 { 4546 fprintf (dump_file, "modifying other_insn "); 4547 dump_insn_slim (dump_file, undobuf.other_insn); 4548 } 4549 df_insn_rescan (undobuf.other_insn); 4550 } 4551 4552 if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED))) 4553 { 4554 if (dump_file) 4555 { 4556 fprintf (dump_file, "modifying insn i0 "); 4557 dump_insn_slim (dump_file, i0); 4558 } 4559 df_insn_rescan (i0); 4560 } 4561 4562 if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED))) 4563 { 4564 if (dump_file) 4565 { 4566 fprintf (dump_file, "modifying insn i1 "); 4567 dump_insn_slim (dump_file, i1); 4568 } 4569 df_insn_rescan (i1); 4570 } 4571 4572 if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED))) 4573 { 4574 if (dump_file) 4575 { 4576 fprintf (dump_file, "modifying insn i2 "); 4577 dump_insn_slim (dump_file, i2); 4578 } 4579 df_insn_rescan (i2); 4580 } 4581 4582 if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED))) 4583 { 4584 if (dump_file) 4585 { 4586 fprintf (dump_file, "modifying insn i3 "); 4587 dump_insn_slim (dump_file, i3); 4588 } 4589 df_insn_rescan (i3); 4590 } 4591 4592 /* Set new_direct_jump_p if a new return or simple jump instruction 4593 has been created. Adjust the CFG accordingly. */ 4594 if (returnjump_p (i3) || any_uncondjump_p (i3)) 4595 { 4596 *new_direct_jump_p = 1; 4597 mark_jump_label (PATTERN (i3), i3, 0); 4598 update_cfg_for_uncondjump (i3); 4599 } 4600 4601 if (undobuf.other_insn != NULL_RTX 4602 && (returnjump_p (undobuf.other_insn) 4603 || any_uncondjump_p (undobuf.other_insn))) 4604 { 4605 *new_direct_jump_p = 1; 4606 update_cfg_for_uncondjump (undobuf.other_insn); 4607 } 4608 4609 /* A noop might also need cleaning up of CFG, if it comes from the 4610 simplification of a jump. */ 4611 if (JUMP_P (i3) 4612 && GET_CODE (newpat) == SET 4613 && SET_SRC (newpat) == pc_rtx 4614 && SET_DEST (newpat) == pc_rtx) 4615 { 4616 *new_direct_jump_p = 1; 4617 update_cfg_for_uncondjump (i3); 4618 } 4619 4620 if (undobuf.other_insn != NULL_RTX 4621 && JUMP_P (undobuf.other_insn) 4622 && GET_CODE (PATTERN (undobuf.other_insn)) == SET 4623 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx 4624 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx) 4625 { 4626 *new_direct_jump_p = 1; 4627 update_cfg_for_uncondjump (undobuf.other_insn); 4628 } 4629 4630 combine_successes++; 4631 undo_commit (); 4632 4633 if (added_links_insn 4634 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2)) 4635 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3)) 4636 return added_links_insn; 4637 else 4638 return newi2pat ? i2 : i3; 4639 } 4640 4641 /* Undo all the modifications recorded in undobuf. */ 4642 4643 static void 4644 undo_all (void) 4645 { 4646 struct undo *undo, *next; 4647 4648 for (undo = undobuf.undos; undo; undo = next) 4649 { 4650 next = undo->next; 4651 switch (undo->kind) 4652 { 4653 case UNDO_RTX: 4654 *undo->where.r = undo->old_contents.r; 4655 break; 4656 case UNDO_INT: 4657 *undo->where.i = undo->old_contents.i; 4658 break; 4659 case UNDO_MODE: 4660 adjust_reg_mode (*undo->where.r, undo->old_contents.m); 4661 break; 4662 case UNDO_LINKS: 4663 *undo->where.l = undo->old_contents.l; 4664 break; 4665 default: 4666 gcc_unreachable (); 4667 } 4668 4669 undo->next = undobuf.frees; 4670 undobuf.frees = undo; 4671 } 4672 4673 undobuf.undos = 0; 4674 } 4675 4676 /* We've committed to accepting the changes we made. Move all 4677 of the undos to the free list. */ 4678 4679 static void 4680 undo_commit (void) 4681 { 4682 struct undo *undo, *next; 4683 4684 for (undo = undobuf.undos; undo; undo = next) 4685 { 4686 next = undo->next; 4687 undo->next = undobuf.frees; 4688 undobuf.frees = undo; 4689 } 4690 undobuf.undos = 0; 4691 } 4692 4693 /* Find the innermost point within the rtx at LOC, possibly LOC itself, 4694 where we have an arithmetic expression and return that point. LOC will 4695 be inside INSN. 4696 4697 try_combine will call this function to see if an insn can be split into 4698 two insns. */ 4699 4700 static rtx * 4701 find_split_point (rtx *loc, rtx_insn *insn, bool set_src) 4702 { 4703 rtx x = *loc; 4704 enum rtx_code code = GET_CODE (x); 4705 rtx *split; 4706 unsigned HOST_WIDE_INT len = 0; 4707 HOST_WIDE_INT pos = 0; 4708 int unsignedp = 0; 4709 rtx inner = NULL_RTX; 4710 4711 /* First special-case some codes. */ 4712 switch (code) 4713 { 4714 case SUBREG: 4715 #ifdef INSN_SCHEDULING 4716 /* If we are making a paradoxical SUBREG invalid, it becomes a split 4717 point. */ 4718 if (MEM_P (SUBREG_REG (x))) 4719 return loc; 4720 #endif 4721 return find_split_point (&SUBREG_REG (x), insn, false); 4722 4723 case MEM: 4724 #ifdef HAVE_lo_sum 4725 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 4726 using LO_SUM and HIGH. */ 4727 if (GET_CODE (XEXP (x, 0)) == CONST 4728 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) 4729 { 4730 machine_mode address_mode = get_address_mode (x); 4731 4732 SUBST (XEXP (x, 0), 4733 gen_rtx_LO_SUM (address_mode, 4734 gen_rtx_HIGH (address_mode, XEXP (x, 0)), 4735 XEXP (x, 0))); 4736 return &XEXP (XEXP (x, 0), 0); 4737 } 4738 #endif 4739 4740 /* If we have a PLUS whose second operand is a constant and the 4741 address is not valid, perhaps will can split it up using 4742 the machine-specific way to split large constants. We use 4743 the first pseudo-reg (one of the virtual regs) as a placeholder; 4744 it will not remain in the result. */ 4745 if (GET_CODE (XEXP (x, 0)) == PLUS 4746 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 4747 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), 4748 MEM_ADDR_SPACE (x))) 4749 { 4750 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; 4751 rtx_insn *seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg, 4752 XEXP (x, 0)), 4753 subst_insn); 4754 4755 /* This should have produced two insns, each of which sets our 4756 placeholder. If the source of the second is a valid address, 4757 we can make put both sources together and make a split point 4758 in the middle. */ 4759 4760 if (seq 4761 && NEXT_INSN (seq) != NULL_RTX 4762 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX 4763 && NONJUMP_INSN_P (seq) 4764 && GET_CODE (PATTERN (seq)) == SET 4765 && SET_DEST (PATTERN (seq)) == reg 4766 && ! reg_mentioned_p (reg, 4767 SET_SRC (PATTERN (seq))) 4768 && NONJUMP_INSN_P (NEXT_INSN (seq)) 4769 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET 4770 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg 4771 && memory_address_addr_space_p 4772 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))), 4773 MEM_ADDR_SPACE (x))) 4774 { 4775 rtx src1 = SET_SRC (PATTERN (seq)); 4776 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq))); 4777 4778 /* Replace the placeholder in SRC2 with SRC1. If we can 4779 find where in SRC2 it was placed, that can become our 4780 split point and we can replace this address with SRC2. 4781 Just try two obvious places. */ 4782 4783 src2 = replace_rtx (src2, reg, src1); 4784 split = 0; 4785 if (XEXP (src2, 0) == src1) 4786 split = &XEXP (src2, 0); 4787 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' 4788 && XEXP (XEXP (src2, 0), 0) == src1) 4789 split = &XEXP (XEXP (src2, 0), 0); 4790 4791 if (split) 4792 { 4793 SUBST (XEXP (x, 0), src2); 4794 return split; 4795 } 4796 } 4797 4798 /* If that didn't work, perhaps the first operand is complex and 4799 needs to be computed separately, so make a split point there. 4800 This will occur on machines that just support REG + CONST 4801 and have a constant moved through some previous computation. */ 4802 4803 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0)) 4804 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 4805 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) 4806 return &XEXP (XEXP (x, 0), 0); 4807 } 4808 4809 /* If we have a PLUS whose first operand is complex, try computing it 4810 separately by making a split there. */ 4811 if (GET_CODE (XEXP (x, 0)) == PLUS 4812 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), 4813 MEM_ADDR_SPACE (x)) 4814 && ! OBJECT_P (XEXP (XEXP (x, 0), 0)) 4815 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 4816 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) 4817 return &XEXP (XEXP (x, 0), 0); 4818 break; 4819 4820 case SET: 4821 #ifdef HAVE_cc0 4822 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a 4823 ZERO_EXTRACT, the most likely reason why this doesn't match is that 4824 we need to put the operand into a register. So split at that 4825 point. */ 4826 4827 if (SET_DEST (x) == cc0_rtx 4828 && GET_CODE (SET_SRC (x)) != COMPARE 4829 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT 4830 && !OBJECT_P (SET_SRC (x)) 4831 && ! (GET_CODE (SET_SRC (x)) == SUBREG 4832 && OBJECT_P (SUBREG_REG (SET_SRC (x))))) 4833 return &SET_SRC (x); 4834 #endif 4835 4836 /* See if we can split SET_SRC as it stands. */ 4837 split = find_split_point (&SET_SRC (x), insn, true); 4838 if (split && split != &SET_SRC (x)) 4839 return split; 4840 4841 /* See if we can split SET_DEST as it stands. */ 4842 split = find_split_point (&SET_DEST (x), insn, false); 4843 if (split && split != &SET_DEST (x)) 4844 return split; 4845 4846 /* See if this is a bitfield assignment with everything constant. If 4847 so, this is an IOR of an AND, so split it into that. */ 4848 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 4849 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0))) 4850 && CONST_INT_P (XEXP (SET_DEST (x), 1)) 4851 && CONST_INT_P (XEXP (SET_DEST (x), 2)) 4852 && CONST_INT_P (SET_SRC (x)) 4853 && ((INTVAL (XEXP (SET_DEST (x), 1)) 4854 + INTVAL (XEXP (SET_DEST (x), 2))) 4855 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)))) 4856 && ! side_effects_p (XEXP (SET_DEST (x), 0))) 4857 { 4858 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); 4859 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); 4860 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); 4861 rtx dest = XEXP (SET_DEST (x), 0); 4862 machine_mode mode = GET_MODE (dest); 4863 unsigned HOST_WIDE_INT mask 4864 = ((unsigned HOST_WIDE_INT) 1 << len) - 1; 4865 rtx or_mask; 4866 4867 if (BITS_BIG_ENDIAN) 4868 pos = GET_MODE_PRECISION (mode) - len - pos; 4869 4870 or_mask = gen_int_mode (src << pos, mode); 4871 if (src == mask) 4872 SUBST (SET_SRC (x), 4873 simplify_gen_binary (IOR, mode, dest, or_mask)); 4874 else 4875 { 4876 rtx negmask = gen_int_mode (~(mask << pos), mode); 4877 SUBST (SET_SRC (x), 4878 simplify_gen_binary (IOR, mode, 4879 simplify_gen_binary (AND, mode, 4880 dest, negmask), 4881 or_mask)); 4882 } 4883 4884 SUBST (SET_DEST (x), dest); 4885 4886 split = find_split_point (&SET_SRC (x), insn, true); 4887 if (split && split != &SET_SRC (x)) 4888 return split; 4889 } 4890 4891 /* Otherwise, see if this is an operation that we can split into two. 4892 If so, try to split that. */ 4893 code = GET_CODE (SET_SRC (x)); 4894 4895 switch (code) 4896 { 4897 case AND: 4898 /* If we are AND'ing with a large constant that is only a single 4899 bit and the result is only being used in a context where we 4900 need to know if it is zero or nonzero, replace it with a bit 4901 extraction. This will avoid the large constant, which might 4902 have taken more than one insn to make. If the constant were 4903 not a valid argument to the AND but took only one insn to make, 4904 this is no worse, but if it took more than one insn, it will 4905 be better. */ 4906 4907 if (CONST_INT_P (XEXP (SET_SRC (x), 1)) 4908 && REG_P (XEXP (SET_SRC (x), 0)) 4909 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7 4910 && REG_P (SET_DEST (x)) 4911 && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0 4912 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) 4913 && XEXP (*split, 0) == SET_DEST (x) 4914 && XEXP (*split, 1) == const0_rtx) 4915 { 4916 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), 4917 XEXP (SET_SRC (x), 0), 4918 pos, NULL_RTX, 1, 1, 0, 0); 4919 if (extraction != 0) 4920 { 4921 SUBST (SET_SRC (x), extraction); 4922 return find_split_point (loc, insn, false); 4923 } 4924 } 4925 break; 4926 4927 case NE: 4928 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X 4929 is known to be on, this can be converted into a NEG of a shift. */ 4930 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx 4931 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) 4932 && 1 <= (pos = exact_log2 4933 (nonzero_bits (XEXP (SET_SRC (x), 0), 4934 GET_MODE (XEXP (SET_SRC (x), 0)))))) 4935 { 4936 machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); 4937 4938 SUBST (SET_SRC (x), 4939 gen_rtx_NEG (mode, 4940 gen_rtx_LSHIFTRT (mode, 4941 XEXP (SET_SRC (x), 0), 4942 GEN_INT (pos)))); 4943 4944 split = find_split_point (&SET_SRC (x), insn, true); 4945 if (split && split != &SET_SRC (x)) 4946 return split; 4947 } 4948 break; 4949 4950 case SIGN_EXTEND: 4951 inner = XEXP (SET_SRC (x), 0); 4952 4953 /* We can't optimize if either mode is a partial integer 4954 mode as we don't know how many bits are significant 4955 in those modes. */ 4956 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT 4957 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) 4958 break; 4959 4960 pos = 0; 4961 len = GET_MODE_PRECISION (GET_MODE (inner)); 4962 unsignedp = 0; 4963 break; 4964 4965 case SIGN_EXTRACT: 4966 case ZERO_EXTRACT: 4967 if (CONST_INT_P (XEXP (SET_SRC (x), 1)) 4968 && CONST_INT_P (XEXP (SET_SRC (x), 2))) 4969 { 4970 inner = XEXP (SET_SRC (x), 0); 4971 len = INTVAL (XEXP (SET_SRC (x), 1)); 4972 pos = INTVAL (XEXP (SET_SRC (x), 2)); 4973 4974 if (BITS_BIG_ENDIAN) 4975 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos; 4976 unsignedp = (code == ZERO_EXTRACT); 4977 } 4978 break; 4979 4980 default: 4981 break; 4982 } 4983 4984 if (len && pos >= 0 4985 && pos + len <= GET_MODE_PRECISION (GET_MODE (inner))) 4986 { 4987 machine_mode mode = GET_MODE (SET_SRC (x)); 4988 4989 /* For unsigned, we have a choice of a shift followed by an 4990 AND or two shifts. Use two shifts for field sizes where the 4991 constant might be too large. We assume here that we can 4992 always at least get 8-bit constants in an AND insn, which is 4993 true for every current RISC. */ 4994 4995 if (unsignedp && len <= 8) 4996 { 4997 unsigned HOST_WIDE_INT mask 4998 = ((unsigned HOST_WIDE_INT) 1 << len) - 1; 4999 SUBST (SET_SRC (x), 5000 gen_rtx_AND (mode, 5001 gen_rtx_LSHIFTRT 5002 (mode, gen_lowpart (mode, inner), 5003 GEN_INT (pos)), 5004 gen_int_mode (mask, mode))); 5005 5006 split = find_split_point (&SET_SRC (x), insn, true); 5007 if (split && split != &SET_SRC (x)) 5008 return split; 5009 } 5010 else 5011 { 5012 SUBST (SET_SRC (x), 5013 gen_rtx_fmt_ee 5014 (unsignedp ? LSHIFTRT : ASHIFTRT, mode, 5015 gen_rtx_ASHIFT (mode, 5016 gen_lowpart (mode, inner), 5017 GEN_INT (GET_MODE_PRECISION (mode) 5018 - len - pos)), 5019 GEN_INT (GET_MODE_PRECISION (mode) - len))); 5020 5021 split = find_split_point (&SET_SRC (x), insn, true); 5022 if (split && split != &SET_SRC (x)) 5023 return split; 5024 } 5025 } 5026 5027 /* See if this is a simple operation with a constant as the second 5028 operand. It might be that this constant is out of range and hence 5029 could be used as a split point. */ 5030 if (BINARY_P (SET_SRC (x)) 5031 && CONSTANT_P (XEXP (SET_SRC (x), 1)) 5032 && (OBJECT_P (XEXP (SET_SRC (x), 0)) 5033 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG 5034 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0)))))) 5035 return &XEXP (SET_SRC (x), 1); 5036 5037 /* Finally, see if this is a simple operation with its first operand 5038 not in a register. The operation might require this operand in a 5039 register, so return it as a split point. We can always do this 5040 because if the first operand were another operation, we would have 5041 already found it as a split point. */ 5042 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x))) 5043 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) 5044 return &XEXP (SET_SRC (x), 0); 5045 5046 return 0; 5047 5048 case AND: 5049 case IOR: 5050 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, 5051 it is better to write this as (not (ior A B)) so we can split it. 5052 Similarly for IOR. */ 5053 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) 5054 { 5055 SUBST (*loc, 5056 gen_rtx_NOT (GET_MODE (x), 5057 gen_rtx_fmt_ee (code == IOR ? AND : IOR, 5058 GET_MODE (x), 5059 XEXP (XEXP (x, 0), 0), 5060 XEXP (XEXP (x, 1), 0)))); 5061 return find_split_point (loc, insn, set_src); 5062 } 5063 5064 /* Many RISC machines have a large set of logical insns. If the 5065 second operand is a NOT, put it first so we will try to split the 5066 other operand first. */ 5067 if (GET_CODE (XEXP (x, 1)) == NOT) 5068 { 5069 rtx tem = XEXP (x, 0); 5070 SUBST (XEXP (x, 0), XEXP (x, 1)); 5071 SUBST (XEXP (x, 1), tem); 5072 } 5073 break; 5074 5075 case PLUS: 5076 case MINUS: 5077 /* Canonicalization can produce (minus A (mult B C)), where C is a 5078 constant. It may be better to try splitting (plus (mult B -C) A) 5079 instead if this isn't a multiply by a power of two. */ 5080 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT 5081 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 5082 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0) 5083 { 5084 machine_mode mode = GET_MODE (x); 5085 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1)); 5086 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode); 5087 SUBST (*loc, gen_rtx_PLUS (mode, 5088 gen_rtx_MULT (mode, 5089 XEXP (XEXP (x, 1), 0), 5090 gen_int_mode (other_int, 5091 mode)), 5092 XEXP (x, 0))); 5093 return find_split_point (loc, insn, set_src); 5094 } 5095 5096 /* Split at a multiply-accumulate instruction. However if this is 5097 the SET_SRC, we likely do not have such an instruction and it's 5098 worthless to try this split. */ 5099 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT) 5100 return loc; 5101 5102 default: 5103 break; 5104 } 5105 5106 /* Otherwise, select our actions depending on our rtx class. */ 5107 switch (GET_RTX_CLASS (code)) 5108 { 5109 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ 5110 case RTX_TERNARY: 5111 split = find_split_point (&XEXP (x, 2), insn, false); 5112 if (split) 5113 return split; 5114 /* ... fall through ... */ 5115 case RTX_BIN_ARITH: 5116 case RTX_COMM_ARITH: 5117 case RTX_COMPARE: 5118 case RTX_COMM_COMPARE: 5119 split = find_split_point (&XEXP (x, 1), insn, false); 5120 if (split) 5121 return split; 5122 /* ... fall through ... */ 5123 case RTX_UNARY: 5124 /* Some machines have (and (shift ...) ...) insns. If X is not 5125 an AND, but XEXP (X, 0) is, use it as our split point. */ 5126 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) 5127 return &XEXP (x, 0); 5128 5129 split = find_split_point (&XEXP (x, 0), insn, false); 5130 if (split) 5131 return split; 5132 return loc; 5133 5134 default: 5135 /* Otherwise, we don't have a split point. */ 5136 return 0; 5137 } 5138 } 5139 5140 /* Throughout X, replace FROM with TO, and return the result. 5141 The result is TO if X is FROM; 5142 otherwise the result is X, but its contents may have been modified. 5143 If they were modified, a record was made in undobuf so that 5144 undo_all will (among other things) return X to its original state. 5145 5146 If the number of changes necessary is too much to record to undo, 5147 the excess changes are not made, so the result is invalid. 5148 The changes already made can still be undone. 5149 undobuf.num_undo is incremented for such changes, so by testing that 5150 the caller can tell whether the result is valid. 5151 5152 `n_occurrences' is incremented each time FROM is replaced. 5153 5154 IN_DEST is nonzero if we are processing the SET_DEST of a SET. 5155 5156 IN_COND is nonzero if we are at the top level of a condition. 5157 5158 UNIQUE_COPY is nonzero if each substitution must be unique. We do this 5159 by copying if `n_occurrences' is nonzero. */ 5160 5161 static rtx 5162 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy) 5163 { 5164 enum rtx_code code = GET_CODE (x); 5165 machine_mode op0_mode = VOIDmode; 5166 const char *fmt; 5167 int len, i; 5168 rtx new_rtx; 5169 5170 /* Two expressions are equal if they are identical copies of a shared 5171 RTX or if they are both registers with the same register number 5172 and mode. */ 5173 5174 #define COMBINE_RTX_EQUAL_P(X,Y) \ 5175 ((X) == (Y) \ 5176 || (REG_P (X) && REG_P (Y) \ 5177 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) 5178 5179 /* Do not substitute into clobbers of regs -- this will never result in 5180 valid RTL. */ 5181 if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0))) 5182 return x; 5183 5184 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) 5185 { 5186 n_occurrences++; 5187 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); 5188 } 5189 5190 /* If X and FROM are the same register but different modes, they 5191 will not have been seen as equal above. However, the log links code 5192 will make a LOG_LINKS entry for that case. If we do nothing, we 5193 will try to rerecognize our original insn and, when it succeeds, 5194 we will delete the feeding insn, which is incorrect. 5195 5196 So force this insn not to match in this (rare) case. */ 5197 if (! in_dest && code == REG && REG_P (from) 5198 && reg_overlap_mentioned_p (x, from)) 5199 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 5200 5201 /* If this is an object, we are done unless it is a MEM or LO_SUM, both 5202 of which may contain things that can be combined. */ 5203 if (code != MEM && code != LO_SUM && OBJECT_P (x)) 5204 return x; 5205 5206 /* It is possible to have a subexpression appear twice in the insn. 5207 Suppose that FROM is a register that appears within TO. 5208 Then, after that subexpression has been scanned once by `subst', 5209 the second time it is scanned, TO may be found. If we were 5210 to scan TO here, we would find FROM within it and create a 5211 self-referent rtl structure which is completely wrong. */ 5212 if (COMBINE_RTX_EQUAL_P (x, to)) 5213 return to; 5214 5215 /* Parallel asm_operands need special attention because all of the 5216 inputs are shared across the arms. Furthermore, unsharing the 5217 rtl results in recognition failures. Failure to handle this case 5218 specially can result in circular rtl. 5219 5220 Solve this by doing a normal pass across the first entry of the 5221 parallel, and only processing the SET_DESTs of the subsequent 5222 entries. Ug. */ 5223 5224 if (code == PARALLEL 5225 && GET_CODE (XVECEXP (x, 0, 0)) == SET 5226 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) 5227 { 5228 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy); 5229 5230 /* If this substitution failed, this whole thing fails. */ 5231 if (GET_CODE (new_rtx) == CLOBBER 5232 && XEXP (new_rtx, 0) == const0_rtx) 5233 return new_rtx; 5234 5235 SUBST (XVECEXP (x, 0, 0), new_rtx); 5236 5237 for (i = XVECLEN (x, 0) - 1; i >= 1; i--) 5238 { 5239 rtx dest = SET_DEST (XVECEXP (x, 0, i)); 5240 5241 if (!REG_P (dest) 5242 && GET_CODE (dest) != CC0 5243 && GET_CODE (dest) != PC) 5244 { 5245 new_rtx = subst (dest, from, to, 0, 0, unique_copy); 5246 5247 /* If this substitution failed, this whole thing fails. */ 5248 if (GET_CODE (new_rtx) == CLOBBER 5249 && XEXP (new_rtx, 0) == const0_rtx) 5250 return new_rtx; 5251 5252 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx); 5253 } 5254 } 5255 } 5256 else 5257 { 5258 len = GET_RTX_LENGTH (code); 5259 fmt = GET_RTX_FORMAT (code); 5260 5261 /* We don't need to process a SET_DEST that is a register, CC0, 5262 or PC, so set up to skip this common case. All other cases 5263 where we want to suppress replacing something inside a 5264 SET_SRC are handled via the IN_DEST operand. */ 5265 if (code == SET 5266 && (REG_P (SET_DEST (x)) 5267 || GET_CODE (SET_DEST (x)) == CC0 5268 || GET_CODE (SET_DEST (x)) == PC)) 5269 fmt = "ie"; 5270 5271 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a 5272 constant. */ 5273 if (fmt[0] == 'e') 5274 op0_mode = GET_MODE (XEXP (x, 0)); 5275 5276 for (i = 0; i < len; i++) 5277 { 5278 if (fmt[i] == 'E') 5279 { 5280 int j; 5281 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 5282 { 5283 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) 5284 { 5285 new_rtx = (unique_copy && n_occurrences 5286 ? copy_rtx (to) : to); 5287 n_occurrences++; 5288 } 5289 else 5290 { 5291 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0, 5292 unique_copy); 5293 5294 /* If this substitution failed, this whole thing 5295 fails. */ 5296 if (GET_CODE (new_rtx) == CLOBBER 5297 && XEXP (new_rtx, 0) == const0_rtx) 5298 return new_rtx; 5299 } 5300 5301 SUBST (XVECEXP (x, i, j), new_rtx); 5302 } 5303 } 5304 else if (fmt[i] == 'e') 5305 { 5306 /* If this is a register being set, ignore it. */ 5307 new_rtx = XEXP (x, i); 5308 if (in_dest 5309 && i == 0 5310 && (((code == SUBREG || code == ZERO_EXTRACT) 5311 && REG_P (new_rtx)) 5312 || code == STRICT_LOW_PART)) 5313 ; 5314 5315 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) 5316 { 5317 /* In general, don't install a subreg involving two 5318 modes not tieable. It can worsen register 5319 allocation, and can even make invalid reload 5320 insns, since the reg inside may need to be copied 5321 from in the outside mode, and that may be invalid 5322 if it is an fp reg copied in integer mode. 5323 5324 We allow two exceptions to this: It is valid if 5325 it is inside another SUBREG and the mode of that 5326 SUBREG and the mode of the inside of TO is 5327 tieable and it is valid if X is a SET that copies 5328 FROM to CC0. */ 5329 5330 if (GET_CODE (to) == SUBREG 5331 && ! MODES_TIEABLE_P (GET_MODE (to), 5332 GET_MODE (SUBREG_REG (to))) 5333 && ! (code == SUBREG 5334 && MODES_TIEABLE_P (GET_MODE (x), 5335 GET_MODE (SUBREG_REG (to)))) 5336 #ifdef HAVE_cc0 5337 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) 5338 #endif 5339 ) 5340 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 5341 5342 if (code == SUBREG 5343 && REG_P (to) 5344 && REGNO (to) < FIRST_PSEUDO_REGISTER 5345 && simplify_subreg_regno (REGNO (to), GET_MODE (to), 5346 SUBREG_BYTE (x), 5347 GET_MODE (x)) < 0) 5348 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 5349 5350 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to); 5351 n_occurrences++; 5352 } 5353 else 5354 /* If we are in a SET_DEST, suppress most cases unless we 5355 have gone inside a MEM, in which case we want to 5356 simplify the address. We assume here that things that 5357 are actually part of the destination have their inner 5358 parts in the first expression. This is true for SUBREG, 5359 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only 5360 things aside from REG and MEM that should appear in a 5361 SET_DEST. */ 5362 new_rtx = subst (XEXP (x, i), from, to, 5363 (((in_dest 5364 && (code == SUBREG || code == STRICT_LOW_PART 5365 || code == ZERO_EXTRACT)) 5366 || code == SET) 5367 && i == 0), 5368 code == IF_THEN_ELSE && i == 0, 5369 unique_copy); 5370 5371 /* If we found that we will have to reject this combination, 5372 indicate that by returning the CLOBBER ourselves, rather than 5373 an expression containing it. This will speed things up as 5374 well as prevent accidents where two CLOBBERs are considered 5375 to be equal, thus producing an incorrect simplification. */ 5376 5377 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx) 5378 return new_rtx; 5379 5380 if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx)) 5381 { 5382 machine_mode mode = GET_MODE (x); 5383 5384 x = simplify_subreg (GET_MODE (x), new_rtx, 5385 GET_MODE (SUBREG_REG (x)), 5386 SUBREG_BYTE (x)); 5387 if (! x) 5388 x = gen_rtx_CLOBBER (mode, const0_rtx); 5389 } 5390 else if (CONST_SCALAR_INT_P (new_rtx) 5391 && GET_CODE (x) == ZERO_EXTEND) 5392 { 5393 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), 5394 new_rtx, GET_MODE (XEXP (x, 0))); 5395 gcc_assert (x); 5396 } 5397 else 5398 SUBST (XEXP (x, i), new_rtx); 5399 } 5400 } 5401 } 5402 5403 /* Check if we are loading something from the constant pool via float 5404 extension; in this case we would undo compress_float_constant 5405 optimization and degenerate constant load to an immediate value. */ 5406 if (GET_CODE (x) == FLOAT_EXTEND 5407 && MEM_P (XEXP (x, 0)) 5408 && MEM_READONLY_P (XEXP (x, 0))) 5409 { 5410 rtx tmp = avoid_constant_pool_reference (x); 5411 if (x != tmp) 5412 return x; 5413 } 5414 5415 /* Try to simplify X. If the simplification changed the code, it is likely 5416 that further simplification will help, so loop, but limit the number 5417 of repetitions that will be performed. */ 5418 5419 for (i = 0; i < 4; i++) 5420 { 5421 /* If X is sufficiently simple, don't bother trying to do anything 5422 with it. */ 5423 if (code != CONST_INT && code != REG && code != CLOBBER) 5424 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond); 5425 5426 if (GET_CODE (x) == code) 5427 break; 5428 5429 code = GET_CODE (x); 5430 5431 /* We no longer know the original mode of operand 0 since we 5432 have changed the form of X) */ 5433 op0_mode = VOIDmode; 5434 } 5435 5436 return x; 5437 } 5438 5439 /* Simplify X, a piece of RTL. We just operate on the expression at the 5440 outer level; call `subst' to simplify recursively. Return the new 5441 expression. 5442 5443 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero 5444 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level 5445 of a condition. */ 5446 5447 static rtx 5448 combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest, 5449 int in_cond) 5450 { 5451 enum rtx_code code = GET_CODE (x); 5452 machine_mode mode = GET_MODE (x); 5453 rtx temp; 5454 int i; 5455 5456 /* If this is a commutative operation, put a constant last and a complex 5457 expression first. We don't need to do this for comparisons here. */ 5458 if (COMMUTATIVE_ARITH_P (x) 5459 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 5460 { 5461 temp = XEXP (x, 0); 5462 SUBST (XEXP (x, 0), XEXP (x, 1)); 5463 SUBST (XEXP (x, 1), temp); 5464 } 5465 5466 /* If this is a simple operation applied to an IF_THEN_ELSE, try 5467 applying it to the arms of the IF_THEN_ELSE. This often simplifies 5468 things. Check for cases where both arms are testing the same 5469 condition. 5470 5471 Don't do anything if all operands are very simple. */ 5472 5473 if ((BINARY_P (x) 5474 && ((!OBJECT_P (XEXP (x, 0)) 5475 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 5476 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))) 5477 || (!OBJECT_P (XEXP (x, 1)) 5478 && ! (GET_CODE (XEXP (x, 1)) == SUBREG 5479 && OBJECT_P (SUBREG_REG (XEXP (x, 1))))))) 5480 || (UNARY_P (x) 5481 && (!OBJECT_P (XEXP (x, 0)) 5482 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 5483 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))))) 5484 { 5485 rtx cond, true_rtx, false_rtx; 5486 5487 cond = if_then_else_cond (x, &true_rtx, &false_rtx); 5488 if (cond != 0 5489 /* If everything is a comparison, what we have is highly unlikely 5490 to be simpler, so don't use it. */ 5491 && ! (COMPARISON_P (x) 5492 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))) 5493 { 5494 rtx cop1 = const0_rtx; 5495 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); 5496 5497 if (cond_code == NE && COMPARISON_P (cond)) 5498 return x; 5499 5500 /* Simplify the alternative arms; this may collapse the true and 5501 false arms to store-flag values. Be careful to use copy_rtx 5502 here since true_rtx or false_rtx might share RTL with x as a 5503 result of the if_then_else_cond call above. */ 5504 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0); 5505 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0); 5506 5507 /* If true_rtx and false_rtx are not general_operands, an if_then_else 5508 is unlikely to be simpler. */ 5509 if (general_operand (true_rtx, VOIDmode) 5510 && general_operand (false_rtx, VOIDmode)) 5511 { 5512 enum rtx_code reversed; 5513 5514 /* Restarting if we generate a store-flag expression will cause 5515 us to loop. Just drop through in this case. */ 5516 5517 /* If the result values are STORE_FLAG_VALUE and zero, we can 5518 just make the comparison operation. */ 5519 if (true_rtx == const_true_rtx && false_rtx == const0_rtx) 5520 x = simplify_gen_relational (cond_code, mode, VOIDmode, 5521 cond, cop1); 5522 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx 5523 && ((reversed = reversed_comparison_code_parts 5524 (cond_code, cond, cop1, NULL)) 5525 != UNKNOWN)) 5526 x = simplify_gen_relational (reversed, mode, VOIDmode, 5527 cond, cop1); 5528 5529 /* Likewise, we can make the negate of a comparison operation 5530 if the result values are - STORE_FLAG_VALUE and zero. */ 5531 else if (CONST_INT_P (true_rtx) 5532 && INTVAL (true_rtx) == - STORE_FLAG_VALUE 5533 && false_rtx == const0_rtx) 5534 x = simplify_gen_unary (NEG, mode, 5535 simplify_gen_relational (cond_code, 5536 mode, VOIDmode, 5537 cond, cop1), 5538 mode); 5539 else if (CONST_INT_P (false_rtx) 5540 && INTVAL (false_rtx) == - STORE_FLAG_VALUE 5541 && true_rtx == const0_rtx 5542 && ((reversed = reversed_comparison_code_parts 5543 (cond_code, cond, cop1, NULL)) 5544 != UNKNOWN)) 5545 x = simplify_gen_unary (NEG, mode, 5546 simplify_gen_relational (reversed, 5547 mode, VOIDmode, 5548 cond, cop1), 5549 mode); 5550 else 5551 return gen_rtx_IF_THEN_ELSE (mode, 5552 simplify_gen_relational (cond_code, 5553 mode, 5554 VOIDmode, 5555 cond, 5556 cop1), 5557 true_rtx, false_rtx); 5558 5559 code = GET_CODE (x); 5560 op0_mode = VOIDmode; 5561 } 5562 } 5563 } 5564 5565 /* Try to fold this expression in case we have constants that weren't 5566 present before. */ 5567 temp = 0; 5568 switch (GET_RTX_CLASS (code)) 5569 { 5570 case RTX_UNARY: 5571 if (op0_mode == VOIDmode) 5572 op0_mode = GET_MODE (XEXP (x, 0)); 5573 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); 5574 break; 5575 case RTX_COMPARE: 5576 case RTX_COMM_COMPARE: 5577 { 5578 machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); 5579 if (cmp_mode == VOIDmode) 5580 { 5581 cmp_mode = GET_MODE (XEXP (x, 1)); 5582 if (cmp_mode == VOIDmode) 5583 cmp_mode = op0_mode; 5584 } 5585 temp = simplify_relational_operation (code, mode, cmp_mode, 5586 XEXP (x, 0), XEXP (x, 1)); 5587 } 5588 break; 5589 case RTX_COMM_ARITH: 5590 case RTX_BIN_ARITH: 5591 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); 5592 break; 5593 case RTX_BITFIELD_OPS: 5594 case RTX_TERNARY: 5595 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), 5596 XEXP (x, 1), XEXP (x, 2)); 5597 break; 5598 default: 5599 break; 5600 } 5601 5602 if (temp) 5603 { 5604 x = temp; 5605 code = GET_CODE (temp); 5606 op0_mode = VOIDmode; 5607 mode = GET_MODE (temp); 5608 } 5609 5610 /* First see if we can apply the inverse distributive law. */ 5611 if (code == PLUS || code == MINUS 5612 || code == AND || code == IOR || code == XOR) 5613 { 5614 x = apply_distributive_law (x); 5615 code = GET_CODE (x); 5616 op0_mode = VOIDmode; 5617 } 5618 5619 /* If CODE is an associative operation not otherwise handled, see if we 5620 can associate some operands. This can win if they are constants or 5621 if they are logically related (i.e. (a & b) & a). */ 5622 if ((code == PLUS || code == MINUS || code == MULT || code == DIV 5623 || code == AND || code == IOR || code == XOR 5624 || code == SMAX || code == SMIN || code == UMAX || code == UMIN) 5625 && ((INTEGRAL_MODE_P (mode) && code != DIV) 5626 || (flag_associative_math && FLOAT_MODE_P (mode)))) 5627 { 5628 if (GET_CODE (XEXP (x, 0)) == code) 5629 { 5630 rtx other = XEXP (XEXP (x, 0), 0); 5631 rtx inner_op0 = XEXP (XEXP (x, 0), 1); 5632 rtx inner_op1 = XEXP (x, 1); 5633 rtx inner; 5634 5635 /* Make sure we pass the constant operand if any as the second 5636 one if this is a commutative operation. */ 5637 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x)) 5638 { 5639 rtx tem = inner_op0; 5640 inner_op0 = inner_op1; 5641 inner_op1 = tem; 5642 } 5643 inner = simplify_binary_operation (code == MINUS ? PLUS 5644 : code == DIV ? MULT 5645 : code, 5646 mode, inner_op0, inner_op1); 5647 5648 /* For commutative operations, try the other pair if that one 5649 didn't simplify. */ 5650 if (inner == 0 && COMMUTATIVE_ARITH_P (x)) 5651 { 5652 other = XEXP (XEXP (x, 0), 1); 5653 inner = simplify_binary_operation (code, mode, 5654 XEXP (XEXP (x, 0), 0), 5655 XEXP (x, 1)); 5656 } 5657 5658 if (inner) 5659 return simplify_gen_binary (code, mode, other, inner); 5660 } 5661 } 5662 5663 /* A little bit of algebraic simplification here. */ 5664 switch (code) 5665 { 5666 case MEM: 5667 /* Ensure that our address has any ASHIFTs converted to MULT in case 5668 address-recognizing predicates are called later. */ 5669 temp = make_compound_operation (XEXP (x, 0), MEM); 5670 SUBST (XEXP (x, 0), temp); 5671 break; 5672 5673 case SUBREG: 5674 if (op0_mode == VOIDmode) 5675 op0_mode = GET_MODE (SUBREG_REG (x)); 5676 5677 /* See if this can be moved to simplify_subreg. */ 5678 if (CONSTANT_P (SUBREG_REG (x)) 5679 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) 5680 /* Don't call gen_lowpart if the inner mode 5681 is VOIDmode and we cannot simplify it, as SUBREG without 5682 inner mode is invalid. */ 5683 && (GET_MODE (SUBREG_REG (x)) != VOIDmode 5684 || gen_lowpart_common (mode, SUBREG_REG (x)))) 5685 return gen_lowpart (mode, SUBREG_REG (x)); 5686 5687 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) 5688 break; 5689 { 5690 rtx temp; 5691 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, 5692 SUBREG_BYTE (x)); 5693 if (temp) 5694 return temp; 5695 5696 /* If op is known to have all lower bits zero, the result is zero. */ 5697 if (!in_dest 5698 && SCALAR_INT_MODE_P (mode) 5699 && SCALAR_INT_MODE_P (op0_mode) 5700 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode) 5701 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) 5702 && HWI_COMPUTABLE_MODE_P (op0_mode) 5703 && (nonzero_bits (SUBREG_REG (x), op0_mode) 5704 & GET_MODE_MASK (mode)) == 0) 5705 return CONST0_RTX (mode); 5706 } 5707 5708 /* Don't change the mode of the MEM if that would change the meaning 5709 of the address. */ 5710 if (MEM_P (SUBREG_REG (x)) 5711 && (MEM_VOLATILE_P (SUBREG_REG (x)) 5712 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0), 5713 MEM_ADDR_SPACE (SUBREG_REG (x))))) 5714 return gen_rtx_CLOBBER (mode, const0_rtx); 5715 5716 /* Note that we cannot do any narrowing for non-constants since 5717 we might have been counting on using the fact that some bits were 5718 zero. We now do this in the SET. */ 5719 5720 break; 5721 5722 case NEG: 5723 temp = expand_compound_operation (XEXP (x, 0)); 5724 5725 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be 5726 replaced by (lshiftrt X C). This will convert 5727 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ 5728 5729 if (GET_CODE (temp) == ASHIFTRT 5730 && CONST_INT_P (XEXP (temp, 1)) 5731 && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1) 5732 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0), 5733 INTVAL (XEXP (temp, 1))); 5734 5735 /* If X has only a single bit that might be nonzero, say, bit I, convert 5736 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of 5737 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to 5738 (sign_extract X 1 Y). But only do this if TEMP isn't a register 5739 or a SUBREG of one since we'd be making the expression more 5740 complex if it was just a register. */ 5741 5742 if (!REG_P (temp) 5743 && ! (GET_CODE (temp) == SUBREG 5744 && REG_P (SUBREG_REG (temp))) 5745 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) 5746 { 5747 rtx temp1 = simplify_shift_const 5748 (NULL_RTX, ASHIFTRT, mode, 5749 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, 5750 GET_MODE_PRECISION (mode) - 1 - i), 5751 GET_MODE_PRECISION (mode) - 1 - i); 5752 5753 /* If all we did was surround TEMP with the two shifts, we 5754 haven't improved anything, so don't use it. Otherwise, 5755 we are better off with TEMP1. */ 5756 if (GET_CODE (temp1) != ASHIFTRT 5757 || GET_CODE (XEXP (temp1, 0)) != ASHIFT 5758 || XEXP (XEXP (temp1, 0), 0) != temp) 5759 return temp1; 5760 } 5761 break; 5762 5763 case TRUNCATE: 5764 /* We can't handle truncation to a partial integer mode here 5765 because we don't know the real bitsize of the partial 5766 integer mode. */ 5767 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) 5768 break; 5769 5770 if (HWI_COMPUTABLE_MODE_P (mode)) 5771 SUBST (XEXP (x, 0), 5772 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), 5773 GET_MODE_MASK (mode), 0)); 5774 5775 /* We can truncate a constant value and return it. */ 5776 if (CONST_INT_P (XEXP (x, 0))) 5777 return gen_int_mode (INTVAL (XEXP (x, 0)), mode); 5778 5779 /* Similarly to what we do in simplify-rtx.c, a truncate of a register 5780 whose value is a comparison can be replaced with a subreg if 5781 STORE_FLAG_VALUE permits. */ 5782 if (HWI_COMPUTABLE_MODE_P (mode) 5783 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 5784 && (temp = get_last_value (XEXP (x, 0))) 5785 && COMPARISON_P (temp)) 5786 return gen_lowpart (mode, XEXP (x, 0)); 5787 break; 5788 5789 case CONST: 5790 /* (const (const X)) can become (const X). Do it this way rather than 5791 returning the inner CONST since CONST can be shared with a 5792 REG_EQUAL note. */ 5793 if (GET_CODE (XEXP (x, 0)) == CONST) 5794 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 5795 break; 5796 5797 #ifdef HAVE_lo_sum 5798 case LO_SUM: 5799 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we 5800 can add in an offset. find_split_point will split this address up 5801 again if it doesn't match. */ 5802 if (GET_CODE (XEXP (x, 0)) == HIGH 5803 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) 5804 return XEXP (x, 1); 5805 break; 5806 #endif 5807 5808 case PLUS: 5809 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) 5810 when c is (const_int (pow2 + 1) / 2) is a sign extension of a 5811 bit-field and can be replaced by either a sign_extend or a 5812 sign_extract. The `and' may be a zero_extend and the two 5813 <c>, -<c> constants may be reversed. */ 5814 if (GET_CODE (XEXP (x, 0)) == XOR 5815 && CONST_INT_P (XEXP (x, 1)) 5816 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 5817 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) 5818 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 5819 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0) 5820 && HWI_COMPUTABLE_MODE_P (mode) 5821 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND 5822 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1)) 5823 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) 5824 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1)) 5825 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND 5826 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) 5827 == (unsigned int) i + 1)))) 5828 return simplify_shift_const 5829 (NULL_RTX, ASHIFTRT, mode, 5830 simplify_shift_const (NULL_RTX, ASHIFT, mode, 5831 XEXP (XEXP (XEXP (x, 0), 0), 0), 5832 GET_MODE_PRECISION (mode) - (i + 1)), 5833 GET_MODE_PRECISION (mode) - (i + 1)); 5834 5835 /* If only the low-order bit of X is possibly nonzero, (plus x -1) 5836 can become (ashiftrt (ashift (xor x 1) C) C) where C is 5837 the bitsize of the mode - 1. This allows simplification of 5838 "a = (b & 8) == 0;" */ 5839 if (XEXP (x, 1) == constm1_rtx 5840 && !REG_P (XEXP (x, 0)) 5841 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 5842 && REG_P (SUBREG_REG (XEXP (x, 0)))) 5843 && nonzero_bits (XEXP (x, 0), mode) == 1) 5844 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, 5845 simplify_shift_const (NULL_RTX, ASHIFT, mode, 5846 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), 5847 GET_MODE_PRECISION (mode) - 1), 5848 GET_MODE_PRECISION (mode) - 1); 5849 5850 /* If we are adding two things that have no bits in common, convert 5851 the addition into an IOR. This will often be further simplified, 5852 for example in cases like ((a & 1) + (a & 2)), which can 5853 become a & 3. */ 5854 5855 if (HWI_COMPUTABLE_MODE_P (mode) 5856 && (nonzero_bits (XEXP (x, 0), mode) 5857 & nonzero_bits (XEXP (x, 1), mode)) == 0) 5858 { 5859 /* Try to simplify the expression further. */ 5860 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 5861 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0); 5862 5863 /* If we could, great. If not, do not go ahead with the IOR 5864 replacement, since PLUS appears in many special purpose 5865 address arithmetic instructions. */ 5866 if (GET_CODE (temp) != CLOBBER 5867 && (GET_CODE (temp) != IOR 5868 || ((XEXP (temp, 0) != XEXP (x, 0) 5869 || XEXP (temp, 1) != XEXP (x, 1)) 5870 && (XEXP (temp, 0) != XEXP (x, 1) 5871 || XEXP (temp, 1) != XEXP (x, 0))))) 5872 return temp; 5873 } 5874 break; 5875 5876 case MINUS: 5877 /* (minus <foo> (and <foo> (const_int -pow2))) becomes 5878 (and <foo> (const_int pow2-1)) */ 5879 if (GET_CODE (XEXP (x, 1)) == AND 5880 && CONST_INT_P (XEXP (XEXP (x, 1), 1)) 5881 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0 5882 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 5883 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), 5884 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); 5885 break; 5886 5887 case MULT: 5888 /* If we have (mult (plus A B) C), apply the distributive law and then 5889 the inverse distributive law to see if things simplify. This 5890 occurs mostly in addresses, often when unrolling loops. */ 5891 5892 if (GET_CODE (XEXP (x, 0)) == PLUS) 5893 { 5894 rtx result = distribute_and_simplify_rtx (x, 0); 5895 if (result) 5896 return result; 5897 } 5898 5899 /* Try simplify a*(b/c) as (a*b)/c. */ 5900 if (FLOAT_MODE_P (mode) && flag_associative_math 5901 && GET_CODE (XEXP (x, 0)) == DIV) 5902 { 5903 rtx tem = simplify_binary_operation (MULT, mode, 5904 XEXP (XEXP (x, 0), 0), 5905 XEXP (x, 1)); 5906 if (tem) 5907 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); 5908 } 5909 break; 5910 5911 case UDIV: 5912 /* If this is a divide by a power of two, treat it as a shift if 5913 its first operand is a shift. */ 5914 if (CONST_INT_P (XEXP (x, 1)) 5915 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0 5916 && (GET_CODE (XEXP (x, 0)) == ASHIFT 5917 || GET_CODE (XEXP (x, 0)) == LSHIFTRT 5918 || GET_CODE (XEXP (x, 0)) == ASHIFTRT 5919 || GET_CODE (XEXP (x, 0)) == ROTATE 5920 || GET_CODE (XEXP (x, 0)) == ROTATERT)) 5921 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); 5922 break; 5923 5924 case EQ: case NE: 5925 case GT: case GTU: case GE: case GEU: 5926 case LT: case LTU: case LE: case LEU: 5927 case UNEQ: case LTGT: 5928 case UNGT: case UNGE: 5929 case UNLT: case UNLE: 5930 case UNORDERED: case ORDERED: 5931 /* If the first operand is a condition code, we can't do anything 5932 with it. */ 5933 if (GET_CODE (XEXP (x, 0)) == COMPARE 5934 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC 5935 && ! CC0_P (XEXP (x, 0)))) 5936 { 5937 rtx op0 = XEXP (x, 0); 5938 rtx op1 = XEXP (x, 1); 5939 enum rtx_code new_code; 5940 5941 if (GET_CODE (op0) == COMPARE) 5942 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 5943 5944 /* Simplify our comparison, if possible. */ 5945 new_code = simplify_comparison (code, &op0, &op1); 5946 5947 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X 5948 if only the low-order bit is possibly nonzero in X (such as when 5949 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to 5950 (xor X 1) or (minus 1 X); we use the former. Finally, if X is 5951 known to be either 0 or -1, NE becomes a NEG and EQ becomes 5952 (plus X 1). 5953 5954 Remove any ZERO_EXTRACT we made when thinking this was a 5955 comparison. It may now be simpler to use, e.g., an AND. If a 5956 ZERO_EXTRACT is indeed appropriate, it will be placed back by 5957 the call to make_compound_operation in the SET case. 5958 5959 Don't apply these optimizations if the caller would 5960 prefer a comparison rather than a value. 5961 E.g., for the condition in an IF_THEN_ELSE most targets need 5962 an explicit comparison. */ 5963 5964 if (in_cond) 5965 ; 5966 5967 else if (STORE_FLAG_VALUE == 1 5968 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 5969 && op1 == const0_rtx 5970 && mode == GET_MODE (op0) 5971 && nonzero_bits (op0, mode) == 1) 5972 return gen_lowpart (mode, 5973 expand_compound_operation (op0)); 5974 5975 else if (STORE_FLAG_VALUE == 1 5976 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 5977 && op1 == const0_rtx 5978 && mode == GET_MODE (op0) 5979 && (num_sign_bit_copies (op0, mode) 5980 == GET_MODE_PRECISION (mode))) 5981 { 5982 op0 = expand_compound_operation (op0); 5983 return simplify_gen_unary (NEG, mode, 5984 gen_lowpart (mode, op0), 5985 mode); 5986 } 5987 5988 else if (STORE_FLAG_VALUE == 1 5989 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 5990 && op1 == const0_rtx 5991 && mode == GET_MODE (op0) 5992 && nonzero_bits (op0, mode) == 1) 5993 { 5994 op0 = expand_compound_operation (op0); 5995 return simplify_gen_binary (XOR, mode, 5996 gen_lowpart (mode, op0), 5997 const1_rtx); 5998 } 5999 6000 else if (STORE_FLAG_VALUE == 1 6001 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 6002 && op1 == const0_rtx 6003 && mode == GET_MODE (op0) 6004 && (num_sign_bit_copies (op0, mode) 6005 == GET_MODE_PRECISION (mode))) 6006 { 6007 op0 = expand_compound_operation (op0); 6008 return plus_constant (mode, gen_lowpart (mode, op0), 1); 6009 } 6010 6011 /* If STORE_FLAG_VALUE is -1, we have cases similar to 6012 those above. */ 6013 if (in_cond) 6014 ; 6015 6016 else if (STORE_FLAG_VALUE == -1 6017 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 6018 && op1 == const0_rtx 6019 && mode == GET_MODE (op0) 6020 && (num_sign_bit_copies (op0, mode) 6021 == GET_MODE_PRECISION (mode))) 6022 return gen_lowpart (mode, 6023 expand_compound_operation (op0)); 6024 6025 else if (STORE_FLAG_VALUE == -1 6026 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 6027 && op1 == const0_rtx 6028 && mode == GET_MODE (op0) 6029 && nonzero_bits (op0, mode) == 1) 6030 { 6031 op0 = expand_compound_operation (op0); 6032 return simplify_gen_unary (NEG, mode, 6033 gen_lowpart (mode, op0), 6034 mode); 6035 } 6036 6037 else if (STORE_FLAG_VALUE == -1 6038 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 6039 && op1 == const0_rtx 6040 && mode == GET_MODE (op0) 6041 && (num_sign_bit_copies (op0, mode) 6042 == GET_MODE_PRECISION (mode))) 6043 { 6044 op0 = expand_compound_operation (op0); 6045 return simplify_gen_unary (NOT, mode, 6046 gen_lowpart (mode, op0), 6047 mode); 6048 } 6049 6050 /* If X is 0/1, (eq X 0) is X-1. */ 6051 else if (STORE_FLAG_VALUE == -1 6052 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 6053 && op1 == const0_rtx 6054 && mode == GET_MODE (op0) 6055 && nonzero_bits (op0, mode) == 1) 6056 { 6057 op0 = expand_compound_operation (op0); 6058 return plus_constant (mode, gen_lowpart (mode, op0), -1); 6059 } 6060 6061 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just 6062 one bit that might be nonzero, we can convert (ne x 0) to 6063 (ashift x c) where C puts the bit in the sign bit. Remove any 6064 AND with STORE_FLAG_VALUE when we are done, since we are only 6065 going to test the sign bit. */ 6066 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 6067 && HWI_COMPUTABLE_MODE_P (mode) 6068 && val_signbit_p (mode, STORE_FLAG_VALUE) 6069 && op1 == const0_rtx 6070 && mode == GET_MODE (op0) 6071 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) 6072 { 6073 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, 6074 expand_compound_operation (op0), 6075 GET_MODE_PRECISION (mode) - 1 - i); 6076 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) 6077 return XEXP (x, 0); 6078 else 6079 return x; 6080 } 6081 6082 /* If the code changed, return a whole new comparison. 6083 We also need to avoid using SUBST in cases where 6084 simplify_comparison has widened a comparison with a CONST_INT, 6085 since in that case the wider CONST_INT may fail the sanity 6086 checks in do_SUBST. */ 6087 if (new_code != code 6088 || (CONST_INT_P (op1) 6089 && GET_MODE (op0) != GET_MODE (XEXP (x, 0)) 6090 && GET_MODE (op0) != GET_MODE (XEXP (x, 1)))) 6091 return gen_rtx_fmt_ee (new_code, mode, op0, op1); 6092 6093 /* Otherwise, keep this operation, but maybe change its operands. 6094 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ 6095 SUBST (XEXP (x, 0), op0); 6096 SUBST (XEXP (x, 1), op1); 6097 } 6098 break; 6099 6100 case IF_THEN_ELSE: 6101 return simplify_if_then_else (x); 6102 6103 case ZERO_EXTRACT: 6104 case SIGN_EXTRACT: 6105 case ZERO_EXTEND: 6106 case SIGN_EXTEND: 6107 /* If we are processing SET_DEST, we are done. */ 6108 if (in_dest) 6109 return x; 6110 6111 return expand_compound_operation (x); 6112 6113 case SET: 6114 return simplify_set (x); 6115 6116 case AND: 6117 case IOR: 6118 return simplify_logical (x); 6119 6120 case ASHIFT: 6121 case LSHIFTRT: 6122 case ASHIFTRT: 6123 case ROTATE: 6124 case ROTATERT: 6125 /* If this is a shift by a constant amount, simplify it. */ 6126 if (CONST_INT_P (XEXP (x, 1))) 6127 return simplify_shift_const (x, code, mode, XEXP (x, 0), 6128 INTVAL (XEXP (x, 1))); 6129 6130 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1))) 6131 SUBST (XEXP (x, 1), 6132 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)), 6133 ((unsigned HOST_WIDE_INT) 1 6134 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) 6135 - 1, 6136 0)); 6137 break; 6138 6139 default: 6140 break; 6141 } 6142 6143 return x; 6144 } 6145 6146 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ 6147 6148 static rtx 6149 simplify_if_then_else (rtx x) 6150 { 6151 machine_mode mode = GET_MODE (x); 6152 rtx cond = XEXP (x, 0); 6153 rtx true_rtx = XEXP (x, 1); 6154 rtx false_rtx = XEXP (x, 2); 6155 enum rtx_code true_code = GET_CODE (cond); 6156 int comparison_p = COMPARISON_P (cond); 6157 rtx temp; 6158 int i; 6159 enum rtx_code false_code; 6160 rtx reversed; 6161 6162 /* Simplify storing of the truth value. */ 6163 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) 6164 return simplify_gen_relational (true_code, mode, VOIDmode, 6165 XEXP (cond, 0), XEXP (cond, 1)); 6166 6167 /* Also when the truth value has to be reversed. */ 6168 if (comparison_p 6169 && true_rtx == const0_rtx && false_rtx == const_true_rtx 6170 && (reversed = reversed_comparison (cond, mode))) 6171 return reversed; 6172 6173 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used 6174 in it is being compared against certain values. Get the true and false 6175 comparisons and see if that says anything about the value of each arm. */ 6176 6177 if (comparison_p 6178 && ((false_code = reversed_comparison_code (cond, NULL)) 6179 != UNKNOWN) 6180 && REG_P (XEXP (cond, 0))) 6181 { 6182 HOST_WIDE_INT nzb; 6183 rtx from = XEXP (cond, 0); 6184 rtx true_val = XEXP (cond, 1); 6185 rtx false_val = true_val; 6186 int swapped = 0; 6187 6188 /* If FALSE_CODE is EQ, swap the codes and arms. */ 6189 6190 if (false_code == EQ) 6191 { 6192 swapped = 1, true_code = EQ, false_code = NE; 6193 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; 6194 } 6195 6196 /* If we are comparing against zero and the expression being tested has 6197 only a single bit that might be nonzero, that is its value when it is 6198 not equal to zero. Similarly if it is known to be -1 or 0. */ 6199 6200 if (true_code == EQ && true_val == const0_rtx 6201 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) 6202 { 6203 false_code = EQ; 6204 false_val = gen_int_mode (nzb, GET_MODE (from)); 6205 } 6206 else if (true_code == EQ && true_val == const0_rtx 6207 && (num_sign_bit_copies (from, GET_MODE (from)) 6208 == GET_MODE_PRECISION (GET_MODE (from)))) 6209 { 6210 false_code = EQ; 6211 false_val = constm1_rtx; 6212 } 6213 6214 /* Now simplify an arm if we know the value of the register in the 6215 branch and it is used in the arm. Be careful due to the potential 6216 of locally-shared RTL. */ 6217 6218 if (reg_mentioned_p (from, true_rtx)) 6219 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, 6220 from, true_val), 6221 pc_rtx, pc_rtx, 0, 0, 0); 6222 if (reg_mentioned_p (from, false_rtx)) 6223 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, 6224 from, false_val), 6225 pc_rtx, pc_rtx, 0, 0, 0); 6226 6227 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); 6228 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); 6229 6230 true_rtx = XEXP (x, 1); 6231 false_rtx = XEXP (x, 2); 6232 true_code = GET_CODE (cond); 6233 } 6234 6235 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be 6236 reversed, do so to avoid needing two sets of patterns for 6237 subtract-and-branch insns. Similarly if we have a constant in the true 6238 arm, the false arm is the same as the first operand of the comparison, or 6239 the false arm is more complicated than the true arm. */ 6240 6241 if (comparison_p 6242 && reversed_comparison_code (cond, NULL) != UNKNOWN 6243 && (true_rtx == pc_rtx 6244 || (CONSTANT_P (true_rtx) 6245 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx) 6246 || true_rtx == const0_rtx 6247 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx)) 6248 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx)) 6249 && !OBJECT_P (false_rtx)) 6250 || reg_mentioned_p (true_rtx, false_rtx) 6251 || rtx_equal_p (false_rtx, XEXP (cond, 0)))) 6252 { 6253 true_code = reversed_comparison_code (cond, NULL); 6254 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond))); 6255 SUBST (XEXP (x, 1), false_rtx); 6256 SUBST (XEXP (x, 2), true_rtx); 6257 6258 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; 6259 cond = XEXP (x, 0); 6260 6261 /* It is possible that the conditional has been simplified out. */ 6262 true_code = GET_CODE (cond); 6263 comparison_p = COMPARISON_P (cond); 6264 } 6265 6266 /* If the two arms are identical, we don't need the comparison. */ 6267 6268 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) 6269 return true_rtx; 6270 6271 /* Convert a == b ? b : a to "a". */ 6272 if (true_code == EQ && ! side_effects_p (cond) 6273 && !HONOR_NANS (mode) 6274 && rtx_equal_p (XEXP (cond, 0), false_rtx) 6275 && rtx_equal_p (XEXP (cond, 1), true_rtx)) 6276 return false_rtx; 6277 else if (true_code == NE && ! side_effects_p (cond) 6278 && !HONOR_NANS (mode) 6279 && rtx_equal_p (XEXP (cond, 0), true_rtx) 6280 && rtx_equal_p (XEXP (cond, 1), false_rtx)) 6281 return true_rtx; 6282 6283 /* Look for cases where we have (abs x) or (neg (abs X)). */ 6284 6285 if (GET_MODE_CLASS (mode) == MODE_INT 6286 && comparison_p 6287 && XEXP (cond, 1) == const0_rtx 6288 && GET_CODE (false_rtx) == NEG 6289 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) 6290 && rtx_equal_p (true_rtx, XEXP (cond, 0)) 6291 && ! side_effects_p (true_rtx)) 6292 switch (true_code) 6293 { 6294 case GT: 6295 case GE: 6296 return simplify_gen_unary (ABS, mode, true_rtx, mode); 6297 case LT: 6298 case LE: 6299 return 6300 simplify_gen_unary (NEG, mode, 6301 simplify_gen_unary (ABS, mode, true_rtx, mode), 6302 mode); 6303 default: 6304 break; 6305 } 6306 6307 /* Look for MIN or MAX. */ 6308 6309 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) 6310 && comparison_p 6311 && rtx_equal_p (XEXP (cond, 0), true_rtx) 6312 && rtx_equal_p (XEXP (cond, 1), false_rtx) 6313 && ! side_effects_p (cond)) 6314 switch (true_code) 6315 { 6316 case GE: 6317 case GT: 6318 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx); 6319 case LE: 6320 case LT: 6321 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx); 6322 case GEU: 6323 case GTU: 6324 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx); 6325 case LEU: 6326 case LTU: 6327 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx); 6328 default: 6329 break; 6330 } 6331 6332 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its 6333 second operand is zero, this can be done as (OP Z (mult COND C2)) where 6334 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or 6335 SIGN_EXTEND as long as Z is already extended (so we don't destroy it). 6336 We can do this kind of thing in some cases when STORE_FLAG_VALUE is 6337 neither 1 or -1, but it isn't worth checking for. */ 6338 6339 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 6340 && comparison_p 6341 && GET_MODE_CLASS (mode) == MODE_INT 6342 && ! side_effects_p (x)) 6343 { 6344 rtx t = make_compound_operation (true_rtx, SET); 6345 rtx f = make_compound_operation (false_rtx, SET); 6346 rtx cond_op0 = XEXP (cond, 0); 6347 rtx cond_op1 = XEXP (cond, 1); 6348 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; 6349 machine_mode m = mode; 6350 rtx z = 0, c1 = NULL_RTX; 6351 6352 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS 6353 || GET_CODE (t) == IOR || GET_CODE (t) == XOR 6354 || GET_CODE (t) == ASHIFT 6355 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) 6356 && rtx_equal_p (XEXP (t, 0), f)) 6357 c1 = XEXP (t, 1), op = GET_CODE (t), z = f; 6358 6359 /* If an identity-zero op is commutative, check whether there 6360 would be a match if we swapped the operands. */ 6361 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR 6362 || GET_CODE (t) == XOR) 6363 && rtx_equal_p (XEXP (t, 1), f)) 6364 c1 = XEXP (t, 0), op = GET_CODE (t), z = f; 6365 else if (GET_CODE (t) == SIGN_EXTEND 6366 && (GET_CODE (XEXP (t, 0)) == PLUS 6367 || GET_CODE (XEXP (t, 0)) == MINUS 6368 || GET_CODE (XEXP (t, 0)) == IOR 6369 || GET_CODE (XEXP (t, 0)) == XOR 6370 || GET_CODE (XEXP (t, 0)) == ASHIFT 6371 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 6372 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 6373 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 6374 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 6375 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 6376 && (num_sign_bit_copies (f, GET_MODE (f)) 6377 > (unsigned int) 6378 (GET_MODE_PRECISION (mode) 6379 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0)))))) 6380 { 6381 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 6382 extend_op = SIGN_EXTEND; 6383 m = GET_MODE (XEXP (t, 0)); 6384 } 6385 else if (GET_CODE (t) == SIGN_EXTEND 6386 && (GET_CODE (XEXP (t, 0)) == PLUS 6387 || GET_CODE (XEXP (t, 0)) == IOR 6388 || GET_CODE (XEXP (t, 0)) == XOR) 6389 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 6390 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 6391 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 6392 && (num_sign_bit_copies (f, GET_MODE (f)) 6393 > (unsigned int) 6394 (GET_MODE_PRECISION (mode) 6395 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1)))))) 6396 { 6397 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 6398 extend_op = SIGN_EXTEND; 6399 m = GET_MODE (XEXP (t, 0)); 6400 } 6401 else if (GET_CODE (t) == ZERO_EXTEND 6402 && (GET_CODE (XEXP (t, 0)) == PLUS 6403 || GET_CODE (XEXP (t, 0)) == MINUS 6404 || GET_CODE (XEXP (t, 0)) == IOR 6405 || GET_CODE (XEXP (t, 0)) == XOR 6406 || GET_CODE (XEXP (t, 0)) == ASHIFT 6407 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 6408 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 6409 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 6410 && HWI_COMPUTABLE_MODE_P (mode) 6411 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 6412 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 6413 && ((nonzero_bits (f, GET_MODE (f)) 6414 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) 6415 == 0)) 6416 { 6417 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 6418 extend_op = ZERO_EXTEND; 6419 m = GET_MODE (XEXP (t, 0)); 6420 } 6421 else if (GET_CODE (t) == ZERO_EXTEND 6422 && (GET_CODE (XEXP (t, 0)) == PLUS 6423 || GET_CODE (XEXP (t, 0)) == IOR 6424 || GET_CODE (XEXP (t, 0)) == XOR) 6425 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 6426 && HWI_COMPUTABLE_MODE_P (mode) 6427 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 6428 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 6429 && ((nonzero_bits (f, GET_MODE (f)) 6430 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) 6431 == 0)) 6432 { 6433 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 6434 extend_op = ZERO_EXTEND; 6435 m = GET_MODE (XEXP (t, 0)); 6436 } 6437 6438 if (z) 6439 { 6440 temp = subst (simplify_gen_relational (true_code, m, VOIDmode, 6441 cond_op0, cond_op1), 6442 pc_rtx, pc_rtx, 0, 0, 0); 6443 temp = simplify_gen_binary (MULT, m, temp, 6444 simplify_gen_binary (MULT, m, c1, 6445 const_true_rtx)); 6446 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0); 6447 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); 6448 6449 if (extend_op != UNKNOWN) 6450 temp = simplify_gen_unary (extend_op, mode, temp, m); 6451 6452 return temp; 6453 } 6454 } 6455 6456 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or 6457 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the 6458 negation of a single bit, we can convert this operation to a shift. We 6459 can actually do this more generally, but it doesn't seem worth it. */ 6460 6461 if (true_code == NE && XEXP (cond, 1) == const0_rtx 6462 && false_rtx == const0_rtx && CONST_INT_P (true_rtx) 6463 && ((1 == nonzero_bits (XEXP (cond, 0), mode) 6464 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0) 6465 || ((num_sign_bit_copies (XEXP (cond, 0), mode) 6466 == GET_MODE_PRECISION (mode)) 6467 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0))) 6468 return 6469 simplify_shift_const (NULL_RTX, ASHIFT, mode, 6470 gen_lowpart (mode, XEXP (cond, 0)), i); 6471 6472 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */ 6473 if (true_code == NE && XEXP (cond, 1) == const0_rtx 6474 && false_rtx == const0_rtx && CONST_INT_P (true_rtx) 6475 && GET_MODE (XEXP (cond, 0)) == mode 6476 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode)) 6477 == nonzero_bits (XEXP (cond, 0), mode) 6478 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0) 6479 return XEXP (cond, 0); 6480 6481 return x; 6482 } 6483 6484 /* Simplify X, a SET expression. Return the new expression. */ 6485 6486 static rtx 6487 simplify_set (rtx x) 6488 { 6489 rtx src = SET_SRC (x); 6490 rtx dest = SET_DEST (x); 6491 machine_mode mode 6492 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); 6493 rtx_insn *other_insn; 6494 rtx *cc_use; 6495 6496 /* (set (pc) (return)) gets written as (return). */ 6497 if (GET_CODE (dest) == PC && ANY_RETURN_P (src)) 6498 return src; 6499 6500 /* Now that we know for sure which bits of SRC we are using, see if we can 6501 simplify the expression for the object knowing that we only need the 6502 low-order bits. */ 6503 6504 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode)) 6505 { 6506 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0); 6507 SUBST (SET_SRC (x), src); 6508 } 6509 6510 /* If we are setting CC0 or if the source is a COMPARE, look for the use of 6511 the comparison result and try to simplify it unless we already have used 6512 undobuf.other_insn. */ 6513 if ((GET_MODE_CLASS (mode) == MODE_CC 6514 || GET_CODE (src) == COMPARE 6515 || CC0_P (dest)) 6516 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 6517 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) 6518 && COMPARISON_P (*cc_use) 6519 && rtx_equal_p (XEXP (*cc_use, 0), dest)) 6520 { 6521 enum rtx_code old_code = GET_CODE (*cc_use); 6522 enum rtx_code new_code; 6523 rtx op0, op1, tmp; 6524 int other_changed = 0; 6525 rtx inner_compare = NULL_RTX; 6526 machine_mode compare_mode = GET_MODE (dest); 6527 6528 if (GET_CODE (src) == COMPARE) 6529 { 6530 op0 = XEXP (src, 0), op1 = XEXP (src, 1); 6531 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) 6532 { 6533 inner_compare = op0; 6534 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1); 6535 } 6536 } 6537 else 6538 op0 = src, op1 = CONST0_RTX (GET_MODE (src)); 6539 6540 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode, 6541 op0, op1); 6542 if (!tmp) 6543 new_code = old_code; 6544 else if (!CONSTANT_P (tmp)) 6545 { 6546 new_code = GET_CODE (tmp); 6547 op0 = XEXP (tmp, 0); 6548 op1 = XEXP (tmp, 1); 6549 } 6550 else 6551 { 6552 rtx pat = PATTERN (other_insn); 6553 undobuf.other_insn = other_insn; 6554 SUBST (*cc_use, tmp); 6555 6556 /* Attempt to simplify CC user. */ 6557 if (GET_CODE (pat) == SET) 6558 { 6559 rtx new_rtx = simplify_rtx (SET_SRC (pat)); 6560 if (new_rtx != NULL_RTX) 6561 SUBST (SET_SRC (pat), new_rtx); 6562 } 6563 6564 /* Convert X into a no-op move. */ 6565 SUBST (SET_DEST (x), pc_rtx); 6566 SUBST (SET_SRC (x), pc_rtx); 6567 return x; 6568 } 6569 6570 /* Simplify our comparison, if possible. */ 6571 new_code = simplify_comparison (new_code, &op0, &op1); 6572 6573 #ifdef SELECT_CC_MODE 6574 /* If this machine has CC modes other than CCmode, check to see if we 6575 need to use a different CC mode here. */ 6576 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) 6577 compare_mode = GET_MODE (op0); 6578 else if (inner_compare 6579 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC 6580 && new_code == old_code 6581 && op0 == XEXP (inner_compare, 0) 6582 && op1 == XEXP (inner_compare, 1)) 6583 compare_mode = GET_MODE (inner_compare); 6584 else 6585 compare_mode = SELECT_CC_MODE (new_code, op0, op1); 6586 6587 #ifndef HAVE_cc0 6588 /* If the mode changed, we have to change SET_DEST, the mode in the 6589 compare, and the mode in the place SET_DEST is used. If SET_DEST is 6590 a hard register, just build new versions with the proper mode. If it 6591 is a pseudo, we lose unless it is only time we set the pseudo, in 6592 which case we can safely change its mode. */ 6593 if (compare_mode != GET_MODE (dest)) 6594 { 6595 if (can_change_dest_mode (dest, 0, compare_mode)) 6596 { 6597 unsigned int regno = REGNO (dest); 6598 rtx new_dest; 6599 6600 if (regno < FIRST_PSEUDO_REGISTER) 6601 new_dest = gen_rtx_REG (compare_mode, regno); 6602 else 6603 { 6604 SUBST_MODE (regno_reg_rtx[regno], compare_mode); 6605 new_dest = regno_reg_rtx[regno]; 6606 } 6607 6608 SUBST (SET_DEST (x), new_dest); 6609 SUBST (XEXP (*cc_use, 0), new_dest); 6610 other_changed = 1; 6611 6612 dest = new_dest; 6613 } 6614 } 6615 #endif /* cc0 */ 6616 #endif /* SELECT_CC_MODE */ 6617 6618 /* If the code changed, we have to build a new comparison in 6619 undobuf.other_insn. */ 6620 if (new_code != old_code) 6621 { 6622 int other_changed_previously = other_changed; 6623 unsigned HOST_WIDE_INT mask; 6624 rtx old_cc_use = *cc_use; 6625 6626 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), 6627 dest, const0_rtx)); 6628 other_changed = 1; 6629 6630 /* If the only change we made was to change an EQ into an NE or 6631 vice versa, OP0 has only one bit that might be nonzero, and OP1 6632 is zero, check if changing the user of the condition code will 6633 produce a valid insn. If it won't, we can keep the original code 6634 in that insn by surrounding our operation with an XOR. */ 6635 6636 if (((old_code == NE && new_code == EQ) 6637 || (old_code == EQ && new_code == NE)) 6638 && ! other_changed_previously && op1 == const0_rtx 6639 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0)) 6640 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) 6641 { 6642 rtx pat = PATTERN (other_insn), note = 0; 6643 6644 if ((recog_for_combine (&pat, other_insn, ¬e) < 0 6645 && ! check_asm_operands (pat))) 6646 { 6647 *cc_use = old_cc_use; 6648 other_changed = 0; 6649 6650 op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0, 6651 gen_int_mode (mask, 6652 GET_MODE (op0))); 6653 } 6654 } 6655 } 6656 6657 if (other_changed) 6658 undobuf.other_insn = other_insn; 6659 6660 /* Otherwise, if we didn't previously have a COMPARE in the 6661 correct mode, we need one. */ 6662 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) 6663 { 6664 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); 6665 src = SET_SRC (x); 6666 } 6667 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx) 6668 { 6669 SUBST (SET_SRC (x), op0); 6670 src = SET_SRC (x); 6671 } 6672 /* Otherwise, update the COMPARE if needed. */ 6673 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1) 6674 { 6675 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); 6676 src = SET_SRC (x); 6677 } 6678 } 6679 else 6680 { 6681 /* Get SET_SRC in a form where we have placed back any 6682 compound expressions. Then do the checks below. */ 6683 src = make_compound_operation (src, SET); 6684 SUBST (SET_SRC (x), src); 6685 } 6686 6687 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, 6688 and X being a REG or (subreg (reg)), we may be able to convert this to 6689 (set (subreg:m2 x) (op)). 6690 6691 We can always do this if M1 is narrower than M2 because that means that 6692 we only care about the low bits of the result. 6693 6694 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot 6695 perform a narrower operation than requested since the high-order bits will 6696 be undefined. On machine where it is defined, this transformation is safe 6697 as long as M1 and M2 have the same number of words. */ 6698 6699 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 6700 && !OBJECT_P (SUBREG_REG (src)) 6701 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) 6702 / UNITS_PER_WORD) 6703 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) 6704 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) 6705 #ifndef WORD_REGISTER_OPERATIONS 6706 && (GET_MODE_SIZE (GET_MODE (src)) 6707 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 6708 #endif 6709 #ifdef CANNOT_CHANGE_MODE_CLASS 6710 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER 6711 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest), 6712 GET_MODE (SUBREG_REG (src)), 6713 GET_MODE (src))) 6714 #endif 6715 && (REG_P (dest) 6716 || (GET_CODE (dest) == SUBREG 6717 && REG_P (SUBREG_REG (dest))))) 6718 { 6719 SUBST (SET_DEST (x), 6720 gen_lowpart (GET_MODE (SUBREG_REG (src)), 6721 dest)); 6722 SUBST (SET_SRC (x), SUBREG_REG (src)); 6723 6724 src = SET_SRC (x), dest = SET_DEST (x); 6725 } 6726 6727 #ifdef HAVE_cc0 6728 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg 6729 in SRC. */ 6730 if (dest == cc0_rtx 6731 && GET_CODE (src) == SUBREG 6732 && subreg_lowpart_p (src) 6733 && (GET_MODE_PRECISION (GET_MODE (src)) 6734 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src))))) 6735 { 6736 rtx inner = SUBREG_REG (src); 6737 machine_mode inner_mode = GET_MODE (inner); 6738 6739 /* Here we make sure that we don't have a sign bit on. */ 6740 if (val_signbit_known_clear_p (GET_MODE (src), 6741 nonzero_bits (inner, inner_mode))) 6742 { 6743 SUBST (SET_SRC (x), inner); 6744 src = SET_SRC (x); 6745 } 6746 } 6747 #endif 6748 6749 #ifdef LOAD_EXTEND_OP 6750 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this 6751 would require a paradoxical subreg. Replace the subreg with a 6752 zero_extend to avoid the reload that would otherwise be required. */ 6753 6754 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 6755 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src))) 6756 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN 6757 && SUBREG_BYTE (src) == 0 6758 && paradoxical_subreg_p (src) 6759 && MEM_P (SUBREG_REG (src))) 6760 { 6761 SUBST (SET_SRC (x), 6762 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), 6763 GET_MODE (src), SUBREG_REG (src))); 6764 6765 src = SET_SRC (x); 6766 } 6767 #endif 6768 6769 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we 6770 are comparing an item known to be 0 or -1 against 0, use a logical 6771 operation instead. Check for one of the arms being an IOR of the other 6772 arm with some value. We compute three terms to be IOR'ed together. In 6773 practice, at most two will be nonzero. Then we do the IOR's. */ 6774 6775 if (GET_CODE (dest) != PC 6776 && GET_CODE (src) == IF_THEN_ELSE 6777 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT 6778 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) 6779 && XEXP (XEXP (src, 0), 1) == const0_rtx 6780 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) 6781 #ifdef HAVE_conditional_move 6782 && ! can_conditionally_move_p (GET_MODE (src)) 6783 #endif 6784 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), 6785 GET_MODE (XEXP (XEXP (src, 0), 0))) 6786 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0)))) 6787 && ! side_effects_p (src)) 6788 { 6789 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE 6790 ? XEXP (src, 1) : XEXP (src, 2)); 6791 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE 6792 ? XEXP (src, 2) : XEXP (src, 1)); 6793 rtx term1 = const0_rtx, term2, term3; 6794 6795 if (GET_CODE (true_rtx) == IOR 6796 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) 6797 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx; 6798 else if (GET_CODE (true_rtx) == IOR 6799 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) 6800 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx; 6801 else if (GET_CODE (false_rtx) == IOR 6802 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) 6803 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx; 6804 else if (GET_CODE (false_rtx) == IOR 6805 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) 6806 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx; 6807 6808 term2 = simplify_gen_binary (AND, GET_MODE (src), 6809 XEXP (XEXP (src, 0), 0), true_rtx); 6810 term3 = simplify_gen_binary (AND, GET_MODE (src), 6811 simplify_gen_unary (NOT, GET_MODE (src), 6812 XEXP (XEXP (src, 0), 0), 6813 GET_MODE (src)), 6814 false_rtx); 6815 6816 SUBST (SET_SRC (x), 6817 simplify_gen_binary (IOR, GET_MODE (src), 6818 simplify_gen_binary (IOR, GET_MODE (src), 6819 term1, term2), 6820 term3)); 6821 6822 src = SET_SRC (x); 6823 } 6824 6825 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this 6826 whole thing fail. */ 6827 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) 6828 return src; 6829 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) 6830 return dest; 6831 else 6832 /* Convert this into a field assignment operation, if possible. */ 6833 return make_field_assignment (x); 6834 } 6835 6836 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified 6837 result. */ 6838 6839 static rtx 6840 simplify_logical (rtx x) 6841 { 6842 machine_mode mode = GET_MODE (x); 6843 rtx op0 = XEXP (x, 0); 6844 rtx op1 = XEXP (x, 1); 6845 6846 switch (GET_CODE (x)) 6847 { 6848 case AND: 6849 /* We can call simplify_and_const_int only if we don't lose 6850 any (sign) bits when converting INTVAL (op1) to 6851 "unsigned HOST_WIDE_INT". */ 6852 if (CONST_INT_P (op1) 6853 && (HWI_COMPUTABLE_MODE_P (mode) 6854 || INTVAL (op1) > 0)) 6855 { 6856 x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); 6857 if (GET_CODE (x) != AND) 6858 return x; 6859 6860 op0 = XEXP (x, 0); 6861 op1 = XEXP (x, 1); 6862 } 6863 6864 /* If we have any of (and (ior A B) C) or (and (xor A B) C), 6865 apply the distributive law and then the inverse distributive 6866 law to see if things simplify. */ 6867 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) 6868 { 6869 rtx result = distribute_and_simplify_rtx (x, 0); 6870 if (result) 6871 return result; 6872 } 6873 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) 6874 { 6875 rtx result = distribute_and_simplify_rtx (x, 1); 6876 if (result) 6877 return result; 6878 } 6879 break; 6880 6881 case IOR: 6882 /* If we have (ior (and A B) C), apply the distributive law and then 6883 the inverse distributive law to see if things simplify. */ 6884 6885 if (GET_CODE (op0) == AND) 6886 { 6887 rtx result = distribute_and_simplify_rtx (x, 0); 6888 if (result) 6889 return result; 6890 } 6891 6892 if (GET_CODE (op1) == AND) 6893 { 6894 rtx result = distribute_and_simplify_rtx (x, 1); 6895 if (result) 6896 return result; 6897 } 6898 break; 6899 6900 default: 6901 gcc_unreachable (); 6902 } 6903 6904 return x; 6905 } 6906 6907 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound 6908 operations" because they can be replaced with two more basic operations. 6909 ZERO_EXTEND is also considered "compound" because it can be replaced with 6910 an AND operation, which is simpler, though only one operation. 6911 6912 The function expand_compound_operation is called with an rtx expression 6913 and will convert it to the appropriate shifts and AND operations, 6914 simplifying at each stage. 6915 6916 The function make_compound_operation is called to convert an expression 6917 consisting of shifts and ANDs into the equivalent compound expression. 6918 It is the inverse of this function, loosely speaking. */ 6919 6920 static rtx 6921 expand_compound_operation (rtx x) 6922 { 6923 unsigned HOST_WIDE_INT pos = 0, len; 6924 int unsignedp = 0; 6925 unsigned int modewidth; 6926 rtx tem; 6927 6928 switch (GET_CODE (x)) 6929 { 6930 case ZERO_EXTEND: 6931 unsignedp = 1; 6932 case SIGN_EXTEND: 6933 /* We can't necessarily use a const_int for a multiword mode; 6934 it depends on implicitly extending the value. 6935 Since we don't know the right way to extend it, 6936 we can't tell whether the implicit way is right. 6937 6938 Even for a mode that is no wider than a const_int, 6939 we can't win, because we need to sign extend one of its bits through 6940 the rest of it, and we don't know which bit. */ 6941 if (CONST_INT_P (XEXP (x, 0))) 6942 return x; 6943 6944 /* Return if (subreg:MODE FROM 0) is not a safe replacement for 6945 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM 6946 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be 6947 reloaded. If not for that, MEM's would very rarely be safe. 6948 6949 Reject MODEs bigger than a word, because we might not be able 6950 to reference a two-register group starting with an arbitrary register 6951 (and currently gen_lowpart might crash for a SUBREG). */ 6952 6953 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) 6954 return x; 6955 6956 /* Reject MODEs that aren't scalar integers because turning vector 6957 or complex modes into shifts causes problems. */ 6958 6959 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) 6960 return x; 6961 6962 len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))); 6963 /* If the inner object has VOIDmode (the only way this can happen 6964 is if it is an ASM_OPERANDS), we can't do anything since we don't 6965 know how much masking to do. */ 6966 if (len == 0) 6967 return x; 6968 6969 break; 6970 6971 case ZERO_EXTRACT: 6972 unsignedp = 1; 6973 6974 /* ... fall through ... */ 6975 6976 case SIGN_EXTRACT: 6977 /* If the operand is a CLOBBER, just return it. */ 6978 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 6979 return XEXP (x, 0); 6980 6981 if (!CONST_INT_P (XEXP (x, 1)) 6982 || !CONST_INT_P (XEXP (x, 2)) 6983 || GET_MODE (XEXP (x, 0)) == VOIDmode) 6984 return x; 6985 6986 /* Reject MODEs that aren't scalar integers because turning vector 6987 or complex modes into shifts causes problems. */ 6988 6989 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) 6990 return x; 6991 6992 len = INTVAL (XEXP (x, 1)); 6993 pos = INTVAL (XEXP (x, 2)); 6994 6995 /* This should stay within the object being extracted, fail otherwise. */ 6996 if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))) 6997 return x; 6998 6999 if (BITS_BIG_ENDIAN) 7000 pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos; 7001 7002 break; 7003 7004 default: 7005 return x; 7006 } 7007 /* Convert sign extension to zero extension, if we know that the high 7008 bit is not set, as this is easier to optimize. It will be converted 7009 back to cheaper alternative in make_extraction. */ 7010 if (GET_CODE (x) == SIGN_EXTEND 7011 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x)) 7012 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 7013 & ~(((unsigned HOST_WIDE_INT) 7014 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) 7015 >> 1)) 7016 == 0))) 7017 { 7018 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0)); 7019 rtx temp2 = expand_compound_operation (temp); 7020 7021 /* Make sure this is a profitable operation. */ 7022 if (set_src_cost (x, optimize_this_for_speed_p) 7023 > set_src_cost (temp2, optimize_this_for_speed_p)) 7024 return temp2; 7025 else if (set_src_cost (x, optimize_this_for_speed_p) 7026 > set_src_cost (temp, optimize_this_for_speed_p)) 7027 return temp; 7028 else 7029 return x; 7030 } 7031 7032 /* We can optimize some special cases of ZERO_EXTEND. */ 7033 if (GET_CODE (x) == ZERO_EXTEND) 7034 { 7035 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we 7036 know that the last value didn't have any inappropriate bits 7037 set. */ 7038 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 7039 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 7040 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)) 7041 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) 7042 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 7043 return XEXP (XEXP (x, 0), 0); 7044 7045 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 7046 if (GET_CODE (XEXP (x, 0)) == SUBREG 7047 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 7048 && subreg_lowpart_p (XEXP (x, 0)) 7049 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)) 7050 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) 7051 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 7052 return SUBREG_REG (XEXP (x, 0)); 7053 7054 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo 7055 is a comparison and STORE_FLAG_VALUE permits. This is like 7056 the first case, but it works even when GET_MODE (x) is larger 7057 than HOST_WIDE_INT. */ 7058 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 7059 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 7060 && COMPARISON_P (XEXP (XEXP (x, 0), 0)) 7061 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) 7062 <= HOST_BITS_PER_WIDE_INT) 7063 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 7064 return XEXP (XEXP (x, 0), 0); 7065 7066 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 7067 if (GET_CODE (XEXP (x, 0)) == SUBREG 7068 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 7069 && subreg_lowpart_p (XEXP (x, 0)) 7070 && COMPARISON_P (SUBREG_REG (XEXP (x, 0))) 7071 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) 7072 <= HOST_BITS_PER_WIDE_INT) 7073 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 7074 return SUBREG_REG (XEXP (x, 0)); 7075 7076 } 7077 7078 /* If we reach here, we want to return a pair of shifts. The inner 7079 shift is a left shift of BITSIZE - POS - LEN bits. The outer 7080 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or 7081 logical depending on the value of UNSIGNEDP. 7082 7083 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be 7084 converted into an AND of a shift. 7085 7086 We must check for the case where the left shift would have a negative 7087 count. This can happen in a case like (x >> 31) & 255 on machines 7088 that can't shift by a constant. On those machines, we would first 7089 combine the shift with the AND to produce a variable-position 7090 extraction. Then the constant of 31 would be substituted in 7091 to produce such a position. */ 7092 7093 modewidth = GET_MODE_PRECISION (GET_MODE (x)); 7094 if (modewidth >= pos + len) 7095 { 7096 machine_mode mode = GET_MODE (x); 7097 tem = gen_lowpart (mode, XEXP (x, 0)); 7098 if (!tem || GET_CODE (tem) == CLOBBER) 7099 return x; 7100 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode, 7101 tem, modewidth - pos - len); 7102 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, 7103 mode, tem, modewidth - len); 7104 } 7105 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) 7106 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), 7107 simplify_shift_const (NULL_RTX, LSHIFTRT, 7108 GET_MODE (x), 7109 XEXP (x, 0), pos), 7110 ((unsigned HOST_WIDE_INT) 1 << len) - 1); 7111 else 7112 /* Any other cases we can't handle. */ 7113 return x; 7114 7115 /* If we couldn't do this for some reason, return the original 7116 expression. */ 7117 if (GET_CODE (tem) == CLOBBER) 7118 return x; 7119 7120 return tem; 7121 } 7122 7123 /* X is a SET which contains an assignment of one object into 7124 a part of another (such as a bit-field assignment, STRICT_LOW_PART, 7125 or certain SUBREGS). If possible, convert it into a series of 7126 logical operations. 7127 7128 We half-heartedly support variable positions, but do not at all 7129 support variable lengths. */ 7130 7131 static const_rtx 7132 expand_field_assignment (const_rtx x) 7133 { 7134 rtx inner; 7135 rtx pos; /* Always counts from low bit. */ 7136 int len; 7137 rtx mask, cleared, masked; 7138 machine_mode compute_mode; 7139 7140 /* Loop until we find something we can't simplify. */ 7141 while (1) 7142 { 7143 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART 7144 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) 7145 { 7146 inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); 7147 len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))); 7148 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); 7149 } 7150 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 7151 && CONST_INT_P (XEXP (SET_DEST (x), 1))) 7152 { 7153 inner = XEXP (SET_DEST (x), 0); 7154 len = INTVAL (XEXP (SET_DEST (x), 1)); 7155 pos = XEXP (SET_DEST (x), 2); 7156 7157 /* A constant position should stay within the width of INNER. */ 7158 if (CONST_INT_P (pos) 7159 && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner))) 7160 break; 7161 7162 if (BITS_BIG_ENDIAN) 7163 { 7164 if (CONST_INT_P (pos)) 7165 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len 7166 - INTVAL (pos)); 7167 else if (GET_CODE (pos) == MINUS 7168 && CONST_INT_P (XEXP (pos, 1)) 7169 && (INTVAL (XEXP (pos, 1)) 7170 == GET_MODE_PRECISION (GET_MODE (inner)) - len)) 7171 /* If position is ADJUST - X, new position is X. */ 7172 pos = XEXP (pos, 0); 7173 else 7174 { 7175 HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner)); 7176 pos = simplify_gen_binary (MINUS, GET_MODE (pos), 7177 gen_int_mode (prec - len, 7178 GET_MODE (pos)), 7179 pos); 7180 } 7181 } 7182 } 7183 7184 /* A SUBREG between two modes that occupy the same numbers of words 7185 can be done by moving the SUBREG to the source. */ 7186 else if (GET_CODE (SET_DEST (x)) == SUBREG 7187 /* We need SUBREGs to compute nonzero_bits properly. */ 7188 && nonzero_sign_valid 7189 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 7190 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 7191 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 7192 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) 7193 { 7194 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), 7195 gen_lowpart 7196 (GET_MODE (SUBREG_REG (SET_DEST (x))), 7197 SET_SRC (x))); 7198 continue; 7199 } 7200 else 7201 break; 7202 7203 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 7204 inner = SUBREG_REG (inner); 7205 7206 compute_mode = GET_MODE (inner); 7207 7208 /* Don't attempt bitwise arithmetic on non scalar integer modes. */ 7209 if (! SCALAR_INT_MODE_P (compute_mode)) 7210 { 7211 machine_mode imode; 7212 7213 /* Don't do anything for vector or complex integral types. */ 7214 if (! FLOAT_MODE_P (compute_mode)) 7215 break; 7216 7217 /* Try to find an integral mode to pun with. */ 7218 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); 7219 if (imode == BLKmode) 7220 break; 7221 7222 compute_mode = imode; 7223 inner = gen_lowpart (imode, inner); 7224 } 7225 7226 /* Compute a mask of LEN bits, if we can do this on the host machine. */ 7227 if (len >= HOST_BITS_PER_WIDE_INT) 7228 break; 7229 7230 /* Don't try to compute in too wide unsupported modes. */ 7231 if (!targetm.scalar_mode_supported_p (compute_mode)) 7232 break; 7233 7234 /* Now compute the equivalent expression. Make a copy of INNER 7235 for the SET_DEST in case it is a MEM into which we will substitute; 7236 we don't want shared RTL in that case. */ 7237 mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1, 7238 compute_mode); 7239 cleared = simplify_gen_binary (AND, compute_mode, 7240 simplify_gen_unary (NOT, compute_mode, 7241 simplify_gen_binary (ASHIFT, 7242 compute_mode, 7243 mask, pos), 7244 compute_mode), 7245 inner); 7246 masked = simplify_gen_binary (ASHIFT, compute_mode, 7247 simplify_gen_binary ( 7248 AND, compute_mode, 7249 gen_lowpart (compute_mode, SET_SRC (x)), 7250 mask), 7251 pos); 7252 7253 x = gen_rtx_SET (VOIDmode, copy_rtx (inner), 7254 simplify_gen_binary (IOR, compute_mode, 7255 cleared, masked)); 7256 } 7257 7258 return x; 7259 } 7260 7261 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, 7262 it is an RTX that represents the (variable) starting position; otherwise, 7263 POS is the (constant) starting bit position. Both are counted from the LSB. 7264 7265 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one. 7266 7267 IN_DEST is nonzero if this is a reference in the destination of a SET. 7268 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, 7269 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will 7270 be used. 7271 7272 IN_COMPARE is nonzero if we are in a COMPARE. This means that a 7273 ZERO_EXTRACT should be built even for bits starting at bit 0. 7274 7275 MODE is the desired mode of the result (if IN_DEST == 0). 7276 7277 The result is an RTX for the extraction or NULL_RTX if the target 7278 can't handle it. */ 7279 7280 static rtx 7281 make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos, 7282 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp, 7283 int in_dest, int in_compare) 7284 { 7285 /* This mode describes the size of the storage area 7286 to fetch the overall value from. Within that, we 7287 ignore the POS lowest bits, etc. */ 7288 machine_mode is_mode = GET_MODE (inner); 7289 machine_mode inner_mode; 7290 machine_mode wanted_inner_mode; 7291 machine_mode wanted_inner_reg_mode = word_mode; 7292 machine_mode pos_mode = word_mode; 7293 machine_mode extraction_mode = word_mode; 7294 machine_mode tmode = mode_for_size (len, MODE_INT, 1); 7295 rtx new_rtx = 0; 7296 rtx orig_pos_rtx = pos_rtx; 7297 HOST_WIDE_INT orig_pos; 7298 7299 if (pos_rtx && CONST_INT_P (pos_rtx)) 7300 pos = INTVAL (pos_rtx), pos_rtx = 0; 7301 7302 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 7303 { 7304 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), 7305 consider just the QI as the memory to extract from. 7306 The subreg adds or removes high bits; its mode is 7307 irrelevant to the meaning of this extraction, 7308 since POS and LEN count from the lsb. */ 7309 if (MEM_P (SUBREG_REG (inner))) 7310 is_mode = GET_MODE (SUBREG_REG (inner)); 7311 inner = SUBREG_REG (inner); 7312 } 7313 else if (GET_CODE (inner) == ASHIFT 7314 && CONST_INT_P (XEXP (inner, 1)) 7315 && pos_rtx == 0 && pos == 0 7316 && len > UINTVAL (XEXP (inner, 1))) 7317 { 7318 /* We're extracting the least significant bits of an rtx 7319 (ashift X (const_int C)), where LEN > C. Extract the 7320 least significant (LEN - C) bits of X, giving an rtx 7321 whose mode is MODE, then shift it left C times. */ 7322 new_rtx = make_extraction (mode, XEXP (inner, 0), 7323 0, 0, len - INTVAL (XEXP (inner, 1)), 7324 unsignedp, in_dest, in_compare); 7325 if (new_rtx != 0) 7326 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1)); 7327 } 7328 else if (GET_CODE (inner) == TRUNCATE) 7329 inner = XEXP (inner, 0); 7330 7331 inner_mode = GET_MODE (inner); 7332 7333 /* See if this can be done without an extraction. We never can if the 7334 width of the field is not the same as that of some integer mode. For 7335 registers, we can only avoid the extraction if the position is at the 7336 low-order bit and this is either not in the destination or we have the 7337 appropriate STRICT_LOW_PART operation available. 7338 7339 For MEM, we can avoid an extract if the field starts on an appropriate 7340 boundary and we can change the mode of the memory reference. */ 7341 7342 if (tmode != BLKmode 7343 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 7344 && !MEM_P (inner) 7345 && (pos == 0 || REG_P (inner)) 7346 && (inner_mode == tmode 7347 || !REG_P (inner) 7348 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode) 7349 || reg_truncated_to_mode (tmode, inner)) 7350 && (! in_dest 7351 || (REG_P (inner) 7352 && have_insn_for (STRICT_LOW_PART, tmode)))) 7353 || (MEM_P (inner) && pos_rtx == 0 7354 && (pos 7355 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) 7356 : BITS_PER_UNIT)) == 0 7357 /* We can't do this if we are widening INNER_MODE (it 7358 may not be aligned, for one thing). */ 7359 && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode) 7360 && (inner_mode == tmode 7361 || (! mode_dependent_address_p (XEXP (inner, 0), 7362 MEM_ADDR_SPACE (inner)) 7363 && ! MEM_VOLATILE_P (inner)))))) 7364 { 7365 /* If INNER is a MEM, make a new MEM that encompasses just the desired 7366 field. If the original and current mode are the same, we need not 7367 adjust the offset. Otherwise, we do if bytes big endian. 7368 7369 If INNER is not a MEM, get a piece consisting of just the field 7370 of interest (in this case POS % BITS_PER_WORD must be 0). */ 7371 7372 if (MEM_P (inner)) 7373 { 7374 HOST_WIDE_INT offset; 7375 7376 /* POS counts from lsb, but make OFFSET count in memory order. */ 7377 if (BYTES_BIG_ENDIAN) 7378 offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT; 7379 else 7380 offset = pos / BITS_PER_UNIT; 7381 7382 new_rtx = adjust_address_nv (inner, tmode, offset); 7383 } 7384 else if (REG_P (inner)) 7385 { 7386 if (tmode != inner_mode) 7387 { 7388 /* We can't call gen_lowpart in a DEST since we 7389 always want a SUBREG (see below) and it would sometimes 7390 return a new hard register. */ 7391 if (pos || in_dest) 7392 { 7393 HOST_WIDE_INT final_word = pos / BITS_PER_WORD; 7394 7395 if (WORDS_BIG_ENDIAN 7396 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) 7397 final_word = ((GET_MODE_SIZE (inner_mode) 7398 - GET_MODE_SIZE (tmode)) 7399 / UNITS_PER_WORD) - final_word; 7400 7401 final_word *= UNITS_PER_WORD; 7402 if (BYTES_BIG_ENDIAN && 7403 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) 7404 final_word += (GET_MODE_SIZE (inner_mode) 7405 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; 7406 7407 /* Avoid creating invalid subregs, for example when 7408 simplifying (x>>32)&255. */ 7409 if (!validate_subreg (tmode, inner_mode, inner, final_word)) 7410 return NULL_RTX; 7411 7412 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word); 7413 } 7414 else 7415 new_rtx = gen_lowpart (tmode, inner); 7416 } 7417 else 7418 new_rtx = inner; 7419 } 7420 else 7421 new_rtx = force_to_mode (inner, tmode, 7422 len >= HOST_BITS_PER_WIDE_INT 7423 ? ~(unsigned HOST_WIDE_INT) 0 7424 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, 0); 7425 7426 /* If this extraction is going into the destination of a SET, 7427 make a STRICT_LOW_PART unless we made a MEM. */ 7428 7429 if (in_dest) 7430 return (MEM_P (new_rtx) ? new_rtx 7431 : (GET_CODE (new_rtx) != SUBREG 7432 ? gen_rtx_CLOBBER (tmode, const0_rtx) 7433 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx))); 7434 7435 if (mode == tmode) 7436 return new_rtx; 7437 7438 if (CONST_SCALAR_INT_P (new_rtx)) 7439 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 7440 mode, new_rtx, tmode); 7441 7442 /* If we know that no extraneous bits are set, and that the high 7443 bit is not set, convert the extraction to the cheaper of 7444 sign and zero extension, that are equivalent in these cases. */ 7445 if (flag_expensive_optimizations 7446 && (HWI_COMPUTABLE_MODE_P (tmode) 7447 && ((nonzero_bits (new_rtx, tmode) 7448 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1)) 7449 == 0))) 7450 { 7451 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx); 7452 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx); 7453 7454 /* Prefer ZERO_EXTENSION, since it gives more information to 7455 backends. */ 7456 if (set_src_cost (temp, optimize_this_for_speed_p) 7457 <= set_src_cost (temp1, optimize_this_for_speed_p)) 7458 return temp; 7459 return temp1; 7460 } 7461 7462 /* Otherwise, sign- or zero-extend unless we already are in the 7463 proper mode. */ 7464 7465 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 7466 mode, new_rtx)); 7467 } 7468 7469 /* Unless this is a COMPARE or we have a funny memory reference, 7470 don't do anything with zero-extending field extracts starting at 7471 the low-order bit since they are simple AND operations. */ 7472 if (pos_rtx == 0 && pos == 0 && ! in_dest 7473 && ! in_compare && unsignedp) 7474 return 0; 7475 7476 /* Unless INNER is not MEM, reject this if we would be spanning bytes or 7477 if the position is not a constant and the length is not 1. In all 7478 other cases, we would only be going outside our object in cases when 7479 an original shift would have been undefined. */ 7480 if (MEM_P (inner) 7481 && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode)) 7482 || (pos_rtx != 0 && len != 1))) 7483 return 0; 7484 7485 enum extraction_pattern pattern = (in_dest ? EP_insv 7486 : unsignedp ? EP_extzv : EP_extv); 7487 7488 /* If INNER is not from memory, we want it to have the mode of a register 7489 extraction pattern's structure operand, or word_mode if there is no 7490 such pattern. The same applies to extraction_mode and pos_mode 7491 and their respective operands. 7492 7493 For memory, assume that the desired extraction_mode and pos_mode 7494 are the same as for a register operation, since at present we don't 7495 have named patterns for aligned memory structures. */ 7496 struct extraction_insn insn; 7497 if (get_best_reg_extraction_insn (&insn, pattern, 7498 GET_MODE_BITSIZE (inner_mode), mode)) 7499 { 7500 wanted_inner_reg_mode = insn.struct_mode; 7501 pos_mode = insn.pos_mode; 7502 extraction_mode = insn.field_mode; 7503 } 7504 7505 /* Never narrow an object, since that might not be safe. */ 7506 7507 if (mode != VOIDmode 7508 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) 7509 extraction_mode = mode; 7510 7511 if (!MEM_P (inner)) 7512 wanted_inner_mode = wanted_inner_reg_mode; 7513 else 7514 { 7515 /* Be careful not to go beyond the extracted object and maintain the 7516 natural alignment of the memory. */ 7517 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT); 7518 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len 7519 > GET_MODE_BITSIZE (wanted_inner_mode)) 7520 { 7521 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode); 7522 gcc_assert (wanted_inner_mode != VOIDmode); 7523 } 7524 } 7525 7526 orig_pos = pos; 7527 7528 if (BITS_BIG_ENDIAN) 7529 { 7530 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to 7531 BITS_BIG_ENDIAN style. If position is constant, compute new 7532 position. Otherwise, build subtraction. 7533 Note that POS is relative to the mode of the original argument. 7534 If it's a MEM we need to recompute POS relative to that. 7535 However, if we're extracting from (or inserting into) a register, 7536 we want to recompute POS relative to wanted_inner_mode. */ 7537 int width = (MEM_P (inner) 7538 ? GET_MODE_BITSIZE (is_mode) 7539 : GET_MODE_BITSIZE (wanted_inner_mode)); 7540 7541 if (pos_rtx == 0) 7542 pos = width - len - pos; 7543 else 7544 pos_rtx 7545 = gen_rtx_MINUS (GET_MODE (pos_rtx), 7546 gen_int_mode (width - len, GET_MODE (pos_rtx)), 7547 pos_rtx); 7548 /* POS may be less than 0 now, but we check for that below. 7549 Note that it can only be less than 0 if !MEM_P (inner). */ 7550 } 7551 7552 /* If INNER has a wider mode, and this is a constant extraction, try to 7553 make it smaller and adjust the byte to point to the byte containing 7554 the value. */ 7555 if (wanted_inner_mode != VOIDmode 7556 && inner_mode != wanted_inner_mode 7557 && ! pos_rtx 7558 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) 7559 && MEM_P (inner) 7560 && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner)) 7561 && ! MEM_VOLATILE_P (inner)) 7562 { 7563 int offset = 0; 7564 7565 /* The computations below will be correct if the machine is big 7566 endian in both bits and bytes or little endian in bits and bytes. 7567 If it is mixed, we must adjust. */ 7568 7569 /* If bytes are big endian and we had a paradoxical SUBREG, we must 7570 adjust OFFSET to compensate. */ 7571 if (BYTES_BIG_ENDIAN 7572 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) 7573 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); 7574 7575 /* We can now move to the desired byte. */ 7576 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode)) 7577 * GET_MODE_SIZE (wanted_inner_mode); 7578 pos %= GET_MODE_BITSIZE (wanted_inner_mode); 7579 7580 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN 7581 && is_mode != wanted_inner_mode) 7582 offset = (GET_MODE_SIZE (is_mode) 7583 - GET_MODE_SIZE (wanted_inner_mode) - offset); 7584 7585 inner = adjust_address_nv (inner, wanted_inner_mode, offset); 7586 } 7587 7588 /* If INNER is not memory, get it into the proper mode. If we are changing 7589 its mode, POS must be a constant and smaller than the size of the new 7590 mode. */ 7591 else if (!MEM_P (inner)) 7592 { 7593 /* On the LHS, don't create paradoxical subregs implicitely truncating 7594 the register unless TRULY_NOOP_TRUNCATION. */ 7595 if (in_dest 7596 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner), 7597 wanted_inner_mode)) 7598 return NULL_RTX; 7599 7600 if (GET_MODE (inner) != wanted_inner_mode 7601 && (pos_rtx != 0 7602 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) 7603 return NULL_RTX; 7604 7605 if (orig_pos < 0) 7606 return NULL_RTX; 7607 7608 inner = force_to_mode (inner, wanted_inner_mode, 7609 pos_rtx 7610 || len + orig_pos >= HOST_BITS_PER_WIDE_INT 7611 ? ~(unsigned HOST_WIDE_INT) 0 7612 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1) 7613 << orig_pos), 7614 0); 7615 } 7616 7617 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we 7618 have to zero extend. Otherwise, we can just use a SUBREG. */ 7619 if (pos_rtx != 0 7620 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) 7621 { 7622 rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx, 7623 GET_MODE (pos_rtx)); 7624 7625 /* If we know that no extraneous bits are set, and that the high 7626 bit is not set, convert extraction to cheaper one - either 7627 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these 7628 cases. */ 7629 if (flag_expensive_optimizations 7630 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx)) 7631 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) 7632 & ~(((unsigned HOST_WIDE_INT) 7633 GET_MODE_MASK (GET_MODE (pos_rtx))) 7634 >> 1)) 7635 == 0))) 7636 { 7637 rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx, 7638 GET_MODE (pos_rtx)); 7639 7640 /* Prefer ZERO_EXTENSION, since it gives more information to 7641 backends. */ 7642 if (set_src_cost (temp1, optimize_this_for_speed_p) 7643 < set_src_cost (temp, optimize_this_for_speed_p)) 7644 temp = temp1; 7645 } 7646 pos_rtx = temp; 7647 } 7648 7649 /* Make POS_RTX unless we already have it and it is correct. If we don't 7650 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must 7651 be a CONST_INT. */ 7652 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) 7653 pos_rtx = orig_pos_rtx; 7654 7655 else if (pos_rtx == 0) 7656 pos_rtx = GEN_INT (pos); 7657 7658 /* Make the required operation. See if we can use existing rtx. */ 7659 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, 7660 extraction_mode, inner, GEN_INT (len), pos_rtx); 7661 if (! in_dest) 7662 new_rtx = gen_lowpart (mode, new_rtx); 7663 7664 return new_rtx; 7665 } 7666 7667 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted 7668 with any other operations in X. Return X without that shift if so. */ 7669 7670 static rtx 7671 extract_left_shift (rtx x, int count) 7672 { 7673 enum rtx_code code = GET_CODE (x); 7674 machine_mode mode = GET_MODE (x); 7675 rtx tem; 7676 7677 switch (code) 7678 { 7679 case ASHIFT: 7680 /* This is the shift itself. If it is wide enough, we will return 7681 either the value being shifted if the shift count is equal to 7682 COUNT or a shift for the difference. */ 7683 if (CONST_INT_P (XEXP (x, 1)) 7684 && INTVAL (XEXP (x, 1)) >= count) 7685 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), 7686 INTVAL (XEXP (x, 1)) - count); 7687 break; 7688 7689 case NEG: case NOT: 7690 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) 7691 return simplify_gen_unary (code, mode, tem, mode); 7692 7693 break; 7694 7695 case PLUS: case IOR: case XOR: case AND: 7696 /* If we can safely shift this constant and we find the inner shift, 7697 make a new operation. */ 7698 if (CONST_INT_P (XEXP (x, 1)) 7699 && (UINTVAL (XEXP (x, 1)) 7700 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0 7701 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) 7702 { 7703 HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count; 7704 return simplify_gen_binary (code, mode, tem, 7705 gen_int_mode (val, mode)); 7706 } 7707 break; 7708 7709 default: 7710 break; 7711 } 7712 7713 return 0; 7714 } 7715 7716 /* Look at the expression rooted at X. Look for expressions 7717 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. 7718 Form these expressions. 7719 7720 Return the new rtx, usually just X. 7721 7722 Also, for machines like the VAX that don't have logical shift insns, 7723 try to convert logical to arithmetic shift operations in cases where 7724 they are equivalent. This undoes the canonicalizations to logical 7725 shifts done elsewhere. 7726 7727 We try, as much as possible, to re-use rtl expressions to save memory. 7728 7729 IN_CODE says what kind of expression we are processing. Normally, 7730 it is SET. In a memory address (inside a MEM, PLUS or minus, the 7731 latter two being kludges), it is MEM. When processing the 7732 arguments of a comparison or a COMPARE against zero, it is COMPARE, 7733 or EQ if more + precisely it is an equality comparison against 7734 zero.. */ 7735 7736 rtx 7737 make_compound_operation (rtx x, enum rtx_code in_code) 7738 { 7739 enum rtx_code code = GET_CODE (x); 7740 machine_mode mode = GET_MODE (x); 7741 int mode_width = GET_MODE_PRECISION (mode); 7742 rtx rhs, lhs; 7743 enum rtx_code next_code; 7744 int i, j; 7745 rtx new_rtx = 0; 7746 rtx tem; 7747 const char *fmt; 7748 bool equality_comparison = false; 7749 7750 /* Select the code to be used in recursive calls. Once we are inside an 7751 address, we stay there. If we have a comparison, set to COMPARE, 7752 but once inside, go back to our default of SET. */ 7753 7754 if (in_code == EQ) 7755 { 7756 equality_comparison = true; 7757 in_code = COMPARE; 7758 } 7759 next_code = (code == MEM ? MEM 7760 : ((code == PLUS || code == MINUS) 7761 && SCALAR_INT_MODE_P (mode)) ? MEM 7762 : ((code == COMPARE || COMPARISON_P (x)) 7763 && XEXP (x, 1) == const0_rtx) ? COMPARE 7764 : in_code == COMPARE ? SET : in_code); 7765 7766 /* Process depending on the code of this operation. If NEW is set 7767 nonzero, it will be returned. */ 7768 7769 switch (code) 7770 { 7771 case ASHIFT: 7772 /* Convert shifts by constants into multiplications if inside 7773 an address. */ 7774 if (in_code == MEM && CONST_INT_P (XEXP (x, 1)) 7775 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 7776 && INTVAL (XEXP (x, 1)) >= 0 7777 && SCALAR_INT_MODE_P (mode)) 7778 { 7779 HOST_WIDE_INT count = INTVAL (XEXP (x, 1)); 7780 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count; 7781 7782 new_rtx = make_compound_operation (XEXP (x, 0), next_code); 7783 if (GET_CODE (new_rtx) == NEG) 7784 { 7785 new_rtx = XEXP (new_rtx, 0); 7786 multval = -multval; 7787 } 7788 multval = trunc_int_for_mode (multval, mode); 7789 new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode)); 7790 } 7791 break; 7792 7793 case PLUS: 7794 lhs = XEXP (x, 0); 7795 rhs = XEXP (x, 1); 7796 lhs = make_compound_operation (lhs, next_code); 7797 rhs = make_compound_operation (rhs, next_code); 7798 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG 7799 && SCALAR_INT_MODE_P (mode)) 7800 { 7801 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0), 7802 XEXP (lhs, 1)); 7803 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem); 7804 } 7805 else if (GET_CODE (lhs) == MULT 7806 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0)) 7807 { 7808 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0), 7809 simplify_gen_unary (NEG, mode, 7810 XEXP (lhs, 1), 7811 mode)); 7812 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem); 7813 } 7814 else 7815 { 7816 SUBST (XEXP (x, 0), lhs); 7817 SUBST (XEXP (x, 1), rhs); 7818 goto maybe_swap; 7819 } 7820 x = gen_lowpart (mode, new_rtx); 7821 goto maybe_swap; 7822 7823 case MINUS: 7824 lhs = XEXP (x, 0); 7825 rhs = XEXP (x, 1); 7826 lhs = make_compound_operation (lhs, next_code); 7827 rhs = make_compound_operation (rhs, next_code); 7828 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG 7829 && SCALAR_INT_MODE_P (mode)) 7830 { 7831 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0), 7832 XEXP (rhs, 1)); 7833 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs); 7834 } 7835 else if (GET_CODE (rhs) == MULT 7836 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0)) 7837 { 7838 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0), 7839 simplify_gen_unary (NEG, mode, 7840 XEXP (rhs, 1), 7841 mode)); 7842 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs); 7843 } 7844 else 7845 { 7846 SUBST (XEXP (x, 0), lhs); 7847 SUBST (XEXP (x, 1), rhs); 7848 return x; 7849 } 7850 return gen_lowpart (mode, new_rtx); 7851 7852 case AND: 7853 /* If the second operand is not a constant, we can't do anything 7854 with it. */ 7855 if (!CONST_INT_P (XEXP (x, 1))) 7856 break; 7857 7858 /* If the constant is a power of two minus one and the first operand 7859 is a logical right shift, make an extraction. */ 7860 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 7861 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 7862 { 7863 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 7864 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1, 7865 0, in_code == COMPARE); 7866 } 7867 7868 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ 7869 else if (GET_CODE (XEXP (x, 0)) == SUBREG 7870 && subreg_lowpart_p (XEXP (x, 0)) 7871 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT 7872 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 7873 { 7874 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), 7875 next_code); 7876 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0, 7877 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, 7878 0, in_code == COMPARE); 7879 } 7880 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ 7881 else if ((GET_CODE (XEXP (x, 0)) == XOR 7882 || GET_CODE (XEXP (x, 0)) == IOR) 7883 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT 7884 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT 7885 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 7886 { 7887 /* Apply the distributive law, and then try to make extractions. */ 7888 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, 7889 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), 7890 XEXP (x, 1)), 7891 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), 7892 XEXP (x, 1))); 7893 new_rtx = make_compound_operation (new_rtx, in_code); 7894 } 7895 7896 /* If we are have (and (rotate X C) M) and C is larger than the number 7897 of bits in M, this is an extraction. */ 7898 7899 else if (GET_CODE (XEXP (x, 0)) == ROTATE 7900 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 7901 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0 7902 && i <= INTVAL (XEXP (XEXP (x, 0), 1))) 7903 { 7904 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 7905 new_rtx = make_extraction (mode, new_rtx, 7906 (GET_MODE_PRECISION (mode) 7907 - INTVAL (XEXP (XEXP (x, 0), 1))), 7908 NULL_RTX, i, 1, 0, in_code == COMPARE); 7909 } 7910 7911 /* On machines without logical shifts, if the operand of the AND is 7912 a logical shift and our mask turns off all the propagated sign 7913 bits, we can replace the logical shift with an arithmetic shift. */ 7914 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 7915 && !have_insn_for (LSHIFTRT, mode) 7916 && have_insn_for (ASHIFTRT, mode) 7917 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 7918 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 7919 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 7920 && mode_width <= HOST_BITS_PER_WIDE_INT) 7921 { 7922 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 7923 7924 mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); 7925 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) 7926 SUBST (XEXP (x, 0), 7927 gen_rtx_ASHIFTRT (mode, 7928 make_compound_operation 7929 (XEXP (XEXP (x, 0), 0), next_code), 7930 XEXP (XEXP (x, 0), 1))); 7931 } 7932 7933 /* If the constant is one less than a power of two, this might be 7934 representable by an extraction even if no shift is present. 7935 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless 7936 we are in a COMPARE. */ 7937 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) 7938 new_rtx = make_extraction (mode, 7939 make_compound_operation (XEXP (x, 0), 7940 next_code), 7941 0, NULL_RTX, i, 1, 0, in_code == COMPARE); 7942 7943 /* If we are in a comparison and this is an AND with a power of two, 7944 convert this into the appropriate bit extract. */ 7945 else if (in_code == COMPARE 7946 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0 7947 && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1)) 7948 new_rtx = make_extraction (mode, 7949 make_compound_operation (XEXP (x, 0), 7950 next_code), 7951 i, NULL_RTX, 1, 1, 0, 1); 7952 7953 break; 7954 7955 case LSHIFTRT: 7956 /* If the sign bit is known to be zero, replace this with an 7957 arithmetic shift. */ 7958 if (have_insn_for (ASHIFTRT, mode) 7959 && ! have_insn_for (LSHIFTRT, mode) 7960 && mode_width <= HOST_BITS_PER_WIDE_INT 7961 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) 7962 { 7963 new_rtx = gen_rtx_ASHIFTRT (mode, 7964 make_compound_operation (XEXP (x, 0), 7965 next_code), 7966 XEXP (x, 1)); 7967 break; 7968 } 7969 7970 /* ... fall through ... */ 7971 7972 case ASHIFTRT: 7973 lhs = XEXP (x, 0); 7974 rhs = XEXP (x, 1); 7975 7976 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, 7977 this is a SIGN_EXTRACT. */ 7978 if (CONST_INT_P (rhs) 7979 && GET_CODE (lhs) == ASHIFT 7980 && CONST_INT_P (XEXP (lhs, 1)) 7981 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)) 7982 && INTVAL (XEXP (lhs, 1)) >= 0 7983 && INTVAL (rhs) < mode_width) 7984 { 7985 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code); 7986 new_rtx = make_extraction (mode, new_rtx, 7987 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), 7988 NULL_RTX, mode_width - INTVAL (rhs), 7989 code == LSHIFTRT, 0, in_code == COMPARE); 7990 break; 7991 } 7992 7993 /* See if we have operations between an ASHIFTRT and an ASHIFT. 7994 If so, try to merge the shifts into a SIGN_EXTEND. We could 7995 also do this for some cases of SIGN_EXTRACT, but it doesn't 7996 seem worth the effort; the case checked for occurs on Alpha. */ 7997 7998 if (!OBJECT_P (lhs) 7999 && ! (GET_CODE (lhs) == SUBREG 8000 && (OBJECT_P (SUBREG_REG (lhs)))) 8001 && CONST_INT_P (rhs) 8002 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT 8003 && INTVAL (rhs) < mode_width 8004 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0) 8005 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code), 8006 0, NULL_RTX, mode_width - INTVAL (rhs), 8007 code == LSHIFTRT, 0, in_code == COMPARE); 8008 8009 break; 8010 8011 case SUBREG: 8012 /* Call ourselves recursively on the inner expression. If we are 8013 narrowing the object and it has a different RTL code from 8014 what it originally did, do this SUBREG as a force_to_mode. */ 8015 { 8016 rtx inner = SUBREG_REG (x), simplified; 8017 enum rtx_code subreg_code = in_code; 8018 8019 /* If in_code is COMPARE, it isn't always safe to pass it through 8020 to the recursive make_compound_operation call. */ 8021 if (subreg_code == COMPARE 8022 && (!subreg_lowpart_p (x) 8023 || GET_CODE (inner) == SUBREG 8024 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0) 8025 is (const_int 0), rather than 8026 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */ 8027 || (GET_CODE (inner) == AND 8028 && CONST_INT_P (XEXP (inner, 1)) 8029 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner)) 8030 && exact_log2 (UINTVAL (XEXP (inner, 1))) 8031 >= GET_MODE_BITSIZE (mode)))) 8032 subreg_code = SET; 8033 8034 tem = make_compound_operation (inner, subreg_code); 8035 8036 simplified 8037 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x)); 8038 if (simplified) 8039 tem = simplified; 8040 8041 if (GET_CODE (tem) != GET_CODE (inner) 8042 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner)) 8043 && subreg_lowpart_p (x)) 8044 { 8045 rtx newer 8046 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0); 8047 8048 /* If we have something other than a SUBREG, we might have 8049 done an expansion, so rerun ourselves. */ 8050 if (GET_CODE (newer) != SUBREG) 8051 newer = make_compound_operation (newer, in_code); 8052 8053 /* force_to_mode can expand compounds. If it just re-expanded the 8054 compound, use gen_lowpart to convert to the desired mode. */ 8055 if (rtx_equal_p (newer, x) 8056 /* Likewise if it re-expanded the compound only partially. 8057 This happens for SUBREG of ZERO_EXTRACT if they extract 8058 the same number of bits. */ 8059 || (GET_CODE (newer) == SUBREG 8060 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT 8061 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT) 8062 && GET_CODE (inner) == AND 8063 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0)))) 8064 return gen_lowpart (GET_MODE (x), tem); 8065 8066 return newer; 8067 } 8068 8069 if (simplified) 8070 return tem; 8071 } 8072 break; 8073 8074 default: 8075 break; 8076 } 8077 8078 if (new_rtx) 8079 { 8080 x = gen_lowpart (mode, new_rtx); 8081 code = GET_CODE (x); 8082 } 8083 8084 /* Now recursively process each operand of this operation. We need to 8085 handle ZERO_EXTEND specially so that we don't lose track of the 8086 inner mode. */ 8087 if (GET_CODE (x) == ZERO_EXTEND) 8088 { 8089 new_rtx = make_compound_operation (XEXP (x, 0), next_code); 8090 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x), 8091 new_rtx, GET_MODE (XEXP (x, 0))); 8092 if (tem) 8093 return tem; 8094 SUBST (XEXP (x, 0), new_rtx); 8095 return x; 8096 } 8097 8098 fmt = GET_RTX_FORMAT (code); 8099 for (i = 0; i < GET_RTX_LENGTH (code); i++) 8100 if (fmt[i] == 'e') 8101 { 8102 new_rtx = make_compound_operation (XEXP (x, i), next_code); 8103 SUBST (XEXP (x, i), new_rtx); 8104 } 8105 else if (fmt[i] == 'E') 8106 for (j = 0; j < XVECLEN (x, i); j++) 8107 { 8108 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code); 8109 SUBST (XVECEXP (x, i, j), new_rtx); 8110 } 8111 8112 maybe_swap: 8113 /* If this is a commutative operation, the changes to the operands 8114 may have made it noncanonical. */ 8115 if (COMMUTATIVE_ARITH_P (x) 8116 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 8117 { 8118 tem = XEXP (x, 0); 8119 SUBST (XEXP (x, 0), XEXP (x, 1)); 8120 SUBST (XEXP (x, 1), tem); 8121 } 8122 8123 return x; 8124 } 8125 8126 /* Given M see if it is a value that would select a field of bits 8127 within an item, but not the entire word. Return -1 if not. 8128 Otherwise, return the starting position of the field, where 0 is the 8129 low-order bit. 8130 8131 *PLEN is set to the length of the field. */ 8132 8133 static int 8134 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen) 8135 { 8136 /* Get the bit number of the first 1 bit from the right, -1 if none. */ 8137 int pos = m ? ctz_hwi (m) : -1; 8138 int len = 0; 8139 8140 if (pos >= 0) 8141 /* Now shift off the low-order zero bits and see if we have a 8142 power of two minus 1. */ 8143 len = exact_log2 ((m >> pos) + 1); 8144 8145 if (len <= 0) 8146 pos = -1; 8147 8148 *plen = len; 8149 return pos; 8150 } 8151 8152 /* If X refers to a register that equals REG in value, replace these 8153 references with REG. */ 8154 static rtx 8155 canon_reg_for_combine (rtx x, rtx reg) 8156 { 8157 rtx op0, op1, op2; 8158 const char *fmt; 8159 int i; 8160 bool copied; 8161 8162 enum rtx_code code = GET_CODE (x); 8163 switch (GET_RTX_CLASS (code)) 8164 { 8165 case RTX_UNARY: 8166 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8167 if (op0 != XEXP (x, 0)) 8168 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0, 8169 GET_MODE (reg)); 8170 break; 8171 8172 case RTX_BIN_ARITH: 8173 case RTX_COMM_ARITH: 8174 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8175 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 8176 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 8177 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); 8178 break; 8179 8180 case RTX_COMPARE: 8181 case RTX_COMM_COMPARE: 8182 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8183 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 8184 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 8185 return simplify_gen_relational (GET_CODE (x), GET_MODE (x), 8186 GET_MODE (op0), op0, op1); 8187 break; 8188 8189 case RTX_TERNARY: 8190 case RTX_BITFIELD_OPS: 8191 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 8192 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 8193 op2 = canon_reg_for_combine (XEXP (x, 2), reg); 8194 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2)) 8195 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x), 8196 GET_MODE (op0), op0, op1, op2); 8197 8198 case RTX_OBJ: 8199 if (REG_P (x)) 8200 { 8201 if (rtx_equal_p (get_last_value (reg), x) 8202 || rtx_equal_p (reg, get_last_value (x))) 8203 return reg; 8204 else 8205 break; 8206 } 8207 8208 /* fall through */ 8209 8210 default: 8211 fmt = GET_RTX_FORMAT (code); 8212 copied = false; 8213 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 8214 if (fmt[i] == 'e') 8215 { 8216 rtx op = canon_reg_for_combine (XEXP (x, i), reg); 8217 if (op != XEXP (x, i)) 8218 { 8219 if (!copied) 8220 { 8221 copied = true; 8222 x = copy_rtx (x); 8223 } 8224 XEXP (x, i) = op; 8225 } 8226 } 8227 else if (fmt[i] == 'E') 8228 { 8229 int j; 8230 for (j = 0; j < XVECLEN (x, i); j++) 8231 { 8232 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg); 8233 if (op != XVECEXP (x, i, j)) 8234 { 8235 if (!copied) 8236 { 8237 copied = true; 8238 x = copy_rtx (x); 8239 } 8240 XVECEXP (x, i, j) = op; 8241 } 8242 } 8243 } 8244 8245 break; 8246 } 8247 8248 return x; 8249 } 8250 8251 /* Return X converted to MODE. If the value is already truncated to 8252 MODE we can just return a subreg even though in the general case we 8253 would need an explicit truncation. */ 8254 8255 static rtx 8256 gen_lowpart_or_truncate (machine_mode mode, rtx x) 8257 { 8258 if (!CONST_INT_P (x) 8259 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)) 8260 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x)) 8261 && !(REG_P (x) && reg_truncated_to_mode (mode, x))) 8262 { 8263 /* Bit-cast X into an integer mode. */ 8264 if (!SCALAR_INT_MODE_P (GET_MODE (x))) 8265 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x); 8266 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode), 8267 x, GET_MODE (x)); 8268 } 8269 8270 return gen_lowpart (mode, x); 8271 } 8272 8273 /* See if X can be simplified knowing that we will only refer to it in 8274 MODE and will only refer to those bits that are nonzero in MASK. 8275 If other bits are being computed or if masking operations are done 8276 that select a superset of the bits in MASK, they can sometimes be 8277 ignored. 8278 8279 Return a possibly simplified expression, but always convert X to 8280 MODE. If X is a CONST_INT, AND the CONST_INT with MASK. 8281 8282 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK 8283 are all off in X. This is used when X will be complemented, by either 8284 NOT, NEG, or XOR. */ 8285 8286 static rtx 8287 force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask, 8288 int just_select) 8289 { 8290 enum rtx_code code = GET_CODE (x); 8291 int next_select = just_select || code == XOR || code == NOT || code == NEG; 8292 machine_mode op_mode; 8293 unsigned HOST_WIDE_INT fuller_mask, nonzero; 8294 rtx op0, op1, temp; 8295 8296 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the 8297 code below will do the wrong thing since the mode of such an 8298 expression is VOIDmode. 8299 8300 Also do nothing if X is a CLOBBER; this can happen if X was 8301 the return value from a call to gen_lowpart. */ 8302 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) 8303 return x; 8304 8305 /* We want to perform the operation in its present mode unless we know 8306 that the operation is valid in MODE, in which case we do the operation 8307 in MODE. */ 8308 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) 8309 && have_insn_for (code, mode)) 8310 ? mode : GET_MODE (x)); 8311 8312 /* It is not valid to do a right-shift in a narrower mode 8313 than the one it came in with. */ 8314 if ((code == LSHIFTRT || code == ASHIFTRT) 8315 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x))) 8316 op_mode = GET_MODE (x); 8317 8318 /* Truncate MASK to fit OP_MODE. */ 8319 if (op_mode) 8320 mask &= GET_MODE_MASK (op_mode); 8321 8322 /* When we have an arithmetic operation, or a shift whose count we 8323 do not know, we need to assume that all bits up to the highest-order 8324 bit in MASK will be needed. This is how we form such a mask. */ 8325 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) 8326 fuller_mask = ~(unsigned HOST_WIDE_INT) 0; 8327 else 8328 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) 8329 - 1); 8330 8331 /* Determine what bits of X are guaranteed to be (non)zero. */ 8332 nonzero = nonzero_bits (x, mode); 8333 8334 /* If none of the bits in X are needed, return a zero. */ 8335 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x)) 8336 x = const0_rtx; 8337 8338 /* If X is a CONST_INT, return a new one. Do this here since the 8339 test below will fail. */ 8340 if (CONST_INT_P (x)) 8341 { 8342 if (SCALAR_INT_MODE_P (mode)) 8343 return gen_int_mode (INTVAL (x) & mask, mode); 8344 else 8345 { 8346 x = GEN_INT (INTVAL (x) & mask); 8347 return gen_lowpart_common (mode, x); 8348 } 8349 } 8350 8351 /* If X is narrower than MODE and we want all the bits in X's mode, just 8352 get X in the proper mode. */ 8353 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) 8354 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) 8355 return gen_lowpart (mode, x); 8356 8357 /* We can ignore the effect of a SUBREG if it narrows the mode or 8358 if the constant masks to zero all the bits the mode doesn't have. */ 8359 if (GET_CODE (x) == SUBREG 8360 && subreg_lowpart_p (x) 8361 && ((GET_MODE_SIZE (GET_MODE (x)) 8362 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 8363 || (0 == (mask 8364 & GET_MODE_MASK (GET_MODE (x)) 8365 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) 8366 return force_to_mode (SUBREG_REG (x), mode, mask, next_select); 8367 8368 /* The arithmetic simplifications here only work for scalar integer modes. */ 8369 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x))) 8370 return gen_lowpart_or_truncate (mode, x); 8371 8372 switch (code) 8373 { 8374 case CLOBBER: 8375 /* If X is a (clobber (const_int)), return it since we know we are 8376 generating something that won't match. */ 8377 return x; 8378 8379 case SIGN_EXTEND: 8380 case ZERO_EXTEND: 8381 case ZERO_EXTRACT: 8382 case SIGN_EXTRACT: 8383 x = expand_compound_operation (x); 8384 if (GET_CODE (x) != code) 8385 return force_to_mode (x, mode, mask, next_select); 8386 break; 8387 8388 case TRUNCATE: 8389 /* Similarly for a truncate. */ 8390 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 8391 8392 case AND: 8393 /* If this is an AND with a constant, convert it into an AND 8394 whose constant is the AND of that constant with MASK. If it 8395 remains an AND of MASK, delete it since it is redundant. */ 8396 8397 if (CONST_INT_P (XEXP (x, 1))) 8398 { 8399 x = simplify_and_const_int (x, op_mode, XEXP (x, 0), 8400 mask & INTVAL (XEXP (x, 1))); 8401 8402 /* If X is still an AND, see if it is an AND with a mask that 8403 is just some low-order bits. If so, and it is MASK, we don't 8404 need it. */ 8405 8406 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1)) 8407 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) 8408 == mask)) 8409 x = XEXP (x, 0); 8410 8411 /* If it remains an AND, try making another AND with the bits 8412 in the mode mask that aren't in MASK turned on. If the 8413 constant in the AND is wide enough, this might make a 8414 cheaper constant. */ 8415 8416 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1)) 8417 && GET_MODE_MASK (GET_MODE (x)) != mask 8418 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))) 8419 { 8420 unsigned HOST_WIDE_INT cval 8421 = UINTVAL (XEXP (x, 1)) 8422 | (GET_MODE_MASK (GET_MODE (x)) & ~mask); 8423 rtx y; 8424 8425 y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0), 8426 gen_int_mode (cval, GET_MODE (x))); 8427 if (set_src_cost (y, optimize_this_for_speed_p) 8428 < set_src_cost (x, optimize_this_for_speed_p)) 8429 x = y; 8430 } 8431 8432 break; 8433 } 8434 8435 goto binop; 8436 8437 case PLUS: 8438 /* In (and (plus FOO C1) M), if M is a mask that just turns off 8439 low-order bits (as in an alignment operation) and FOO is already 8440 aligned to that boundary, mask C1 to that boundary as well. 8441 This may eliminate that PLUS and, later, the AND. */ 8442 8443 { 8444 unsigned int width = GET_MODE_PRECISION (mode); 8445 unsigned HOST_WIDE_INT smask = mask; 8446 8447 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative 8448 number, sign extend it. */ 8449 8450 if (width < HOST_BITS_PER_WIDE_INT 8451 && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0) 8452 smask |= HOST_WIDE_INT_M1U << width; 8453 8454 if (CONST_INT_P (XEXP (x, 1)) 8455 && exact_log2 (- smask) >= 0 8456 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 8457 && (INTVAL (XEXP (x, 1)) & ~smask) != 0) 8458 return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0), 8459 (INTVAL (XEXP (x, 1)) & smask)), 8460 mode, smask, next_select); 8461 } 8462 8463 /* ... fall through ... */ 8464 8465 case MULT: 8466 /* For PLUS, MINUS and MULT, we need any bits less significant than the 8467 most significant bit in MASK since carries from those bits will 8468 affect the bits we are interested in. */ 8469 mask = fuller_mask; 8470 goto binop; 8471 8472 case MINUS: 8473 /* If X is (minus C Y) where C's least set bit is larger than any bit 8474 in the mask, then we may replace with (neg Y). */ 8475 if (CONST_INT_P (XEXP (x, 0)) 8476 && ((UINTVAL (XEXP (x, 0)) & -UINTVAL (XEXP (x, 0))) > mask)) 8477 { 8478 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), 8479 GET_MODE (x)); 8480 return force_to_mode (x, mode, mask, next_select); 8481 } 8482 8483 /* Similarly, if C contains every bit in the fuller_mask, then we may 8484 replace with (not Y). */ 8485 if (CONST_INT_P (XEXP (x, 0)) 8486 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0)))) 8487 { 8488 x = simplify_gen_unary (NOT, GET_MODE (x), 8489 XEXP (x, 1), GET_MODE (x)); 8490 return force_to_mode (x, mode, mask, next_select); 8491 } 8492 8493 mask = fuller_mask; 8494 goto binop; 8495 8496 case IOR: 8497 case XOR: 8498 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and 8499 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) 8500 operation which may be a bitfield extraction. Ensure that the 8501 constant we form is not wider than the mode of X. */ 8502 8503 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 8504 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 8505 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 8506 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 8507 && CONST_INT_P (XEXP (x, 1)) 8508 && ((INTVAL (XEXP (XEXP (x, 0), 1)) 8509 + floor_log2 (INTVAL (XEXP (x, 1)))) 8510 < GET_MODE_PRECISION (GET_MODE (x))) 8511 && (UINTVAL (XEXP (x, 1)) 8512 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) 8513 { 8514 temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask) 8515 << INTVAL (XEXP (XEXP (x, 0), 1)), 8516 GET_MODE (x)); 8517 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x), 8518 XEXP (XEXP (x, 0), 0), temp); 8519 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp, 8520 XEXP (XEXP (x, 0), 1)); 8521 return force_to_mode (x, mode, mask, next_select); 8522 } 8523 8524 binop: 8525 /* For most binary operations, just propagate into the operation and 8526 change the mode if we have an operation of that mode. */ 8527 8528 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select); 8529 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select); 8530 8531 /* If we ended up truncating both operands, truncate the result of the 8532 operation instead. */ 8533 if (GET_CODE (op0) == TRUNCATE 8534 && GET_CODE (op1) == TRUNCATE) 8535 { 8536 op0 = XEXP (op0, 0); 8537 op1 = XEXP (op1, 0); 8538 } 8539 8540 op0 = gen_lowpart_or_truncate (op_mode, op0); 8541 op1 = gen_lowpart_or_truncate (op_mode, op1); 8542 8543 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 8544 x = simplify_gen_binary (code, op_mode, op0, op1); 8545 break; 8546 8547 case ASHIFT: 8548 /* For left shifts, do the same, but just for the first operand. 8549 However, we cannot do anything with shifts where we cannot 8550 guarantee that the counts are smaller than the size of the mode 8551 because such a count will have a different meaning in a 8552 wider mode. */ 8553 8554 if (! (CONST_INT_P (XEXP (x, 1)) 8555 && INTVAL (XEXP (x, 1)) >= 0 8556 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode)) 8557 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode 8558 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) 8559 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode)))) 8560 break; 8561 8562 /* If the shift count is a constant and we can do arithmetic in 8563 the mode of the shift, refine which bits we need. Otherwise, use the 8564 conservative form of the mask. */ 8565 if (CONST_INT_P (XEXP (x, 1)) 8566 && INTVAL (XEXP (x, 1)) >= 0 8567 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode) 8568 && HWI_COMPUTABLE_MODE_P (op_mode)) 8569 mask >>= INTVAL (XEXP (x, 1)); 8570 else 8571 mask = fuller_mask; 8572 8573 op0 = gen_lowpart_or_truncate (op_mode, 8574 force_to_mode (XEXP (x, 0), op_mode, 8575 mask, next_select)); 8576 8577 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 8578 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1)); 8579 break; 8580 8581 case LSHIFTRT: 8582 /* Here we can only do something if the shift count is a constant, 8583 this shift constant is valid for the host, and we can do arithmetic 8584 in OP_MODE. */ 8585 8586 if (CONST_INT_P (XEXP (x, 1)) 8587 && INTVAL (XEXP (x, 1)) >= 0 8588 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 8589 && HWI_COMPUTABLE_MODE_P (op_mode)) 8590 { 8591 rtx inner = XEXP (x, 0); 8592 unsigned HOST_WIDE_INT inner_mask; 8593 8594 /* Select the mask of the bits we need for the shift operand. */ 8595 inner_mask = mask << INTVAL (XEXP (x, 1)); 8596 8597 /* We can only change the mode of the shift if we can do arithmetic 8598 in the mode of the shift and INNER_MASK is no wider than the 8599 width of X's mode. */ 8600 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0) 8601 op_mode = GET_MODE (x); 8602 8603 inner = force_to_mode (inner, op_mode, inner_mask, next_select); 8604 8605 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) 8606 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); 8607 } 8608 8609 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the 8610 shift and AND produces only copies of the sign bit (C2 is one less 8611 than a power of two), we can do this with just a shift. */ 8612 8613 if (GET_CODE (x) == LSHIFTRT 8614 && CONST_INT_P (XEXP (x, 1)) 8615 /* The shift puts one of the sign bit copies in the least significant 8616 bit. */ 8617 && ((INTVAL (XEXP (x, 1)) 8618 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) 8619 >= GET_MODE_PRECISION (GET_MODE (x))) 8620 && exact_log2 (mask + 1) >= 0 8621 /* Number of bits left after the shift must be more than the mask 8622 needs. */ 8623 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) 8624 <= GET_MODE_PRECISION (GET_MODE (x))) 8625 /* Must be more sign bit copies than the mask needs. */ 8626 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 8627 >= exact_log2 (mask + 1))) 8628 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), 8629 GEN_INT (GET_MODE_PRECISION (GET_MODE (x)) 8630 - exact_log2 (mask + 1))); 8631 8632 goto shiftrt; 8633 8634 case ASHIFTRT: 8635 /* If we are just looking for the sign bit, we don't need this shift at 8636 all, even if it has a variable count. */ 8637 if (val_signbit_p (GET_MODE (x), mask)) 8638 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 8639 8640 /* If this is a shift by a constant, get a mask that contains those bits 8641 that are not copies of the sign bit. We then have two cases: If 8642 MASK only includes those bits, this can be a logical shift, which may 8643 allow simplifications. If MASK is a single-bit field not within 8644 those bits, we are requesting a copy of the sign bit and hence can 8645 shift the sign bit to the appropriate location. */ 8646 8647 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0 8648 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 8649 { 8650 int i; 8651 8652 /* If the considered data is wider than HOST_WIDE_INT, we can't 8653 represent a mask for all its bits in a single scalar. 8654 But we only care about the lower bits, so calculate these. */ 8655 8656 if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) 8657 { 8658 nonzero = ~(unsigned HOST_WIDE_INT) 0; 8659 8660 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 8661 is the number of bits a full-width mask would have set. 8662 We need only shift if these are fewer than nonzero can 8663 hold. If not, we must keep all bits set in nonzero. */ 8664 8665 if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 8666 < HOST_BITS_PER_WIDE_INT) 8667 nonzero >>= INTVAL (XEXP (x, 1)) 8668 + HOST_BITS_PER_WIDE_INT 8669 - GET_MODE_PRECISION (GET_MODE (x)) ; 8670 } 8671 else 8672 { 8673 nonzero = GET_MODE_MASK (GET_MODE (x)); 8674 nonzero >>= INTVAL (XEXP (x, 1)); 8675 } 8676 8677 if ((mask & ~nonzero) == 0) 8678 { 8679 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x), 8680 XEXP (x, 0), INTVAL (XEXP (x, 1))); 8681 if (GET_CODE (x) != ASHIFTRT) 8682 return force_to_mode (x, mode, mask, next_select); 8683 } 8684 8685 else if ((i = exact_log2 (mask)) >= 0) 8686 { 8687 x = simplify_shift_const 8688 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0), 8689 GET_MODE_PRECISION (GET_MODE (x)) - 1 - i); 8690 8691 if (GET_CODE (x) != ASHIFTRT) 8692 return force_to_mode (x, mode, mask, next_select); 8693 } 8694 } 8695 8696 /* If MASK is 1, convert this to an LSHIFTRT. This can be done 8697 even if the shift count isn't a constant. */ 8698 if (mask == 1) 8699 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), 8700 XEXP (x, 0), XEXP (x, 1)); 8701 8702 shiftrt: 8703 8704 /* If this is a zero- or sign-extension operation that just affects bits 8705 we don't care about, remove it. Be sure the call above returned 8706 something that is still a shift. */ 8707 8708 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) 8709 && CONST_INT_P (XEXP (x, 1)) 8710 && INTVAL (XEXP (x, 1)) >= 0 8711 && (INTVAL (XEXP (x, 1)) 8712 <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1)) 8713 && GET_CODE (XEXP (x, 0)) == ASHIFT 8714 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1)) 8715 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, 8716 next_select); 8717 8718 break; 8719 8720 case ROTATE: 8721 case ROTATERT: 8722 /* If the shift count is constant and we can do computations 8723 in the mode of X, compute where the bits we care about are. 8724 Otherwise, we can't do anything. Don't change the mode of 8725 the shift or propagate MODE into the shift, though. */ 8726 if (CONST_INT_P (XEXP (x, 1)) 8727 && INTVAL (XEXP (x, 1)) >= 0) 8728 { 8729 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, 8730 GET_MODE (x), 8731 gen_int_mode (mask, GET_MODE (x)), 8732 XEXP (x, 1)); 8733 if (temp && CONST_INT_P (temp)) 8734 x = simplify_gen_binary (code, GET_MODE (x), 8735 force_to_mode (XEXP (x, 0), GET_MODE (x), 8736 INTVAL (temp), next_select), 8737 XEXP (x, 1)); 8738 } 8739 break; 8740 8741 case NEG: 8742 /* If we just want the low-order bit, the NEG isn't needed since it 8743 won't change the low-order bit. */ 8744 if (mask == 1) 8745 return force_to_mode (XEXP (x, 0), mode, mask, just_select); 8746 8747 /* We need any bits less significant than the most significant bit in 8748 MASK since carries from those bits will affect the bits we are 8749 interested in. */ 8750 mask = fuller_mask; 8751 goto unop; 8752 8753 case NOT: 8754 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the 8755 same as the XOR case above. Ensure that the constant we form is not 8756 wider than the mode of X. */ 8757 8758 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 8759 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 8760 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 8761 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) 8762 < GET_MODE_PRECISION (GET_MODE (x))) 8763 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) 8764 { 8765 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), 8766 GET_MODE (x)); 8767 temp = simplify_gen_binary (XOR, GET_MODE (x), 8768 XEXP (XEXP (x, 0), 0), temp); 8769 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), 8770 temp, XEXP (XEXP (x, 0), 1)); 8771 8772 return force_to_mode (x, mode, mask, next_select); 8773 } 8774 8775 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must 8776 use the full mask inside the NOT. */ 8777 mask = fuller_mask; 8778 8779 unop: 8780 op0 = gen_lowpart_or_truncate (op_mode, 8781 force_to_mode (XEXP (x, 0), mode, mask, 8782 next_select)); 8783 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 8784 x = simplify_gen_unary (code, op_mode, op0, op_mode); 8785 break; 8786 8787 case NE: 8788 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included 8789 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, 8790 which is equal to STORE_FLAG_VALUE. */ 8791 if ((mask & ~STORE_FLAG_VALUE) == 0 8792 && XEXP (x, 1) == const0_rtx 8793 && GET_MODE (XEXP (x, 0)) == mode 8794 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 8795 && (nonzero_bits (XEXP (x, 0), mode) 8796 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE)) 8797 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 8798 8799 break; 8800 8801 case IF_THEN_ELSE: 8802 /* We have no way of knowing if the IF_THEN_ELSE can itself be 8803 written in a narrower mode. We play it safe and do not do so. */ 8804 8805 op0 = gen_lowpart_or_truncate (GET_MODE (x), 8806 force_to_mode (XEXP (x, 1), mode, 8807 mask, next_select)); 8808 op1 = gen_lowpart_or_truncate (GET_MODE (x), 8809 force_to_mode (XEXP (x, 2), mode, 8810 mask, next_select)); 8811 if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2)) 8812 x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x), 8813 GET_MODE (XEXP (x, 0)), XEXP (x, 0), 8814 op0, op1); 8815 break; 8816 8817 default: 8818 break; 8819 } 8820 8821 /* Ensure we return a value of the proper mode. */ 8822 return gen_lowpart_or_truncate (mode, x); 8823 } 8824 8825 /* Return nonzero if X is an expression that has one of two values depending on 8826 whether some other value is zero or nonzero. In that case, we return the 8827 value that is being tested, *PTRUE is set to the value if the rtx being 8828 returned has a nonzero value, and *PFALSE is set to the other alternative. 8829 8830 If we return zero, we set *PTRUE and *PFALSE to X. */ 8831 8832 static rtx 8833 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse) 8834 { 8835 machine_mode mode = GET_MODE (x); 8836 enum rtx_code code = GET_CODE (x); 8837 rtx cond0, cond1, true0, true1, false0, false1; 8838 unsigned HOST_WIDE_INT nz; 8839 8840 /* If we are comparing a value against zero, we are done. */ 8841 if ((code == NE || code == EQ) 8842 && XEXP (x, 1) == const0_rtx) 8843 { 8844 *ptrue = (code == NE) ? const_true_rtx : const0_rtx; 8845 *pfalse = (code == NE) ? const0_rtx : const_true_rtx; 8846 return XEXP (x, 0); 8847 } 8848 8849 /* If this is a unary operation whose operand has one of two values, apply 8850 our opcode to compute those values. */ 8851 else if (UNARY_P (x) 8852 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) 8853 { 8854 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); 8855 *pfalse = simplify_gen_unary (code, mode, false0, 8856 GET_MODE (XEXP (x, 0))); 8857 return cond0; 8858 } 8859 8860 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would 8861 make can't possibly match and would suppress other optimizations. */ 8862 else if (code == COMPARE) 8863 ; 8864 8865 /* If this is a binary operation, see if either side has only one of two 8866 values. If either one does or if both do and they are conditional on 8867 the same value, compute the new true and false values. */ 8868 else if (BINARY_P (x)) 8869 { 8870 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); 8871 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); 8872 8873 if ((cond0 != 0 || cond1 != 0) 8874 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) 8875 { 8876 /* If if_then_else_cond returned zero, then true/false are the 8877 same rtl. We must copy one of them to prevent invalid rtl 8878 sharing. */ 8879 if (cond0 == 0) 8880 true0 = copy_rtx (true0); 8881 else if (cond1 == 0) 8882 true1 = copy_rtx (true1); 8883 8884 if (COMPARISON_P (x)) 8885 { 8886 *ptrue = simplify_gen_relational (code, mode, VOIDmode, 8887 true0, true1); 8888 *pfalse = simplify_gen_relational (code, mode, VOIDmode, 8889 false0, false1); 8890 } 8891 else 8892 { 8893 *ptrue = simplify_gen_binary (code, mode, true0, true1); 8894 *pfalse = simplify_gen_binary (code, mode, false0, false1); 8895 } 8896 8897 return cond0 ? cond0 : cond1; 8898 } 8899 8900 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the 8901 operands is zero when the other is nonzero, and vice-versa, 8902 and STORE_FLAG_VALUE is 1 or -1. */ 8903 8904 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 8905 && (code == PLUS || code == IOR || code == XOR || code == MINUS 8906 || code == UMAX) 8907 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 8908 { 8909 rtx op0 = XEXP (XEXP (x, 0), 1); 8910 rtx op1 = XEXP (XEXP (x, 1), 1); 8911 8912 cond0 = XEXP (XEXP (x, 0), 0); 8913 cond1 = XEXP (XEXP (x, 1), 0); 8914 8915 if (COMPARISON_P (cond0) 8916 && COMPARISON_P (cond1) 8917 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) 8918 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 8919 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 8920 || ((swap_condition (GET_CODE (cond0)) 8921 == reversed_comparison_code (cond1, NULL)) 8922 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 8923 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 8924 && ! side_effects_p (x)) 8925 { 8926 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx); 8927 *pfalse = simplify_gen_binary (MULT, mode, 8928 (code == MINUS 8929 ? simplify_gen_unary (NEG, mode, 8930 op1, mode) 8931 : op1), 8932 const_true_rtx); 8933 return cond0; 8934 } 8935 } 8936 8937 /* Similarly for MULT, AND and UMIN, except that for these the result 8938 is always zero. */ 8939 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 8940 && (code == MULT || code == AND || code == UMIN) 8941 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 8942 { 8943 cond0 = XEXP (XEXP (x, 0), 0); 8944 cond1 = XEXP (XEXP (x, 1), 0); 8945 8946 if (COMPARISON_P (cond0) 8947 && COMPARISON_P (cond1) 8948 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) 8949 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 8950 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 8951 || ((swap_condition (GET_CODE (cond0)) 8952 == reversed_comparison_code (cond1, NULL)) 8953 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 8954 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 8955 && ! side_effects_p (x)) 8956 { 8957 *ptrue = *pfalse = const0_rtx; 8958 return cond0; 8959 } 8960 } 8961 } 8962 8963 else if (code == IF_THEN_ELSE) 8964 { 8965 /* If we have IF_THEN_ELSE already, extract the condition and 8966 canonicalize it if it is NE or EQ. */ 8967 cond0 = XEXP (x, 0); 8968 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); 8969 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) 8970 return XEXP (cond0, 0); 8971 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) 8972 { 8973 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); 8974 return XEXP (cond0, 0); 8975 } 8976 else 8977 return cond0; 8978 } 8979 8980 /* If X is a SUBREG, we can narrow both the true and false values 8981 if the inner expression, if there is a condition. */ 8982 else if (code == SUBREG 8983 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), 8984 &true0, &false0))) 8985 { 8986 true0 = simplify_gen_subreg (mode, true0, 8987 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 8988 false0 = simplify_gen_subreg (mode, false0, 8989 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 8990 if (true0 && false0) 8991 { 8992 *ptrue = true0; 8993 *pfalse = false0; 8994 return cond0; 8995 } 8996 } 8997 8998 /* If X is a constant, this isn't special and will cause confusions 8999 if we treat it as such. Likewise if it is equivalent to a constant. */ 9000 else if (CONSTANT_P (x) 9001 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) 9002 ; 9003 9004 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that 9005 will be least confusing to the rest of the compiler. */ 9006 else if (mode == BImode) 9007 { 9008 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; 9009 return x; 9010 } 9011 9012 /* If X is known to be either 0 or -1, those are the true and 9013 false values when testing X. */ 9014 else if (x == constm1_rtx || x == const0_rtx 9015 || (mode != VOIDmode 9016 && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode))) 9017 { 9018 *ptrue = constm1_rtx, *pfalse = const0_rtx; 9019 return x; 9020 } 9021 9022 /* Likewise for 0 or a single bit. */ 9023 else if (HWI_COMPUTABLE_MODE_P (mode) 9024 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0) 9025 { 9026 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx; 9027 return x; 9028 } 9029 9030 /* Otherwise fail; show no condition with true and false values the same. */ 9031 *ptrue = *pfalse = x; 9032 return 0; 9033 } 9034 9035 /* Return the value of expression X given the fact that condition COND 9036 is known to be true when applied to REG as its first operand and VAL 9037 as its second. X is known to not be shared and so can be modified in 9038 place. 9039 9040 We only handle the simplest cases, and specifically those cases that 9041 arise with IF_THEN_ELSE expressions. */ 9042 9043 static rtx 9044 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val) 9045 { 9046 enum rtx_code code = GET_CODE (x); 9047 rtx temp; 9048 const char *fmt; 9049 int i, j; 9050 9051 if (side_effects_p (x)) 9052 return x; 9053 9054 /* If either operand of the condition is a floating point value, 9055 then we have to avoid collapsing an EQ comparison. */ 9056 if (cond == EQ 9057 && rtx_equal_p (x, reg) 9058 && ! FLOAT_MODE_P (GET_MODE (x)) 9059 && ! FLOAT_MODE_P (GET_MODE (val))) 9060 return val; 9061 9062 if (cond == UNEQ && rtx_equal_p (x, reg)) 9063 return val; 9064 9065 /* If X is (abs REG) and we know something about REG's relationship 9066 with zero, we may be able to simplify this. */ 9067 9068 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) 9069 switch (cond) 9070 { 9071 case GE: case GT: case EQ: 9072 return XEXP (x, 0); 9073 case LT: case LE: 9074 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), 9075 XEXP (x, 0), 9076 GET_MODE (XEXP (x, 0))); 9077 default: 9078 break; 9079 } 9080 9081 /* The only other cases we handle are MIN, MAX, and comparisons if the 9082 operands are the same as REG and VAL. */ 9083 9084 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x)) 9085 { 9086 if (rtx_equal_p (XEXP (x, 0), val)) 9087 cond = swap_condition (cond), temp = val, val = reg, reg = temp; 9088 9089 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) 9090 { 9091 if (COMPARISON_P (x)) 9092 { 9093 if (comparison_dominates_p (cond, code)) 9094 return const_true_rtx; 9095 9096 code = reversed_comparison_code (x, NULL); 9097 if (code != UNKNOWN 9098 && comparison_dominates_p (cond, code)) 9099 return const0_rtx; 9100 else 9101 return x; 9102 } 9103 else if (code == SMAX || code == SMIN 9104 || code == UMIN || code == UMAX) 9105 { 9106 int unsignedp = (code == UMIN || code == UMAX); 9107 9108 /* Do not reverse the condition when it is NE or EQ. 9109 This is because we cannot conclude anything about 9110 the value of 'SMAX (x, y)' when x is not equal to y, 9111 but we can when x equals y. */ 9112 if ((code == SMAX || code == UMAX) 9113 && ! (cond == EQ || cond == NE)) 9114 cond = reverse_condition (cond); 9115 9116 switch (cond) 9117 { 9118 case GE: case GT: 9119 return unsignedp ? x : XEXP (x, 1); 9120 case LE: case LT: 9121 return unsignedp ? x : XEXP (x, 0); 9122 case GEU: case GTU: 9123 return unsignedp ? XEXP (x, 1) : x; 9124 case LEU: case LTU: 9125 return unsignedp ? XEXP (x, 0) : x; 9126 default: 9127 break; 9128 } 9129 } 9130 } 9131 } 9132 else if (code == SUBREG) 9133 { 9134 machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); 9135 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val); 9136 9137 if (SUBREG_REG (x) != r) 9138 { 9139 /* We must simplify subreg here, before we lose track of the 9140 original inner_mode. */ 9141 new_rtx = simplify_subreg (GET_MODE (x), r, 9142 inner_mode, SUBREG_BYTE (x)); 9143 if (new_rtx) 9144 return new_rtx; 9145 else 9146 SUBST (SUBREG_REG (x), r); 9147 } 9148 9149 return x; 9150 } 9151 /* We don't have to handle SIGN_EXTEND here, because even in the 9152 case of replacing something with a modeless CONST_INT, a 9153 CONST_INT is already (supposed to be) a valid sign extension for 9154 its narrower mode, which implies it's already properly 9155 sign-extended for the wider mode. Now, for ZERO_EXTEND, the 9156 story is different. */ 9157 else if (code == ZERO_EXTEND) 9158 { 9159 machine_mode inner_mode = GET_MODE (XEXP (x, 0)); 9160 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val); 9161 9162 if (XEXP (x, 0) != r) 9163 { 9164 /* We must simplify the zero_extend here, before we lose 9165 track of the original inner_mode. */ 9166 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), 9167 r, inner_mode); 9168 if (new_rtx) 9169 return new_rtx; 9170 else 9171 SUBST (XEXP (x, 0), r); 9172 } 9173 9174 return x; 9175 } 9176 9177 fmt = GET_RTX_FORMAT (code); 9178 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 9179 { 9180 if (fmt[i] == 'e') 9181 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); 9182 else if (fmt[i] == 'E') 9183 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 9184 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), 9185 cond, reg, val)); 9186 } 9187 9188 return x; 9189 } 9190 9191 /* See if X and Y are equal for the purposes of seeing if we can rewrite an 9192 assignment as a field assignment. */ 9193 9194 static int 9195 rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x) 9196 { 9197 if (widen_x && GET_MODE (x) != GET_MODE (y)) 9198 { 9199 if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (y))) 9200 return 0; 9201 if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN) 9202 return 0; 9203 /* For big endian, adjust the memory offset. */ 9204 if (BYTES_BIG_ENDIAN) 9205 x = adjust_address_nv (x, GET_MODE (y), 9206 -subreg_lowpart_offset (GET_MODE (x), 9207 GET_MODE (y))); 9208 else 9209 x = adjust_address_nv (x, GET_MODE (y), 0); 9210 } 9211 9212 if (x == y || rtx_equal_p (x, y)) 9213 return 1; 9214 9215 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) 9216 return 0; 9217 9218 /* Check for a paradoxical SUBREG of a MEM compared with the MEM. 9219 Note that all SUBREGs of MEM are paradoxical; otherwise they 9220 would have been rewritten. */ 9221 if (MEM_P (x) && GET_CODE (y) == SUBREG 9222 && MEM_P (SUBREG_REG (y)) 9223 && rtx_equal_p (SUBREG_REG (y), 9224 gen_lowpart (GET_MODE (SUBREG_REG (y)), x))) 9225 return 1; 9226 9227 if (MEM_P (y) && GET_CODE (x) == SUBREG 9228 && MEM_P (SUBREG_REG (x)) 9229 && rtx_equal_p (SUBREG_REG (x), 9230 gen_lowpart (GET_MODE (SUBREG_REG (x)), y))) 9231 return 1; 9232 9233 /* We used to see if get_last_value of X and Y were the same but that's 9234 not correct. In one direction, we'll cause the assignment to have 9235 the wrong destination and in the case, we'll import a register into this 9236 insn that might have already have been dead. So fail if none of the 9237 above cases are true. */ 9238 return 0; 9239 } 9240 9241 /* See if X, a SET operation, can be rewritten as a bit-field assignment. 9242 Return that assignment if so. 9243 9244 We only handle the most common cases. */ 9245 9246 static rtx 9247 make_field_assignment (rtx x) 9248 { 9249 rtx dest = SET_DEST (x); 9250 rtx src = SET_SRC (x); 9251 rtx assign; 9252 rtx rhs, lhs; 9253 HOST_WIDE_INT c1; 9254 HOST_WIDE_INT pos; 9255 unsigned HOST_WIDE_INT len; 9256 rtx other; 9257 machine_mode mode; 9258 9259 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is 9260 a clear of a one-bit field. We will have changed it to 9261 (and (rotate (const_int -2) POS) DEST), so check for that. Also check 9262 for a SUBREG. */ 9263 9264 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE 9265 && CONST_INT_P (XEXP (XEXP (src, 0), 0)) 9266 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 9267 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 9268 { 9269 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 9270 1, 1, 1, 0); 9271 if (assign != 0) 9272 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 9273 return x; 9274 } 9275 9276 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG 9277 && subreg_lowpart_p (XEXP (src, 0)) 9278 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) 9279 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) 9280 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE 9281 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) 9282 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 9283 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 9284 { 9285 assign = make_extraction (VOIDmode, dest, 0, 9286 XEXP (SUBREG_REG (XEXP (src, 0)), 1), 9287 1, 1, 1, 0); 9288 if (assign != 0) 9289 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 9290 return x; 9291 } 9292 9293 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a 9294 one-bit field. */ 9295 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT 9296 && XEXP (XEXP (src, 0), 0) == const1_rtx 9297 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 9298 { 9299 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 9300 1, 1, 1, 0); 9301 if (assign != 0) 9302 return gen_rtx_SET (VOIDmode, assign, const1_rtx); 9303 return x; 9304 } 9305 9306 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the 9307 SRC is an AND with all bits of that field set, then we can discard 9308 the AND. */ 9309 if (GET_CODE (dest) == ZERO_EXTRACT 9310 && CONST_INT_P (XEXP (dest, 1)) 9311 && GET_CODE (src) == AND 9312 && CONST_INT_P (XEXP (src, 1))) 9313 { 9314 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1)); 9315 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1)); 9316 unsigned HOST_WIDE_INT ze_mask; 9317 9318 if (width >= HOST_BITS_PER_WIDE_INT) 9319 ze_mask = -1; 9320 else 9321 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; 9322 9323 /* Complete overlap. We can remove the source AND. */ 9324 if ((and_mask & ze_mask) == ze_mask) 9325 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0)); 9326 9327 /* Partial overlap. We can reduce the source AND. */ 9328 if ((and_mask & ze_mask) != and_mask) 9329 { 9330 mode = GET_MODE (src); 9331 src = gen_rtx_AND (mode, XEXP (src, 0), 9332 gen_int_mode (and_mask & ze_mask, mode)); 9333 return gen_rtx_SET (VOIDmode, dest, src); 9334 } 9335 } 9336 9337 /* The other case we handle is assignments into a constant-position 9338 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents 9339 a mask that has all one bits except for a group of zero bits and 9340 OTHER is known to have zeros where C1 has ones, this is such an 9341 assignment. Compute the position and length from C1. Shift OTHER 9342 to the appropriate position, force it to the required mode, and 9343 make the extraction. Check for the AND in both operands. */ 9344 9345 /* One or more SUBREGs might obscure the constant-position field 9346 assignment. The first one we are likely to encounter is an outer 9347 narrowing SUBREG, which we can just strip for the purposes of 9348 identifying the constant-field assignment. */ 9349 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)) 9350 src = SUBREG_REG (src); 9351 9352 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) 9353 return x; 9354 9355 rhs = expand_compound_operation (XEXP (src, 0)); 9356 lhs = expand_compound_operation (XEXP (src, 1)); 9357 9358 if (GET_CODE (rhs) == AND 9359 && CONST_INT_P (XEXP (rhs, 1)) 9360 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) 9361 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 9362 /* The second SUBREG that might get in the way is a paradoxical 9363 SUBREG around the first operand of the AND. We want to 9364 pretend the operand is as wide as the destination here. We 9365 do this by adjusting the MEM to wider mode for the sole 9366 purpose of the call to rtx_equal_for_field_assignment_p. Also 9367 note this trick only works for MEMs. */ 9368 else if (GET_CODE (rhs) == AND 9369 && paradoxical_subreg_p (XEXP (rhs, 0)) 9370 && MEM_P (SUBREG_REG (XEXP (rhs, 0))) 9371 && CONST_INT_P (XEXP (rhs, 1)) 9372 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)), 9373 dest, true)) 9374 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 9375 else if (GET_CODE (lhs) == AND 9376 && CONST_INT_P (XEXP (lhs, 1)) 9377 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) 9378 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 9379 /* The second SUBREG that might get in the way is a paradoxical 9380 SUBREG around the first operand of the AND. We want to 9381 pretend the operand is as wide as the destination here. We 9382 do this by adjusting the MEM to wider mode for the sole 9383 purpose of the call to rtx_equal_for_field_assignment_p. Also 9384 note this trick only works for MEMs. */ 9385 else if (GET_CODE (lhs) == AND 9386 && paradoxical_subreg_p (XEXP (lhs, 0)) 9387 && MEM_P (SUBREG_REG (XEXP (lhs, 0))) 9388 && CONST_INT_P (XEXP (lhs, 1)) 9389 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)), 9390 dest, true)) 9391 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 9392 else 9393 return x; 9394 9395 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); 9396 if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest)) 9397 || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT 9398 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) 9399 return x; 9400 9401 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); 9402 if (assign == 0) 9403 return x; 9404 9405 /* The mode to use for the source is the mode of the assignment, or of 9406 what is inside a possible STRICT_LOW_PART. */ 9407 mode = (GET_CODE (assign) == STRICT_LOW_PART 9408 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); 9409 9410 /* Shift OTHER right POS places and make it the source, restricting it 9411 to the proper length and mode. */ 9412 9413 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT, 9414 GET_MODE (src), 9415 other, pos), 9416 dest); 9417 src = force_to_mode (src, mode, 9418 GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT 9419 ? ~(unsigned HOST_WIDE_INT) 0 9420 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, 9421 0); 9422 9423 /* If SRC is masked by an AND that does not make a difference in 9424 the value being stored, strip it. */ 9425 if (GET_CODE (assign) == ZERO_EXTRACT 9426 && CONST_INT_P (XEXP (assign, 1)) 9427 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT 9428 && GET_CODE (src) == AND 9429 && CONST_INT_P (XEXP (src, 1)) 9430 && UINTVAL (XEXP (src, 1)) 9431 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1) 9432 src = XEXP (src, 0); 9433 9434 return gen_rtx_SET (VOIDmode, assign, src); 9435 } 9436 9437 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) 9438 if so. */ 9439 9440 static rtx 9441 apply_distributive_law (rtx x) 9442 { 9443 enum rtx_code code = GET_CODE (x); 9444 enum rtx_code inner_code; 9445 rtx lhs, rhs, other; 9446 rtx tem; 9447 9448 /* Distributivity is not true for floating point as it can change the 9449 value. So we don't do it unless -funsafe-math-optimizations. */ 9450 if (FLOAT_MODE_P (GET_MODE (x)) 9451 && ! flag_unsafe_math_optimizations) 9452 return x; 9453 9454 /* The outer operation can only be one of the following: */ 9455 if (code != IOR && code != AND && code != XOR 9456 && code != PLUS && code != MINUS) 9457 return x; 9458 9459 lhs = XEXP (x, 0); 9460 rhs = XEXP (x, 1); 9461 9462 /* If either operand is a primitive we can't do anything, so get out 9463 fast. */ 9464 if (OBJECT_P (lhs) || OBJECT_P (rhs)) 9465 return x; 9466 9467 lhs = expand_compound_operation (lhs); 9468 rhs = expand_compound_operation (rhs); 9469 inner_code = GET_CODE (lhs); 9470 if (inner_code != GET_CODE (rhs)) 9471 return x; 9472 9473 /* See if the inner and outer operations distribute. */ 9474 switch (inner_code) 9475 { 9476 case LSHIFTRT: 9477 case ASHIFTRT: 9478 case AND: 9479 case IOR: 9480 /* These all distribute except over PLUS. */ 9481 if (code == PLUS || code == MINUS) 9482 return x; 9483 break; 9484 9485 case MULT: 9486 if (code != PLUS && code != MINUS) 9487 return x; 9488 break; 9489 9490 case ASHIFT: 9491 /* This is also a multiply, so it distributes over everything. */ 9492 break; 9493 9494 /* This used to handle SUBREG, but this turned out to be counter- 9495 productive, since (subreg (op ...)) usually is not handled by 9496 insn patterns, and this "optimization" therefore transformed 9497 recognizable patterns into unrecognizable ones. Therefore the 9498 SUBREG case was removed from here. 9499 9500 It is possible that distributing SUBREG over arithmetic operations 9501 leads to an intermediate result than can then be optimized further, 9502 e.g. by moving the outer SUBREG to the other side of a SET as done 9503 in simplify_set. This seems to have been the original intent of 9504 handling SUBREGs here. 9505 9506 However, with current GCC this does not appear to actually happen, 9507 at least on major platforms. If some case is found where removing 9508 the SUBREG case here prevents follow-on optimizations, distributing 9509 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */ 9510 9511 default: 9512 return x; 9513 } 9514 9515 /* Set LHS and RHS to the inner operands (A and B in the example 9516 above) and set OTHER to the common operand (C in the example). 9517 There is only one way to do this unless the inner operation is 9518 commutative. */ 9519 if (COMMUTATIVE_ARITH_P (lhs) 9520 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) 9521 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); 9522 else if (COMMUTATIVE_ARITH_P (lhs) 9523 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) 9524 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); 9525 else if (COMMUTATIVE_ARITH_P (lhs) 9526 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) 9527 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); 9528 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) 9529 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); 9530 else 9531 return x; 9532 9533 /* Form the new inner operation, seeing if it simplifies first. */ 9534 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs); 9535 9536 /* There is one exception to the general way of distributing: 9537 (a | c) ^ (b | c) -> (a ^ b) & ~c */ 9538 if (code == XOR && inner_code == IOR) 9539 { 9540 inner_code = AND; 9541 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); 9542 } 9543 9544 /* We may be able to continuing distributing the result, so call 9545 ourselves recursively on the inner operation before forming the 9546 outer operation, which we return. */ 9547 return simplify_gen_binary (inner_code, GET_MODE (x), 9548 apply_distributive_law (tem), other); 9549 } 9550 9551 /* See if X is of the form (* (+ A B) C), and if so convert to 9552 (+ (* A C) (* B C)) and try to simplify. 9553 9554 Most of the time, this results in no change. However, if some of 9555 the operands are the same or inverses of each other, simplifications 9556 will result. 9557 9558 For example, (and (ior A B) (not B)) can occur as the result of 9559 expanding a bit field assignment. When we apply the distributive 9560 law to this, we get (ior (and (A (not B))) (and (B (not B)))), 9561 which then simplifies to (and (A (not B))). 9562 9563 Note that no checks happen on the validity of applying the inverse 9564 distributive law. This is pointless since we can do it in the 9565 few places where this routine is called. 9566 9567 N is the index of the term that is decomposed (the arithmetic operation, 9568 i.e. (+ A B) in the first example above). !N is the index of the term that 9569 is distributed, i.e. of C in the first example above. */ 9570 static rtx 9571 distribute_and_simplify_rtx (rtx x, int n) 9572 { 9573 machine_mode mode; 9574 enum rtx_code outer_code, inner_code; 9575 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp; 9576 9577 /* Distributivity is not true for floating point as it can change the 9578 value. So we don't do it unless -funsafe-math-optimizations. */ 9579 if (FLOAT_MODE_P (GET_MODE (x)) 9580 && ! flag_unsafe_math_optimizations) 9581 return NULL_RTX; 9582 9583 decomposed = XEXP (x, n); 9584 if (!ARITHMETIC_P (decomposed)) 9585 return NULL_RTX; 9586 9587 mode = GET_MODE (x); 9588 outer_code = GET_CODE (x); 9589 distributed = XEXP (x, !n); 9590 9591 inner_code = GET_CODE (decomposed); 9592 inner_op0 = XEXP (decomposed, 0); 9593 inner_op1 = XEXP (decomposed, 1); 9594 9595 /* Special case (and (xor B C) (not A)), which is equivalent to 9596 (xor (ior A B) (ior A C)) */ 9597 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT) 9598 { 9599 distributed = XEXP (distributed, 0); 9600 outer_code = IOR; 9601 } 9602 9603 if (n == 0) 9604 { 9605 /* Distribute the second term. */ 9606 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed); 9607 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed); 9608 } 9609 else 9610 { 9611 /* Distribute the first term. */ 9612 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0); 9613 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1); 9614 } 9615 9616 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode, 9617 new_op0, new_op1)); 9618 if (GET_CODE (tmp) != outer_code 9619 && (set_src_cost (tmp, optimize_this_for_speed_p) 9620 < set_src_cost (x, optimize_this_for_speed_p))) 9621 return tmp; 9622 9623 return NULL_RTX; 9624 } 9625 9626 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done 9627 in MODE. Return an equivalent form, if different from (and VAROP 9628 (const_int CONSTOP)). Otherwise, return NULL_RTX. */ 9629 9630 static rtx 9631 simplify_and_const_int_1 (machine_mode mode, rtx varop, 9632 unsigned HOST_WIDE_INT constop) 9633 { 9634 unsigned HOST_WIDE_INT nonzero; 9635 unsigned HOST_WIDE_INT orig_constop; 9636 rtx orig_varop; 9637 int i; 9638 9639 orig_varop = varop; 9640 orig_constop = constop; 9641 if (GET_CODE (varop) == CLOBBER) 9642 return NULL_RTX; 9643 9644 /* Simplify VAROP knowing that we will be only looking at some of the 9645 bits in it. 9646 9647 Note by passing in CONSTOP, we guarantee that the bits not set in 9648 CONSTOP are not significant and will never be examined. We must 9649 ensure that is the case by explicitly masking out those bits 9650 before returning. */ 9651 varop = force_to_mode (varop, mode, constop, 0); 9652 9653 /* If VAROP is a CLOBBER, we will fail so return it. */ 9654 if (GET_CODE (varop) == CLOBBER) 9655 return varop; 9656 9657 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP 9658 to VAROP and return the new constant. */ 9659 if (CONST_INT_P (varop)) 9660 return gen_int_mode (INTVAL (varop) & constop, mode); 9661 9662 /* See what bits may be nonzero in VAROP. Unlike the general case of 9663 a call to nonzero_bits, here we don't care about bits outside 9664 MODE. */ 9665 9666 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); 9667 9668 /* Turn off all bits in the constant that are known to already be zero. 9669 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS 9670 which is tested below. */ 9671 9672 constop &= nonzero; 9673 9674 /* If we don't have any bits left, return zero. */ 9675 if (constop == 0) 9676 return const0_rtx; 9677 9678 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is 9679 a power of two, we can replace this with an ASHIFT. */ 9680 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 9681 && (i = exact_log2 (constop)) >= 0) 9682 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); 9683 9684 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR 9685 or XOR, then try to apply the distributive law. This may eliminate 9686 operations if either branch can be simplified because of the AND. 9687 It may also make some cases more complex, but those cases probably 9688 won't match a pattern either with or without this. */ 9689 9690 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) 9691 return 9692 gen_lowpart 9693 (mode, 9694 apply_distributive_law 9695 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop), 9696 simplify_and_const_int (NULL_RTX, 9697 GET_MODE (varop), 9698 XEXP (varop, 0), 9699 constop), 9700 simplify_and_const_int (NULL_RTX, 9701 GET_MODE (varop), 9702 XEXP (varop, 1), 9703 constop)))); 9704 9705 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute 9706 the AND and see if one of the operands simplifies to zero. If so, we 9707 may eliminate it. */ 9708 9709 if (GET_CODE (varop) == PLUS 9710 && exact_log2 (constop + 1) >= 0) 9711 { 9712 rtx o0, o1; 9713 9714 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); 9715 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); 9716 if (o0 == const0_rtx) 9717 return o1; 9718 if (o1 == const0_rtx) 9719 return o0; 9720 } 9721 9722 /* Make a SUBREG if necessary. If we can't make it, fail. */ 9723 varop = gen_lowpart (mode, varop); 9724 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) 9725 return NULL_RTX; 9726 9727 /* If we are only masking insignificant bits, return VAROP. */ 9728 if (constop == nonzero) 9729 return varop; 9730 9731 if (varop == orig_varop && constop == orig_constop) 9732 return NULL_RTX; 9733 9734 /* Otherwise, return an AND. */ 9735 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode)); 9736 } 9737 9738 9739 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done 9740 in MODE. 9741 9742 Return an equivalent form, if different from X. Otherwise, return X. If 9743 X is zero, we are to always construct the equivalent form. */ 9744 9745 static rtx 9746 simplify_and_const_int (rtx x, machine_mode mode, rtx varop, 9747 unsigned HOST_WIDE_INT constop) 9748 { 9749 rtx tem = simplify_and_const_int_1 (mode, varop, constop); 9750 if (tem) 9751 return tem; 9752 9753 if (!x) 9754 x = simplify_gen_binary (AND, GET_MODE (varop), varop, 9755 gen_int_mode (constop, mode)); 9756 if (GET_MODE (x) != mode) 9757 x = gen_lowpart (mode, x); 9758 return x; 9759 } 9760 9761 /* Given a REG, X, compute which bits in X can be nonzero. 9762 We don't care about bits outside of those defined in MODE. 9763 9764 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 9765 a shift, AND, or zero_extract, we can do better. */ 9766 9767 static rtx 9768 reg_nonzero_bits_for_combine (const_rtx x, machine_mode mode, 9769 const_rtx known_x ATTRIBUTE_UNUSED, 9770 machine_mode known_mode ATTRIBUTE_UNUSED, 9771 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED, 9772 unsigned HOST_WIDE_INT *nonzero) 9773 { 9774 rtx tem; 9775 reg_stat_type *rsp; 9776 9777 /* If X is a register whose nonzero bits value is current, use it. 9778 Otherwise, if X is a register whose value we can find, use that 9779 value. Otherwise, use the previously-computed global nonzero bits 9780 for this register. */ 9781 9782 rsp = ®_stat[REGNO (x)]; 9783 if (rsp->last_set_value != 0 9784 && (rsp->last_set_mode == mode 9785 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT 9786 && GET_MODE_CLASS (mode) == MODE_INT)) 9787 && ((rsp->last_set_label >= label_tick_ebb_start 9788 && rsp->last_set_label < label_tick) 9789 || (rsp->last_set_label == label_tick 9790 && DF_INSN_LUID (rsp->last_set) < subst_low_luid) 9791 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 9792 && REGNO (x) < reg_n_sets_max 9793 && REG_N_SETS (REGNO (x)) == 1 9794 && !REGNO_REG_SET_P 9795 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), 9796 REGNO (x))))) 9797 { 9798 unsigned HOST_WIDE_INT mask = rsp->last_set_nonzero_bits; 9799 9800 if (GET_MODE_PRECISION (rsp->last_set_mode) < GET_MODE_PRECISION (mode)) 9801 /* We don't know anything about the upper bits. */ 9802 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (rsp->last_set_mode); 9803 9804 *nonzero &= mask; 9805 return NULL; 9806 } 9807 9808 tem = get_last_value (x); 9809 9810 if (tem) 9811 { 9812 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND 9813 /* If X is narrower than MODE and TEM is a non-negative 9814 constant that would appear negative in the mode of X, 9815 sign-extend it for use in reg_nonzero_bits because some 9816 machines (maybe most) will actually do the sign-extension 9817 and this is the conservative approach. 9818 9819 ??? For 2.5, try to tighten up the MD files in this regard 9820 instead of this kludge. */ 9821 9822 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode) 9823 && CONST_INT_P (tem) 9824 && INTVAL (tem) > 0 9825 && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem))) 9826 tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x))); 9827 #endif 9828 return tem; 9829 } 9830 else if (nonzero_sign_valid && rsp->nonzero_bits) 9831 { 9832 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits; 9833 9834 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)) 9835 /* We don't know anything about the upper bits. */ 9836 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); 9837 9838 *nonzero &= mask; 9839 } 9840 9841 return NULL; 9842 } 9843 9844 /* Return the number of bits at the high-order end of X that are known to 9845 be equal to the sign bit. X will be used in mode MODE; if MODE is 9846 VOIDmode, X will be used in its own mode. The returned value will always 9847 be between 1 and the number of bits in MODE. */ 9848 9849 static rtx 9850 reg_num_sign_bit_copies_for_combine (const_rtx x, machine_mode mode, 9851 const_rtx known_x ATTRIBUTE_UNUSED, 9852 machine_mode known_mode 9853 ATTRIBUTE_UNUSED, 9854 unsigned int known_ret ATTRIBUTE_UNUSED, 9855 unsigned int *result) 9856 { 9857 rtx tem; 9858 reg_stat_type *rsp; 9859 9860 rsp = ®_stat[REGNO (x)]; 9861 if (rsp->last_set_value != 0 9862 && rsp->last_set_mode == mode 9863 && ((rsp->last_set_label >= label_tick_ebb_start 9864 && rsp->last_set_label < label_tick) 9865 || (rsp->last_set_label == label_tick 9866 && DF_INSN_LUID (rsp->last_set) < subst_low_luid) 9867 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 9868 && REGNO (x) < reg_n_sets_max 9869 && REG_N_SETS (REGNO (x)) == 1 9870 && !REGNO_REG_SET_P 9871 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), 9872 REGNO (x))))) 9873 { 9874 *result = rsp->last_set_sign_bit_copies; 9875 return NULL; 9876 } 9877 9878 tem = get_last_value (x); 9879 if (tem != 0) 9880 return tem; 9881 9882 if (nonzero_sign_valid && rsp->sign_bit_copies != 0 9883 && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode)) 9884 *result = rsp->sign_bit_copies; 9885 9886 return NULL; 9887 } 9888 9889 /* Return the number of "extended" bits there are in X, when interpreted 9890 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For 9891 unsigned quantities, this is the number of high-order zero bits. 9892 For signed quantities, this is the number of copies of the sign bit 9893 minus 1. In both case, this function returns the number of "spare" 9894 bits. For example, if two quantities for which this function returns 9895 at least 1 are added, the addition is known not to overflow. 9896 9897 This function will always return 0 unless called during combine, which 9898 implies that it must be called from a define_split. */ 9899 9900 unsigned int 9901 extended_count (const_rtx x, machine_mode mode, int unsignedp) 9902 { 9903 if (nonzero_sign_valid == 0) 9904 return 0; 9905 9906 return (unsignedp 9907 ? (HWI_COMPUTABLE_MODE_P (mode) 9908 ? (unsigned int) (GET_MODE_PRECISION (mode) - 1 9909 - floor_log2 (nonzero_bits (x, mode))) 9910 : 0) 9911 : num_sign_bit_copies (x, mode) - 1); 9912 } 9913 9914 /* This function is called from `simplify_shift_const' to merge two 9915 outer operations. Specifically, we have already found that we need 9916 to perform operation *POP0 with constant *PCONST0 at the outermost 9917 position. We would now like to also perform OP1 with constant CONST1 9918 (with *POP0 being done last). 9919 9920 Return 1 if we can do the operation and update *POP0 and *PCONST0 with 9921 the resulting operation. *PCOMP_P is set to 1 if we would need to 9922 complement the innermost operand, otherwise it is unchanged. 9923 9924 MODE is the mode in which the operation will be done. No bits outside 9925 the width of this mode matter. It is assumed that the width of this mode 9926 is smaller than or equal to HOST_BITS_PER_WIDE_INT. 9927 9928 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, 9929 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper 9930 result is simply *PCONST0. 9931 9932 If the resulting operation cannot be expressed as one operation, we 9933 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ 9934 9935 static int 9936 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p) 9937 { 9938 enum rtx_code op0 = *pop0; 9939 HOST_WIDE_INT const0 = *pconst0; 9940 9941 const0 &= GET_MODE_MASK (mode); 9942 const1 &= GET_MODE_MASK (mode); 9943 9944 /* If OP0 is an AND, clear unimportant bits in CONST1. */ 9945 if (op0 == AND) 9946 const1 &= const0; 9947 9948 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or 9949 if OP0 is SET. */ 9950 9951 if (op1 == UNKNOWN || op0 == SET) 9952 return 1; 9953 9954 else if (op0 == UNKNOWN) 9955 op0 = op1, const0 = const1; 9956 9957 else if (op0 == op1) 9958 { 9959 switch (op0) 9960 { 9961 case AND: 9962 const0 &= const1; 9963 break; 9964 case IOR: 9965 const0 |= const1; 9966 break; 9967 case XOR: 9968 const0 ^= const1; 9969 break; 9970 case PLUS: 9971 const0 += const1; 9972 break; 9973 case NEG: 9974 op0 = UNKNOWN; 9975 break; 9976 default: 9977 break; 9978 } 9979 } 9980 9981 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ 9982 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) 9983 return 0; 9984 9985 /* If the two constants aren't the same, we can't do anything. The 9986 remaining six cases can all be done. */ 9987 else if (const0 != const1) 9988 return 0; 9989 9990 else 9991 switch (op0) 9992 { 9993 case IOR: 9994 if (op1 == AND) 9995 /* (a & b) | b == b */ 9996 op0 = SET; 9997 else /* op1 == XOR */ 9998 /* (a ^ b) | b == a | b */ 9999 {;} 10000 break; 10001 10002 case XOR: 10003 if (op1 == AND) 10004 /* (a & b) ^ b == (~a) & b */ 10005 op0 = AND, *pcomp_p = 1; 10006 else /* op1 == IOR */ 10007 /* (a | b) ^ b == a & ~b */ 10008 op0 = AND, const0 = ~const0; 10009 break; 10010 10011 case AND: 10012 if (op1 == IOR) 10013 /* (a | b) & b == b */ 10014 op0 = SET; 10015 else /* op1 == XOR */ 10016 /* (a ^ b) & b) == (~a) & b */ 10017 *pcomp_p = 1; 10018 break; 10019 default: 10020 break; 10021 } 10022 10023 /* Check for NO-OP cases. */ 10024 const0 &= GET_MODE_MASK (mode); 10025 if (const0 == 0 10026 && (op0 == IOR || op0 == XOR || op0 == PLUS)) 10027 op0 = UNKNOWN; 10028 else if (const0 == 0 && op0 == AND) 10029 op0 = SET; 10030 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) 10031 && op0 == AND) 10032 op0 = UNKNOWN; 10033 10034 *pop0 = op0; 10035 10036 /* ??? Slightly redundant with the above mask, but not entirely. 10037 Moving this above means we'd have to sign-extend the mode mask 10038 for the final test. */ 10039 if (op0 != UNKNOWN && op0 != NEG) 10040 *pconst0 = trunc_int_for_mode (const0, mode); 10041 10042 return 1; 10043 } 10044 10045 /* A helper to simplify_shift_const_1 to determine the mode we can perform 10046 the shift in. The original shift operation CODE is performed on OP in 10047 ORIG_MODE. Return the wider mode MODE if we can perform the operation 10048 in that mode. Return ORIG_MODE otherwise. We can also assume that the 10049 result of the shift is subject to operation OUTER_CODE with operand 10050 OUTER_CONST. */ 10051 10052 static machine_mode 10053 try_widen_shift_mode (enum rtx_code code, rtx op, int count, 10054 machine_mode orig_mode, machine_mode mode, 10055 enum rtx_code outer_code, HOST_WIDE_INT outer_const) 10056 { 10057 if (orig_mode == mode) 10058 return mode; 10059 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode)); 10060 10061 /* In general we can't perform in wider mode for right shift and rotate. */ 10062 switch (code) 10063 { 10064 case ASHIFTRT: 10065 /* We can still widen if the bits brought in from the left are identical 10066 to the sign bit of ORIG_MODE. */ 10067 if (num_sign_bit_copies (op, mode) 10068 > (unsigned) (GET_MODE_PRECISION (mode) 10069 - GET_MODE_PRECISION (orig_mode))) 10070 return mode; 10071 return orig_mode; 10072 10073 case LSHIFTRT: 10074 /* Similarly here but with zero bits. */ 10075 if (HWI_COMPUTABLE_MODE_P (mode) 10076 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0) 10077 return mode; 10078 10079 /* We can also widen if the bits brought in will be masked off. This 10080 operation is performed in ORIG_MODE. */ 10081 if (outer_code == AND) 10082 { 10083 int care_bits = low_bitmask_len (orig_mode, outer_const); 10084 10085 if (care_bits >= 0 10086 && GET_MODE_PRECISION (orig_mode) - care_bits >= count) 10087 return mode; 10088 } 10089 /* fall through */ 10090 10091 case ROTATE: 10092 return orig_mode; 10093 10094 case ROTATERT: 10095 gcc_unreachable (); 10096 10097 default: 10098 return mode; 10099 } 10100 } 10101 10102 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind 10103 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX 10104 if we cannot simplify it. Otherwise, return a simplified value. 10105 10106 The shift is normally computed in the widest mode we find in VAROP, as 10107 long as it isn't a different number of words than RESULT_MODE. Exceptions 10108 are ASHIFTRT and ROTATE, which are always done in their original mode. */ 10109 10110 static rtx 10111 simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode, 10112 rtx varop, int orig_count) 10113 { 10114 enum rtx_code orig_code = code; 10115 rtx orig_varop = varop; 10116 int count; 10117 machine_mode mode = result_mode; 10118 machine_mode shift_mode, tmode; 10119 unsigned int mode_words 10120 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; 10121 /* We form (outer_op (code varop count) (outer_const)). */ 10122 enum rtx_code outer_op = UNKNOWN; 10123 HOST_WIDE_INT outer_const = 0; 10124 int complement_p = 0; 10125 rtx new_rtx, x; 10126 10127 /* Make sure and truncate the "natural" shift on the way in. We don't 10128 want to do this inside the loop as it makes it more difficult to 10129 combine shifts. */ 10130 if (SHIFT_COUNT_TRUNCATED) 10131 orig_count &= GET_MODE_BITSIZE (mode) - 1; 10132 10133 /* If we were given an invalid count, don't do anything except exactly 10134 what was requested. */ 10135 10136 if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode)) 10137 return NULL_RTX; 10138 10139 count = orig_count; 10140 10141 /* Unless one of the branches of the `if' in this loop does a `continue', 10142 we will `break' the loop after the `if'. */ 10143 10144 while (count != 0) 10145 { 10146 /* If we have an operand of (clobber (const_int 0)), fail. */ 10147 if (GET_CODE (varop) == CLOBBER) 10148 return NULL_RTX; 10149 10150 /* Convert ROTATERT to ROTATE. */ 10151 if (code == ROTATERT) 10152 { 10153 unsigned int bitsize = GET_MODE_PRECISION (result_mode); 10154 code = ROTATE; 10155 if (VECTOR_MODE_P (result_mode)) 10156 count = bitsize / GET_MODE_NUNITS (result_mode) - count; 10157 else 10158 count = bitsize - count; 10159 } 10160 10161 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, 10162 mode, outer_op, outer_const); 10163 10164 /* Handle cases where the count is greater than the size of the mode 10165 minus 1. For ASHIFT, use the size minus one as the count (this can 10166 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, 10167 take the count modulo the size. For other shifts, the result is 10168 zero. 10169 10170 Since these shifts are being produced by the compiler by combining 10171 multiple operations, each of which are defined, we know what the 10172 result is supposed to be. */ 10173 10174 if (count > (GET_MODE_PRECISION (shift_mode) - 1)) 10175 { 10176 if (code == ASHIFTRT) 10177 count = GET_MODE_PRECISION (shift_mode) - 1; 10178 else if (code == ROTATE || code == ROTATERT) 10179 count %= GET_MODE_PRECISION (shift_mode); 10180 else 10181 { 10182 /* We can't simply return zero because there may be an 10183 outer op. */ 10184 varop = const0_rtx; 10185 count = 0; 10186 break; 10187 } 10188 } 10189 10190 /* If we discovered we had to complement VAROP, leave. Making a NOT 10191 here would cause an infinite loop. */ 10192 if (complement_p) 10193 break; 10194 10195 /* An arithmetic right shift of a quantity known to be -1 or 0 10196 is a no-op. */ 10197 if (code == ASHIFTRT 10198 && (num_sign_bit_copies (varop, shift_mode) 10199 == GET_MODE_PRECISION (shift_mode))) 10200 { 10201 count = 0; 10202 break; 10203 } 10204 10205 /* If we are doing an arithmetic right shift and discarding all but 10206 the sign bit copies, this is equivalent to doing a shift by the 10207 bitsize minus one. Convert it into that shift because it will often 10208 allow other simplifications. */ 10209 10210 if (code == ASHIFTRT 10211 && (count + num_sign_bit_copies (varop, shift_mode) 10212 >= GET_MODE_PRECISION (shift_mode))) 10213 count = GET_MODE_PRECISION (shift_mode) - 1; 10214 10215 /* We simplify the tests below and elsewhere by converting 10216 ASHIFTRT to LSHIFTRT if we know the sign bit is clear. 10217 `make_compound_operation' will convert it to an ASHIFTRT for 10218 those machines (such as VAX) that don't have an LSHIFTRT. */ 10219 if (code == ASHIFTRT 10220 && val_signbit_known_clear_p (shift_mode, 10221 nonzero_bits (varop, shift_mode))) 10222 code = LSHIFTRT; 10223 10224 if (((code == LSHIFTRT 10225 && HWI_COMPUTABLE_MODE_P (shift_mode) 10226 && !(nonzero_bits (varop, shift_mode) >> count)) 10227 || (code == ASHIFT 10228 && HWI_COMPUTABLE_MODE_P (shift_mode) 10229 && !((nonzero_bits (varop, shift_mode) << count) 10230 & GET_MODE_MASK (shift_mode)))) 10231 && !side_effects_p (varop)) 10232 varop = const0_rtx; 10233 10234 switch (GET_CODE (varop)) 10235 { 10236 case SIGN_EXTEND: 10237 case ZERO_EXTEND: 10238 case SIGN_EXTRACT: 10239 case ZERO_EXTRACT: 10240 new_rtx = expand_compound_operation (varop); 10241 if (new_rtx != varop) 10242 { 10243 varop = new_rtx; 10244 continue; 10245 } 10246 break; 10247 10248 case MEM: 10249 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH 10250 minus the width of a smaller mode, we can do this with a 10251 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ 10252 if ((code == ASHIFTRT || code == LSHIFTRT) 10253 && ! mode_dependent_address_p (XEXP (varop, 0), 10254 MEM_ADDR_SPACE (varop)) 10255 && ! MEM_VOLATILE_P (varop) 10256 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 10257 MODE_INT, 1)) != BLKmode) 10258 { 10259 new_rtx = adjust_address_nv (varop, tmode, 10260 BYTES_BIG_ENDIAN ? 0 10261 : count / BITS_PER_UNIT); 10262 10263 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND 10264 : ZERO_EXTEND, mode, new_rtx); 10265 count = 0; 10266 continue; 10267 } 10268 break; 10269 10270 case SUBREG: 10271 /* If VAROP is a SUBREG, strip it as long as the inner operand has 10272 the same number of words as what we've seen so far. Then store 10273 the widest mode in MODE. */ 10274 if (subreg_lowpart_p (varop) 10275 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 10276 > GET_MODE_SIZE (GET_MODE (varop))) 10277 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 10278 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 10279 == mode_words 10280 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT 10281 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT) 10282 { 10283 varop = SUBREG_REG (varop); 10284 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) 10285 mode = GET_MODE (varop); 10286 continue; 10287 } 10288 break; 10289 10290 case MULT: 10291 /* Some machines use MULT instead of ASHIFT because MULT 10292 is cheaper. But it is still better on those machines to 10293 merge two shifts into one. */ 10294 if (CONST_INT_P (XEXP (varop, 1)) 10295 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0) 10296 { 10297 varop 10298 = simplify_gen_binary (ASHIFT, GET_MODE (varop), 10299 XEXP (varop, 0), 10300 GEN_INT (exact_log2 ( 10301 UINTVAL (XEXP (varop, 1))))); 10302 continue; 10303 } 10304 break; 10305 10306 case UDIV: 10307 /* Similar, for when divides are cheaper. */ 10308 if (CONST_INT_P (XEXP (varop, 1)) 10309 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0) 10310 { 10311 varop 10312 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop), 10313 XEXP (varop, 0), 10314 GEN_INT (exact_log2 ( 10315 UINTVAL (XEXP (varop, 1))))); 10316 continue; 10317 } 10318 break; 10319 10320 case ASHIFTRT: 10321 /* If we are extracting just the sign bit of an arithmetic 10322 right shift, that shift is not needed. However, the sign 10323 bit of a wider mode may be different from what would be 10324 interpreted as the sign bit in a narrower mode, so, if 10325 the result is narrower, don't discard the shift. */ 10326 if (code == LSHIFTRT 10327 && count == (GET_MODE_BITSIZE (result_mode) - 1) 10328 && (GET_MODE_BITSIZE (result_mode) 10329 >= GET_MODE_BITSIZE (GET_MODE (varop)))) 10330 { 10331 varop = XEXP (varop, 0); 10332 continue; 10333 } 10334 10335 /* ... fall through ... */ 10336 10337 case LSHIFTRT: 10338 case ASHIFT: 10339 case ROTATE: 10340 /* Here we have two nested shifts. The result is usually the 10341 AND of a new shift with a mask. We compute the result below. */ 10342 if (CONST_INT_P (XEXP (varop, 1)) 10343 && INTVAL (XEXP (varop, 1)) >= 0 10344 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop)) 10345 && HWI_COMPUTABLE_MODE_P (result_mode) 10346 && HWI_COMPUTABLE_MODE_P (mode) 10347 && !VECTOR_MODE_P (result_mode)) 10348 { 10349 enum rtx_code first_code = GET_CODE (varop); 10350 unsigned int first_count = INTVAL (XEXP (varop, 1)); 10351 unsigned HOST_WIDE_INT mask; 10352 rtx mask_rtx; 10353 10354 /* We have one common special case. We can't do any merging if 10355 the inner code is an ASHIFTRT of a smaller mode. However, if 10356 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) 10357 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), 10358 we can convert it to 10359 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1). 10360 This simplifies certain SIGN_EXTEND operations. */ 10361 if (code == ASHIFT && first_code == ASHIFTRT 10362 && count == (GET_MODE_PRECISION (result_mode) 10363 - GET_MODE_PRECISION (GET_MODE (varop)))) 10364 { 10365 /* C3 has the low-order C1 bits zero. */ 10366 10367 mask = GET_MODE_MASK (mode) 10368 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1); 10369 10370 varop = simplify_and_const_int (NULL_RTX, result_mode, 10371 XEXP (varop, 0), mask); 10372 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, 10373 varop, count); 10374 count = first_count; 10375 code = ASHIFTRT; 10376 continue; 10377 } 10378 10379 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more 10380 than C1 high-order bits equal to the sign bit, we can convert 10381 this to either an ASHIFT or an ASHIFTRT depending on the 10382 two counts. 10383 10384 We cannot do this if VAROP's mode is not SHIFT_MODE. */ 10385 10386 if (code == ASHIFTRT && first_code == ASHIFT 10387 && GET_MODE (varop) == shift_mode 10388 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) 10389 > first_count)) 10390 { 10391 varop = XEXP (varop, 0); 10392 count -= first_count; 10393 if (count < 0) 10394 { 10395 count = -count; 10396 code = ASHIFT; 10397 } 10398 10399 continue; 10400 } 10401 10402 /* There are some cases we can't do. If CODE is ASHIFTRT, 10403 we can only do this if FIRST_CODE is also ASHIFTRT. 10404 10405 We can't do the case when CODE is ROTATE and FIRST_CODE is 10406 ASHIFTRT. 10407 10408 If the mode of this shift is not the mode of the outer shift, 10409 we can't do this if either shift is a right shift or ROTATE. 10410 10411 Finally, we can't do any of these if the mode is too wide 10412 unless the codes are the same. 10413 10414 Handle the case where the shift codes are the same 10415 first. */ 10416 10417 if (code == first_code) 10418 { 10419 if (GET_MODE (varop) != result_mode 10420 && (code == ASHIFTRT || code == LSHIFTRT 10421 || code == ROTATE)) 10422 break; 10423 10424 count += first_count; 10425 varop = XEXP (varop, 0); 10426 continue; 10427 } 10428 10429 if (code == ASHIFTRT 10430 || (code == ROTATE && first_code == ASHIFTRT) 10431 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT 10432 || (GET_MODE (varop) != result_mode 10433 && (first_code == ASHIFTRT || first_code == LSHIFTRT 10434 || first_code == ROTATE 10435 || code == ROTATE))) 10436 break; 10437 10438 /* To compute the mask to apply after the shift, shift the 10439 nonzero bits of the inner shift the same way the 10440 outer shift will. */ 10441 10442 mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)), 10443 result_mode); 10444 10445 mask_rtx 10446 = simplify_const_binary_operation (code, result_mode, mask_rtx, 10447 GEN_INT (count)); 10448 10449 /* Give up if we can't compute an outer operation to use. */ 10450 if (mask_rtx == 0 10451 || !CONST_INT_P (mask_rtx) 10452 || ! merge_outer_ops (&outer_op, &outer_const, AND, 10453 INTVAL (mask_rtx), 10454 result_mode, &complement_p)) 10455 break; 10456 10457 /* If the shifts are in the same direction, we add the 10458 counts. Otherwise, we subtract them. */ 10459 if ((code == ASHIFTRT || code == LSHIFTRT) 10460 == (first_code == ASHIFTRT || first_code == LSHIFTRT)) 10461 count += first_count; 10462 else 10463 count -= first_count; 10464 10465 /* If COUNT is positive, the new shift is usually CODE, 10466 except for the two exceptions below, in which case it is 10467 FIRST_CODE. If the count is negative, FIRST_CODE should 10468 always be used */ 10469 if (count > 0 10470 && ((first_code == ROTATE && code == ASHIFT) 10471 || (first_code == ASHIFTRT && code == LSHIFTRT))) 10472 code = first_code; 10473 else if (count < 0) 10474 code = first_code, count = -count; 10475 10476 varop = XEXP (varop, 0); 10477 continue; 10478 } 10479 10480 /* If we have (A << B << C) for any shift, we can convert this to 10481 (A << C << B). This wins if A is a constant. Only try this if 10482 B is not a constant. */ 10483 10484 else if (GET_CODE (varop) == code 10485 && CONST_INT_P (XEXP (varop, 0)) 10486 && !CONST_INT_P (XEXP (varop, 1))) 10487 { 10488 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make 10489 sure the result will be masked. See PR70222. */ 10490 if (code == LSHIFTRT 10491 && mode != result_mode 10492 && !merge_outer_ops (&outer_op, &outer_const, AND, 10493 GET_MODE_MASK (result_mode) 10494 >> orig_count, result_mode, 10495 &complement_p)) 10496 break; 10497 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing 10498 up outer sign extension (often left and right shift) is 10499 hardly more efficient than the original. See PR70429. */ 10500 if (code == ASHIFTRT && mode != result_mode) 10501 break; 10502 10503 rtx new_rtx = simplify_const_binary_operation (code, mode, 10504 XEXP (varop, 0), 10505 GEN_INT (count)); 10506 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1)); 10507 count = 0; 10508 continue; 10509 } 10510 break; 10511 10512 case NOT: 10513 if (VECTOR_MODE_P (mode)) 10514 break; 10515 10516 /* Make this fit the case below. */ 10517 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx); 10518 continue; 10519 10520 case IOR: 10521 case AND: 10522 case XOR: 10523 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) 10524 with C the size of VAROP - 1 and the shift is logical if 10525 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 10526 we have an (le X 0) operation. If we have an arithmetic shift 10527 and STORE_FLAG_VALUE is 1 or we have a logical shift with 10528 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ 10529 10530 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS 10531 && XEXP (XEXP (varop, 0), 1) == constm1_rtx 10532 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 10533 && (code == LSHIFTRT || code == ASHIFTRT) 10534 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1) 10535 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 10536 { 10537 count = 0; 10538 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), 10539 const0_rtx); 10540 10541 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 10542 varop = gen_rtx_NEG (GET_MODE (varop), varop); 10543 10544 continue; 10545 } 10546 10547 /* If we have (shift (logical)), move the logical to the outside 10548 to allow it to possibly combine with another logical and the 10549 shift to combine with another shift. This also canonicalizes to 10550 what a ZERO_EXTRACT looks like. Also, some machines have 10551 (and (shift)) insns. */ 10552 10553 if (CONST_INT_P (XEXP (varop, 1)) 10554 /* We can't do this if we have (ashiftrt (xor)) and the 10555 constant has its sign bit set in shift_mode with shift_mode 10556 wider than result_mode. */ 10557 && !(code == ASHIFTRT && GET_CODE (varop) == XOR 10558 && result_mode != shift_mode 10559 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), 10560 shift_mode)) 10561 && (new_rtx = simplify_const_binary_operation 10562 (code, result_mode, 10563 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode), 10564 GEN_INT (count))) != 0 10565 && CONST_INT_P (new_rtx) 10566 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), 10567 INTVAL (new_rtx), result_mode, &complement_p)) 10568 { 10569 varop = XEXP (varop, 0); 10570 continue; 10571 } 10572 10573 /* If we can't do that, try to simplify the shift in each arm of the 10574 logical expression, make a new logical expression, and apply 10575 the inverse distributive law. This also can't be done for 10576 (ashiftrt (xor)) where we've widened the shift and the constant 10577 changes the sign bit. */ 10578 if (CONST_INT_P (XEXP (varop, 1)) 10579 && !(code == ASHIFTRT && GET_CODE (varop) == XOR 10580 && result_mode != shift_mode 10581 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), 10582 shift_mode))) 10583 { 10584 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, 10585 XEXP (varop, 0), count); 10586 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, 10587 XEXP (varop, 1), count); 10588 10589 varop = simplify_gen_binary (GET_CODE (varop), shift_mode, 10590 lhs, rhs); 10591 varop = apply_distributive_law (varop); 10592 10593 count = 0; 10594 continue; 10595 } 10596 break; 10597 10598 case EQ: 10599 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE 10600 says that the sign bit can be tested, FOO has mode MODE, C is 10601 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit 10602 that may be nonzero. */ 10603 if (code == LSHIFTRT 10604 && XEXP (varop, 1) == const0_rtx 10605 && GET_MODE (XEXP (varop, 0)) == result_mode 10606 && count == (GET_MODE_PRECISION (result_mode) - 1) 10607 && HWI_COMPUTABLE_MODE_P (result_mode) 10608 && STORE_FLAG_VALUE == -1 10609 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 10610 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode, 10611 &complement_p)) 10612 { 10613 varop = XEXP (varop, 0); 10614 count = 0; 10615 continue; 10616 } 10617 break; 10618 10619 case NEG: 10620 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less 10621 than the number of bits in the mode is equivalent to A. */ 10622 if (code == LSHIFTRT 10623 && count == (GET_MODE_PRECISION (result_mode) - 1) 10624 && nonzero_bits (XEXP (varop, 0), result_mode) == 1) 10625 { 10626 varop = XEXP (varop, 0); 10627 count = 0; 10628 continue; 10629 } 10630 10631 /* NEG commutes with ASHIFT since it is multiplication. Move the 10632 NEG outside to allow shifts to combine. */ 10633 if (code == ASHIFT 10634 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode, 10635 &complement_p)) 10636 { 10637 varop = XEXP (varop, 0); 10638 continue; 10639 } 10640 break; 10641 10642 case PLUS: 10643 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C 10644 is one less than the number of bits in the mode is 10645 equivalent to (xor A 1). */ 10646 if (code == LSHIFTRT 10647 && count == (GET_MODE_PRECISION (result_mode) - 1) 10648 && XEXP (varop, 1) == constm1_rtx 10649 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 10650 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode, 10651 &complement_p)) 10652 { 10653 count = 0; 10654 varop = XEXP (varop, 0); 10655 continue; 10656 } 10657 10658 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits 10659 that might be nonzero in BAR are those being shifted out and those 10660 bits are known zero in FOO, we can replace the PLUS with FOO. 10661 Similarly in the other operand order. This code occurs when 10662 we are computing the size of a variable-size array. */ 10663 10664 if ((code == ASHIFTRT || code == LSHIFTRT) 10665 && count < HOST_BITS_PER_WIDE_INT 10666 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 10667 && (nonzero_bits (XEXP (varop, 1), result_mode) 10668 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) 10669 { 10670 varop = XEXP (varop, 0); 10671 continue; 10672 } 10673 else if ((code == ASHIFTRT || code == LSHIFTRT) 10674 && count < HOST_BITS_PER_WIDE_INT 10675 && HWI_COMPUTABLE_MODE_P (result_mode) 10676 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 10677 >> count) 10678 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 10679 & nonzero_bits (XEXP (varop, 1), 10680 result_mode))) 10681 { 10682 varop = XEXP (varop, 1); 10683 continue; 10684 } 10685 10686 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ 10687 if (code == ASHIFT 10688 && CONST_INT_P (XEXP (varop, 1)) 10689 && (new_rtx = simplify_const_binary_operation 10690 (ASHIFT, result_mode, 10691 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode), 10692 GEN_INT (count))) != 0 10693 && CONST_INT_P (new_rtx) 10694 && merge_outer_ops (&outer_op, &outer_const, PLUS, 10695 INTVAL (new_rtx), result_mode, &complement_p)) 10696 { 10697 varop = XEXP (varop, 0); 10698 continue; 10699 } 10700 10701 /* Check for 'PLUS signbit', which is the canonical form of 'XOR 10702 signbit', and attempt to change the PLUS to an XOR and move it to 10703 the outer operation as is done above in the AND/IOR/XOR case 10704 leg for shift(logical). See details in logical handling above 10705 for reasoning in doing so. */ 10706 if (code == LSHIFTRT 10707 && CONST_INT_P (XEXP (varop, 1)) 10708 && mode_signbit_p (result_mode, XEXP (varop, 1)) 10709 && (new_rtx = simplify_const_binary_operation 10710 (code, result_mode, 10711 gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode), 10712 GEN_INT (count))) != 0 10713 && CONST_INT_P (new_rtx) 10714 && merge_outer_ops (&outer_op, &outer_const, XOR, 10715 INTVAL (new_rtx), result_mode, &complement_p)) 10716 { 10717 varop = XEXP (varop, 0); 10718 continue; 10719 } 10720 10721 break; 10722 10723 case MINUS: 10724 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) 10725 with C the size of VAROP - 1 and the shift is logical if 10726 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 10727 we have a (gt X 0) operation. If the shift is arithmetic with 10728 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, 10729 we have a (neg (gt X 0)) operation. */ 10730 10731 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 10732 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT 10733 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1) 10734 && (code == LSHIFTRT || code == ASHIFTRT) 10735 && CONST_INT_P (XEXP (XEXP (varop, 0), 1)) 10736 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count 10737 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 10738 { 10739 count = 0; 10740 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), 10741 const0_rtx); 10742 10743 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 10744 varop = gen_rtx_NEG (GET_MODE (varop), varop); 10745 10746 continue; 10747 } 10748 break; 10749 10750 case TRUNCATE: 10751 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) 10752 if the truncate does not affect the value. */ 10753 if (code == LSHIFTRT 10754 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT 10755 && CONST_INT_P (XEXP (XEXP (varop, 0), 1)) 10756 && (INTVAL (XEXP (XEXP (varop, 0), 1)) 10757 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0))) 10758 - GET_MODE_PRECISION (GET_MODE (varop))))) 10759 { 10760 rtx varop_inner = XEXP (varop, 0); 10761 10762 varop_inner 10763 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), 10764 XEXP (varop_inner, 0), 10765 GEN_INT 10766 (count + INTVAL (XEXP (varop_inner, 1)))); 10767 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); 10768 count = 0; 10769 continue; 10770 } 10771 break; 10772 10773 default: 10774 break; 10775 } 10776 10777 break; 10778 } 10779 10780 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode, 10781 outer_op, outer_const); 10782 10783 /* We have now finished analyzing the shift. The result should be 10784 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If 10785 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied 10786 to the result of the shift. OUTER_CONST is the relevant constant, 10787 but we must turn off all bits turned off in the shift. */ 10788 10789 if (outer_op == UNKNOWN 10790 && orig_code == code && orig_count == count 10791 && varop == orig_varop 10792 && shift_mode == GET_MODE (varop)) 10793 return NULL_RTX; 10794 10795 /* Make a SUBREG if necessary. If we can't make it, fail. */ 10796 varop = gen_lowpart (shift_mode, varop); 10797 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) 10798 return NULL_RTX; 10799 10800 /* If we have an outer operation and we just made a shift, it is 10801 possible that we could have simplified the shift were it not 10802 for the outer operation. So try to do the simplification 10803 recursively. */ 10804 10805 if (outer_op != UNKNOWN) 10806 x = simplify_shift_const_1 (code, shift_mode, varop, count); 10807 else 10808 x = NULL_RTX; 10809 10810 if (x == NULL_RTX) 10811 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count)); 10812 10813 /* If we were doing an LSHIFTRT in a wider mode than it was originally, 10814 turn off all the bits that the shift would have turned off. */ 10815 if (orig_code == LSHIFTRT && result_mode != shift_mode) 10816 x = simplify_and_const_int (NULL_RTX, shift_mode, x, 10817 GET_MODE_MASK (result_mode) >> orig_count); 10818 10819 /* Do the remainder of the processing in RESULT_MODE. */ 10820 x = gen_lowpart_or_truncate (result_mode, x); 10821 10822 /* If COMPLEMENT_P is set, we have to complement X before doing the outer 10823 operation. */ 10824 if (complement_p) 10825 x = simplify_gen_unary (NOT, result_mode, x, result_mode); 10826 10827 if (outer_op != UNKNOWN) 10828 { 10829 if (GET_RTX_CLASS (outer_op) != RTX_UNARY 10830 && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT) 10831 outer_const = trunc_int_for_mode (outer_const, result_mode); 10832 10833 if (outer_op == AND) 10834 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); 10835 else if (outer_op == SET) 10836 { 10837 /* This means that we have determined that the result is 10838 equivalent to a constant. This should be rare. */ 10839 if (!side_effects_p (x)) 10840 x = GEN_INT (outer_const); 10841 } 10842 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY) 10843 x = simplify_gen_unary (outer_op, result_mode, x, result_mode); 10844 else 10845 x = simplify_gen_binary (outer_op, result_mode, x, 10846 GEN_INT (outer_const)); 10847 } 10848 10849 return x; 10850 } 10851 10852 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 10853 The result of the shift is RESULT_MODE. If we cannot simplify it, 10854 return X or, if it is NULL, synthesize the expression with 10855 simplify_gen_binary. Otherwise, return a simplified value. 10856 10857 The shift is normally computed in the widest mode we find in VAROP, as 10858 long as it isn't a different number of words than RESULT_MODE. Exceptions 10859 are ASHIFTRT and ROTATE, which are always done in their original mode. */ 10860 10861 static rtx 10862 simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode, 10863 rtx varop, int count) 10864 { 10865 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count); 10866 if (tem) 10867 return tem; 10868 10869 if (!x) 10870 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count)); 10871 if (GET_MODE (x) != result_mode) 10872 x = gen_lowpart (result_mode, x); 10873 return x; 10874 } 10875 10876 10877 /* Like recog, but we receive the address of a pointer to a new pattern. 10878 We try to match the rtx that the pointer points to. 10879 If that fails, we may try to modify or replace the pattern, 10880 storing the replacement into the same pointer object. 10881 10882 Modifications include deletion or addition of CLOBBERs. 10883 10884 PNOTES is a pointer to a location where any REG_UNUSED notes added for 10885 the CLOBBERs are placed. 10886 10887 The value is the final insn code from the pattern ultimately matched, 10888 or -1. */ 10889 10890 static int 10891 recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) 10892 { 10893 rtx pat = *pnewpat; 10894 rtx pat_without_clobbers; 10895 int insn_code_number; 10896 int num_clobbers_to_add = 0; 10897 int i; 10898 rtx notes = NULL_RTX; 10899 rtx old_notes, old_pat; 10900 int old_icode; 10901 10902 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER 10903 we use to indicate that something didn't match. If we find such a 10904 thing, force rejection. */ 10905 if (GET_CODE (pat) == PARALLEL) 10906 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 10907 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER 10908 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 10909 return -1; 10910 10911 old_pat = PATTERN (insn); 10912 old_notes = REG_NOTES (insn); 10913 PATTERN (insn) = pat; 10914 REG_NOTES (insn) = NULL_RTX; 10915 10916 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 10917 if (dump_file && (dump_flags & TDF_DETAILS)) 10918 { 10919 if (insn_code_number < 0) 10920 fputs ("Failed to match this instruction:\n", dump_file); 10921 else 10922 fputs ("Successfully matched this instruction:\n", dump_file); 10923 print_rtl_single (dump_file, pat); 10924 } 10925 10926 /* If it isn't, there is the possibility that we previously had an insn 10927 that clobbered some register as a side effect, but the combined 10928 insn doesn't need to do that. So try once more without the clobbers 10929 unless this represents an ASM insn. */ 10930 10931 if (insn_code_number < 0 && ! check_asm_operands (pat) 10932 && GET_CODE (pat) == PARALLEL) 10933 { 10934 int pos; 10935 10936 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) 10937 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 10938 { 10939 if (i != pos) 10940 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); 10941 pos++; 10942 } 10943 10944 SUBST_INT (XVECLEN (pat, 0), pos); 10945 10946 if (pos == 1) 10947 pat = XVECEXP (pat, 0, 0); 10948 10949 PATTERN (insn) = pat; 10950 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 10951 if (dump_file && (dump_flags & TDF_DETAILS)) 10952 { 10953 if (insn_code_number < 0) 10954 fputs ("Failed to match this instruction:\n", dump_file); 10955 else 10956 fputs ("Successfully matched this instruction:\n", dump_file); 10957 print_rtl_single (dump_file, pat); 10958 } 10959 } 10960 10961 pat_without_clobbers = pat; 10962 10963 PATTERN (insn) = old_pat; 10964 REG_NOTES (insn) = old_notes; 10965 10966 /* Recognize all noop sets, these will be killed by followup pass. */ 10967 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) 10968 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; 10969 10970 /* If we had any clobbers to add, make a new pattern than contains 10971 them. Then check to make sure that all of them are dead. */ 10972 if (num_clobbers_to_add) 10973 { 10974 rtx newpat = gen_rtx_PARALLEL (VOIDmode, 10975 rtvec_alloc (GET_CODE (pat) == PARALLEL 10976 ? (XVECLEN (pat, 0) 10977 + num_clobbers_to_add) 10978 : num_clobbers_to_add + 1)); 10979 10980 if (GET_CODE (pat) == PARALLEL) 10981 for (i = 0; i < XVECLEN (pat, 0); i++) 10982 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); 10983 else 10984 XVECEXP (newpat, 0, 0) = pat; 10985 10986 add_clobbers (newpat, insn_code_number); 10987 10988 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; 10989 i < XVECLEN (newpat, 0); i++) 10990 { 10991 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)) 10992 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) 10993 return -1; 10994 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH) 10995 { 10996 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))); 10997 notes = alloc_reg_note (REG_UNUSED, 10998 XEXP (XVECEXP (newpat, 0, i), 0), notes); 10999 } 11000 } 11001 pat = newpat; 11002 } 11003 11004 if (insn_code_number >= 0 11005 && insn_code_number != NOOP_MOVE_INSN_CODE) 11006 { 11007 old_pat = PATTERN (insn); 11008 old_notes = REG_NOTES (insn); 11009 old_icode = INSN_CODE (insn); 11010 PATTERN (insn) = pat; 11011 REG_NOTES (insn) = notes; 11012 11013 /* Allow targets to reject combined insn. */ 11014 if (!targetm.legitimate_combined_insn (insn)) 11015 { 11016 if (dump_file && (dump_flags & TDF_DETAILS)) 11017 fputs ("Instruction not appropriate for target.", 11018 dump_file); 11019 11020 /* Callers expect recog_for_combine to strip 11021 clobbers from the pattern on failure. */ 11022 pat = pat_without_clobbers; 11023 notes = NULL_RTX; 11024 11025 insn_code_number = -1; 11026 } 11027 11028 PATTERN (insn) = old_pat; 11029 REG_NOTES (insn) = old_notes; 11030 INSN_CODE (insn) = old_icode; 11031 } 11032 11033 *pnewpat = pat; 11034 *pnotes = notes; 11035 11036 return insn_code_number; 11037 } 11038 11039 /* Like gen_lowpart_general but for use by combine. In combine it 11040 is not possible to create any new pseudoregs. However, it is 11041 safe to create invalid memory addresses, because combine will 11042 try to recognize them and all they will do is make the combine 11043 attempt fail. 11044 11045 If for some reason this cannot do its job, an rtx 11046 (clobber (const_int 0)) is returned. 11047 An insn containing that will not be recognized. */ 11048 11049 static rtx 11050 gen_lowpart_for_combine (machine_mode omode, rtx x) 11051 { 11052 machine_mode imode = GET_MODE (x); 11053 unsigned int osize = GET_MODE_SIZE (omode); 11054 unsigned int isize = GET_MODE_SIZE (imode); 11055 rtx result; 11056 11057 if (omode == imode) 11058 return x; 11059 11060 /* We can only support MODE being wider than a word if X is a 11061 constant integer or has a mode the same size. */ 11062 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD 11063 && ! (CONST_SCALAR_INT_P (x) || isize == osize)) 11064 goto fail; 11065 11066 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart 11067 won't know what to do. So we will strip off the SUBREG here and 11068 process normally. */ 11069 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) 11070 { 11071 x = SUBREG_REG (x); 11072 11073 /* For use in case we fall down into the address adjustments 11074 further below, we need to adjust the known mode and size of 11075 x; imode and isize, since we just adjusted x. */ 11076 imode = GET_MODE (x); 11077 11078 if (imode == omode) 11079 return x; 11080 11081 isize = GET_MODE_SIZE (imode); 11082 } 11083 11084 result = gen_lowpart_common (omode, x); 11085 11086 if (result) 11087 return result; 11088 11089 if (MEM_P (x)) 11090 { 11091 int offset = 0; 11092 11093 /* Refuse to work on a volatile memory ref or one with a mode-dependent 11094 address. */ 11095 if (MEM_VOLATILE_P (x) 11096 || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x))) 11097 goto fail; 11098 11099 /* If we want to refer to something bigger than the original memref, 11100 generate a paradoxical subreg instead. That will force a reload 11101 of the original memref X. */ 11102 if (isize < osize) 11103 return gen_rtx_SUBREG (omode, x, 0); 11104 11105 if (WORDS_BIG_ENDIAN) 11106 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD); 11107 11108 /* Adjust the address so that the address-after-the-data is 11109 unchanged. */ 11110 if (BYTES_BIG_ENDIAN) 11111 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize); 11112 11113 return adjust_address_nv (x, omode, offset); 11114 } 11115 11116 /* If X is a comparison operator, rewrite it in a new mode. This 11117 probably won't match, but may allow further simplifications. */ 11118 else if (COMPARISON_P (x)) 11119 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1)); 11120 11121 /* If we couldn't simplify X any other way, just enclose it in a 11122 SUBREG. Normally, this SUBREG won't match, but some patterns may 11123 include an explicit SUBREG or we may simplify it further in combine. */ 11124 else 11125 { 11126 int offset = 0; 11127 rtx res; 11128 11129 offset = subreg_lowpart_offset (omode, imode); 11130 if (imode == VOIDmode) 11131 { 11132 imode = int_mode_for_mode (omode); 11133 x = gen_lowpart_common (imode, x); 11134 if (x == NULL) 11135 goto fail; 11136 } 11137 res = simplify_gen_subreg (omode, x, imode, offset); 11138 if (res) 11139 return res; 11140 } 11141 11142 fail: 11143 return gen_rtx_CLOBBER (omode, const0_rtx); 11144 } 11145 11146 /* Try to simplify a comparison between OP0 and a constant OP1, 11147 where CODE is the comparison code that will be tested, into a 11148 (CODE OP0 const0_rtx) form. 11149 11150 The result is a possibly different comparison code to use. 11151 *POP1 may be updated. */ 11152 11153 static enum rtx_code 11154 simplify_compare_const (enum rtx_code code, machine_mode mode, 11155 rtx op0, rtx *pop1) 11156 { 11157 unsigned int mode_width = GET_MODE_PRECISION (mode); 11158 HOST_WIDE_INT const_op = INTVAL (*pop1); 11159 11160 /* Get the constant we are comparing against and turn off all bits 11161 not on in our mode. */ 11162 if (mode != VOIDmode) 11163 const_op = trunc_int_for_mode (const_op, mode); 11164 11165 /* If we are comparing against a constant power of two and the value 11166 being compared can only have that single bit nonzero (e.g., it was 11167 `and'ed with that bit), we can replace this with a comparison 11168 with zero. */ 11169 if (const_op 11170 && (code == EQ || code == NE || code == GE || code == GEU 11171 || code == LT || code == LTU) 11172 && mode_width - 1 < HOST_BITS_PER_WIDE_INT 11173 && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0 11174 && (nonzero_bits (op0, mode) 11175 == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode)))) 11176 { 11177 code = (code == EQ || code == GE || code == GEU ? NE : EQ); 11178 const_op = 0; 11179 } 11180 11181 /* Similarly, if we are comparing a value known to be either -1 or 11182 0 with -1, change it to the opposite comparison against zero. */ 11183 if (const_op == -1 11184 && (code == EQ || code == NE || code == GT || code == LE 11185 || code == GEU || code == LTU) 11186 && num_sign_bit_copies (op0, mode) == mode_width) 11187 { 11188 code = (code == EQ || code == LE || code == GEU ? NE : EQ); 11189 const_op = 0; 11190 } 11191 11192 /* Do some canonicalizations based on the comparison code. We prefer 11193 comparisons against zero and then prefer equality comparisons. 11194 If we can reduce the size of a constant, we will do that too. */ 11195 switch (code) 11196 { 11197 case LT: 11198 /* < C is equivalent to <= (C - 1) */ 11199 if (const_op > 0) 11200 { 11201 const_op -= 1; 11202 code = LE; 11203 /* ... fall through to LE case below. */ 11204 } 11205 else 11206 break; 11207 11208 case LE: 11209 /* <= C is equivalent to < (C + 1); we do this for C < 0 */ 11210 if (const_op < 0) 11211 { 11212 const_op += 1; 11213 code = LT; 11214 } 11215 11216 /* If we are doing a <= 0 comparison on a value known to have 11217 a zero sign bit, we can replace this with == 0. */ 11218 else if (const_op == 0 11219 && mode_width - 1 < HOST_BITS_PER_WIDE_INT 11220 && (nonzero_bits (op0, mode) 11221 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 11222 == 0) 11223 code = EQ; 11224 break; 11225 11226 case GE: 11227 /* >= C is equivalent to > (C - 1). */ 11228 if (const_op > 0) 11229 { 11230 const_op -= 1; 11231 code = GT; 11232 /* ... fall through to GT below. */ 11233 } 11234 else 11235 break; 11236 11237 case GT: 11238 /* > C is equivalent to >= (C + 1); we do this for C < 0. */ 11239 if (const_op < 0) 11240 { 11241 const_op += 1; 11242 code = GE; 11243 } 11244 11245 /* If we are doing a > 0 comparison on a value known to have 11246 a zero sign bit, we can replace this with != 0. */ 11247 else if (const_op == 0 11248 && mode_width - 1 < HOST_BITS_PER_WIDE_INT 11249 && (nonzero_bits (op0, mode) 11250 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 11251 == 0) 11252 code = NE; 11253 break; 11254 11255 case LTU: 11256 /* < C is equivalent to <= (C - 1). */ 11257 if (const_op > 0) 11258 { 11259 const_op -= 1; 11260 code = LEU; 11261 /* ... fall through ... */ 11262 } 11263 /* (unsigned) < 0x80000000 is equivalent to >= 0. */ 11264 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT 11265 && (unsigned HOST_WIDE_INT) const_op 11266 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) 11267 { 11268 const_op = 0; 11269 code = GE; 11270 break; 11271 } 11272 else 11273 break; 11274 11275 case LEU: 11276 /* unsigned <= 0 is equivalent to == 0 */ 11277 if (const_op == 0) 11278 code = EQ; 11279 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ 11280 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT 11281 && (unsigned HOST_WIDE_INT) const_op 11282 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1) 11283 { 11284 const_op = 0; 11285 code = GE; 11286 } 11287 break; 11288 11289 case GEU: 11290 /* >= C is equivalent to > (C - 1). */ 11291 if (const_op > 1) 11292 { 11293 const_op -= 1; 11294 code = GTU; 11295 /* ... fall through ... */ 11296 } 11297 11298 /* (unsigned) >= 0x80000000 is equivalent to < 0. */ 11299 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT 11300 && (unsigned HOST_WIDE_INT) const_op 11301 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) 11302 { 11303 const_op = 0; 11304 code = LT; 11305 break; 11306 } 11307 else 11308 break; 11309 11310 case GTU: 11311 /* unsigned > 0 is equivalent to != 0 */ 11312 if (const_op == 0) 11313 code = NE; 11314 /* (unsigned) > 0x7fffffff is equivalent to < 0. */ 11315 else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT 11316 && (unsigned HOST_WIDE_INT) const_op 11317 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1) 11318 { 11319 const_op = 0; 11320 code = LT; 11321 } 11322 break; 11323 11324 default: 11325 break; 11326 } 11327 11328 *pop1 = GEN_INT (const_op); 11329 return code; 11330 } 11331 11332 /* Simplify a comparison between *POP0 and *POP1 where CODE is the 11333 comparison code that will be tested. 11334 11335 The result is a possibly different comparison code to use. *POP0 and 11336 *POP1 may be updated. 11337 11338 It is possible that we might detect that a comparison is either always 11339 true or always false. However, we do not perform general constant 11340 folding in combine, so this knowledge isn't useful. Such tautologies 11341 should have been detected earlier. Hence we ignore all such cases. */ 11342 11343 static enum rtx_code 11344 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) 11345 { 11346 rtx op0 = *pop0; 11347 rtx op1 = *pop1; 11348 rtx tem, tem1; 11349 int i; 11350 machine_mode mode, tmode; 11351 11352 /* Try a few ways of applying the same transformation to both operands. */ 11353 while (1) 11354 { 11355 #ifndef WORD_REGISTER_OPERATIONS 11356 /* The test below this one won't handle SIGN_EXTENDs on these machines, 11357 so check specially. */ 11358 if (code != GTU && code != GEU && code != LTU && code != LEU 11359 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT 11360 && GET_CODE (XEXP (op0, 0)) == ASHIFT 11361 && GET_CODE (XEXP (op1, 0)) == ASHIFT 11362 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG 11363 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG 11364 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) 11365 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) 11366 && CONST_INT_P (XEXP (op0, 1)) 11367 && XEXP (op0, 1) == XEXP (op1, 1) 11368 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 11369 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1) 11370 && (INTVAL (XEXP (op0, 1)) 11371 == (GET_MODE_PRECISION (GET_MODE (op0)) 11372 - (GET_MODE_PRECISION 11373 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) 11374 { 11375 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); 11376 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); 11377 } 11378 #endif 11379 11380 /* If both operands are the same constant shift, see if we can ignore the 11381 shift. We can if the shift is a rotate or if the bits shifted out of 11382 this shift are known to be zero for both inputs and if the type of 11383 comparison is compatible with the shift. */ 11384 if (GET_CODE (op0) == GET_CODE (op1) 11385 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0)) 11386 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) 11387 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) 11388 && (code != GT && code != LT && code != GE && code != LE)) 11389 || (GET_CODE (op0) == ASHIFTRT 11390 && (code != GTU && code != LTU 11391 && code != GEU && code != LEU))) 11392 && CONST_INT_P (XEXP (op0, 1)) 11393 && INTVAL (XEXP (op0, 1)) >= 0 11394 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 11395 && XEXP (op0, 1) == XEXP (op1, 1)) 11396 { 11397 machine_mode mode = GET_MODE (op0); 11398 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 11399 int shift_count = INTVAL (XEXP (op0, 1)); 11400 11401 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) 11402 mask &= (mask >> shift_count) << shift_count; 11403 else if (GET_CODE (op0) == ASHIFT) 11404 mask = (mask & (mask << shift_count)) >> shift_count; 11405 11406 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 11407 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) 11408 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); 11409 else 11410 break; 11411 } 11412 11413 /* If both operands are AND's of a paradoxical SUBREG by constant, the 11414 SUBREGs are of the same mode, and, in both cases, the AND would 11415 be redundant if the comparison was done in the narrower mode, 11416 do the comparison in the narrower mode (e.g., we are AND'ing with 1 11417 and the operand's possibly nonzero bits are 0xffffff01; in that case 11418 if we only care about QImode, we don't need the AND). This case 11419 occurs if the output mode of an scc insn is not SImode and 11420 STORE_FLAG_VALUE == 1 (e.g., the 386). 11421 11422 Similarly, check for a case where the AND's are ZERO_EXTEND 11423 operations from some narrower mode even though a SUBREG is not 11424 present. */ 11425 11426 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND 11427 && CONST_INT_P (XEXP (op0, 1)) 11428 && CONST_INT_P (XEXP (op1, 1))) 11429 { 11430 rtx inner_op0 = XEXP (op0, 0); 11431 rtx inner_op1 = XEXP (op1, 0); 11432 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); 11433 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); 11434 int changed = 0; 11435 11436 if (paradoxical_subreg_p (inner_op0) 11437 && GET_CODE (inner_op1) == SUBREG 11438 && (GET_MODE (SUBREG_REG (inner_op0)) 11439 == GET_MODE (SUBREG_REG (inner_op1))) 11440 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0))) 11441 <= HOST_BITS_PER_WIDE_INT) 11442 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), 11443 GET_MODE (SUBREG_REG (inner_op0))))) 11444 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), 11445 GET_MODE (SUBREG_REG (inner_op1)))))) 11446 { 11447 op0 = SUBREG_REG (inner_op0); 11448 op1 = SUBREG_REG (inner_op1); 11449 11450 /* The resulting comparison is always unsigned since we masked 11451 off the original sign bit. */ 11452 code = unsigned_condition (code); 11453 11454 changed = 1; 11455 } 11456 11457 else if (c0 == c1) 11458 for (tmode = GET_CLASS_NARROWEST_MODE 11459 (GET_MODE_CLASS (GET_MODE (op0))); 11460 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) 11461 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) 11462 { 11463 op0 = gen_lowpart_or_truncate (tmode, inner_op0); 11464 op1 = gen_lowpart_or_truncate (tmode, inner_op1); 11465 code = unsigned_condition (code); 11466 changed = 1; 11467 break; 11468 } 11469 11470 if (! changed) 11471 break; 11472 } 11473 11474 /* If both operands are NOT, we can strip off the outer operation 11475 and adjust the comparison code for swapped operands; similarly for 11476 NEG, except that this must be an equality comparison. */ 11477 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) 11478 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG 11479 && (code == EQ || code == NE))) 11480 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); 11481 11482 else 11483 break; 11484 } 11485 11486 /* If the first operand is a constant, swap the operands and adjust the 11487 comparison code appropriately, but don't do this if the second operand 11488 is already a constant integer. */ 11489 if (swap_commutative_operands_p (op0, op1)) 11490 { 11491 tem = op0, op0 = op1, op1 = tem; 11492 code = swap_condition (code); 11493 } 11494 11495 /* We now enter a loop during which we will try to simplify the comparison. 11496 For the most part, we only are concerned with comparisons with zero, 11497 but some things may really be comparisons with zero but not start 11498 out looking that way. */ 11499 11500 while (CONST_INT_P (op1)) 11501 { 11502 machine_mode mode = GET_MODE (op0); 11503 unsigned int mode_width = GET_MODE_PRECISION (mode); 11504 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 11505 int equality_comparison_p; 11506 int sign_bit_comparison_p; 11507 int unsigned_comparison_p; 11508 HOST_WIDE_INT const_op; 11509 11510 /* We only want to handle integral modes. This catches VOIDmode, 11511 CCmode, and the floating-point modes. An exception is that we 11512 can handle VOIDmode if OP0 is a COMPARE or a comparison 11513 operation. */ 11514 11515 if (GET_MODE_CLASS (mode) != MODE_INT 11516 && ! (mode == VOIDmode 11517 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0)))) 11518 break; 11519 11520 /* Try to simplify the compare to constant, possibly changing the 11521 comparison op, and/or changing op1 to zero. */ 11522 code = simplify_compare_const (code, mode, op0, &op1); 11523 const_op = INTVAL (op1); 11524 11525 /* Compute some predicates to simplify code below. */ 11526 11527 equality_comparison_p = (code == EQ || code == NE); 11528 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); 11529 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU 11530 || code == GEU); 11531 11532 /* If this is a sign bit comparison and we can do arithmetic in 11533 MODE, say that we will only be needing the sign bit of OP0. */ 11534 if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode)) 11535 op0 = force_to_mode (op0, mode, 11536 (unsigned HOST_WIDE_INT) 1 11537 << (GET_MODE_PRECISION (mode) - 1), 11538 0); 11539 11540 /* Now try cases based on the opcode of OP0. If none of the cases 11541 does a "continue", we exit this loop immediately after the 11542 switch. */ 11543 11544 switch (GET_CODE (op0)) 11545 { 11546 case ZERO_EXTRACT: 11547 /* If we are extracting a single bit from a variable position in 11548 a constant that has only a single bit set and are comparing it 11549 with zero, we can convert this into an equality comparison 11550 between the position and the location of the single bit. */ 11551 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might 11552 have already reduced the shift count modulo the word size. */ 11553 if (!SHIFT_COUNT_TRUNCATED 11554 && CONST_INT_P (XEXP (op0, 0)) 11555 && XEXP (op0, 1) == const1_rtx 11556 && equality_comparison_p && const_op == 0 11557 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0) 11558 { 11559 if (BITS_BIG_ENDIAN) 11560 i = BITS_PER_WORD - 1 - i; 11561 11562 op0 = XEXP (op0, 2); 11563 op1 = GEN_INT (i); 11564 const_op = i; 11565 11566 /* Result is nonzero iff shift count is equal to I. */ 11567 code = reverse_condition (code); 11568 continue; 11569 } 11570 11571 /* ... fall through ... */ 11572 11573 case SIGN_EXTRACT: 11574 tem = expand_compound_operation (op0); 11575 if (tem != op0) 11576 { 11577 op0 = tem; 11578 continue; 11579 } 11580 break; 11581 11582 case NOT: 11583 /* If testing for equality, we can take the NOT of the constant. */ 11584 if (equality_comparison_p 11585 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) 11586 { 11587 op0 = XEXP (op0, 0); 11588 op1 = tem; 11589 continue; 11590 } 11591 11592 /* If just looking at the sign bit, reverse the sense of the 11593 comparison. */ 11594 if (sign_bit_comparison_p) 11595 { 11596 op0 = XEXP (op0, 0); 11597 code = (code == GE ? LT : GE); 11598 continue; 11599 } 11600 break; 11601 11602 case NEG: 11603 /* If testing for equality, we can take the NEG of the constant. */ 11604 if (equality_comparison_p 11605 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) 11606 { 11607 op0 = XEXP (op0, 0); 11608 op1 = tem; 11609 continue; 11610 } 11611 11612 /* The remaining cases only apply to comparisons with zero. */ 11613 if (const_op != 0) 11614 break; 11615 11616 /* When X is ABS or is known positive, 11617 (neg X) is < 0 if and only if X != 0. */ 11618 11619 if (sign_bit_comparison_p 11620 && (GET_CODE (XEXP (op0, 0)) == ABS 11621 || (mode_width <= HOST_BITS_PER_WIDE_INT 11622 && (nonzero_bits (XEXP (op0, 0), mode) 11623 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 11624 == 0))) 11625 { 11626 op0 = XEXP (op0, 0); 11627 code = (code == LT ? NE : EQ); 11628 continue; 11629 } 11630 11631 /* If we have NEG of something whose two high-order bits are the 11632 same, we know that "(-a) < 0" is equivalent to "a > 0". */ 11633 if (num_sign_bit_copies (op0, mode) >= 2) 11634 { 11635 op0 = XEXP (op0, 0); 11636 code = swap_condition (code); 11637 continue; 11638 } 11639 break; 11640 11641 case ROTATE: 11642 /* If we are testing equality and our count is a constant, we 11643 can perform the inverse operation on our RHS. */ 11644 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1)) 11645 && (tem = simplify_binary_operation (ROTATERT, mode, 11646 op1, XEXP (op0, 1))) != 0) 11647 { 11648 op0 = XEXP (op0, 0); 11649 op1 = tem; 11650 continue; 11651 } 11652 11653 /* If we are doing a < 0 or >= 0 comparison, it means we are testing 11654 a particular bit. Convert it to an AND of a constant of that 11655 bit. This will be converted into a ZERO_EXTRACT. */ 11656 if (const_op == 0 && sign_bit_comparison_p 11657 && CONST_INT_P (XEXP (op0, 1)) 11658 && mode_width <= HOST_BITS_PER_WIDE_INT) 11659 { 11660 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 11661 ((unsigned HOST_WIDE_INT) 1 11662 << (mode_width - 1 11663 - INTVAL (XEXP (op0, 1))))); 11664 code = (code == LT ? NE : EQ); 11665 continue; 11666 } 11667 11668 /* Fall through. */ 11669 11670 case ABS: 11671 /* ABS is ignorable inside an equality comparison with zero. */ 11672 if (const_op == 0 && equality_comparison_p) 11673 { 11674 op0 = XEXP (op0, 0); 11675 continue; 11676 } 11677 break; 11678 11679 case SIGN_EXTEND: 11680 /* Can simplify (compare (zero/sign_extend FOO) CONST) to 11681 (compare FOO CONST) if CONST fits in FOO's mode and we 11682 are either testing inequality or have an unsigned 11683 comparison with ZERO_EXTEND or a signed comparison with 11684 SIGN_EXTEND. But don't do it if we don't have a compare 11685 insn of the given mode, since we'd have to revert it 11686 later on, and then we wouldn't know whether to sign- or 11687 zero-extend. */ 11688 mode = GET_MODE (XEXP (op0, 0)); 11689 if (GET_MODE_CLASS (mode) == MODE_INT 11690 && ! unsigned_comparison_p 11691 && HWI_COMPUTABLE_MODE_P (mode) 11692 && trunc_int_for_mode (const_op, mode) == const_op 11693 && have_insn_for (COMPARE, mode)) 11694 { 11695 op0 = XEXP (op0, 0); 11696 continue; 11697 } 11698 break; 11699 11700 case SUBREG: 11701 /* Check for the case where we are comparing A - C1 with C2, that is 11702 11703 (subreg:MODE (plus (A) (-C1))) op (C2) 11704 11705 with C1 a constant, and try to lift the SUBREG, i.e. to do the 11706 comparison in the wider mode. One of the following two conditions 11707 must be true in order for this to be valid: 11708 11709 1. The mode extension results in the same bit pattern being added 11710 on both sides and the comparison is equality or unsigned. As 11711 C2 has been truncated to fit in MODE, the pattern can only be 11712 all 0s or all 1s. 11713 11714 2. The mode extension results in the sign bit being copied on 11715 each side. 11716 11717 The difficulty here is that we have predicates for A but not for 11718 (A - C1) so we need to check that C1 is within proper bounds so 11719 as to perturbate A as little as possible. */ 11720 11721 if (mode_width <= HOST_BITS_PER_WIDE_INT 11722 && subreg_lowpart_p (op0) 11723 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width 11724 && GET_CODE (SUBREG_REG (op0)) == PLUS 11725 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1))) 11726 { 11727 machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); 11728 rtx a = XEXP (SUBREG_REG (op0), 0); 11729 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1)); 11730 11731 if ((c1 > 0 11732 && (unsigned HOST_WIDE_INT) c1 11733 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1) 11734 && (equality_comparison_p || unsigned_comparison_p) 11735 /* (A - C1) zero-extends if it is positive and sign-extends 11736 if it is negative, C2 both zero- and sign-extends. */ 11737 && ((0 == (nonzero_bits (a, inner_mode) 11738 & ~GET_MODE_MASK (mode)) 11739 && const_op >= 0) 11740 /* (A - C1) sign-extends if it is positive and 1-extends 11741 if it is negative, C2 both sign- and 1-extends. */ 11742 || (num_sign_bit_copies (a, inner_mode) 11743 > (unsigned int) (GET_MODE_PRECISION (inner_mode) 11744 - mode_width) 11745 && const_op < 0))) 11746 || ((unsigned HOST_WIDE_INT) c1 11747 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2) 11748 /* (A - C1) always sign-extends, like C2. */ 11749 && num_sign_bit_copies (a, inner_mode) 11750 > (unsigned int) (GET_MODE_PRECISION (inner_mode) 11751 - (mode_width - 1)))) 11752 { 11753 op0 = SUBREG_REG (op0); 11754 continue; 11755 } 11756 } 11757 11758 /* If the inner mode is narrower and we are extracting the low part, 11759 we can treat the SUBREG as if it were a ZERO_EXTEND. */ 11760 if (subreg_lowpart_p (op0) 11761 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width) 11762 /* Fall through */ ; 11763 else 11764 break; 11765 11766 /* ... fall through ... */ 11767 11768 case ZERO_EXTEND: 11769 mode = GET_MODE (XEXP (op0, 0)); 11770 if (GET_MODE_CLASS (mode) == MODE_INT 11771 && (unsigned_comparison_p || equality_comparison_p) 11772 && HWI_COMPUTABLE_MODE_P (mode) 11773 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode) 11774 && const_op >= 0 11775 && have_insn_for (COMPARE, mode)) 11776 { 11777 op0 = XEXP (op0, 0); 11778 continue; 11779 } 11780 break; 11781 11782 case PLUS: 11783 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do 11784 this for equality comparisons due to pathological cases involving 11785 overflows. */ 11786 if (equality_comparison_p 11787 && 0 != (tem = simplify_binary_operation (MINUS, mode, 11788 op1, XEXP (op0, 1)))) 11789 { 11790 op0 = XEXP (op0, 0); 11791 op1 = tem; 11792 continue; 11793 } 11794 11795 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ 11796 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx 11797 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) 11798 { 11799 op0 = XEXP (XEXP (op0, 0), 0); 11800 code = (code == LT ? EQ : NE); 11801 continue; 11802 } 11803 break; 11804 11805 case MINUS: 11806 /* We used to optimize signed comparisons against zero, but that 11807 was incorrect. Unsigned comparisons against zero (GTU, LEU) 11808 arrive here as equality comparisons, or (GEU, LTU) are 11809 optimized away. No need to special-case them. */ 11810 11811 /* (eq (minus A B) C) -> (eq A (plus B C)) or 11812 (eq B (minus A C)), whichever simplifies. We can only do 11813 this for equality comparisons due to pathological cases involving 11814 overflows. */ 11815 if (equality_comparison_p 11816 && 0 != (tem = simplify_binary_operation (PLUS, mode, 11817 XEXP (op0, 1), op1))) 11818 { 11819 op0 = XEXP (op0, 0); 11820 op1 = tem; 11821 continue; 11822 } 11823 11824 if (equality_comparison_p 11825 && 0 != (tem = simplify_binary_operation (MINUS, mode, 11826 XEXP (op0, 0), op1))) 11827 { 11828 op0 = XEXP (op0, 1); 11829 op1 = tem; 11830 continue; 11831 } 11832 11833 /* The sign bit of (minus (ashiftrt X C) X), where C is the number 11834 of bits in X minus 1, is one iff X > 0. */ 11835 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT 11836 && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) 11837 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 11838 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 11839 { 11840 op0 = XEXP (op0, 1); 11841 code = (code == GE ? LE : GT); 11842 continue; 11843 } 11844 break; 11845 11846 case XOR: 11847 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification 11848 if C is zero or B is a constant. */ 11849 if (equality_comparison_p 11850 && 0 != (tem = simplify_binary_operation (XOR, mode, 11851 XEXP (op0, 1), op1))) 11852 { 11853 op0 = XEXP (op0, 0); 11854 op1 = tem; 11855 continue; 11856 } 11857 break; 11858 11859 case EQ: case NE: 11860 case UNEQ: case LTGT: 11861 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: 11862 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: 11863 case UNORDERED: case ORDERED: 11864 /* We can't do anything if OP0 is a condition code value, rather 11865 than an actual data value. */ 11866 if (const_op != 0 11867 || CC0_P (XEXP (op0, 0)) 11868 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) 11869 break; 11870 11871 /* Get the two operands being compared. */ 11872 if (GET_CODE (XEXP (op0, 0)) == COMPARE) 11873 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); 11874 else 11875 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); 11876 11877 /* Check for the cases where we simply want the result of the 11878 earlier test or the opposite of that result. */ 11879 if (code == NE || code == EQ 11880 || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE) 11881 && (code == LT || code == GE))) 11882 { 11883 enum rtx_code new_code; 11884 if (code == LT || code == NE) 11885 new_code = GET_CODE (op0); 11886 else 11887 new_code = reversed_comparison_code (op0, NULL); 11888 11889 if (new_code != UNKNOWN) 11890 { 11891 code = new_code; 11892 op0 = tem; 11893 op1 = tem1; 11894 continue; 11895 } 11896 } 11897 break; 11898 11899 case IOR: 11900 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero 11901 iff X <= 0. */ 11902 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS 11903 && XEXP (XEXP (op0, 0), 1) == constm1_rtx 11904 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 11905 { 11906 op0 = XEXP (op0, 1); 11907 code = (code == GE ? GT : LE); 11908 continue; 11909 } 11910 break; 11911 11912 case AND: 11913 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This 11914 will be converted to a ZERO_EXTRACT later. */ 11915 if (const_op == 0 && equality_comparison_p 11916 && GET_CODE (XEXP (op0, 0)) == ASHIFT 11917 && XEXP (XEXP (op0, 0), 0) == const1_rtx) 11918 { 11919 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1), 11920 XEXP (XEXP (op0, 0), 1)); 11921 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1); 11922 continue; 11923 } 11924 11925 /* If we are comparing (and (lshiftrt X C1) C2) for equality with 11926 zero and X is a comparison and C1 and C2 describe only bits set 11927 in STORE_FLAG_VALUE, we can compare with X. */ 11928 if (const_op == 0 && equality_comparison_p 11929 && mode_width <= HOST_BITS_PER_WIDE_INT 11930 && CONST_INT_P (XEXP (op0, 1)) 11931 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 11932 && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) 11933 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 11934 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) 11935 { 11936 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 11937 << INTVAL (XEXP (XEXP (op0, 0), 1))); 11938 if ((~STORE_FLAG_VALUE & mask) == 0 11939 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0)) 11940 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 11941 && COMPARISON_P (tem)))) 11942 { 11943 op0 = XEXP (XEXP (op0, 0), 0); 11944 continue; 11945 } 11946 } 11947 11948 /* If we are doing an equality comparison of an AND of a bit equal 11949 to the sign bit, replace this with a LT or GE comparison of 11950 the underlying value. */ 11951 if (equality_comparison_p 11952 && const_op == 0 11953 && CONST_INT_P (XEXP (op0, 1)) 11954 && mode_width <= HOST_BITS_PER_WIDE_INT 11955 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 11956 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 11957 { 11958 op0 = XEXP (op0, 0); 11959 code = (code == EQ ? GE : LT); 11960 continue; 11961 } 11962 11963 /* If this AND operation is really a ZERO_EXTEND from a narrower 11964 mode, the constant fits within that mode, and this is either an 11965 equality or unsigned comparison, try to do this comparison in 11966 the narrower mode. 11967 11968 Note that in: 11969 11970 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0)) 11971 -> (ne:DI (reg:SI 4) (const_int 0)) 11972 11973 unless TRULY_NOOP_TRUNCATION allows it or the register is 11974 known to hold a value of the required mode the 11975 transformation is invalid. */ 11976 if ((equality_comparison_p || unsigned_comparison_p) 11977 && CONST_INT_P (XEXP (op0, 1)) 11978 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1)) 11979 & GET_MODE_MASK (mode)) 11980 + 1)) >= 0 11981 && const_op >> i == 0 11982 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) 11983 { 11984 op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0)); 11985 continue; 11986 } 11987 11988 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1 11989 fits in both M1 and M2 and the SUBREG is either paradoxical 11990 or represents the low part, permute the SUBREG and the AND 11991 and try again. */ 11992 if (GET_CODE (XEXP (op0, 0)) == SUBREG 11993 && CONST_INT_P (XEXP (op0, 1))) 11994 { 11995 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0))); 11996 unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1)); 11997 /* Require an integral mode, to avoid creating something like 11998 (AND:SF ...). */ 11999 if (SCALAR_INT_MODE_P (tmode) 12000 /* It is unsafe to commute the AND into the SUBREG if the 12001 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is 12002 not defined. As originally written the upper bits 12003 have a defined value due to the AND operation. 12004 However, if we commute the AND inside the SUBREG then 12005 they no longer have defined values and the meaning of 12006 the code has been changed. 12007 Also C1 should not change value in the smaller mode, 12008 see PR67028 (a positive C1 can become negative in the 12009 smaller mode, so that the AND does no longer mask the 12010 upper bits). */ 12011 && (0 12012 #ifdef WORD_REGISTER_OPERATIONS 12013 || (mode_width > GET_MODE_PRECISION (tmode) 12014 && mode_width <= BITS_PER_WORD 12015 && trunc_int_for_mode (c1, tmode) == (HOST_WIDE_INT) c1) 12016 #endif 12017 || (mode_width <= GET_MODE_PRECISION (tmode) 12018 && subreg_lowpart_p (XEXP (op0, 0)))) 12019 && mode_width <= HOST_BITS_PER_WIDE_INT 12020 && HWI_COMPUTABLE_MODE_P (tmode) 12021 && (c1 & ~mask) == 0 12022 && (c1 & ~GET_MODE_MASK (tmode)) == 0 12023 && c1 != mask 12024 && c1 != GET_MODE_MASK (tmode)) 12025 { 12026 op0 = simplify_gen_binary (AND, tmode, 12027 SUBREG_REG (XEXP (op0, 0)), 12028 gen_int_mode (c1, tmode)); 12029 op0 = gen_lowpart (mode, op0); 12030 continue; 12031 } 12032 } 12033 12034 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */ 12035 if (const_op == 0 && equality_comparison_p 12036 && XEXP (op0, 1) == const1_rtx 12037 && GET_CODE (XEXP (op0, 0)) == NOT) 12038 { 12039 op0 = simplify_and_const_int (NULL_RTX, mode, 12040 XEXP (XEXP (op0, 0), 0), 1); 12041 code = (code == NE ? EQ : NE); 12042 continue; 12043 } 12044 12045 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to 12046 (eq (and (lshiftrt X) 1) 0). 12047 Also handle the case where (not X) is expressed using xor. */ 12048 if (const_op == 0 && equality_comparison_p 12049 && XEXP (op0, 1) == const1_rtx 12050 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT) 12051 { 12052 rtx shift_op = XEXP (XEXP (op0, 0), 0); 12053 rtx shift_count = XEXP (XEXP (op0, 0), 1); 12054 12055 if (GET_CODE (shift_op) == NOT 12056 || (GET_CODE (shift_op) == XOR 12057 && CONST_INT_P (XEXP (shift_op, 1)) 12058 && CONST_INT_P (shift_count) 12059 && HWI_COMPUTABLE_MODE_P (mode) 12060 && (UINTVAL (XEXP (shift_op, 1)) 12061 == (unsigned HOST_WIDE_INT) 1 12062 << INTVAL (shift_count)))) 12063 { 12064 op0 12065 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count); 12066 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1); 12067 code = (code == NE ? EQ : NE); 12068 continue; 12069 } 12070 } 12071 break; 12072 12073 case ASHIFT: 12074 /* If we have (compare (ashift FOO N) (const_int C)) and 12075 the high order N bits of FOO (N+1 if an inequality comparison) 12076 are known to be zero, we can do this by comparing FOO with C 12077 shifted right N bits so long as the low-order N bits of C are 12078 zero. */ 12079 if (CONST_INT_P (XEXP (op0, 1)) 12080 && INTVAL (XEXP (op0, 1)) >= 0 12081 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) 12082 < HOST_BITS_PER_WIDE_INT) 12083 && (((unsigned HOST_WIDE_INT) const_op 12084 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) 12085 - 1)) == 0) 12086 && mode_width <= HOST_BITS_PER_WIDE_INT 12087 && (nonzero_bits (XEXP (op0, 0), mode) 12088 & ~(mask >> (INTVAL (XEXP (op0, 1)) 12089 + ! equality_comparison_p))) == 0) 12090 { 12091 /* We must perform a logical shift, not an arithmetic one, 12092 as we want the top N bits of C to be zero. */ 12093 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); 12094 12095 temp >>= INTVAL (XEXP (op0, 1)); 12096 op1 = gen_int_mode (temp, mode); 12097 op0 = XEXP (op0, 0); 12098 continue; 12099 } 12100 12101 /* If we are doing a sign bit comparison, it means we are testing 12102 a particular bit. Convert it to the appropriate AND. */ 12103 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1)) 12104 && mode_width <= HOST_BITS_PER_WIDE_INT) 12105 { 12106 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 12107 ((unsigned HOST_WIDE_INT) 1 12108 << (mode_width - 1 12109 - INTVAL (XEXP (op0, 1))))); 12110 code = (code == LT ? NE : EQ); 12111 continue; 12112 } 12113 12114 /* If this an equality comparison with zero and we are shifting 12115 the low bit to the sign bit, we can convert this to an AND of the 12116 low-order bit. */ 12117 if (const_op == 0 && equality_comparison_p 12118 && CONST_INT_P (XEXP (op0, 1)) 12119 && UINTVAL (XEXP (op0, 1)) == mode_width - 1) 12120 { 12121 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1); 12122 continue; 12123 } 12124 break; 12125 12126 case ASHIFTRT: 12127 /* If this is an equality comparison with zero, we can do this 12128 as a logical shift, which might be much simpler. */ 12129 if (equality_comparison_p && const_op == 0 12130 && CONST_INT_P (XEXP (op0, 1))) 12131 { 12132 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, 12133 XEXP (op0, 0), 12134 INTVAL (XEXP (op0, 1))); 12135 continue; 12136 } 12137 12138 /* If OP0 is a sign extension and CODE is not an unsigned comparison, 12139 do the comparison in a narrower mode. */ 12140 if (! unsigned_comparison_p 12141 && CONST_INT_P (XEXP (op0, 1)) 12142 && GET_CODE (XEXP (op0, 0)) == ASHIFT 12143 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 12144 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 12145 MODE_INT, 1)) != BLKmode 12146 && (((unsigned HOST_WIDE_INT) const_op 12147 + (GET_MODE_MASK (tmode) >> 1) + 1) 12148 <= GET_MODE_MASK (tmode))) 12149 { 12150 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0)); 12151 continue; 12152 } 12153 12154 /* Likewise if OP0 is a PLUS of a sign extension with a 12155 constant, which is usually represented with the PLUS 12156 between the shifts. */ 12157 if (! unsigned_comparison_p 12158 && CONST_INT_P (XEXP (op0, 1)) 12159 && GET_CODE (XEXP (op0, 0)) == PLUS 12160 && CONST_INT_P (XEXP (XEXP (op0, 0), 1)) 12161 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT 12162 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) 12163 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 12164 MODE_INT, 1)) != BLKmode 12165 && (((unsigned HOST_WIDE_INT) const_op 12166 + (GET_MODE_MASK (tmode) >> 1) + 1) 12167 <= GET_MODE_MASK (tmode))) 12168 { 12169 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); 12170 rtx add_const = XEXP (XEXP (op0, 0), 1); 12171 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0), 12172 add_const, XEXP (op0, 1)); 12173 12174 op0 = simplify_gen_binary (PLUS, tmode, 12175 gen_lowpart (tmode, inner), 12176 new_const); 12177 continue; 12178 } 12179 12180 /* ... fall through ... */ 12181 case LSHIFTRT: 12182 /* If we have (compare (xshiftrt FOO N) (const_int C)) and 12183 the low order N bits of FOO are known to be zero, we can do this 12184 by comparing FOO with C shifted left N bits so long as no 12185 overflow occurs. Even if the low order N bits of FOO aren't known 12186 to be zero, if the comparison is >= or < we can use the same 12187 optimization and for > or <= by setting all the low 12188 order N bits in the comparison constant. */ 12189 if (CONST_INT_P (XEXP (op0, 1)) 12190 && INTVAL (XEXP (op0, 1)) > 0 12191 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 12192 && mode_width <= HOST_BITS_PER_WIDE_INT 12193 && (((unsigned HOST_WIDE_INT) const_op 12194 + (GET_CODE (op0) != LSHIFTRT 12195 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) 12196 + 1) 12197 : 0)) 12198 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) 12199 { 12200 unsigned HOST_WIDE_INT low_bits 12201 = (nonzero_bits (XEXP (op0, 0), mode) 12202 & (((unsigned HOST_WIDE_INT) 1 12203 << INTVAL (XEXP (op0, 1))) - 1)); 12204 if (low_bits == 0 || !equality_comparison_p) 12205 { 12206 /* If the shift was logical, then we must make the condition 12207 unsigned. */ 12208 if (GET_CODE (op0) == LSHIFTRT) 12209 code = unsigned_condition (code); 12210 12211 const_op <<= INTVAL (XEXP (op0, 1)); 12212 if (low_bits != 0 12213 && (code == GT || code == GTU 12214 || code == LE || code == LEU)) 12215 const_op 12216 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1); 12217 op1 = GEN_INT (const_op); 12218 op0 = XEXP (op0, 0); 12219 continue; 12220 } 12221 } 12222 12223 /* If we are using this shift to extract just the sign bit, we 12224 can replace this with an LT or GE comparison. */ 12225 if (const_op == 0 12226 && (equality_comparison_p || sign_bit_comparison_p) 12227 && CONST_INT_P (XEXP (op0, 1)) 12228 && UINTVAL (XEXP (op0, 1)) == mode_width - 1) 12229 { 12230 op0 = XEXP (op0, 0); 12231 code = (code == NE || code == GT ? LT : GE); 12232 continue; 12233 } 12234 break; 12235 12236 default: 12237 break; 12238 } 12239 12240 break; 12241 } 12242 12243 /* Now make any compound operations involved in this comparison. Then, 12244 check for an outmost SUBREG on OP0 that is not doing anything or is 12245 paradoxical. The latter transformation must only be performed when 12246 it is known that the "extra" bits will be the same in op0 and op1 or 12247 that they don't matter. There are three cases to consider: 12248 12249 1. SUBREG_REG (op0) is a register. In this case the bits are don't 12250 care bits and we can assume they have any convenient value. So 12251 making the transformation is safe. 12252 12253 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. 12254 In this case the upper bits of op0 are undefined. We should not make 12255 the simplification in that case as we do not know the contents of 12256 those bits. 12257 12258 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not 12259 UNKNOWN. In that case we know those bits are zeros or ones. We must 12260 also be sure that they are the same as the upper bits of op1. 12261 12262 We can never remove a SUBREG for a non-equality comparison because 12263 the sign bit is in a different place in the underlying object. */ 12264 12265 rtx_code op0_mco_code = SET; 12266 if (op1 == const0_rtx) 12267 op0_mco_code = code == NE || code == EQ ? EQ : COMPARE; 12268 12269 op0 = make_compound_operation (op0, op0_mco_code); 12270 op1 = make_compound_operation (op1, SET); 12271 12272 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 12273 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 12274 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT 12275 && (code == NE || code == EQ)) 12276 { 12277 if (paradoxical_subreg_p (op0)) 12278 { 12279 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't 12280 implemented. */ 12281 if (REG_P (SUBREG_REG (op0))) 12282 { 12283 op0 = SUBREG_REG (op0); 12284 op1 = gen_lowpart (GET_MODE (op0), op1); 12285 } 12286 } 12287 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) 12288 <= HOST_BITS_PER_WIDE_INT) 12289 && (nonzero_bits (SUBREG_REG (op0), 12290 GET_MODE (SUBREG_REG (op0))) 12291 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 12292 { 12293 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1); 12294 12295 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) 12296 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 12297 op0 = SUBREG_REG (op0), op1 = tem; 12298 } 12299 } 12300 12301 /* We now do the opposite procedure: Some machines don't have compare 12302 insns in all modes. If OP0's mode is an integer mode smaller than a 12303 word and we can't do a compare in that mode, see if there is a larger 12304 mode for which we can do the compare. There are a number of cases in 12305 which we can use the wider mode. */ 12306 12307 mode = GET_MODE (op0); 12308 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 12309 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 12310 && ! have_insn_for (COMPARE, mode)) 12311 for (tmode = GET_MODE_WIDER_MODE (mode); 12312 (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode)); 12313 tmode = GET_MODE_WIDER_MODE (tmode)) 12314 if (have_insn_for (COMPARE, tmode)) 12315 { 12316 int zero_extended; 12317 12318 /* If this is a test for negative, we can make an explicit 12319 test of the sign bit. Test this first so we can use 12320 a paradoxical subreg to extend OP0. */ 12321 12322 if (op1 == const0_rtx && (code == LT || code == GE) 12323 && HWI_COMPUTABLE_MODE_P (mode)) 12324 { 12325 unsigned HOST_WIDE_INT sign 12326 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1); 12327 op0 = simplify_gen_binary (AND, tmode, 12328 gen_lowpart (tmode, op0), 12329 gen_int_mode (sign, tmode)); 12330 code = (code == LT) ? NE : EQ; 12331 break; 12332 } 12333 12334 /* If the only nonzero bits in OP0 and OP1 are those in the 12335 narrower mode and this is an equality or unsigned comparison, 12336 we can use the wider mode. Similarly for sign-extended 12337 values, in which case it is true for all comparisons. */ 12338 zero_extended = ((code == EQ || code == NE 12339 || code == GEU || code == GTU 12340 || code == LEU || code == LTU) 12341 && (nonzero_bits (op0, tmode) 12342 & ~GET_MODE_MASK (mode)) == 0 12343 && ((CONST_INT_P (op1) 12344 || (nonzero_bits (op1, tmode) 12345 & ~GET_MODE_MASK (mode)) == 0))); 12346 12347 if (zero_extended 12348 || ((num_sign_bit_copies (op0, tmode) 12349 > (unsigned int) (GET_MODE_PRECISION (tmode) 12350 - GET_MODE_PRECISION (mode))) 12351 && (num_sign_bit_copies (op1, tmode) 12352 > (unsigned int) (GET_MODE_PRECISION (tmode) 12353 - GET_MODE_PRECISION (mode))))) 12354 { 12355 /* If OP0 is an AND and we don't have an AND in MODE either, 12356 make a new AND in the proper mode. */ 12357 if (GET_CODE (op0) == AND 12358 && !have_insn_for (AND, mode)) 12359 op0 = simplify_gen_binary (AND, tmode, 12360 gen_lowpart (tmode, 12361 XEXP (op0, 0)), 12362 gen_lowpart (tmode, 12363 XEXP (op0, 1))); 12364 else 12365 { 12366 if (zero_extended) 12367 { 12368 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode); 12369 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode); 12370 } 12371 else 12372 { 12373 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode); 12374 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode); 12375 } 12376 break; 12377 } 12378 } 12379 } 12380 12381 /* We may have changed the comparison operands. Re-canonicalize. */ 12382 if (swap_commutative_operands_p (op0, op1)) 12383 { 12384 tem = op0, op0 = op1, op1 = tem; 12385 code = swap_condition (code); 12386 } 12387 12388 /* If this machine only supports a subset of valid comparisons, see if we 12389 can convert an unsupported one into a supported one. */ 12390 target_canonicalize_comparison (&code, &op0, &op1, 0); 12391 12392 *pop0 = op0; 12393 *pop1 = op1; 12394 12395 return code; 12396 } 12397 12398 /* Utility function for record_value_for_reg. Count number of 12399 rtxs in X. */ 12400 static int 12401 count_rtxs (rtx x) 12402 { 12403 enum rtx_code code = GET_CODE (x); 12404 const char *fmt; 12405 int i, j, ret = 1; 12406 12407 if (GET_RTX_CLASS (code) == RTX_BIN_ARITH 12408 || GET_RTX_CLASS (code) == RTX_COMM_ARITH) 12409 { 12410 rtx x0 = XEXP (x, 0); 12411 rtx x1 = XEXP (x, 1); 12412 12413 if (x0 == x1) 12414 return 1 + 2 * count_rtxs (x0); 12415 12416 if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH 12417 || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH) 12418 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 12419 return 2 + 2 * count_rtxs (x0) 12420 + count_rtxs (x == XEXP (x1, 0) 12421 ? XEXP (x1, 1) : XEXP (x1, 0)); 12422 12423 if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH 12424 || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH) 12425 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 12426 return 2 + 2 * count_rtxs (x1) 12427 + count_rtxs (x == XEXP (x0, 0) 12428 ? XEXP (x0, 1) : XEXP (x0, 0)); 12429 } 12430 12431 fmt = GET_RTX_FORMAT (code); 12432 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 12433 if (fmt[i] == 'e') 12434 ret += count_rtxs (XEXP (x, i)); 12435 else if (fmt[i] == 'E') 12436 for (j = 0; j < XVECLEN (x, i); j++) 12437 ret += count_rtxs (XVECEXP (x, i, j)); 12438 12439 return ret; 12440 } 12441 12442 /* Utility function for following routine. Called when X is part of a value 12443 being stored into last_set_value. Sets last_set_table_tick 12444 for each register mentioned. Similar to mention_regs in cse.c */ 12445 12446 static void 12447 update_table_tick (rtx x) 12448 { 12449 enum rtx_code code = GET_CODE (x); 12450 const char *fmt = GET_RTX_FORMAT (code); 12451 int i, j; 12452 12453 if (code == REG) 12454 { 12455 unsigned int regno = REGNO (x); 12456 unsigned int endregno = END_REGNO (x); 12457 unsigned int r; 12458 12459 for (r = regno; r < endregno; r++) 12460 { 12461 reg_stat_type *rsp = ®_stat[r]; 12462 rsp->last_set_table_tick = label_tick; 12463 } 12464 12465 return; 12466 } 12467 12468 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 12469 if (fmt[i] == 'e') 12470 { 12471 /* Check for identical subexpressions. If x contains 12472 identical subexpression we only have to traverse one of 12473 them. */ 12474 if (i == 0 && ARITHMETIC_P (x)) 12475 { 12476 /* Note that at this point x1 has already been 12477 processed. */ 12478 rtx x0 = XEXP (x, 0); 12479 rtx x1 = XEXP (x, 1); 12480 12481 /* If x0 and x1 are identical then there is no need to 12482 process x0. */ 12483 if (x0 == x1) 12484 break; 12485 12486 /* If x0 is identical to a subexpression of x1 then while 12487 processing x1, x0 has already been processed. Thus we 12488 are done with x. */ 12489 if (ARITHMETIC_P (x1) 12490 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 12491 break; 12492 12493 /* If x1 is identical to a subexpression of x0 then we 12494 still have to process the rest of x0. */ 12495 if (ARITHMETIC_P (x0) 12496 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 12497 { 12498 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0)); 12499 break; 12500 } 12501 } 12502 12503 update_table_tick (XEXP (x, i)); 12504 } 12505 else if (fmt[i] == 'E') 12506 for (j = 0; j < XVECLEN (x, i); j++) 12507 update_table_tick (XVECEXP (x, i, j)); 12508 } 12509 12510 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we 12511 are saying that the register is clobbered and we no longer know its 12512 value. If INSN is zero, don't update reg_stat[].last_set; this is 12513 only permitted with VALUE also zero and is used to invalidate the 12514 register. */ 12515 12516 static void 12517 record_value_for_reg (rtx reg, rtx_insn *insn, rtx value) 12518 { 12519 unsigned int regno = REGNO (reg); 12520 unsigned int endregno = END_REGNO (reg); 12521 unsigned int i; 12522 reg_stat_type *rsp; 12523 12524 /* If VALUE contains REG and we have a previous value for REG, substitute 12525 the previous value. */ 12526 if (value && insn && reg_overlap_mentioned_p (reg, value)) 12527 { 12528 rtx tem; 12529 12530 /* Set things up so get_last_value is allowed to see anything set up to 12531 our insn. */ 12532 subst_low_luid = DF_INSN_LUID (insn); 12533 tem = get_last_value (reg); 12534 12535 /* If TEM is simply a binary operation with two CLOBBERs as operands, 12536 it isn't going to be useful and will take a lot of time to process, 12537 so just use the CLOBBER. */ 12538 12539 if (tem) 12540 { 12541 if (ARITHMETIC_P (tem) 12542 && GET_CODE (XEXP (tem, 0)) == CLOBBER 12543 && GET_CODE (XEXP (tem, 1)) == CLOBBER) 12544 tem = XEXP (tem, 0); 12545 else if (count_occurrences (value, reg, 1) >= 2) 12546 { 12547 /* If there are two or more occurrences of REG in VALUE, 12548 prevent the value from growing too much. */ 12549 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL) 12550 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx); 12551 } 12552 12553 value = replace_rtx (copy_rtx (value), reg, tem); 12554 } 12555 } 12556 12557 /* For each register modified, show we don't know its value, that 12558 we don't know about its bitwise content, that its value has been 12559 updated, and that we don't know the location of the death of the 12560 register. */ 12561 for (i = regno; i < endregno; i++) 12562 { 12563 rsp = ®_stat[i]; 12564 12565 if (insn) 12566 rsp->last_set = insn; 12567 12568 rsp->last_set_value = 0; 12569 rsp->last_set_mode = VOIDmode; 12570 rsp->last_set_nonzero_bits = 0; 12571 rsp->last_set_sign_bit_copies = 0; 12572 rsp->last_death = 0; 12573 rsp->truncated_to_mode = VOIDmode; 12574 } 12575 12576 /* Mark registers that are being referenced in this value. */ 12577 if (value) 12578 update_table_tick (value); 12579 12580 /* Now update the status of each register being set. 12581 If someone is using this register in this block, set this register 12582 to invalid since we will get confused between the two lives in this 12583 basic block. This makes using this register always invalid. In cse, we 12584 scan the table to invalidate all entries using this register, but this 12585 is too much work for us. */ 12586 12587 for (i = regno; i < endregno; i++) 12588 { 12589 rsp = ®_stat[i]; 12590 rsp->last_set_label = label_tick; 12591 if (!insn 12592 || (value && rsp->last_set_table_tick >= label_tick_ebb_start)) 12593 rsp->last_set_invalid = 1; 12594 else 12595 rsp->last_set_invalid = 0; 12596 } 12597 12598 /* The value being assigned might refer to X (like in "x++;"). In that 12599 case, we must replace it with (clobber (const_int 0)) to prevent 12600 infinite loops. */ 12601 rsp = ®_stat[regno]; 12602 if (value && !get_last_value_validate (&value, insn, label_tick, 0)) 12603 { 12604 value = copy_rtx (value); 12605 if (!get_last_value_validate (&value, insn, label_tick, 1)) 12606 value = 0; 12607 } 12608 12609 /* For the main register being modified, update the value, the mode, the 12610 nonzero bits, and the number of sign bit copies. */ 12611 12612 rsp->last_set_value = value; 12613 12614 if (value) 12615 { 12616 machine_mode mode = GET_MODE (reg); 12617 subst_low_luid = DF_INSN_LUID (insn); 12618 rsp->last_set_mode = mode; 12619 if (GET_MODE_CLASS (mode) == MODE_INT 12620 && HWI_COMPUTABLE_MODE_P (mode)) 12621 mode = nonzero_bits_mode; 12622 rsp->last_set_nonzero_bits = nonzero_bits (value, mode); 12623 rsp->last_set_sign_bit_copies 12624 = num_sign_bit_copies (value, GET_MODE (reg)); 12625 } 12626 } 12627 12628 /* Called via note_stores from record_dead_and_set_regs to handle one 12629 SET or CLOBBER in an insn. DATA is the instruction in which the 12630 set is occurring. */ 12631 12632 static void 12633 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data) 12634 { 12635 rtx_insn *record_dead_insn = (rtx_insn *) data; 12636 12637 if (GET_CODE (dest) == SUBREG) 12638 dest = SUBREG_REG (dest); 12639 12640 if (!record_dead_insn) 12641 { 12642 if (REG_P (dest)) 12643 record_value_for_reg (dest, NULL, NULL_RTX); 12644 return; 12645 } 12646 12647 if (REG_P (dest)) 12648 { 12649 /* If we are setting the whole register, we know its value. Otherwise 12650 show that we don't know the value. We can handle SUBREG in 12651 some cases. */ 12652 if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) 12653 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); 12654 else if (GET_CODE (setter) == SET 12655 && GET_CODE (SET_DEST (setter)) == SUBREG 12656 && SUBREG_REG (SET_DEST (setter)) == dest 12657 && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD 12658 && subreg_lowpart_p (SET_DEST (setter))) 12659 record_value_for_reg (dest, record_dead_insn, 12660 gen_lowpart (GET_MODE (dest), 12661 SET_SRC (setter))); 12662 else 12663 record_value_for_reg (dest, record_dead_insn, NULL_RTX); 12664 } 12665 else if (MEM_P (dest) 12666 /* Ignore pushes, they clobber nothing. */ 12667 && ! push_operand (dest, GET_MODE (dest))) 12668 mem_last_set = DF_INSN_LUID (record_dead_insn); 12669 } 12670 12671 /* Update the records of when each REG was most recently set or killed 12672 for the things done by INSN. This is the last thing done in processing 12673 INSN in the combiner loop. 12674 12675 We update reg_stat[], in particular fields last_set, last_set_value, 12676 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies, 12677 last_death, and also the similar information mem_last_set (which insn 12678 most recently modified memory) and last_call_luid (which insn was the 12679 most recent subroutine call). */ 12680 12681 static void 12682 record_dead_and_set_regs (rtx_insn *insn) 12683 { 12684 rtx link; 12685 unsigned int i; 12686 12687 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 12688 { 12689 if (REG_NOTE_KIND (link) == REG_DEAD 12690 && REG_P (XEXP (link, 0))) 12691 { 12692 unsigned int regno = REGNO (XEXP (link, 0)); 12693 unsigned int endregno = END_REGNO (XEXP (link, 0)); 12694 12695 for (i = regno; i < endregno; i++) 12696 { 12697 reg_stat_type *rsp; 12698 12699 rsp = ®_stat[i]; 12700 rsp->last_death = insn; 12701 } 12702 } 12703 else if (REG_NOTE_KIND (link) == REG_INC) 12704 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); 12705 } 12706 12707 if (CALL_P (insn)) 12708 { 12709 hard_reg_set_iterator hrsi; 12710 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi) 12711 { 12712 reg_stat_type *rsp; 12713 12714 rsp = ®_stat[i]; 12715 rsp->last_set_invalid = 1; 12716 rsp->last_set = insn; 12717 rsp->last_set_value = 0; 12718 rsp->last_set_mode = VOIDmode; 12719 rsp->last_set_nonzero_bits = 0; 12720 rsp->last_set_sign_bit_copies = 0; 12721 rsp->last_death = 0; 12722 rsp->truncated_to_mode = VOIDmode; 12723 } 12724 12725 last_call_luid = mem_last_set = DF_INSN_LUID (insn); 12726 12727 /* We can't combine into a call pattern. Remember, though, that 12728 the return value register is set at this LUID. We could 12729 still replace a register with the return value from the 12730 wrong subroutine call! */ 12731 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX); 12732 } 12733 else 12734 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); 12735 } 12736 12737 /* If a SUBREG has the promoted bit set, it is in fact a property of the 12738 register present in the SUBREG, so for each such SUBREG go back and 12739 adjust nonzero and sign bit information of the registers that are 12740 known to have some zero/sign bits set. 12741 12742 This is needed because when combine blows the SUBREGs away, the 12743 information on zero/sign bits is lost and further combines can be 12744 missed because of that. */ 12745 12746 static void 12747 record_promoted_value (rtx_insn *insn, rtx subreg) 12748 { 12749 struct insn_link *links; 12750 rtx set; 12751 unsigned int regno = REGNO (SUBREG_REG (subreg)); 12752 machine_mode mode = GET_MODE (subreg); 12753 12754 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT) 12755 return; 12756 12757 for (links = LOG_LINKS (insn); links;) 12758 { 12759 reg_stat_type *rsp; 12760 12761 insn = links->insn; 12762 set = single_set (insn); 12763 12764 if (! set || !REG_P (SET_DEST (set)) 12765 || REGNO (SET_DEST (set)) != regno 12766 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) 12767 { 12768 links = links->next; 12769 continue; 12770 } 12771 12772 rsp = ®_stat[regno]; 12773 if (rsp->last_set == insn) 12774 { 12775 if (SUBREG_PROMOTED_UNSIGNED_P (subreg)) 12776 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode); 12777 } 12778 12779 if (REG_P (SET_SRC (set))) 12780 { 12781 regno = REGNO (SET_SRC (set)); 12782 links = LOG_LINKS (insn); 12783 } 12784 else 12785 break; 12786 } 12787 } 12788 12789 /* Check if X, a register, is known to contain a value already 12790 truncated to MODE. In this case we can use a subreg to refer to 12791 the truncated value even though in the generic case we would need 12792 an explicit truncation. */ 12793 12794 static bool 12795 reg_truncated_to_mode (machine_mode mode, const_rtx x) 12796 { 12797 reg_stat_type *rsp = ®_stat[REGNO (x)]; 12798 machine_mode truncated = rsp->truncated_to_mode; 12799 12800 if (truncated == 0 12801 || rsp->truncation_label < label_tick_ebb_start) 12802 return false; 12803 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode)) 12804 return true; 12805 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated)) 12806 return true; 12807 return false; 12808 } 12809 12810 /* If X is a hard reg or a subreg record the mode that the register is 12811 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able 12812 to turn a truncate into a subreg using this information. Return true 12813 if traversing X is complete. */ 12814 12815 static bool 12816 record_truncated_value (rtx x) 12817 { 12818 machine_mode truncated_mode; 12819 reg_stat_type *rsp; 12820 12821 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))) 12822 { 12823 machine_mode original_mode = GET_MODE (SUBREG_REG (x)); 12824 truncated_mode = GET_MODE (x); 12825 12826 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode)) 12827 return true; 12828 12829 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode)) 12830 return true; 12831 12832 x = SUBREG_REG (x); 12833 } 12834 /* ??? For hard-regs we now record everything. We might be able to 12835 optimize this using last_set_mode. */ 12836 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) 12837 truncated_mode = GET_MODE (x); 12838 else 12839 return false; 12840 12841 rsp = ®_stat[REGNO (x)]; 12842 if (rsp->truncated_to_mode == 0 12843 || rsp->truncation_label < label_tick_ebb_start 12844 || (GET_MODE_SIZE (truncated_mode) 12845 < GET_MODE_SIZE (rsp->truncated_to_mode))) 12846 { 12847 rsp->truncated_to_mode = truncated_mode; 12848 rsp->truncation_label = label_tick; 12849 } 12850 12851 return true; 12852 } 12853 12854 /* Callback for note_uses. Find hardregs and subregs of pseudos and 12855 the modes they are used in. This can help truning TRUNCATEs into 12856 SUBREGs. */ 12857 12858 static void 12859 record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED) 12860 { 12861 subrtx_var_iterator::array_type array; 12862 FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST) 12863 if (record_truncated_value (*iter)) 12864 iter.skip_subrtxes (); 12865 } 12866 12867 /* Scan X for promoted SUBREGs. For each one found, 12868 note what it implies to the registers used in it. */ 12869 12870 static void 12871 check_promoted_subreg (rtx_insn *insn, rtx x) 12872 { 12873 if (GET_CODE (x) == SUBREG 12874 && SUBREG_PROMOTED_VAR_P (x) 12875 && REG_P (SUBREG_REG (x))) 12876 record_promoted_value (insn, x); 12877 else 12878 { 12879 const char *format = GET_RTX_FORMAT (GET_CODE (x)); 12880 int i, j; 12881 12882 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) 12883 switch (format[i]) 12884 { 12885 case 'e': 12886 check_promoted_subreg (insn, XEXP (x, i)); 12887 break; 12888 case 'V': 12889 case 'E': 12890 if (XVEC (x, i) != 0) 12891 for (j = 0; j < XVECLEN (x, i); j++) 12892 check_promoted_subreg (insn, XVECEXP (x, i, j)); 12893 break; 12894 } 12895 } 12896 } 12897 12898 /* Verify that all the registers and memory references mentioned in *LOC are 12899 still valid. *LOC was part of a value set in INSN when label_tick was 12900 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace 12901 the invalid references with (clobber (const_int 0)) and return 1. This 12902 replacement is useful because we often can get useful information about 12903 the form of a value (e.g., if it was produced by a shift that always 12904 produces -1 or 0) even though we don't know exactly what registers it 12905 was produced from. */ 12906 12907 static int 12908 get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, int replace) 12909 { 12910 rtx x = *loc; 12911 const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); 12912 int len = GET_RTX_LENGTH (GET_CODE (x)); 12913 int i, j; 12914 12915 if (REG_P (x)) 12916 { 12917 unsigned int regno = REGNO (x); 12918 unsigned int endregno = END_REGNO (x); 12919 unsigned int j; 12920 12921 for (j = regno; j < endregno; j++) 12922 { 12923 reg_stat_type *rsp = ®_stat[j]; 12924 if (rsp->last_set_invalid 12925 /* If this is a pseudo-register that was only set once and not 12926 live at the beginning of the function, it is always valid. */ 12927 || (! (regno >= FIRST_PSEUDO_REGISTER 12928 && regno < reg_n_sets_max 12929 && REG_N_SETS (regno) == 1 12930 && (!REGNO_REG_SET_P 12931 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), 12932 regno))) 12933 && rsp->last_set_label > tick)) 12934 { 12935 if (replace) 12936 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 12937 return replace; 12938 } 12939 } 12940 12941 return 1; 12942 } 12943 /* If this is a memory reference, make sure that there were no stores after 12944 it that might have clobbered the value. We don't have alias info, so we 12945 assume any store invalidates it. Moreover, we only have local UIDs, so 12946 we also assume that there were stores in the intervening basic blocks. */ 12947 else if (MEM_P (x) && !MEM_READONLY_P (x) 12948 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set)) 12949 { 12950 if (replace) 12951 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 12952 return replace; 12953 } 12954 12955 for (i = 0; i < len; i++) 12956 { 12957 if (fmt[i] == 'e') 12958 { 12959 /* Check for identical subexpressions. If x contains 12960 identical subexpression we only have to traverse one of 12961 them. */ 12962 if (i == 1 && ARITHMETIC_P (x)) 12963 { 12964 /* Note that at this point x0 has already been checked 12965 and found valid. */ 12966 rtx x0 = XEXP (x, 0); 12967 rtx x1 = XEXP (x, 1); 12968 12969 /* If x0 and x1 are identical then x is also valid. */ 12970 if (x0 == x1) 12971 return 1; 12972 12973 /* If x1 is identical to a subexpression of x0 then 12974 while checking x0, x1 has already been checked. Thus 12975 it is valid and so as x. */ 12976 if (ARITHMETIC_P (x0) 12977 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 12978 return 1; 12979 12980 /* If x0 is identical to a subexpression of x1 then x is 12981 valid iff the rest of x1 is valid. */ 12982 if (ARITHMETIC_P (x1) 12983 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 12984 return 12985 get_last_value_validate (&XEXP (x1, 12986 x0 == XEXP (x1, 0) ? 1 : 0), 12987 insn, tick, replace); 12988 } 12989 12990 if (get_last_value_validate (&XEXP (x, i), insn, tick, 12991 replace) == 0) 12992 return 0; 12993 } 12994 else if (fmt[i] == 'E') 12995 for (j = 0; j < XVECLEN (x, i); j++) 12996 if (get_last_value_validate (&XVECEXP (x, i, j), 12997 insn, tick, replace) == 0) 12998 return 0; 12999 } 13000 13001 /* If we haven't found a reason for it to be invalid, it is valid. */ 13002 return 1; 13003 } 13004 13005 /* Get the last value assigned to X, if known. Some registers 13006 in the value may be replaced with (clobber (const_int 0)) if their value 13007 is known longer known reliably. */ 13008 13009 static rtx 13010 get_last_value (const_rtx x) 13011 { 13012 unsigned int regno; 13013 rtx value; 13014 reg_stat_type *rsp; 13015 13016 /* If this is a non-paradoxical SUBREG, get the value of its operand and 13017 then convert it to the desired mode. If this is a paradoxical SUBREG, 13018 we cannot predict what values the "extra" bits might have. */ 13019 if (GET_CODE (x) == SUBREG 13020 && subreg_lowpart_p (x) 13021 && !paradoxical_subreg_p (x) 13022 && (value = get_last_value (SUBREG_REG (x))) != 0) 13023 return gen_lowpart (GET_MODE (x), value); 13024 13025 if (!REG_P (x)) 13026 return 0; 13027 13028 regno = REGNO (x); 13029 rsp = ®_stat[regno]; 13030 value = rsp->last_set_value; 13031 13032 /* If we don't have a value, or if it isn't for this basic block and 13033 it's either a hard register, set more than once, or it's a live 13034 at the beginning of the function, return 0. 13035 13036 Because if it's not live at the beginning of the function then the reg 13037 is always set before being used (is never used without being set). 13038 And, if it's set only once, and it's always set before use, then all 13039 uses must have the same last value, even if it's not from this basic 13040 block. */ 13041 13042 if (value == 0 13043 || (rsp->last_set_label < label_tick_ebb_start 13044 && (regno < FIRST_PSEUDO_REGISTER 13045 || regno >= reg_n_sets_max 13046 || REG_N_SETS (regno) != 1 13047 || REGNO_REG_SET_P 13048 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno)))) 13049 return 0; 13050 13051 /* If the value was set in a later insn than the ones we are processing, 13052 we can't use it even if the register was only set once. */ 13053 if (rsp->last_set_label == label_tick 13054 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid) 13055 return 0; 13056 13057 /* If fewer bits were set than what we are asked for now, we cannot use 13058 the value. */ 13059 if (GET_MODE_PRECISION (rsp->last_set_mode) 13060 < GET_MODE_PRECISION (GET_MODE (x))) 13061 return 0; 13062 13063 /* If the value has all its registers valid, return it. */ 13064 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0)) 13065 return value; 13066 13067 /* Otherwise, make a copy and replace any invalid register with 13068 (clobber (const_int 0)). If that fails for some reason, return 0. */ 13069 13070 value = copy_rtx (value); 13071 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1)) 13072 return value; 13073 13074 return 0; 13075 } 13076 13077 /* Return nonzero if expression X refers to a REG or to memory 13078 that is set in an instruction more recent than FROM_LUID. */ 13079 13080 static int 13081 use_crosses_set_p (const_rtx x, int from_luid) 13082 { 13083 const char *fmt; 13084 int i; 13085 enum rtx_code code = GET_CODE (x); 13086 13087 if (code == REG) 13088 { 13089 unsigned int regno = REGNO (x); 13090 unsigned endreg = END_REGNO (x); 13091 13092 #ifdef PUSH_ROUNDING 13093 /* Don't allow uses of the stack pointer to be moved, 13094 because we don't know whether the move crosses a push insn. */ 13095 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) 13096 return 1; 13097 #endif 13098 for (; regno < endreg; regno++) 13099 { 13100 reg_stat_type *rsp = ®_stat[regno]; 13101 if (rsp->last_set 13102 && rsp->last_set_label == label_tick 13103 && DF_INSN_LUID (rsp->last_set) > from_luid) 13104 return 1; 13105 } 13106 return 0; 13107 } 13108 13109 if (code == MEM && mem_last_set > from_luid) 13110 return 1; 13111 13112 fmt = GET_RTX_FORMAT (code); 13113 13114 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 13115 { 13116 if (fmt[i] == 'E') 13117 { 13118 int j; 13119 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 13120 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid)) 13121 return 1; 13122 } 13123 else if (fmt[i] == 'e' 13124 && use_crosses_set_p (XEXP (x, i), from_luid)) 13125 return 1; 13126 } 13127 return 0; 13128 } 13129 13130 /* Define three variables used for communication between the following 13131 routines. */ 13132 13133 static unsigned int reg_dead_regno, reg_dead_endregno; 13134 static int reg_dead_flag; 13135 13136 /* Function called via note_stores from reg_dead_at_p. 13137 13138 If DEST is within [reg_dead_regno, reg_dead_endregno), set 13139 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ 13140 13141 static void 13142 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) 13143 { 13144 unsigned int regno, endregno; 13145 13146 if (!REG_P (dest)) 13147 return; 13148 13149 regno = REGNO (dest); 13150 endregno = END_REGNO (dest); 13151 if (reg_dead_endregno > regno && reg_dead_regno < endregno) 13152 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; 13153 } 13154 13155 /* Return nonzero if REG is known to be dead at INSN. 13156 13157 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER 13158 referencing REG, it is dead. If we hit a SET referencing REG, it is 13159 live. Otherwise, see if it is live or dead at the start of the basic 13160 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS 13161 must be assumed to be always live. */ 13162 13163 static int 13164 reg_dead_at_p (rtx reg, rtx_insn *insn) 13165 { 13166 basic_block block; 13167 unsigned int i; 13168 13169 /* Set variables for reg_dead_at_p_1. */ 13170 reg_dead_regno = REGNO (reg); 13171 reg_dead_endregno = END_REGNO (reg); 13172 13173 reg_dead_flag = 0; 13174 13175 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers 13176 we allow the machine description to decide whether use-and-clobber 13177 patterns are OK. */ 13178 if (reg_dead_regno < FIRST_PSEUDO_REGISTER) 13179 { 13180 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 13181 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i)) 13182 return 0; 13183 } 13184 13185 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or 13186 beginning of basic block. */ 13187 block = BLOCK_FOR_INSN (insn); 13188 for (;;) 13189 { 13190 if (INSN_P (insn)) 13191 { 13192 if (find_regno_note (insn, REG_UNUSED, reg_dead_regno)) 13193 return 1; 13194 13195 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); 13196 if (reg_dead_flag) 13197 return reg_dead_flag == 1 ? 1 : 0; 13198 13199 if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) 13200 return 1; 13201 } 13202 13203 if (insn == BB_HEAD (block)) 13204 break; 13205 13206 insn = PREV_INSN (insn); 13207 } 13208 13209 /* Look at live-in sets for the basic block that we were in. */ 13210 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 13211 if (REGNO_REG_SET_P (df_get_live_in (block), i)) 13212 return 0; 13213 13214 return 1; 13215 } 13216 13217 /* Note hard registers in X that are used. */ 13218 13219 static void 13220 mark_used_regs_combine (rtx x) 13221 { 13222 RTX_CODE code = GET_CODE (x); 13223 unsigned int regno; 13224 int i; 13225 13226 switch (code) 13227 { 13228 case LABEL_REF: 13229 case SYMBOL_REF: 13230 case CONST: 13231 CASE_CONST_ANY: 13232 case PC: 13233 case ADDR_VEC: 13234 case ADDR_DIFF_VEC: 13235 case ASM_INPUT: 13236 #ifdef HAVE_cc0 13237 /* CC0 must die in the insn after it is set, so we don't need to take 13238 special note of it here. */ 13239 case CC0: 13240 #endif 13241 return; 13242 13243 case CLOBBER: 13244 /* If we are clobbering a MEM, mark any hard registers inside the 13245 address as used. */ 13246 if (MEM_P (XEXP (x, 0))) 13247 mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); 13248 return; 13249 13250 case REG: 13251 regno = REGNO (x); 13252 /* A hard reg in a wide mode may really be multiple registers. 13253 If so, mark all of them just like the first. */ 13254 if (regno < FIRST_PSEUDO_REGISTER) 13255 { 13256 /* None of this applies to the stack, frame or arg pointers. */ 13257 if (regno == STACK_POINTER_REGNUM 13258 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER 13259 || regno == HARD_FRAME_POINTER_REGNUM 13260 #endif 13261 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 13262 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) 13263 #endif 13264 || regno == FRAME_POINTER_REGNUM) 13265 return; 13266 13267 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno); 13268 } 13269 return; 13270 13271 case SET: 13272 { 13273 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in 13274 the address. */ 13275 rtx testreg = SET_DEST (x); 13276 13277 while (GET_CODE (testreg) == SUBREG 13278 || GET_CODE (testreg) == ZERO_EXTRACT 13279 || GET_CODE (testreg) == STRICT_LOW_PART) 13280 testreg = XEXP (testreg, 0); 13281 13282 if (MEM_P (testreg)) 13283 mark_used_regs_combine (XEXP (testreg, 0)); 13284 13285 mark_used_regs_combine (SET_SRC (x)); 13286 } 13287 return; 13288 13289 default: 13290 break; 13291 } 13292 13293 /* Recursively scan the operands of this expression. */ 13294 13295 { 13296 const char *fmt = GET_RTX_FORMAT (code); 13297 13298 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 13299 { 13300 if (fmt[i] == 'e') 13301 mark_used_regs_combine (XEXP (x, i)); 13302 else if (fmt[i] == 'E') 13303 { 13304 int j; 13305 13306 for (j = 0; j < XVECLEN (x, i); j++) 13307 mark_used_regs_combine (XVECEXP (x, i, j)); 13308 } 13309 } 13310 } 13311 } 13312 13313 /* Remove register number REGNO from the dead registers list of INSN. 13314 13315 Return the note used to record the death, if there was one. */ 13316 13317 rtx 13318 remove_death (unsigned int regno, rtx_insn *insn) 13319 { 13320 rtx note = find_regno_note (insn, REG_DEAD, regno); 13321 13322 if (note) 13323 remove_note (insn, note); 13324 13325 return note; 13326 } 13327 13328 /* For each register (hardware or pseudo) used within expression X, if its 13329 death is in an instruction with luid between FROM_LUID (inclusive) and 13330 TO_INSN (exclusive), put a REG_DEAD note for that register in the 13331 list headed by PNOTES. 13332 13333 That said, don't move registers killed by maybe_kill_insn. 13334 13335 This is done when X is being merged by combination into TO_INSN. These 13336 notes will then be distributed as needed. */ 13337 13338 static void 13339 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn, 13340 rtx *pnotes) 13341 { 13342 const char *fmt; 13343 int len, i; 13344 enum rtx_code code = GET_CODE (x); 13345 13346 if (code == REG) 13347 { 13348 unsigned int regno = REGNO (x); 13349 rtx_insn *where_dead = reg_stat[regno].last_death; 13350 13351 /* Don't move the register if it gets killed in between from and to. */ 13352 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) 13353 && ! reg_referenced_p (x, maybe_kill_insn)) 13354 return; 13355 13356 if (where_dead 13357 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn) 13358 && DF_INSN_LUID (where_dead) >= from_luid 13359 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn)) 13360 { 13361 rtx note = remove_death (regno, where_dead); 13362 13363 /* It is possible for the call above to return 0. This can occur 13364 when last_death points to I2 or I1 that we combined with. 13365 In that case make a new note. 13366 13367 We must also check for the case where X is a hard register 13368 and NOTE is a death note for a range of hard registers 13369 including X. In that case, we must put REG_DEAD notes for 13370 the remaining registers in place of NOTE. */ 13371 13372 if (note != 0 && regno < FIRST_PSEUDO_REGISTER 13373 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 13374 > GET_MODE_SIZE (GET_MODE (x)))) 13375 { 13376 unsigned int deadregno = REGNO (XEXP (note, 0)); 13377 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0)); 13378 unsigned int ourend = END_HARD_REGNO (x); 13379 unsigned int i; 13380 13381 for (i = deadregno; i < deadend; i++) 13382 if (i < regno || i >= ourend) 13383 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]); 13384 } 13385 13386 /* If we didn't find any note, or if we found a REG_DEAD note that 13387 covers only part of the given reg, and we have a multi-reg hard 13388 register, then to be safe we must check for REG_DEAD notes 13389 for each register other than the first. They could have 13390 their own REG_DEAD notes lying around. */ 13391 else if ((note == 0 13392 || (note != 0 13393 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 13394 < GET_MODE_SIZE (GET_MODE (x))))) 13395 && regno < FIRST_PSEUDO_REGISTER 13396 && hard_regno_nregs[regno][GET_MODE (x)] > 1) 13397 { 13398 unsigned int ourend = END_HARD_REGNO (x); 13399 unsigned int i, offset; 13400 rtx oldnotes = 0; 13401 13402 if (note) 13403 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))]; 13404 else 13405 offset = 1; 13406 13407 for (i = regno + offset; i < ourend; i++) 13408 move_deaths (regno_reg_rtx[i], 13409 maybe_kill_insn, from_luid, to_insn, &oldnotes); 13410 } 13411 13412 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) 13413 { 13414 XEXP (note, 1) = *pnotes; 13415 *pnotes = note; 13416 } 13417 else 13418 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes); 13419 } 13420 13421 return; 13422 } 13423 13424 else if (GET_CODE (x) == SET) 13425 { 13426 rtx dest = SET_DEST (x); 13427 13428 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes); 13429 13430 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG 13431 that accesses one word of a multi-word item, some 13432 piece of everything register in the expression is used by 13433 this insn, so remove any old death. */ 13434 /* ??? So why do we test for equality of the sizes? */ 13435 13436 if (GET_CODE (dest) == ZERO_EXTRACT 13437 || GET_CODE (dest) == STRICT_LOW_PART 13438 || (GET_CODE (dest) == SUBREG 13439 && (((GET_MODE_SIZE (GET_MODE (dest)) 13440 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 13441 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) 13442 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) 13443 { 13444 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes); 13445 return; 13446 } 13447 13448 /* If this is some other SUBREG, we know it replaces the entire 13449 value, so use that as the destination. */ 13450 if (GET_CODE (dest) == SUBREG) 13451 dest = SUBREG_REG (dest); 13452 13453 /* If this is a MEM, adjust deaths of anything used in the address. 13454 For a REG (the only other possibility), the entire value is 13455 being replaced so the old value is not used in this insn. */ 13456 13457 if (MEM_P (dest)) 13458 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid, 13459 to_insn, pnotes); 13460 return; 13461 } 13462 13463 else if (GET_CODE (x) == CLOBBER) 13464 return; 13465 13466 len = GET_RTX_LENGTH (code); 13467 fmt = GET_RTX_FORMAT (code); 13468 13469 for (i = 0; i < len; i++) 13470 { 13471 if (fmt[i] == 'E') 13472 { 13473 int j; 13474 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 13475 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid, 13476 to_insn, pnotes); 13477 } 13478 else if (fmt[i] == 'e') 13479 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes); 13480 } 13481 } 13482 13483 /* Return 1 if X is the target of a bit-field assignment in BODY, the 13484 pattern of an insn. X must be a REG. */ 13485 13486 static int 13487 reg_bitfield_target_p (rtx x, rtx body) 13488 { 13489 int i; 13490 13491 if (GET_CODE (body) == SET) 13492 { 13493 rtx dest = SET_DEST (body); 13494 rtx target; 13495 unsigned int regno, tregno, endregno, endtregno; 13496 13497 if (GET_CODE (dest) == ZERO_EXTRACT) 13498 target = XEXP (dest, 0); 13499 else if (GET_CODE (dest) == STRICT_LOW_PART) 13500 target = SUBREG_REG (XEXP (dest, 0)); 13501 else 13502 return 0; 13503 13504 if (GET_CODE (target) == SUBREG) 13505 target = SUBREG_REG (target); 13506 13507 if (!REG_P (target)) 13508 return 0; 13509 13510 tregno = REGNO (target), regno = REGNO (x); 13511 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) 13512 return target == x; 13513 13514 endtregno = end_hard_regno (GET_MODE (target), tregno); 13515 endregno = end_hard_regno (GET_MODE (x), regno); 13516 13517 return endregno > tregno && regno < endtregno; 13518 } 13519 13520 else if (GET_CODE (body) == PARALLEL) 13521 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 13522 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) 13523 return 1; 13524 13525 return 0; 13526 } 13527 13528 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them 13529 as appropriate. I3 and I2 are the insns resulting from the combination 13530 insns including FROM (I2 may be zero). 13531 13532 ELIM_I2 and ELIM_I1 are either zero or registers that we know will 13533 not need REG_DEAD notes because they are being substituted for. This 13534 saves searching in the most common cases. 13535 13536 Each note in the list is either ignored or placed on some insns, depending 13537 on the type of note. */ 13538 13539 static void 13540 distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2, 13541 rtx elim_i2, rtx elim_i1, rtx elim_i0) 13542 { 13543 rtx note, next_note; 13544 rtx tem_note; 13545 rtx_insn *tem_insn; 13546 13547 for (note = notes; note; note = next_note) 13548 { 13549 rtx_insn *place = 0, *place2 = 0; 13550 13551 next_note = XEXP (note, 1); 13552 switch (REG_NOTE_KIND (note)) 13553 { 13554 case REG_BR_PROB: 13555 case REG_BR_PRED: 13556 /* Doesn't matter much where we put this, as long as it's somewhere. 13557 It is preferable to keep these notes on branches, which is most 13558 likely to be i3. */ 13559 place = i3; 13560 break; 13561 13562 case REG_NON_LOCAL_GOTO: 13563 if (JUMP_P (i3)) 13564 place = i3; 13565 else 13566 { 13567 gcc_assert (i2 && JUMP_P (i2)); 13568 place = i2; 13569 } 13570 break; 13571 13572 case REG_EH_REGION: 13573 /* These notes must remain with the call or trapping instruction. */ 13574 if (CALL_P (i3)) 13575 place = i3; 13576 else if (i2 && CALL_P (i2)) 13577 place = i2; 13578 else 13579 { 13580 gcc_assert (cfun->can_throw_non_call_exceptions); 13581 if (may_trap_p (i3)) 13582 place = i3; 13583 else if (i2 && may_trap_p (i2)) 13584 place = i2; 13585 /* ??? Otherwise assume we've combined things such that we 13586 can now prove that the instructions can't trap. Drop the 13587 note in this case. */ 13588 } 13589 break; 13590 13591 case REG_ARGS_SIZE: 13592 /* ??? How to distribute between i3-i1. Assume i3 contains the 13593 entire adjustment. Assert i3 contains at least some adjust. */ 13594 if (!noop_move_p (i3)) 13595 { 13596 int old_size, args_size = INTVAL (XEXP (note, 0)); 13597 /* fixup_args_size_notes looks at REG_NORETURN note, 13598 so ensure the note is placed there first. */ 13599 if (CALL_P (i3)) 13600 { 13601 rtx *np; 13602 for (np = &next_note; *np; np = &XEXP (*np, 1)) 13603 if (REG_NOTE_KIND (*np) == REG_NORETURN) 13604 { 13605 rtx n = *np; 13606 *np = XEXP (n, 1); 13607 XEXP (n, 1) = REG_NOTES (i3); 13608 REG_NOTES (i3) = n; 13609 break; 13610 } 13611 } 13612 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size); 13613 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS 13614 REG_ARGS_SIZE note to all noreturn calls, allow that here. */ 13615 gcc_assert (old_size != args_size 13616 || (CALL_P (i3) 13617 && !ACCUMULATE_OUTGOING_ARGS 13618 && find_reg_note (i3, REG_NORETURN, NULL_RTX))); 13619 } 13620 break; 13621 13622 case REG_NORETURN: 13623 case REG_SETJMP: 13624 case REG_TM: 13625 case REG_CALL_DECL: 13626 /* These notes must remain with the call. It should not be 13627 possible for both I2 and I3 to be a call. */ 13628 if (CALL_P (i3)) 13629 place = i3; 13630 else 13631 { 13632 gcc_assert (i2 && CALL_P (i2)); 13633 place = i2; 13634 } 13635 break; 13636 13637 case REG_UNUSED: 13638 /* Any clobbers for i3 may still exist, and so we must process 13639 REG_UNUSED notes from that insn. 13640 13641 Any clobbers from i2 or i1 can only exist if they were added by 13642 recog_for_combine. In that case, recog_for_combine created the 13643 necessary REG_UNUSED notes. Trying to keep any original 13644 REG_UNUSED notes from these insns can cause incorrect output 13645 if it is for the same register as the original i3 dest. 13646 In that case, we will notice that the register is set in i3, 13647 and then add a REG_UNUSED note for the destination of i3, which 13648 is wrong. However, it is possible to have REG_UNUSED notes from 13649 i2 or i1 for register which were both used and clobbered, so 13650 we keep notes from i2 or i1 if they will turn into REG_DEAD 13651 notes. */ 13652 13653 /* If this register is set or clobbered in I3, put the note there 13654 unless there is one already. */ 13655 if (reg_set_p (XEXP (note, 0), PATTERN (i3))) 13656 { 13657 if (from_insn != i3) 13658 break; 13659 13660 if (! (REG_P (XEXP (note, 0)) 13661 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) 13662 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) 13663 place = i3; 13664 } 13665 /* Otherwise, if this register is used by I3, then this register 13666 now dies here, so we must put a REG_DEAD note here unless there 13667 is one already. */ 13668 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) 13669 && ! (REG_P (XEXP (note, 0)) 13670 ? find_regno_note (i3, REG_DEAD, 13671 REGNO (XEXP (note, 0))) 13672 : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) 13673 { 13674 PUT_REG_NOTE_KIND (note, REG_DEAD); 13675 place = i3; 13676 } 13677 break; 13678 13679 case REG_EQUAL: 13680 case REG_EQUIV: 13681 case REG_NOALIAS: 13682 /* These notes say something about results of an insn. We can 13683 only support them if they used to be on I3 in which case they 13684 remain on I3. Otherwise they are ignored. 13685 13686 If the note refers to an expression that is not a constant, we 13687 must also ignore the note since we cannot tell whether the 13688 equivalence is still true. It might be possible to do 13689 slightly better than this (we only have a problem if I2DEST 13690 or I1DEST is present in the expression), but it doesn't 13691 seem worth the trouble. */ 13692 13693 if (from_insn == i3 13694 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) 13695 place = i3; 13696 break; 13697 13698 case REG_INC: 13699 /* These notes say something about how a register is used. They must 13700 be present on any use of the register in I2 or I3. */ 13701 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) 13702 place = i3; 13703 13704 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) 13705 { 13706 if (place) 13707 place2 = i2; 13708 else 13709 place = i2; 13710 } 13711 break; 13712 13713 case REG_LABEL_TARGET: 13714 case REG_LABEL_OPERAND: 13715 /* This can show up in several ways -- either directly in the 13716 pattern, or hidden off in the constant pool with (or without?) 13717 a REG_EQUAL note. */ 13718 /* ??? Ignore the without-reg_equal-note problem for now. */ 13719 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) 13720 || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX)) 13721 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF 13722 && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0))) 13723 place = i3; 13724 13725 if (i2 13726 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) 13727 || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX)) 13728 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF 13729 && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0)))) 13730 { 13731 if (place) 13732 place2 = i2; 13733 else 13734 place = i2; 13735 } 13736 13737 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note 13738 as a JUMP_LABEL or decrement LABEL_NUSES if it's already 13739 there. */ 13740 if (place && JUMP_P (place) 13741 && REG_NOTE_KIND (note) == REG_LABEL_TARGET 13742 && (JUMP_LABEL (place) == NULL 13743 || JUMP_LABEL (place) == XEXP (note, 0))) 13744 { 13745 rtx label = JUMP_LABEL (place); 13746 13747 if (!label) 13748 JUMP_LABEL (place) = XEXP (note, 0); 13749 else if (LABEL_P (label)) 13750 LABEL_NUSES (label)--; 13751 } 13752 13753 if (place2 && JUMP_P (place2) 13754 && REG_NOTE_KIND (note) == REG_LABEL_TARGET 13755 && (JUMP_LABEL (place2) == NULL 13756 || JUMP_LABEL (place2) == XEXP (note, 0))) 13757 { 13758 rtx label = JUMP_LABEL (place2); 13759 13760 if (!label) 13761 JUMP_LABEL (place2) = XEXP (note, 0); 13762 else if (LABEL_P (label)) 13763 LABEL_NUSES (label)--; 13764 place2 = 0; 13765 } 13766 break; 13767 13768 case REG_NONNEG: 13769 /* This note says something about the value of a register prior 13770 to the execution of an insn. It is too much trouble to see 13771 if the note is still correct in all situations. It is better 13772 to simply delete it. */ 13773 break; 13774 13775 case REG_DEAD: 13776 /* If we replaced the right hand side of FROM_INSN with a 13777 REG_EQUAL note, the original use of the dying register 13778 will not have been combined into I3 and I2. In such cases, 13779 FROM_INSN is guaranteed to be the first of the combined 13780 instructions, so we simply need to search back before 13781 FROM_INSN for the previous use or set of this register, 13782 then alter the notes there appropriately. 13783 13784 If the register is used as an input in I3, it dies there. 13785 Similarly for I2, if it is nonzero and adjacent to I3. 13786 13787 If the register is not used as an input in either I3 or I2 13788 and it is not one of the registers we were supposed to eliminate, 13789 there are two possibilities. We might have a non-adjacent I2 13790 or we might have somehow eliminated an additional register 13791 from a computation. For example, we might have had A & B where 13792 we discover that B will always be zero. In this case we will 13793 eliminate the reference to A. 13794 13795 In both cases, we must search to see if we can find a previous 13796 use of A and put the death note there. */ 13797 13798 if (from_insn 13799 && from_insn == i2mod 13800 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs)) 13801 tem_insn = from_insn; 13802 else 13803 { 13804 if (from_insn 13805 && CALL_P (from_insn) 13806 && find_reg_fusage (from_insn, USE, XEXP (note, 0))) 13807 place = from_insn; 13808 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) 13809 place = i3; 13810 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3 13811 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 13812 place = i2; 13813 else if ((rtx_equal_p (XEXP (note, 0), elim_i2) 13814 && !(i2mod 13815 && reg_overlap_mentioned_p (XEXP (note, 0), 13816 i2mod_old_rhs))) 13817 || rtx_equal_p (XEXP (note, 0), elim_i1) 13818 || rtx_equal_p (XEXP (note, 0), elim_i0)) 13819 break; 13820 tem_insn = i3; 13821 /* If the new I2 sets the same register that is marked dead 13822 in the note, we do not know where to put the note. 13823 Give up. */ 13824 if (i2 != 0 && reg_set_p (XEXP (note, 0), PATTERN (i2))) 13825 break; 13826 } 13827 13828 if (place == 0) 13829 { 13830 basic_block bb = this_basic_block; 13831 13832 for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn)) 13833 { 13834 if (!NONDEBUG_INSN_P (tem_insn)) 13835 { 13836 if (tem_insn == BB_HEAD (bb)) 13837 break; 13838 continue; 13839 } 13840 13841 /* If the register is being set at TEM_INSN, see if that is all 13842 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this 13843 into a REG_UNUSED note instead. Don't delete sets to 13844 global register vars. */ 13845 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER 13846 || !global_regs[REGNO (XEXP (note, 0))]) 13847 && reg_set_p (XEXP (note, 0), PATTERN (tem_insn))) 13848 { 13849 rtx set = single_set (tem_insn); 13850 rtx inner_dest = 0; 13851 #ifdef HAVE_cc0 13852 rtx_insn *cc0_setter = NULL; 13853 #endif 13854 13855 if (set != 0) 13856 for (inner_dest = SET_DEST (set); 13857 (GET_CODE (inner_dest) == STRICT_LOW_PART 13858 || GET_CODE (inner_dest) == SUBREG 13859 || GET_CODE (inner_dest) == ZERO_EXTRACT); 13860 inner_dest = XEXP (inner_dest, 0)) 13861 ; 13862 13863 /* Verify that it was the set, and not a clobber that 13864 modified the register. 13865 13866 CC0 targets must be careful to maintain setter/user 13867 pairs. If we cannot delete the setter due to side 13868 effects, mark the user with an UNUSED note instead 13869 of deleting it. */ 13870 13871 if (set != 0 && ! side_effects_p (SET_SRC (set)) 13872 && rtx_equal_p (XEXP (note, 0), inner_dest) 13873 #ifdef HAVE_cc0 13874 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) 13875 || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL 13876 && sets_cc0_p (PATTERN (cc0_setter)) > 0)) 13877 #endif 13878 ) 13879 { 13880 /* Move the notes and links of TEM_INSN elsewhere. 13881 This might delete other dead insns recursively. 13882 First set the pattern to something that won't use 13883 any register. */ 13884 rtx old_notes = REG_NOTES (tem_insn); 13885 13886 PATTERN (tem_insn) = pc_rtx; 13887 REG_NOTES (tem_insn) = NULL; 13888 13889 distribute_notes (old_notes, tem_insn, tem_insn, NULL, 13890 NULL_RTX, NULL_RTX, NULL_RTX); 13891 distribute_links (LOG_LINKS (tem_insn)); 13892 13893 SET_INSN_DELETED (tem_insn); 13894 if (tem_insn == i2) 13895 i2 = NULL; 13896 13897 #ifdef HAVE_cc0 13898 /* Delete the setter too. */ 13899 if (cc0_setter) 13900 { 13901 PATTERN (cc0_setter) = pc_rtx; 13902 old_notes = REG_NOTES (cc0_setter); 13903 REG_NOTES (cc0_setter) = NULL; 13904 13905 distribute_notes (old_notes, cc0_setter, 13906 cc0_setter, NULL, 13907 NULL_RTX, NULL_RTX, NULL_RTX); 13908 distribute_links (LOG_LINKS (cc0_setter)); 13909 13910 SET_INSN_DELETED (cc0_setter); 13911 if (cc0_setter == i2) 13912 i2 = NULL; 13913 } 13914 #endif 13915 } 13916 else 13917 { 13918 PUT_REG_NOTE_KIND (note, REG_UNUSED); 13919 13920 /* If there isn't already a REG_UNUSED note, put one 13921 here. Do not place a REG_DEAD note, even if 13922 the register is also used here; that would not 13923 match the algorithm used in lifetime analysis 13924 and can cause the consistency check in the 13925 scheduler to fail. */ 13926 if (! find_regno_note (tem_insn, REG_UNUSED, 13927 REGNO (XEXP (note, 0)))) 13928 place = tem_insn; 13929 break; 13930 } 13931 } 13932 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn)) 13933 || (CALL_P (tem_insn) 13934 && find_reg_fusage (tem_insn, USE, XEXP (note, 0)))) 13935 { 13936 place = tem_insn; 13937 13938 /* If we are doing a 3->2 combination, and we have a 13939 register which formerly died in i3 and was not used 13940 by i2, which now no longer dies in i3 and is used in 13941 i2 but does not die in i2, and place is between i2 13942 and i3, then we may need to move a link from place to 13943 i2. */ 13944 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2) 13945 && from_insn 13946 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2) 13947 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 13948 { 13949 struct insn_link *links = LOG_LINKS (place); 13950 LOG_LINKS (place) = NULL; 13951 distribute_links (links); 13952 } 13953 break; 13954 } 13955 13956 if (tem_insn == BB_HEAD (bb)) 13957 break; 13958 } 13959 13960 } 13961 13962 /* If the register is set or already dead at PLACE, we needn't do 13963 anything with this note if it is still a REG_DEAD note. 13964 We check here if it is set at all, not if is it totally replaced, 13965 which is what `dead_or_set_p' checks, so also check for it being 13966 set partially. */ 13967 13968 if (place && REG_NOTE_KIND (note) == REG_DEAD) 13969 { 13970 unsigned int regno = REGNO (XEXP (note, 0)); 13971 reg_stat_type *rsp = ®_stat[regno]; 13972 13973 if (dead_or_set_p (place, XEXP (note, 0)) 13974 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) 13975 { 13976 /* Unless the register previously died in PLACE, clear 13977 last_death. [I no longer understand why this is 13978 being done.] */ 13979 if (rsp->last_death != place) 13980 rsp->last_death = 0; 13981 place = 0; 13982 } 13983 else 13984 rsp->last_death = place; 13985 13986 /* If this is a death note for a hard reg that is occupying 13987 multiple registers, ensure that we are still using all 13988 parts of the object. If we find a piece of the object 13989 that is unused, we must arrange for an appropriate REG_DEAD 13990 note to be added for it. However, we can't just emit a USE 13991 and tag the note to it, since the register might actually 13992 be dead; so we recourse, and the recursive call then finds 13993 the previous insn that used this register. */ 13994 13995 if (place && regno < FIRST_PSEUDO_REGISTER 13996 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1) 13997 { 13998 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0)); 13999 bool all_used = true; 14000 unsigned int i; 14001 14002 for (i = regno; i < endregno; i++) 14003 if ((! refers_to_regno_p (i, PATTERN (place)) 14004 && ! find_regno_fusage (place, USE, i)) 14005 || dead_or_set_regno_p (place, i)) 14006 { 14007 all_used = false; 14008 break; 14009 } 14010 14011 if (! all_used) 14012 { 14013 /* Put only REG_DEAD notes for pieces that are 14014 not already dead or set. */ 14015 14016 for (i = regno; i < endregno; 14017 i += hard_regno_nregs[i][reg_raw_mode[i]]) 14018 { 14019 rtx piece = regno_reg_rtx[i]; 14020 basic_block bb = this_basic_block; 14021 14022 if (! dead_or_set_p (place, piece) 14023 && ! reg_bitfield_target_p (piece, 14024 PATTERN (place))) 14025 { 14026 rtx new_note = alloc_reg_note (REG_DEAD, piece, 14027 NULL_RTX); 14028 14029 distribute_notes (new_note, place, place, 14030 NULL, NULL_RTX, NULL_RTX, 14031 NULL_RTX); 14032 } 14033 else if (! refers_to_regno_p (i, PATTERN (place)) 14034 && ! find_regno_fusage (place, USE, i)) 14035 for (tem_insn = PREV_INSN (place); ; 14036 tem_insn = PREV_INSN (tem_insn)) 14037 { 14038 if (!NONDEBUG_INSN_P (tem_insn)) 14039 { 14040 if (tem_insn == BB_HEAD (bb)) 14041 break; 14042 continue; 14043 } 14044 if (dead_or_set_p (tem_insn, piece) 14045 || reg_bitfield_target_p (piece, 14046 PATTERN (tem_insn))) 14047 { 14048 add_reg_note (tem_insn, REG_UNUSED, piece); 14049 break; 14050 } 14051 } 14052 } 14053 14054 place = 0; 14055 } 14056 } 14057 } 14058 break; 14059 14060 default: 14061 /* Any other notes should not be present at this point in the 14062 compilation. */ 14063 gcc_unreachable (); 14064 } 14065 14066 if (place) 14067 { 14068 XEXP (note, 1) = REG_NOTES (place); 14069 REG_NOTES (place) = note; 14070 } 14071 14072 if (place2) 14073 add_shallow_copy_of_reg_note (place2, note); 14074 } 14075 } 14076 14077 /* Similarly to above, distribute the LOG_LINKS that used to be present on 14078 I3, I2, and I1 to new locations. This is also called to add a link 14079 pointing at I3 when I3's destination is changed. */ 14080 14081 static void 14082 distribute_links (struct insn_link *links) 14083 { 14084 struct insn_link *link, *next_link; 14085 14086 for (link = links; link; link = next_link) 14087 { 14088 rtx_insn *place = 0; 14089 rtx_insn *insn; 14090 rtx set, reg; 14091 14092 next_link = link->next; 14093 14094 /* If the insn that this link points to is a NOTE, ignore it. */ 14095 if (NOTE_P (link->insn)) 14096 continue; 14097 14098 set = 0; 14099 rtx pat = PATTERN (link->insn); 14100 if (GET_CODE (pat) == SET) 14101 set = pat; 14102 else if (GET_CODE (pat) == PARALLEL) 14103 { 14104 int i; 14105 for (i = 0; i < XVECLEN (pat, 0); i++) 14106 { 14107 set = XVECEXP (pat, 0, i); 14108 if (GET_CODE (set) != SET) 14109 continue; 14110 14111 reg = SET_DEST (set); 14112 while (GET_CODE (reg) == ZERO_EXTRACT 14113 || GET_CODE (reg) == STRICT_LOW_PART 14114 || GET_CODE (reg) == SUBREG) 14115 reg = XEXP (reg, 0); 14116 14117 if (!REG_P (reg)) 14118 continue; 14119 14120 if (REGNO (reg) == link->regno) 14121 break; 14122 } 14123 if (i == XVECLEN (pat, 0)) 14124 continue; 14125 } 14126 else 14127 continue; 14128 14129 reg = SET_DEST (set); 14130 14131 while (GET_CODE (reg) == ZERO_EXTRACT 14132 || GET_CODE (reg) == STRICT_LOW_PART 14133 || GET_CODE (reg) == SUBREG) 14134 reg = XEXP (reg, 0); 14135 14136 /* A LOG_LINK is defined as being placed on the first insn that uses 14137 a register and points to the insn that sets the register. Start 14138 searching at the next insn after the target of the link and stop 14139 when we reach a set of the register or the end of the basic block. 14140 14141 Note that this correctly handles the link that used to point from 14142 I3 to I2. Also note that not much searching is typically done here 14143 since most links don't point very far away. */ 14144 14145 for (insn = NEXT_INSN (link->insn); 14146 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 14147 || BB_HEAD (this_basic_block->next_bb) != insn)); 14148 insn = NEXT_INSN (insn)) 14149 if (DEBUG_INSN_P (insn)) 14150 continue; 14151 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) 14152 { 14153 if (reg_referenced_p (reg, PATTERN (insn))) 14154 place = insn; 14155 break; 14156 } 14157 else if (CALL_P (insn) 14158 && find_reg_fusage (insn, USE, reg)) 14159 { 14160 place = insn; 14161 break; 14162 } 14163 else if (INSN_P (insn) && reg_set_p (reg, insn)) 14164 break; 14165 14166 /* If we found a place to put the link, place it there unless there 14167 is already a link to the same insn as LINK at that point. */ 14168 14169 if (place) 14170 { 14171 struct insn_link *link2; 14172 14173 FOR_EACH_LOG_LINK (link2, place) 14174 if (link2->insn == link->insn && link2->regno == link->regno) 14175 break; 14176 14177 if (link2 == NULL) 14178 { 14179 link->next = LOG_LINKS (place); 14180 LOG_LINKS (place) = link; 14181 14182 /* Set added_links_insn to the earliest insn we added a 14183 link to. */ 14184 if (added_links_insn == 0 14185 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place)) 14186 added_links_insn = place; 14187 } 14188 } 14189 } 14190 } 14191 14192 /* Check for any register or memory mentioned in EQUIV that is not 14193 mentioned in EXPR. This is used to restrict EQUIV to "specializations" 14194 of EXPR where some registers may have been replaced by constants. */ 14195 14196 static bool 14197 unmentioned_reg_p (rtx equiv, rtx expr) 14198 { 14199 subrtx_iterator::array_type array; 14200 FOR_EACH_SUBRTX (iter, array, equiv, NONCONST) 14201 { 14202 const_rtx x = *iter; 14203 if ((REG_P (x) || MEM_P (x)) 14204 && !reg_mentioned_p (x, expr)) 14205 return true; 14206 } 14207 return false; 14208 } 14209 14210 DEBUG_FUNCTION void 14211 dump_combine_stats (FILE *file) 14212 { 14213 fprintf 14214 (file, 14215 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", 14216 combine_attempts, combine_merges, combine_extras, combine_successes); 14217 } 14218 14219 void 14220 dump_combine_total_stats (FILE *file) 14221 { 14222 fprintf 14223 (file, 14224 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", 14225 total_attempts, total_merges, total_extras, total_successes); 14226 } 14227 14228 /* Try combining insns through substitution. */ 14229 static unsigned int 14230 rest_of_handle_combine (void) 14231 { 14232 int rebuild_jump_labels_after_combine; 14233 14234 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN); 14235 df_note_add_problem (); 14236 df_analyze (); 14237 14238 regstat_init_n_sets_and_refs (); 14239 reg_n_sets_max = max_reg_num (); 14240 14241 rebuild_jump_labels_after_combine 14242 = combine_instructions (get_insns (), max_reg_num ()); 14243 14244 /* Combining insns may have turned an indirect jump into a 14245 direct jump. Rebuild the JUMP_LABEL fields of jumping 14246 instructions. */ 14247 if (rebuild_jump_labels_after_combine) 14248 { 14249 timevar_push (TV_JUMP); 14250 rebuild_jump_labels (get_insns ()); 14251 cleanup_cfg (0); 14252 timevar_pop (TV_JUMP); 14253 } 14254 14255 regstat_free_n_sets_and_refs (); 14256 return 0; 14257 } 14258 14259 namespace { 14260 14261 const pass_data pass_data_combine = 14262 { 14263 RTL_PASS, /* type */ 14264 "combine", /* name */ 14265 OPTGROUP_NONE, /* optinfo_flags */ 14266 TV_COMBINE, /* tv_id */ 14267 PROP_cfglayout, /* properties_required */ 14268 0, /* properties_provided */ 14269 0, /* properties_destroyed */ 14270 0, /* todo_flags_start */ 14271 TODO_df_finish, /* todo_flags_finish */ 14272 }; 14273 14274 class pass_combine : public rtl_opt_pass 14275 { 14276 public: 14277 pass_combine (gcc::context *ctxt) 14278 : rtl_opt_pass (pass_data_combine, ctxt) 14279 {} 14280 14281 /* opt_pass methods: */ 14282 virtual bool gate (function *) { return (optimize > 0); } 14283 virtual unsigned int execute (function *) 14284 { 14285 return rest_of_handle_combine (); 14286 } 14287 14288 }; // class pass_combine 14289 14290 } // anon namespace 14291 14292 rtl_opt_pass * 14293 make_pass_combine (gcc::context *ctxt) 14294 { 14295 return new pass_combine (ctxt); 14296 } 14297