1 /* Save and restore call-clobbered registers which are live across a call. 2 Copyright (C) 1989-2015 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "tm.h" 24 #include "rtl.h" 25 #include "regs.h" 26 #include "insn-config.h" 27 #include "flags.h" 28 #include "hard-reg-set.h" 29 #include "recog.h" 30 #include "predict.h" 31 #include "vec.h" 32 #include "hashtab.h" 33 #include "hash-set.h" 34 #include "machmode.h" 35 #include "input.h" 36 #include "function.h" 37 #include "dominance.h" 38 #include "cfg.h" 39 #include "basic-block.h" 40 #include "df.h" 41 #include "reload.h" 42 #include "symtab.h" 43 #include "statistics.h" 44 #include "double-int.h" 45 #include "real.h" 46 #include "fixed-value.h" 47 #include "alias.h" 48 #include "wide-int.h" 49 #include "inchash.h" 50 #include "tree.h" 51 #include "expmed.h" 52 #include "dojump.h" 53 #include "explow.h" 54 #include "calls.h" 55 #include "emit-rtl.h" 56 #include "varasm.h" 57 #include "stmt.h" 58 #include "expr.h" 59 #include "diagnostic-core.h" 60 #include "tm_p.h" 61 #include "addresses.h" 62 #include "ggc.h" 63 #include "dumpfile.h" 64 #include "rtl-iter.h" 65 66 #define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD) 67 68 #define regno_save_mode \ 69 (this_target_reload->x_regno_save_mode) 70 #define cached_reg_save_code \ 71 (this_target_reload->x_cached_reg_save_code) 72 #define cached_reg_restore_code \ 73 (this_target_reload->x_cached_reg_restore_code) 74 75 /* For each hard register, a place on the stack where it can be saved, 76 if needed. */ 77 78 static rtx 79 regno_save_mem[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1]; 80 81 /* The number of elements in the subsequent array. */ 82 static int save_slots_num; 83 84 /* Allocated slots so far. */ 85 static rtx save_slots[FIRST_PSEUDO_REGISTER]; 86 87 /* Set of hard regs currently residing in save area (during insn scan). */ 88 89 static HARD_REG_SET hard_regs_saved; 90 91 /* Number of registers currently in hard_regs_saved. */ 92 93 static int n_regs_saved; 94 95 /* Computed by mark_referenced_regs, all regs referenced in a given 96 insn. */ 97 static HARD_REG_SET referenced_regs; 98 99 100 typedef void refmarker_fn (rtx *loc, machine_mode mode, int hardregno, 101 void *mark_arg); 102 103 static int reg_save_code (int, machine_mode); 104 static int reg_restore_code (int, machine_mode); 105 106 struct saved_hard_reg; 107 static void initiate_saved_hard_regs (void); 108 static void new_saved_hard_reg (int, int); 109 static void finish_saved_hard_regs (void); 110 static int saved_hard_reg_compare_func (const void *, const void *); 111 112 static void mark_set_regs (rtx, const_rtx, void *); 113 static void mark_referenced_regs (rtx *, refmarker_fn *mark, void *mark_arg); 114 static refmarker_fn mark_reg_as_referenced; 115 static refmarker_fn replace_reg_with_saved_mem; 116 static int insert_save (struct insn_chain *, int, int, HARD_REG_SET *, 117 machine_mode *); 118 static int insert_restore (struct insn_chain *, int, int, int, 119 machine_mode *); 120 static struct insn_chain *insert_one_insn (struct insn_chain *, int, int, 121 rtx); 122 static void add_stored_regs (rtx, const_rtx, void *); 123 124 125 126 static GTY(()) rtx savepat; 127 static GTY(()) rtx restpat; 128 static GTY(()) rtx test_reg; 129 static GTY(()) rtx test_mem; 130 static GTY(()) rtx_insn *saveinsn; 131 static GTY(()) rtx_insn *restinsn; 132 133 /* Return the INSN_CODE used to save register REG in mode MODE. */ 134 static int 135 reg_save_code (int reg, machine_mode mode) 136 { 137 bool ok; 138 if (cached_reg_save_code[reg][mode]) 139 return cached_reg_save_code[reg][mode]; 140 if (!HARD_REGNO_MODE_OK (reg, mode)) 141 { 142 /* Depending on how HARD_REGNO_MODE_OK is defined, range propagation 143 might deduce here that reg >= FIRST_PSEUDO_REGISTER. So the assert 144 below silences a warning. */ 145 gcc_assert (reg < FIRST_PSEUDO_REGISTER); 146 cached_reg_save_code[reg][mode] = -1; 147 cached_reg_restore_code[reg][mode] = -1; 148 return -1; 149 } 150 151 /* Update the register number and modes of the register 152 and memory operand. */ 153 SET_REGNO_RAW (test_reg, reg); 154 PUT_MODE (test_reg, mode); 155 PUT_MODE (test_mem, mode); 156 157 /* Force re-recognition of the modified insns. */ 158 INSN_CODE (saveinsn) = -1; 159 INSN_CODE (restinsn) = -1; 160 161 cached_reg_save_code[reg][mode] = recog_memoized (saveinsn); 162 cached_reg_restore_code[reg][mode] = recog_memoized (restinsn); 163 164 /* Now extract both insns and see if we can meet their 165 constraints. We don't know here whether the save and restore will 166 be in size- or speed-tuned code, so just use the set of enabled 167 alternatives. */ 168 ok = (cached_reg_save_code[reg][mode] != -1 169 && cached_reg_restore_code[reg][mode] != -1); 170 if (ok) 171 { 172 extract_insn (saveinsn); 173 ok = constrain_operands (1, get_enabled_alternatives (saveinsn)); 174 extract_insn (restinsn); 175 ok &= constrain_operands (1, get_enabled_alternatives (restinsn)); 176 } 177 178 if (! ok) 179 { 180 cached_reg_save_code[reg][mode] = -1; 181 cached_reg_restore_code[reg][mode] = -1; 182 } 183 gcc_assert (cached_reg_save_code[reg][mode]); 184 return cached_reg_save_code[reg][mode]; 185 } 186 187 /* Return the INSN_CODE used to restore register REG in mode MODE. */ 188 static int 189 reg_restore_code (int reg, machine_mode mode) 190 { 191 if (cached_reg_restore_code[reg][mode]) 192 return cached_reg_restore_code[reg][mode]; 193 /* Populate our cache. */ 194 reg_save_code (reg, mode); 195 return cached_reg_restore_code[reg][mode]; 196 } 197 198 /* Initialize for caller-save. 199 200 Look at all the hard registers that are used by a call and for which 201 reginfo.c has not already excluded from being used across a call. 202 203 Ensure that we can find a mode to save the register and that there is a 204 simple insn to save and restore the register. This latter check avoids 205 problems that would occur if we tried to save the MQ register of some 206 machines directly into memory. */ 207 208 void 209 init_caller_save (void) 210 { 211 rtx addr_reg; 212 int offset; 213 rtx address; 214 int i, j; 215 216 if (caller_save_initialized_p) 217 return; 218 219 caller_save_initialized_p = true; 220 221 CLEAR_HARD_REG_SET (no_caller_save_reg_set); 222 /* First find all the registers that we need to deal with and all 223 the modes that they can have. If we can't find a mode to use, 224 we can't have the register live over calls. */ 225 226 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 227 { 228 if (call_used_regs[i] 229 && !TEST_HARD_REG_BIT (call_fixed_reg_set, i)) 230 { 231 for (j = 1; j <= MOVE_MAX_WORDS; j++) 232 { 233 regno_save_mode[i][j] = HARD_REGNO_CALLER_SAVE_MODE (i, j, 234 VOIDmode); 235 if (regno_save_mode[i][j] == VOIDmode && j == 1) 236 { 237 SET_HARD_REG_BIT (call_fixed_reg_set, i); 238 } 239 } 240 } 241 else 242 regno_save_mode[i][1] = VOIDmode; 243 } 244 245 /* The following code tries to approximate the conditions under which 246 we can easily save and restore a register without scratch registers or 247 other complexities. It will usually work, except under conditions where 248 the validity of an insn operand is dependent on the address offset. 249 No such cases are currently known. 250 251 We first find a typical offset from some BASE_REG_CLASS register. 252 This address is chosen by finding the first register in the class 253 and by finding the smallest power of two that is a valid offset from 254 that register in every mode we will use to save registers. */ 255 256 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 257 if (TEST_HARD_REG_BIT 258 (reg_class_contents 259 [(int) base_reg_class (regno_save_mode[i][1], ADDR_SPACE_GENERIC, 260 PLUS, CONST_INT)], i)) 261 break; 262 263 gcc_assert (i < FIRST_PSEUDO_REGISTER); 264 265 addr_reg = gen_rtx_REG (Pmode, i); 266 267 for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1) 268 { 269 address = gen_rtx_PLUS (Pmode, addr_reg, gen_int_mode (offset, Pmode)); 270 271 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 272 if (regno_save_mode[i][1] != VOIDmode 273 && ! strict_memory_address_p (regno_save_mode[i][1], address)) 274 break; 275 276 if (i == FIRST_PSEUDO_REGISTER) 277 break; 278 } 279 280 /* If we didn't find a valid address, we must use register indirect. */ 281 if (offset == 0) 282 address = addr_reg; 283 284 /* Next we try to form an insn to save and restore the register. We 285 see if such an insn is recognized and meets its constraints. 286 287 To avoid lots of unnecessary RTL allocation, we construct all the RTL 288 once, then modify the memory and register operands in-place. */ 289 290 test_reg = gen_rtx_REG (VOIDmode, 0); 291 test_mem = gen_rtx_MEM (VOIDmode, address); 292 savepat = gen_rtx_SET (VOIDmode, test_mem, test_reg); 293 restpat = gen_rtx_SET (VOIDmode, test_reg, test_mem); 294 295 saveinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, savepat, 0, -1, 0); 296 restinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, restpat, 0, -1, 0); 297 298 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 299 for (j = 1; j <= MOVE_MAX_WORDS; j++) 300 if (reg_save_code (i,regno_save_mode[i][j]) == -1) 301 { 302 regno_save_mode[i][j] = VOIDmode; 303 if (j == 1) 304 { 305 SET_HARD_REG_BIT (call_fixed_reg_set, i); 306 if (call_used_regs[i]) 307 SET_HARD_REG_BIT (no_caller_save_reg_set, i); 308 } 309 } 310 } 311 312 313 314 /* Initialize save areas by showing that we haven't allocated any yet. */ 315 316 void 317 init_save_areas (void) 318 { 319 int i, j; 320 321 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 322 for (j = 1; j <= MOVE_MAX_WORDS; j++) 323 regno_save_mem[i][j] = 0; 324 save_slots_num = 0; 325 326 } 327 328 /* The structure represents a hard register which should be saved 329 through the call. It is used when the integrated register 330 allocator (IRA) is used and sharing save slots is on. */ 331 struct saved_hard_reg 332 { 333 /* Order number starting with 0. */ 334 int num; 335 /* The hard regno. */ 336 int hard_regno; 337 /* Execution frequency of all calls through which given hard 338 register should be saved. */ 339 int call_freq; 340 /* Stack slot reserved to save the hard register through calls. */ 341 rtx slot; 342 /* True if it is first hard register in the chain of hard registers 343 sharing the same stack slot. */ 344 int first_p; 345 /* Order number of the next hard register structure with the same 346 slot in the chain. -1 represents end of the chain. */ 347 int next; 348 }; 349 350 /* Map: hard register number to the corresponding structure. */ 351 static struct saved_hard_reg *hard_reg_map[FIRST_PSEUDO_REGISTER]; 352 353 /* The number of all structures representing hard registers should be 354 saved, in order words, the number of used elements in the following 355 array. */ 356 static int saved_regs_num; 357 358 /* Pointers to all the structures. Index is the order number of the 359 corresponding structure. */ 360 static struct saved_hard_reg *all_saved_regs[FIRST_PSEUDO_REGISTER]; 361 362 /* First called function for work with saved hard registers. */ 363 static void 364 initiate_saved_hard_regs (void) 365 { 366 int i; 367 368 saved_regs_num = 0; 369 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 370 hard_reg_map[i] = NULL; 371 } 372 373 /* Allocate and return new saved hard register with given REGNO and 374 CALL_FREQ. */ 375 static void 376 new_saved_hard_reg (int regno, int call_freq) 377 { 378 struct saved_hard_reg *saved_reg; 379 380 saved_reg 381 = (struct saved_hard_reg *) xmalloc (sizeof (struct saved_hard_reg)); 382 hard_reg_map[regno] = all_saved_regs[saved_regs_num] = saved_reg; 383 saved_reg->num = saved_regs_num++; 384 saved_reg->hard_regno = regno; 385 saved_reg->call_freq = call_freq; 386 saved_reg->first_p = FALSE; 387 saved_reg->next = -1; 388 } 389 390 /* Free memory allocated for the saved hard registers. */ 391 static void 392 finish_saved_hard_regs (void) 393 { 394 int i; 395 396 for (i = 0; i < saved_regs_num; i++) 397 free (all_saved_regs[i]); 398 } 399 400 /* The function is used to sort the saved hard register structures 401 according their frequency. */ 402 static int 403 saved_hard_reg_compare_func (const void *v1p, const void *v2p) 404 { 405 const struct saved_hard_reg *p1 = *(struct saved_hard_reg * const *) v1p; 406 const struct saved_hard_reg *p2 = *(struct saved_hard_reg * const *) v2p; 407 408 if (flag_omit_frame_pointer) 409 { 410 if (p1->call_freq - p2->call_freq != 0) 411 return p1->call_freq - p2->call_freq; 412 } 413 else if (p2->call_freq - p1->call_freq != 0) 414 return p2->call_freq - p1->call_freq; 415 416 return p1->num - p2->num; 417 } 418 419 /* Allocate save areas for any hard registers that might need saving. 420 We take a conservative approach here and look for call-clobbered hard 421 registers that are assigned to pseudos that cross calls. This may 422 overestimate slightly (especially if some of these registers are later 423 used as spill registers), but it should not be significant. 424 425 For IRA we use priority coloring to decrease stack slots needed for 426 saving hard registers through calls. We build conflicts for them 427 to do coloring. 428 429 Future work: 430 431 In the fallback case we should iterate backwards across all possible 432 modes for the save, choosing the largest available one instead of 433 falling back to the smallest mode immediately. (eg TF -> DF -> SF). 434 435 We do not try to use "move multiple" instructions that exist 436 on some machines (such as the 68k moveml). It could be a win to try 437 and use them when possible. The hard part is doing it in a way that is 438 machine independent since they might be saving non-consecutive 439 registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */ 440 441 void 442 setup_save_areas (void) 443 { 444 int i, j, k, freq; 445 HARD_REG_SET hard_regs_used; 446 struct saved_hard_reg *saved_reg; 447 rtx_insn *insn; 448 struct insn_chain *chain, *next; 449 unsigned int regno; 450 HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets; 451 reg_set_iterator rsi; 452 453 CLEAR_HARD_REG_SET (hard_regs_used); 454 455 /* Find every CALL_INSN and record which hard regs are live across the 456 call into HARD_REG_MAP and HARD_REGS_USED. */ 457 initiate_saved_hard_regs (); 458 /* Create hard reg saved regs. */ 459 for (chain = reload_insn_chain; chain != 0; chain = next) 460 { 461 rtx cheap; 462 463 insn = chain->insn; 464 next = chain->next; 465 if (!CALL_P (insn) 466 || find_reg_note (insn, REG_NORETURN, NULL)) 467 continue; 468 freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)); 469 REG_SET_TO_HARD_REG_SET (hard_regs_to_save, 470 &chain->live_throughout); 471 get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); 472 473 /* Record all registers set in this call insn. These don't 474 need to be saved. N.B. the call insn might set a subreg 475 of a multi-hard-reg pseudo; then the pseudo is considered 476 live during the call, but the subreg that is set 477 isn't. */ 478 CLEAR_HARD_REG_SET (this_insn_sets); 479 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); 480 /* Sibcalls are considered to set the return value. */ 481 if (SIBLING_CALL_P (insn) && crtl->return_rtx) 482 mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); 483 484 AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); 485 AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); 486 AND_HARD_REG_SET (hard_regs_to_save, used_regs); 487 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 488 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) 489 { 490 if (hard_reg_map[regno] != NULL) 491 hard_reg_map[regno]->call_freq += freq; 492 else 493 new_saved_hard_reg (regno, freq); 494 SET_HARD_REG_BIT (hard_regs_used, regno); 495 } 496 cheap = find_reg_note (insn, REG_RETURNED, NULL); 497 if (cheap) 498 cheap = XEXP (cheap, 0); 499 /* Look through all live pseudos, mark their hard registers. */ 500 EXECUTE_IF_SET_IN_REG_SET 501 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) 502 { 503 int r = reg_renumber[regno]; 504 int bound; 505 506 if (r < 0 || regno_reg_rtx[regno] == cheap) 507 continue; 508 509 bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; 510 for (; r < bound; r++) 511 if (TEST_HARD_REG_BIT (used_regs, r)) 512 { 513 if (hard_reg_map[r] != NULL) 514 hard_reg_map[r]->call_freq += freq; 515 else 516 new_saved_hard_reg (r, freq); 517 SET_HARD_REG_BIT (hard_regs_to_save, r); 518 SET_HARD_REG_BIT (hard_regs_used, r); 519 } 520 } 521 } 522 523 /* If requested, figure out which hard regs can share save slots. */ 524 if (optimize && flag_ira_share_save_slots) 525 { 526 rtx slot; 527 char *saved_reg_conflicts; 528 int next_k; 529 struct saved_hard_reg *saved_reg2, *saved_reg3; 530 int call_saved_regs_num; 531 struct saved_hard_reg *call_saved_regs[FIRST_PSEUDO_REGISTER]; 532 int best_slot_num; 533 int prev_save_slots_num; 534 rtx prev_save_slots[FIRST_PSEUDO_REGISTER]; 535 536 /* Find saved hard register conflicts. */ 537 saved_reg_conflicts = (char *) xmalloc (saved_regs_num * saved_regs_num); 538 memset (saved_reg_conflicts, 0, saved_regs_num * saved_regs_num); 539 for (chain = reload_insn_chain; chain != 0; chain = next) 540 { 541 rtx cheap; 542 call_saved_regs_num = 0; 543 insn = chain->insn; 544 next = chain->next; 545 if (!CALL_P (insn) 546 || find_reg_note (insn, REG_NORETURN, NULL)) 547 continue; 548 549 cheap = find_reg_note (insn, REG_RETURNED, NULL); 550 if (cheap) 551 cheap = XEXP (cheap, 0); 552 553 REG_SET_TO_HARD_REG_SET (hard_regs_to_save, 554 &chain->live_throughout); 555 get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); 556 557 /* Record all registers set in this call insn. These don't 558 need to be saved. N.B. the call insn might set a subreg 559 of a multi-hard-reg pseudo; then the pseudo is considered 560 live during the call, but the subreg that is set 561 isn't. */ 562 CLEAR_HARD_REG_SET (this_insn_sets); 563 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); 564 /* Sibcalls are considered to set the return value, 565 compare df-scan.c:df_get_call_refs. */ 566 if (SIBLING_CALL_P (insn) && crtl->return_rtx) 567 mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); 568 569 AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); 570 AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); 571 AND_HARD_REG_SET (hard_regs_to_save, used_regs); 572 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 573 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) 574 { 575 gcc_assert (hard_reg_map[regno] != NULL); 576 call_saved_regs[call_saved_regs_num++] = hard_reg_map[regno]; 577 } 578 /* Look through all live pseudos, mark their hard registers. */ 579 EXECUTE_IF_SET_IN_REG_SET 580 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) 581 { 582 int r = reg_renumber[regno]; 583 int bound; 584 585 if (r < 0 || regno_reg_rtx[regno] == cheap) 586 continue; 587 588 bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; 589 for (; r < bound; r++) 590 if (TEST_HARD_REG_BIT (used_regs, r)) 591 call_saved_regs[call_saved_regs_num++] = hard_reg_map[r]; 592 } 593 for (i = 0; i < call_saved_regs_num; i++) 594 { 595 saved_reg = call_saved_regs[i]; 596 for (j = 0; j < call_saved_regs_num; j++) 597 if (i != j) 598 { 599 saved_reg2 = call_saved_regs[j]; 600 saved_reg_conflicts[saved_reg->num * saved_regs_num 601 + saved_reg2->num] 602 = saved_reg_conflicts[saved_reg2->num * saved_regs_num 603 + saved_reg->num] 604 = TRUE; 605 } 606 } 607 } 608 /* Sort saved hard regs. */ 609 qsort (all_saved_regs, saved_regs_num, sizeof (struct saved_hard_reg *), 610 saved_hard_reg_compare_func); 611 /* Initiate slots available from the previous reload 612 iteration. */ 613 prev_save_slots_num = save_slots_num; 614 memcpy (prev_save_slots, save_slots, save_slots_num * sizeof (rtx)); 615 save_slots_num = 0; 616 /* Allocate stack slots for the saved hard registers. */ 617 for (i = 0; i < saved_regs_num; i++) 618 { 619 saved_reg = all_saved_regs[i]; 620 regno = saved_reg->hard_regno; 621 for (j = 0; j < i; j++) 622 { 623 saved_reg2 = all_saved_regs[j]; 624 if (! saved_reg2->first_p) 625 continue; 626 slot = saved_reg2->slot; 627 for (k = j; k >= 0; k = next_k) 628 { 629 saved_reg3 = all_saved_regs[k]; 630 next_k = saved_reg3->next; 631 if (saved_reg_conflicts[saved_reg->num * saved_regs_num 632 + saved_reg3->num]) 633 break; 634 } 635 if (k < 0 636 && (GET_MODE_SIZE (regno_save_mode[regno][1]) 637 <= GET_MODE_SIZE (regno_save_mode 638 [saved_reg2->hard_regno][1]))) 639 { 640 saved_reg->slot 641 = adjust_address_nv 642 (slot, regno_save_mode[saved_reg->hard_regno][1], 0); 643 regno_save_mem[regno][1] = saved_reg->slot; 644 saved_reg->next = saved_reg2->next; 645 saved_reg2->next = i; 646 if (dump_file != NULL) 647 fprintf (dump_file, "%d uses slot of %d\n", 648 regno, saved_reg2->hard_regno); 649 break; 650 } 651 } 652 if (j == i) 653 { 654 saved_reg->first_p = TRUE; 655 for (best_slot_num = -1, j = 0; j < prev_save_slots_num; j++) 656 { 657 slot = prev_save_slots[j]; 658 if (slot == NULL_RTX) 659 continue; 660 if (GET_MODE_SIZE (regno_save_mode[regno][1]) 661 <= GET_MODE_SIZE (GET_MODE (slot)) 662 && best_slot_num < 0) 663 best_slot_num = j; 664 if (GET_MODE (slot) == regno_save_mode[regno][1]) 665 break; 666 } 667 if (best_slot_num >= 0) 668 { 669 saved_reg->slot = prev_save_slots[best_slot_num]; 670 saved_reg->slot 671 = adjust_address_nv 672 (saved_reg->slot, 673 regno_save_mode[saved_reg->hard_regno][1], 0); 674 if (dump_file != NULL) 675 fprintf (dump_file, 676 "%d uses a slot from prev iteration\n", regno); 677 prev_save_slots[best_slot_num] = NULL_RTX; 678 if (best_slot_num + 1 == prev_save_slots_num) 679 prev_save_slots_num--; 680 } 681 else 682 { 683 saved_reg->slot 684 = assign_stack_local_1 685 (regno_save_mode[regno][1], 686 GET_MODE_SIZE (regno_save_mode[regno][1]), 0, 687 ASLK_REDUCE_ALIGN); 688 if (dump_file != NULL) 689 fprintf (dump_file, "%d uses a new slot\n", regno); 690 } 691 regno_save_mem[regno][1] = saved_reg->slot; 692 save_slots[save_slots_num++] = saved_reg->slot; 693 } 694 } 695 free (saved_reg_conflicts); 696 finish_saved_hard_regs (); 697 } 698 else 699 { 700 /* We are not sharing slots. 701 702 Run through all the call-used hard-registers and allocate 703 space for each in the caller-save area. Try to allocate space 704 in a manner which allows multi-register saves/restores to be done. */ 705 706 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 707 for (j = MOVE_MAX_WORDS; j > 0; j--) 708 { 709 int do_save = 1; 710 711 /* If no mode exists for this size, try another. Also break out 712 if we have already saved this hard register. */ 713 if (regno_save_mode[i][j] == VOIDmode || regno_save_mem[i][1] != 0) 714 continue; 715 716 /* See if any register in this group has been saved. */ 717 for (k = 0; k < j; k++) 718 if (regno_save_mem[i + k][1]) 719 { 720 do_save = 0; 721 break; 722 } 723 if (! do_save) 724 continue; 725 726 for (k = 0; k < j; k++) 727 if (! TEST_HARD_REG_BIT (hard_regs_used, i + k)) 728 { 729 do_save = 0; 730 break; 731 } 732 if (! do_save) 733 continue; 734 735 /* We have found an acceptable mode to store in. Since 736 hard register is always saved in the widest mode 737 available, the mode may be wider than necessary, it is 738 OK to reduce the alignment of spill space. We will 739 verify that it is equal to or greater than required 740 when we restore and save the hard register in 741 insert_restore and insert_save. */ 742 regno_save_mem[i][j] 743 = assign_stack_local_1 (regno_save_mode[i][j], 744 GET_MODE_SIZE (regno_save_mode[i][j]), 745 0, ASLK_REDUCE_ALIGN); 746 747 /* Setup single word save area just in case... */ 748 for (k = 0; k < j; k++) 749 /* This should not depend on WORDS_BIG_ENDIAN. 750 The order of words in regs is the same as in memory. */ 751 regno_save_mem[i + k][1] 752 = adjust_address_nv (regno_save_mem[i][j], 753 regno_save_mode[i + k][1], 754 k * UNITS_PER_WORD); 755 } 756 } 757 758 /* Now loop again and set the alias set of any save areas we made to 759 the alias set used to represent frame objects. */ 760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 761 for (j = MOVE_MAX_WORDS; j > 0; j--) 762 if (regno_save_mem[i][j] != 0) 763 set_mem_alias_set (regno_save_mem[i][j], get_frame_alias_set ()); 764 } 765 766 767 768 /* Find the places where hard regs are live across calls and save them. */ 769 770 void 771 save_call_clobbered_regs (void) 772 { 773 struct insn_chain *chain, *next, *last = NULL; 774 machine_mode save_mode [FIRST_PSEUDO_REGISTER]; 775 776 /* Computed in mark_set_regs, holds all registers set by the current 777 instruction. */ 778 HARD_REG_SET this_insn_sets; 779 780 CLEAR_HARD_REG_SET (hard_regs_saved); 781 n_regs_saved = 0; 782 783 for (chain = reload_insn_chain; chain != 0; chain = next) 784 { 785 rtx_insn *insn = chain->insn; 786 enum rtx_code code = GET_CODE (insn); 787 788 next = chain->next; 789 790 gcc_assert (!chain->is_caller_save_insn); 791 792 if (NONDEBUG_INSN_P (insn)) 793 { 794 /* If some registers have been saved, see if INSN references 795 any of them. We must restore them before the insn if so. */ 796 797 if (n_regs_saved) 798 { 799 int regno; 800 HARD_REG_SET this_insn_sets; 801 802 if (code == JUMP_INSN) 803 /* Restore all registers if this is a JUMP_INSN. */ 804 COPY_HARD_REG_SET (referenced_regs, hard_regs_saved); 805 else 806 { 807 CLEAR_HARD_REG_SET (referenced_regs); 808 mark_referenced_regs (&PATTERN (insn), 809 mark_reg_as_referenced, NULL); 810 AND_HARD_REG_SET (referenced_regs, hard_regs_saved); 811 } 812 813 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 814 if (TEST_HARD_REG_BIT (referenced_regs, regno)) 815 regno += insert_restore (chain, 1, regno, MOVE_MAX_WORDS, 816 save_mode); 817 /* If a saved register is set after the call, this means we no 818 longer should restore it. This can happen when parts of a 819 multi-word pseudo do not conflict with other pseudos, so 820 IRA may allocate the same hard register for both. One may 821 be live across the call, while the other is set 822 afterwards. */ 823 CLEAR_HARD_REG_SET (this_insn_sets); 824 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); 825 AND_COMPL_HARD_REG_SET (hard_regs_saved, this_insn_sets); 826 } 827 828 if (code == CALL_INSN 829 && ! SIBLING_CALL_P (insn) 830 && ! find_reg_note (insn, REG_NORETURN, NULL)) 831 { 832 unsigned regno; 833 HARD_REG_SET hard_regs_to_save; 834 HARD_REG_SET call_def_reg_set; 835 reg_set_iterator rsi; 836 rtx cheap; 837 838 cheap = find_reg_note (insn, REG_RETURNED, NULL); 839 if (cheap) 840 cheap = XEXP (cheap, 0); 841 842 /* Use the register life information in CHAIN to compute which 843 regs are live during the call. */ 844 REG_SET_TO_HARD_REG_SET (hard_regs_to_save, 845 &chain->live_throughout); 846 /* Save hard registers always in the widest mode available. */ 847 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 848 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) 849 save_mode [regno] = regno_save_mode [regno][1]; 850 else 851 save_mode [regno] = VOIDmode; 852 853 /* Look through all live pseudos, mark their hard registers 854 and choose proper mode for saving. */ 855 EXECUTE_IF_SET_IN_REG_SET 856 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) 857 { 858 int r = reg_renumber[regno]; 859 int nregs; 860 machine_mode mode; 861 862 if (r < 0 || regno_reg_rtx[regno] == cheap) 863 continue; 864 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; 865 mode = HARD_REGNO_CALLER_SAVE_MODE 866 (r, nregs, PSEUDO_REGNO_MODE (regno)); 867 if (GET_MODE_BITSIZE (mode) 868 > GET_MODE_BITSIZE (save_mode[r])) 869 save_mode[r] = mode; 870 while (nregs-- > 0) 871 SET_HARD_REG_BIT (hard_regs_to_save, r + nregs); 872 } 873 874 /* Record all registers set in this call insn. These don't need 875 to be saved. N.B. the call insn might set a subreg of a 876 multi-hard-reg pseudo; then the pseudo is considered live 877 during the call, but the subreg that is set isn't. */ 878 CLEAR_HARD_REG_SET (this_insn_sets); 879 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); 880 881 /* Compute which hard regs must be saved before this call. */ 882 AND_COMPL_HARD_REG_SET (hard_regs_to_save, call_fixed_reg_set); 883 AND_COMPL_HARD_REG_SET (hard_regs_to_save, this_insn_sets); 884 AND_COMPL_HARD_REG_SET (hard_regs_to_save, hard_regs_saved); 885 get_call_reg_set_usage (insn, &call_def_reg_set, 886 call_used_reg_set); 887 AND_HARD_REG_SET (hard_regs_to_save, call_def_reg_set); 888 889 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 890 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) 891 regno += insert_save (chain, 1, regno, &hard_regs_to_save, save_mode); 892 893 /* Must recompute n_regs_saved. */ 894 n_regs_saved = 0; 895 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 896 if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) 897 n_regs_saved++; 898 899 if (cheap 900 && HARD_REGISTER_P (cheap) 901 && TEST_HARD_REG_BIT (call_used_reg_set, REGNO (cheap))) 902 { 903 rtx dest, newpat; 904 rtx pat = PATTERN (insn); 905 if (GET_CODE (pat) == PARALLEL) 906 pat = XVECEXP (pat, 0, 0); 907 dest = SET_DEST (pat); 908 /* For multiple return values dest is PARALLEL. 909 Currently we handle only single return value case. */ 910 if (REG_P (dest)) 911 { 912 newpat = gen_rtx_SET (VOIDmode, cheap, copy_rtx (dest)); 913 chain = insert_one_insn (chain, 0, -1, newpat); 914 } 915 } 916 } 917 last = chain; 918 } 919 else if (DEBUG_INSN_P (insn) && n_regs_saved) 920 mark_referenced_regs (&PATTERN (insn), 921 replace_reg_with_saved_mem, 922 save_mode); 923 924 if (chain->next == 0 || chain->next->block != chain->block) 925 { 926 int regno; 927 /* At the end of the basic block, we must restore any registers that 928 remain saved. If the last insn in the block is a JUMP_INSN, put 929 the restore before the insn, otherwise, put it after the insn. */ 930 931 if (n_regs_saved 932 && DEBUG_INSN_P (insn) 933 && last 934 && last->block == chain->block) 935 { 936 rtx_insn *ins, *prev; 937 basic_block bb = BLOCK_FOR_INSN (insn); 938 939 /* When adding hard reg restores after a DEBUG_INSN, move 940 all notes between last real insn and this DEBUG_INSN after 941 the DEBUG_INSN, otherwise we could get code 942 -g/-g0 differences. */ 943 for (ins = PREV_INSN (insn); ins != last->insn; ins = prev) 944 { 945 prev = PREV_INSN (ins); 946 if (NOTE_P (ins)) 947 { 948 SET_NEXT_INSN (prev) = NEXT_INSN (ins); 949 SET_PREV_INSN (NEXT_INSN (ins)) = prev; 950 SET_PREV_INSN (ins) = insn; 951 SET_NEXT_INSN (ins) = NEXT_INSN (insn); 952 SET_NEXT_INSN (insn) = ins; 953 if (NEXT_INSN (ins)) 954 SET_PREV_INSN (NEXT_INSN (ins)) = ins; 955 if (BB_END (bb) == insn) 956 BB_END (bb) = ins; 957 } 958 else 959 gcc_assert (DEBUG_INSN_P (ins)); 960 } 961 } 962 last = NULL; 963 964 if (n_regs_saved) 965 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 966 if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) 967 regno += insert_restore (chain, JUMP_P (insn), 968 regno, MOVE_MAX_WORDS, save_mode); 969 } 970 } 971 } 972 973 /* Here from note_stores, or directly from save_call_clobbered_regs, when 974 an insn stores a value in a register. 975 Set the proper bit or bits in this_insn_sets. All pseudos that have 976 been assigned hard regs have had their register number changed already, 977 so we can ignore pseudos. */ 978 static void 979 mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data) 980 { 981 int regno, endregno, i; 982 HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data; 983 984 if (GET_CODE (reg) == SUBREG) 985 { 986 rtx inner = SUBREG_REG (reg); 987 if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER) 988 return; 989 regno = subreg_regno (reg); 990 endregno = regno + subreg_nregs (reg); 991 } 992 else if (REG_P (reg) 993 && REGNO (reg) < FIRST_PSEUDO_REGISTER) 994 { 995 regno = REGNO (reg); 996 endregno = END_HARD_REGNO (reg); 997 } 998 else 999 return; 1000 1001 for (i = regno; i < endregno; i++) 1002 SET_HARD_REG_BIT (*this_insn_sets, i); 1003 } 1004 1005 /* Here from note_stores when an insn stores a value in a register. 1006 Set the proper bit or bits in the passed regset. All pseudos that have 1007 been assigned hard regs have had their register number changed already, 1008 so we can ignore pseudos. */ 1009 static void 1010 add_stored_regs (rtx reg, const_rtx setter, void *data) 1011 { 1012 int regno, endregno, i; 1013 machine_mode mode = GET_MODE (reg); 1014 int offset = 0; 1015 1016 if (GET_CODE (setter) == CLOBBER) 1017 return; 1018 1019 if (GET_CODE (reg) == SUBREG 1020 && REG_P (SUBREG_REG (reg)) 1021 && REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER) 1022 { 1023 offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)), 1024 GET_MODE (SUBREG_REG (reg)), 1025 SUBREG_BYTE (reg), 1026 GET_MODE (reg)); 1027 regno = REGNO (SUBREG_REG (reg)) + offset; 1028 endregno = regno + subreg_nregs (reg); 1029 } 1030 else 1031 { 1032 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) 1033 return; 1034 1035 regno = REGNO (reg) + offset; 1036 endregno = end_hard_regno (mode, regno); 1037 } 1038 1039 for (i = regno; i < endregno; i++) 1040 SET_REGNO_REG_SET ((regset) data, i); 1041 } 1042 1043 /* Walk X and record all referenced registers in REFERENCED_REGS. */ 1044 static void 1045 mark_referenced_regs (rtx *loc, refmarker_fn *mark, void *arg) 1046 { 1047 enum rtx_code code = GET_CODE (*loc); 1048 const char *fmt; 1049 int i, j; 1050 1051 if (code == SET) 1052 mark_referenced_regs (&SET_SRC (*loc), mark, arg); 1053 if (code == SET || code == CLOBBER) 1054 { 1055 loc = &SET_DEST (*loc); 1056 code = GET_CODE (*loc); 1057 if ((code == REG && REGNO (*loc) < FIRST_PSEUDO_REGISTER) 1058 || code == PC || code == CC0 1059 || (code == SUBREG && REG_P (SUBREG_REG (*loc)) 1060 && REGNO (SUBREG_REG (*loc)) < FIRST_PSEUDO_REGISTER 1061 /* If we're setting only part of a multi-word register, 1062 we shall mark it as referenced, because the words 1063 that are not being set should be restored. */ 1064 && ((GET_MODE_SIZE (GET_MODE (*loc)) 1065 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc)))) 1066 || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc))) 1067 <= UNITS_PER_WORD)))) 1068 return; 1069 } 1070 if (code == MEM || code == SUBREG) 1071 { 1072 loc = &XEXP (*loc, 0); 1073 code = GET_CODE (*loc); 1074 } 1075 1076 if (code == REG) 1077 { 1078 int regno = REGNO (*loc); 1079 int hardregno = (regno < FIRST_PSEUDO_REGISTER ? regno 1080 : reg_renumber[regno]); 1081 1082 if (hardregno >= 0) 1083 mark (loc, GET_MODE (*loc), hardregno, arg); 1084 else if (arg) 1085 /* ??? Will we ever end up with an equiv expression in a debug 1086 insn, that would have required restoring a reg, or will 1087 reload take care of it for us? */ 1088 return; 1089 /* If this is a pseudo that did not get a hard register, scan its 1090 memory location, since it might involve the use of another 1091 register, which might be saved. */ 1092 else if (reg_equiv_mem (regno) != 0) 1093 mark_referenced_regs (&XEXP (reg_equiv_mem (regno), 0), mark, arg); 1094 else if (reg_equiv_address (regno) != 0) 1095 mark_referenced_regs (®_equiv_address (regno), mark, arg); 1096 return; 1097 } 1098 1099 fmt = GET_RTX_FORMAT (code); 1100 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1101 { 1102 if (fmt[i] == 'e') 1103 mark_referenced_regs (&XEXP (*loc, i), mark, arg); 1104 else if (fmt[i] == 'E') 1105 for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) 1106 mark_referenced_regs (&XVECEXP (*loc, i, j), mark, arg); 1107 } 1108 } 1109 1110 /* Parameter function for mark_referenced_regs() that adds registers 1111 present in the insn and in equivalent mems and addresses to 1112 referenced_regs. */ 1113 1114 static void 1115 mark_reg_as_referenced (rtx *loc ATTRIBUTE_UNUSED, 1116 machine_mode mode, 1117 int hardregno, 1118 void *arg ATTRIBUTE_UNUSED) 1119 { 1120 add_to_hard_reg_set (&referenced_regs, mode, hardregno); 1121 } 1122 1123 /* Parameter function for mark_referenced_regs() that replaces 1124 registers referenced in a debug_insn that would have been restored, 1125 should it be a non-debug_insn, with their save locations. */ 1126 1127 static void 1128 replace_reg_with_saved_mem (rtx *loc, 1129 machine_mode mode, 1130 int regno, 1131 void *arg) 1132 { 1133 unsigned int i, nregs = hard_regno_nregs [regno][mode]; 1134 rtx mem; 1135 machine_mode *save_mode = (machine_mode *)arg; 1136 1137 for (i = 0; i < nregs; i++) 1138 if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) 1139 break; 1140 1141 /* If none of the registers in the range would need restoring, we're 1142 all set. */ 1143 if (i == nregs) 1144 return; 1145 1146 while (++i < nregs) 1147 if (!TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) 1148 break; 1149 1150 if (i == nregs 1151 && regno_save_mem[regno][nregs]) 1152 { 1153 mem = copy_rtx (regno_save_mem[regno][nregs]); 1154 1155 if (nregs == (unsigned int) hard_regno_nregs[regno][save_mode[regno]]) 1156 mem = adjust_address_nv (mem, save_mode[regno], 0); 1157 1158 if (GET_MODE (mem) != mode) 1159 { 1160 /* This is gen_lowpart_if_possible(), but without validating 1161 the newly-formed address. */ 1162 int offset = 0; 1163 1164 if (WORDS_BIG_ENDIAN) 1165 offset = (MAX (GET_MODE_SIZE (GET_MODE (mem)), UNITS_PER_WORD) 1166 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); 1167 if (BYTES_BIG_ENDIAN) 1168 /* Adjust the address so that the address-after-the-data is 1169 unchanged. */ 1170 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) 1171 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (mem)))); 1172 1173 mem = adjust_address_nv (mem, mode, offset); 1174 } 1175 } 1176 else 1177 { 1178 mem = gen_rtx_CONCATN (mode, rtvec_alloc (nregs)); 1179 for (i = 0; i < nregs; i++) 1180 if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) 1181 { 1182 gcc_assert (regno_save_mem[regno + i][1]); 1183 XVECEXP (mem, 0, i) = copy_rtx (regno_save_mem[regno + i][1]); 1184 } 1185 else 1186 { 1187 machine_mode smode = save_mode[regno]; 1188 gcc_assert (smode != VOIDmode); 1189 if (hard_regno_nregs [regno][smode] > 1) 1190 smode = mode_for_size (GET_MODE_SIZE (mode) / nregs, 1191 GET_MODE_CLASS (mode), 0); 1192 XVECEXP (mem, 0, i) = gen_rtx_REG (smode, regno + i); 1193 } 1194 } 1195 1196 gcc_assert (GET_MODE (mem) == mode); 1197 *loc = mem; 1198 } 1199 1200 1201 /* Insert a sequence of insns to restore. Place these insns in front of 1202 CHAIN if BEFORE_P is nonzero, behind the insn otherwise. MAXRESTORE is 1203 the maximum number of registers which should be restored during this call. 1204 It should never be less than 1 since we only work with entire registers. 1205 1206 Note that we have verified in init_caller_save that we can do this 1207 with a simple SET, so use it. Set INSN_CODE to what we save there 1208 since the address might not be valid so the insn might not be recognized. 1209 These insns will be reloaded and have register elimination done by 1210 find_reload, so we need not worry about that here. 1211 1212 Return the extra number of registers saved. */ 1213 1214 static int 1215 insert_restore (struct insn_chain *chain, int before_p, int regno, 1216 int maxrestore, machine_mode *save_mode) 1217 { 1218 int i, k; 1219 rtx pat = NULL_RTX; 1220 int code; 1221 unsigned int numregs = 0; 1222 struct insn_chain *new_chain; 1223 rtx mem; 1224 1225 /* A common failure mode if register status is not correct in the 1226 RTL is for this routine to be called with a REGNO we didn't 1227 expect to save. That will cause us to write an insn with a (nil) 1228 SET_DEST or SET_SRC. Instead of doing so and causing a crash 1229 later, check for this common case here instead. This will remove 1230 one step in debugging such problems. */ 1231 gcc_assert (regno_save_mem[regno][1]); 1232 1233 /* Get the pattern to emit and update our status. 1234 1235 See if we can restore `maxrestore' registers at once. Work 1236 backwards to the single register case. */ 1237 for (i = maxrestore; i > 0; i--) 1238 { 1239 int j; 1240 int ok = 1; 1241 1242 if (regno_save_mem[regno][i] == 0) 1243 continue; 1244 1245 for (j = 0; j < i; j++) 1246 if (! TEST_HARD_REG_BIT (hard_regs_saved, regno + j)) 1247 { 1248 ok = 0; 1249 break; 1250 } 1251 /* Must do this one restore at a time. */ 1252 if (! ok) 1253 continue; 1254 1255 numregs = i; 1256 break; 1257 } 1258 1259 mem = regno_save_mem [regno][numregs]; 1260 if (save_mode [regno] != VOIDmode 1261 && save_mode [regno] != GET_MODE (mem) 1262 && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] 1263 /* Check that insn to restore REGNO in save_mode[regno] is 1264 correct. */ 1265 && reg_save_code (regno, save_mode[regno]) >= 0) 1266 mem = adjust_address_nv (mem, save_mode[regno], 0); 1267 else 1268 mem = copy_rtx (mem); 1269 1270 /* Verify that the alignment of spill space is equal to or greater 1271 than required. */ 1272 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, 1273 GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); 1274 1275 pat = gen_rtx_SET (VOIDmode, 1276 gen_rtx_REG (GET_MODE (mem), 1277 regno), mem); 1278 code = reg_restore_code (regno, GET_MODE (mem)); 1279 new_chain = insert_one_insn (chain, before_p, code, pat); 1280 1281 /* Clear status for all registers we restored. */ 1282 for (k = 0; k < i; k++) 1283 { 1284 CLEAR_HARD_REG_BIT (hard_regs_saved, regno + k); 1285 SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); 1286 n_regs_saved--; 1287 } 1288 1289 /* Tell our callers how many extra registers we saved/restored. */ 1290 return numregs - 1; 1291 } 1292 1293 /* Like insert_restore above, but save registers instead. */ 1294 1295 static int 1296 insert_save (struct insn_chain *chain, int before_p, int regno, 1297 HARD_REG_SET (*to_save), machine_mode *save_mode) 1298 { 1299 int i; 1300 unsigned int k; 1301 rtx pat = NULL_RTX; 1302 int code; 1303 unsigned int numregs = 0; 1304 struct insn_chain *new_chain; 1305 rtx mem; 1306 1307 /* A common failure mode if register status is not correct in the 1308 RTL is for this routine to be called with a REGNO we didn't 1309 expect to save. That will cause us to write an insn with a (nil) 1310 SET_DEST or SET_SRC. Instead of doing so and causing a crash 1311 later, check for this common case here. This will remove one 1312 step in debugging such problems. */ 1313 gcc_assert (regno_save_mem[regno][1]); 1314 1315 /* Get the pattern to emit and update our status. 1316 1317 See if we can save several registers with a single instruction. 1318 Work backwards to the single register case. */ 1319 for (i = MOVE_MAX_WORDS; i > 0; i--) 1320 { 1321 int j; 1322 int ok = 1; 1323 if (regno_save_mem[regno][i] == 0) 1324 continue; 1325 1326 for (j = 0; j < i; j++) 1327 if (! TEST_HARD_REG_BIT (*to_save, regno + j)) 1328 { 1329 ok = 0; 1330 break; 1331 } 1332 /* Must do this one save at a time. */ 1333 if (! ok) 1334 continue; 1335 1336 numregs = i; 1337 break; 1338 } 1339 1340 mem = regno_save_mem [regno][numregs]; 1341 if (save_mode [regno] != VOIDmode 1342 && save_mode [regno] != GET_MODE (mem) 1343 && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] 1344 /* Check that insn to save REGNO in save_mode[regno] is 1345 correct. */ 1346 && reg_save_code (regno, save_mode[regno]) >= 0) 1347 mem = adjust_address_nv (mem, save_mode[regno], 0); 1348 else 1349 mem = copy_rtx (mem); 1350 1351 /* Verify that the alignment of spill space is equal to or greater 1352 than required. */ 1353 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, 1354 GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); 1355 1356 pat = gen_rtx_SET (VOIDmode, mem, 1357 gen_rtx_REG (GET_MODE (mem), 1358 regno)); 1359 code = reg_save_code (regno, GET_MODE (mem)); 1360 new_chain = insert_one_insn (chain, before_p, code, pat); 1361 1362 /* Set hard_regs_saved and dead_or_set for all the registers we saved. */ 1363 for (k = 0; k < numregs; k++) 1364 { 1365 SET_HARD_REG_BIT (hard_regs_saved, regno + k); 1366 SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); 1367 n_regs_saved++; 1368 } 1369 1370 /* Tell our callers how many extra registers we saved/restored. */ 1371 return numregs - 1; 1372 } 1373 1374 /* A note_uses callback used by insert_one_insn. Add the hard-register 1375 equivalent of each REG to regset DATA. */ 1376 1377 static void 1378 add_used_regs (rtx *loc, void *data) 1379 { 1380 subrtx_iterator::array_type array; 1381 FOR_EACH_SUBRTX (iter, array, *loc, NONCONST) 1382 { 1383 const_rtx x = *iter; 1384 if (REG_P (x)) 1385 { 1386 unsigned int regno = REGNO (x); 1387 if (HARD_REGISTER_NUM_P (regno)) 1388 bitmap_set_range ((regset) data, regno, 1389 hard_regno_nregs[regno][GET_MODE (x)]); 1390 else 1391 gcc_checking_assert (reg_renumber[regno] < 0); 1392 } 1393 } 1394 } 1395 1396 /* Emit a new caller-save insn and set the code. */ 1397 static struct insn_chain * 1398 insert_one_insn (struct insn_chain *chain, int before_p, int code, rtx pat) 1399 { 1400 rtx_insn *insn = chain->insn; 1401 struct insn_chain *new_chain; 1402 1403 #ifdef HAVE_cc0 1404 /* If INSN references CC0, put our insns in front of the insn that sets 1405 CC0. This is always safe, since the only way we could be passed an 1406 insn that references CC0 is for a restore, and doing a restore earlier 1407 isn't a problem. We do, however, assume here that CALL_INSNs don't 1408 reference CC0. Guard against non-INSN's like CODE_LABEL. */ 1409 1410 if ((NONJUMP_INSN_P (insn) || JUMP_P (insn)) 1411 && before_p 1412 && reg_referenced_p (cc0_rtx, PATTERN (insn))) 1413 chain = chain->prev, insn = chain->insn; 1414 #endif 1415 1416 new_chain = new_insn_chain (); 1417 if (before_p) 1418 { 1419 rtx link; 1420 1421 new_chain->prev = chain->prev; 1422 if (new_chain->prev != 0) 1423 new_chain->prev->next = new_chain; 1424 else 1425 reload_insn_chain = new_chain; 1426 1427 chain->prev = new_chain; 1428 new_chain->next = chain; 1429 new_chain->insn = emit_insn_before (pat, insn); 1430 /* ??? It would be nice if we could exclude the already / still saved 1431 registers from the live sets. */ 1432 COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); 1433 note_uses (&PATTERN (chain->insn), add_used_regs, 1434 &new_chain->live_throughout); 1435 /* If CHAIN->INSN is a call, then the registers which contain 1436 the arguments to the function are live in the new insn. */ 1437 if (CALL_P (chain->insn)) 1438 for (link = CALL_INSN_FUNCTION_USAGE (chain->insn); 1439 link != NULL_RTX; 1440 link = XEXP (link, 1)) 1441 note_uses (&XEXP (link, 0), add_used_regs, 1442 &new_chain->live_throughout); 1443 1444 CLEAR_REG_SET (&new_chain->dead_or_set); 1445 if (chain->insn == BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block))) 1446 BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; 1447 } 1448 else 1449 { 1450 new_chain->next = chain->next; 1451 if (new_chain->next != 0) 1452 new_chain->next->prev = new_chain; 1453 chain->next = new_chain; 1454 new_chain->prev = chain; 1455 new_chain->insn = emit_insn_after (pat, insn); 1456 /* ??? It would be nice if we could exclude the already / still saved 1457 registers from the live sets, and observe REG_UNUSED notes. */ 1458 COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); 1459 /* Registers that are set in CHAIN->INSN live in the new insn. 1460 (Unless there is a REG_UNUSED note for them, but we don't 1461 look for them here.) */ 1462 note_stores (PATTERN (chain->insn), add_stored_regs, 1463 &new_chain->live_throughout); 1464 CLEAR_REG_SET (&new_chain->dead_or_set); 1465 if (chain->insn == BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block))) 1466 BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; 1467 } 1468 new_chain->block = chain->block; 1469 new_chain->is_caller_save_insn = 1; 1470 1471 INSN_CODE (new_chain->insn) = code; 1472 return new_chain; 1473 } 1474 #include "gt-caller-save.h" 1475