1 /* Save and restore call-clobbered registers which are live across a call. 2 Copyright (C) 1989-2013 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "tm.h" 24 #include "rtl.h" 25 #include "regs.h" 26 #include "insn-config.h" 27 #include "flags.h" 28 #include "hard-reg-set.h" 29 #include "recog.h" 30 #include "basic-block.h" 31 #include "df.h" 32 #include "reload.h" 33 #include "function.h" 34 #include "expr.h" 35 #include "diagnostic-core.h" 36 #include "tm_p.h" 37 #include "addresses.h" 38 #include "ggc.h" 39 #include "dumpfile.h" 40 41 #define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD) 42 43 #define regno_save_mode \ 44 (this_target_reload->x_regno_save_mode) 45 #define cached_reg_save_code \ 46 (this_target_reload->x_cached_reg_save_code) 47 #define cached_reg_restore_code \ 48 (this_target_reload->x_cached_reg_restore_code) 49 50 /* For each hard register, a place on the stack where it can be saved, 51 if needed. */ 52 53 static rtx 54 regno_save_mem[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1]; 55 56 /* The number of elements in the subsequent array. */ 57 static int save_slots_num; 58 59 /* Allocated slots so far. */ 60 static rtx save_slots[FIRST_PSEUDO_REGISTER]; 61 62 /* Set of hard regs currently residing in save area (during insn scan). */ 63 64 static HARD_REG_SET hard_regs_saved; 65 66 /* Number of registers currently in hard_regs_saved. */ 67 68 static int n_regs_saved; 69 70 /* Computed by mark_referenced_regs, all regs referenced in a given 71 insn. */ 72 static HARD_REG_SET referenced_regs; 73 74 75 typedef void refmarker_fn (rtx *loc, enum machine_mode mode, int hardregno, 76 void *mark_arg); 77 78 static int reg_save_code (int, enum machine_mode); 79 static int reg_restore_code (int, enum machine_mode); 80 81 struct saved_hard_reg; 82 static void initiate_saved_hard_regs (void); 83 static void new_saved_hard_reg (int, int); 84 static void finish_saved_hard_regs (void); 85 static int saved_hard_reg_compare_func (const void *, const void *); 86 87 static void mark_set_regs (rtx, const_rtx, void *); 88 static void mark_referenced_regs (rtx *, refmarker_fn *mark, void *mark_arg); 89 static refmarker_fn mark_reg_as_referenced; 90 static refmarker_fn replace_reg_with_saved_mem; 91 static int insert_save (struct insn_chain *, int, int, HARD_REG_SET *, 92 enum machine_mode *); 93 static int insert_restore (struct insn_chain *, int, int, int, 94 enum machine_mode *); 95 static struct insn_chain *insert_one_insn (struct insn_chain *, int, int, 96 rtx); 97 static void add_stored_regs (rtx, const_rtx, void *); 98 99 100 101 static GTY(()) rtx savepat; 102 static GTY(()) rtx restpat; 103 static GTY(()) rtx test_reg; 104 static GTY(()) rtx test_mem; 105 static GTY(()) rtx saveinsn; 106 static GTY(()) rtx restinsn; 107 108 /* Return the INSN_CODE used to save register REG in mode MODE. */ 109 static int 110 reg_save_code (int reg, enum machine_mode mode) 111 { 112 bool ok; 113 if (cached_reg_save_code[reg][mode]) 114 return cached_reg_save_code[reg][mode]; 115 if (!HARD_REGNO_MODE_OK (reg, mode)) 116 { 117 /* Depending on how HARD_REGNO_MODE_OK is defined, range propagation 118 might deduce here that reg >= FIRST_PSEUDO_REGISTER. So the assert 119 below silences a warning. */ 120 gcc_assert (reg < FIRST_PSEUDO_REGISTER); 121 cached_reg_save_code[reg][mode] = -1; 122 cached_reg_restore_code[reg][mode] = -1; 123 return -1; 124 } 125 126 /* Update the register number and modes of the register 127 and memory operand. */ 128 SET_REGNO_RAW (test_reg, reg); 129 PUT_MODE (test_reg, mode); 130 PUT_MODE (test_mem, mode); 131 132 /* Force re-recognition of the modified insns. */ 133 INSN_CODE (saveinsn) = -1; 134 INSN_CODE (restinsn) = -1; 135 136 cached_reg_save_code[reg][mode] = recog_memoized (saveinsn); 137 cached_reg_restore_code[reg][mode] = recog_memoized (restinsn); 138 139 /* Now extract both insns and see if we can meet their 140 constraints. */ 141 ok = (cached_reg_save_code[reg][mode] != -1 142 && cached_reg_restore_code[reg][mode] != -1); 143 if (ok) 144 { 145 extract_insn (saveinsn); 146 ok = constrain_operands (1); 147 extract_insn (restinsn); 148 ok &= constrain_operands (1); 149 } 150 151 if (! ok) 152 { 153 cached_reg_save_code[reg][mode] = -1; 154 cached_reg_restore_code[reg][mode] = -1; 155 } 156 gcc_assert (cached_reg_save_code[reg][mode]); 157 return cached_reg_save_code[reg][mode]; 158 } 159 160 /* Return the INSN_CODE used to restore register REG in mode MODE. */ 161 static int 162 reg_restore_code (int reg, enum machine_mode mode) 163 { 164 if (cached_reg_restore_code[reg][mode]) 165 return cached_reg_restore_code[reg][mode]; 166 /* Populate our cache. */ 167 reg_save_code (reg, mode); 168 return cached_reg_restore_code[reg][mode]; 169 } 170 171 /* Initialize for caller-save. 172 173 Look at all the hard registers that are used by a call and for which 174 reginfo.c has not already excluded from being used across a call. 175 176 Ensure that we can find a mode to save the register and that there is a 177 simple insn to save and restore the register. This latter check avoids 178 problems that would occur if we tried to save the MQ register of some 179 machines directly into memory. */ 180 181 void 182 init_caller_save (void) 183 { 184 rtx addr_reg; 185 int offset; 186 rtx address; 187 int i, j; 188 189 if (caller_save_initialized_p) 190 return; 191 192 caller_save_initialized_p = true; 193 194 CLEAR_HARD_REG_SET (no_caller_save_reg_set); 195 /* First find all the registers that we need to deal with and all 196 the modes that they can have. If we can't find a mode to use, 197 we can't have the register live over calls. */ 198 199 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 200 { 201 if (call_used_regs[i] 202 && !TEST_HARD_REG_BIT (call_fixed_reg_set, i)) 203 { 204 for (j = 1; j <= MOVE_MAX_WORDS; j++) 205 { 206 regno_save_mode[i][j] = HARD_REGNO_CALLER_SAVE_MODE (i, j, 207 VOIDmode); 208 if (regno_save_mode[i][j] == VOIDmode && j == 1) 209 { 210 SET_HARD_REG_BIT (call_fixed_reg_set, i); 211 } 212 } 213 } 214 else 215 regno_save_mode[i][1] = VOIDmode; 216 } 217 218 /* The following code tries to approximate the conditions under which 219 we can easily save and restore a register without scratch registers or 220 other complexities. It will usually work, except under conditions where 221 the validity of an insn operand is dependent on the address offset. 222 No such cases are currently known. 223 224 We first find a typical offset from some BASE_REG_CLASS register. 225 This address is chosen by finding the first register in the class 226 and by finding the smallest power of two that is a valid offset from 227 that register in every mode we will use to save registers. */ 228 229 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 230 if (TEST_HARD_REG_BIT 231 (reg_class_contents 232 [(int) base_reg_class (regno_save_mode[i][1], ADDR_SPACE_GENERIC, 233 PLUS, CONST_INT)], i)) 234 break; 235 236 gcc_assert (i < FIRST_PSEUDO_REGISTER); 237 238 addr_reg = gen_rtx_REG (Pmode, i); 239 240 for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1) 241 { 242 address = gen_rtx_PLUS (Pmode, addr_reg, GEN_INT (offset)); 243 244 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 245 if (regno_save_mode[i][1] != VOIDmode 246 && ! strict_memory_address_p (regno_save_mode[i][1], address)) 247 break; 248 249 if (i == FIRST_PSEUDO_REGISTER) 250 break; 251 } 252 253 /* If we didn't find a valid address, we must use register indirect. */ 254 if (offset == 0) 255 address = addr_reg; 256 257 /* Next we try to form an insn to save and restore the register. We 258 see if such an insn is recognized and meets its constraints. 259 260 To avoid lots of unnecessary RTL allocation, we construct all the RTL 261 once, then modify the memory and register operands in-place. */ 262 263 test_reg = gen_rtx_REG (VOIDmode, 0); 264 test_mem = gen_rtx_MEM (VOIDmode, address); 265 savepat = gen_rtx_SET (VOIDmode, test_mem, test_reg); 266 restpat = gen_rtx_SET (VOIDmode, test_reg, test_mem); 267 268 saveinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, 0, savepat, 0, -1, 0); 269 restinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, 0, restpat, 0, -1, 0); 270 271 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 272 for (j = 1; j <= MOVE_MAX_WORDS; j++) 273 if (reg_save_code (i,regno_save_mode[i][j]) == -1) 274 { 275 regno_save_mode[i][j] = VOIDmode; 276 if (j == 1) 277 { 278 SET_HARD_REG_BIT (call_fixed_reg_set, i); 279 if (call_used_regs[i]) 280 SET_HARD_REG_BIT (no_caller_save_reg_set, i); 281 } 282 } 283 } 284 285 286 287 /* Initialize save areas by showing that we haven't allocated any yet. */ 288 289 void 290 init_save_areas (void) 291 { 292 int i, j; 293 294 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 295 for (j = 1; j <= MOVE_MAX_WORDS; j++) 296 regno_save_mem[i][j] = 0; 297 save_slots_num = 0; 298 299 } 300 301 /* The structure represents a hard register which should be saved 302 through the call. It is used when the integrated register 303 allocator (IRA) is used and sharing save slots is on. */ 304 struct saved_hard_reg 305 { 306 /* Order number starting with 0. */ 307 int num; 308 /* The hard regno. */ 309 int hard_regno; 310 /* Execution frequency of all calls through which given hard 311 register should be saved. */ 312 int call_freq; 313 /* Stack slot reserved to save the hard register through calls. */ 314 rtx slot; 315 /* True if it is first hard register in the chain of hard registers 316 sharing the same stack slot. */ 317 int first_p; 318 /* Order number of the next hard register structure with the same 319 slot in the chain. -1 represents end of the chain. */ 320 int next; 321 }; 322 323 /* Map: hard register number to the corresponding structure. */ 324 static struct saved_hard_reg *hard_reg_map[FIRST_PSEUDO_REGISTER]; 325 326 /* The number of all structures representing hard registers should be 327 saved, in order words, the number of used elements in the following 328 array. */ 329 static int saved_regs_num; 330 331 /* Pointers to all the structures. Index is the order number of the 332 corresponding structure. */ 333 static struct saved_hard_reg *all_saved_regs[FIRST_PSEUDO_REGISTER]; 334 335 /* First called function for work with saved hard registers. */ 336 static void 337 initiate_saved_hard_regs (void) 338 { 339 int i; 340 341 saved_regs_num = 0; 342 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 343 hard_reg_map[i] = NULL; 344 } 345 346 /* Allocate and return new saved hard register with given REGNO and 347 CALL_FREQ. */ 348 static void 349 new_saved_hard_reg (int regno, int call_freq) 350 { 351 struct saved_hard_reg *saved_reg; 352 353 saved_reg 354 = (struct saved_hard_reg *) xmalloc (sizeof (struct saved_hard_reg)); 355 hard_reg_map[regno] = all_saved_regs[saved_regs_num] = saved_reg; 356 saved_reg->num = saved_regs_num++; 357 saved_reg->hard_regno = regno; 358 saved_reg->call_freq = call_freq; 359 saved_reg->first_p = FALSE; 360 saved_reg->next = -1; 361 } 362 363 /* Free memory allocated for the saved hard registers. */ 364 static void 365 finish_saved_hard_regs (void) 366 { 367 int i; 368 369 for (i = 0; i < saved_regs_num; i++) 370 free (all_saved_regs[i]); 371 } 372 373 /* The function is used to sort the saved hard register structures 374 according their frequency. */ 375 static int 376 saved_hard_reg_compare_func (const void *v1p, const void *v2p) 377 { 378 const struct saved_hard_reg *p1 = *(struct saved_hard_reg * const *) v1p; 379 const struct saved_hard_reg *p2 = *(struct saved_hard_reg * const *) v2p; 380 381 if (flag_omit_frame_pointer) 382 { 383 if (p1->call_freq - p2->call_freq != 0) 384 return p1->call_freq - p2->call_freq; 385 } 386 else if (p2->call_freq - p1->call_freq != 0) 387 return p2->call_freq - p1->call_freq; 388 389 return p1->num - p2->num; 390 } 391 392 /* Allocate save areas for any hard registers that might need saving. 393 We take a conservative approach here and look for call-clobbered hard 394 registers that are assigned to pseudos that cross calls. This may 395 overestimate slightly (especially if some of these registers are later 396 used as spill registers), but it should not be significant. 397 398 For IRA we use priority coloring to decrease stack slots needed for 399 saving hard registers through calls. We build conflicts for them 400 to do coloring. 401 402 Future work: 403 404 In the fallback case we should iterate backwards across all possible 405 modes for the save, choosing the largest available one instead of 406 falling back to the smallest mode immediately. (eg TF -> DF -> SF). 407 408 We do not try to use "move multiple" instructions that exist 409 on some machines (such as the 68k moveml). It could be a win to try 410 and use them when possible. The hard part is doing it in a way that is 411 machine independent since they might be saving non-consecutive 412 registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */ 413 414 void 415 setup_save_areas (void) 416 { 417 int i, j, k, freq; 418 HARD_REG_SET hard_regs_used; 419 struct saved_hard_reg *saved_reg; 420 rtx insn; 421 struct insn_chain *chain, *next; 422 unsigned int regno; 423 HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets; 424 reg_set_iterator rsi; 425 426 CLEAR_HARD_REG_SET (hard_regs_used); 427 428 /* Find every CALL_INSN and record which hard regs are live across the 429 call into HARD_REG_MAP and HARD_REGS_USED. */ 430 initiate_saved_hard_regs (); 431 /* Create hard reg saved regs. */ 432 for (chain = reload_insn_chain; chain != 0; chain = next) 433 { 434 rtx cheap; 435 436 insn = chain->insn; 437 next = chain->next; 438 if (!CALL_P (insn) 439 || find_reg_note (insn, REG_NORETURN, NULL)) 440 continue; 441 freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)); 442 REG_SET_TO_HARD_REG_SET (hard_regs_to_save, 443 &chain->live_throughout); 444 COPY_HARD_REG_SET (used_regs, call_used_reg_set); 445 446 /* Record all registers set in this call insn. These don't 447 need to be saved. N.B. the call insn might set a subreg 448 of a multi-hard-reg pseudo; then the pseudo is considered 449 live during the call, but the subreg that is set 450 isn't. */ 451 CLEAR_HARD_REG_SET (this_insn_sets); 452 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); 453 /* Sibcalls are considered to set the return value. */ 454 if (SIBLING_CALL_P (insn) && crtl->return_rtx) 455 mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); 456 457 AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); 458 AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); 459 AND_HARD_REG_SET (hard_regs_to_save, used_regs); 460 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 461 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) 462 { 463 if (hard_reg_map[regno] != NULL) 464 hard_reg_map[regno]->call_freq += freq; 465 else 466 new_saved_hard_reg (regno, freq); 467 SET_HARD_REG_BIT (hard_regs_used, regno); 468 } 469 cheap = find_reg_note (insn, REG_RETURNED, NULL); 470 if (cheap) 471 cheap = XEXP (cheap, 0); 472 /* Look through all live pseudos, mark their hard registers. */ 473 EXECUTE_IF_SET_IN_REG_SET 474 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) 475 { 476 int r = reg_renumber[regno]; 477 int bound; 478 479 if (r < 0 || regno_reg_rtx[regno] == cheap) 480 continue; 481 482 bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; 483 for (; r < bound; r++) 484 if (TEST_HARD_REG_BIT (used_regs, r)) 485 { 486 if (hard_reg_map[r] != NULL) 487 hard_reg_map[r]->call_freq += freq; 488 else 489 new_saved_hard_reg (r, freq); 490 SET_HARD_REG_BIT (hard_regs_to_save, r); 491 SET_HARD_REG_BIT (hard_regs_used, r); 492 } 493 } 494 } 495 496 /* If requested, figure out which hard regs can share save slots. */ 497 if (optimize && flag_ira_share_save_slots) 498 { 499 rtx slot; 500 char *saved_reg_conflicts; 501 int next_k; 502 struct saved_hard_reg *saved_reg2, *saved_reg3; 503 int call_saved_regs_num; 504 struct saved_hard_reg *call_saved_regs[FIRST_PSEUDO_REGISTER]; 505 int best_slot_num; 506 int prev_save_slots_num; 507 rtx prev_save_slots[FIRST_PSEUDO_REGISTER]; 508 509 /* Find saved hard register conflicts. */ 510 saved_reg_conflicts = (char *) xmalloc (saved_regs_num * saved_regs_num); 511 memset (saved_reg_conflicts, 0, saved_regs_num * saved_regs_num); 512 for (chain = reload_insn_chain; chain != 0; chain = next) 513 { 514 rtx cheap; 515 call_saved_regs_num = 0; 516 insn = chain->insn; 517 next = chain->next; 518 if (!CALL_P (insn) 519 || find_reg_note (insn, REG_NORETURN, NULL)) 520 continue; 521 522 cheap = find_reg_note (insn, REG_RETURNED, NULL); 523 if (cheap) 524 cheap = XEXP (cheap, 0); 525 526 REG_SET_TO_HARD_REG_SET (hard_regs_to_save, 527 &chain->live_throughout); 528 COPY_HARD_REG_SET (used_regs, call_used_reg_set); 529 530 /* Record all registers set in this call insn. These don't 531 need to be saved. N.B. the call insn might set a subreg 532 of a multi-hard-reg pseudo; then the pseudo is considered 533 live during the call, but the subreg that is set 534 isn't. */ 535 CLEAR_HARD_REG_SET (this_insn_sets); 536 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); 537 /* Sibcalls are considered to set the return value, 538 compare df-scan.c:df_get_call_refs. */ 539 if (SIBLING_CALL_P (insn) && crtl->return_rtx) 540 mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); 541 542 AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); 543 AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); 544 AND_HARD_REG_SET (hard_regs_to_save, used_regs); 545 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 546 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) 547 { 548 gcc_assert (hard_reg_map[regno] != NULL); 549 call_saved_regs[call_saved_regs_num++] = hard_reg_map[regno]; 550 } 551 /* Look through all live pseudos, mark their hard registers. */ 552 EXECUTE_IF_SET_IN_REG_SET 553 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) 554 { 555 int r = reg_renumber[regno]; 556 int bound; 557 558 if (r < 0 || regno_reg_rtx[regno] == cheap) 559 continue; 560 561 bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; 562 for (; r < bound; r++) 563 if (TEST_HARD_REG_BIT (used_regs, r)) 564 call_saved_regs[call_saved_regs_num++] = hard_reg_map[r]; 565 } 566 for (i = 0; i < call_saved_regs_num; i++) 567 { 568 saved_reg = call_saved_regs[i]; 569 for (j = 0; j < call_saved_regs_num; j++) 570 if (i != j) 571 { 572 saved_reg2 = call_saved_regs[j]; 573 saved_reg_conflicts[saved_reg->num * saved_regs_num 574 + saved_reg2->num] 575 = saved_reg_conflicts[saved_reg2->num * saved_regs_num 576 + saved_reg->num] 577 = TRUE; 578 } 579 } 580 } 581 /* Sort saved hard regs. */ 582 qsort (all_saved_regs, saved_regs_num, sizeof (struct saved_hard_reg *), 583 saved_hard_reg_compare_func); 584 /* Initiate slots available from the previous reload 585 iteration. */ 586 prev_save_slots_num = save_slots_num; 587 memcpy (prev_save_slots, save_slots, save_slots_num * sizeof (rtx)); 588 save_slots_num = 0; 589 /* Allocate stack slots for the saved hard registers. */ 590 for (i = 0; i < saved_regs_num; i++) 591 { 592 saved_reg = all_saved_regs[i]; 593 regno = saved_reg->hard_regno; 594 for (j = 0; j < i; j++) 595 { 596 saved_reg2 = all_saved_regs[j]; 597 if (! saved_reg2->first_p) 598 continue; 599 slot = saved_reg2->slot; 600 for (k = j; k >= 0; k = next_k) 601 { 602 saved_reg3 = all_saved_regs[k]; 603 next_k = saved_reg3->next; 604 if (saved_reg_conflicts[saved_reg->num * saved_regs_num 605 + saved_reg3->num]) 606 break; 607 } 608 if (k < 0 609 && (GET_MODE_SIZE (regno_save_mode[regno][1]) 610 <= GET_MODE_SIZE (regno_save_mode 611 [saved_reg2->hard_regno][1]))) 612 { 613 saved_reg->slot 614 = adjust_address_nv 615 (slot, regno_save_mode[saved_reg->hard_regno][1], 0); 616 regno_save_mem[regno][1] = saved_reg->slot; 617 saved_reg->next = saved_reg2->next; 618 saved_reg2->next = i; 619 if (dump_file != NULL) 620 fprintf (dump_file, "%d uses slot of %d\n", 621 regno, saved_reg2->hard_regno); 622 break; 623 } 624 } 625 if (j == i) 626 { 627 saved_reg->first_p = TRUE; 628 for (best_slot_num = -1, j = 0; j < prev_save_slots_num; j++) 629 { 630 slot = prev_save_slots[j]; 631 if (slot == NULL_RTX) 632 continue; 633 if (GET_MODE_SIZE (regno_save_mode[regno][1]) 634 <= GET_MODE_SIZE (GET_MODE (slot)) 635 && best_slot_num < 0) 636 best_slot_num = j; 637 if (GET_MODE (slot) == regno_save_mode[regno][1]) 638 break; 639 } 640 if (best_slot_num >= 0) 641 { 642 saved_reg->slot = prev_save_slots[best_slot_num]; 643 saved_reg->slot 644 = adjust_address_nv 645 (saved_reg->slot, 646 regno_save_mode[saved_reg->hard_regno][1], 0); 647 if (dump_file != NULL) 648 fprintf (dump_file, 649 "%d uses a slot from prev iteration\n", regno); 650 prev_save_slots[best_slot_num] = NULL_RTX; 651 if (best_slot_num + 1 == prev_save_slots_num) 652 prev_save_slots_num--; 653 } 654 else 655 { 656 saved_reg->slot 657 = assign_stack_local_1 658 (regno_save_mode[regno][1], 659 GET_MODE_SIZE (regno_save_mode[regno][1]), 0, 660 ASLK_REDUCE_ALIGN); 661 if (dump_file != NULL) 662 fprintf (dump_file, "%d uses a new slot\n", regno); 663 } 664 regno_save_mem[regno][1] = saved_reg->slot; 665 save_slots[save_slots_num++] = saved_reg->slot; 666 } 667 } 668 free (saved_reg_conflicts); 669 finish_saved_hard_regs (); 670 } 671 else 672 { 673 /* We are not sharing slots. 674 675 Run through all the call-used hard-registers and allocate 676 space for each in the caller-save area. Try to allocate space 677 in a manner which allows multi-register saves/restores to be done. */ 678 679 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 680 for (j = MOVE_MAX_WORDS; j > 0; j--) 681 { 682 int do_save = 1; 683 684 /* If no mode exists for this size, try another. Also break out 685 if we have already saved this hard register. */ 686 if (regno_save_mode[i][j] == VOIDmode || regno_save_mem[i][1] != 0) 687 continue; 688 689 /* See if any register in this group has been saved. */ 690 for (k = 0; k < j; k++) 691 if (regno_save_mem[i + k][1]) 692 { 693 do_save = 0; 694 break; 695 } 696 if (! do_save) 697 continue; 698 699 for (k = 0; k < j; k++) 700 if (! TEST_HARD_REG_BIT (hard_regs_used, i + k)) 701 { 702 do_save = 0; 703 break; 704 } 705 if (! do_save) 706 continue; 707 708 /* We have found an acceptable mode to store in. Since 709 hard register is always saved in the widest mode 710 available, the mode may be wider than necessary, it is 711 OK to reduce the alignment of spill space. We will 712 verify that it is equal to or greater than required 713 when we restore and save the hard register in 714 insert_restore and insert_save. */ 715 regno_save_mem[i][j] 716 = assign_stack_local_1 (regno_save_mode[i][j], 717 GET_MODE_SIZE (regno_save_mode[i][j]), 718 0, ASLK_REDUCE_ALIGN); 719 720 /* Setup single word save area just in case... */ 721 for (k = 0; k < j; k++) 722 /* This should not depend on WORDS_BIG_ENDIAN. 723 The order of words in regs is the same as in memory. */ 724 regno_save_mem[i + k][1] 725 = adjust_address_nv (regno_save_mem[i][j], 726 regno_save_mode[i + k][1], 727 k * UNITS_PER_WORD); 728 } 729 } 730 731 /* Now loop again and set the alias set of any save areas we made to 732 the alias set used to represent frame objects. */ 733 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 734 for (j = MOVE_MAX_WORDS; j > 0; j--) 735 if (regno_save_mem[i][j] != 0) 736 set_mem_alias_set (regno_save_mem[i][j], get_frame_alias_set ()); 737 } 738 739 740 741 /* Find the places where hard regs are live across calls and save them. */ 742 743 void 744 save_call_clobbered_regs (void) 745 { 746 struct insn_chain *chain, *next, *last = NULL; 747 enum machine_mode save_mode [FIRST_PSEUDO_REGISTER]; 748 749 /* Computed in mark_set_regs, holds all registers set by the current 750 instruction. */ 751 HARD_REG_SET this_insn_sets; 752 753 CLEAR_HARD_REG_SET (hard_regs_saved); 754 n_regs_saved = 0; 755 756 for (chain = reload_insn_chain; chain != 0; chain = next) 757 { 758 rtx insn = chain->insn; 759 enum rtx_code code = GET_CODE (insn); 760 761 next = chain->next; 762 763 gcc_assert (!chain->is_caller_save_insn); 764 765 if (NONDEBUG_INSN_P (insn)) 766 { 767 /* If some registers have been saved, see if INSN references 768 any of them. We must restore them before the insn if so. */ 769 770 if (n_regs_saved) 771 { 772 int regno; 773 HARD_REG_SET this_insn_sets; 774 775 if (code == JUMP_INSN) 776 /* Restore all registers if this is a JUMP_INSN. */ 777 COPY_HARD_REG_SET (referenced_regs, hard_regs_saved); 778 else 779 { 780 CLEAR_HARD_REG_SET (referenced_regs); 781 mark_referenced_regs (&PATTERN (insn), 782 mark_reg_as_referenced, NULL); 783 AND_HARD_REG_SET (referenced_regs, hard_regs_saved); 784 } 785 786 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 787 if (TEST_HARD_REG_BIT (referenced_regs, regno)) 788 regno += insert_restore (chain, 1, regno, MOVE_MAX_WORDS, 789 save_mode); 790 /* If a saved register is set after the call, this means we no 791 longer should restore it. This can happen when parts of a 792 multi-word pseudo do not conflict with other pseudos, so 793 IRA may allocate the same hard register for both. One may 794 be live across the call, while the other is set 795 afterwards. */ 796 CLEAR_HARD_REG_SET (this_insn_sets); 797 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); 798 AND_COMPL_HARD_REG_SET (hard_regs_saved, this_insn_sets); 799 } 800 801 if (code == CALL_INSN 802 && ! SIBLING_CALL_P (insn) 803 && ! find_reg_note (insn, REG_NORETURN, NULL)) 804 { 805 unsigned regno; 806 HARD_REG_SET hard_regs_to_save; 807 reg_set_iterator rsi; 808 rtx cheap; 809 810 cheap = find_reg_note (insn, REG_RETURNED, NULL); 811 if (cheap) 812 cheap = XEXP (cheap, 0); 813 814 /* Use the register life information in CHAIN to compute which 815 regs are live during the call. */ 816 REG_SET_TO_HARD_REG_SET (hard_regs_to_save, 817 &chain->live_throughout); 818 /* Save hard registers always in the widest mode available. */ 819 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 820 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) 821 save_mode [regno] = regno_save_mode [regno][1]; 822 else 823 save_mode [regno] = VOIDmode; 824 825 /* Look through all live pseudos, mark their hard registers 826 and choose proper mode for saving. */ 827 EXECUTE_IF_SET_IN_REG_SET 828 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) 829 { 830 int r = reg_renumber[regno]; 831 int nregs; 832 enum machine_mode mode; 833 834 if (r < 0 || regno_reg_rtx[regno] == cheap) 835 continue; 836 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; 837 mode = HARD_REGNO_CALLER_SAVE_MODE 838 (r, nregs, PSEUDO_REGNO_MODE (regno)); 839 if (GET_MODE_BITSIZE (mode) 840 > GET_MODE_BITSIZE (save_mode[r])) 841 save_mode[r] = mode; 842 while (nregs-- > 0) 843 SET_HARD_REG_BIT (hard_regs_to_save, r + nregs); 844 } 845 846 /* Record all registers set in this call insn. These don't need 847 to be saved. N.B. the call insn might set a subreg of a 848 multi-hard-reg pseudo; then the pseudo is considered live 849 during the call, but the subreg that is set isn't. */ 850 CLEAR_HARD_REG_SET (this_insn_sets); 851 note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); 852 853 /* Compute which hard regs must be saved before this call. */ 854 AND_COMPL_HARD_REG_SET (hard_regs_to_save, call_fixed_reg_set); 855 AND_COMPL_HARD_REG_SET (hard_regs_to_save, this_insn_sets); 856 AND_COMPL_HARD_REG_SET (hard_regs_to_save, hard_regs_saved); 857 AND_HARD_REG_SET (hard_regs_to_save, call_used_reg_set); 858 859 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 860 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) 861 regno += insert_save (chain, 1, regno, &hard_regs_to_save, save_mode); 862 863 /* Must recompute n_regs_saved. */ 864 n_regs_saved = 0; 865 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 866 if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) 867 n_regs_saved++; 868 869 if (cheap 870 && HARD_REGISTER_P (cheap) 871 && TEST_HARD_REG_BIT (call_used_reg_set, REGNO (cheap))) 872 { 873 rtx dest, newpat; 874 rtx pat = PATTERN (insn); 875 if (GET_CODE (pat) == PARALLEL) 876 pat = XVECEXP (pat, 0, 0); 877 dest = SET_DEST (pat); 878 newpat = gen_rtx_SET (VOIDmode, cheap, copy_rtx (dest)); 879 chain = insert_one_insn (chain, 0, -1, newpat); 880 } 881 } 882 last = chain; 883 } 884 else if (DEBUG_INSN_P (insn) && n_regs_saved) 885 mark_referenced_regs (&PATTERN (insn), 886 replace_reg_with_saved_mem, 887 save_mode); 888 889 if (chain->next == 0 || chain->next->block != chain->block) 890 { 891 int regno; 892 /* At the end of the basic block, we must restore any registers that 893 remain saved. If the last insn in the block is a JUMP_INSN, put 894 the restore before the insn, otherwise, put it after the insn. */ 895 896 if (n_regs_saved 897 && DEBUG_INSN_P (insn) 898 && last 899 && last->block == chain->block) 900 { 901 rtx ins, prev; 902 basic_block bb = BLOCK_FOR_INSN (insn); 903 904 /* When adding hard reg restores after a DEBUG_INSN, move 905 all notes between last real insn and this DEBUG_INSN after 906 the DEBUG_INSN, otherwise we could get code 907 -g/-g0 differences. */ 908 for (ins = PREV_INSN (insn); ins != last->insn; ins = prev) 909 { 910 prev = PREV_INSN (ins); 911 if (NOTE_P (ins)) 912 { 913 NEXT_INSN (prev) = NEXT_INSN (ins); 914 PREV_INSN (NEXT_INSN (ins)) = prev; 915 PREV_INSN (ins) = insn; 916 NEXT_INSN (ins) = NEXT_INSN (insn); 917 NEXT_INSN (insn) = ins; 918 if (NEXT_INSN (ins)) 919 PREV_INSN (NEXT_INSN (ins)) = ins; 920 if (BB_END (bb) == insn) 921 BB_END (bb) = ins; 922 } 923 else 924 gcc_assert (DEBUG_INSN_P (ins)); 925 } 926 } 927 last = NULL; 928 929 if (n_regs_saved) 930 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 931 if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) 932 regno += insert_restore (chain, JUMP_P (insn), 933 regno, MOVE_MAX_WORDS, save_mode); 934 } 935 } 936 } 937 938 /* Here from note_stores, or directly from save_call_clobbered_regs, when 939 an insn stores a value in a register. 940 Set the proper bit or bits in this_insn_sets. All pseudos that have 941 been assigned hard regs have had their register number changed already, 942 so we can ignore pseudos. */ 943 static void 944 mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data) 945 { 946 int regno, endregno, i; 947 HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data; 948 949 if (GET_CODE (reg) == SUBREG) 950 { 951 rtx inner = SUBREG_REG (reg); 952 if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER) 953 return; 954 regno = subreg_regno (reg); 955 endregno = regno + subreg_nregs (reg); 956 } 957 else if (REG_P (reg) 958 && REGNO (reg) < FIRST_PSEUDO_REGISTER) 959 { 960 regno = REGNO (reg); 961 endregno = END_HARD_REGNO (reg); 962 } 963 else 964 return; 965 966 for (i = regno; i < endregno; i++) 967 SET_HARD_REG_BIT (*this_insn_sets, i); 968 } 969 970 /* Here from note_stores when an insn stores a value in a register. 971 Set the proper bit or bits in the passed regset. All pseudos that have 972 been assigned hard regs have had their register number changed already, 973 so we can ignore pseudos. */ 974 static void 975 add_stored_regs (rtx reg, const_rtx setter, void *data) 976 { 977 int regno, endregno, i; 978 enum machine_mode mode = GET_MODE (reg); 979 int offset = 0; 980 981 if (GET_CODE (setter) == CLOBBER) 982 return; 983 984 if (GET_CODE (reg) == SUBREG 985 && REG_P (SUBREG_REG (reg)) 986 && REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER) 987 { 988 offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)), 989 GET_MODE (SUBREG_REG (reg)), 990 SUBREG_BYTE (reg), 991 GET_MODE (reg)); 992 regno = REGNO (SUBREG_REG (reg)) + offset; 993 endregno = regno + subreg_nregs (reg); 994 } 995 else 996 { 997 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) 998 return; 999 1000 regno = REGNO (reg) + offset; 1001 endregno = end_hard_regno (mode, regno); 1002 } 1003 1004 for (i = regno; i < endregno; i++) 1005 SET_REGNO_REG_SET ((regset) data, i); 1006 } 1007 1008 /* Walk X and record all referenced registers in REFERENCED_REGS. */ 1009 static void 1010 mark_referenced_regs (rtx *loc, refmarker_fn *mark, void *arg) 1011 { 1012 enum rtx_code code = GET_CODE (*loc); 1013 const char *fmt; 1014 int i, j; 1015 1016 if (code == SET) 1017 mark_referenced_regs (&SET_SRC (*loc), mark, arg); 1018 if (code == SET || code == CLOBBER) 1019 { 1020 loc = &SET_DEST (*loc); 1021 code = GET_CODE (*loc); 1022 if ((code == REG && REGNO (*loc) < FIRST_PSEUDO_REGISTER) 1023 || code == PC || code == CC0 1024 || (code == SUBREG && REG_P (SUBREG_REG (*loc)) 1025 && REGNO (SUBREG_REG (*loc)) < FIRST_PSEUDO_REGISTER 1026 /* If we're setting only part of a multi-word register, 1027 we shall mark it as referenced, because the words 1028 that are not being set should be restored. */ 1029 && ((GET_MODE_SIZE (GET_MODE (*loc)) 1030 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc)))) 1031 || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc))) 1032 <= UNITS_PER_WORD)))) 1033 return; 1034 } 1035 if (code == MEM || code == SUBREG) 1036 { 1037 loc = &XEXP (*loc, 0); 1038 code = GET_CODE (*loc); 1039 } 1040 1041 if (code == REG) 1042 { 1043 int regno = REGNO (*loc); 1044 int hardregno = (regno < FIRST_PSEUDO_REGISTER ? regno 1045 : reg_renumber[regno]); 1046 1047 if (hardregno >= 0) 1048 mark (loc, GET_MODE (*loc), hardregno, arg); 1049 else if (arg) 1050 /* ??? Will we ever end up with an equiv expression in a debug 1051 insn, that would have required restoring a reg, or will 1052 reload take care of it for us? */ 1053 return; 1054 /* If this is a pseudo that did not get a hard register, scan its 1055 memory location, since it might involve the use of another 1056 register, which might be saved. */ 1057 else if (reg_equiv_mem (regno) != 0) 1058 mark_referenced_regs (&XEXP (reg_equiv_mem (regno), 0), mark, arg); 1059 else if (reg_equiv_address (regno) != 0) 1060 mark_referenced_regs (®_equiv_address (regno), mark, arg); 1061 return; 1062 } 1063 1064 fmt = GET_RTX_FORMAT (code); 1065 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1066 { 1067 if (fmt[i] == 'e') 1068 mark_referenced_regs (&XEXP (*loc, i), mark, arg); 1069 else if (fmt[i] == 'E') 1070 for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) 1071 mark_referenced_regs (&XVECEXP (*loc, i, j), mark, arg); 1072 } 1073 } 1074 1075 /* Parameter function for mark_referenced_regs() that adds registers 1076 present in the insn and in equivalent mems and addresses to 1077 referenced_regs. */ 1078 1079 static void 1080 mark_reg_as_referenced (rtx *loc ATTRIBUTE_UNUSED, 1081 enum machine_mode mode, 1082 int hardregno, 1083 void *arg ATTRIBUTE_UNUSED) 1084 { 1085 add_to_hard_reg_set (&referenced_regs, mode, hardregno); 1086 } 1087 1088 /* Parameter function for mark_referenced_regs() that replaces 1089 registers referenced in a debug_insn that would have been restored, 1090 should it be a non-debug_insn, with their save locations. */ 1091 1092 static void 1093 replace_reg_with_saved_mem (rtx *loc, 1094 enum machine_mode mode, 1095 int regno, 1096 void *arg) 1097 { 1098 unsigned int i, nregs = hard_regno_nregs [regno][mode]; 1099 rtx mem; 1100 enum machine_mode *save_mode = (enum machine_mode *)arg; 1101 1102 for (i = 0; i < nregs; i++) 1103 if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) 1104 break; 1105 1106 /* If none of the registers in the range would need restoring, we're 1107 all set. */ 1108 if (i == nregs) 1109 return; 1110 1111 while (++i < nregs) 1112 if (!TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) 1113 break; 1114 1115 if (i == nregs 1116 && regno_save_mem[regno][nregs]) 1117 { 1118 mem = copy_rtx (regno_save_mem[regno][nregs]); 1119 1120 if (nregs == (unsigned int) hard_regno_nregs[regno][save_mode[regno]]) 1121 mem = adjust_address_nv (mem, save_mode[regno], 0); 1122 1123 if (GET_MODE (mem) != mode) 1124 { 1125 /* This is gen_lowpart_if_possible(), but without validating 1126 the newly-formed address. */ 1127 int offset = 0; 1128 1129 if (WORDS_BIG_ENDIAN) 1130 offset = (MAX (GET_MODE_SIZE (GET_MODE (mem)), UNITS_PER_WORD) 1131 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); 1132 if (BYTES_BIG_ENDIAN) 1133 /* Adjust the address so that the address-after-the-data is 1134 unchanged. */ 1135 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) 1136 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (mem)))); 1137 1138 mem = adjust_address_nv (mem, mode, offset); 1139 } 1140 } 1141 else 1142 { 1143 mem = gen_rtx_CONCATN (mode, rtvec_alloc (nregs)); 1144 for (i = 0; i < nregs; i++) 1145 if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) 1146 { 1147 gcc_assert (regno_save_mem[regno + i][1]); 1148 XVECEXP (mem, 0, i) = copy_rtx (regno_save_mem[regno + i][1]); 1149 } 1150 else 1151 { 1152 gcc_assert (save_mode[regno] != VOIDmode); 1153 XVECEXP (mem, 0, i) = gen_rtx_REG (save_mode [regno], 1154 regno + i); 1155 } 1156 } 1157 1158 gcc_assert (GET_MODE (mem) == mode); 1159 *loc = mem; 1160 } 1161 1162 1163 /* Insert a sequence of insns to restore. Place these insns in front of 1164 CHAIN if BEFORE_P is nonzero, behind the insn otherwise. MAXRESTORE is 1165 the maximum number of registers which should be restored during this call. 1166 It should never be less than 1 since we only work with entire registers. 1167 1168 Note that we have verified in init_caller_save that we can do this 1169 with a simple SET, so use it. Set INSN_CODE to what we save there 1170 since the address might not be valid so the insn might not be recognized. 1171 These insns will be reloaded and have register elimination done by 1172 find_reload, so we need not worry about that here. 1173 1174 Return the extra number of registers saved. */ 1175 1176 static int 1177 insert_restore (struct insn_chain *chain, int before_p, int regno, 1178 int maxrestore, enum machine_mode *save_mode) 1179 { 1180 int i, k; 1181 rtx pat = NULL_RTX; 1182 int code; 1183 unsigned int numregs = 0; 1184 struct insn_chain *new_chain; 1185 rtx mem; 1186 1187 /* A common failure mode if register status is not correct in the 1188 RTL is for this routine to be called with a REGNO we didn't 1189 expect to save. That will cause us to write an insn with a (nil) 1190 SET_DEST or SET_SRC. Instead of doing so and causing a crash 1191 later, check for this common case here instead. This will remove 1192 one step in debugging such problems. */ 1193 gcc_assert (regno_save_mem[regno][1]); 1194 1195 /* Get the pattern to emit and update our status. 1196 1197 See if we can restore `maxrestore' registers at once. Work 1198 backwards to the single register case. */ 1199 for (i = maxrestore; i > 0; i--) 1200 { 1201 int j; 1202 int ok = 1; 1203 1204 if (regno_save_mem[regno][i] == 0) 1205 continue; 1206 1207 for (j = 0; j < i; j++) 1208 if (! TEST_HARD_REG_BIT (hard_regs_saved, regno + j)) 1209 { 1210 ok = 0; 1211 break; 1212 } 1213 /* Must do this one restore at a time. */ 1214 if (! ok) 1215 continue; 1216 1217 numregs = i; 1218 break; 1219 } 1220 1221 mem = regno_save_mem [regno][numregs]; 1222 if (save_mode [regno] != VOIDmode 1223 && save_mode [regno] != GET_MODE (mem) 1224 && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] 1225 /* Check that insn to restore REGNO in save_mode[regno] is 1226 correct. */ 1227 && reg_save_code (regno, save_mode[regno]) >= 0) 1228 mem = adjust_address_nv (mem, save_mode[regno], 0); 1229 else 1230 mem = copy_rtx (mem); 1231 1232 /* Verify that the alignment of spill space is equal to or greater 1233 than required. */ 1234 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, 1235 GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); 1236 1237 pat = gen_rtx_SET (VOIDmode, 1238 gen_rtx_REG (GET_MODE (mem), 1239 regno), mem); 1240 code = reg_restore_code (regno, GET_MODE (mem)); 1241 new_chain = insert_one_insn (chain, before_p, code, pat); 1242 1243 /* Clear status for all registers we restored. */ 1244 for (k = 0; k < i; k++) 1245 { 1246 CLEAR_HARD_REG_BIT (hard_regs_saved, regno + k); 1247 SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); 1248 n_regs_saved--; 1249 } 1250 1251 /* Tell our callers how many extra registers we saved/restored. */ 1252 return numregs - 1; 1253 } 1254 1255 /* Like insert_restore above, but save registers instead. */ 1256 1257 static int 1258 insert_save (struct insn_chain *chain, int before_p, int regno, 1259 HARD_REG_SET (*to_save), enum machine_mode *save_mode) 1260 { 1261 int i; 1262 unsigned int k; 1263 rtx pat = NULL_RTX; 1264 int code; 1265 unsigned int numregs = 0; 1266 struct insn_chain *new_chain; 1267 rtx mem; 1268 1269 /* A common failure mode if register status is not correct in the 1270 RTL is for this routine to be called with a REGNO we didn't 1271 expect to save. That will cause us to write an insn with a (nil) 1272 SET_DEST or SET_SRC. Instead of doing so and causing a crash 1273 later, check for this common case here. This will remove one 1274 step in debugging such problems. */ 1275 gcc_assert (regno_save_mem[regno][1]); 1276 1277 /* Get the pattern to emit and update our status. 1278 1279 See if we can save several registers with a single instruction. 1280 Work backwards to the single register case. */ 1281 for (i = MOVE_MAX_WORDS; i > 0; i--) 1282 { 1283 int j; 1284 int ok = 1; 1285 if (regno_save_mem[regno][i] == 0) 1286 continue; 1287 1288 for (j = 0; j < i; j++) 1289 if (! TEST_HARD_REG_BIT (*to_save, regno + j)) 1290 { 1291 ok = 0; 1292 break; 1293 } 1294 /* Must do this one save at a time. */ 1295 if (! ok) 1296 continue; 1297 1298 numregs = i; 1299 break; 1300 } 1301 1302 mem = regno_save_mem [regno][numregs]; 1303 if (save_mode [regno] != VOIDmode 1304 && save_mode [regno] != GET_MODE (mem) 1305 && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] 1306 /* Check that insn to save REGNO in save_mode[regno] is 1307 correct. */ 1308 && reg_save_code (regno, save_mode[regno]) >= 0) 1309 mem = adjust_address_nv (mem, save_mode[regno], 0); 1310 else 1311 mem = copy_rtx (mem); 1312 1313 /* Verify that the alignment of spill space is equal to or greater 1314 than required. */ 1315 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, 1316 GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); 1317 1318 pat = gen_rtx_SET (VOIDmode, mem, 1319 gen_rtx_REG (GET_MODE (mem), 1320 regno)); 1321 code = reg_save_code (regno, GET_MODE (mem)); 1322 new_chain = insert_one_insn (chain, before_p, code, pat); 1323 1324 /* Set hard_regs_saved and dead_or_set for all the registers we saved. */ 1325 for (k = 0; k < numregs; k++) 1326 { 1327 SET_HARD_REG_BIT (hard_regs_saved, regno + k); 1328 SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); 1329 n_regs_saved++; 1330 } 1331 1332 /* Tell our callers how many extra registers we saved/restored. */ 1333 return numregs - 1; 1334 } 1335 1336 /* A for_each_rtx callback used by add_used_regs. Add the hard-register 1337 equivalent of each REG to regset DATA. */ 1338 1339 static int 1340 add_used_regs_1 (rtx *loc, void *data) 1341 { 1342 unsigned int regno; 1343 regset live; 1344 rtx x; 1345 1346 x = *loc; 1347 live = (regset) data; 1348 if (REG_P (x)) 1349 { 1350 regno = REGNO (x); 1351 if (HARD_REGISTER_NUM_P (regno)) 1352 bitmap_set_range (live, regno, hard_regno_nregs[regno][GET_MODE (x)]); 1353 else 1354 regno = reg_renumber[regno]; 1355 } 1356 return 0; 1357 } 1358 1359 /* A note_uses callback used by insert_one_insn. Add the hard-register 1360 equivalent of each REG to regset DATA. */ 1361 1362 static void 1363 add_used_regs (rtx *loc, void *data) 1364 { 1365 for_each_rtx (loc, add_used_regs_1, data); 1366 } 1367 1368 /* Emit a new caller-save insn and set the code. */ 1369 static struct insn_chain * 1370 insert_one_insn (struct insn_chain *chain, int before_p, int code, rtx pat) 1371 { 1372 rtx insn = chain->insn; 1373 struct insn_chain *new_chain; 1374 1375 #ifdef HAVE_cc0 1376 /* If INSN references CC0, put our insns in front of the insn that sets 1377 CC0. This is always safe, since the only way we could be passed an 1378 insn that references CC0 is for a restore, and doing a restore earlier 1379 isn't a problem. We do, however, assume here that CALL_INSNs don't 1380 reference CC0. Guard against non-INSN's like CODE_LABEL. */ 1381 1382 if ((NONJUMP_INSN_P (insn) || JUMP_P (insn)) 1383 && before_p 1384 && reg_referenced_p (cc0_rtx, PATTERN (insn))) 1385 chain = chain->prev, insn = chain->insn; 1386 #endif 1387 1388 new_chain = new_insn_chain (); 1389 if (before_p) 1390 { 1391 rtx link; 1392 1393 new_chain->prev = chain->prev; 1394 if (new_chain->prev != 0) 1395 new_chain->prev->next = new_chain; 1396 else 1397 reload_insn_chain = new_chain; 1398 1399 chain->prev = new_chain; 1400 new_chain->next = chain; 1401 new_chain->insn = emit_insn_before (pat, insn); 1402 /* ??? It would be nice if we could exclude the already / still saved 1403 registers from the live sets. */ 1404 COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); 1405 note_uses (&PATTERN (chain->insn), add_used_regs, 1406 &new_chain->live_throughout); 1407 /* If CHAIN->INSN is a call, then the registers which contain 1408 the arguments to the function are live in the new insn. */ 1409 if (CALL_P (chain->insn)) 1410 for (link = CALL_INSN_FUNCTION_USAGE (chain->insn); 1411 link != NULL_RTX; 1412 link = XEXP (link, 1)) 1413 note_uses (&XEXP (link, 0), add_used_regs, 1414 &new_chain->live_throughout); 1415 1416 CLEAR_REG_SET (&new_chain->dead_or_set); 1417 if (chain->insn == BB_HEAD (BASIC_BLOCK (chain->block))) 1418 BB_HEAD (BASIC_BLOCK (chain->block)) = new_chain->insn; 1419 } 1420 else 1421 { 1422 new_chain->next = chain->next; 1423 if (new_chain->next != 0) 1424 new_chain->next->prev = new_chain; 1425 chain->next = new_chain; 1426 new_chain->prev = chain; 1427 new_chain->insn = emit_insn_after (pat, insn); 1428 /* ??? It would be nice if we could exclude the already / still saved 1429 registers from the live sets, and observe REG_UNUSED notes. */ 1430 COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); 1431 /* Registers that are set in CHAIN->INSN live in the new insn. 1432 (Unless there is a REG_UNUSED note for them, but we don't 1433 look for them here.) */ 1434 note_stores (PATTERN (chain->insn), add_stored_regs, 1435 &new_chain->live_throughout); 1436 CLEAR_REG_SET (&new_chain->dead_or_set); 1437 if (chain->insn == BB_END (BASIC_BLOCK (chain->block))) 1438 BB_END (BASIC_BLOCK (chain->block)) = new_chain->insn; 1439 } 1440 new_chain->block = chain->block; 1441 new_chain->is_caller_save_insn = 1; 1442 1443 INSN_CODE (new_chain->insn) = code; 1444 return new_chain; 1445 } 1446 #include "gt-caller-save.h" 1447