1 /* Assemble V850 instructions. 2 Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2010, 3 2012 Free Software Foundation, Inc. 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include <stdio.h> 24 #include "opcode/v850.h" 25 #include "bfd.h" 26 #include "opintl.h" 27 28 29 /* Regular opcodes. */ 30 #define OP(x) ((x & 0x3f) << 5) 31 #define OP_MASK OP (0x3f) 32 33 /* Conditional branch opcodes (Format III). */ 34 #define BOP(x) ((0x58 << 4) | (x & 0x0f)) 35 #define BOP_MASK ((0x78 << 4) | 0x0f) 36 37 /* Conditional branch opcodes (Format VII). */ 38 #define BOP7(x) (0x107e0 | (x & 0xf)) 39 #define BOP7_MASK (0x1ffe0 | 0xf) 40 41 /* One-word opcodes. */ 42 #define one(x) ((unsigned int) (x)) 43 44 /* Two-word opcodes. */ 45 #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) 46 47 48 /* The functions used to insert and extract complicated operands. */ 49 50 /* Note: There is a conspiracy between these functions and 51 v850_insert_operand() in gas/config/tc-v850.c. Error messages 52 containing the string 'out of range' will be ignored unless a 53 specific command line option is given to GAS. */ 54 55 static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); 56 static const char * out_of_range = N_ ("displacement value is out of range"); 57 static const char * not_aligned = N_ ("displacement value is not aligned"); 58 59 static const char * immediate_out_of_range = N_ ("immediate value is out of range"); 60 static const char * branch_out_of_range = N_ ("branch value out of range"); 61 static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset"); 62 static const char * branch_to_odd_offset = N_ ("branch to odd offset"); 63 64 65 int 66 v850_msg_is_out_of_range (const char* msg) 67 { 68 return msg == out_of_range 69 || msg == immediate_out_of_range 70 || msg == branch_out_of_range; 71 } 72 73 static unsigned long 74 insert_i5div1 (unsigned long insn, long value, const char ** errmsg) 75 { 76 if (value > 30 || value < 2) 77 { 78 if (value & 1) 79 * errmsg = _(not_valid); 80 else 81 * errmsg = _(out_of_range); 82 } 83 else if (value & 1) 84 * errmsg = _(not_aligned); 85 86 value = (32 - value)/2; 87 88 return (insn | ((value << (2+16)) & 0x3c0000)); 89 } 90 91 static unsigned long 92 extract_i5div1 (unsigned long insn, int * invalid) 93 { 94 unsigned long ret = (insn & 0x003c0000) >> (16+2); 95 ret = 32 - (ret * 2); 96 97 if (invalid != 0) 98 *invalid = (ret > 30 || ret < 2) ? 1 : 0; 99 return ret; 100 } 101 102 static unsigned long 103 insert_i5div2 (unsigned long insn, long value, const char ** errmsg) 104 { 105 if (value > 30 || value < 4) 106 { 107 if (value & 1) 108 * errmsg = _(not_valid); 109 else 110 * errmsg = _(out_of_range); 111 } 112 else if (value & 1) 113 * errmsg = _(not_aligned); 114 115 value = (32 - value)/2; 116 117 return (insn | ((value << (2+16)) & 0x3c0000)); 118 } 119 120 static unsigned long 121 extract_i5div2 (unsigned long insn, int * invalid) 122 { 123 unsigned long ret = (insn & 0x003c0000) >> (16+2); 124 ret = 32 - (ret * 2); 125 126 if (invalid != 0) 127 *invalid = (ret > 30 || ret < 4) ? 1 : 0; 128 return ret; 129 } 130 131 static unsigned long 132 insert_i5div3 (unsigned long insn, long value, const char ** errmsg) 133 { 134 if (value > 32 || value < 2) 135 { 136 if (value & 1) 137 * errmsg = _(not_valid); 138 else 139 * errmsg = _(out_of_range); 140 } 141 else if (value & 1) 142 * errmsg = _(not_aligned); 143 144 value = (32 - value)/2; 145 146 return (insn | ((value << (2+16)) & 0x3c0000)); 147 } 148 149 static unsigned long 150 extract_i5div3 (unsigned long insn, int * invalid) 151 { 152 unsigned long ret = (insn & 0x003c0000) >> (16+2); 153 ret = 32 - (ret * 2); 154 155 if (invalid != 0) 156 *invalid = (ret > 32 || ret < 2) ? 1 : 0; 157 return ret; 158 } 159 160 static unsigned long 161 insert_d5_4 (unsigned long insn, long value, const char ** errmsg) 162 { 163 if (value > 0x1f || value < 0) 164 { 165 if (value & 1) 166 * errmsg = _(not_valid); 167 else 168 * errmsg = _(out_of_range); 169 } 170 else if (value & 1) 171 * errmsg = _(not_aligned); 172 173 value >>= 1; 174 175 return insn | (value & 0x0f); 176 } 177 178 static unsigned long 179 extract_d5_4 (unsigned long insn, int * invalid) 180 { 181 unsigned long ret = (insn & 0x0f); 182 183 ret <<= 1; 184 185 if (invalid != 0) 186 *invalid = 0; 187 return ret; 188 } 189 190 static unsigned long 191 insert_d8_6 (unsigned long insn, long value, const char ** errmsg) 192 { 193 if (value > 0xff || value < 0) 194 { 195 if ((value % 4) != 0) 196 * errmsg = _(not_valid); 197 else 198 * errmsg = _(out_of_range); 199 } 200 else if ((value % 4) != 0) 201 * errmsg = _(not_aligned); 202 203 value >>= 1; 204 205 return insn | (value & 0x7e); 206 } 207 208 static unsigned long 209 extract_d8_6 (unsigned long insn, int * invalid) 210 { 211 unsigned long ret = (insn & 0x7e); 212 213 ret <<= 1; 214 215 if (invalid != 0) 216 *invalid = 0; 217 return ret; 218 } 219 220 static unsigned long 221 insert_d8_7 (unsigned long insn, long value, const char ** errmsg) 222 { 223 if (value > 0xff || value < 0) 224 { 225 if ((value % 2) != 0) 226 * errmsg = _(not_valid); 227 else 228 * errmsg = _(out_of_range); 229 } 230 else if ((value % 2) != 0) 231 * errmsg = _(not_aligned); 232 233 value >>= 1; 234 235 return insn | (value & 0x7f); 236 } 237 238 static unsigned long 239 extract_d8_7 (unsigned long insn, int * invalid) 240 { 241 unsigned long ret = (insn & 0x7f); 242 243 ret <<= 1; 244 245 if (invalid != 0) 246 *invalid = 0; 247 return ret; 248 } 249 250 static unsigned long 251 insert_v8 (unsigned long insn, long value, const char ** errmsg) 252 { 253 if (value > 0xff || value < 0) 254 * errmsg = _(immediate_out_of_range); 255 256 return insn | (value & 0x1f) | ((value & 0xe0) << (27-5)); 257 } 258 259 static unsigned long 260 extract_v8 (unsigned long insn, int * invalid) 261 { 262 unsigned long ret = (insn & 0x1f) | ((insn >> (27-5)) & 0xe0); 263 264 if (invalid != 0) 265 *invalid = 0; 266 return ret; 267 } 268 269 static unsigned long 270 insert_d9 (unsigned long insn, long value, const char ** errmsg) 271 { 272 if (value > 0xff || value < -0x100) 273 { 274 if ((value % 2) != 0) 275 * errmsg = branch_out_of_range_and_odd_offset; 276 else 277 * errmsg = branch_out_of_range; 278 } 279 else if ((value % 2) != 0) 280 * errmsg = branch_to_odd_offset; 281 282 return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3); 283 } 284 285 static unsigned long 286 extract_d9 (unsigned long insn, int * invalid) 287 { 288 signed long ret = ((insn >> 7) & 0x1f0) | ((insn >> 3) & 0x0e); 289 290 ret = (ret ^ 0x100) - 0x100; 291 292 if (invalid != 0) 293 *invalid = 0; 294 return ret; 295 } 296 297 static unsigned long 298 insert_u16_loop (unsigned long insn, long value, const char ** errmsg) 299 { 300 if (value < -0xffff || value > 0) 301 { 302 if ((value % 2) != 0) 303 * errmsg = branch_out_of_range_and_odd_offset; 304 else 305 * errmsg = branch_out_of_range; 306 } 307 else if ((value % 2) != 0) 308 * errmsg = branch_to_odd_offset; 309 310 return insn | ((-value & 0xfffe) << 16); 311 } 312 313 static unsigned long 314 extract_u16_loop (unsigned long insn, int * invalid) 315 { 316 long ret = (insn >> 16) & 0xfffe; 317 ret = -ret; 318 319 if (invalid != 0) 320 *invalid = 0; 321 return ret; 322 } 323 324 static unsigned long 325 insert_d16_15 (unsigned long insn, long value, const char ** errmsg) 326 { 327 if (value > 0x7fff || value < -0x8000) 328 { 329 if ((value % 2) != 0) 330 * errmsg = _(not_valid); 331 else 332 * errmsg = _(out_of_range); 333 } 334 else if ((value % 2) != 0) 335 * errmsg = _(not_aligned); 336 337 return insn | ((value & 0xfffe) << 16); 338 } 339 340 static unsigned long 341 extract_d16_15 (unsigned long insn, int * invalid) 342 { 343 signed long ret = (insn >> 16) & 0xfffe; 344 345 ret = (ret ^ 0x8000) - 0x8000; 346 347 if (invalid != 0) 348 *invalid = 0; 349 return ret; 350 } 351 352 static unsigned long 353 insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg) 354 { 355 if (value > 0x7fff || value < -0x8000) 356 * errmsg = _(out_of_range); 357 358 return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5); 359 } 360 361 static unsigned long 362 extract_d16_16 (unsigned long insn, int * invalid) 363 { 364 signed long ret = ((insn >> 16) & 0xfffe) | ((insn >> 5) & 1); 365 366 ret = (ret ^ 0x8000) - 0x8000; 367 368 if (invalid != 0) 369 *invalid = 0; 370 return ret; 371 } 372 373 static unsigned long 374 insert_d17_16 (unsigned long insn, long value, const char ** errmsg) 375 { 376 if (value > 0xffff || value < -0x10000) 377 * errmsg = _(out_of_range); 378 379 return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4)); 380 } 381 382 static unsigned long 383 extract_d17_16 (unsigned long insn, int * invalid) 384 { 385 signed long ret = ((insn >> 16) & 0xfffe) | ((insn << (16 - 4)) & 0x10000); 386 387 ret = (ret ^ 0x10000) - 0x10000; 388 389 if (invalid != 0) 390 *invalid = 0; 391 return (unsigned long)ret; 392 } 393 394 static unsigned long 395 insert_d22 (unsigned long insn, long value, const char ** errmsg) 396 { 397 if (value > 0x1fffff || value < -0x200000) 398 { 399 if ((value % 2) != 0) 400 * errmsg = branch_out_of_range_and_odd_offset; 401 else 402 * errmsg = branch_out_of_range; 403 } 404 else if ((value % 2) != 0) 405 * errmsg = branch_to_odd_offset; 406 407 return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16); 408 } 409 410 static unsigned long 411 extract_d22 (unsigned long insn, int * invalid) 412 { 413 signed long ret = ((insn >> 16) & 0xfffe) | ((insn << 16) & 0x3f0000); 414 415 ret = (ret ^ 0x200000) - 0x200000; 416 417 if (invalid != 0) 418 *invalid = 0; 419 return (unsigned long) ret; 420 } 421 422 static unsigned long 423 insert_d23 (unsigned long insn, long value, const char ** errmsg) 424 { 425 if (value > 0x3fffff || value < -0x400000) 426 * errmsg = out_of_range; 427 428 return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)); 429 } 430 431 static unsigned long 432 extract_d23 (unsigned long insn, int * invalid) 433 { 434 signed long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fff80); 435 436 ret = (ret ^ 0x400000) - 0x400000; 437 438 if (invalid != 0) 439 *invalid = 0; 440 return (unsigned long) ret; 441 } 442 443 static unsigned long 444 insert_i9 (unsigned long insn, signed long value, const char ** errmsg) 445 { 446 if (value > 0xff || value < -0x100) 447 * errmsg = _(immediate_out_of_range); 448 449 return insn | ((value & 0x1e0) << 13) | (value & 0x1f); 450 } 451 452 static unsigned long 453 extract_i9 (unsigned long insn, int * invalid) 454 { 455 signed long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); 456 457 ret = (ret ^ 0x100) - 0x100; 458 459 if (invalid != 0) 460 *invalid = 0; 461 return ret; 462 } 463 464 static unsigned long 465 insert_u9 (unsigned long insn, long v, const char ** errmsg) 466 { 467 unsigned long value = (unsigned long) v; 468 469 if (value > 0x1ff) 470 * errmsg = _(immediate_out_of_range); 471 472 return insn | ((value & 0x1e0) << 13) | (value & 0x1f); 473 } 474 475 static unsigned long 476 extract_u9 (unsigned long insn, int * invalid) 477 { 478 unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); 479 480 if (invalid != 0) 481 *invalid = 0; 482 return ret; 483 } 484 485 static unsigned long 486 insert_spe (unsigned long insn, long v, const char ** errmsg) 487 { 488 unsigned long value = (unsigned long) v; 489 490 if (value != 3) 491 * errmsg = _("invalid register for stack adjustment"); 492 493 return insn & ~0x180000; 494 } 495 496 static unsigned long 497 extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid) 498 { 499 if (invalid != 0) 500 *invalid = 0; 501 502 return 3; 503 } 504 505 static unsigned long 506 insert_r4 (unsigned long insn, long v, const char ** errmsg) 507 { 508 unsigned long value = (unsigned long) v; 509 510 if (value >= 32) 511 { 512 * errmsg = _("invalid register name"); 513 } 514 515 return insn | ((value & 0x10) << (23-4)) | ((value & 0x0f) << (17)); 516 } 517 518 static unsigned long 519 extract_r4 (unsigned long insn, int * invalid) 520 { 521 unsigned long ret = ((insn >> (23-4)) & 0x10) | ((insn >> 17) & 0x0f); 522 523 if (invalid != 0) 524 *invalid = 0; 525 return ret; 526 } 527 528 /* Warning: code in gas/config/tc-v850.c examines the contents of this array. 529 If you change any of the values here, be sure to look for side effects in 530 that code. */ 531 const struct v850_operand v850_operands[] = 532 { 533 #define UNUSED 0 534 { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 535 536 /* The R1 field in a format 1, 6, 7, 9, C insn. */ 537 #define R1 (UNUSED + 1) 538 { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, 539 540 /* As above, but register 0 is not allowed. */ 541 #define R1_NOTR0 (R1 + 1) 542 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, 543 544 /* Even register is allowed. */ 545 #define R1_EVEN (R1_NOTR0 + 1) 546 { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, 547 548 /* Bang (bit reverse). */ 549 #define R1_BANG (R1_EVEN + 1) 550 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE }, 551 552 /* Percent (modulo). */ 553 #define R1_PERCENT (R1_BANG + 1) 554 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE }, 555 556 /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */ 557 #define R2 (R1_PERCENT + 1) 558 { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, 559 560 /* As above, but register 0 is not allowed. */ 561 #define R2_NOTR0 (R2 + 1) 562 { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, 563 564 /* Even register is allowed. */ 565 #define R2_EVEN (R2_NOTR0 + 1) 566 { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, 567 568 /* Reg2 in dispose instruction. */ 569 #define R2_DISPOSE (R2_EVEN + 1) 570 { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, 571 572 /* The R3 field in a format 11, 12, C insn. */ 573 #define R3 (R2_DISPOSE + 1) 574 { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, 575 576 /* As above, but register 0 is not allowed. */ 577 #define R3_NOTR0 (R3 + 1) 578 { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, 579 580 /* As above, but odd number registers are not allowed. */ 581 #define R3_EVEN (R3_NOTR0 + 1) 582 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, 583 584 /* As above, but register 0 is not allowed. */ 585 #define R3_EVEN_NOTR0 (R3_EVEN + 1) 586 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE }, 587 588 /* Forth register in FPU Instruction. */ 589 #define R4 (R3_EVEN_NOTR0 + 1) 590 { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE }, 591 592 /* As above, but odd number registers are not allowed. */ 593 #define R4_EVEN (R4 + 1) 594 { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, 595 596 /* Stack pointer in prepare instruction. */ 597 #define SP (R4_EVEN + 1) 598 { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE }, 599 600 /* EP Register. */ 601 #define EP (SP + 1) 602 { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE }, 603 604 /* A list of registers in a prepare/dispose instruction. */ 605 #define LIST12 (EP + 1) 606 { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE }, 607 608 /* System register operands. */ 609 #define SR1 (LIST12 + 1) 610 { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, 611 612 /* The R2 field as a system register. */ 613 #define SR2 (SR1 + 1) 614 { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, 615 616 /* FPU CC bit position. */ 617 #define FFF (SR2 + 1) 618 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, 619 620 /* The 4 bit condition code in a setf instruction. */ 621 #define CCCC (FFF + 1) 622 { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, 623 624 /* Condition code in adf,sdf. */ 625 #define CCCC_NOTSA (CCCC + 1) 626 { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE }, 627 628 /* Condition code in conditional moves. */ 629 #define MOVCC (CCCC_NOTSA + 1) 630 { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, 631 632 /* Condition code in FPU. */ 633 #define FLOAT_CCCC (MOVCC + 1) 634 { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE }, 635 636 /* The 1 bit immediate field in format C insn. */ 637 #define VI1 (FLOAT_CCCC + 1) 638 { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE }, 639 640 /* The 1 bit immediate field in format C insn. */ 641 #define VC1 (VI1 + 1) 642 { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 643 644 /* The 2 bit immediate field in format C insn. */ 645 #define DI2 (VC1 + 1) 646 { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE }, 647 648 /* The 2 bit immediate field in format C insn. */ 649 #define VI2 (DI2 + 1) 650 { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 651 652 /* The 2 bit immediate field in format C - DUP insn. */ 653 #define VI2DUP (VI2 + 1) 654 { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE }, 655 656 /* The 3 bit immediate field in format 8 insn. */ 657 #define B3 (VI2DUP + 1) 658 { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE }, 659 660 /* The 3 bit immediate field in format C insn. */ 661 #define DI3 (B3 + 1) 662 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, 663 664 /* The 3 bit immediate field in format C insn. */ 665 #define I3U (DI3 + 1) 666 { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 667 668 /* The 4 bit immediate field in format C insn. */ 669 #define I4U (I3U + 1) 670 { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 671 672 /* The 4 bit immediate field in fetrap. */ 673 #define I4U_NOTIMM0 (I4U + 1) 674 { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE }, 675 676 /* The unsigned disp4 field in a sld.bu. */ 677 #define D4U (I4U_NOTIMM0 + 1) 678 { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET }, 679 680 /* The imm5 field in a format 2 insn. */ 681 #define I5 (D4U + 1) 682 { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, 683 684 /* The imm5 field in a format 11 insn. */ 685 #define I5DIV1 (I5 + 1) 686 { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE }, 687 688 #define I5DIV2 (I5DIV1 + 1) 689 { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE }, 690 691 #define I5DIV3 (I5DIV2 + 1) 692 { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE }, 693 694 /* The unsigned imm5 field in a format 2 insn. */ 695 #define I5U (I5DIV3 + 1) 696 { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE }, 697 698 /* The imm5 field in a prepare/dispose instruction. */ 699 #define IMM5 (I5U + 1) 700 { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE }, 701 702 /* The unsigned disp5 field in a sld.hu. */ 703 #define D5_4U (IMM5 + 1) 704 { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET }, 705 706 /* The IMM6 field in a callt instruction. */ 707 #define IMM6 (D5_4U + 1) 708 { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET }, 709 710 /* The signed disp7 field in a format 4 insn. */ 711 #define D7U (IMM6 + 1) 712 { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET }, 713 714 /* The unsigned DISP8 field in a format 4 insn. */ 715 #define D8_7U (D7U + 1) 716 { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET }, 717 718 /* The unsigned DISP8 field in a format 4 insn. */ 719 #define D8_6U (D8_7U + 1) 720 { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET }, 721 722 /* The unsigned DISP8 field in a format 4 insn. */ 723 #define V8 (D8_6U + 1) 724 { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE }, 725 726 /* The imm9 field in a multiply word. */ 727 #define I9 (V8 + 1) 728 { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, 729 730 /* The unsigned imm9 field in a multiply word. */ 731 #define U9 (I9 + 1) 732 { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE }, 733 734 /* The DISP9 field in a format 3 insn. */ 735 #define D9 (U9 + 1) 736 { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, 737 738 /* The DISP9 field in a format 3 insn, relaxable. */ 739 #define D9_RELAX (D9 + 1) 740 { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, 741 742 /* The imm16 field in a format 6 insn. */ 743 #define I16 (D9_RELAX + 1) 744 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 }, 745 746 /* The 16 bit immediate following a 32 bit instruction. */ 747 #define IMM16 (I16 + 1) 748 { 16, 32, NULL, NULL, V850E_IMMEDIATE16, BFD_RELOC_16 }, 749 750 /* The 16 bit immediate following a 32 bit instruction. */ 751 #define IMM16LO (IMM16 + 1) 752 { 16, 32, NULL, NULL, V850E_IMMEDIATE16, BFD_RELOC_LO16 }, 753 754 /* The hi 16 bit immediate following a 32 bit instruction. */ 755 #define IMM16HI (IMM16LO + 1) 756 { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 }, 757 758 /* The unsigned imm16 in a format 6 insn. */ 759 #define I16U (IMM16HI + 1) 760 { 16, 16, NULL, NULL, 0, BFD_RELOC_16 }, 761 762 /* The disp16 field in a format 8 insn. */ 763 #define D16 (I16U + 1) 764 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 }, 765 766 /* The disp16 field in an format 7 unsigned byte load insn. */ 767 #define D16_16 (D16 + 1) 768 { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET }, 769 770 /* The disp16 field in a format 6 insn. */ 771 #define D16_15 (D16_16 + 1) 772 { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 }, 773 774 /* The unsigned DISP16 field in a format 7 insn. */ 775 #define D16_LOOP (D16_15 + 1) 776 { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_16_PCREL }, 777 778 /* The DISP17 field in a format 7 insn. */ 779 #define D17_16 (D16_LOOP + 1) 780 { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL }, 781 782 /* The DISP22 field in a format 4 insn, relaxable. 783 This _must_ follow D9_RELAX; the assembler assumes that the longer 784 version immediately follows the shorter version for relaxing. */ 785 #define D22 (D17_16 + 1) 786 { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL }, 787 788 #define D23 (D22 + 1) 789 { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, 790 791 /* The 32 bit immediate following a 32 bit instruction. */ 792 #define IMM32 (D23 + 1) 793 { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 }, 794 795 #define D32_31 (IMM32 + 1) 796 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS }, 797 798 #define D32_31_PCREL (D32_31 + 1) 799 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL }, 800 801 }; 802 803 804 /* Reg - Reg instruction format (Format I). */ 805 #define IF1 {R1, R2} 806 807 /* Imm - Reg instruction format (Format II). */ 808 #define IF2 {I5, R2} 809 810 /* Conditional branch instruction format (Format III). */ 811 #define IF3 {D9_RELAX} 812 813 /* 3 operand instruction (Format VI). */ 814 #define IF6 {I16, R1, R2} 815 816 /* 3 operand instruction (Format VI). */ 817 #define IF6U {I16U, R1, R2} 818 819 /* Conditional branch instruction format (Format VII). */ 820 #define IF7 {D17_16} 821 822 823 /* The opcode table. 824 825 The format of the opcode table is: 826 827 NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR 828 829 NAME is the name of the instruction. 830 OPCODE is the instruction opcode. 831 MASK is the opcode mask; this is used to tell the disassembler 832 which bits in the actual opcode must match OPCODE. 833 OPERANDS is the list of operands. 834 MEMOP specifies which operand (if any) is a memory operand. 835 PROCESSORS specifies which CPU(s) support the opcode. 836 837 The disassembler reads the table in order and prints the first 838 instruction which matches, so this table is sorted to put more 839 specific instructions before more general instructions. It is also 840 sorted by major opcode. 841 842 The table is also sorted by name. This is used by the assembler. 843 When parsing an instruction the assembler finds the first occurance 844 of the name of the instruciton in this table and then attempts to 845 match the instruction's arguments with description of the operands 846 associated with the entry it has just found in this table. If the 847 match fails the assembler looks at the next entry in this table. 848 If that entry has the same name as the previous entry, then it 849 tries to match the instruction against that entry and so on. This 850 is how the assembler copes with multiple, different formats of the 851 same instruction. */ 852 853 const struct v850_opcode v850_opcodes[] = 854 { 855 /* Standard instructions. */ 856 { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, 857 { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, 858 859 { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, 860 861 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, 862 863 { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, 864 865 { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, 866 867 /* Signed integer. */ 868 { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 869 { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 870 { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 871 { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 872 /* Unsigned integer. */ 873 { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 874 { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 875 { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 876 { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 877 /* Common. */ 878 { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 879 { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 880 /* Others. */ 881 { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 882 { "bf", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 883 { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 884 { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 885 { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 886 { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 887 { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 888 { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 889 { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 890 { "bt", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 891 { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 892 { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 893 894 { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, 895 896 { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, 897 898 { "callt", one (0x0200), one (0xffc0), {IMM6}, 0, PROCESSOR_NOT_V850 }, 899 900 { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_ALL }, 901 902 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, 903 { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, 904 905 { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 906 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, 907 908 { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, 909 { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, 910 911 { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, 912 913 { "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, 914 915 { "dbtrap", one (0xf840), one (0xffff), {0}, 0, PROCESSOR_NOT_V850 }, 916 917 { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, 918 919 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 }, 920 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, 921 922 { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 923 924 { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 925 { "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, PROCESSOR_ALL }, 926 927 { "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 928 929 { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 930 931 { "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 932 { "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 933 934 { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, 935 936 { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, 937 938 { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 939 940 { "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 941 942 { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, 943 944 { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_ALL }, 945 946 { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_ALL }, 947 948 { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_ALL }, 949 950 { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, 951 952 { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, 953 954 { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, 955 956 { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL}, 957 { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_ALL }, 958 /* Gas local alias of mov imm22(not defined in spec). */ 959 { "jarl22", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS}, 960 /* Gas local alias of mov imm32(not defined in spec). */ 961 { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 962 { "jarlw", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 963 964 { "jmp", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_ALL }, 965 { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, 966 /* Gas local alias of jmp disp22(not defined in spec). */ 967 { "jmp22", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, 968 /* Gas local alias of jmp disp32(not defined in spec). */ 969 { "jmp32", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 970 { "jmpw", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 971 972 { "jr", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, 973 { "jr", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_ALL }, 974 /* Gas local alias of mov imm22(not defined in spec). */ 975 { "jr22", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, 976 /* Gas local alias of mov imm32(not defined in spec). */ 977 { "jr32", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 978 979 /* Alias of bcond (same as CA850). */ 980 { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 981 { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 982 { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 983 { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 984 /* Unsigned integer. */ 985 { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 986 { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 987 { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 988 { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 989 /* Common. */ 990 { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 991 { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 992 /* Others. */ 993 { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 994 { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 995 { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 996 { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 997 { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 998 { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 999 { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1000 { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1001 { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, 1002 1003 1004 { "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, 1005 1006 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL }, 1007 { "ld.b", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, 1008 { "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 1009 1010 { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, 1011 { "ld.bu", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, 1012 { "ld.bu23", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 1013 1014 { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, 1015 { "ld.h", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, 1016 { "ld.h23", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 1017 1018 { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, 1019 { "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, 1020 { "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 1021 1022 1023 { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, 1024 { "ld.w", two (0x0780, 0x0009), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, 1025 { "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 1026 1027 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, 1028 1029 { "macacc", two (0x07e0, 0x0bc0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, 1030 1031 { "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_ALL }, 1032 1033 { "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_ALL }, 1034 1035 { "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, 1036 1037 { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1038 { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, 1039 { "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 }, 1040 /* Gas local alias of mov imm32(not defined in spec). */ 1041 { "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS }, 1042 1043 { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1044 1045 { "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1046 1047 { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1048 { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1049 1050 { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, 1051 { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1052 1053 { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1054 1055 { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1056 { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, 1057 1058 { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, 1059 1060 { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1061 1062 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, 1063 { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, 1064 1065 { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1066 1067 { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, 1068 1069 { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, 1070 { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }, 1071 { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 }, 1072 { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, 1073 { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, 1074 1075 { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, 1076 1077 { "sar", two (0x07e0, 0x00a2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1078 { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, 1079 { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, 1080 1081 { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, 1082 1083 { "satadd", two (0x07e0, 0x03ba), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1084 { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, 1085 { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1086 1087 { "satsub", two (0x07e0, 0x039a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1088 { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1089 1090 { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1091 1092 { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, 1093 1094 { "sbf", two (0x07e0, 0x0380), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1095 1096 { "sch0l", two (0x07e0, 0x0364), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1097 1098 { "sch0r", two (0x07e0, 0x0360), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1099 1100 { "sch1l", two (0x07e0, 0x0366), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1101 1102 { "sch1r", two (0x07e0, 0x0362), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1103 1104 { "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1105 { "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1106 { "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1107 { "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, 1108 1109 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, 1110 { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, 1111 1112 { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, 1113 1114 { "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1115 { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, 1116 { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, 1117 1118 { "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, 1119 { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, 1120 { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, 1121 1122 { "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, PROCESSOR_ALL }, 1123 1124 { "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, 1125 1126 { "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, PROCESSOR_ALL }, 1127 1128 { "sld.hu", one (0x0070), one (0x07f0), {D5_4U,EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, 1129 1130 { "sld.w", one (0x0500), one (0x0781), {D8_6U,EP, R2}, 2, PROCESSOR_ALL }, 1131 1132 { "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, PROCESSOR_ALL }, 1133 1134 { "sst.h", one (0x0480), one (0x0780), {R2, D8_7U,EP}, 3, PROCESSOR_ALL }, 1135 1136 { "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, PROCESSOR_ALL }, 1137 1138 { "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, 1139 { "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, 1140 1141 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL }, 1142 { "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL }, 1143 { "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 1144 1145 { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, 1146 { "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL }, 1147 { "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 1148 1149 { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, 1150 { "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL }, 1151 { "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, 1152 1153 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, 1154 1155 { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1156 1157 { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1158 1159 { "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, 1160 1161 { "sxb", one (0x00a0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, 1162 1163 { "sxh", one (0x00e0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, 1164 1165 { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, 1166 1167 { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1168 1169 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, 1170 { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, 1171 1172 { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, 1173 1174 { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, 1175 1176 { "zxb", one (0x0080), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, 1177 1178 { "zxh", one (0x00c0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, 1179 1180 /* Floating point operation. */ 1181 { "absf.d", two (0x07e0, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1182 { "absf.s", two (0x07e0, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1183 { "addf.d", two (0x07e0, 0x0470), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1184 { "addf.s", two (0x07e0, 0x0460), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, 1185 { "ceilf.dl", two (0x07e2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1186 { "ceilf.dul", two (0x07f2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1187 { "ceilf.duw", two (0x07f2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1188 { "ceilf.dw", two (0x07e2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1189 { "ceilf.sl", two (0x07e2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1190 { "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1191 { "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1192 { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1193 { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1194 { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3 }, 1195 /* Default value for FFF is 0(not defined in spec). */ 1196 { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3 }, 1197 { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3 }, 1198 /* Default value for FFF is 0(not defined in spec). */ 1199 { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07ff), {R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3 }, 1200 { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF}, 0, PROCESSOR_V850E2V3 }, 1201 { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87ff), {FLOAT_CCCC, R2_EVEN, R1_EVEN}, 0, PROCESSOR_V850E2V3 }, 1202 { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R2, R1, FFF}, 0, PROCESSOR_V850E2V3 }, 1203 { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87ff), {FLOAT_CCCC, R2, R1}, 0, PROCESSOR_V850E2V3 }, 1204 { "cvtf.dl", two (0x07e4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1205 { "cvtf.ds", two (0x07e3, 0x0452), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1206 { "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1207 { "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1208 { "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1209 { "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1210 { "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1211 { "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1212 { "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1213 { "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1214 { "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1215 { "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1216 { "cvtf.uld", two (0x07f1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1217 { "cvtf.uls", two (0x07f1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1218 { "cvtf.uwd", two (0x07f0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1219 { "cvtf.uws", two (0x07f0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1220 { "cvtf.wd", two (0x07e0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1221 { "cvtf.ws", two (0x07e0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1222 { "divf.d", two (0x07e0, 0x047e), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1223 { "divf.s", two (0x07e0, 0x046e), two (0x07e0, 0x07ff), {R1_NOTR0, R2, R3}, 0, PROCESSOR_V850E2V3 }, 1224 { "floorf.dl", two (0x07e3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1225 { "floorf.dul", two (0x07f3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1226 { "floorf.duw", two (0x07f3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1227 { "floorf.dw", two (0x07e3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1228 { "floorf.sl", two (0x07e3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1229 { "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1230 { "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1231 { "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1232 { "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, 1233 { "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1234 { "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, 1235 { "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1236 { "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, 1237 { "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, 1238 { "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1239 { "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, 1240 { "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1241 { "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1242 { "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, 1243 { "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, 1244 { "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1245 { "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1246 1247 { "roundf.dl", two (0x07e0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, 1248 { "roundf.dul", two (0x07f0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, 1249 { "roundf.duw", two (0x07f0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, 1250 { "roundf.dw", two (0x07e0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, 1251 { "roundf.sl", two (0x07e0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, 1252 { "roundf.sul", two (0x07f0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, 1253 { "roundf.suw", two (0x07f0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, 1254 { "roundf.sw", two (0x07e0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, 1255 1256 { "rsqrtf.d", two (0x07e2, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1257 { "rsqrtf.s", two (0x07e2, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1258 { "sqrtf.d", two (0x07e0, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1259 { "sqrtf.s", two (0x07e0, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1260 { "subf.d", two (0x07e0, 0x0472), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1261 { "subf.s", two (0x07e0, 0x0462), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, 1262 { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3 }, 1263 { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2V3 }, 1264 { "trncf.dl", two (0x07e1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1265 { "trncf.dul", two (0x07f1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1266 { "trncf.duw", two (0x07f1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1267 { "trncf.dw", two (0x07e1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, 1268 { "trncf.sl", two (0x07e1, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, 1269 { "trncf.sul", two (0x07f1, 0x0444), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1270 { "trncf.suw", two (0x07f1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1271 { "trncf.sw", two (0x07e1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, 1272 1273 /* Special instruction (from gdb) mov 1, r0. */ 1274 { "breakpoint", one (0x0001), one (0xffff), {UNUSED}, 0, PROCESSOR_ALL }, 1275 1276 /* V850e2-v3. */ 1277 { "synce", one (0x001d), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, 1278 { "syncm", one (0x001e), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, 1279 { "syncp", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, 1280 { "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3 }, 1281 /* Alias of syncp. */ 1282 { "sync", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_ALIAS }, 1283 { "rmtrap", one (0xf040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, 1284 1285 1286 { "rie", one (0x0040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, 1287 { "rie", two (0x07f0, 0x0000), two (0x07f0, 0xffff), {0}, 0, PROCESSOR_V850E2V3 }, 1288 1289 { 0, 0, 0, {0}, 0, 0 }, 1290 } ; 1291 1292 const int v850_num_opcodes = 1293 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); 1294