1 /* Print SPARC instructions. 2 Copyright (C) 1989-2018 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 #include "sysdep.h" 22 #include <stdio.h> 23 #include "opcode/sparc.h" 24 #include "dis-asm.h" 25 #include "libiberty.h" 26 #include "opintl.h" 27 28 /* Bitmask of v9 architectures. */ 29 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ 30 | (1 << SPARC_OPCODE_ARCH_V9A) \ 31 | (1 << SPARC_OPCODE_ARCH_V9B) \ 32 | (1 << SPARC_OPCODE_ARCH_V9C) \ 33 | (1 << SPARC_OPCODE_ARCH_V9D) \ 34 | (1 << SPARC_OPCODE_ARCH_V9E) \ 35 | (1 << SPARC_OPCODE_ARCH_V9V) \ 36 | (1 << SPARC_OPCODE_ARCH_V9M) \ 37 | (1 << SPARC_OPCODE_ARCH_M8)) 38 /* 1 if INSN is for v9 only. */ 39 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) 40 /* 1 if INSN is for v9. */ 41 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) 42 43 /* The sorted opcode table. */ 44 static const sparc_opcode **sorted_opcodes; 45 46 /* For faster lookup, after insns are sorted they are hashed. */ 47 /* ??? I think there is room for even more improvement. */ 48 49 #define HASH_SIZE 256 50 /* It is important that we only look at insn code bits as that is how the 51 opcode table is hashed. OPCODE_BITS is a table of valid bits for each 52 of the main types (0,1,2,3). */ 53 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; 54 #define HASH_INSN(INSN) \ 55 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) 56 typedef struct sparc_opcode_hash 57 { 58 struct sparc_opcode_hash *next; 59 const sparc_opcode *opcode; 60 } sparc_opcode_hash; 61 62 static sparc_opcode_hash *opcode_hash_table[HASH_SIZE]; 63 64 /* Sign-extend a value which is N bits long. */ 65 #define SEX(value, bits) \ 66 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ 67 >> ((8 * sizeof (int)) - bits) ) 68 69 static char *reg_names[] = 70 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 71 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", 72 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 73 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", 74 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 75 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 76 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 77 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 78 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", 79 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", 80 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", 81 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", 82 /* psr, wim, tbr, fpsr, cpsr are v8 only. */ 83 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" 84 }; 85 86 #define freg_names (®_names[4 * 8]) 87 88 /* These are ordered according to there register number in 89 rdpr and wrpr insns. */ 90 static char *v9_priv_reg_names[] = 91 { 92 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", 93 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", 94 "wstate", "fq", "gl" 95 /* "ver" and "pmcdper" - special cased */ 96 }; 97 98 /* These are ordered according to there register number in 99 rdhpr and wrhpr insns. */ 100 static char *v9_hpriv_reg_names[] = 101 { 102 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver", 103 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13", 104 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20", 105 "resv21", "resv22", "hmcdper", "hmcddfr", "resv25", "resv26", "hva_mask_nz", 106 "hstick_offset", "hstick_enable", "resv30", "hstick_cmpr" 107 }; 108 109 /* These are ordered according to there register number in 110 rd and wr insns (-16). */ 111 static char *v9a_asr_reg_names[] = 112 { 113 "pcr", "pic", "dcr", "gsr", "softint_set", "softint_clear", 114 "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr", 115 "pause", "mwait" 116 }; 117 118 /* Macros used to extract instruction fields. Not all fields have 119 macros defined here, only those which are actually used. */ 120 121 #define X_RD(i) (((i) >> 25) & 0x1f) 122 #define X_RS1(i) (((i) >> 14) & 0x1f) 123 #define X_LDST_I(i) (((i) >> 13) & 1) 124 #define X_ASI(i) (((i) >> 5) & 0xff) 125 #define X_RS2(i) (((i) >> 0) & 0x1f) 126 #define X_RS3(i) (((i) >> 9) & 0x1f) 127 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) 128 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) 129 #define X_DISP22(i) (((i) >> 0) & 0x3fffff) 130 #define X_IMM22(i) X_DISP22 (i) 131 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff) 132 #define X_IMM2(i) (((i & 0x10) >> 3) | (i & 0x1)) 133 134 /* These are for v9. */ 135 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) 136 #define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff)) 137 #define X_DISP19(i) (((i) >> 0) & 0x7ffff) 138 #define X_MEMBAR(i) ((i) & 0x7f) 139 140 /* Here is the union which was used to extract instruction fields 141 before the shift and mask macros were written. 142 143 union sparc_insn 144 { 145 unsigned long int code; 146 struct 147 { 148 unsigned int anop:2; 149 #define op ldst.anop 150 unsigned int anrd:5; 151 #define rd ldst.anrd 152 unsigned int op3:6; 153 unsigned int anrs1:5; 154 #define rs1 ldst.anrs1 155 unsigned int i:1; 156 unsigned int anasi:8; 157 #define asi ldst.anasi 158 unsigned int anrs2:5; 159 #define rs2 ldst.anrs2 160 #define shcnt rs2 161 } ldst; 162 struct 163 { 164 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; 165 unsigned int IMM13:13; 166 #define imm13 IMM13.IMM13 167 } IMM13; 168 struct 169 { 170 unsigned int anop:2; 171 unsigned int a:1; 172 unsigned int cond:4; 173 unsigned int op2:3; 174 unsigned int DISP22:22; 175 #define disp22 branch.DISP22 176 #define imm22 disp22 177 } branch; 178 struct 179 { 180 unsigned int anop:2; 181 unsigned int a:1; 182 unsigned int z:1; 183 unsigned int rcond:3; 184 unsigned int op2:3; 185 unsigned int DISP16HI:2; 186 unsigned int p:1; 187 unsigned int _rs1:5; 188 unsigned int DISP16LO:14; 189 } branch16; 190 struct 191 { 192 unsigned int anop:2; 193 unsigned int adisp30:30; 194 #define disp30 call.adisp30 195 } call; 196 }; */ 197 198 /* Nonzero if INSN is the opcode for a delayed branch. */ 199 200 static int 201 is_delayed_branch (unsigned long insn) 202 { 203 sparc_opcode_hash *op; 204 205 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) 206 { 207 const sparc_opcode *opcode = op->opcode; 208 209 if ((opcode->match & insn) == opcode->match 210 && (opcode->lose & insn) == 0) 211 return opcode->flags & F_DELAYED; 212 } 213 return 0; 214 } 215 216 /* extern void qsort (); */ 217 218 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value 219 to compare_opcodes. */ 220 static unsigned int current_arch_mask; 221 222 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ 223 224 static int 225 compute_arch_mask (unsigned long mach) 226 { 227 switch (mach) 228 { 229 case 0 : 230 case bfd_mach_sparc : 231 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) 232 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)); 233 case bfd_mach_sparc_sparclet : 234 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); 235 case bfd_mach_sparc_sparclite : 236 case bfd_mach_sparc_sparclite_le : 237 /* sparclites insns are recognized by default (because that's how 238 they've always been treated, for better or worse). Kludge this by 239 indicating generic v8 is also selected. */ 240 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) 241 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); 242 case bfd_mach_sparc_v8plus : 243 case bfd_mach_sparc_v9 : 244 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 245 case bfd_mach_sparc_v8plusa : 246 case bfd_mach_sparc_v9a : 247 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); 248 case bfd_mach_sparc_v8plusb : 249 case bfd_mach_sparc_v9b : 250 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); 251 case bfd_mach_sparc_v8plusc : 252 case bfd_mach_sparc_v9c : 253 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C); 254 case bfd_mach_sparc_v8plusd : 255 case bfd_mach_sparc_v9d : 256 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D); 257 case bfd_mach_sparc_v8pluse : 258 case bfd_mach_sparc_v9e : 259 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E); 260 case bfd_mach_sparc_v8plusv : 261 case bfd_mach_sparc_v9v : 262 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V); 263 case bfd_mach_sparc_v8plusm : 264 case bfd_mach_sparc_v9m : 265 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M); 266 case bfd_mach_sparc_v8plusm8 : 267 case bfd_mach_sparc_v9m8 : 268 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8); 269 } 270 abort (); 271 } 272 273 /* Compare opcodes A and B. */ 274 275 static int 276 compare_opcodes (const void * a, const void * b) 277 { 278 sparc_opcode *op0 = * (sparc_opcode **) a; 279 sparc_opcode *op1 = * (sparc_opcode **) b; 280 unsigned long int match0 = op0->match, match1 = op1->match; 281 unsigned long int lose0 = op0->lose, lose1 = op1->lose; 282 register unsigned int i; 283 284 /* If one (and only one) insn isn't supported by the current architecture, 285 prefer the one that is. If neither are supported, but they're both for 286 the same architecture, continue processing. Otherwise (both unsupported 287 and for different architectures), prefer lower numbered arch's (fudged 288 by comparing the bitmasks). */ 289 if (op0->architecture & current_arch_mask) 290 { 291 if (! (op1->architecture & current_arch_mask)) 292 return -1; 293 } 294 else 295 { 296 if (op1->architecture & current_arch_mask) 297 return 1; 298 else if (op0->architecture != op1->architecture) 299 return op0->architecture - op1->architecture; 300 } 301 302 /* If a bit is set in both match and lose, there is something 303 wrong with the opcode table. */ 304 if (match0 & lose0) 305 { 306 fprintf 307 (stderr, 308 /* xgettext:c-format */ 309 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), 310 op0->name, match0, lose0); 311 op0->lose &= ~op0->match; 312 lose0 = op0->lose; 313 } 314 315 if (match1 & lose1) 316 { 317 fprintf 318 (stderr, 319 /* xgettext:c-format */ 320 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), 321 op1->name, match1, lose1); 322 op1->lose &= ~op1->match; 323 lose1 = op1->lose; 324 } 325 326 /* Because the bits that are variable in one opcode are constant in 327 another, it is important to order the opcodes in the right order. */ 328 for (i = 0; i < 32; ++i) 329 { 330 unsigned long int x = 1 << i; 331 int x0 = (match0 & x) != 0; 332 int x1 = (match1 & x) != 0; 333 334 if (x0 != x1) 335 return x1 - x0; 336 } 337 338 for (i = 0; i < 32; ++i) 339 { 340 unsigned long int x = 1 << i; 341 int x0 = (lose0 & x) != 0; 342 int x1 = (lose1 & x) != 0; 343 344 if (x0 != x1) 345 return x1 - x0; 346 } 347 348 /* They are functionally equal. So as long as the opcode table is 349 valid, we can put whichever one first we want, on aesthetic grounds. */ 350 351 /* Our first aesthetic ground is that aliases defer to real insns. */ 352 { 353 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); 354 355 if (alias_diff != 0) 356 /* Put the one that isn't an alias first. */ 357 return alias_diff; 358 } 359 360 /* Except for aliases, two "identical" instructions had 361 better have the same opcode. This is a sanity check on the table. */ 362 i = strcmp (op0->name, op1->name); 363 if (i) 364 { 365 if (op0->flags & F_ALIAS) 366 { 367 if (op0->flags & F_PREFERRED) 368 return -1; 369 if (op1->flags & F_PREFERRED) 370 return 1; 371 372 /* If they're both aliases, and neither is marked as preferred, 373 be arbitrary. */ 374 return i; 375 } 376 else 377 fprintf (stderr, 378 /* xgettext:c-format */ 379 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), 380 op0->name, op1->name); 381 } 382 383 /* Fewer arguments are preferred. */ 384 { 385 int length_diff = strlen (op0->args) - strlen (op1->args); 386 387 if (length_diff != 0) 388 /* Put the one with fewer arguments first. */ 389 return length_diff; 390 } 391 392 /* Put 1+i before i+1. */ 393 { 394 char *p0 = (char *) strchr (op0->args, '+'); 395 char *p1 = (char *) strchr (op1->args, '+'); 396 397 if (p0 && p1) 398 { 399 /* There is a plus in both operands. Note that a plus 400 sign cannot be the first character in args, 401 so the following [-1]'s are valid. */ 402 if (p0[-1] == 'i' && p1[1] == 'i') 403 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ 404 return 1; 405 if (p0[1] == 'i' && p1[-1] == 'i') 406 /* op0 is 1+i and op1 is i+1, so op0 goes first. */ 407 return -1; 408 } 409 } 410 411 /* Put 1,i before i,1. */ 412 { 413 int i0 = strncmp (op0->args, "i,1", 3) == 0; 414 int i1 = strncmp (op1->args, "i,1", 3) == 0; 415 416 if (i0 ^ i1) 417 return i0 - i1; 418 } 419 420 /* They are, as far as we can tell, identical. 421 Since qsort may have rearranged the table partially, there is 422 no way to tell which one was first in the opcode table as 423 written, so just say there are equal. */ 424 /* ??? This is no longer true now that we sort a vector of pointers, 425 not the table itself. */ 426 return 0; 427 } 428 429 /* Build a hash table from the opcode table. 430 OPCODE_TABLE is a sorted list of pointers into the opcode table. */ 431 432 static void 433 build_hash_table (const sparc_opcode **opcode_table, 434 sparc_opcode_hash **hash_table, 435 int num_opcodes) 436 { 437 int i; 438 int hash_count[HASH_SIZE]; 439 static sparc_opcode_hash *hash_buf = NULL; 440 441 /* Start at the end of the table and work backwards so that each 442 chain is sorted. */ 443 444 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); 445 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); 446 if (hash_buf != NULL) 447 free (hash_buf); 448 hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes); 449 for (i = num_opcodes - 1; i >= 0; --i) 450 { 451 int hash = HASH_INSN (opcode_table[i]->match); 452 sparc_opcode_hash *h = &hash_buf[i]; 453 454 h->next = hash_table[hash]; 455 h->opcode = opcode_table[i]; 456 hash_table[hash] = h; 457 ++hash_count[hash]; 458 } 459 460 #if 0 /* for debugging */ 461 { 462 int min_count = num_opcodes, max_count = 0; 463 int total; 464 465 for (i = 0; i < HASH_SIZE; ++i) 466 { 467 if (hash_count[i] < min_count) 468 min_count = hash_count[i]; 469 if (hash_count[i] > max_count) 470 max_count = hash_count[i]; 471 total += hash_count[i]; 472 } 473 474 printf ("Opcode hash table stats: min %d, max %d, ave %f\n", 475 min_count, max_count, (double) total / HASH_SIZE); 476 } 477 #endif 478 } 479 480 /* Print one instruction from MEMADDR on INFO->STREAM. 481 482 We suffix the instruction with a comment that gives the absolute 483 address involved, as well as its symbolic form, if the instruction 484 is preceded by a findable `sethi' and it either adds an immediate 485 displacement to that register, or it is an `add' or `or' instruction 486 on that register. */ 487 488 int 489 print_insn_sparc (bfd_vma memaddr, disassemble_info *info) 490 { 491 FILE *stream = info->stream; 492 bfd_byte buffer[4]; 493 unsigned long insn; 494 sparc_opcode_hash *op; 495 /* Nonzero of opcode table has been initialized. */ 496 static int opcodes_initialized = 0; 497 /* bfd mach number of last call. */ 498 static unsigned long current_mach = 0; 499 bfd_vma (*getword) (const void *); 500 501 if (!opcodes_initialized 502 || info->mach != current_mach) 503 { 504 int i; 505 506 current_arch_mask = compute_arch_mask (info->mach); 507 508 if (!opcodes_initialized) 509 sorted_opcodes = 510 xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *)); 511 /* Reset the sorted table so we can resort it. */ 512 for (i = 0; i < sparc_num_opcodes; ++i) 513 sorted_opcodes[i] = &sparc_opcodes[i]; 514 qsort ((char *) sorted_opcodes, sparc_num_opcodes, 515 sizeof (sorted_opcodes[0]), compare_opcodes); 516 517 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); 518 current_mach = info->mach; 519 opcodes_initialized = 1; 520 } 521 522 { 523 int status = 524 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); 525 526 if (status != 0) 527 { 528 (*info->memory_error_func) (status, memaddr, info); 529 return -1; 530 } 531 } 532 533 /* On SPARClite variants such as DANlite (sparc86x), instructions 534 are always big-endian even when the machine is in little-endian mode. */ 535 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) 536 getword = bfd_getb32; 537 else 538 getword = bfd_getl32; 539 540 insn = getword (buffer); 541 542 info->insn_info_valid = 1; /* We do return this info. */ 543 info->insn_type = dis_nonbranch; /* Assume non branch insn. */ 544 info->branch_delay_insns = 0; /* Assume no delay. */ 545 info->target = 0; /* Assume no target known. */ 546 547 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) 548 { 549 const sparc_opcode *opcode = op->opcode; 550 551 /* If the insn isn't supported by the current architecture, skip it. */ 552 if (! (opcode->architecture & current_arch_mask)) 553 continue; 554 555 if ((opcode->match & insn) == opcode->match 556 && (opcode->lose & insn) == 0) 557 { 558 /* Nonzero means that we have found an instruction which has 559 the effect of adding or or'ing the imm13 field to rs1. */ 560 int imm_added_to_rs1 = 0; 561 int imm_ored_to_rs1 = 0; 562 563 /* Nonzero means that we have found a plus sign in the args 564 field of the opcode table. */ 565 int found_plus = 0; 566 567 /* Nonzero means we have an annulled branch. */ 568 int is_annulled = 0; 569 570 /* Do we have an `add' or `or' instruction combining an 571 immediate with rs1? */ 572 if (opcode->match == 0x80102000) /* or */ 573 imm_ored_to_rs1 = 1; 574 if (opcode->match == 0x80002000) /* add */ 575 imm_added_to_rs1 = 1; 576 577 if (X_RS1 (insn) != X_RD (insn) 578 && strchr (opcode->args, 'r') != 0) 579 /* Can't do simple format if source and dest are different. */ 580 continue; 581 if (X_RS2 (insn) != X_RD (insn) 582 && strchr (opcode->args, 'O') != 0) 583 /* Can't do simple format if source and dest are different. */ 584 continue; 585 586 (*info->fprintf_func) (stream, "%s", opcode->name); 587 588 { 589 const char *s; 590 591 if (opcode->args[0] != ',') 592 (*info->fprintf_func) (stream, " "); 593 594 for (s = opcode->args; *s != '\0'; ++s) 595 { 596 while (*s == ',') 597 { 598 (*info->fprintf_func) (stream, ","); 599 ++s; 600 switch (*s) 601 { 602 case 'a': 603 (*info->fprintf_func) (stream, "a"); 604 is_annulled = 1; 605 ++s; 606 continue; 607 case 'N': 608 (*info->fprintf_func) (stream, "pn"); 609 ++s; 610 continue; 611 612 case 'T': 613 (*info->fprintf_func) (stream, "pt"); 614 ++s; 615 continue; 616 617 default: 618 break; 619 } 620 } 621 622 (*info->fprintf_func) (stream, " "); 623 624 switch (*s) 625 { 626 case '+': 627 found_plus = 1; 628 /* Fall through. */ 629 630 default: 631 (*info->fprintf_func) (stream, "%c", *s); 632 break; 633 634 case '#': 635 (*info->fprintf_func) (stream, "0"); 636 break; 637 638 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) 639 case '1': 640 case 'r': 641 reg (X_RS1 (insn)); 642 break; 643 644 case '2': 645 case 'O': 646 reg (X_RS2 (insn)); 647 break; 648 649 case 'd': 650 reg (X_RD (insn)); 651 break; 652 #undef reg 653 654 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) 655 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) 656 case 'e': 657 freg (X_RS1 (insn)); 658 break; 659 case 'v': /* Double/even. */ 660 case 'V': /* Quad/multiple of 4. */ 661 case ';': /* Double/even multiple of 8 doubles. */ 662 fregx (X_RS1 (insn)); 663 break; 664 665 case 'f': 666 freg (X_RS2 (insn)); 667 break; 668 case 'B': /* Double/even. */ 669 case 'R': /* Quad/multiple of 4. */ 670 case ':': /* Double/even multiple of 8 doubles. */ 671 fregx (X_RS2 (insn)); 672 break; 673 674 case '4': 675 freg (X_RS3 (insn)); 676 break; 677 case '5': /* Double/even. */ 678 fregx (X_RS3 (insn)); 679 break; 680 681 case 'g': 682 freg (X_RD (insn)); 683 break; 684 case 'H': /* Double/even. */ 685 case 'J': /* Quad/multiple of 4. */ 686 case '}': /* Double/even. */ 687 fregx (X_RD (insn)); 688 break; 689 690 case '^': /* Double/even multiple of 8 doubles. */ 691 fregx (X_RD (insn) & ~0x6); 692 break; 693 694 case '\'': /* Double/even in FPCMPSHL. */ 695 fregx (X_RS2 (insn | 0x11)); 696 break; 697 698 #undef freg 699 #undef fregx 700 701 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) 702 case 'b': 703 creg (X_RS1 (insn)); 704 break; 705 706 case 'c': 707 creg (X_RS2 (insn)); 708 break; 709 710 case 'D': 711 creg (X_RD (insn)); 712 break; 713 #undef creg 714 715 case 'h': 716 (*info->fprintf_func) (stream, "%%hi(%#x)", 717 ((unsigned) 0xFFFFFFFF 718 & ((int) X_IMM22 (insn) << 10))); 719 break; 720 721 case 'i': /* 13 bit immediate. */ 722 case 'I': /* 11 bit immediate. */ 723 case 'j': /* 10 bit immediate. */ 724 { 725 int imm; 726 727 if (*s == 'i') 728 imm = X_SIMM (insn, 13); 729 else if (*s == 'I') 730 imm = X_SIMM (insn, 11); 731 else 732 imm = X_SIMM (insn, 10); 733 734 /* Check to see whether we have a 1+i, and take 735 note of that fact. 736 737 Note: because of the way we sort the table, 738 we will be matching 1+i rather than i+1, 739 so it is OK to assume that i is after +, 740 not before it. */ 741 if (found_plus) 742 imm_added_to_rs1 = 1; 743 744 if (imm <= 9) 745 (*info->fprintf_func) (stream, "%d", imm); 746 else 747 (*info->fprintf_func) (stream, "%#x", imm); 748 } 749 break; 750 751 case ')': /* 5 bit unsigned immediate from RS3. */ 752 (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn)); 753 break; 754 755 case 'X': /* 5 bit unsigned immediate. */ 756 case 'Y': /* 6 bit unsigned immediate. */ 757 { 758 int imm = X_IMM (insn, *s == 'X' ? 5 : 6); 759 760 if (imm <= 9) 761 (info->fprintf_func) (stream, "%d", imm); 762 else 763 (info->fprintf_func) (stream, "%#x", (unsigned) imm); 764 } 765 break; 766 767 case '3': 768 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); 769 break; 770 771 case 'K': 772 { 773 int mask = X_MEMBAR (insn); 774 int bit = 0x40, printed_one = 0; 775 const char *name; 776 777 if (mask == 0) 778 (info->fprintf_func) (stream, "0"); 779 else 780 while (bit) 781 { 782 if (mask & bit) 783 { 784 if (printed_one) 785 (info->fprintf_func) (stream, "|"); 786 name = sparc_decode_membar (bit); 787 (info->fprintf_func) (stream, "%s", name); 788 printed_one = 1; 789 } 790 bit >>= 1; 791 } 792 break; 793 } 794 795 case '=': 796 info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4; 797 (*info->print_address_func) (info->target, info); 798 break; 799 800 case 'k': 801 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; 802 (*info->print_address_func) (info->target, info); 803 break; 804 805 case 'G': 806 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; 807 (*info->print_address_func) (info->target, info); 808 break; 809 810 case '6': 811 case '7': 812 case '8': 813 case '9': 814 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); 815 break; 816 817 case 'z': 818 (*info->fprintf_func) (stream, "%%icc"); 819 break; 820 821 case 'Z': 822 (*info->fprintf_func) (stream, "%%xcc"); 823 break; 824 825 case 'E': 826 (*info->fprintf_func) (stream, "%%ccr"); 827 break; 828 829 case 's': 830 (*info->fprintf_func) (stream, "%%fprs"); 831 break; 832 833 case '{': 834 (*info->fprintf_func) (stream, "%%mcdper"); 835 break; 836 837 case '&': 838 (*info->fprintf_func) (stream, "%%entropy"); 839 break; 840 841 case 'o': 842 (*info->fprintf_func) (stream, "%%asi"); 843 break; 844 845 case 'W': 846 (*info->fprintf_func) (stream, "%%tick"); 847 break; 848 849 case 'P': 850 (*info->fprintf_func) (stream, "%%pc"); 851 break; 852 853 case '?': 854 if (X_RS1 (insn) == 31) 855 (*info->fprintf_func) (stream, "%%ver"); 856 else if (X_RS1 (insn) == 23) 857 (*info->fprintf_func) (stream, "%%pmcdper"); 858 else if ((unsigned) X_RS1 (insn) < 17) 859 (*info->fprintf_func) (stream, "%%%s", 860 v9_priv_reg_names[X_RS1 (insn)]); 861 else 862 (*info->fprintf_func) (stream, "%%reserved"); 863 break; 864 865 case '!': 866 if (X_RD (insn) == 31) 867 (*info->fprintf_func) (stream, "%%ver"); 868 else if (X_RD (insn) == 23) 869 (*info->fprintf_func) (stream, "%%pmcdper"); 870 else if ((unsigned) X_RD (insn) < 17) 871 (*info->fprintf_func) (stream, "%%%s", 872 v9_priv_reg_names[X_RD (insn)]); 873 else 874 (*info->fprintf_func) (stream, "%%reserved"); 875 break; 876 877 case '$': 878 if ((unsigned) X_RS1 (insn) < 32) 879 (*info->fprintf_func) (stream, "%%%s", 880 v9_hpriv_reg_names[X_RS1 (insn)]); 881 else 882 (*info->fprintf_func) (stream, "%%reserved"); 883 break; 884 885 case '%': 886 if ((unsigned) X_RD (insn) < 32) 887 (*info->fprintf_func) (stream, "%%%s", 888 v9_hpriv_reg_names[X_RD (insn)]); 889 else 890 (*info->fprintf_func) (stream, "%%reserved"); 891 break; 892 893 case '/': 894 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28) 895 (*info->fprintf_func) (stream, "%%reserved"); 896 else 897 (*info->fprintf_func) (stream, "%%%s", 898 v9a_asr_reg_names[X_RS1 (insn)-16]); 899 break; 900 901 case '_': 902 if (X_RD (insn) < 16 || X_RD (insn) > 28) 903 (*info->fprintf_func) (stream, "%%reserved"); 904 else 905 (*info->fprintf_func) (stream, "%%%s", 906 v9a_asr_reg_names[X_RD (insn)-16]); 907 break; 908 909 case '*': 910 { 911 const char *name = sparc_decode_prefetch (X_RD (insn)); 912 913 if (name) 914 (*info->fprintf_func) (stream, "%s", name); 915 else 916 (*info->fprintf_func) (stream, "%ld", X_RD (insn)); 917 break; 918 } 919 920 case 'M': 921 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); 922 break; 923 924 case 'm': 925 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); 926 break; 927 928 case 'L': 929 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; 930 (*info->print_address_func) (info->target, info); 931 break; 932 933 case 'n': 934 (*info->fprintf_func) 935 (stream, "%#x", SEX (X_DISP22 (insn), 22)); 936 break; 937 938 case 'l': 939 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; 940 (*info->print_address_func) (info->target, info); 941 break; 942 943 case 'A': 944 { 945 const char *name = sparc_decode_asi (X_ASI (insn)); 946 947 if (name) 948 (*info->fprintf_func) (stream, "%s", name); 949 else 950 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); 951 break; 952 } 953 954 case 'C': 955 (*info->fprintf_func) (stream, "%%csr"); 956 break; 957 958 case 'F': 959 (*info->fprintf_func) (stream, "%%fsr"); 960 break; 961 962 case '(': 963 (*info->fprintf_func) (stream, "%%efsr"); 964 break; 965 966 case 'p': 967 (*info->fprintf_func) (stream, "%%psr"); 968 break; 969 970 case 'q': 971 (*info->fprintf_func) (stream, "%%fq"); 972 break; 973 974 case 'Q': 975 (*info->fprintf_func) (stream, "%%cq"); 976 break; 977 978 case 't': 979 (*info->fprintf_func) (stream, "%%tbr"); 980 break; 981 982 case 'w': 983 (*info->fprintf_func) (stream, "%%wim"); 984 break; 985 986 case 'x': 987 (*info->fprintf_func) (stream, "%ld", 988 ((X_LDST_I (insn) << 8) 989 + X_ASI (insn))); 990 break; 991 992 case '|': /* 2-bit immediate */ 993 (*info->fprintf_func) (stream, "%ld", X_IMM2 (insn)); 994 break; 995 996 case 'y': 997 (*info->fprintf_func) (stream, "%%y"); 998 break; 999 1000 case 'u': 1001 case 'U': 1002 { 1003 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); 1004 const char *name = sparc_decode_sparclet_cpreg (val); 1005 1006 if (name) 1007 (*info->fprintf_func) (stream, "%s", name); 1008 else 1009 (*info->fprintf_func) (stream, "%%cpreg(%d)", val); 1010 break; 1011 } 1012 } 1013 } 1014 } 1015 1016 /* If we are adding or or'ing something to rs1, then 1017 check to see whether the previous instruction was 1018 a sethi to the same register as in the sethi. 1019 If so, attempt to print the result of the add or 1020 or (in this context add and or do the same thing) 1021 and its symbolic value. */ 1022 if (imm_ored_to_rs1 || imm_added_to_rs1) 1023 { 1024 unsigned long prev_insn; 1025 int errcode; 1026 1027 if (memaddr >= 4) 1028 errcode = 1029 (*info->read_memory_func) 1030 (memaddr - 4, buffer, sizeof (buffer), info); 1031 else 1032 errcode = 1; 1033 1034 prev_insn = getword (buffer); 1035 1036 if (errcode == 0) 1037 { 1038 /* If it is a delayed branch, we need to look at the 1039 instruction before the delayed branch. This handles 1040 sequences such as: 1041 1042 sethi %o1, %hi(_foo), %o1 1043 call _printf 1044 or %o1, %lo(_foo), %o1 */ 1045 1046 if (is_delayed_branch (prev_insn)) 1047 { 1048 if (memaddr >= 8) 1049 errcode = (*info->read_memory_func) 1050 (memaddr - 8, buffer, sizeof (buffer), info); 1051 else 1052 errcode = 1; 1053 1054 prev_insn = getword (buffer); 1055 } 1056 } 1057 1058 /* If there was a problem reading memory, then assume 1059 the previous instruction was not sethi. */ 1060 if (errcode == 0) 1061 { 1062 /* Is it sethi to the same register? */ 1063 if ((prev_insn & 0xc1c00000) == 0x01000000 1064 && X_RD (prev_insn) == X_RS1 (insn)) 1065 { 1066 (*info->fprintf_func) (stream, "\t! "); 1067 info->target = 1068 ((unsigned) 0xFFFFFFFF 1069 & ((int) X_IMM22 (prev_insn) << 10)); 1070 if (imm_added_to_rs1) 1071 info->target += X_SIMM (insn, 13); 1072 else 1073 info->target |= X_SIMM (insn, 13); 1074 (*info->print_address_func) (info->target, info); 1075 info->insn_type = dis_dref; 1076 info->data_size = 4; /* FIXME!!! */ 1077 } 1078 } 1079 } 1080 1081 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) 1082 { 1083 /* FIXME -- check is_annulled flag. */ 1084 (void) is_annulled; 1085 if (opcode->flags & F_UNBR) 1086 info->insn_type = dis_branch; 1087 if (opcode->flags & F_CONDBR) 1088 info->insn_type = dis_condbranch; 1089 if (opcode->flags & F_JSR) 1090 info->insn_type = dis_jsr; 1091 if (opcode->flags & F_DELAYED) 1092 info->branch_delay_insns = 1; 1093 } 1094 1095 return sizeof (buffer); 1096 } 1097 } 1098 1099 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ 1100 (*info->fprintf_func) (stream, _("unknown")); 1101 return sizeof (buffer); 1102 } 1103