1 /* ppc-opc.c -- PowerPC opcode list 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 3 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of the GNU opcodes library. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the 20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include <stdio.h> 24 #include "sysdep.h" 25 #include "opcode/ppc.h" 26 #include "opintl.h" 27 28 /* This file holds the PowerPC opcode table. The opcode table 29 includes almost all of the extended instruction mnemonics. This 30 permits the disassembler to use them, and simplifies the assembler 31 logic, at the cost of increasing the table size. The table is 32 strictly constant data, so the compiler should be able to put it in 33 the .text section. 34 35 This file also holds the operand table. All knowledge about 36 inserting operands into instructions and vice-versa is kept in this 37 file. */ 38 39 /* Local insertion and extraction functions. */ 40 41 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **); 42 static long extract_bat (unsigned long, ppc_cpu_t, int *); 43 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **); 44 static long extract_bba (unsigned long, ppc_cpu_t, int *); 45 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **); 46 static long extract_bdm (unsigned long, ppc_cpu_t, int *); 47 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **); 48 static long extract_bdp (unsigned long, ppc_cpu_t, int *); 49 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **); 50 static long extract_bo (unsigned long, ppc_cpu_t, int *); 51 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **); 52 static long extract_boe (unsigned long, ppc_cpu_t, int *); 53 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); 54 static long extract_fxm (unsigned long, ppc_cpu_t, int *); 55 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); 56 static long extract_mbe (unsigned long, ppc_cpu_t, int *); 57 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **); 58 static long extract_mb6 (unsigned long, ppc_cpu_t, int *); 59 static long extract_nb (unsigned long, ppc_cpu_t, int *); 60 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **); 61 static long extract_nsi (unsigned long, ppc_cpu_t, int *); 62 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **); 63 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **); 64 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **); 65 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **); 66 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **); 67 static long extract_rbs (unsigned long, ppc_cpu_t, int *); 68 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **); 69 static long extract_sh6 (unsigned long, ppc_cpu_t, int *); 70 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **); 71 static long extract_spr (unsigned long, ppc_cpu_t, int *); 72 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **); 73 static long extract_sprg (unsigned long, ppc_cpu_t, int *); 74 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **); 75 static long extract_tbr (unsigned long, ppc_cpu_t, int *); 76 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **); 77 static long extract_xt6 (unsigned long, ppc_cpu_t, int *); 78 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **); 79 static long extract_xa6 (unsigned long, ppc_cpu_t, int *); 80 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **); 81 static long extract_xb6 (unsigned long, ppc_cpu_t, int *); 82 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **); 83 static long extract_xb6s (unsigned long, ppc_cpu_t, int *); 84 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **); 85 static long extract_xc6 (unsigned long, ppc_cpu_t, int *); 86 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **); 87 static long extract_dm (unsigned long, ppc_cpu_t, int *); 88 89 /* The operands table. 90 91 The fields are bitm, shift, insert, extract, flags. 92 93 We used to put parens around the various additions, like the one 94 for BA just below. However, that caused trouble with feeble 95 compilers with a limit on depth of a parenthesized expression, like 96 (reportedly) the compiler in Microsoft Developer Studio 5. So we 97 omit the parens, since the macros are never used in a context where 98 the addition will be ambiguous. */ 99 100 const struct powerpc_operand powerpc_operands[] = 101 { 102 /* The zero index is used to indicate the end of the list of 103 operands. */ 104 #define UNUSED 0 105 { 0, 0, NULL, NULL, 0 }, 106 107 /* The BA field in an XL form instruction. */ 108 #define BA UNUSED + 1 109 /* The BI field in a B form or XL form instruction. */ 110 #define BI BA 111 #define BI_MASK (0x1f << 16) 112 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, 113 114 /* The BA field in an XL form instruction when it must be the same 115 as the BT field in the same instruction. */ 116 #define BAT BA + 1 117 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, 118 119 /* The BB field in an XL form instruction. */ 120 #define BB BAT + 1 121 #define BB_MASK (0x1f << 11) 122 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, 123 124 /* The BB field in an XL form instruction when it must be the same 125 as the BA field in the same instruction. */ 126 #define BBA BB + 1 127 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 128 129 /* The BD field in a B form instruction. The lower two bits are 130 forced to zero. */ 131 #define BD BBA + 1 132 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 133 134 /* The BD field in a B form instruction when absolute addressing is 135 used. */ 136 #define BDA BD + 1 137 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 138 139 /* The BD field in a B form instruction when the - modifier is used. 140 This sets the y bit of the BO field appropriately. */ 141 #define BDM BDA + 1 142 { 0xfffc, 0, insert_bdm, extract_bdm, 143 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 144 145 /* The BD field in a B form instruction when the - modifier is used 146 and absolute address is used. */ 147 #define BDMA BDM + 1 148 { 0xfffc, 0, insert_bdm, extract_bdm, 149 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 150 151 /* The BD field in a B form instruction when the + modifier is used. 152 This sets the y bit of the BO field appropriately. */ 153 #define BDP BDMA + 1 154 { 0xfffc, 0, insert_bdp, extract_bdp, 155 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 156 157 /* The BD field in a B form instruction when the + modifier is used 158 and absolute addressing is used. */ 159 #define BDPA BDP + 1 160 { 0xfffc, 0, insert_bdp, extract_bdp, 161 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 162 163 /* The BF field in an X or XL form instruction. */ 164 #define BF BDPA + 1 165 /* The CRFD field in an X form instruction. */ 166 #define CRFD BF 167 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, 168 169 /* The BF field in an X or XL form instruction. */ 170 #define BFF BF + 1 171 { 0x7, 23, NULL, NULL, 0 }, 172 173 /* An optional BF field. This is used for comparison instructions, 174 in which an omitted BF field is taken as zero. */ 175 #define OBF BFF + 1 176 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 177 178 /* The BFA field in an X or XL form instruction. */ 179 #define BFA OBF + 1 180 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, 181 182 /* The BO field in a B form instruction. Certain values are 183 illegal. */ 184 #define BO BFA + 1 185 #define BO_MASK (0x1f << 21) 186 { 0x1f, 21, insert_bo, extract_bo, 0 }, 187 188 /* The BO field in a B form instruction when the + or - modifier is 189 used. This is like the BO field, but it must be even. */ 190 #define BOE BO + 1 191 { 0x1e, 21, insert_boe, extract_boe, 0 }, 192 193 #define BH BOE + 1 194 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 195 196 /* The BT field in an X or XL form instruction. */ 197 #define BT BH + 1 198 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, 199 200 /* The condition register number portion of the BI field in a B form 201 or XL form instruction. This is used for the extended 202 conditional branch mnemonics, which set the lower two bits of the 203 BI field. This field is optional. */ 204 #define CR BT + 1 205 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 206 207 /* The CRB field in an X form instruction. */ 208 #define CRB CR + 1 209 /* The MB field in an M form instruction. */ 210 #define MB CRB 211 #define MB_MASK (0x1f << 6) 212 { 0x1f, 6, NULL, NULL, 0 }, 213 214 /* The CRFS field in an X form instruction. */ 215 #define CRFS CRB + 1 216 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, 217 218 /* The CT field in an X form instruction. */ 219 #define CT CRFS + 1 220 /* The MO field in an mbar instruction. */ 221 #define MO CT 222 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 223 224 /* The D field in a D form instruction. This is a displacement off 225 a register, and implies that the next operand is a register in 226 parentheses. */ 227 #define D CT + 1 228 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 229 230 /* The DQ field in a DQ form instruction. This is like D, but the 231 lower four bits are forced to zero. */ 232 #define DQ D + 1 233 { 0xfff0, 0, NULL, NULL, 234 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 235 236 /* The DS field in a DS form instruction. This is like D, but the 237 lower two bits are forced to zero. */ 238 #define DS DQ + 1 239 { 0xfffc, 0, NULL, NULL, 240 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 241 242 /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */ 243 #define DUIS DS + 1 244 { 0x3ff, 11, NULL, NULL, 0 }, 245 246 /* The E field in a wrteei instruction. */ 247 /* And the W bit in the pair singles instructions. */ 248 #define E DUIS + 1 249 #define PSW E 250 { 0x1, 15, NULL, NULL, 0 }, 251 252 /* The FL1 field in a POWER SC form instruction. */ 253 #define FL1 E + 1 254 /* The U field in an X form instruction. */ 255 #define U FL1 256 { 0xf, 12, NULL, NULL, 0 }, 257 258 /* The FL2 field in a POWER SC form instruction. */ 259 #define FL2 FL1 + 1 260 { 0x7, 2, NULL, NULL, 0 }, 261 262 /* The FLM field in an XFL form instruction. */ 263 #define FLM FL2 + 1 264 { 0xff, 17, NULL, NULL, 0 }, 265 266 /* The FRA field in an X or A form instruction. */ 267 #define FRA FLM + 1 268 #define FRA_MASK (0x1f << 16) 269 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, 270 271 /* The FRB field in an X or A form instruction. */ 272 #define FRB FRA + 1 273 #define FRB_MASK (0x1f << 11) 274 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, 275 276 /* The FRC field in an A form instruction. */ 277 #define FRC FRB + 1 278 #define FRC_MASK (0x1f << 6) 279 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, 280 281 /* The FRS field in an X form instruction or the FRT field in a D, X 282 or A form instruction. */ 283 #define FRS FRC + 1 284 #define FRT FRS 285 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, 286 287 /* The FXM field in an XFX instruction. */ 288 #define FXM FRS + 1 289 { 0xff, 12, insert_fxm, extract_fxm, 0 }, 290 291 /* Power4 version for mfcr. */ 292 #define FXM4 FXM + 1 293 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, 294 295 /* The L field in a D or X form instruction. */ 296 #define L FXM4 + 1 297 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 298 299 /* The LEV field in a POWER SVC form instruction. */ 300 #define SVC_LEV L + 1 301 { 0x7f, 5, NULL, NULL, 0 }, 302 303 /* The LEV field in an SC form instruction. */ 304 #define LEV SVC_LEV + 1 305 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, 306 307 /* The LI field in an I form instruction. The lower two bits are 308 forced to zero. */ 309 #define LI LEV + 1 310 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 311 312 /* The LI field in an I form instruction when used as an absolute 313 address. */ 314 #define LIA LI + 1 315 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 316 317 /* The LS or WC field in an X (sync or wait) form instruction. */ 318 #define LS LIA + 1 319 #define WC LS 320 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 321 322 /* The ME field in an M form instruction. */ 323 #define ME LS + 1 324 #define ME_MASK (0x1f << 1) 325 { 0x1f, 1, NULL, NULL, 0 }, 326 327 /* The MB and ME fields in an M form instruction expressed a single 328 operand which is a bitmask indicating which bits to select. This 329 is a two operand form using PPC_OPERAND_NEXT. See the 330 description in opcode/ppc.h for what this means. */ 331 #define MBE ME + 1 332 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 333 { -1, 0, insert_mbe, extract_mbe, 0 }, 334 335 /* The MB or ME field in an MD or MDS form instruction. The high 336 bit is wrapped to the low end. */ 337 #define MB6 MBE + 2 338 #define ME6 MB6 339 #define MB6_MASK (0x3f << 5) 340 { 0x3f, 5, insert_mb6, extract_mb6, 0 }, 341 342 /* The NB field in an X form instruction. The value 32 is stored as 343 0. */ 344 #define NB MB6 + 1 345 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, 346 347 /* The NSI field in a D form instruction. This is the same as the 348 SI field, only negated. */ 349 #define NSI NB + 1 350 { 0xffff, 0, insert_nsi, extract_nsi, 351 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 352 353 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 354 #define RA NSI + 1 355 #define RA_MASK (0x1f << 16) 356 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, 357 358 /* As above, but 0 in the RA field means zero, not r0. */ 359 #define RA0 RA + 1 360 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 361 362 /* The RA field in the DQ form lq instruction, which has special 363 value restrictions. */ 364 #define RAQ RA0 + 1 365 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, 366 367 /* The RA field in a D or X form instruction which is an updating 368 load, which means that the RA field may not be zero and may not 369 equal the RT field. */ 370 #define RAL RAQ + 1 371 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, 372 373 /* The RA field in an lmw instruction, which has special value 374 restrictions. */ 375 #define RAM RAL + 1 376 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, 377 378 /* The RA field in a D or X form instruction which is an updating 379 store or an updating floating point load, which means that the RA 380 field may not be zero. */ 381 #define RAS RAM + 1 382 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, 383 384 /* The RA field of the tlbwe instruction, which is optional. */ 385 #define RAOPT RAS + 1 386 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 387 388 /* The RB field in an X, XO, M, or MDS form instruction. */ 389 #define RB RAOPT + 1 390 #define RB_MASK (0x1f << 11) 391 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, 392 393 /* The RB field in an X form instruction when it must be the same as 394 the RS field in the instruction. This is used for extended 395 mnemonics like mr. */ 396 #define RBS RB + 1 397 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 398 399 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 400 instruction or the RT field in a D, DS, X, XFX or XO form 401 instruction. */ 402 #define RS RBS + 1 403 #define RT RS 404 #define RT_MASK (0x1f << 21) 405 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, 406 407 /* The RS and RT fields of the DS form stq instruction, which have 408 special value restrictions. */ 409 #define RSQ RS + 1 410 #define RTQ RSQ 411 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 }, 412 413 /* The RS field of the tlbwe instruction, which is optional. */ 414 #define RSO RSQ + 1 415 #define RTO RSO 416 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 417 418 /* The SH field in an X or M form instruction. */ 419 #define SH RSO + 1 420 #define SH_MASK (0x1f << 11) 421 /* The other UIMM field in a EVX form instruction. */ 422 #define EVUIMM SH 423 { 0x1f, 11, NULL, NULL, 0 }, 424 425 /* The SH field in an MD form instruction. This is split. */ 426 #define SH6 SH + 1 427 #define SH6_MASK ((0x1f << 11) | (1 << 1)) 428 { 0x3f, -1, insert_sh6, extract_sh6, 0 }, 429 430 /* The SH field of the tlbwe instruction, which is optional. */ 431 #define SHO SH6 + 1 432 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 433 434 /* The SI field in a D form instruction. */ 435 #define SI SHO + 1 436 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 437 438 /* The SI field in a D form instruction when we accept a wide range 439 of positive values. */ 440 #define SISIGNOPT SI + 1 441 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 442 443 /* The SPR field in an XFX form instruction. This is flipped--the 444 lower 5 bits are stored in the upper 5 and vice- versa. */ 445 #define SPR SISIGNOPT + 1 446 #define PMR SPR 447 #define SPR_MASK (0x3ff << 11) 448 { 0x3ff, 11, insert_spr, extract_spr, 0 }, 449 450 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 451 #define SPRBAT SPR + 1 452 #define SPRBAT_MASK (0x3 << 17) 453 { 0x3, 17, NULL, NULL, 0 }, 454 455 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 456 #define SPRG SPRBAT + 1 457 { 0x1f, 16, insert_sprg, extract_sprg, 0 }, 458 459 /* The SR field in an X form instruction. */ 460 #define SR SPRG + 1 461 { 0xf, 16, NULL, NULL, 0 }, 462 463 /* The STRM field in an X AltiVec form instruction. */ 464 #define STRM SR + 1 465 /* The T field in a tlbilx form instruction. */ 466 #define T STRM 467 { 0x3, 21, NULL, NULL, 0 }, 468 469 /* The SV field in a POWER SC form instruction. */ 470 #define SV STRM + 1 471 { 0x3fff, 2, NULL, NULL, 0 }, 472 473 /* The TBR field in an XFX form instruction. This is like the SPR 474 field, but it is optional. */ 475 #define TBR SV + 1 476 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, 477 478 /* The TO field in a D or X form instruction. */ 479 #define TO TBR + 1 480 #define DUI TO 481 #define TO_MASK (0x1f << 21) 482 { 0x1f, 21, NULL, NULL, 0 }, 483 484 /* The UI field in a D form instruction. */ 485 #define UI TO + 1 486 { 0xffff, 0, NULL, NULL, 0 }, 487 488 /* The VA field in a VA, VX or VXR form instruction. */ 489 #define VA UI + 1 490 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, 491 492 /* The VB field in a VA, VX or VXR form instruction. */ 493 #define VB VA + 1 494 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, 495 496 /* The VC field in a VA form instruction. */ 497 #define VC VB + 1 498 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, 499 500 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 501 #define VD VC + 1 502 #define VS VD 503 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, 504 505 /* The SIMM field in a VX form instruction, and TE in Z form. */ 506 #define SIMM VD + 1 507 #define TE SIMM 508 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 509 510 /* The UIMM field in a VX form instruction. */ 511 #define UIMM SIMM + 1 512 { 0x1f, 16, NULL, NULL, 0 }, 513 514 /* The SHB field in a VA form instruction. */ 515 #define SHB UIMM + 1 516 { 0xf, 6, NULL, NULL, 0 }, 517 518 /* The other UIMM field in a half word EVX form instruction. */ 519 #define EVUIMM_2 SHB + 1 520 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, 521 522 /* The other UIMM field in a word EVX form instruction. */ 523 #define EVUIMM_4 EVUIMM_2 + 1 524 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, 525 526 /* The other UIMM field in a double EVX form instruction. */ 527 #define EVUIMM_8 EVUIMM_4 + 1 528 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, 529 530 /* The WS field. */ 531 #define WS EVUIMM_8 + 1 532 { 0x7, 11, NULL, NULL, 0 }, 533 534 /* PowerPC paired singles extensions. */ 535 /* W bit in the pair singles instructions for x type instructions. */ 536 #define PSWM WS + 1 537 { 0x1, 10, 0, 0, 0 }, 538 539 /* IDX bits for quantization in the pair singles instructions. */ 540 #define PSQ PSWM + 1 541 { 0x7, 12, 0, 0, 0 }, 542 543 /* IDX bits for quantization in the pair singles x-type instructions. */ 544 #define PSQM PSQ + 1 545 { 0x7, 7, 0, 0, 0 }, 546 547 /* Smaller D field for quantization in the pair singles instructions. */ 548 #define PSD PSQM + 1 549 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 550 551 #define A_L PSD + 1 552 #define W A_L 553 #define MTMSRD_L W 554 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 555 556 #define RMC MTMSRD_L + 1 557 { 0x3, 9, NULL, NULL, 0 }, 558 559 #define R RMC + 1 560 { 0x1, 16, NULL, NULL, 0 }, 561 562 #define SP R + 1 563 { 0x3, 19, NULL, NULL, 0 }, 564 565 #define S SP + 1 566 { 0x1, 20, NULL, NULL, 0 }, 567 568 /* SH field starting at bit position 16. */ 569 #define SH16 S + 1 570 /* The DCM and DGM fields in a Z form instruction. */ 571 #define DCM SH16 572 #define DGM DCM 573 { 0x3f, 10, NULL, NULL, 0 }, 574 575 /* The EH field in larx instruction. */ 576 #define EH SH16 + 1 577 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, 578 579 /* The L field in an mtfsf or XFL form instruction. */ 580 #define XFL_L EH + 1 581 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, 582 583 /* Xilinx APU related masks and macros */ 584 #define FCRT XFL_L + 1 585 #define FCRT_MASK (0x1f << 21) 586 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, 587 588 /* Xilinx FSL related masks and macros */ 589 #define FSL FCRT + 1 590 #define FSL_MASK (0x1f << 11) 591 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, 592 593 /* Xilinx UDI related masks and macros */ 594 #define URT FSL + 1 595 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, 596 597 #define URA URT + 1 598 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, 599 600 #define URB URA + 1 601 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, 602 603 #define URC URB + 1 604 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, 605 606 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ 607 #define XS6 URC + 1 608 #define XT6 XS6 609 { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, 610 611 /* The XA field in an XX3 form instruction. This is split. */ 612 #define XA6 XT6 + 1 613 { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, 614 615 /* The XB field in an XX2 or XX3 form instruction. This is split. */ 616 #define XB6 XA6 + 1 617 { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, 618 619 /* The XB field in an XX3 form instruction when it must be the same as 620 the XA field in the instruction. This is used in extended mnemonics 621 like xvmovdp. This is split. */ 622 #define XB6S XB6 + 1 623 { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, 624 625 /* The XC field in an XX4 form instruction. This is split. */ 626 #define XC6 XB6S + 1 627 { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, 628 629 /* The DM or SHW field in an XX3 form instruction. */ 630 #define DM XC6 + 1 631 #define SHW DM 632 { 0x3, 8, NULL, NULL, 0 }, 633 634 /* The DM field in an extended mnemonic XX3 form instruction. */ 635 #define DMEX DM + 1 636 { 0x3, 8, insert_dm, extract_dm, 0 }, 637 638 /* The UIM field in an XX2 form instruction. */ 639 #define UIM DMEX + 1 640 { 0x3, 16, NULL, NULL, 0 }, 641 }; 642 643 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) 644 / sizeof (powerpc_operands[0])); 645 646 /* The functions used to insert and extract complicated operands. */ 647 648 /* The BA field in an XL form instruction when it must be the same as 649 the BT field in the same instruction. This operand is marked FAKE. 650 The insertion function just copies the BT field into the BA field, 651 and the extraction function just checks that the fields are the 652 same. */ 653 654 static unsigned long 655 insert_bat (unsigned long insn, 656 long value ATTRIBUTE_UNUSED, 657 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 658 const char **errmsg ATTRIBUTE_UNUSED) 659 { 660 return insn | (((insn >> 21) & 0x1f) << 16); 661 } 662 663 static long 664 extract_bat (unsigned long insn, 665 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 666 int *invalid) 667 { 668 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 669 *invalid = 1; 670 return 0; 671 } 672 673 /* The BB field in an XL form instruction when it must be the same as 674 the BA field in the same instruction. This operand is marked FAKE. 675 The insertion function just copies the BA field into the BB field, 676 and the extraction function just checks that the fields are the 677 same. */ 678 679 static unsigned long 680 insert_bba (unsigned long insn, 681 long value ATTRIBUTE_UNUSED, 682 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 683 const char **errmsg ATTRIBUTE_UNUSED) 684 { 685 return insn | (((insn >> 16) & 0x1f) << 11); 686 } 687 688 static long 689 extract_bba (unsigned long insn, 690 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 691 int *invalid) 692 { 693 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 694 *invalid = 1; 695 return 0; 696 } 697 698 /* The BD field in a B form instruction when the - modifier is used. 699 This modifier means that the branch is not expected to be taken. 700 For chips built to versions of the architecture prior to version 2 701 (ie. not Power4 compatible), we set the y bit of the BO field to 1 702 if the offset is negative. When extracting, we require that the y 703 bit be 1 and that the offset be positive, since if the y bit is 0 704 we just want to print the normal form of the instruction. 705 Power4 compatible targets use two bits, "a", and "t", instead of 706 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 707 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 708 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 709 for branch on CTR. We only handle the taken/not-taken hint here. 710 Note that we don't relax the conditions tested here when 711 disassembling with -Many because insns using extract_bdm and 712 extract_bdp always occur in pairs. One or the other will always 713 be valid. */ 714 715 static unsigned long 716 insert_bdm (unsigned long insn, 717 long value, 718 ppc_cpu_t dialect, 719 const char **errmsg ATTRIBUTE_UNUSED) 720 { 721 if ((dialect & PPC_OPCODE_POWER4) == 0) 722 { 723 if ((value & 0x8000) != 0) 724 insn |= 1 << 21; 725 } 726 else 727 { 728 if ((insn & (0x14 << 21)) == (0x04 << 21)) 729 insn |= 0x02 << 21; 730 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 731 insn |= 0x08 << 21; 732 } 733 return insn | (value & 0xfffc); 734 } 735 736 static long 737 extract_bdm (unsigned long insn, 738 ppc_cpu_t dialect, 739 int *invalid) 740 { 741 if ((dialect & PPC_OPCODE_POWER4) == 0) 742 { 743 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 744 *invalid = 1; 745 } 746 else 747 { 748 if ((insn & (0x17 << 21)) != (0x06 << 21) 749 && (insn & (0x1d << 21)) != (0x18 << 21)) 750 *invalid = 1; 751 } 752 753 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 754 } 755 756 /* The BD field in a B form instruction when the + modifier is used. 757 This is like BDM, above, except that the branch is expected to be 758 taken. */ 759 760 static unsigned long 761 insert_bdp (unsigned long insn, 762 long value, 763 ppc_cpu_t dialect, 764 const char **errmsg ATTRIBUTE_UNUSED) 765 { 766 if ((dialect & PPC_OPCODE_POWER4) == 0) 767 { 768 if ((value & 0x8000) == 0) 769 insn |= 1 << 21; 770 } 771 else 772 { 773 if ((insn & (0x14 << 21)) == (0x04 << 21)) 774 insn |= 0x03 << 21; 775 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 776 insn |= 0x09 << 21; 777 } 778 return insn | (value & 0xfffc); 779 } 780 781 static long 782 extract_bdp (unsigned long insn, 783 ppc_cpu_t dialect, 784 int *invalid) 785 { 786 if ((dialect & PPC_OPCODE_POWER4) == 0) 787 { 788 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 789 *invalid = 1; 790 } 791 else 792 { 793 if ((insn & (0x17 << 21)) != (0x07 << 21) 794 && (insn & (0x1d << 21)) != (0x19 << 21)) 795 *invalid = 1; 796 } 797 798 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 799 } 800 801 /* Check for legal values of a BO field. */ 802 803 static int 804 valid_bo (long value, ppc_cpu_t dialect, int extract) 805 { 806 if ((dialect & PPC_OPCODE_POWER4) == 0) 807 { 808 int valid; 809 /* Certain encodings have bits that are required to be zero. 810 These are (z must be zero, y may be anything): 811 001zy 812 011zy 813 1z00y 814 1z01y 815 1z1zz 816 */ 817 switch (value & 0x14) 818 { 819 default: 820 case 0: 821 valid = 1; 822 break; 823 case 0x4: 824 valid = (value & 0x2) == 0; 825 break; 826 case 0x10: 827 valid = (value & 0x8) == 0; 828 break; 829 case 0x14: 830 valid = value == 0x14; 831 break; 832 } 833 /* When disassembling with -Many, accept power4 encodings too. */ 834 if (valid 835 || (dialect & PPC_OPCODE_ANY) == 0 836 || !extract) 837 return valid; 838 } 839 840 /* Certain encodings have bits that are required to be zero. 841 These are (z must be zero, a & t may be anything): 842 0000z 843 0001z 844 0100z 845 0101z 846 001at 847 011at 848 1a00t 849 1a01t 850 1z1zz 851 */ 852 if ((value & 0x14) == 0) 853 return (value & 0x1) == 0; 854 else if ((value & 0x14) == 0x14) 855 return value == 0x14; 856 else 857 return 1; 858 } 859 860 /* The BO field in a B form instruction. Warn about attempts to set 861 the field to an illegal value. */ 862 863 static unsigned long 864 insert_bo (unsigned long insn, 865 long value, 866 ppc_cpu_t dialect, 867 const char **errmsg) 868 { 869 if (!valid_bo (value, dialect, 0)) 870 *errmsg = _("invalid conditional option"); 871 return insn | ((value & 0x1f) << 21); 872 } 873 874 static long 875 extract_bo (unsigned long insn, 876 ppc_cpu_t dialect, 877 int *invalid) 878 { 879 long value; 880 881 value = (insn >> 21) & 0x1f; 882 if (!valid_bo (value, dialect, 1)) 883 *invalid = 1; 884 return value; 885 } 886 887 /* The BO field in a B form instruction when the + or - modifier is 888 used. This is like the BO field, but it must be even. When 889 extracting it, we force it to be even. */ 890 891 static unsigned long 892 insert_boe (unsigned long insn, 893 long value, 894 ppc_cpu_t dialect, 895 const char **errmsg) 896 { 897 if (!valid_bo (value, dialect, 0)) 898 *errmsg = _("invalid conditional option"); 899 else if ((value & 1) != 0) 900 *errmsg = _("attempt to set y bit when using + or - modifier"); 901 902 return insn | ((value & 0x1f) << 21); 903 } 904 905 static long 906 extract_boe (unsigned long insn, 907 ppc_cpu_t dialect, 908 int *invalid) 909 { 910 long value; 911 912 value = (insn >> 21) & 0x1f; 913 if (!valid_bo (value, dialect, 1)) 914 *invalid = 1; 915 return value & 0x1e; 916 } 917 918 /* FXM mask in mfcr and mtcrf instructions. */ 919 920 static unsigned long 921 insert_fxm (unsigned long insn, 922 long value, 923 ppc_cpu_t dialect, 924 const char **errmsg) 925 { 926 /* If we're handling the mfocrf and mtocrf insns ensure that exactly 927 one bit of the mask field is set. */ 928 if ((insn & (1 << 20)) != 0) 929 { 930 if (value == 0 || (value & -value) != value) 931 { 932 *errmsg = _("invalid mask field"); 933 value = 0; 934 } 935 } 936 937 /* If the optional field on mfcr is missing that means we want to use 938 the old form of the instruction that moves the whole cr. In that 939 case we'll have VALUE zero. There doesn't seem to be a way to 940 distinguish this from the case where someone writes mfcr %r3,0. */ 941 else if (value == 0) 942 ; 943 944 /* If only one bit of the FXM field is set, we can use the new form 945 of the instruction, which is faster. Unlike the Power4 branch hint 946 encoding, this is not backward compatible. Do not generate the 947 new form unless -mpower4 has been given, or -many and the two 948 operand form of mfcr was used. */ 949 else if ((value & -value) == value 950 && ((dialect & PPC_OPCODE_POWER4) != 0 951 || ((dialect & PPC_OPCODE_ANY) != 0 952 && (insn & (0x3ff << 1)) == 19 << 1))) 953 insn |= 1 << 20; 954 955 /* Any other value on mfcr is an error. */ 956 else if ((insn & (0x3ff << 1)) == 19 << 1) 957 { 958 *errmsg = _("ignoring invalid mfcr mask"); 959 value = 0; 960 } 961 962 return insn | ((value & 0xff) << 12); 963 } 964 965 static long 966 extract_fxm (unsigned long insn, 967 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 968 int *invalid) 969 { 970 long mask = (insn >> 12) & 0xff; 971 972 /* Is this a Power4 insn? */ 973 if ((insn & (1 << 20)) != 0) 974 { 975 /* Exactly one bit of MASK should be set. */ 976 if (mask == 0 || (mask & -mask) != mask) 977 *invalid = 1; 978 } 979 980 /* Check that non-power4 form of mfcr has a zero MASK. */ 981 else if ((insn & (0x3ff << 1)) == 19 << 1) 982 { 983 if (mask != 0) 984 *invalid = 1; 985 } 986 987 return mask; 988 } 989 990 /* The MB and ME fields in an M form instruction expressed as a single 991 operand which is itself a bitmask. The extraction function always 992 marks it as invalid, since we never want to recognize an 993 instruction which uses a field of this type. */ 994 995 static unsigned long 996 insert_mbe (unsigned long insn, 997 long value, 998 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 999 const char **errmsg) 1000 { 1001 unsigned long uval, mask; 1002 int mb, me, mx, count, last; 1003 1004 uval = value; 1005 1006 if (uval == 0) 1007 { 1008 *errmsg = _("illegal bitmask"); 1009 return insn; 1010 } 1011 1012 mb = 0; 1013 me = 32; 1014 if ((uval & 1) != 0) 1015 last = 1; 1016 else 1017 last = 0; 1018 count = 0; 1019 1020 /* mb: location of last 0->1 transition */ 1021 /* me: location of last 1->0 transition */ 1022 /* count: # transitions */ 1023 1024 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) 1025 { 1026 if ((uval & mask) && !last) 1027 { 1028 ++count; 1029 mb = mx; 1030 last = 1; 1031 } 1032 else if (!(uval & mask) && last) 1033 { 1034 ++count; 1035 me = mx; 1036 last = 0; 1037 } 1038 } 1039 if (me == 0) 1040 me = 32; 1041 1042 if (count != 2 && (count != 0 || ! last)) 1043 *errmsg = _("illegal bitmask"); 1044 1045 return insn | (mb << 6) | ((me - 1) << 1); 1046 } 1047 1048 static long 1049 extract_mbe (unsigned long insn, 1050 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1051 int *invalid) 1052 { 1053 long ret; 1054 int mb, me; 1055 int i; 1056 1057 *invalid = 1; 1058 1059 mb = (insn >> 6) & 0x1f; 1060 me = (insn >> 1) & 0x1f; 1061 if (mb < me + 1) 1062 { 1063 ret = 0; 1064 for (i = mb; i <= me; i++) 1065 ret |= 1L << (31 - i); 1066 } 1067 else if (mb == me + 1) 1068 ret = ~0; 1069 else /* (mb > me + 1) */ 1070 { 1071 ret = ~0; 1072 for (i = me + 1; i < mb; i++) 1073 ret &= ~(1L << (31 - i)); 1074 } 1075 return ret; 1076 } 1077 1078 /* The MB or ME field in an MD or MDS form instruction. The high bit 1079 is wrapped to the low end. */ 1080 1081 static unsigned long 1082 insert_mb6 (unsigned long insn, 1083 long value, 1084 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1085 const char **errmsg ATTRIBUTE_UNUSED) 1086 { 1087 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1088 } 1089 1090 static long 1091 extract_mb6 (unsigned long insn, 1092 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1093 int *invalid ATTRIBUTE_UNUSED) 1094 { 1095 return ((insn >> 6) & 0x1f) | (insn & 0x20); 1096 } 1097 1098 /* The NB field in an X form instruction. The value 32 is stored as 1099 0. */ 1100 1101 static long 1102 extract_nb (unsigned long insn, 1103 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1104 int *invalid ATTRIBUTE_UNUSED) 1105 { 1106 long ret; 1107 1108 ret = (insn >> 11) & 0x1f; 1109 if (ret == 0) 1110 ret = 32; 1111 return ret; 1112 } 1113 1114 /* The NSI field in a D form instruction. This is the same as the SI 1115 field, only negated. The extraction function always marks it as 1116 invalid, since we never want to recognize an instruction which uses 1117 a field of this type. */ 1118 1119 static unsigned long 1120 insert_nsi (unsigned long insn, 1121 long value, 1122 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1123 const char **errmsg ATTRIBUTE_UNUSED) 1124 { 1125 return insn | (-value & 0xffff); 1126 } 1127 1128 static long 1129 extract_nsi (unsigned long insn, 1130 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1131 int *invalid) 1132 { 1133 *invalid = 1; 1134 return -(((insn & 0xffff) ^ 0x8000) - 0x8000); 1135 } 1136 1137 /* The RA field in a D or X form instruction which is an updating 1138 load, which means that the RA field may not be zero and may not 1139 equal the RT field. */ 1140 1141 static unsigned long 1142 insert_ral (unsigned long insn, 1143 long value, 1144 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1145 const char **errmsg) 1146 { 1147 if (value == 0 1148 || (unsigned long) value == ((insn >> 21) & 0x1f)) 1149 *errmsg = "invalid register operand when updating"; 1150 return insn | ((value & 0x1f) << 16); 1151 } 1152 1153 /* The RA field in an lmw instruction, which has special value 1154 restrictions. */ 1155 1156 static unsigned long 1157 insert_ram (unsigned long insn, 1158 long value, 1159 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1160 const char **errmsg) 1161 { 1162 if ((unsigned long) value >= ((insn >> 21) & 0x1f)) 1163 *errmsg = _("index register in load range"); 1164 return insn | ((value & 0x1f) << 16); 1165 } 1166 1167 /* The RA field in the DQ form lq instruction, which has special 1168 value restrictions. */ 1169 1170 static unsigned long 1171 insert_raq (unsigned long insn, 1172 long value, 1173 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1174 const char **errmsg) 1175 { 1176 long rtvalue = (insn & RT_MASK) >> 21; 1177 1178 if (value == rtvalue) 1179 *errmsg = _("source and target register operands must be different"); 1180 return insn | ((value & 0x1f) << 16); 1181 } 1182 1183 /* The RA field in a D or X form instruction which is an updating 1184 store or an updating floating point load, which means that the RA 1185 field may not be zero. */ 1186 1187 static unsigned long 1188 insert_ras (unsigned long insn, 1189 long value, 1190 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1191 const char **errmsg) 1192 { 1193 if (value == 0) 1194 *errmsg = _("invalid register operand when updating"); 1195 return insn | ((value & 0x1f) << 16); 1196 } 1197 1198 /* The RB field in an X form instruction when it must be the same as 1199 the RS field in the instruction. This is used for extended 1200 mnemonics like mr. This operand is marked FAKE. The insertion 1201 function just copies the BT field into the BA field, and the 1202 extraction function just checks that the fields are the same. */ 1203 1204 static unsigned long 1205 insert_rbs (unsigned long insn, 1206 long value ATTRIBUTE_UNUSED, 1207 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1208 const char **errmsg ATTRIBUTE_UNUSED) 1209 { 1210 return insn | (((insn >> 21) & 0x1f) << 11); 1211 } 1212 1213 static long 1214 extract_rbs (unsigned long insn, 1215 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1216 int *invalid) 1217 { 1218 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) 1219 *invalid = 1; 1220 return 0; 1221 } 1222 1223 /* The SH field in an MD form instruction. This is split. */ 1224 1225 static unsigned long 1226 insert_sh6 (unsigned long insn, 1227 long value, 1228 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1229 const char **errmsg ATTRIBUTE_UNUSED) 1230 { 1231 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1232 } 1233 1234 static long 1235 extract_sh6 (unsigned long insn, 1236 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1237 int *invalid ATTRIBUTE_UNUSED) 1238 { 1239 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 1240 } 1241 1242 /* The SPR field in an XFX form instruction. This is flipped--the 1243 lower 5 bits are stored in the upper 5 and vice- versa. */ 1244 1245 static unsigned long 1246 insert_spr (unsigned long insn, 1247 long value, 1248 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1249 const char **errmsg ATTRIBUTE_UNUSED) 1250 { 1251 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1252 } 1253 1254 static long 1255 extract_spr (unsigned long insn, 1256 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1257 int *invalid ATTRIBUTE_UNUSED) 1258 { 1259 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1260 } 1261 1262 /* Some dialects have 8 SPRG registers instead of the standard 4. */ 1263 1264 static unsigned long 1265 insert_sprg (unsigned long insn, 1266 long value, 1267 ppc_cpu_t dialect, 1268 const char **errmsg) 1269 { 1270 if (value > 7 1271 || (value > 3 1272 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)) 1273 *errmsg = _("invalid sprg number"); 1274 1275 /* If this is mfsprg4..7 then use spr 260..263 which can be read in 1276 user mode. Anything else must use spr 272..279. */ 1277 if (value <= 3 || (insn & 0x100) != 0) 1278 value |= 0x10; 1279 1280 return insn | ((value & 0x17) << 16); 1281 } 1282 1283 static long 1284 extract_sprg (unsigned long insn, 1285 ppc_cpu_t dialect, 1286 int *invalid) 1287 { 1288 unsigned long val = (insn >> 16) & 0x1f; 1289 1290 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 1291 If not BOOKE or 405, then both use only 272..275. */ 1292 if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0) 1293 || (val - 0x10 > 7 && (insn & 0x100) != 0) 1294 || val <= 3 1295 || (val & 8) != 0) 1296 *invalid = 1; 1297 return val & 7; 1298 } 1299 1300 /* The TBR field in an XFX instruction. This is just like SPR, but it 1301 is optional. When TBR is omitted, it must be inserted as 268 (the 1302 magic number of the TB register). These functions treat 0 1303 (indicating an omitted optional operand) as 268. This means that 1304 ``mftb 4,0'' is not handled correctly. This does not matter very 1305 much, since the architecture manual does not define mftb as 1306 accepting any values other than 268 or 269. */ 1307 1308 #define TB (268) 1309 1310 static unsigned long 1311 insert_tbr (unsigned long insn, 1312 long value, 1313 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1314 const char **errmsg ATTRIBUTE_UNUSED) 1315 { 1316 if (value == 0) 1317 value = TB; 1318 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1319 } 1320 1321 static long 1322 extract_tbr (unsigned long insn, 1323 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1324 int *invalid ATTRIBUTE_UNUSED) 1325 { 1326 long ret; 1327 1328 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1329 if (ret == TB) 1330 ret = 0; 1331 return ret; 1332 } 1333 1334 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ 1335 1336 static unsigned long 1337 insert_xt6 (unsigned long insn, 1338 long value, 1339 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1340 const char **errmsg ATTRIBUTE_UNUSED) 1341 { 1342 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); 1343 } 1344 1345 static long 1346 extract_xt6 (unsigned long insn, 1347 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1348 int *invalid ATTRIBUTE_UNUSED) 1349 { 1350 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); 1351 } 1352 1353 /* The XA field in an XX3 form instruction. This is split. */ 1354 1355 static unsigned long 1356 insert_xa6 (unsigned long insn, 1357 long value, 1358 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1359 const char **errmsg ATTRIBUTE_UNUSED) 1360 { 1361 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); 1362 } 1363 1364 static long 1365 extract_xa6 (unsigned long insn, 1366 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1367 int *invalid ATTRIBUTE_UNUSED) 1368 { 1369 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); 1370 } 1371 1372 /* The XB field in an XX3 form instruction. This is split. */ 1373 1374 static unsigned long 1375 insert_xb6 (unsigned long insn, 1376 long value, 1377 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1378 const char **errmsg ATTRIBUTE_UNUSED) 1379 { 1380 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1381 } 1382 1383 static long 1384 extract_xb6 (unsigned long insn, 1385 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1386 int *invalid ATTRIBUTE_UNUSED) 1387 { 1388 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); 1389 } 1390 1391 /* The XB field in an XX3 form instruction when it must be the same as 1392 the XA field in the instruction. This is used for extended 1393 mnemonics like xvmovdp. This operand is marked FAKE. The insertion 1394 function just copies the XA field into the XB field, and the 1395 extraction function just checks that the fields are the same. */ 1396 1397 static unsigned long 1398 insert_xb6s (unsigned long insn, 1399 long value ATTRIBUTE_UNUSED, 1400 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1401 const char **errmsg ATTRIBUTE_UNUSED) 1402 { 1403 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1); 1404 } 1405 1406 static long 1407 extract_xb6s (unsigned long insn, 1408 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1409 int *invalid) 1410 { 1411 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 1412 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1))) 1413 *invalid = 1; 1414 return 0; 1415 } 1416 1417 /* The XC field in an XX4 form instruction. This is split. */ 1418 1419 static unsigned long 1420 insert_xc6 (unsigned long insn, 1421 long value, 1422 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1423 const char **errmsg ATTRIBUTE_UNUSED) 1424 { 1425 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); 1426 } 1427 1428 static long 1429 extract_xc6 (unsigned long insn, 1430 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1431 int *invalid ATTRIBUTE_UNUSED) 1432 { 1433 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); 1434 } 1435 1436 static unsigned long 1437 insert_dm (unsigned long insn, 1438 long value, 1439 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1440 const char **errmsg) 1441 { 1442 if (value != 0 && value != 1) 1443 *errmsg = _("invalid constant"); 1444 return insn | (((value) ? 3 : 0) << 8); 1445 } 1446 1447 static long 1448 extract_dm (unsigned long insn, 1449 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1450 int *invalid) 1451 { 1452 long value; 1453 1454 value = (insn >> 8) & 3; 1455 if (value != 0 && value != 3) 1456 *invalid = 1; 1457 return (value) ? 1 : 0; 1458 } 1459 1460 /* Macros used to form opcodes. */ 1461 1462 /* The main opcode. */ 1463 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) 1464 #define OP_MASK OP (0x3f) 1465 1466 /* The main opcode combined with a trap code in the TO field of a D 1467 form instruction. Used for extended mnemonics for the trap 1468 instructions. */ 1469 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) 1470 #define OPTO_MASK (OP_MASK | TO_MASK) 1471 1472 /* The main opcode combined with a comparison size bit in the L field 1473 of a D form or X form instruction. Used for extended mnemonics for 1474 the comparison instructions. */ 1475 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) 1476 #define OPL_MASK OPL (0x3f,1) 1477 1478 /* An A form instruction. */ 1479 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) 1480 #define A_MASK A (0x3f, 0x1f, 1) 1481 1482 /* An A_MASK with the FRB field fixed. */ 1483 #define AFRB_MASK (A_MASK | FRB_MASK) 1484 1485 /* An A_MASK with the FRC field fixed. */ 1486 #define AFRC_MASK (A_MASK | FRC_MASK) 1487 1488 /* An A_MASK with the FRA and FRC fields fixed. */ 1489 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 1490 1491 /* An AFRAFRC_MASK, but with L bit clear. */ 1492 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) 1493 1494 /* A B form instruction. */ 1495 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 1496 #define B_MASK B (0x3f, 1, 1) 1497 1498 /* A B form instruction setting the BO field. */ 1499 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 1500 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 1501 1502 /* A BBO_MASK with the y bit of the BO field removed. This permits 1503 matching a conditional branch regardless of the setting of the y 1504 bit. Similarly for the 'at' bits used for power4 branch hints. */ 1505 #define Y_MASK (((unsigned long) 1) << 21) 1506 #define AT1_MASK (((unsigned long) 3) << 21) 1507 #define AT2_MASK (((unsigned long) 9) << 21) 1508 #define BBOY_MASK (BBO_MASK &~ Y_MASK) 1509 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) 1510 1511 /* A B form instruction setting the BO field and the condition bits of 1512 the BI field. */ 1513 #define BBOCB(op, bo, cb, aa, lk) \ 1514 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) 1515 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) 1516 1517 /* A BBOCB_MASK with the y bit of the BO field removed. */ 1518 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) 1519 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) 1520 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) 1521 1522 /* A BBOYCB_MASK in which the BI field is fixed. */ 1523 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 1524 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 1525 1526 /* An Context form instruction. */ 1527 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) 1528 #define CTX_MASK CTX(0x3f, 0x7) 1529 1530 /* An User Context form instruction. */ 1531 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 1532 #define UCTX_MASK UCTX(0x3f, 0x1f) 1533 1534 /* The main opcode mask with the RA field clear. */ 1535 #define DRA_MASK (OP_MASK | RA_MASK) 1536 1537 /* A DS form instruction. */ 1538 #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 1539 #define DS_MASK DSO (0x3f, 3) 1540 1541 /* An EVSEL form instruction. */ 1542 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) 1543 #define EVSEL_MASK EVSEL(0x3f, 0xff) 1544 1545 /* An M form instruction. */ 1546 #define M(op, rc) (OP (op) | ((rc) & 1)) 1547 #define M_MASK M (0x3f, 1) 1548 1549 /* An M form instruction with the ME field specified. */ 1550 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) 1551 1552 /* An M_MASK with the MB and ME fields fixed. */ 1553 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) 1554 1555 /* An M_MASK with the SH and ME fields fixed. */ 1556 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) 1557 1558 /* An MD form instruction. */ 1559 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) 1560 #define MD_MASK MD (0x3f, 0x7, 1) 1561 1562 /* An MD_MASK with the MB field fixed. */ 1563 #define MDMB_MASK (MD_MASK | MB6_MASK) 1564 1565 /* An MD_MASK with the SH field fixed. */ 1566 #define MDSH_MASK (MD_MASK | SH6_MASK) 1567 1568 /* An MDS form instruction. */ 1569 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) 1570 #define MDS_MASK MDS (0x3f, 0xf, 1) 1571 1572 /* An MDS_MASK with the MB field fixed. */ 1573 #define MDSMB_MASK (MDS_MASK | MB6_MASK) 1574 1575 /* An SC form instruction. */ 1576 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) 1577 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) 1578 1579 /* An VX form instruction. */ 1580 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 1581 1582 /* The mask for an VX form instruction. */ 1583 #define VX_MASK VX(0x3f, 0x7ff) 1584 1585 /* An VA form instruction. */ 1586 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) 1587 1588 /* The mask for an VA form instruction. */ 1589 #define VXA_MASK VXA(0x3f, 0x3f) 1590 1591 /* An VXR form instruction. */ 1592 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) 1593 1594 /* The mask for a VXR form instruction. */ 1595 #define VXR_MASK VXR(0x3f, 0x3ff, 1) 1596 1597 /* An X form instruction. */ 1598 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1599 1600 /* An XX2 form instruction. */ 1601 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) 1602 1603 /* An XX3 form instruction. */ 1604 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) 1605 1606 /* An XX3 form instruction with the RC bit specified. */ 1607 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3)) 1608 1609 /* An XX4 form instruction. */ 1610 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4)) 1611 1612 /* A Z form instruction. */ 1613 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) 1614 1615 /* An X form instruction with the RC bit specified. */ 1616 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 1617 1618 /* A Z form instruction with the RC bit specified. */ 1619 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) 1620 1621 /* The mask for an X form instruction. */ 1622 #define X_MASK XRC (0x3f, 0x3ff, 1) 1623 1624 /* The mask for an XX1 form instruction. */ 1625 #define XX1_MASK X (0x3f, 0x3ff) 1626 1627 /* The mask for an XX2 form instruction. */ 1628 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) 1629 1630 /* The mask for an XX2 form instruction with the UIM bits specified. */ 1631 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) 1632 1633 /* The mask for an XX2 form instruction with the BF bits specified. */ 1634 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) 1635 1636 /* The mask for an XX3 form instruction. */ 1637 #define XX3_MASK XX3 (0x3f, 0xff) 1638 1639 /* The mask for an XX3 form instruction with the BF bits specified. */ 1640 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) 1641 1642 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */ 1643 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) 1644 #define XX3SHW_MASK XX3DM_MASK 1645 1646 /* The mask for an XX4 form instruction. */ 1647 #define XX4_MASK XX4 (0x3f, 0x3) 1648 1649 /* An X form wait instruction with everything filled in except the WC field. */ 1650 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) 1651 1652 /* The mask for a Z form instruction. */ 1653 #define Z_MASK ZRC (0x3f, 0x1ff, 1) 1654 #define Z2_MASK ZRC (0x3f, 0xff, 1) 1655 1656 /* An X_MASK with the RA field fixed. */ 1657 #define XRA_MASK (X_MASK | RA_MASK) 1658 1659 /* An XRA_MASK with the W field clear. */ 1660 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) 1661 1662 /* An X_MASK with the RB field fixed. */ 1663 #define XRB_MASK (X_MASK | RB_MASK) 1664 1665 /* An X_MASK with the RT field fixed. */ 1666 #define XRT_MASK (X_MASK | RT_MASK) 1667 1668 /* An XRT_MASK mask with the L bits clear. */ 1669 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) 1670 1671 /* An X_MASK with the RA and RB fields fixed. */ 1672 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 1673 1674 /* An XRARB_MASK, but with the L bit clear. */ 1675 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) 1676 1677 /* An X_MASK with the RT and RA fields fixed. */ 1678 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 1679 1680 /* An XRTRA_MASK, but with L bit clear. */ 1681 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) 1682 1683 /* An X form instruction with the L bit specified. */ 1684 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 1685 1686 /* An X form instruction with RT fields specified */ 1687 #define XRT(op, xop, rt) (X ((op), (xop)) \ 1688 | ((((unsigned long)(rt)) & 0x1f) << 21)) 1689 1690 /* An X form instruction with RT and RA fields specified */ 1691 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \ 1692 | ((((unsigned long)(rt)) & 0x1f) << 21) \ 1693 | ((((unsigned long)(ra)) & 0x1f) << 16)) 1694 1695 /* The mask for an X form comparison instruction. */ 1696 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) 1697 1698 /* The mask for an X form comparison instruction with the L field 1699 fixed. */ 1700 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) 1701 1702 /* An X form trap instruction with the TO field specified. */ 1703 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) 1704 #define XTO_MASK (X_MASK | TO_MASK) 1705 1706 /* An X form tlb instruction with the SH field specified. */ 1707 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) 1708 #define XTLB_MASK (X_MASK | SH_MASK) 1709 1710 /* An X form sync instruction. */ 1711 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) 1712 1713 /* An X form sync instruction with everything filled in except the LS field. */ 1714 #define XSYNC_MASK (0xff9fffff) 1715 1716 /* An X_MASK, but with the EH bit clear. */ 1717 #define XEH_MASK (X_MASK & ~((unsigned long )1)) 1718 1719 /* An X form AltiVec dss instruction. */ 1720 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) 1721 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 1722 1723 /* An XFL form instruction. */ 1724 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 1725 #define XFL_MASK XFL (0x3f, 0x3ff, 1) 1726 1727 /* An X form isel instruction. */ 1728 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 1729 #define XISEL_MASK XISEL(0x3f, 0x1f) 1730 1731 /* An XL form instruction with the LK field set to 0. */ 1732 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1733 1734 /* An XL form instruction which uses the LK field. */ 1735 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) 1736 1737 /* The mask for an XL form instruction. */ 1738 #define XL_MASK XLLK (0x3f, 0x3ff, 1) 1739 1740 /* An XL form instruction which explicitly sets the BO field. */ 1741 #define XLO(op, bo, xop, lk) \ 1742 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 1743 #define XLO_MASK (XL_MASK | BO_MASK) 1744 1745 /* An XL form instruction which explicitly sets the y bit of the BO 1746 field. */ 1747 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) 1748 #define XLYLK_MASK (XL_MASK | Y_MASK) 1749 1750 /* An XL form instruction which sets the BO field and the condition 1751 bits of the BI field. */ 1752 #define XLOCB(op, bo, cb, xop, lk) \ 1753 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) 1754 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) 1755 1756 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ 1757 #define XLBB_MASK (XL_MASK | BB_MASK) 1758 #define XLYBB_MASK (XLYLK_MASK | BB_MASK) 1759 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) 1760 1761 /* A mask for branch instructions using the BH field. */ 1762 #define XLBH_MASK (XL_MASK | (0x1c << 11)) 1763 1764 /* An XL_MASK with the BO and BB fields fixed. */ 1765 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) 1766 1767 /* An XL_MASK with the BO, BI and BB fields fixed. */ 1768 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 1769 1770 /* An XO form instruction. */ 1771 #define XO(op, xop, oe, rc) \ 1772 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) 1773 #define XO_MASK XO (0x3f, 0x1ff, 1, 1) 1774 1775 /* An XO_MASK with the RB field fixed. */ 1776 #define XORB_MASK (XO_MASK | RB_MASK) 1777 1778 /* An XOPS form instruction for paired singles. */ 1779 #define XOPS(op, xop, rc) \ 1780 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 1781 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1) 1782 1783 1784 /* An XS form instruction. */ 1785 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) 1786 #define XS_MASK XS (0x3f, 0x1ff, 1) 1787 1788 /* A mask for the FXM version of an XFX form instruction. */ 1789 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) 1790 1791 /* An XFX form instruction with the FXM field filled in. */ 1792 #define XFXM(op, xop, fxm, p4) \ 1793 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ 1794 | ((unsigned long)(p4) << 20)) 1795 1796 /* An XFX form instruction with the SPR field filled in. */ 1797 #define XSPR(op, xop, spr) \ 1798 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) 1799 #define XSPR_MASK (X_MASK | SPR_MASK) 1800 1801 /* An XFX form instruction with the SPR field filled in except for the 1802 SPRBAT field. */ 1803 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) 1804 1805 /* An XFX form instruction with the SPR field filled in except for the 1806 SPRG field. */ 1807 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) 1808 1809 /* An X form instruction with everything filled in except the E field. */ 1810 #define XE_MASK (0xffff7fff) 1811 1812 /* An X form user context instruction. */ 1813 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 1814 #define XUC_MASK XUC(0x3f, 0x1f) 1815 1816 /* An XW form instruction. */ 1817 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1)) 1818 /* The mask for a G form instruction. rc not supported at present. */ 1819 #define XW_MASK XW (0x3f, 0x3f, 0) 1820 1821 /* An APU form instruction. */ 1822 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1)) 1823 1824 /* The mask for an APU form instruction. */ 1825 #define APU_MASK APU (0x3f, 0x3ff, 1) 1826 #define APU_RT_MASK (APU_MASK | RT_MASK) 1827 #define APU_RA_MASK (APU_MASK | RA_MASK) 1828 1829 /* The BO encodings used in extended conditional branch mnemonics. */ 1830 #define BODNZF (0x0) 1831 #define BODNZFP (0x1) 1832 #define BODZF (0x2) 1833 #define BODZFP (0x3) 1834 #define BODNZT (0x8) 1835 #define BODNZTP (0x9) 1836 #define BODZT (0xa) 1837 #define BODZTP (0xb) 1838 1839 #define BOF (0x4) 1840 #define BOFP (0x5) 1841 #define BOFM4 (0x6) 1842 #define BOFP4 (0x7) 1843 #define BOT (0xc) 1844 #define BOTP (0xd) 1845 #define BOTM4 (0xe) 1846 #define BOTP4 (0xf) 1847 1848 #define BODNZ (0x10) 1849 #define BODNZP (0x11) 1850 #define BODZ (0x12) 1851 #define BODZP (0x13) 1852 #define BODNZM4 (0x18) 1853 #define BODNZP4 (0x19) 1854 #define BODZM4 (0x1a) 1855 #define BODZP4 (0x1b) 1856 1857 #define BOU (0x14) 1858 1859 /* The BI condition bit encodings used in extended conditional branch 1860 mnemonics. */ 1861 #define CBLT (0) 1862 #define CBGT (1) 1863 #define CBEQ (2) 1864 #define CBSO (3) 1865 1866 /* The TO encodings used in extended trap mnemonics. */ 1867 #define TOLGT (0x1) 1868 #define TOLLT (0x2) 1869 #define TOEQ (0x4) 1870 #define TOLGE (0x5) 1871 #define TOLNL (0x5) 1872 #define TOLLE (0x6) 1873 #define TOLNG (0x6) 1874 #define TOGT (0x8) 1875 #define TOGE (0xc) 1876 #define TONL (0xc) 1877 #define TOLT (0x10) 1878 #define TOLE (0x14) 1879 #define TONG (0x14) 1880 #define TONE (0x18) 1881 #define TOU (0x1f) 1882 1883 /* Smaller names for the flags so each entry in the opcodes table will 1884 fit on a single line. */ 1885 #define PPCNONE 0 1886 #undef PPC 1887 #define PPC PPC_OPCODE_PPC 1888 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 1889 #define POWER4 PPC_OPCODE_POWER4 1890 #define POWER5 PPC_OPCODE_POWER5 1891 #define POWER6 PPC_OPCODE_POWER6 1892 #define POWER7 PPC_OPCODE_POWER7 1893 #define CELL PPC_OPCODE_CELL 1894 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC 1895 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC 1896 #define PPC403 PPC_OPCODE_403 1897 #define PPC405 PPC_OPCODE_405 1898 #define PPC440 PPC_OPCODE_440 1899 #define PPC464 PPC440 1900 #define PPC750 PPC 1901 #define PPC7450 PPC 1902 #define PPC860 PPC 1903 #define PPCPS PPC_OPCODE_PPCPS 1904 #define PPCVEC PPC_OPCODE_ALTIVEC 1905 #define PPCVSX PPC_OPCODE_VSX 1906 #define POWER PPC_OPCODE_POWER 1907 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1908 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1909 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 1910 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 1911 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 1912 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 1913 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 1914 #define MFDEC1 PPC_OPCODE_POWER 1915 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE 1916 #define BOOKE PPC_OPCODE_BOOKE 1917 #define CLASSIC PPC_OPCODE_CLASSIC 1918 #define PPCE300 PPC_OPCODE_E300 1919 #define PPCSPE PPC_OPCODE_SPE 1920 #define PPCISEL PPC_OPCODE_ISEL 1921 #define PPCEFS PPC_OPCODE_EFS 1922 #define PPCBRLK PPC_OPCODE_BRLOCK 1923 #define PPCPMR PPC_OPCODE_PMR 1924 #define PPCCHLK PPC_OPCODE_CACHELCK 1925 #define PPCRFMCI PPC_OPCODE_RFMCI 1926 #define E500MC PPC_OPCODE_E500MC 1927 1928 /* The opcode table. 1929 1930 The format of the opcode table is: 1931 1932 NAME OPCODE MASK FLAGS {OPERANDS} 1933 1934 NAME is the name of the instruction. 1935 OPCODE is the instruction opcode. 1936 MASK is the opcode mask; this is used to tell the disassembler 1937 which bits in the actual opcode must match OPCODE. 1938 FLAGS are flags indicated what processors support the instruction. 1939 OPERANDS is the list of operands. 1940 1941 The disassembler reads the table in order and prints the first 1942 instruction which matches, so this table is sorted to put more 1943 specific instructions before more general instructions. 1944 1945 This table must be sorted by major opcode. Please try to keep it 1946 vaguely sorted within major opcode too, except of course where 1947 constrained otherwise by disassembler operation. */ 1948 1949 const struct powerpc_opcode powerpc_opcodes[] = { 1950 {"attn", X(0,256), X_MASK, POWER4, PPCNONE, {0}}, 1951 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1952 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1953 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1954 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1955 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1956 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1957 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1958 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1959 {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1960 {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1961 {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1962 {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1963 {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1964 {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, 1965 {"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}}, 1966 1967 {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1968 {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1969 {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1970 {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1971 {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1972 {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1973 {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1974 {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1975 {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1976 {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1977 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1978 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1979 {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1980 {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1981 {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1982 {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1983 {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1984 {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1985 {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1986 {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1987 {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1988 {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1989 {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1990 {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1991 {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1992 {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1993 {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, 1994 {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, 1995 {"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}}, 1996 {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}}, 1997 1998 {"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, 1999 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2000 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2001 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2002 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2003 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2004 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2005 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, 2006 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2007 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, 2008 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2009 {"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2010 {"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2011 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2012 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2013 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2014 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2015 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, 2016 {"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2017 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, 2018 {"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2019 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, 2020 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, 2021 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2022 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2023 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2024 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2025 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2026 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2027 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2028 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2029 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2030 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2031 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2032 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2033 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2034 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2035 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2036 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2037 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2038 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2039 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2040 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2041 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, 2042 {"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, SHB}}, 2043 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2044 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}}, 2045 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2046 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}}, 2047 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2048 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2049 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, 2050 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, 2051 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2052 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2053 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2054 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2055 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2056 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2057 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2058 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2059 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2060 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, 2061 {"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, 2062 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2063 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2064 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2065 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2066 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2067 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2068 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, 2069 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2070 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, 2071 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2072 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2073 {"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2074 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2075 {"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2076 {"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2077 {"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2078 {"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2079 {"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2080 {"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, 2081 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2082 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2083 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2084 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2085 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2086 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2087 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2088 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2089 {"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2090 {"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2091 {"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, 2092 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2093 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2094 {"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2095 {"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2096 {"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2097 {"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2098 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2099 {"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2100 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2101 {"vrefp", VX (4, 266), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2102 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2103 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2104 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2105 {"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2106 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2107 {"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2108 {"macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2109 {"macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2110 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2111 {"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2112 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2113 {"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2114 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2115 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2116 {"mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2117 {"mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2118 {"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2119 {"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2120 {"nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2121 {"nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2122 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2123 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2124 {"vslw", VX (4, 388), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2125 {"vexptefp", VX (4, 394), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2126 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2127 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2128 {"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2129 {"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2130 {"vsl", VX (4, 452), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2131 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2132 {"vlogefp", VX (4, 458), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2133 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2134 {"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2135 {"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2136 {"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2137 {"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2138 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2139 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2140 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}}, 2141 {"vminub", VX (4, 514), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2142 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2143 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}}, 2144 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2145 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, UIMM, RB}}, 2146 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}}, 2147 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2148 {"evabs", VX (4, 520), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2149 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2150 {"evneg", VX (4, 521), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2151 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2152 {"vrfin", VX (4, 522), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2153 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2154 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2155 {"vspltb", VX (4, 524), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, 2156 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2157 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2158 {"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2159 {"brinc", VX (4, 527), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2160 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2161 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, 2162 {"evand", VX (4, 529), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2163 {"evandc", VX (4, 530), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2164 {"evxor", VX (4, 534), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2165 {"evmr", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}}, 2166 {"evor", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2167 {"evnor", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2168 {"evnot", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}}, 2169 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, 2170 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2171 {"evorc", VX (4, 539), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2172 {"evnand", VX (4, 542), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2173 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2174 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2175 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, 2176 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, 2177 {"evslw", VX (4, 548), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2178 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, 2179 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2180 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}}, 2181 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, 2182 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}}, 2183 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2184 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2185 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2186 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2187 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2188 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2189 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2190 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2191 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2192 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, 2193 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2194 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2195 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2196 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2197 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2198 {"vrfiz", VX (4, 586), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2199 {"vsplth", VX (4, 588), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, 2200 {"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2201 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, 2202 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, PPCNONE, {RS, RA, RB, CRFS}}, 2203 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, 2204 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2205 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2206 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2207 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2208 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2209 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2210 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2211 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2212 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2213 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2214 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2215 {"vrfip", VX (4, 650), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2216 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2217 {"vspltw", VX (4, 652), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, 2218 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2219 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2220 {"vupklsb", VX (4, 654), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2221 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2222 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2223 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2224 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2225 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2226 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2227 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2228 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2229 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2230 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, 2231 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, 2232 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2233 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2234 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, 2235 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, 2236 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, 2237 {"efssub", VX (4, 705), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, 2238 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, 2239 {"vsr", VX (4, 708), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2240 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, 2241 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, 2242 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2243 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, 2244 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, 2245 {"vrfim", VX (4, 714), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2246 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2247 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2248 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2249 {"vupklsh", VX (4, 718), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2250 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2251 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2252 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2253 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2254 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2255 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2256 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2257 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2258 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2259 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2260 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, 2261 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2262 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2263 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2264 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2265 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, 2266 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, 2267 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2268 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2269 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, 2270 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, 2271 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, 2272 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, 2273 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, 2274 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2275 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2276 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2277 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2278 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2279 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2280 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2281 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2282 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2283 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2284 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2285 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2286 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2287 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2288 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2289 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, 2290 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, 2291 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2292 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2293 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, 2294 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2295 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2296 {"evldd", VX (4, 769), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, 2297 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2298 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2299 {"evldw", VX (4, 771), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, 2300 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2301 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2302 {"evldh", VX (4, 773), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, 2303 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2304 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2305 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2306 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, 2307 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, 2308 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2309 {"vspltisb", VX (4, 780), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, 2310 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, 2311 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2312 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2313 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, 2314 {"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2315 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2316 {"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2317 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, 2318 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2319 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, 2320 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2321 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, 2322 {"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2323 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2324 {"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2325 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, 2326 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2327 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, 2328 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2329 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, 2330 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2331 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, 2332 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2333 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, 2334 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2335 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, 2336 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2337 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, 2338 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2339 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, 2340 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2341 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, 2342 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2343 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2344 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2345 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2346 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2347 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, 2348 {"vspltish", VX (4, 844), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, 2349 {"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2350 {"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2351 {"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2352 {"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2353 {"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2354 {"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2355 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2356 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2357 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2358 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2359 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2360 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, 2361 {"vspltisw", VX (4, 908), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, 2362 {"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2363 {"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2364 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2365 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, 2366 {"vupklpx", VX (4, 974), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, 2367 {"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2368 {"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2369 {"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2370 {"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2371 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2372 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2373 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2374 {"vand", VX (4,1028), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2375 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2376 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2377 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2378 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2379 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2380 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2381 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2382 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2383 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2384 {"vslo", VX (4,1036), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2385 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2386 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2387 {"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2388 {"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2389 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2390 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2391 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2392 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2393 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2394 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2395 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2396 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2397 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2398 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2399 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2400 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2401 {"vandc", VX (4,1092), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2402 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2403 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2404 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2405 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2406 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2407 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2408 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2409 {"vsro", VX (4,1100), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2410 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2411 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2412 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2413 {"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2414 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2415 {"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2416 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2417 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2418 {"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2419 {"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2420 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2421 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2422 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2423 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2424 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2425 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2426 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2427 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2428 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2429 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2430 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2431 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2432 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2433 {"vor", VX (4,1156), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2434 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2435 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2436 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2437 {"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2438 {"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2439 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2440 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2441 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2442 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2443 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2444 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2445 {"evmra", VX (4,1220), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2446 {"vxor", VX (4,1220), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2447 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2448 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2449 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2450 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2451 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2452 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2453 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2454 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2455 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, 2456 {"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2457 {"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2458 {"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2459 {"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2460 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2461 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, 2462 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2463 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2464 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2465 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2466 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2467 {"vnor", VX (4,1284), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2468 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2469 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2470 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2471 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2472 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2473 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2474 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2475 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2476 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2477 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2478 {"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2479 {"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2480 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2481 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2482 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2483 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2484 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2485 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2486 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2487 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2488 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2489 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2490 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2491 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2492 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2493 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2494 {"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2495 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2496 {"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2497 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2498 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2499 {"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2500 {"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2501 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2502 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2503 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2504 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2505 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2506 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2507 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2508 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2509 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2510 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2511 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2512 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2513 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2514 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2515 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2516 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2517 {"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2518 {"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2519 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2520 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2521 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2522 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2523 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2524 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2525 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2526 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2527 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2528 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2529 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, 2530 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2531 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2532 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2533 {"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2534 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2535 {"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2536 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2537 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, 2538 {"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2539 {"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2540 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2541 {"mfvscr", VX (4,1540), VX_MASK, PPCVEC, PPCNONE, {VD}}, 2542 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2543 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2544 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2545 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2546 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2547 {"mtvscr", VX (4,1604), VX_MASK, PPCVEC, PPCNONE, {VB}}, 2548 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2549 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2550 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2551 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2552 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2553 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2554 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2555 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2556 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2557 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2558 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2559 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2560 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2561 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2562 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2563 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2564 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2565 {"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2566 {"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2567 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2568 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2569 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2570 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2571 {"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2572 {"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2573 {"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2574 {"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2575 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2576 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2577 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2578 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2579 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2580 {"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2581 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2582 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, 2583 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2584 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, 2585 {"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2586 {"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2587 {"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2588 {"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, 2589 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}}, 2590 2591 {"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, 2592 {"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, 2593 2594 {"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, 2595 {"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, 2596 2597 {"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}}, 2598 2599 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}}, 2600 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}}, 2601 {"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}}, 2602 {"cmpli", OP(10), OP_MASK, PWRCOM, PPCNONE, {BF, RA, UI}}, 2603 2604 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}}, 2605 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}}, 2606 {"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}}, 2607 {"cmpi", OP(11), OP_MASK, PWRCOM, PPCNONE, {BF, RA, SI}}, 2608 2609 {"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, 2610 {"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, 2611 {"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}}, 2612 2613 {"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, 2614 {"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, 2615 {"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}}, 2616 2617 {"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}}, 2618 {"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}}, 2619 {"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}}, 2620 {"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, 2621 {"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}}, 2622 {"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}}, 2623 2624 {"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}}, 2625 {"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}}, 2626 {"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, 2627 {"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, 2628 {"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}}, 2629 2630 {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, 2631 {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, 2632 {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}}, 2633 {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}}, 2634 {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, 2635 {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, 2636 {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}}, 2637 {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}}, 2638 {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, 2639 {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, 2640 {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}}, 2641 {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}}, 2642 {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, 2643 {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, 2644 {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}}, 2645 {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}}, 2646 {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, 2647 {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, 2648 {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}}, 2649 {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, 2650 {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, 2651 {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}}, 2652 {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, 2653 {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, 2654 {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}}, 2655 {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, 2656 {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, 2657 {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}}, 2658 2659 {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2660 {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2661 {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2662 {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2663 {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2664 {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2665 {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2666 {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2667 {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2668 {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2669 {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2670 {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2671 {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2672 {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2673 {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2674 {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2675 {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2676 {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2677 {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2678 {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2679 {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2680 {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2681 {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2682 {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2683 {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2684 {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2685 {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2686 {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2687 {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2688 {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2689 {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2690 {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2691 {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2692 {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2693 {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2694 {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2695 {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2696 {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2697 {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2698 {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2699 {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2700 {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2701 {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2702 {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2703 {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2704 {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2705 {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2706 {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2707 {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2708 {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2709 {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2710 {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2711 {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2712 {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2713 {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2714 {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2715 {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2716 {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2717 {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2718 {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2719 {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2720 {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2721 {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2722 {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2723 {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2724 {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, 2725 {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2726 {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2727 {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2728 {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2729 {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2730 {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, 2731 {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2732 {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2733 {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2734 {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2735 {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2736 {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, 2737 {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2738 {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2739 {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2740 {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2741 {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2742 {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, 2743 2744 {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2745 {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2746 {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2747 {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2748 {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2749 {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2750 {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2751 {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2752 {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2753 {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2754 {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2755 {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2756 {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2757 {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2758 {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2759 {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2760 {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2761 {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2762 {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2763 {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2764 {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2765 {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2766 {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2767 {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2768 {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2769 {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2770 {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2771 {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2772 {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2773 {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2774 {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2775 {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2776 {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2777 {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2778 {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2779 {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2780 {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2781 {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2782 {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2783 {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2784 {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2785 {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, 2786 {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2787 {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2788 {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, 2789 {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, 2790 {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, 2791 {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, 2792 {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2793 {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2794 {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2795 {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2796 {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2797 {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, 2798 {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2799 {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2800 {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, 2801 {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, 2802 {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, 2803 {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, 2804 2805 {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, 2806 {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, 2807 {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2808 {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, 2809 {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, 2810 {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2811 {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, 2812 {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, 2813 {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2814 {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, 2815 {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, 2816 {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2817 {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, 2818 {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, 2819 {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2820 {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, 2821 {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, 2822 {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2823 {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, 2824 {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, 2825 {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2826 {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, 2827 {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, 2828 {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2829 2830 {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, 2831 {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, 2832 {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2833 {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, 2834 {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, 2835 {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, 2836 {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2837 {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, 2838 {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, 2839 {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, 2840 {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2841 {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, 2842 {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, 2843 {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, 2844 {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2845 {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, 2846 2847 {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, 2848 {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, 2849 {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2850 {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, 2851 {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, 2852 {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2853 {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, 2854 {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, 2855 {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2856 {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, 2857 {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, 2858 {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2859 {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, 2860 {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, 2861 {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2862 {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, 2863 {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, 2864 {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2865 {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, 2866 {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, 2867 {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2868 {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, 2869 {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, 2870 {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2871 2872 {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, 2873 {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, 2874 {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2875 {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, 2876 {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, 2877 {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, 2878 {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, 2879 {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, 2880 {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, 2881 {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, 2882 {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2883 {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, 2884 {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, 2885 {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, 2886 {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, 2887 {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, 2888 2889 {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}}, 2890 {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}}, 2891 {"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}}, 2892 {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}}, 2893 {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}}, 2894 {"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}}, 2895 {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}}, 2896 {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}}, 2897 {"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}}, 2898 {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}}, 2899 {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}}, 2900 {"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}}, 2901 2902 {"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}}, 2903 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}}, 2904 {"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}}, 2905 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}}, 2906 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}}, 2907 2908 {"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}}, 2909 {"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}}, 2910 {"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}}, 2911 {"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}}, 2912 2913 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, 2914 2915 {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, 2916 {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, 2917 {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, 2918 {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, 2919 {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, 2920 {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, 2921 {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, 2922 {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, 2923 {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, 2924 {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, 2925 {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, 2926 {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, 2927 {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, 2928 {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}}, 2929 {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, 2930 {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}}, 2931 {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, 2932 {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, 2933 {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, 2934 {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, 2935 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, 2936 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, 2937 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, 2938 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, 2939 2940 {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2941 {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2942 {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2943 {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2944 {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2945 {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2946 {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2947 {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2948 {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2949 {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2950 {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2951 {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2952 {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2953 {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2954 {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2955 {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2956 {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2957 {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2958 {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2959 {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2960 {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2961 {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2962 {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2963 {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2964 {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2965 {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2966 {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2967 {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2968 {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2969 {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2970 {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2971 {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2972 {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2973 {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2974 {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2975 {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2976 {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2977 {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 2978 {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 2979 {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2980 {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2981 {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2982 {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2983 {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2984 {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2985 {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2986 {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2987 {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2988 {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2989 {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2990 {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2991 {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2992 {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2993 {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 2994 {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 2995 {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 2996 {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 2997 {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 2998 {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 2999 {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3000 {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3001 {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3002 {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3003 {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3004 {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3005 {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3006 {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3007 {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3008 {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3009 {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3010 {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3011 {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3012 {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3013 {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3014 {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3015 {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3016 {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3017 {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3018 {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3019 {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3020 {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3021 {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3022 {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3023 {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3024 {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 3025 {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3026 {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3027 {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 3028 {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3029 {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3030 {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 3031 {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3032 {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3033 {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 3034 {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3035 {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3036 {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 3037 {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3038 {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3039 {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 3040 {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3041 {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3042 {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 3043 {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3044 {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3045 {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3046 {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3047 {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, 3048 {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3049 {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3050 {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3051 {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3052 {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3053 {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3054 {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3055 {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3056 {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3057 {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3058 {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3059 {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3060 {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3061 {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3062 {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3063 {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3064 {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3065 {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3066 {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3067 {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3068 {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3069 {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3070 {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3071 {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3072 {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3073 {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3074 {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3075 {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3076 {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3077 {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3078 {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3079 {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3080 3081 {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3082 {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3083 {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3084 {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3085 {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3086 {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3087 {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3088 {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3089 {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3090 {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3091 {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3092 {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3093 {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3094 {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3095 {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, 3096 {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3097 {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3098 {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, 3099 {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3100 {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3101 {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3102 {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3103 {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3104 {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3105 {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3106 {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3107 {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3108 {"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3109 {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3110 {"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3111 {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3112 {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3113 {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3114 {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3115 {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3116 {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3117 {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3118 {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3119 {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, 3120 {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3121 {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3122 {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, 3123 {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3124 {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3125 {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3126 {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3127 {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3128 {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3129 3130 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, 3131 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, 3132 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, 3133 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, 3134 {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, 3135 {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, 3136 {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, 3137 {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, 3138 3139 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}}, 3140 3141 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}}, 3142 {"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, 3143 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI, PPCNONE, {0}}, 3144 3145 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}}, 3146 {"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}}, 3147 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, PPCNONE, {0}}, 3148 3149 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}}, 3150 3151 {"rfgi", XL(19,102), 0xffffffff, E500MC, PPCNONE, {0}}, 3152 3153 {"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, 3154 3155 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}}, 3156 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}}, 3157 3158 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}}, 3159 {"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, 3160 3161 {"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}}, 3162 3163 {"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, 3164 3165 {"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, 3166 3167 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPCNONE, {0}}, 3168 3169 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}}, 3170 {"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, 3171 3172 {"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}}, 3173 3174 {"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, 3175 3176 {"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}}, 3177 3178 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}}, 3179 {"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, 3180 3181 {"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}}, 3182 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}}, 3183 3184 {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}}, 3185 {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}}, 3186 3187 {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3188 {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3189 {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3190 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3191 {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3192 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3193 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3194 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3195 {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3196 {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3197 {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3198 {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3199 {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3200 {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3201 {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3202 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3203 {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3204 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3205 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3206 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3207 {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3208 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3209 {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3210 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3211 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3212 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3213 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3214 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3215 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3216 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3217 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3218 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3219 {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3220 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3221 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3222 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3223 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3224 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3225 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3226 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3227 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3228 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3229 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3230 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3231 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3232 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3233 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3234 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3235 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3236 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3237 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3238 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3239 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3240 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3241 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3242 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3243 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3244 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3245 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3246 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3247 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3248 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3249 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3250 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3251 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3252 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3253 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3254 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3255 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3256 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3257 {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3258 {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3259 {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3260 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3261 {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3262 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3263 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3264 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3265 {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3266 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3267 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3268 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3269 {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3270 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3271 {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3272 {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3273 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3274 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3275 {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, 3276 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3277 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3278 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3279 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3280 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3281 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3282 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3283 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3284 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3285 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3286 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, 3287 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3288 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3289 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3290 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3291 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3292 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3293 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3294 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3295 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3296 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3297 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3298 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3299 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3300 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3301 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3302 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3303 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3304 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3305 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3306 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, 3307 3308 {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3309 {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3310 {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3311 {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3312 {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3313 {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3314 {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3315 {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3316 {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3317 {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3318 {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3319 {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3320 {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, 3321 {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3322 {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3323 {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, 3324 {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3325 {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3326 {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3327 {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, 3328 3329 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, 3330 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, 3331 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, 3332 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, 3333 {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, 3334 {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, 3335 {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, 3336 {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, 3337 3338 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, 3339 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, 3340 3341 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, 3342 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, 3343 3344 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, 3345 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, 3346 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, 3347 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, 3348 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, 3349 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, 3350 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, 3351 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, 3352 3353 {"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}}, 3354 {"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}}, 3355 3356 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, 3357 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, 3358 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, 3359 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, 3360 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, 3361 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, 3362 3363 {"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}}, 3364 {"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, 3365 {"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, 3366 3367 {"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, 3368 {"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, 3369 3370 {"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, 3371 {"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, 3372 3373 {"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, 3374 {"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, 3375 3376 {"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, 3377 {"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, 3378 3379 {"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, 3380 {"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, 3381 3382 {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, 3383 {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}}, 3384 {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, 3385 {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, 3386 {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}}, 3387 {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, 3388 3389 {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}}, 3390 {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}}, 3391 3392 {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, 3393 {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, 3394 3395 {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, 3396 {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, 3397 3398 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}}, 3399 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}}, 3400 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}}, 3401 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}}, 3402 3403 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}}, 3404 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}}, 3405 3406 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, 3407 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, 3408 {"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, 3409 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}}, 3410 3411 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3412 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3413 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3414 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3415 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3416 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3417 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3418 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3419 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3420 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3421 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3422 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3423 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3424 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3425 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3426 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3427 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3428 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3429 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3430 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3431 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3432 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3433 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3434 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3435 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3436 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3437 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, 3438 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, 3439 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}}, 3440 {"tw", X(31,4), X_MASK, PPCCOM, PPCNONE, {TO, RA, RB}}, 3441 {"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}}, 3442 3443 {"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, 3444 {"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, 3445 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 3446 3447 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3448 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3449 {"subc", XO(31,8,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, 3450 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3451 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3452 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, 3453 3454 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 3455 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 3456 3457 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3458 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3459 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3460 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3461 3462 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 3463 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 3464 3465 {"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, 3466 3467 {"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}}, 3468 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}}, 3469 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}}, 3470 3471 {"lwarx", X(31,20), XEH_MASK, PPC, PPCNONE, {RT, RA0, RB, EH}}, 3472 3473 {"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}}, 3474 3475 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300, PPCNONE, {CT, RA, RB}}, 3476 3477 {"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, 3478 {"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3479 3480 {"slw", XRC(31,24,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, 3481 {"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, 3482 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, 3483 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, 3484 3485 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, 3486 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, 3487 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, 3488 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, 3489 3490 {"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, 3491 {"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, 3492 3493 {"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3494 {"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3495 3496 {"maskg", XRC(31,29,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3497 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3498 3499 {"ldepx", X(31,29), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 3500 {"lwepx", X(31,31), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 3501 3502 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, 3503 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, 3504 {"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, 3505 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}}, 3506 3507 {"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, 3508 {"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, 3509 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 3510 3511 {"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, 3512 3513 {"lvewx", X(31,71), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, 3514 3515 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}}, 3516 3517 {"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, 3518 3519 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL, PPCNONE, {RT, RA, RB, CRB}}, 3520 3521 {"subf", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 3522 {"sub", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, 3523 {"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 3524 {"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, 3525 3526 {"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}}, 3527 3528 {"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}}, 3529 3530 {"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}}, 3531 3532 {"lwzux", X(31,55), X_MASK, PPCCOM, PPCNONE, {RT, RAL, RB}}, 3533 {"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3534 3535 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, 3536 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, 3537 3538 {"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3539 {"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3540 3541 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}}, 3542 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}}, 3543 {"wait", X(31,62), XWC_MASK, POWER7|E500MC, PPCNONE, {WC}}, 3544 3545 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, 3546 3547 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3548 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3549 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3550 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3551 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3552 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3553 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3554 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3555 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3556 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3557 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3558 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3559 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3560 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, 3561 {"td", X(31,68), X_MASK, PPC64, PPCNONE, {TO, RA, RB}}, 3562 3563 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 3564 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 3565 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 3566 3567 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 3568 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 3569 3570 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, PPCNONE, {RA, RS, RB}}, 3571 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, PPCNONE, {RA, RS, RB}}, 3572 3573 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}}, 3574 3575 {"mfmsr", X(31,83), XRARB_MASK, COM, PPCNONE, {RT}}, 3576 3577 {"ldarx", X(31,84), XEH_MASK, PPC64, PPCNONE, {RT, RA0, RB, EH}}, 3578 3579 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPCNONE, {RA, RB}}, 3580 {"dcbf", X(31,86), XLRT_MASK, PPC, PPCNONE, {RA, RB, L}}, 3581 3582 {"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, 3583 3584 {"lbepx", X(31,95), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 3585 3586 {"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, 3587 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 3588 3589 {"neg", XO(31,104,0,0), XORB_MASK, COM, PPCNONE, {RT, RA}}, 3590 {"neg.", XO(31,104,0,1), XORB_MASK, COM, PPCNONE, {RT, RA}}, 3591 3592 {"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 3593 {"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 3594 3595 {"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, 3596 3597 {"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}}, 3598 3599 {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}}, 3600 3601 {"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, 3602 3603 {"popcntb", X(31,122), XRB_MASK, POWER5, PPCNONE, {RA, RS}}, 3604 3605 {"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, 3606 {"nor", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3607 {"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, 3608 {"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3609 3610 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, 3611 3612 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, PPCNONE, {RS}}, 3613 3614 {"dcbtstls", X(31,134), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 3615 3616 {"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, 3617 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 3618 3619 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3620 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3621 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3622 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3623 3624 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3625 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3626 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3627 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3628 3629 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 3630 3631 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}}, 3632 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, 3633 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, 3634 3635 {"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}}, 3636 3637 {"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}}, 3638 3639 {"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}}, 3640 3641 {"stwx", X(31,151), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, 3642 {"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}}, 3643 3644 {"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3645 {"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3646 3647 {"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3648 {"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3649 3650 {"prtyw", X(31,154), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, 3651 3652 {"stdepx", X(31,157), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, 3653 3654 {"stwepx", X(31,159), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, 3655 3656 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, PPCNONE, {E}}, 3657 3658 {"dcbtls", X(31,166), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 3659 3660 {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, 3661 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 3662 3663 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 3664 3665 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}}, 3666 3667 {"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}}, 3668 3669 {"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}}, 3670 {"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, 3671 3672 {"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 3673 {"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 3674 3675 {"prtyd", X(31,186), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, 3676 3677 {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, 3678 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 3679 3680 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 3681 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 3682 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 3683 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 3684 3685 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 3686 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 3687 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 3688 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 3689 3690 {"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}}, 3691 3692 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, PPCNONE, {SR, RS}}, 3693 3694 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}}, 3695 3696 {"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, 3697 3698 {"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3699 {"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3700 3701 {"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3702 {"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 3703 3704 {"stbepx", X(31,223), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, 3705 3706 {"icblc", X(31,230), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 3707 3708 {"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, 3709 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 3710 3711 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 3712 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 3713 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 3714 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 3715 3716 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 3717 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 3718 3719 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 3720 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 3721 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 3722 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 3723 3724 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3725 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3726 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3727 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3728 3729 {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}}, 3730 {"icblce", X(31,238), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 3731 {"mtsrin", X(31,242), XRA_MASK, PPC32, PPCNONE, {RS, RB}}, 3732 {"mtsri", X(31,242), XRA_MASK, POWER32, PPCNONE, {RS, RB}}, 3733 3734 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}}, 3735 {"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}}, 3736 {"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}}, 3737 3738 {"stbux", X(31,247), X_MASK, COM, PPCNONE, {RS, RAS, RB}}, 3739 3740 {"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 3741 {"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 3742 3743 {"bpermd", X(31,252), X_MASK, POWER7, PPCNONE, {RA, RS, RB}}, 3744 3745 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 3746 3747 {"mfdcrx", X(31,259), X_MASK, BOOKE, PPCNONE, {RS, RA}}, 3748 3749 {"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}}, 3750 3751 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 3752 {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 3753 {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 3754 3755 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3756 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3757 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 3758 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 3759 3760 {"ehpriv", X(31,270), 0xffffffff, E500MC, PPCNONE, {0}}, 3761 3762 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPCNONE, {RB, L}}, 3763 3764 {"mfapidi", X(31,275), X_MASK, BOOKE, PPCNONE, {RT, RA}}, 3765 3766 {"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}}, 3767 {"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}}, 3768 3769 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}}, 3770 {"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}}, 3771 {"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}}, 3772 3773 {"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, 3774 3775 {"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, 3776 3777 {"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3778 {"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3779 3780 {"lhepx", X(31,287), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 3781 3782 {"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}}, 3783 3784 {"tlbie", X(31,306), XRTLRA_MASK, PPC, PPCNONE, {RB, L}}, 3785 {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}}, 3786 3787 {"eciwx", X(31,310), X_MASK, PPC, PPCNONE, {RT, RA, RB}}, 3788 3789 {"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, 3790 3791 {"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, 3792 3793 {"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3794 {"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 3795 3796 {"dcbtep", XRT(31,319,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 3797 3798 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3799 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3800 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3801 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3802 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3803 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3804 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3805 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3806 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3807 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3808 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3809 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3810 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3811 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3812 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3813 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3814 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3815 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3816 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3817 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3818 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3819 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3820 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3821 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3822 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3823 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3824 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3825 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3826 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3827 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3828 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3829 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3830 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3831 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3832 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, PPCNONE, {RT, SPR}}, 3833 3834 {"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 3835 {"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 3836 3837 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, 3838 3839 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}}, 3840 3841 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}}, 3842 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}}, 3843 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, PPCNONE, {RT}}, 3844 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, PPCNONE, {RT}}, 3845 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}}, 3846 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, PPCNONE, {RT}}, 3847 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, PPCNONE, {RT}}, 3848 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}}, 3849 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, PPCNONE, {RT}}, 3850 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, PPCNONE, {RT}}, 3851 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, PPCNONE, {RT}}, 3852 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}}, 3853 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, PPCNONE, {RT}}, 3854 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}}, 3855 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}}, 3856 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}}, 3857 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3858 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3859 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3860 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3861 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3862 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3863 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3864 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3865 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3866 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3867 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3868 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3869 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3870 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3871 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3872 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3873 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3874 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3875 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3876 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3877 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3878 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3879 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}}, 3880 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3881 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, PPCNONE, {RT, SPRG}}, 3882 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, 3883 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, 3884 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, 3885 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, 3886 {"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3887 {"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3888 {"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3889 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, PPCNONE, {RT}}, 3890 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, PPCNONE, {RT}}, 3891 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, PPCNONE, {RT}}, 3892 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, PPCNONE, {RT}}, 3893 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}}, 3894 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, PPCNONE, {RT}}, 3895 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3896 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, PPCNONE, {RT}}, 3897 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3898 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3899 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3900 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3901 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3902 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3903 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3904 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3905 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3906 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3907 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3908 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3909 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3910 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3911 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3912 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3913 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3914 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3915 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3916 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3917 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3918 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3919 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3920 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3921 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3922 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3923 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3924 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3925 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3926 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, PPCNONE, {RT}}, 3927 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, 3928 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, 3929 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, 3930 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, 3931 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}}, 3932 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, 3933 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}}, 3934 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, 3935 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}}, 3936 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}}, 3937 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}}, 3938 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3939 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3940 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3941 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3942 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3943 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3944 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 3945 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 3946 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 3947 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, 3948 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3949 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3950 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3951 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3952 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3953 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3954 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3955 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3956 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3957 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3958 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3959 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3960 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3961 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3962 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3963 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3964 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3965 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3966 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3967 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3968 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3969 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}}, 3970 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3971 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3972 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3973 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3974 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3975 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3976 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3977 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3978 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3979 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, PPCNONE, {RT}}, 3980 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}}, 3981 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}}, 3982 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}}, 3983 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}}, 3984 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3985 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3986 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3987 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3988 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3989 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3990 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}}, 3991 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3992 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}}, 3993 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}}, 3994 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3995 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}}, 3996 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3997 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3998 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}}, 3999 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4000 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4001 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4002 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4003 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4004 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4005 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4006 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4007 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4008 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4009 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}}, 4010 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4011 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4012 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4013 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4014 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}}, 4015 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4016 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4017 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}}, 4018 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4019 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}}, 4020 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4021 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}}, 4022 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4023 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}}, 4024 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}}, 4025 {"mfspr", X(31,339), X_MASK, COM, PPCNONE, {RT, SPR}}, 4026 4027 {"lwax", X(31,341), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}}, 4028 4029 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, 4030 4031 {"lhax", X(31,343), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, 4032 4033 {"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, 4034 4035 {"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, 4036 {"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, 4037 4038 {"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4039 {"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4040 4041 {"tlbia", X(31,370), 0xffffffff, PPC, PPCNONE, {0}}, 4042 4043 {"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, PPCNONE, {RT}}, 4044 {"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, PPCNONE, {RT}}, 4045 {"mftb", X(31,371), X_MASK, CLASSIC, POWER7, {RT, TBR}}, 4046 4047 {"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}}, 4048 4049 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, 4050 4051 {"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, 4052 4053 {"popcntw", X(31,378), XRB_MASK, POWER7, PPCNONE, {RA, RS}}, 4054 4055 {"mtdcrx", X(31,387), X_MASK, BOOKE, PPCNONE, {RA, RS}}, 4056 4057 {"dcblc", X(31,390), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 4058 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4059 4060 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4061 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4062 {"divweu", XO(31,395,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4063 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4064 4065 {"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 4066 4067 {"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, 4068 4069 {"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, 4070 4071 {"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 4072 {"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 4073 4074 {"sthepx", X(31,415), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, 4075 4076 {"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}}, 4077 4078 {"divde", XO(31,425,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4079 {"divde.", XO(31,425,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4080 {"divwe", XO(31,427,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4081 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4082 4083 {"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}}, 4084 4085 {"ecowx", X(31,438), X_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4086 4087 {"sthux", X(31,439), X_MASK, COM, PPCNONE, {RS, RAS, RB}}, 4088 4089 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}}, 4090 4091 {"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, 4092 {"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 4093 {"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, 4094 {"or.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 4095 4096 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4097 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4098 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4099 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4100 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4101 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4102 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4103 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4104 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4105 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4106 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4107 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4108 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4109 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4110 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4111 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4112 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4113 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4114 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4115 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4116 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4117 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4118 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4119 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4120 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4121 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4122 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4123 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4124 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4125 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4126 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4127 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4128 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4129 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4130 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, PPCNONE, {SPR, RS}}, 4131 4132 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}}, 4133 4134 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4135 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4136 4137 {"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4138 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4139 4140 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}}, 4141 4142 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}}, 4143 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}}, 4144 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, PPCNONE, {RS}}, 4145 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, PPCNONE, {RS}}, 4146 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}}, 4147 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, PPCNONE, {RS}}, 4148 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, PPCNONE, {RS}}, 4149 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, PPCNONE, {RS}}, 4150 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, PPCNONE, {RS}}, 4151 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}}, 4152 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}}, 4153 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, PPCNONE, {RS}}, 4154 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, PPCNONE, {RS}}, 4155 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, PPCNONE, {RS}}, 4156 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}}, 4157 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4158 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4159 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4160 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4161 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4162 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4163 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4164 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4165 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4166 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4167 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4168 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4169 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4170 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4171 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4172 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4173 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4174 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4175 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4176 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4177 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4178 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4179 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}}, 4180 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}}, 4181 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4182 {"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, PPCNONE, {SPRG, RS}}, 4183 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, PPCNONE, {RS}}, 4184 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, PPCNONE, {RS}}, 4185 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, PPCNONE, {RS}}, 4186 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, PPCNONE, {RS}}, 4187 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, 4188 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, 4189 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, 4190 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, 4191 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}}, 4192 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, PPCNONE, {RS}}, 4193 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}}, 4194 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}}, 4195 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4196 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4197 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4198 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4199 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4200 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4201 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4202 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4203 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4204 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4205 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4206 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4207 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4208 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4209 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4210 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4211 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4212 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4213 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4214 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4215 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4216 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4217 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4218 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4219 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4220 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4221 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4222 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4223 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4224 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, PPCNONE, {RS}}, 4225 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, 4226 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, 4227 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, 4228 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, 4229 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}}, 4230 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, 4231 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}}, 4232 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, 4233 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}}, 4234 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}}, 4235 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}}, 4236 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, 4237 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, 4238 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, 4239 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4240 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4241 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4242 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4243 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4244 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4245 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4246 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4247 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4248 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, PPCNONE, {RS}}, 4249 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}}, 4250 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}}, 4251 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}}, 4252 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}}, 4253 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4254 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4255 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4256 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4257 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4258 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4259 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}}, 4260 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4261 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}}, 4262 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}}, 4263 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4264 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4265 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4266 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4267 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4268 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4269 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4270 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4271 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4272 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4273 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4274 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4275 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4276 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4277 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4278 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}}, 4279 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4280 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4281 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4282 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4283 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4284 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4285 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4286 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4287 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4288 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4289 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4290 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4291 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4292 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}}, 4293 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}}, 4294 {"mtspr", X(31,467), X_MASK, COM, PPCNONE, {SPR, RS}}, 4295 4296 {"dcbi", X(31,470), XRT_MASK, PPC, PPCNONE, {RA, RB}}, 4297 4298 {"nand", XRC(31,476,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 4299 {"nand.", XRC(31,476,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, 4300 4301 {"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, 4302 4303 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCNONE, {RT, RA, RB}}, 4304 4305 {"icbtls", X(31,486), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 4306 4307 {"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, 4308 4309 {"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, 4310 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, 4311 4312 {"divd", XO(31,489,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4313 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4314 4315 {"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4316 {"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4317 4318 {"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, 4319 4320 {"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}}, 4321 4322 {"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}}, 4323 4324 {"popcntd", X(31,506), XRB_MASK, POWER7, PPCNONE, {RA, RS}}, 4325 4326 {"cmpb", X(31,508), X_MASK, POWER6, PPCNONE, {RA, RS, RB}}, 4327 4328 {"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}}, 4329 4330 {"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 4331 4332 {"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}}, 4333 4334 {"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, 4335 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4336 4337 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4338 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4339 {"subco", XO(31,8,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, 4340 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4341 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4342 {"subco.", XO(31,8,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, 4343 4344 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4345 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4346 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4347 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4348 4349 {"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}}, 4350 4351 {"ldbrx", X(31,532), X_MASK, CELL|POWER7, PPCNONE, {RT, RA0, RB}}, 4352 4353 {"lswx", X(31,533), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, 4354 {"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4355 4356 {"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, 4357 {"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4358 4359 {"lfsx", X(31,535), X_MASK, COM, PPCNONE, {FRT, RA0, RB}}, 4360 4361 {"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, 4362 {"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, 4363 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, 4364 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, 4365 4366 {"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4367 {"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4368 4369 {"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, 4370 {"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, 4371 4372 {"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4373 {"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4374 4375 {"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 4376 4377 {"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}}, 4378 4379 {"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, 4380 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4381 4382 {"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4383 {"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, 4384 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4385 {"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, 4386 4387 {"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}}, 4388 4389 {"lfsux", X(31,567), X_MASK, COM, PPCNONE, {FRT, RAS, RB}}, 4390 4391 {"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 4392 4393 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4394 4395 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, 4396 4397 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, PPCNONE, {RT, SR}}, 4398 4399 {"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}}, 4400 {"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}}, 4401 4402 {"msync", X(31,598), 0xffffffff, BOOKE, PPCNONE, {0}}, 4403 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, PPCNONE, {0}}, 4404 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, 4405 {"sync", X(31,598), XSYNC_MASK, PPCCOM, PPCNONE, {LS}}, 4406 {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}}, 4407 4408 {"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}}, 4409 4410 {"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}}, 4411 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, 4412 4413 {"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, 4414 4415 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4416 4417 {"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}}, 4418 {"nego.", XO(31,104,1,1), XORB_MASK, COM, PPCNONE, {RT, RA}}, 4419 4420 {"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4421 {"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4422 4423 {"lxsdux", X(31,620), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, 4424 4425 {"mfsri", X(31,627), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4426 4427 {"dclst", X(31,630), XRB_MASK, PWRCOM, PPCNONE, {RS, RA}}, 4428 4429 {"lfdux", X(31,631), X_MASK, COM, PPCNONE, {FRT, RAS, RB}}, 4430 4431 {"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, 4432 4433 {"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, 4434 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4435 4436 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4437 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4438 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4439 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4440 4441 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4442 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4443 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4444 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4445 4446 {"mfsrin", X(31,659), XRA_MASK, PPC32, PPCNONE, {RT, RB}}, 4447 4448 {"stdbrx", X(31,660), X_MASK, CELL|POWER7, PPCNONE, {RS, RA0, RB}}, 4449 4450 {"stswx", X(31,661), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, 4451 {"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, 4452 4453 {"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, 4454 {"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, 4455 4456 {"stfsx", X(31,663), X_MASK, COM, PPCNONE, {FRS, RA0, RB}}, 4457 4458 {"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4459 {"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4460 4461 {"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4462 {"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4463 4464 {"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, 4465 4466 {"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, 4467 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4468 4469 {"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, 4470 4471 {"stfsux", X(31,695), X_MASK, COM, PPCNONE, {FRS, RAS, RB}}, 4472 4473 {"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 4474 {"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 4475 4476 {"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, 4477 4478 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4479 4480 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, 4481 4482 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 4483 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 4484 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 4485 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 4486 4487 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 4488 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 4489 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 4490 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 4491 4492 {"stswi", X(31,725), X_MASK, PPCCOM, PPCNONE, {RS, RA0, NB}}, 4493 {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}}, 4494 4495 {"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, 4496 4497 {"stfdx", X(31,727), X_MASK, COM, PPCNONE, {FRS, RA0, RB}}, 4498 4499 {"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4500 {"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4501 4502 {"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4503 {"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4504 4505 {"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, 4506 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, 4507 4508 {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, 4509 4510 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4511 4512 {"stxsdux", X(31,748), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, 4513 4514 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 4515 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 4516 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 4517 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 4518 4519 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4520 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4521 4522 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 4523 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 4524 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, 4525 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, 4526 4527 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4528 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4529 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4530 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4531 4532 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, PPCNONE, {RA, RB}}, 4533 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, 4534 4535 {"stfdux", X(31,759), X_MASK, COM, PPCNONE, {FRS, RAS, RB}}, 4536 4537 {"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 4538 {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 4539 4540 {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, 4541 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4542 4543 {"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4544 {"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4545 4546 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4547 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4548 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, 4549 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4550 4551 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, 4552 4553 {"tlbivax", X(31,786), XRT_MASK, BOOKE, PPCNONE, {RA, RB}}, 4554 {"tlbilx", X(31,787), X_MASK, E500MC, PPCNONE, {T, RA0, RB}}, 4555 {"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, PPCNONE, {0}}, 4556 {"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, PPCNONE, {0}}, 4557 {"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, PPCNONE, {RA0, RB}}, 4558 4559 {"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, 4560 4561 {"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, 4562 4563 {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB}}, 4564 {"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, 4565 4566 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, 4567 {"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, 4568 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, 4569 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, 4570 4571 {"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, 4572 {"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, 4573 4574 {"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}}, 4575 4576 {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, 4577 4578 {"lxvw4ux", X(31,812), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, 4579 4580 {"rac", X(31,818), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, 4581 4582 {"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, 4583 4584 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}}, 4585 4586 {"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, 4587 4588 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, 4589 {"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, 4590 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, 4591 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, 4592 4593 {"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, 4594 {"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, 4595 4596 {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4597 {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4598 4599 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, 4600 4601 {"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, 4602 4603 {"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, 4604 4605 {"mbar", X(31,854), X_MASK, BOOKE, PPCNONE, {MO}}, 4606 {"eieio", X(31,854), 0xffffffff, PPC, PPCNONE, {0}}, 4607 4608 {"lfiwax", X(31,855), X_MASK, POWER6, PPCNONE, {FRT, RA0, RB}}, 4609 4610 {"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, 4611 {"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, 4612 4613 {"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4614 {"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, 4615 4616 {"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, 4617 4618 {"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, 4619 4620 {"lfiwzx", X(31,887), X_MASK, POWER7, PPCNONE, {FRT, RA0, RB}}, 4621 4622 {"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, 4623 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, 4624 4625 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4626 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4627 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4628 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4629 4630 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, 4631 4632 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}}, 4633 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}}, 4634 4635 {"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, 4636 4637 {"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, 4638 4639 {"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, 4640 4641 {"stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB}}, 4642 {"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, 4643 4644 {"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4645 {"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4646 4647 {"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4648 {"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, 4649 4650 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, 4651 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, 4652 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, 4653 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, 4654 4655 {"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, 4656 4657 {"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, 4658 4659 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4660 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4661 {"divweo", XO(31,427,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4662 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, 4663 4664 {"stxvw4ux", X(31,940), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, 4665 4666 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, 4667 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, 4668 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}}, 4669 4670 {"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, 4671 4672 {"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, 4673 4674 {"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 4675 {"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, 4676 4677 {"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}}, 4678 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}}, 4679 4680 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}}, 4681 4682 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4683 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4684 4685 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4686 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4687 4688 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, 4689 4690 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, 4691 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, 4692 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}}, 4693 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPCNONE, {RB}}, 4694 4695 {"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, 4696 4697 {"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA, RB}}, 4698 4699 {"stfiwx", X(31,983), X_MASK, PPC, PPCNONE, {FRS, RA0, RB}}, 4700 4701 {"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, 4702 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, 4703 4704 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, 4705 4706 {"icread", X(31,998), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}}, 4707 4708 {"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, 4709 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, 4710 4711 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4712 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, 4713 4714 {"divwo", XO(31,491,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4715 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, 4716 4717 {"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, 4718 4719 {"tlbli", X(31,1010), XRTRA_MASK, PPC, PPCNONE, {RB}}, 4720 4721 {"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, 4722 4723 {"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}}, 4724 {"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}}, 4725 4726 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, 4727 4728 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, PPCNONE, {RA, RB}}, 4729 {"dcbzl", XOPL(31,1014,1), XRT_MASK, PPCCOM|E500MC,POWER4, {RA, RB}}, 4730 4731 {"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}}, 4732 {"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}}, 4733 {"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}}, 4734 4735 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, 4736 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, 4737 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}}, 4738 4739 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}}, 4740 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}}, 4741 {"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}}, 4742 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}}, 4743 4744 {"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}}, 4745 {"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, 4746 4747 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}}, 4748 {"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, 4749 4750 {"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, 4751 4752 {"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, 4753 4754 {"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}}, 4755 {"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, 4756 4757 {"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}}, 4758 {"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, 4759 4760 {"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}}, 4761 4762 {"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}}, 4763 4764 {"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, 4765 4766 {"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, 4767 4768 {"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, 4769 4770 {"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, 4771 4772 {"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}}, 4773 4774 {"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}}, 4775 4776 {"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}}, 4777 {"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, 4778 4779 {"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}}, 4780 {"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, 4781 4782 {"lfs", OP(48), OP_MASK, COM, PPCNONE, {FRT, D, RA0}}, 4783 4784 {"lfsu", OP(49), OP_MASK, COM, PPCNONE, {FRT, D, RAS}}, 4785 4786 {"lfd", OP(50), OP_MASK, COM, PPCNONE, {FRT, D, RA0}}, 4787 4788 {"lfdu", OP(51), OP_MASK, COM, PPCNONE, {FRT, D, RAS}}, 4789 4790 {"stfs", OP(52), OP_MASK, COM, PPCNONE, {FRS, D, RA0}}, 4791 4792 {"stfsu", OP(53), OP_MASK, COM, PPCNONE, {FRS, D, RAS}}, 4793 4794 {"stfd", OP(54), OP_MASK, COM, PPCNONE, {FRS, D, RA0}}, 4795 4796 {"stfdu", OP(55), OP_MASK, COM, PPCNONE, {FRS, D, RAS}}, 4797 4798 {"lq", OP(56), OP_MASK, POWER4, PPCNONE, {RTQ, DQ, RAQ}}, 4799 4800 {"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, 4801 4802 {"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, 4803 4804 {"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}}, 4805 4806 {"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, 4807 4808 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, 4809 4810 {"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, 4811 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}}, 4812 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, 4813 4814 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4815 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4816 4817 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, 4818 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, 4819 4820 {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, 4821 {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, 4822 4823 {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, 4824 {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, 4825 4826 {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, 4827 {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, 4828 4829 {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}}, 4830 {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}}, 4831 4832 {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, 4833 {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, 4834 {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4835 {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4836 4837 {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}}, 4838 {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}}, 4839 4840 {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, 4841 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, 4842 {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4843 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4844 4845 {"fmsubs", A(59,28,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 4846 {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 4847 4848 {"fmadds", A(59,29,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 4849 {"fmadds.", A(59,29,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 4850 4851 {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 4852 {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 4853 4854 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 4855 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 4856 4857 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4858 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4859 4860 {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, 4861 {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, 4862 4863 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, 4864 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, 4865 4866 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}}, 4867 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}}, 4868 4869 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, 4870 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, 4871 4872 {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, 4873 {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, 4874 4875 {"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, 4876 4877 {"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, 4878 {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}}, 4879 {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}}, 4880 4881 {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, 4882 {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, 4883 4884 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 4885 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 4886 4887 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 4888 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 4889 4890 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, 4891 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, 4892 4893 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 4894 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 4895 4896 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4897 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4898 4899 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4900 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4901 4902 {"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, 4903 4904 {"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, 4905 4906 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 4907 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 4908 4909 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4910 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4911 4912 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, 4913 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, 4914 4915 {"fcfids", XRC(59,846,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4916 {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4917 4918 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4919 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 4920 4921 {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4922 {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 4923 4924 {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}}, 4925 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}}, 4926 {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}}, 4927 {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4928 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, 4929 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4930 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}}, 4931 {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4932 {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4933 {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4934 {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, 4935 {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4936 {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4937 {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, 4938 {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4939 {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4940 {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4941 {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4942 {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4943 {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, 4944 {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4945 {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4946 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4947 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4948 {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4949 {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4950 {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4951 {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4952 {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4953 {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4954 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4955 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4956 {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4957 {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4958 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4959 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4960 {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4961 {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4962 {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4963 {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4964 {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4965 {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, 4966 {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4967 {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4968 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4969 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4970 {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4971 {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4972 {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4973 {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, 4974 {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4975 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4976 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4977 {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4978 {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4979 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4980 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4981 {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4982 {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4983 {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4984 {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, 4985 {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4986 {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4987 {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4988 {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4989 {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4990 {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4991 {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4992 {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4993 {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4994 {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4995 {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 4996 {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4997 {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4998 {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 4999 {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}}, 5000 {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5001 {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5002 {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5003 {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5004 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, 5005 {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5006 {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5007 {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5008 {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5009 {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5010 {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5011 {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5012 {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5013 {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5014 {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5015 {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5016 {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5017 {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5018 {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5019 {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, 5020 {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5021 {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5022 {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5023 {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5024 {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5025 {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5026 {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5027 {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5028 {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5029 {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5030 {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5031 {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5032 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, 5033 {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5034 {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, 5035 {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5036 {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5037 {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5038 {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, 5039 {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5040 {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5041 {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5042 {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5043 {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5044 {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5045 {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5046 {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5047 {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5048 {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5049 {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5050 {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5051 {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5052 {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5053 {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5054 {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5055 {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5056 {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5057 {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5058 {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5059 {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5060 {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5061 {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5062 {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5063 {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5064 {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, 5065 5066 {"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, 5067 5068 {"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, 5069 5070 {"stfdp", OP(61), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}}, 5071 5072 {"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, 5073 5074 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, 5075 5076 {"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}}, 5077 {"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}}, 5078 {"stq", DSO(62,2), DS_MASK, POWER4, PPCNONE, {RSQ, DS, RA0}}, 5079 5080 {"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}}, 5081 5082 {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5083 {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5084 5085 {"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, 5086 {"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, 5087 5088 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5089 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5090 5091 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5092 {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5093 5094 {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, 5095 {"fcir", XRC(63,14,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, 5096 {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, 5097 {"fcir.", XRC(63,14,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, 5098 5099 {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, 5100 {"fcirz", XRC(63,15,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, 5101 {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, 5102 {"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, 5103 5104 {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, 5105 {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, 5106 {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, 5107 {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, 5108 5109 {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, 5110 {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, 5111 {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, 5112 {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, 5113 5114 {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, 5115 {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, 5116 {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, 5117 {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, 5118 5119 {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}}, 5120 {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}}, 5121 5122 {"fsel", A(63,23,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 5123 {"fsel.", A(63,23,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, 5124 5125 {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, 5126 {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, 5127 {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5128 {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5129 5130 {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}}, 5131 {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, 5132 {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}}, 5133 {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, 5134 5135 {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, 5136 {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, 5137 {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5138 {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5139 5140 {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5141 {"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5142 {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5143 {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5144 5145 {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5146 {"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5147 {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5148 {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5149 5150 {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5151 {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5152 {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5153 {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5154 5155 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5156 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5157 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5158 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, 5159 5160 {"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}}, 5161 5162 {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5163 {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5164 5165 {"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, 5166 {"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, 5167 5168 {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}}, 5169 {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}}, 5170 5171 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5172 {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5173 5174 {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, 5175 5176 {"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, 5177 {"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, 5178 5179 {"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}}, 5180 {"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}}, 5181 5182 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}}, 5183 {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}}, 5184 5185 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5186 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5187 5188 {"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, 5189 {"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, 5190 5191 {"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, 5192 {"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, 5193 5194 {"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}}, 5195 5196 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, 5197 5198 {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}}, 5199 {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}}, 5200 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}}, 5201 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}}, 5202 5203 {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5204 {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5205 5206 {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5207 {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5208 {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5209 {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5210 5211 {"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}}, 5212 5213 {"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, 5214 {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}}, 5215 {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}}, 5216 5217 {"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, 5218 {"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, 5219 5220 {"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5221 {"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5222 5223 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5224 {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, 5225 5226 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5227 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5228 5229 {"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, 5230 {"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, 5231 5232 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5233 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5234 5235 {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, 5236 {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, 5237 {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, 5238 {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, 5239 {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, 5240 {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, 5241 {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, 5242 {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, 5243 5244 {"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5245 {"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5246 5247 {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5248 {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5249 5250 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCNONE, {FRT}}, 5251 {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCNONE, {FRT}}, 5252 5253 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, 5254 5255 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, 5256 5257 {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6, {FLM, FRB}}, 5258 {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}}, 5259 {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6, {FLM, FRB}}, 5260 {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}}, 5261 5262 {"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5263 {"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5264 5265 {"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5266 {"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, 5267 5268 {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, 5269 {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, 5270 5271 {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, 5272 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, 5273 5274 {"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, 5275 {"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, 5276 5277 {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, 5278 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, 5279 5280 {"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5281 {"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, 5282 5283 {"fctidu", XRC(63,942,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5284 {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5285 5286 {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5287 {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5288 5289 {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5290 {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, 5291 }; 5292 5293 const int powerpc_num_opcodes = 5294 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); 5295 5296 /* The macro table. This is only used by the assembler. */ 5297 5298 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 5299 when x=0; 32-x when x is between 1 and 31; are negative if x is 5300 negative; and are 32 or more otherwise. This is what you want 5301 when, for instance, you are emulating a right shift by a 5302 rotate-left-and-mask, because the underlying instructions support 5303 shifts of size 0 but not shifts of size 32. By comparison, when 5304 extracting x bits from some word you want to use just 32-x, because 5305 the underlying instructions don't support extracting 0 bits but do 5306 support extracting the whole word (32 bits in this case). */ 5307 5308 const struct powerpc_macro powerpc_macros[] = { 5309 {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, 5310 {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, 5311 {"extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)"}, 5312 {"extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)"}, 5313 {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, 5314 {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, 5315 {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, 5316 {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, 5317 {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, 5318 {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, 5319 {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, 5320 {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, 5321 {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, 5322 {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, 5323 {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, 5324 {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, 5325 5326 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 5327 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 5328 {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 5329 {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 5330 {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 5331 {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 5332 {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 5333 {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 5334 {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 5335 {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 5336 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 5337 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, 5338 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 5339 {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, 5340 {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 5341 {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 5342 {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 5343 {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 5344 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, 5345 {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, 5346 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, 5347 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, 5348 }; 5349 5350 const int powerpc_num_macros = 5351 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); 5352