1 /* ppc-dis.c -- Disassemble PowerPC instructions 2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 3 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of the GNU opcodes library. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the 20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 #include <stdio.h> 25 #include "dis-asm.h" 26 #include "elf-bfd.h" 27 #include "elf/ppc.h" 28 #include "opintl.h" 29 #include "opcode/ppc.h" 30 31 /* This file provides several disassembler functions, all of which use 32 the disassembler interface defined in dis-asm.h. Several functions 33 are provided because this file handles disassembly for the PowerPC 34 in both big and little endian mode and also for the POWER (RS/6000) 35 chip. */ 36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, 37 ppc_cpu_t); 38 39 struct dis_private 40 { 41 /* Stash the result of parsing disassembler_options here. */ 42 ppc_cpu_t dialect; 43 } private; 44 45 #define POWERPC_DIALECT(INFO) \ 46 (((struct dis_private *) ((INFO)->private_data))->dialect) 47 48 struct ppc_mopt { 49 const char *opt; 50 ppc_cpu_t cpu; 51 ppc_cpu_t sticky; 52 }; 53 54 struct ppc_mopt ppc_opts[] = { 55 { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403), 56 0 }, 57 { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405), 58 0 }, 59 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 60 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), 61 0 }, 62 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 63 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), 64 0 }, 65 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440 66 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), 67 0 }, 68 { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601), 69 0 }, 70 { "603", (PPC_OPCODE_PPC), 71 0 }, 72 { "604", (PPC_OPCODE_PPC), 73 0 }, 74 { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64), 75 0 }, 76 { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 77 0 }, 78 { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 79 0 }, 80 { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 81 0 }, 82 { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), 83 0 }, 84 { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS) 85 , 0 }, 86 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4 87 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64 88 | PPC_OPCODE_A2), 89 0 }, 90 { "altivec", (PPC_OPCODE_PPC), 91 PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 }, 92 { "any", 0, 93 PPC_OPCODE_ANY }, 94 { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), 95 0 }, 96 { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), 97 0 }, 98 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 99 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), 100 0 }, 101 { "com", (PPC_OPCODE_COMMON), 102 0 }, 103 { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300), 104 0 }, 105 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 106 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 107 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 108 | PPC_OPCODE_E500), 109 0 }, 110 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 111 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 112 | PPC_OPCODE_E500MC), 113 0 }, 114 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 115 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 116 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 117 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 118 0 }, 119 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 120 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 121 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 122 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 123 | PPC_OPCODE_POWER7), 124 0 }, 125 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 126 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 127 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC 128 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 129 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 130 0 }, 131 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 132 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 133 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 134 | PPC_OPCODE_E500), 135 0 }, 136 { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), 137 0 }, 138 { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), 139 0 }, 140 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 141 | PPC_OPCODE_POWER5), 142 0 }, 143 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 144 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), 145 0 }, 146 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 147 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 148 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 149 0 }, 150 { "ppc", (PPC_OPCODE_PPC), 151 0 }, 152 { "ppc32", (PPC_OPCODE_PPC), 153 0 }, 154 { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64), 155 0 }, 156 { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE), 157 0 }, 158 { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS), 159 0 }, 160 { "pwr", (PPC_OPCODE_POWER), 161 0 }, 162 { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), 163 0 }, 164 { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), 165 0 }, 166 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 167 | PPC_OPCODE_POWER5), 168 0 }, 169 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 170 | PPC_OPCODE_POWER5), 171 0 }, 172 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 173 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), 174 0 }, 175 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 176 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 177 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 178 0 }, 179 { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), 180 0 }, 181 { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), 182 PPC_OPCODE_SPE }, 183 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR 184 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), 185 0 }, 186 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE), 187 PPC_OPCODE_VLE }, 188 { "vsx", (PPC_OPCODE_PPC), 189 PPC_OPCODE_VSX }, 190 }; 191 192 /* Switch between Booke and VLE dialects for interlinked dumps. */ 193 static ppc_cpu_t 194 get_powerpc_dialect (struct disassemble_info *info) 195 { 196 ppc_cpu_t dialect = 0; 197 198 dialect = POWERPC_DIALECT (info); 199 200 /* Disassemble according to the section headers flags for VLE-mode. */ 201 if (dialect & PPC_OPCODE_VLE 202 && info->section->owner != NULL 203 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour 204 && elf_object_id (info->section->owner) == PPC32_ELF_DATA 205 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0) 206 return dialect; 207 else 208 return dialect & ~ PPC_OPCODE_VLE; 209 } 210 211 /* Handle -m and -M options that set cpu type, and .machine arg. */ 212 213 ppc_cpu_t 214 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg) 215 { 216 unsigned int i; 217 218 for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) 219 if (strcmp (ppc_opts[i].opt, arg) == 0) 220 { 221 if (ppc_opts[i].sticky) 222 { 223 *sticky |= ppc_opts[i].sticky; 224 if ((ppc_cpu & ~*sticky) != 0) 225 break; 226 } 227 ppc_cpu = ppc_opts[i].cpu; 228 break; 229 } 230 if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0])) 231 return 0; 232 233 ppc_cpu |= *sticky; 234 return ppc_cpu; 235 } 236 237 /* Determine which set of machines to disassemble for. */ 238 239 static void 240 powerpc_init_dialect (struct disassemble_info *info) 241 { 242 ppc_cpu_t dialect = 0; 243 ppc_cpu_t sticky = 0; 244 char *arg; 245 struct dis_private *priv = calloc (sizeof (*priv), 1); 246 247 if (priv == NULL) 248 priv = &private; 249 250 switch (info->mach) 251 { 252 case bfd_mach_ppc_403: 253 case bfd_mach_ppc_403gc: 254 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403); 255 break; 256 case bfd_mach_ppc_405: 257 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405); 258 break; 259 case bfd_mach_ppc_601: 260 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_601); 261 break; 262 case bfd_mach_ppc_a35: 263 case bfd_mach_ppc_rs64ii: 264 case bfd_mach_ppc_rs64iii: 265 dialect = (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_64); 266 break; 267 case bfd_mach_ppc_e500: 268 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 269 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 270 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 271 | PPC_OPCODE_E500); 272 break; 273 case bfd_mach_ppc_e500mc: 274 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 275 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 276 | PPC_OPCODE_E500MC); 277 break; 278 case bfd_mach_ppc_e500mc64: 279 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 280 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 281 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 282 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7); 283 break; 284 case bfd_mach_ppc_e5500: 285 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 286 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 287 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 288 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 289 | PPC_OPCODE_POWER7); 290 break; 291 case bfd_mach_ppc_e6500: 292 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 293 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 294 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC 295 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 296 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7); 297 break; 298 case bfd_mach_ppc_titan: 299 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR 300 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN); 301 break; 302 case bfd_mach_ppc_vle: 303 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE); 304 break; 305 default: 306 dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 307 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 308 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX 309 | PPC_OPCODE_ANY); 310 } 311 312 arg = info->disassembler_options; 313 while (arg != NULL) 314 { 315 ppc_cpu_t new_cpu = 0; 316 char *end = strchr (arg, ','); 317 318 if (end != NULL) 319 *end = 0; 320 321 if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0) 322 dialect = new_cpu; 323 else if (strcmp (arg, "32") == 0) 324 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; 325 else if (strcmp (arg, "64") == 0) 326 dialect |= PPC_OPCODE_64; 327 else 328 fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg); 329 330 if (end != NULL) 331 *end++ = ','; 332 arg = end; 333 } 334 335 info->private_data = priv; 336 POWERPC_DIALECT(info) = dialect; 337 } 338 339 #define PPC_OPCD_SEGS 64 340 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; 341 #define VLE_OPCD_SEGS 32 342 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; 343 344 /* Calculate opcode table indices to speed up disassembly, 345 and init dialect. */ 346 347 void 348 disassemble_init_powerpc (struct disassemble_info *info) 349 { 350 int i; 351 unsigned short last; 352 353 i = powerpc_num_opcodes; 354 while (--i >= 0) 355 { 356 unsigned op = PPC_OP (powerpc_opcodes[i].opcode); 357 358 powerpc_opcd_indices[op] = i; 359 } 360 361 last = powerpc_num_opcodes; 362 for (i = PPC_OPCD_SEGS; i > 0; --i) 363 { 364 if (powerpc_opcd_indices[i] == 0) 365 powerpc_opcd_indices[i] = last; 366 last = powerpc_opcd_indices[i]; 367 } 368 369 i = vle_num_opcodes; 370 while (--i >= 0) 371 { 372 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask); 373 unsigned seg = VLE_OP_TO_SEG (op); 374 375 vle_opcd_indices[seg] = i; 376 } 377 378 last = vle_num_opcodes; 379 for (i = VLE_OPCD_SEGS; i > 0; --i) 380 { 381 if (vle_opcd_indices[i] == 0) 382 vle_opcd_indices[i] = last; 383 last = vle_opcd_indices[i]; 384 } 385 386 if (info->arch == bfd_arch_powerpc) 387 powerpc_init_dialect (info); 388 } 389 390 /* Print a big endian PowerPC instruction. */ 391 392 int 393 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) 394 { 395 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info)); 396 } 397 398 /* Print a little endian PowerPC instruction. */ 399 400 int 401 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) 402 { 403 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info)); 404 } 405 406 /* Print a POWER (RS/6000) instruction. */ 407 408 int 409 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) 410 { 411 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); 412 } 413 414 /* Extract the operand value from the PowerPC or POWER instruction. */ 415 416 static long 417 operand_value_powerpc (const struct powerpc_operand *operand, 418 unsigned long insn, ppc_cpu_t dialect) 419 { 420 long value; 421 int invalid; 422 /* Extract the value from the instruction. */ 423 if (operand->extract) 424 value = (*operand->extract) (insn, dialect, &invalid); 425 else 426 { 427 if (operand->shift >= 0) 428 value = (insn >> operand->shift) & operand->bitm; 429 else 430 value = (insn << -operand->shift) & operand->bitm; 431 if ((operand->flags & PPC_OPERAND_SIGNED) != 0) 432 { 433 /* BITM is always some number of zeros followed by some 434 number of ones, followed by some number of zeros. */ 435 unsigned long top = operand->bitm; 436 /* top & -top gives the rightmost 1 bit, so this 437 fills in any trailing zeros. */ 438 top |= (top & -top) - 1; 439 top &= ~(top >> 1); 440 value = (value ^ top) - top; 441 } 442 } 443 444 return value; 445 } 446 447 /* Determine whether the optional operand(s) should be printed. */ 448 449 static int 450 skip_optional_operands (const unsigned char *opindex, 451 unsigned long insn, ppc_cpu_t dialect) 452 { 453 const struct powerpc_operand *operand; 454 455 for (; *opindex != 0; opindex++) 456 { 457 operand = &powerpc_operands[*opindex]; 458 if ((operand->flags & PPC_OPERAND_NEXT) != 0 459 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 460 && operand_value_powerpc (operand, insn, dialect) != 0)) 461 return 0; 462 } 463 464 return 1; 465 } 466 467 /* Find a match for INSN in the opcode table, given machine DIALECT. 468 A DIALECT of -1 is special, matching all machine opcode variations. */ 469 470 static const struct powerpc_opcode * 471 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect) 472 { 473 const struct powerpc_opcode *opcode; 474 const struct powerpc_opcode *opcode_end; 475 unsigned long op; 476 477 /* Get the major opcode of the instruction. */ 478 op = PPC_OP (insn); 479 480 /* Find the first match in the opcode table for this major opcode. */ 481 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1]; 482 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op]; 483 opcode < opcode_end; 484 ++opcode) 485 { 486 const unsigned char *opindex; 487 const struct powerpc_operand *operand; 488 int invalid; 489 490 if ((insn & opcode->mask) != opcode->opcode 491 || (dialect != (ppc_cpu_t) -1 492 && ((opcode->flags & dialect) == 0 493 || (opcode->deprecated & dialect) != 0))) 494 continue; 495 496 /* Check validity of operands. */ 497 invalid = 0; 498 for (opindex = opcode->operands; *opindex != 0; opindex++) 499 { 500 operand = powerpc_operands + *opindex; 501 if (operand->extract) 502 (*operand->extract) (insn, dialect, &invalid); 503 } 504 if (invalid) 505 continue; 506 507 return opcode; 508 } 509 510 return NULL; 511 } 512 513 /* Find a match for INSN in the VLE opcode table. */ 514 515 static const struct powerpc_opcode * 516 lookup_vle (unsigned long insn) 517 { 518 const struct powerpc_opcode *opcode; 519 const struct powerpc_opcode *opcode_end; 520 unsigned op, seg; 521 522 op = PPC_OP (insn); 523 if (op >= 0x20 && op <= 0x37) 524 { 525 /* This insn has a 4-bit opcode. */ 526 op &= 0x3c; 527 } 528 seg = VLE_OP_TO_SEG (op); 529 530 /* Find the first match in the opcode table for this major opcode. */ 531 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1]; 532 for (opcode = vle_opcodes + vle_opcd_indices[seg]; 533 opcode < opcode_end; 534 ++opcode) 535 { 536 unsigned long table_opcd = opcode->opcode; 537 unsigned long table_mask = opcode->mask; 538 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); 539 unsigned long insn2; 540 const unsigned char *opindex; 541 const struct powerpc_operand *operand; 542 int invalid; 543 544 insn2 = insn; 545 if (table_op_is_short) 546 insn2 >>= 16; 547 if ((insn2 & table_mask) != table_opcd) 548 continue; 549 550 /* Check validity of operands. */ 551 invalid = 0; 552 for (opindex = opcode->operands; *opindex != 0; ++opindex) 553 { 554 operand = powerpc_operands + *opindex; 555 if (operand->extract) 556 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); 557 } 558 if (invalid) 559 continue; 560 561 return opcode; 562 } 563 564 return NULL; 565 } 566 567 /* Print a PowerPC or POWER instruction. */ 568 569 static int 570 print_insn_powerpc (bfd_vma memaddr, 571 struct disassemble_info *info, 572 int bigendian, 573 ppc_cpu_t dialect) 574 { 575 bfd_byte buffer[4]; 576 int status; 577 unsigned long insn; 578 const struct powerpc_opcode *opcode; 579 bfd_boolean insn_is_short; 580 581 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 582 if (status != 0) 583 { 584 /* The final instruction may be a 2-byte VLE insn. */ 585 if ((dialect & PPC_OPCODE_VLE) != 0) 586 { 587 /* Clear buffer so unused bytes will not have garbage in them. */ 588 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0; 589 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 590 if (status != 0) 591 { 592 (*info->memory_error_func) (status, memaddr, info); 593 return -1; 594 } 595 } 596 else 597 { 598 (*info->memory_error_func) (status, memaddr, info); 599 return -1; 600 } 601 } 602 603 if (bigendian) 604 insn = bfd_getb32 (buffer); 605 else 606 insn = bfd_getl32 (buffer); 607 608 /* Get the major opcode of the insn. */ 609 opcode = NULL; 610 insn_is_short = FALSE; 611 if ((dialect & PPC_OPCODE_VLE) != 0) 612 { 613 opcode = lookup_vle (insn); 614 if (opcode != NULL) 615 insn_is_short = PPC_OP_SE_VLE(opcode->mask); 616 } 617 if (opcode == NULL) 618 opcode = lookup_powerpc (insn, dialect); 619 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) 620 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1); 621 622 if (opcode != NULL) 623 { 624 const unsigned char *opindex; 625 const struct powerpc_operand *operand; 626 int need_comma; 627 int need_paren; 628 int skip_optional; 629 630 if (opcode->operands[0] != 0) 631 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); 632 else 633 (*info->fprintf_func) (info->stream, "%s", opcode->name); 634 635 if (insn_is_short) 636 /* The operands will be fetched out of the 16-bit instruction. */ 637 insn >>= 16; 638 639 /* Now extract and print the operands. */ 640 need_comma = 0; 641 need_paren = 0; 642 skip_optional = -1; 643 for (opindex = opcode->operands; *opindex != 0; opindex++) 644 { 645 long value; 646 647 operand = powerpc_operands + *opindex; 648 649 /* Operands that are marked FAKE are simply ignored. We 650 already made sure that the extract function considered 651 the instruction to be valid. */ 652 if ((operand->flags & PPC_OPERAND_FAKE) != 0) 653 continue; 654 655 /* If all of the optional operands have the value zero, 656 then don't print any of them. */ 657 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) 658 { 659 if (skip_optional < 0) 660 skip_optional = skip_optional_operands (opindex, insn, 661 dialect); 662 if (skip_optional) 663 continue; 664 } 665 666 value = operand_value_powerpc (operand, insn, dialect); 667 668 if (need_comma) 669 { 670 (*info->fprintf_func) (info->stream, ","); 671 need_comma = 0; 672 } 673 674 /* Print the operand as directed by the flags. */ 675 if ((operand->flags & PPC_OPERAND_GPR) != 0 676 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) 677 (*info->fprintf_func) (info->stream, "r%ld", value); 678 else if ((operand->flags & PPC_OPERAND_FPR) != 0) 679 (*info->fprintf_func) (info->stream, "f%ld", value); 680 else if ((operand->flags & PPC_OPERAND_VR) != 0) 681 (*info->fprintf_func) (info->stream, "v%ld", value); 682 else if ((operand->flags & PPC_OPERAND_VSR) != 0) 683 (*info->fprintf_func) (info->stream, "vs%ld", value); 684 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) 685 (*info->print_address_func) (memaddr + value, info); 686 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) 687 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); 688 else if ((operand->flags & PPC_OPERAND_FSL) != 0) 689 (*info->fprintf_func) (info->stream, "fsl%ld", value); 690 else if ((operand->flags & PPC_OPERAND_FCR) != 0) 691 (*info->fprintf_func) (info->stream, "fcr%ld", value); 692 else if ((operand->flags & PPC_OPERAND_UDI) != 0) 693 (*info->fprintf_func) (info->stream, "%ld", value); 694 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 695 && (((dialect & PPC_OPCODE_PPC) != 0) 696 || ((dialect & PPC_OPCODE_VLE) != 0))) 697 (*info->fprintf_func) (info->stream, "cr%ld", value); 698 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) 699 && (((dialect & PPC_OPCODE_PPC) != 0) 700 || ((dialect & PPC_OPCODE_VLE) != 0))) 701 { 702 static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; 703 int cr; 704 int cc; 705 706 cr = value >> 2; 707 if (cr != 0) 708 (*info->fprintf_func) (info->stream, "4*cr%d+", cr); 709 cc = value & 3; 710 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); 711 } 712 else 713 (*info->fprintf_func) (info->stream, "%d", (int) value); 714 715 if (need_paren) 716 { 717 (*info->fprintf_func) (info->stream, ")"); 718 need_paren = 0; 719 } 720 721 if ((operand->flags & PPC_OPERAND_PARENS) == 0) 722 need_comma = 1; 723 else 724 { 725 (*info->fprintf_func) (info->stream, "("); 726 need_paren = 1; 727 } 728 } 729 730 /* We have found and printed an instruction. 731 If it was a short VLE instruction we have more to do. */ 732 if (insn_is_short) 733 { 734 memaddr += 2; 735 return 2; 736 } 737 else 738 /* Otherwise, return. */ 739 return 4; 740 } 741 742 /* We could not find a match. */ 743 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); 744 745 return 4; 746 } 747 748 void 749 print_ppc_disassembler_options (FILE *stream) 750 { 751 unsigned int i, col; 752 753 fprintf (stream, _("\n\ 754 The following PPC specific disassembler options are supported for use with\n\ 755 the -M switch:\n")); 756 757 for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) 758 { 759 col += fprintf (stream, " %s,", ppc_opts[i].opt); 760 if (col > 66) 761 { 762 fprintf (stream, "\n"); 763 col = 0; 764 } 765 } 766 fprintf (stream, " 32, 64\n"); 767 } 768