1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2 /* Instruction building/extraction support for or1k. -*- C -*- 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 5 - the resultant file is machine generated, cgen-ibld.in isn't 6 7 Copyright (C) 1996-2020 Free Software Foundation, Inc. 8 9 This file is part of libopcodes. 10 11 This library is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 It is distributed in the hope that it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 24 25 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 26 Keep that in mind. */ 27 28 #include "sysdep.h" 29 #include <stdio.h> 30 #include "ansidecl.h" 31 #include "dis-asm.h" 32 #include "bfd.h" 33 #include "symcat.h" 34 #include "or1k-desc.h" 35 #include "or1k-opc.h" 36 #include "cgen/basic-modes.h" 37 #include "opintl.h" 38 #include "safe-ctype.h" 39 40 #undef min 41 #define min(a,b) ((a) < (b) ? (a) : (b)) 42 #undef max 43 #define max(a,b) ((a) > (b) ? (a) : (b)) 44 45 /* Used by the ifield rtx function. */ 46 #define FLD(f) (fields->f) 47 48 static const char * insert_normal 49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 51 static const char * insert_insn_normal 52 (CGEN_CPU_DESC, const CGEN_INSN *, 53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 54 static int extract_normal 55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 56 unsigned int, unsigned int, unsigned int, unsigned int, 57 unsigned int, unsigned int, bfd_vma, long *); 58 static int extract_insn_normal 59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 61 #if CGEN_INT_INSN_P 62 static void put_insn_int_value 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 64 #endif 65 #if ! CGEN_INT_INSN_P 66 static CGEN_INLINE void insert_1 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 68 static CGEN_INLINE int fill_cache 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 70 static CGEN_INLINE long extract_1 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 72 #endif 73 74 /* Operand insertion. */ 75 76 #if ! CGEN_INT_INSN_P 77 78 /* Subroutine of insert_normal. */ 79 80 static CGEN_INLINE void 81 insert_1 (CGEN_CPU_DESC cd, 82 unsigned long value, 83 int start, 84 int length, 85 int word_length, 86 unsigned char *bufp) 87 { 88 unsigned long x,mask; 89 int shift; 90 91 x = cgen_get_insn_value (cd, bufp, word_length); 92 93 /* Written this way to avoid undefined behaviour. */ 94 mask = (((1L << (length - 1)) - 1) << 1) | 1; 95 if (CGEN_INSN_LSB0_P) 96 shift = (start + 1) - length; 97 else 98 shift = (word_length - (start + length)); 99 x = (x & ~(mask << shift)) | ((value & mask) << shift); 100 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); 102 } 103 104 #endif /* ! CGEN_INT_INSN_P */ 105 106 /* Default insertion routine. 107 108 ATTRS is a mask of the boolean attributes. 109 WORD_OFFSET is the offset in bits from the start of the insn of the value. 110 WORD_LENGTH is the length of the word in bits in which the value resides. 111 START is the starting bit number in the word, architecture origin. 112 LENGTH is the length of VALUE in bits. 113 TOTAL_LENGTH is the total length of the insn in bits. 114 115 The result is an error message or NULL if success. */ 116 117 /* ??? This duplicates functionality with bfd's howto table and 118 bfd_install_relocation. */ 119 /* ??? This doesn't handle bfd_vma's. Create another function when 120 necessary. */ 121 122 static const char * 123 insert_normal (CGEN_CPU_DESC cd, 124 long value, 125 unsigned int attrs, 126 unsigned int word_offset, 127 unsigned int start, 128 unsigned int length, 129 unsigned int word_length, 130 unsigned int total_length, 131 CGEN_INSN_BYTES_PTR buffer) 132 { 133 static char errbuf[100]; 134 /* Written this way to avoid undefined behaviour. */ 135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; 136 137 /* If LENGTH is zero, this operand doesn't contribute to the value. */ 138 if (length == 0) 139 return NULL; 140 141 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 142 abort (); 143 144 /* For architectures with insns smaller than the base-insn-bitsize, 145 word_length may be too big. */ 146 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 147 { 148 if (word_offset == 0 149 && word_length > total_length) 150 word_length = total_length; 151 } 152 153 /* Ensure VALUE will fit. */ 154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 155 { 156 long minval = - (1L << (length - 1)); 157 unsigned long maxval = mask; 158 159 if ((value > 0 && (unsigned long) value > maxval) 160 || value < minval) 161 { 162 /* xgettext:c-format */ 163 sprintf (errbuf, 164 _("operand out of range (%ld not between %ld and %lu)"), 165 value, minval, maxval); 166 return errbuf; 167 } 168 } 169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 170 { 171 unsigned long maxval = mask; 172 unsigned long val = (unsigned long) value; 173 174 /* For hosts with a word size > 32 check to see if value has been sign 175 extended beyond 32 bits. If so then ignore these higher sign bits 176 as the user is attempting to store a 32-bit signed value into an 177 unsigned 32-bit field which is allowed. */ 178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 179 val &= 0xFFFFFFFF; 180 181 if (val > maxval) 182 { 183 /* xgettext:c-format */ 184 sprintf (errbuf, 185 _("operand out of range (0x%lx not between 0 and 0x%lx)"), 186 val, maxval); 187 return errbuf; 188 } 189 } 190 else 191 { 192 if (! cgen_signed_overflow_ok_p (cd)) 193 { 194 long minval = - (1L << (length - 1)); 195 long maxval = (1L << (length - 1)) - 1; 196 197 if (value < minval || value > maxval) 198 { 199 sprintf 200 /* xgettext:c-format */ 201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 202 value, minval, maxval); 203 return errbuf; 204 } 205 } 206 } 207 208 #if CGEN_INT_INSN_P 209 210 { 211 int shift_within_word, shift_to_word, shift; 212 213 /* How to shift the value to BIT0 of the word. */ 214 shift_to_word = total_length - (word_offset + word_length); 215 216 /* How to shift the value to the field within the word. */ 217 if (CGEN_INSN_LSB0_P) 218 shift_within_word = start + 1 - length; 219 else 220 shift_within_word = word_length - start - length; 221 222 /* The total SHIFT, then mask in the value. */ 223 shift = shift_to_word + shift_within_word; 224 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 225 } 226 227 #else /* ! CGEN_INT_INSN_P */ 228 229 { 230 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 231 232 insert_1 (cd, value, start, length, word_length, bufp); 233 } 234 235 #endif /* ! CGEN_INT_INSN_P */ 236 237 return NULL; 238 } 239 240 /* Default insn builder (insert handler). 241 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 242 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 243 recorded in host byte order, otherwise BUFFER is an array of bytes 244 and the value is recorded in target byte order). 245 The result is an error message or NULL if success. */ 246 247 static const char * 248 insert_insn_normal (CGEN_CPU_DESC cd, 249 const CGEN_INSN * insn, 250 CGEN_FIELDS * fields, 251 CGEN_INSN_BYTES_PTR buffer, 252 bfd_vma pc) 253 { 254 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 255 unsigned long value; 256 const CGEN_SYNTAX_CHAR_TYPE * syn; 257 258 CGEN_INIT_INSERT (cd); 259 value = CGEN_INSN_BASE_VALUE (insn); 260 261 /* If we're recording insns as numbers (rather than a string of bytes), 262 target byte order handling is deferred until later. */ 263 264 #if CGEN_INT_INSN_P 265 266 put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 267 CGEN_FIELDS_BITSIZE (fields), value); 268 269 #else 270 271 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 272 (unsigned) CGEN_FIELDS_BITSIZE (fields)), 273 value); 274 275 #endif /* ! CGEN_INT_INSN_P */ 276 277 /* ??? It would be better to scan the format's fields. 278 Still need to be able to insert a value based on the operand though; 279 e.g. storing a branch displacement that got resolved later. 280 Needs more thought first. */ 281 282 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 283 { 284 const char *errmsg; 285 286 if (CGEN_SYNTAX_CHAR_P (* syn)) 287 continue; 288 289 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 290 fields, buffer, pc); 291 if (errmsg) 292 return errmsg; 293 } 294 295 return NULL; 296 } 297 298 #if CGEN_INT_INSN_P 299 /* Cover function to store an insn value into an integral insn. Must go here 300 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 301 302 static void 303 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 304 CGEN_INSN_BYTES_PTR buf, 305 int length, 306 int insn_length, 307 CGEN_INSN_INT value) 308 { 309 /* For architectures with insns smaller than the base-insn-bitsize, 310 length may be too big. */ 311 if (length > insn_length) 312 *buf = value; 313 else 314 { 315 int shift = insn_length - length; 316 /* Written this way to avoid undefined behaviour. */ 317 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; 318 319 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 320 } 321 } 322 #endif 323 324 /* Operand extraction. */ 325 326 #if ! CGEN_INT_INSN_P 327 328 /* Subroutine of extract_normal. 329 Ensure sufficient bytes are cached in EX_INFO. 330 OFFSET is the offset in bytes from the start of the insn of the value. 331 BYTES is the length of the needed value. 332 Returns 1 for success, 0 for failure. */ 333 334 static CGEN_INLINE int 335 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 336 CGEN_EXTRACT_INFO *ex_info, 337 int offset, 338 int bytes, 339 bfd_vma pc) 340 { 341 /* It's doubtful that the middle part has already been fetched so 342 we don't optimize that case. kiss. */ 343 unsigned int mask; 344 disassemble_info *info = (disassemble_info *) ex_info->dis_info; 345 346 /* First do a quick check. */ 347 mask = (1 << bytes) - 1; 348 if (((ex_info->valid >> offset) & mask) == mask) 349 return 1; 350 351 /* Search for the first byte we need to read. */ 352 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 353 if (! (mask & ex_info->valid)) 354 break; 355 356 if (bytes) 357 { 358 int status; 359 360 pc += offset; 361 status = (*info->read_memory_func) 362 (pc, ex_info->insn_bytes + offset, bytes, info); 363 364 if (status != 0) 365 { 366 (*info->memory_error_func) (status, pc, info); 367 return 0; 368 } 369 370 ex_info->valid |= ((1 << bytes) - 1) << offset; 371 } 372 373 return 1; 374 } 375 376 /* Subroutine of extract_normal. */ 377 378 static CGEN_INLINE long 379 extract_1 (CGEN_CPU_DESC cd, 380 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 381 int start, 382 int length, 383 int word_length, 384 unsigned char *bufp, 385 bfd_vma pc ATTRIBUTE_UNUSED) 386 { 387 unsigned long x; 388 int shift; 389 390 x = cgen_get_insn_value (cd, bufp, word_length); 391 392 if (CGEN_INSN_LSB0_P) 393 shift = (start + 1) - length; 394 else 395 shift = (word_length - (start + length)); 396 return x >> shift; 397 } 398 399 #endif /* ! CGEN_INT_INSN_P */ 400 401 /* Default extraction routine. 402 403 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 404 or sometimes less for cases like the m32r where the base insn size is 32 405 but some insns are 16 bits. 406 ATTRS is a mask of the boolean attributes. We only need `SIGNED', 407 but for generality we take a bitmask of all of them. 408 WORD_OFFSET is the offset in bits from the start of the insn of the value. 409 WORD_LENGTH is the length of the word in bits in which the value resides. 410 START is the starting bit number in the word, architecture origin. 411 LENGTH is the length of VALUE in bits. 412 TOTAL_LENGTH is the total length of the insn in bits. 413 414 Returns 1 for success, 0 for failure. */ 415 416 /* ??? The return code isn't properly used. wip. */ 417 418 /* ??? This doesn't handle bfd_vma's. Create another function when 419 necessary. */ 420 421 static int 422 extract_normal (CGEN_CPU_DESC cd, 423 #if ! CGEN_INT_INSN_P 424 CGEN_EXTRACT_INFO *ex_info, 425 #else 426 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 427 #endif 428 CGEN_INSN_INT insn_value, 429 unsigned int attrs, 430 unsigned int word_offset, 431 unsigned int start, 432 unsigned int length, 433 unsigned int word_length, 434 unsigned int total_length, 435 #if ! CGEN_INT_INSN_P 436 bfd_vma pc, 437 #else 438 bfd_vma pc ATTRIBUTE_UNUSED, 439 #endif 440 long *valuep) 441 { 442 long value, mask; 443 444 /* If LENGTH is zero, this operand doesn't contribute to the value 445 so give it a standard value of zero. */ 446 if (length == 0) 447 { 448 *valuep = 0; 449 return 1; 450 } 451 452 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 453 abort (); 454 455 /* For architectures with insns smaller than the insn-base-bitsize, 456 word_length may be too big. */ 457 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 458 { 459 if (word_offset + word_length > total_length) 460 word_length = total_length - word_offset; 461 } 462 463 /* Does the value reside in INSN_VALUE, and at the right alignment? */ 464 465 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 466 { 467 if (CGEN_INSN_LSB0_P) 468 value = insn_value >> ((word_offset + start + 1) - length); 469 else 470 value = insn_value >> (total_length - ( word_offset + start + length)); 471 } 472 473 #if ! CGEN_INT_INSN_P 474 475 else 476 { 477 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 478 479 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 480 abort (); 481 482 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 483 return 0; 484 485 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 486 } 487 488 #endif /* ! CGEN_INT_INSN_P */ 489 490 /* Written this way to avoid undefined behaviour. */ 491 mask = (((1L << (length - 1)) - 1) << 1) | 1; 492 493 value &= mask; 494 /* sign extend? */ 495 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 496 && (value & (1L << (length - 1)))) 497 value |= ~mask; 498 499 *valuep = value; 500 501 return 1; 502 } 503 504 /* Default insn extractor. 505 506 INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 507 The extracted fields are stored in FIELDS. 508 EX_INFO is used to handle reading variable length insns. 509 Return the length of the insn in bits, or 0 if no match, 510 or -1 if an error occurs fetching data (memory_error_func will have 511 been called). */ 512 513 static int 514 extract_insn_normal (CGEN_CPU_DESC cd, 515 const CGEN_INSN *insn, 516 CGEN_EXTRACT_INFO *ex_info, 517 CGEN_INSN_INT insn_value, 518 CGEN_FIELDS *fields, 519 bfd_vma pc) 520 { 521 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 522 const CGEN_SYNTAX_CHAR_TYPE *syn; 523 524 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 525 526 CGEN_INIT_EXTRACT (cd); 527 528 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 529 { 530 int length; 531 532 if (CGEN_SYNTAX_CHAR_P (*syn)) 533 continue; 534 535 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 536 ex_info, insn_value, fields, pc); 537 if (length <= 0) 538 return length; 539 } 540 541 /* We recognized and successfully extracted this insn. */ 542 return CGEN_INSN_BITSIZE (insn); 543 } 544 545 /* Machine generated code added here. */ 546 547 const char * or1k_cgen_insert_operand 548 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 549 550 /* Main entry point for operand insertion. 551 552 This function is basically just a big switch statement. Earlier versions 553 used tables to look up the function to use, but 554 - if the table contains both assembler and disassembler functions then 555 the disassembler contains much of the assembler and vice-versa, 556 - there's a lot of inlining possibilities as things grow, 557 - using a switch statement avoids the function call overhead. 558 559 This function could be moved into `parse_insn_normal', but keeping it 560 separate makes clear the interface between `parse_insn_normal' and each of 561 the handlers. It's also needed by GAS to insert operands that couldn't be 562 resolved during parsing. */ 563 564 const char * 565 or1k_cgen_insert_operand (CGEN_CPU_DESC cd, 566 int opindex, 567 CGEN_FIELDS * fields, 568 CGEN_INSN_BYTES_PTR buffer, 569 bfd_vma pc ATTRIBUTE_UNUSED) 570 { 571 const char * errmsg = NULL; 572 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 573 574 switch (opindex) 575 { 576 case OR1K_OPERAND_DISP21 : 577 { 578 long value = fields->f_disp21; 579 value = ((((DI) (value) >> (13))) - (((DI) (pc) >> (13)))); 580 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, buffer); 581 } 582 break; 583 case OR1K_OPERAND_DISP26 : 584 { 585 long value = fields->f_disp26; 586 value = ((DI) (((value) - (pc))) >> (2)); 587 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer); 588 } 589 break; 590 case OR1K_OPERAND_RA : 591 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 592 break; 593 case OR1K_OPERAND_RAD32F : 594 { 595 { 596 FLD (f_r2) = ((FLD (f_rad32)) & (31)); 597 FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1)); 598 } 599 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 600 if (errmsg) 601 break; 602 errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer); 603 if (errmsg) 604 break; 605 } 606 break; 607 case OR1K_OPERAND_RADF : 608 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 609 break; 610 case OR1K_OPERAND_RADI : 611 { 612 { 613 FLD (f_r2) = ((FLD (f_rad32)) & (31)); 614 FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1)); 615 } 616 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 617 if (errmsg) 618 break; 619 errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer); 620 if (errmsg) 621 break; 622 } 623 break; 624 case OR1K_OPERAND_RASF : 625 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 626 break; 627 case OR1K_OPERAND_RB : 628 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 629 break; 630 case OR1K_OPERAND_RBD32F : 631 { 632 { 633 FLD (f_r3) = ((FLD (f_rbd32)) & (31)); 634 FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1)); 635 } 636 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 637 if (errmsg) 638 break; 639 errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer); 640 if (errmsg) 641 break; 642 } 643 break; 644 case OR1K_OPERAND_RBDF : 645 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 646 break; 647 case OR1K_OPERAND_RBDI : 648 { 649 { 650 FLD (f_r3) = ((FLD (f_rbd32)) & (31)); 651 FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1)); 652 } 653 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 654 if (errmsg) 655 break; 656 errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer); 657 if (errmsg) 658 break; 659 } 660 break; 661 case OR1K_OPERAND_RBSF : 662 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 663 break; 664 case OR1K_OPERAND_RD : 665 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 666 break; 667 case OR1K_OPERAND_RDD32F : 668 { 669 { 670 FLD (f_r1) = ((FLD (f_rdd32)) & (31)); 671 FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1)); 672 } 673 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 674 if (errmsg) 675 break; 676 errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer); 677 if (errmsg) 678 break; 679 } 680 break; 681 case OR1K_OPERAND_RDDF : 682 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 683 break; 684 case OR1K_OPERAND_RDDI : 685 { 686 { 687 FLD (f_r1) = ((FLD (f_rdd32)) & (31)); 688 FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1)); 689 } 690 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 691 if (errmsg) 692 break; 693 errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer); 694 if (errmsg) 695 break; 696 } 697 break; 698 case OR1K_OPERAND_RDSF : 699 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 700 break; 701 case OR1K_OPERAND_SIMM16 : 702 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, buffer); 703 break; 704 case OR1K_OPERAND_SIMM16_SPLIT : 705 { 706 { 707 FLD (f_imm16_25_5) = ((((INT) (FLD (f_simm16_split)) >> (11))) & (31)); 708 FLD (f_imm16_10_11) = ((FLD (f_simm16_split)) & (2047)); 709 } 710 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer); 711 if (errmsg) 712 break; 713 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer); 714 if (errmsg) 715 break; 716 } 717 break; 718 case OR1K_OPERAND_UIMM16 : 719 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer); 720 break; 721 case OR1K_OPERAND_UIMM16_SPLIT : 722 { 723 { 724 FLD (f_imm16_25_5) = ((((UINT) (FLD (f_uimm16_split)) >> (11))) & (31)); 725 FLD (f_imm16_10_11) = ((FLD (f_uimm16_split)) & (2047)); 726 } 727 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer); 728 if (errmsg) 729 break; 730 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer); 731 if (errmsg) 732 break; 733 } 734 break; 735 case OR1K_OPERAND_UIMM6 : 736 errmsg = insert_normal (cd, fields->f_uimm6, 0, 0, 5, 6, 32, total_length, buffer); 737 break; 738 739 default : 740 /* xgettext:c-format */ 741 opcodes_error_handler 742 (_("internal error: unrecognized field %d while building insn"), 743 opindex); 744 abort (); 745 } 746 747 return errmsg; 748 } 749 750 int or1k_cgen_extract_operand 751 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 752 753 /* Main entry point for operand extraction. 754 The result is <= 0 for error, >0 for success. 755 ??? Actual values aren't well defined right now. 756 757 This function is basically just a big switch statement. Earlier versions 758 used tables to look up the function to use, but 759 - if the table contains both assembler and disassembler functions then 760 the disassembler contains much of the assembler and vice-versa, 761 - there's a lot of inlining possibilities as things grow, 762 - using a switch statement avoids the function call overhead. 763 764 This function could be moved into `print_insn_normal', but keeping it 765 separate makes clear the interface between `print_insn_normal' and each of 766 the handlers. */ 767 768 int 769 or1k_cgen_extract_operand (CGEN_CPU_DESC cd, 770 int opindex, 771 CGEN_EXTRACT_INFO *ex_info, 772 CGEN_INSN_INT insn_value, 773 CGEN_FIELDS * fields, 774 bfd_vma pc) 775 { 776 /* Assume success (for those operands that are nops). */ 777 int length = 1; 778 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 779 780 switch (opindex) 781 { 782 case OR1K_OPERAND_DISP21 : 783 { 784 long value; 785 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, pc, & value); 786 value = ((((value) + (((DI) (pc) >> (13))))) * (MAKEDI (0, 8192))); 787 fields->f_disp21 = value; 788 } 789 break; 790 case OR1K_OPERAND_DISP26 : 791 { 792 long value; 793 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value); 794 value = ((((value) * (MAKEDI (0, 4)))) + (pc)); 795 fields->f_disp26 = value; 796 } 797 break; 798 case OR1K_OPERAND_RA : 799 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 800 break; 801 case OR1K_OPERAND_RAD32F : 802 { 803 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 804 if (length <= 0) break; 805 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1); 806 if (length <= 0) break; 807 FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5)))); 808 } 809 break; 810 case OR1K_OPERAND_RADF : 811 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 812 break; 813 case OR1K_OPERAND_RADI : 814 { 815 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 816 if (length <= 0) break; 817 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1); 818 if (length <= 0) break; 819 FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5)))); 820 } 821 break; 822 case OR1K_OPERAND_RASF : 823 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 824 break; 825 case OR1K_OPERAND_RB : 826 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 827 break; 828 case OR1K_OPERAND_RBD32F : 829 { 830 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 831 if (length <= 0) break; 832 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1); 833 if (length <= 0) break; 834 FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5)))); 835 } 836 break; 837 case OR1K_OPERAND_RBDF : 838 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 839 break; 840 case OR1K_OPERAND_RBDI : 841 { 842 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 843 if (length <= 0) break; 844 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1); 845 if (length <= 0) break; 846 FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5)))); 847 } 848 break; 849 case OR1K_OPERAND_RBSF : 850 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 851 break; 852 case OR1K_OPERAND_RD : 853 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 854 break; 855 case OR1K_OPERAND_RDD32F : 856 { 857 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 858 if (length <= 0) break; 859 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1); 860 if (length <= 0) break; 861 FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5)))); 862 } 863 break; 864 case OR1K_OPERAND_RDDF : 865 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 866 break; 867 case OR1K_OPERAND_RDDI : 868 { 869 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 870 if (length <= 0) break; 871 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1); 872 if (length <= 0) break; 873 FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5)))); 874 } 875 break; 876 case OR1K_OPERAND_RDSF : 877 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 878 break; 879 case OR1K_OPERAND_SIMM16 : 880 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); 881 break; 882 case OR1K_OPERAND_SIMM16_SPLIT : 883 { 884 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5); 885 if (length <= 0) break; 886 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11); 887 if (length <= 0) break; 888 FLD (f_simm16_split) = ((HI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11))))); 889 } 890 break; 891 case OR1K_OPERAND_UIMM16 : 892 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16); 893 break; 894 case OR1K_OPERAND_UIMM16_SPLIT : 895 { 896 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5); 897 if (length <= 0) break; 898 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11); 899 if (length <= 0) break; 900 FLD (f_uimm16_split) = ((UHI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11))))); 901 } 902 break; 903 case OR1K_OPERAND_UIMM6 : 904 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_uimm6); 905 break; 906 907 default : 908 /* xgettext:c-format */ 909 opcodes_error_handler 910 (_("internal error: unrecognized field %d while decoding insn"), 911 opindex); 912 abort (); 913 } 914 915 return length; 916 } 917 918 cgen_insert_fn * const or1k_cgen_insert_handlers[] = 919 { 920 insert_insn_normal, 921 }; 922 923 cgen_extract_fn * const or1k_cgen_extract_handlers[] = 924 { 925 extract_insn_normal, 926 }; 927 928 int or1k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 929 bfd_vma or1k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 930 931 /* Getting values from cgen_fields is handled by a collection of functions. 932 They are distinguished by the type of the VALUE argument they return. 933 TODO: floating point, inlining support, remove cases where result type 934 not appropriate. */ 935 936 int 937 or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 938 int opindex, 939 const CGEN_FIELDS * fields) 940 { 941 int value; 942 943 switch (opindex) 944 { 945 case OR1K_OPERAND_DISP21 : 946 value = fields->f_disp21; 947 break; 948 case OR1K_OPERAND_DISP26 : 949 value = fields->f_disp26; 950 break; 951 case OR1K_OPERAND_RA : 952 value = fields->f_r2; 953 break; 954 case OR1K_OPERAND_RAD32F : 955 value = fields->f_rad32; 956 break; 957 case OR1K_OPERAND_RADF : 958 value = fields->f_r2; 959 break; 960 case OR1K_OPERAND_RADI : 961 value = fields->f_rad32; 962 break; 963 case OR1K_OPERAND_RASF : 964 value = fields->f_r2; 965 break; 966 case OR1K_OPERAND_RB : 967 value = fields->f_r3; 968 break; 969 case OR1K_OPERAND_RBD32F : 970 value = fields->f_rbd32; 971 break; 972 case OR1K_OPERAND_RBDF : 973 value = fields->f_r3; 974 break; 975 case OR1K_OPERAND_RBDI : 976 value = fields->f_rbd32; 977 break; 978 case OR1K_OPERAND_RBSF : 979 value = fields->f_r3; 980 break; 981 case OR1K_OPERAND_RD : 982 value = fields->f_r1; 983 break; 984 case OR1K_OPERAND_RDD32F : 985 value = fields->f_rdd32; 986 break; 987 case OR1K_OPERAND_RDDF : 988 value = fields->f_r1; 989 break; 990 case OR1K_OPERAND_RDDI : 991 value = fields->f_rdd32; 992 break; 993 case OR1K_OPERAND_RDSF : 994 value = fields->f_r1; 995 break; 996 case OR1K_OPERAND_SIMM16 : 997 value = fields->f_simm16; 998 break; 999 case OR1K_OPERAND_SIMM16_SPLIT : 1000 value = fields->f_simm16_split; 1001 break; 1002 case OR1K_OPERAND_UIMM16 : 1003 value = fields->f_uimm16; 1004 break; 1005 case OR1K_OPERAND_UIMM16_SPLIT : 1006 value = fields->f_uimm16_split; 1007 break; 1008 case OR1K_OPERAND_UIMM6 : 1009 value = fields->f_uimm6; 1010 break; 1011 1012 default : 1013 /* xgettext:c-format */ 1014 opcodes_error_handler 1015 (_("internal error: unrecognized field %d while getting int operand"), 1016 opindex); 1017 abort (); 1018 } 1019 1020 return value; 1021 } 1022 1023 bfd_vma 1024 or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1025 int opindex, 1026 const CGEN_FIELDS * fields) 1027 { 1028 bfd_vma value; 1029 1030 switch (opindex) 1031 { 1032 case OR1K_OPERAND_DISP21 : 1033 value = fields->f_disp21; 1034 break; 1035 case OR1K_OPERAND_DISP26 : 1036 value = fields->f_disp26; 1037 break; 1038 case OR1K_OPERAND_RA : 1039 value = fields->f_r2; 1040 break; 1041 case OR1K_OPERAND_RAD32F : 1042 value = fields->f_rad32; 1043 break; 1044 case OR1K_OPERAND_RADF : 1045 value = fields->f_r2; 1046 break; 1047 case OR1K_OPERAND_RADI : 1048 value = fields->f_rad32; 1049 break; 1050 case OR1K_OPERAND_RASF : 1051 value = fields->f_r2; 1052 break; 1053 case OR1K_OPERAND_RB : 1054 value = fields->f_r3; 1055 break; 1056 case OR1K_OPERAND_RBD32F : 1057 value = fields->f_rbd32; 1058 break; 1059 case OR1K_OPERAND_RBDF : 1060 value = fields->f_r3; 1061 break; 1062 case OR1K_OPERAND_RBDI : 1063 value = fields->f_rbd32; 1064 break; 1065 case OR1K_OPERAND_RBSF : 1066 value = fields->f_r3; 1067 break; 1068 case OR1K_OPERAND_RD : 1069 value = fields->f_r1; 1070 break; 1071 case OR1K_OPERAND_RDD32F : 1072 value = fields->f_rdd32; 1073 break; 1074 case OR1K_OPERAND_RDDF : 1075 value = fields->f_r1; 1076 break; 1077 case OR1K_OPERAND_RDDI : 1078 value = fields->f_rdd32; 1079 break; 1080 case OR1K_OPERAND_RDSF : 1081 value = fields->f_r1; 1082 break; 1083 case OR1K_OPERAND_SIMM16 : 1084 value = fields->f_simm16; 1085 break; 1086 case OR1K_OPERAND_SIMM16_SPLIT : 1087 value = fields->f_simm16_split; 1088 break; 1089 case OR1K_OPERAND_UIMM16 : 1090 value = fields->f_uimm16; 1091 break; 1092 case OR1K_OPERAND_UIMM16_SPLIT : 1093 value = fields->f_uimm16_split; 1094 break; 1095 case OR1K_OPERAND_UIMM6 : 1096 value = fields->f_uimm6; 1097 break; 1098 1099 default : 1100 /* xgettext:c-format */ 1101 opcodes_error_handler 1102 (_("internal error: unrecognized field %d while getting vma operand"), 1103 opindex); 1104 abort (); 1105 } 1106 1107 return value; 1108 } 1109 1110 void or1k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 1111 void or1k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 1112 1113 /* Stuffing values in cgen_fields is handled by a collection of functions. 1114 They are distinguished by the type of the VALUE argument they accept. 1115 TODO: floating point, inlining support, remove cases where argument type 1116 not appropriate. */ 1117 1118 void 1119 or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1120 int opindex, 1121 CGEN_FIELDS * fields, 1122 int value) 1123 { 1124 switch (opindex) 1125 { 1126 case OR1K_OPERAND_DISP21 : 1127 fields->f_disp21 = value; 1128 break; 1129 case OR1K_OPERAND_DISP26 : 1130 fields->f_disp26 = value; 1131 break; 1132 case OR1K_OPERAND_RA : 1133 fields->f_r2 = value; 1134 break; 1135 case OR1K_OPERAND_RAD32F : 1136 fields->f_rad32 = value; 1137 break; 1138 case OR1K_OPERAND_RADF : 1139 fields->f_r2 = value; 1140 break; 1141 case OR1K_OPERAND_RADI : 1142 fields->f_rad32 = value; 1143 break; 1144 case OR1K_OPERAND_RASF : 1145 fields->f_r2 = value; 1146 break; 1147 case OR1K_OPERAND_RB : 1148 fields->f_r3 = value; 1149 break; 1150 case OR1K_OPERAND_RBD32F : 1151 fields->f_rbd32 = value; 1152 break; 1153 case OR1K_OPERAND_RBDF : 1154 fields->f_r3 = value; 1155 break; 1156 case OR1K_OPERAND_RBDI : 1157 fields->f_rbd32 = value; 1158 break; 1159 case OR1K_OPERAND_RBSF : 1160 fields->f_r3 = value; 1161 break; 1162 case OR1K_OPERAND_RD : 1163 fields->f_r1 = value; 1164 break; 1165 case OR1K_OPERAND_RDD32F : 1166 fields->f_rdd32 = value; 1167 break; 1168 case OR1K_OPERAND_RDDF : 1169 fields->f_r1 = value; 1170 break; 1171 case OR1K_OPERAND_RDDI : 1172 fields->f_rdd32 = value; 1173 break; 1174 case OR1K_OPERAND_RDSF : 1175 fields->f_r1 = value; 1176 break; 1177 case OR1K_OPERAND_SIMM16 : 1178 fields->f_simm16 = value; 1179 break; 1180 case OR1K_OPERAND_SIMM16_SPLIT : 1181 fields->f_simm16_split = value; 1182 break; 1183 case OR1K_OPERAND_UIMM16 : 1184 fields->f_uimm16 = value; 1185 break; 1186 case OR1K_OPERAND_UIMM16_SPLIT : 1187 fields->f_uimm16_split = value; 1188 break; 1189 case OR1K_OPERAND_UIMM6 : 1190 fields->f_uimm6 = value; 1191 break; 1192 1193 default : 1194 /* xgettext:c-format */ 1195 opcodes_error_handler 1196 (_("internal error: unrecognized field %d while setting int operand"), 1197 opindex); 1198 abort (); 1199 } 1200 } 1201 1202 void 1203 or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1204 int opindex, 1205 CGEN_FIELDS * fields, 1206 bfd_vma value) 1207 { 1208 switch (opindex) 1209 { 1210 case OR1K_OPERAND_DISP21 : 1211 fields->f_disp21 = value; 1212 break; 1213 case OR1K_OPERAND_DISP26 : 1214 fields->f_disp26 = value; 1215 break; 1216 case OR1K_OPERAND_RA : 1217 fields->f_r2 = value; 1218 break; 1219 case OR1K_OPERAND_RAD32F : 1220 fields->f_rad32 = value; 1221 break; 1222 case OR1K_OPERAND_RADF : 1223 fields->f_r2 = value; 1224 break; 1225 case OR1K_OPERAND_RADI : 1226 fields->f_rad32 = value; 1227 break; 1228 case OR1K_OPERAND_RASF : 1229 fields->f_r2 = value; 1230 break; 1231 case OR1K_OPERAND_RB : 1232 fields->f_r3 = value; 1233 break; 1234 case OR1K_OPERAND_RBD32F : 1235 fields->f_rbd32 = value; 1236 break; 1237 case OR1K_OPERAND_RBDF : 1238 fields->f_r3 = value; 1239 break; 1240 case OR1K_OPERAND_RBDI : 1241 fields->f_rbd32 = value; 1242 break; 1243 case OR1K_OPERAND_RBSF : 1244 fields->f_r3 = value; 1245 break; 1246 case OR1K_OPERAND_RD : 1247 fields->f_r1 = value; 1248 break; 1249 case OR1K_OPERAND_RDD32F : 1250 fields->f_rdd32 = value; 1251 break; 1252 case OR1K_OPERAND_RDDF : 1253 fields->f_r1 = value; 1254 break; 1255 case OR1K_OPERAND_RDDI : 1256 fields->f_rdd32 = value; 1257 break; 1258 case OR1K_OPERAND_RDSF : 1259 fields->f_r1 = value; 1260 break; 1261 case OR1K_OPERAND_SIMM16 : 1262 fields->f_simm16 = value; 1263 break; 1264 case OR1K_OPERAND_SIMM16_SPLIT : 1265 fields->f_simm16_split = value; 1266 break; 1267 case OR1K_OPERAND_UIMM16 : 1268 fields->f_uimm16 = value; 1269 break; 1270 case OR1K_OPERAND_UIMM16_SPLIT : 1271 fields->f_uimm16_split = value; 1272 break; 1273 case OR1K_OPERAND_UIMM6 : 1274 fields->f_uimm6 = value; 1275 break; 1276 1277 default : 1278 /* xgettext:c-format */ 1279 opcodes_error_handler 1280 (_("internal error: unrecognized field %d while setting vma operand"), 1281 opindex); 1282 abort (); 1283 } 1284 } 1285 1286 /* Function to call before using the instruction builder tables. */ 1287 1288 void 1289 or1k_cgen_init_ibld_table (CGEN_CPU_DESC cd) 1290 { 1291 cd->insert_handlers = & or1k_cgen_insert_handlers[0]; 1292 cd->extract_handlers = & or1k_cgen_extract_handlers[0]; 1293 1294 cd->insert_operand = or1k_cgen_insert_operand; 1295 cd->extract_operand = or1k_cgen_extract_operand; 1296 1297 cd->get_int_operand = or1k_cgen_get_int_operand; 1298 cd->set_int_operand = or1k_cgen_set_int_operand; 1299 cd->get_vma_operand = or1k_cgen_get_vma_operand; 1300 cd->set_vma_operand = or1k_cgen_set_vma_operand; 1301 } 1302