12011-04-26 Anton Blanchard <anton@samba.org> 2 3 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7. 4 52011-02-01 Alan Modra <amodra@gmail.com> 6 7 Backport from mainline 8 2011-01-21 Dave Murphy <davem@devkitpro.org> 9 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS. 10 11 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> 12 * i386-gen.c (process_copyright): Update copyright to 2011. 13 142010-11-25 Alan Modra <amodra@gmail.com> 15 16 * po/es.po: Update. 17 * po/fr.po: Update. 18 * po/nl.po: Update. 19 * po/zh_CN.po: Update. 20 212010-11-10 Nick Clifton <nickc@redhat.com> 22 23 * po/fi.po: Updated Finnish translation. 24 252010-11-05 Tristan Gingold <gingold@adacore.com> 26 27 * po/opcodes.pot: Regenerate 28 292010-10-28 Maciej W. Rozycki <macro@codesourcery.com> 30 31 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld". 32 332010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 34 35 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5. 36 372010-10-25 Chao-ying Fu <fu@mips.com> 38 39 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32. 40 412010-10-25 Nathan Sidwell <nathan@codesourcery.com> 42 43 * tic6x-dis.c: Add attribution. 44 452010-10-22 Alan Modra <amodra@gmail.com> 46 47 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort. 48 * Makefile.in: Regenerate. 49 502010-10-18 Maciej W. Rozycki <macro@linux-mips.org> 51 52 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB 53 macros before their corresponding MIPS III hardware instructions. 54 552010-10-16 H.J. Lu <hongjiu.lu@intel.com> 56 57 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS. 58 59 * i386-init.h: Regenerated. 60 612010-10-15 Mike Frysinger <vapier@gentoo.org> 62 63 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M. 64 652010-10-14 H.J. Lu <hongjiu.lu@intel.com> 66 67 * i386-opc.tbl: Remove CheckRegSize from movq. 68 * i386-tbl.h: Regenerated. 69 702010-10-14 H.J. Lu <hongjiu.lu@intel.com> 71 72 * i386-opc.tbl: Remove CheckRegSize from instructions with 73 0, 1 or fixed operands. 74 * i386-tbl.h: Regenerated. 75 762010-10-14 H.J. Lu <hongjiu.lu@intel.com> 77 78 * i386-gen.c (opcode_modifiers): Add CheckRegSize. 79 80 * i386-opc.h (CheckRegSize): New. 81 (i386_opcode_modifier): Add checkregsize. 82 83 * i386-opc.tbl: Add CheckRegSize to instructions which 84 require register size check. 85 * i386-tbl.h: Regenerated. 86 872010-10-12 Andreas Schwab <schwab@linux-m68k.org> 88 89 * m68k-opc.c (m68k_opcodes): Move fnop before fbf. 90 912010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 92 93 * s390-opc.c: Make the instruction masks for the load/store on 94 condition instructions to cover the condition code mask as well. 95 * s390-opc.txt: lgoc -> locg and stgoc -> stocg. 96 972010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com> 98 Jiang Jilin <freephp@gmail.com> 99 100 * Makefile.am (libopcodes_a_SOURCES): New as empty. 101 * Makefile.in: Regenerate. 102 1032010-10-09 Matt Rice <ratmice@gmail.com> 104 105 * fr30-desc.h: Regenerate. 106 * frv-desc.h: Regenerate. 107 * ip2k-desc.h: Regenerate. 108 * iq2000-desc.h: Regenerate. 109 * lm32-desc.h: Regenerate. 110 * m32c-desc.h: Regenerate. 111 * m32r-desc.h: Regenerate. 112 * mep-desc.h: Regenerate. 113 * mep-opc.c: Regenerate. 114 * mt-desc.h: Regenerate. 115 * openrisc-desc.h: Regenerate. 116 * xc16x-desc.h: Regenerate. 117 * xstormy16-desc.h: Regenerate. 118 1192010-10-08 Pierre Muller <muller@ics.u-strasbg.fr> 120 121 Fix build with -DDEBUG=7 122 * frv-opc.c: Regenerate. 123 * or32-dis.c (DEBUG): Don't redefine. 124 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register): 125 Adapt DEBUG code to some type changes throughout. 126 * or32-opc.c (or32_extract): Likewise. 127 1282010-10-07 Bernd Schmidt <bernds@codesourcery.com> 129 130 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field 131 in SPKERNEL instructions. 132 1332010-10-02 H.J. Lu <hongjiu.lu@intel.com> 134 135 PR binutils/12076 136 * i386-dis.c (RMAL): Remove duplicate. 137 1382010-09-30 Pierre Muller <muller@ics.u-strasbg.fr> 139 140 * s390-mkopc.c (main): Exit with error 1 if sscanf fails 141 to parse all 6 parameters. 142 1432010-09-28 Pierre Muller <muller@ics.u-strasbg.fr> 144 145 * s390-mkopc.c (main): Change description array size to 80. 146 Add maximum length of 79 to description parsing. 147 1482010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> 149 150 * configure: Regenerate. 151 1522010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 153 154 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196. 155 (main): Recognize the new CPU string. 156 * s390-opc.c: Add new instruction formats and masks. 157 * s390-opc.txt: Add new z196 instructions. 158 1592010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 160 161 * s390-dis.c (print_insn_s390): Pick instruction with most 162 specific mask. 163 * s390-opc.c: Add unused bits to the insn mask. 164 * s390-opc.txt: Reorder some instructions to prefer more recent 165 versions. 166 1672010-09-27 Tejas Belagod <tejas.belagod@arm.com> 168 169 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment 170 correction to unaligned PCs while printing comment. 171 1722010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 173 174 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support. 175 (thumb32_opcodes): Likewise. 176 (banked_regname): New function. 177 (print_insn_arm): Add Virtualization Extensions support. 178 (print_insn_thumb32): Likewise. 179 1802010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 181 182 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in 183 ARM state. 184 1852010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 186 187 * arm-dis.c (arm_opcodes): SMC implies Security Extensions. 188 (thumb32_opcodes): Likewise. 189 1902010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 191 192 * arm-dis.c (arm_opcodes): Add support for pldw. 193 (thumb32_opcodes): Likewise. 194 1952010-09-22 Robin Getz <robin.getz@analog.com> 196 197 * bfin-dis.c (fmtconst): Cast address to 32bits. 198 1992010-09-22 Mike Frysinger <vapier@gentoo.org> 200 201 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks. 202 2032010-09-22 Robin Getz <robin.getz@analog.com> 204 205 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns. 206 Reject P6/P7 to TESTSET. 207 (decode_PushPopReg_0): Check for parallel insns. Reject pushing 208 SP onto the stack. 209 (decode_PushPopMultiple_0): Check for parallel insns. Make sure 210 P/D fields match all the time. 211 (decode_CCflag_0): Check for parallel insns. Verify x/y fields 212 are 0 for accumulator compares. 213 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC. 214 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0, 215 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0, 216 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0, 217 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0, 218 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel 219 insns. 220 (decode_dagMODim_0): Verify br field for IREG ops. 221 (decode_LDST_0): Reject preg load into same preg. 222 (_print_insn_bfin): Handle returns for ILLEGAL decodes. 223 (print_insn_bfin): Likewise. 224 2252010-09-22 Mike Frysinger <vapier@gentoo.org> 226 227 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5. 228 2292010-09-22 Robin Getz <robin.getz@analog.com> 230 231 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag. 232 2332010-09-22 Mike Frysinger <vapier@gentoo.org> 234 235 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits. 236 2372010-09-22 Robin Getz <robin.getz@analog.com> 238 239 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject 240 register values greater than 8. 241 (IS_RESERVEDREG, allreg, mostreg): New helpers. 242 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate. 243 (decode_PushPopReg_0): Call mostreg/allreg as appropriate. 244 (decode_CC2dreg_0): Check valid CC register number. 245 2462010-09-22 Robin Getz <robin.getz@analog.com> 247 248 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG. 249 2502010-09-22 Robin Getz <robin.getz@analog.com> 251 252 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD. 253 (reg_names): Likewise. 254 (decode_statbits): Likewise; while reformatting to make manageable. 255 2562010-09-22 Mike Frysinger <vapier@gentoo.org> 257 258 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC. 259 (decode_pseudoOChar_0): New function. 260 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0. 261 2622010-09-22 Robin Getz <robin.getz@analog.com> 263 264 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as 265 LSHIFT instead of SHIFT. 266 2672010-09-22 Mike Frysinger <vapier@gentoo.org> 268 269 * bfin-dis.c (constant_formats): Constify the whole structure. 270 (fmtconst): Add const to return value. 271 (reg_names): Mark const. 272 (decode_multfunc): Mark s0/s1 as const. 273 (decode_macfunc): Mark a/sop as const. 274 2752010-09-17 Tejas Belagod <tejas.belagod@arm.com> 276 277 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv. 278 2792010-09-14 Maciej W. Rozycki <macro@codesourcery.com> 280 281 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire", 282 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb". 283 2842010-09-10 Pierre Muller <muller@ics.u-strasbg.fr> 285 286 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for 287 dlx_insn_type array. 288 2892010-08-31 H.J. Lu <hongjiu.lu@intel.com> 290 291 PR binutils/11960 292 * i386-dis.c (sIv): New. 293 (dis386): Replace Iq with sIv on "pushT". 294 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT. 295 (x86_64_table): Replace {T|}/{P|} with P. 296 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax. 297 (OP_sI): Update v_mode. Remove w_mode. 298 2992010-08-27 Nathan Froyd <froydnj@codesourcery.com> 300 301 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate 302 on E500 and E500MC. 303 3042010-08-17 H.J. Lu <hongjiu.lu@intel.com> 305 306 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and 307 prefetchw. 308 3092010-08-06 Quentin Neill <quentin.neill@amd.com> 310 311 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add 312 to processor flags for PENTIUMPRO processors and later. 313 * i386-opc.h (enum): Add CpuNop. 314 (i386_cpu_flags): Add cpunop bit. 315 * i386-opc.tbl: Change nop cpu_flags. 316 * i386-init.h: Regenerated. 317 * i386-tbl.h: Likewise. 318 3192010-08-06 Quentin Neill <quentin.neill@amd.com> 320 321 * i386-opc.h (enum): Fix typos in comments. 322 3232010-08-06 Alan Modra <amodra@gmail.com> 324 325 * disassemble.c: Formatting. 326 (disassemble_init_for_target <ARCH_m32c>): Comment on endian. 327 3282010-08-05 H.J. Lu <hongjiu.lu@intel.com> 329 330 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b. 331 * i386-tbl.h: Regenerated. 332 3332010-08-05 H.J. Lu <hongjiu.lu@intel.com> 334 335 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1. 336 337 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b. 338 * i386-tbl.h: Regenerated. 339 3402010-07-29 DJ Delorie <dj@redhat.com> 341 342 * rx-decode.opc (SRR): New. 343 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov 344 r0,r0) and NOP3 (max r0,r0) special cases. 345 * rx-decode.c: Regenerate. 346 3472010-07-28 H.J. Lu <hongjiu.lu@intel.com> 348 349 * i386-dis.c: Add 0F to VEX opcode enums. 350 3512010-07-27 DJ Delorie <dj@redhat.com> 352 353 * rx-decode.opc (store_flags): Remove, replace with F_* macros. 354 (rx_decode_opcode): Likewise. 355 * rx-decode.c: Regenerate. 356 3572010-07-23 Naveen.H.S <naveen.S@kpitcummins.com> 358 Ina Pandit <ina.pandit@kpitcummins.com> 359 360 * v850-dis.c (v850_sreg_names): Updated structure for system 361 registers. 362 (float_cc_names): new structure for condition codes. 363 (print_value): Update the function that prints value. 364 (get_operand_value): New function to get the operand value. 365 (disassemble): Updated to handle the disassembly of instructions. 366 (print_insn_v850): Updated function to print instruction for different 367 families. 368 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1, 369 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3, 370 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6, 371 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop, 372 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16, 373 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22, 374 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9, 375 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New. 376 (insert_d8_7, insert_d5_4, insert_i5div): Remove. 377 (v850_operands): Update with the relocation name. Also update 378 the instructions with specific set of processors. 379 3802010-07-08 Tejas Belagod <tejas.belagod@arm.com> 381 382 * arm-dis.c (print_insn_arm): Add cases for printing more 383 symbolic operands. 384 (print_insn_thumb32): Likewise. 385 3862010-07-06 Maciej W. Rozycki <macro@codesourcery.com> 387 388 * mips-dis.c (print_insn_mips): Correct branch instruction type 389 determination. 390 3912010-07-06 Maciej W. Rozycki <macro@codesourcery.com> 392 393 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction 394 type and delay slot determination. 395 (print_insn_mips16): Extend branch instruction type and delay 396 slot determination to cover all instructions. 397 * mips16-opc.c (BR): Remove macro. 398 (UBR, CBR): New macros. 399 (mips16_opcodes): Update branch annotation for "b", "beqz", 400 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc" 401 and "jrc". 402 4032010-07-05 H.J. Lu <hongjiu.lu@intel.com> 404 405 AVX Programming Reference (June, 2010) 406 * i386-dis.c (mod_table): Replace rdrnd with rdrand. 407 * i386-opc.tbl: Likewise. 408 * i386-tbl.h: Regenerated. 409 4102010-07-05 H.J. Lu <hongjiu.lu@intel.com> 411 412 * i386-opc.h (CpuFSGSBase): Fix a typo in comments. 413 4142010-07-03 Andreas Schwab <schwab@linux-m68k.org> 415 416 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to 417 ppc_cpu_t before inverting. 418 (ppc_parse_cpu): Likewise. 419 (print_insn_powerpc): Likewise. 420 4212010-07-03 Alan Modra <amodra@gmail.com> 422 423 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags. 424 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete. 425 (PPC64, MFDEC2): Update. 426 (NON32, NO371): Define. 427 (powerpc_opcode): Update to not use old opcode flags, and avoid 428 -m601 duplicates. 429 4302010-07-03 DJ Delorie <dj@delorie.com> 431 432 * m32c-ibld.c: Regenerate. 433 4342010-07-03 Alan Modra <amodra@gmail.com> 435 436 * ppc-opc.c (PWR2COM): Define. 437 (PPCPWR2): Add PPC_OPCODE_COMMON. 438 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.", 439 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst", 440 "rac" from -mcom. 441 4422010-07-01 H.J. Lu <hongjiu.lu@intel.com> 443 444 AVX Programming Reference (June, 2010) 445 * i386-dis.c (PREFIX_0FAE_REG_0): New. 446 (PREFIX_0FAE_REG_1): Likewise. 447 (PREFIX_0FAE_REG_2): Likewise. 448 (PREFIX_0FAE_REG_3): Likewise. 449 (PREFIX_VEX_3813): Likewise. 450 (PREFIX_VEX_3A1D): Likewise. 451 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, 452 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and 453 PREFIX_VEX_3A1D. 454 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D. 455 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, 456 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd. 457 458 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS, 459 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS. 460 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C. 461 462 * i386-opc.h (CpuXsaveopt): New. 463 (CpuFSGSBase): Likewise. 464 (CpuRdRnd): Likewise. 465 (CpuF16C): Likewise. 466 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and 467 cpuf16c. 468 469 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd, 470 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph. 471 * i386-init.h: Regenerated. 472 * i386-tbl.h: Likewise. 473 4742010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de> 475 476 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf 477 and mtocrf on EFS. 478 4792010-06-29 Alan Modra <amodra@gmail.com> 480 481 * maxq-dis.c: Delete file. 482 * Makefile.am: Remove references to maxq. 483 * configure.in: Likewise. 484 * disassemble.c: Likewise. 485 * Makefile.in: Regenerate. 486 * configure: Regenerate. 487 * po/POTFILES.in: Regenerate. 488 4892010-06-29 Alan Modra <amodra@gmail.com> 490 491 * mep-dis.c: Regenerate. 492 4932010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 494 495 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax. 496 4972010-06-27 Alan Modra <amodra@gmail.com> 498 499 * arc-dis.c (arc_sprintf): Delete set but unused variables. 500 (decodeInstr): Likewise. 501 * dlx-dis.c (print_insn_dlx): Likewise. 502 * h8300-dis.c (bfd_h8_disassemble_init): Likewise. 503 * maxq-dis.c (check_move, print_insn): Likewise. 504 * mep-dis.c (mep_examine_ivc2_insns): Likewise. 505 * msp430-dis.c (msp430_branchinstr): Likewise. 506 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning. 507 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise. 508 * sparc-dis.c (print_insn_sparc): Likewise. 509 * fr30-asm.c: Regenerate. 510 * frv-asm.c: Regenerate. 511 * ip2k-asm.c: Regenerate. 512 * iq2000-asm.c: Regenerate. 513 * lm32-asm.c: Regenerate. 514 * m32c-asm.c: Regenerate. 515 * m32r-asm.c: Regenerate. 516 * mep-asm.c: Regenerate. 517 * mt-asm.c: Regenerate. 518 * openrisc-asm.c: Regenerate. 519 * xc16x-asm.c: Regenerate. 520 * xstormy16-asm.c: Regenerate. 521 5222010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr> 523 524 PR gas/11673 525 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later. 526 5272010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr> 528 529 PR binutils/11676 530 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e. 531 5322010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de> 533 534 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and 535 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2 536 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which 537 touch floating point regs and are enabled by COM, PPC or PPCCOM. 538 Treat sync as msync on e500. Treat eieio as mbar 1 on e500. 539 Treat lwsync as msync on e500. 540 5412010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 542 543 * arm-dis.c (thumb-opcodes): Add disassembly for movs. 544 5452010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 546 547 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon 548 constants is the same on 32-bit and 64-bit hosts. 549 5502010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com> 551 552 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as 553 .short directives so that they can be reassembled. 554 5552010-05-26 Catherine Moore <clm@codesourcery.com> 556 David Ung <davidu@mips.com> 557 558 * mips-opc.c: Change membership to I1 for instructions ssnop and 559 ehb. 560 5612010-05-26 H.J. Lu <hongjiu.lu@intel.com> 562 563 * i386-dis.c (sib): New. 564 (get_sib): Likewise. 565 (print_insn): Call get_sib. 566 OP_E_memory): Use sib. 567 5682010-05-26 Catherine Moore <clm@codesoourcery.com> 569 570 * mips-dis.c (mips_arch): Remove INSN_MIPS16. 571 * mips-opc.c (I16): Remove. 572 (mips_builtin_op): Reclassify jalx. 573 5742010-05-19 Alan Modra <amodra@gmail.com> 575 576 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde, 577 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx. 578 5792010-05-13 Alan Modra <amodra@gmail.com> 580 581 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding. 582 5832010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 584 585 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W 586 format. 587 (print_insn_thumb16): Add support for new %W format. 588 5892010-05-07 Tristan Gingold <gingold@adacore.com> 590 591 * Makefile.in: Regenerate with automake 1.11.1. 592 * aclocal.m4: Ditto. 593 5942010-05-05 Nick Clifton <nickc@redhat.com> 595 596 * po/es.po: Updated Spanish translation. 597 5982010-04-22 Nick Clifton <nickc@redhat.com> 599 600 * po/opcodes.pot: Updated by the Translation project. 601 * po/vi.po: Updated Vietnamese translation. 602 6032010-04-16 H.J. Lu <hongjiu.lu@intel.com> 604 605 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown 606 bits in opcode. 607 6082010-04-09 Nick Clifton <nickc@redhat.com> 609 610 * i386-dis.c (print_insn): Remove unused variable op. 611 (OP_sI): Remove unused variable mask. 612 6132010-04-07 Alan Modra <amodra@gmail.com> 614 615 * configure: Regenerate. 616 6172010-04-06 Peter Bergner <bergner@vnet.ibm.com> 618 619 * ppc-opc.c (RBOPT): New define. 620 ("dccci"): Enable for PPCA2. Make operands optional. 621 ("iccci"): Likewise. Do not deprecate for PPC476. 622 6232010-04-02 Masaki Muranaka <monaka@monami-software.com> 624 625 * cr16-opc.c (cr16_instruction): Fix typo in comment. 626 6272010-03-25 Joseph Myers <joseph@codesourcery.com> 628 629 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c. 630 * Makefile.in: Regenerate. 631 * configure.in (bfd_tic6x_arch): New. 632 * configure: Regenerate. 633 * disassemble.c (ARCH_tic6x): Define if ARCH_all. 634 (disassembler): Handle TI C6X. 635 * tic6x-dis.c: New. 636 6372010-03-24 Mike Frysinger <vapier@gentoo.org> 638 639 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2. 640 6412010-03-23 Joseph Myers <joseph@codesourcery.com> 642 643 * dis-buf.c (buffer_read_memory): Give error for reading just 644 before the start of memory. 645 6462010-03-22 Sebastian Pop <sebastian.pop@amd.com> 647 Quentin Neill <quentin.neill@amd.com> 648 649 * i386-dis.c (OP_LWP_I): Removed. 650 (reg_table): Do not use OP_LWP_I, use Iq. 651 (OP_LWPCB_E): Remove use of names16. 652 (OP_LWP_E): Same. 653 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns 654 should not set the Vex.length bit. 655 * i386-tbl.h: Regenerated. 656 6572010-02-25 Edmar Wienskoski <edmar@freescale.com> 658 659 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64". 660 6612010-02-24 Nick Clifton <nickc@redhat.com> 662 663 PR binutils/6773 664 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with 665 <prefix>asx. Replace <prefix>subaddx with <prefix>sax. 666 (thumb32_opcodes): Likewise. 667 6682010-02-15 Nick Clifton <nickc@redhat.com> 669 670 * po/vi.po: Updated Vietnamese translation. 671 6722010-02-12 Doug Evans <dje@sebabeach.org> 673 674 * lm32-opinst.c: Regenerate. 675 6762010-02-11 Doug Evans <dje@sebabeach.org> 677 678 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL. 679 (print_address): Delete CGEN_PRINT_ADDRESS. 680 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c, 681 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h, 682 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c, 683 * xc16x-dis.c, * xstormy16-dis.c: Regenerate. 684 685 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c, 686 * frv-desc.c, * frv-desc.h, * frv-opc.c, 687 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c, 688 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c, 689 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c, 690 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c, 691 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c, 692 * mep-desc.c, * mep-desc.h, * mep-opc.c, 693 * mt-desc.c, * mt-desc.h, * mt-opc.c, 694 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c, 695 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c, 696 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate. 697 6982010-02-11 H.J. Lu <hongjiu.lu@intel.com> 699 700 * i386-dis.c: Update copyright. 701 * i386-gen.c: Likewise. 702 * i386-opc.h: Likewise. 703 * i386-opc.tbl: Likewise. 704 7052010-02-10 Quentin Neill <quentin.neill@amd.com> 706 Sebastian Pop <sebastian.pop@amd.com> 707 708 * i386-dis.c (OP_EX_VexImmW): Reintroduced 709 function to handle 5th imm8 operand. 710 (PREFIX_VEX_3A48): Added. 711 (PREFIX_VEX_3A49): Added. 712 (VEX_W_3A48_P_2): Added. 713 (VEX_W_3A49_P_2): Added. 714 (prefix table): Added entries for PREFIX_VEX_3A48 715 and PREFIX_VEX_3A49. 716 (vex table): Added entries for VEX_W_3A48_P_2 and 717 and VEX_W_3A49_P_2. 718 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4 719 for Vec_Imm4 operands. 720 * i386-opc.h (enum): Added Vec_Imm4. 721 (i386_operand_type): Added vec_imm4. 722 * i386-opc.tbl: Add entries for vpermilp[ds]. 723 * i386-init.h: Regenerated. 724 * i386-tbl.h: Regenerated. 725 7262010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com> 727 728 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6" 729 and "pwr7". Move "a2" into alphabetical order. 730 7312010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 732 733 * ppc-dis.c (ppc_opts): Add titan entry. 734 * ppc-opc.c (TITAN, MULHW): Define. 735 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx). 736 7372010-02-03 Quentin Neill <quentin.neill@amd.com> 738 739 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS 740 to CPU_BDVER1_FLAGS 741 * i386-init.h: Regenerated. 742 7432010-02-03 Anthony Green <green@moxielogic.com> 744 745 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to 746 0x0f, and make 0x00 an illegal instruction. 747 7482010-01-29 Daniel Jacobowitz <dan@codesourcery.com> 749 750 * opcodes/arm-dis.c (struct arm_private_data): New. 751 (print_insn_coprocessor, print_insn_arm): Update to use struct 752 arm_private_data. 753 (is_mapping_symbol, get_map_sym_type): New functions. 754 (get_sym_code_type): Check the symbol's section. Do not check 755 mapping symbols. 756 (print_insn): Default to disassembling ARM mode code. Check 757 for mapping symbols separately from other symbols. Use 758 struct arm_private_data. 759 7602010-01-28 H.J. Lu <hongjiu.lu@intel.com> 761 762 * i386-dis.c (EXVexWdqScalar): New. 763 (vex_scalar_w_dq_mode): Likewise. 764 (prefix_table): Update entries for PREFIX_VEX_3899, 765 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F, 766 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD, 767 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB, 768 PREFIX_VEX_38BD and PREFIX_VEX_38BF. 769 (intel_operand_size): Handle vex_scalar_w_dq_mode. 770 (OP_EX): Likewise. 771 7722010-01-27 H.J. Lu <hongjiu.lu@intel.com> 773 774 * i386-dis.c (XMScalar): New. 775 (EXdScalar): Likewise. 776 (EXqScalar): Likewise. 777 (EXqScalarS): Likewise. 778 (VexScalar): Likewise. 779 (EXdVexScalarS): Likewise. 780 (EXqVexScalarS): Likewise. 781 (XMVexScalar): Likewise. 782 (scalar_mode): Likewise. 783 (d_scalar_mode): Likewise. 784 (d_scalar_swap_mode): Likewise. 785 (q_scalar_mode): Likewise. 786 (q_scalar_swap_mode): Likewise. 787 (vex_scalar_mode): Likewise. 788 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1, 789 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1, 790 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0, 791 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3, 792 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3, 793 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1, 794 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1, 795 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2, 796 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1, 797 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2. 798 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3, 799 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2, 800 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3, 801 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3, 802 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3, 803 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3, 804 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3, 805 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3, 806 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2. 807 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode, 808 q_scalar_mode, q_scalar_swap_mode. 809 (OP_XMM): Handle scalar_mode. 810 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode 811 and q_scalar_swap_mode. 812 (OP_VEX): Handle vex_scalar_mode. 813 8142010-01-24 H.J. Lu <hongjiu.lu@intel.com> 815 816 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }. 817 8182010-01-24 H.J. Lu <hongjiu.lu@intel.com> 819 820 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }. 821 8222010-01-24 H.J. Lu <hongjiu.lu@intel.com> 823 824 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }. 825 8262010-01-24 H.J. Lu <hongjiu.lu@intel.com> 827 828 * i386-dis.c (Bad_Opcode): New. 829 (bad_opcode): Likewise. 830 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }. 831 (dis386_twobyte): Likewise. 832 (reg_table): Likewise. 833 (prefix_table): Likewise. 834 (x86_64_table): Likewise. 835 (vex_len_table): Likewise. 836 (vex_w_table): Likewise. 837 (mod_table): Likewise. 838 (rm_table): Likewise. 839 (float_reg): Likewise. 840 (reg_table): Remove trailing "(bad)" entries. 841 (prefix_table): Likewise. 842 (x86_64_table): Likewise. 843 (vex_len_table): Likewise. 844 (vex_w_table): Likewise. 845 (mod_table): Likewise. 846 (rm_table): Likewise. 847 (get_valid_dis386): Handle bytemode 0. 848 8492010-01-23 H.J. Lu <hongjiu.lu@intel.com> 850 851 * i386-opc.h (VEXScalar): New. 852 853 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar 854 instructions. 855 * i386-tbl.h: Regenerated. 856 8572010-01-21 H.J. Lu <hongjiu.lu@intel.com> 858 859 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor. 860 861 * i386-opc.tbl: Add xsave64 and xrstor64. 862 * i386-tbl.h: Regenerated. 863 8642010-01-20 Nick Clifton <nickc@redhat.com> 865 866 PR 11170 867 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC 868 based post-indexed addressing. 869 8702010-01-15 Sebastian Pop <sebastian.pop@amd.com> 871 872 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns. 873 * i386-tbl.h: Regenerated. 874 8752010-01-14 H.J. Lu <hongjiu.lu@intel.com> 876 877 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in 878 comments. 879 8802010-01-14 H.J. Lu <hongjiu.lu@intel.com> 881 882 * i386-dis.c (names_mm): New. 883 (intel_names_mm): Likewise. 884 (att_names_mm): Likewise. 885 (names_xmm): Likewise. 886 (intel_names_xmm): Likewise. 887 (att_names_xmm): Likewise. 888 (names_ymm): Likewise. 889 (intel_names_ymm): Likewise. 890 (att_names_ymm): Likewise. 891 (print_insn): Set names_mm, names_xmm and names_ymm. 892 (OP_MMX): Use names_mm, names_xmm and names_ymm. 893 (OP_XMM): Likewise. 894 (OP_EM): Likewise. 895 (OP_EMC): Likewise. 896 (OP_MXC): Likewise. 897 (OP_EX): Likewise. 898 (XMM_Fixup): Likewise. 899 (OP_VEX): Likewise. 900 (OP_EX_VexReg): Likewise. 901 (OP_Vex_2src): Likewise. 902 (OP_Vex_2src_1): Likewise. 903 (OP_Vex_2src_2): Likewise. 904 (OP_REG_VexI4): Likewise. 905 9062010-01-13 H.J. Lu <hongjiu.lu@intel.com> 907 908 * i386-dis.c (print_insn): Update comments. 909 9102010-01-12 H.J. Lu <hongjiu.lu@intel.com> 911 912 * i386-dis.c (rex_original): Removed. 913 (ckprefix): Remove rex_original. 914 (print_insn): Update comments. 915 9162010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> 917 918 * Makefile.in: Regenerate. 919 * configure: Regenerate. 920 9212010-01-07 Doug Evans <dje@sebabeach.org> 922 923 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup. 924 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, 925 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, 926 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, 927 * xstormy16-ibld.c: Regenerate. 928 9292010-01-06 Quentin Neill <quentin.neill@amd.com> 930 931 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS. 932 * i386-init.h: Regenerated. 933 9342010-01-06 Daniel Gutson <dgutson@codesourcery.com> 935 936 * arm-dis.c (print_insn): Fixed search for next symbol and data 937 dumping condition, and the initial mapping symbol state. 938 9392010-01-05 Doug Evans <dje@sebabeach.org> 940 941 * cgen-ibld.in: #include "cgen/basic-modes.h". 942 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, 943 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, 944 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, 945 * xstormy16-ibld.c: Regenerate. 946 9472010-01-04 Nick Clifton <nickc@redhat.com> 948 949 PR 11123 950 * arm-dis.c (print_insn_coprocessor): Initialise value. 951 9522010-01-04 Edmar Wienskoski <edmar@freescale.com> 953 954 * ppc-dis.c (ppc_opts): Add entry for "e500mc64". 955 9562010-01-02 Doug Evans <dje@sebabeach.org> 957 958 * cgen-asm.in: Update copyright year. 959 * cgen-dis.in: Update copyright year. 960 * cgen-ibld.in: Update copyright year. 961 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c, 962 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c, 963 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h, 964 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c, 965 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c, 966 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c, 967 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c, 968 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h, 969 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h, 970 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c, 971 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c, 972 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c, 973 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h, 974 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c, 975 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c, 976 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c, 977 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c, 978 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c, 979 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c, 980 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c, 981 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate. 982 983For older changes see ChangeLog-2009 984 985Local Variables: 986mode: change-log 987left-margin: 8 988fill-column: 74 989version-control: never 990End: 991