12010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2 3 PR gas/11395 4 * hppa-dis.c (compare_cond_64_names): Change never condition to ",*". 5 (add_cond_64_names): Likewise. 6 (logical_cond_64_names): Likewise. 7 (unit_cond_64_names): Likewise. 8 92010-12-30 H.J. Lu <hongjiu.lu@intel.com> 10 11 * i386-dis.c (print_insn): Support bfd_mach_x64_32 and 12 bfd_mach_x64_32_intel_syntax. 13 142010-12-18 Mingjie Xing <mingjie.xing@gmail.com> 15 16 * mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define. 17 (mips_builtin_opcodes): Add loongson3a specific instructions. 18 * mips-dis.c (print_insn_args): Handle the new arguments +a|b|c|z|Z. 19 202010-12-11 Mingming Sun <mingm.sun@gmail.com> 21 22 * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and 23 fixed point instructions. 24 252010-12-09 Mike Frysinger <vapier@gentoo.org> 26 27 * .gitignore: New file. 28 292010-11-25 Alan Modra <amodra@gmail.com> 30 31 * po/es.po: Update. 32 * po/fr.po: Update. 33 * po/nl.po: Update. 34 * po/zh_CN.po: Update. 35 362010-11-11 Mingming Sun <mingm.sun@gmail.com> 37 38 * mips-dis.c (mips_arch_choices): Add loongson3a. 39 * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A. 40 (mips_builtin_opcodes): Modify some instructions' membership from 41 IL2F to IL2F|IL3A. 42 432010-11-10 Nick Clifton <nickc@redhat.com> 44 45 * po/fi.po: Updated Finnish translation. 46 472010-11-05 Tristan Gingold <gingold@adacore.com> 48 49 * po/opcodes.pot: Regenerate 50 512010-10-28 Maciej W. Rozycki <macro@codesourcery.com> 52 53 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld". 54 552010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 56 57 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5. 58 592010-10-25 Chao-ying Fu <fu@mips.com> 60 61 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32. 62 632010-10-25 Nathan Sidwell <nathan@codesourcery.com> 64 65 * tic6x-dis.c: Add attribution. 66 672010-10-22 Alan Modra <amodra@gmail.com> 68 69 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort. 70 * Makefile.in: Regenerate. 71 722010-10-18 Maciej W. Rozycki <macro@linux-mips.org> 73 74 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB 75 macros before their corresponding MIPS III hardware instructions. 76 772010-10-16 H.J. Lu <hongjiu.lu@intel.com> 78 79 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS. 80 81 * i386-init.h: Regenerated. 82 832010-10-15 Mike Frysinger <vapier@gentoo.org> 84 85 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M. 86 872010-10-14 H.J. Lu <hongjiu.lu@intel.com> 88 89 * i386-opc.tbl: Remove CheckRegSize from movq. 90 * i386-tbl.h: Regenerated. 91 922010-10-14 H.J. Lu <hongjiu.lu@intel.com> 93 94 * i386-opc.tbl: Remove CheckRegSize from instructions with 95 0, 1 or fixed operands. 96 * i386-tbl.h: Regenerated. 97 982010-10-14 H.J. Lu <hongjiu.lu@intel.com> 99 100 * i386-gen.c (opcode_modifiers): Add CheckRegSize. 101 102 * i386-opc.h (CheckRegSize): New. 103 (i386_opcode_modifier): Add checkregsize. 104 105 * i386-opc.tbl: Add CheckRegSize to instructions which 106 require register size check. 107 * i386-tbl.h: Regenerated. 108 1092010-10-12 Andreas Schwab <schwab@linux-m68k.org> 110 111 * m68k-opc.c (m68k_opcodes): Move fnop before fbf. 112 1132010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 114 115 * s390-opc.c: Make the instruction masks for the load/store on 116 condition instructions to cover the condition code mask as well. 117 * s390-opc.txt: lgoc -> locg and stgoc -> stocg. 118 1192010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com> 120 Jiang Jilin <freephp@gmail.com> 121 122 * Makefile.am (libopcodes_a_SOURCES): New as empty. 123 * Makefile.in: Regenerate. 124 1252010-10-09 Matt Rice <ratmice@gmail.com> 126 127 * fr30-desc.h: Regenerate. 128 * frv-desc.h: Regenerate. 129 * ip2k-desc.h: Regenerate. 130 * iq2000-desc.h: Regenerate. 131 * lm32-desc.h: Regenerate. 132 * m32c-desc.h: Regenerate. 133 * m32r-desc.h: Regenerate. 134 * mep-desc.h: Regenerate. 135 * mep-opc.c: Regenerate. 136 * mt-desc.h: Regenerate. 137 * openrisc-desc.h: Regenerate. 138 * xc16x-desc.h: Regenerate. 139 * xstormy16-desc.h: Regenerate. 140 1412010-10-08 Pierre Muller <muller@ics.u-strasbg.fr> 142 143 Fix build with -DDEBUG=7 144 * frv-opc.c: Regenerate. 145 * or32-dis.c (DEBUG): Don't redefine. 146 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register): 147 Adapt DEBUG code to some type changes throughout. 148 * or32-opc.c (or32_extract): Likewise. 149 1502010-10-07 Bernd Schmidt <bernds@codesourcery.com> 151 152 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field 153 in SPKERNEL instructions. 154 1552010-10-02 H.J. Lu <hongjiu.lu@intel.com> 156 157 PR binutils/12076 158 * i386-dis.c (RMAL): Remove duplicate. 159 1602010-09-30 Pierre Muller <muller@ics.u-strasbg.fr> 161 162 * s390-mkopc.c (main): Exit with error 1 if sscanf fails 163 to parse all 6 parameters. 164 1652010-09-28 Pierre Muller <muller@ics.u-strasbg.fr> 166 167 * s390-mkopc.c (main): Change description array size to 80. 168 Add maximum length of 79 to description parsing. 169 1702010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> 171 172 * configure: Regenerate. 173 1742010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 175 176 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196. 177 (main): Recognize the new CPU string. 178 * s390-opc.c: Add new instruction formats and masks. 179 * s390-opc.txt: Add new z196 instructions. 180 1812010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 182 183 * s390-dis.c (print_insn_s390): Pick instruction with most 184 specific mask. 185 * s390-opc.c: Add unused bits to the insn mask. 186 * s390-opc.txt: Reorder some instructions to prefer more recent 187 versions. 188 1892010-09-27 Tejas Belagod <tejas.belagod@arm.com> 190 191 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment 192 correction to unaligned PCs while printing comment. 193 1942010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 195 196 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support. 197 (thumb32_opcodes): Likewise. 198 (banked_regname): New function. 199 (print_insn_arm): Add Virtualization Extensions support. 200 (print_insn_thumb32): Likewise. 201 2022010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 203 204 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in 205 ARM state. 206 2072010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 208 209 * arm-dis.c (arm_opcodes): SMC implies Security Extensions. 210 (thumb32_opcodes): Likewise. 211 2122010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 213 214 * arm-dis.c (arm_opcodes): Add support for pldw. 215 (thumb32_opcodes): Likewise. 216 2172010-09-22 Robin Getz <robin.getz@analog.com> 218 219 * bfin-dis.c (fmtconst): Cast address to 32bits. 220 2212010-09-22 Mike Frysinger <vapier@gentoo.org> 222 223 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks. 224 2252010-09-22 Robin Getz <robin.getz@analog.com> 226 227 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns. 228 Reject P6/P7 to TESTSET. 229 (decode_PushPopReg_0): Check for parallel insns. Reject pushing 230 SP onto the stack. 231 (decode_PushPopMultiple_0): Check for parallel insns. Make sure 232 P/D fields match all the time. 233 (decode_CCflag_0): Check for parallel insns. Verify x/y fields 234 are 0 for accumulator compares. 235 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC. 236 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0, 237 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0, 238 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0, 239 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0, 240 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel 241 insns. 242 (decode_dagMODim_0): Verify br field for IREG ops. 243 (decode_LDST_0): Reject preg load into same preg. 244 (_print_insn_bfin): Handle returns for ILLEGAL decodes. 245 (print_insn_bfin): Likewise. 246 2472010-09-22 Mike Frysinger <vapier@gentoo.org> 248 249 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5. 250 2512010-09-22 Robin Getz <robin.getz@analog.com> 252 253 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag. 254 2552010-09-22 Mike Frysinger <vapier@gentoo.org> 256 257 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits. 258 2592010-09-22 Robin Getz <robin.getz@analog.com> 260 261 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject 262 register values greater than 8. 263 (IS_RESERVEDREG, allreg, mostreg): New helpers. 264 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate. 265 (decode_PushPopReg_0): Call mostreg/allreg as appropriate. 266 (decode_CC2dreg_0): Check valid CC register number. 267 2682010-09-22 Robin Getz <robin.getz@analog.com> 269 270 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG. 271 2722010-09-22 Robin Getz <robin.getz@analog.com> 273 274 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD. 275 (reg_names): Likewise. 276 (decode_statbits): Likewise; while reformatting to make manageable. 277 2782010-09-22 Mike Frysinger <vapier@gentoo.org> 279 280 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC. 281 (decode_pseudoOChar_0): New function. 282 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0. 283 2842010-09-22 Robin Getz <robin.getz@analog.com> 285 286 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as 287 LSHIFT instead of SHIFT. 288 2892010-09-22 Mike Frysinger <vapier@gentoo.org> 290 291 * bfin-dis.c (constant_formats): Constify the whole structure. 292 (fmtconst): Add const to return value. 293 (reg_names): Mark const. 294 (decode_multfunc): Mark s0/s1 as const. 295 (decode_macfunc): Mark a/sop as const. 296 2972010-09-17 Tejas Belagod <tejas.belagod@arm.com> 298 299 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv. 300 3012010-09-14 Maciej W. Rozycki <macro@codesourcery.com> 302 303 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire", 304 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb". 305 3062010-09-10 Pierre Muller <muller@ics.u-strasbg.fr> 307 308 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for 309 dlx_insn_type array. 310 3112010-08-31 H.J. Lu <hongjiu.lu@intel.com> 312 313 PR binutils/11960 314 * i386-dis.c (sIv): New. 315 (dis386): Replace Iq with sIv on "pushT". 316 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT. 317 (x86_64_table): Replace {T|}/{P|} with P. 318 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax. 319 (OP_sI): Update v_mode. Remove w_mode. 320 3212010-08-27 Nathan Froyd <froydnj@codesourcery.com> 322 323 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate 324 on E500 and E500MC. 325 3262010-08-17 H.J. Lu <hongjiu.lu@intel.com> 327 328 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and 329 prefetchw. 330 3312010-08-06 Quentin Neill <quentin.neill@amd.com> 332 333 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add 334 to processor flags for PENTIUMPRO processors and later. 335 * i386-opc.h (enum): Add CpuNop. 336 (i386_cpu_flags): Add cpunop bit. 337 * i386-opc.tbl: Change nop cpu_flags. 338 * i386-init.h: Regenerated. 339 * i386-tbl.h: Likewise. 340 3412010-08-06 Quentin Neill <quentin.neill@amd.com> 342 343 * i386-opc.h (enum): Fix typos in comments. 344 3452010-08-06 Alan Modra <amodra@gmail.com> 346 347 * disassemble.c: Formatting. 348 (disassemble_init_for_target <ARCH_m32c>): Comment on endian. 349 3502010-08-05 H.J. Lu <hongjiu.lu@intel.com> 351 352 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b. 353 * i386-tbl.h: Regenerated. 354 3552010-08-05 H.J. Lu <hongjiu.lu@intel.com> 356 357 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1. 358 359 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b. 360 * i386-tbl.h: Regenerated. 361 3622010-07-29 DJ Delorie <dj@redhat.com> 363 364 * rx-decode.opc (SRR): New. 365 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov 366 r0,r0) and NOP3 (max r0,r0) special cases. 367 * rx-decode.c: Regenerate. 368 3692010-07-28 H.J. Lu <hongjiu.lu@intel.com> 370 371 * i386-dis.c: Add 0F to VEX opcode enums. 372 3732010-07-27 DJ Delorie <dj@redhat.com> 374 375 * rx-decode.opc (store_flags): Remove, replace with F_* macros. 376 (rx_decode_opcode): Likewise. 377 * rx-decode.c: Regenerate. 378 3792010-07-23 Naveen.H.S <naveen.S@kpitcummins.com> 380 Ina Pandit <ina.pandit@kpitcummins.com> 381 382 * v850-dis.c (v850_sreg_names): Updated structure for system 383 registers. 384 (float_cc_names): new structure for condition codes. 385 (print_value): Update the function that prints value. 386 (get_operand_value): New function to get the operand value. 387 (disassemble): Updated to handle the disassembly of instructions. 388 (print_insn_v850): Updated function to print instruction for different 389 families. 390 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1, 391 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3, 392 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6, 393 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop, 394 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16, 395 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22, 396 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9, 397 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New. 398 (insert_d8_7, insert_d5_4, insert_i5div): Remove. 399 (v850_operands): Update with the relocation name. Also update 400 the instructions with specific set of processors. 401 4022010-07-08 Tejas Belagod <tejas.belagod@arm.com> 403 404 * arm-dis.c (print_insn_arm): Add cases for printing more 405 symbolic operands. 406 (print_insn_thumb32): Likewise. 407 4082010-07-06 Maciej W. Rozycki <macro@codesourcery.com> 409 410 * mips-dis.c (print_insn_mips): Correct branch instruction type 411 determination. 412 4132010-07-06 Maciej W. Rozycki <macro@codesourcery.com> 414 415 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction 416 type and delay slot determination. 417 (print_insn_mips16): Extend branch instruction type and delay 418 slot determination to cover all instructions. 419 * mips16-opc.c (BR): Remove macro. 420 (UBR, CBR): New macros. 421 (mips16_opcodes): Update branch annotation for "b", "beqz", 422 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc" 423 and "jrc". 424 4252010-07-05 H.J. Lu <hongjiu.lu@intel.com> 426 427 AVX Programming Reference (June, 2010) 428 * i386-dis.c (mod_table): Replace rdrnd with rdrand. 429 * i386-opc.tbl: Likewise. 430 * i386-tbl.h: Regenerated. 431 4322010-07-05 H.J. Lu <hongjiu.lu@intel.com> 433 434 * i386-opc.h (CpuFSGSBase): Fix a typo in comments. 435 4362010-07-03 Andreas Schwab <schwab@linux-m68k.org> 437 438 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to 439 ppc_cpu_t before inverting. 440 (ppc_parse_cpu): Likewise. 441 (print_insn_powerpc): Likewise. 442 4432010-07-03 Alan Modra <amodra@gmail.com> 444 445 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags. 446 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete. 447 (PPC64, MFDEC2): Update. 448 (NON32, NO371): Define. 449 (powerpc_opcode): Update to not use old opcode flags, and avoid 450 -m601 duplicates. 451 4522010-07-03 DJ Delorie <dj@delorie.com> 453 454 * m32c-ibld.c: Regenerate. 455 4562010-07-03 Alan Modra <amodra@gmail.com> 457 458 * ppc-opc.c (PWR2COM): Define. 459 (PPCPWR2): Add PPC_OPCODE_COMMON. 460 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.", 461 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst", 462 "rac" from -mcom. 463 4642010-07-01 H.J. Lu <hongjiu.lu@intel.com> 465 466 AVX Programming Reference (June, 2010) 467 * i386-dis.c (PREFIX_0FAE_REG_0): New. 468 (PREFIX_0FAE_REG_1): Likewise. 469 (PREFIX_0FAE_REG_2): Likewise. 470 (PREFIX_0FAE_REG_3): Likewise. 471 (PREFIX_VEX_3813): Likewise. 472 (PREFIX_VEX_3A1D): Likewise. 473 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, 474 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and 475 PREFIX_VEX_3A1D. 476 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D. 477 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, 478 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd. 479 480 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS, 481 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS. 482 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C. 483 484 * i386-opc.h (CpuXsaveopt): New. 485 (CpuFSGSBase): Likewise. 486 (CpuRdRnd): Likewise. 487 (CpuF16C): Likewise. 488 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and 489 cpuf16c. 490 491 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd, 492 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph. 493 * i386-init.h: Regenerated. 494 * i386-tbl.h: Likewise. 495 4962010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de> 497 498 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf 499 and mtocrf on EFS. 500 5012010-06-29 Alan Modra <amodra@gmail.com> 502 503 * maxq-dis.c: Delete file. 504 * Makefile.am: Remove references to maxq. 505 * configure.in: Likewise. 506 * disassemble.c: Likewise. 507 * Makefile.in: Regenerate. 508 * configure: Regenerate. 509 * po/POTFILES.in: Regenerate. 510 5112010-06-29 Alan Modra <amodra@gmail.com> 512 513 * mep-dis.c: Regenerate. 514 5152010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 516 517 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax. 518 5192010-06-27 Alan Modra <amodra@gmail.com> 520 521 * arc-dis.c (arc_sprintf): Delete set but unused variables. 522 (decodeInstr): Likewise. 523 * dlx-dis.c (print_insn_dlx): Likewise. 524 * h8300-dis.c (bfd_h8_disassemble_init): Likewise. 525 * maxq-dis.c (check_move, print_insn): Likewise. 526 * mep-dis.c (mep_examine_ivc2_insns): Likewise. 527 * msp430-dis.c (msp430_branchinstr): Likewise. 528 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning. 529 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise. 530 * sparc-dis.c (print_insn_sparc): Likewise. 531 * fr30-asm.c: Regenerate. 532 * frv-asm.c: Regenerate. 533 * ip2k-asm.c: Regenerate. 534 * iq2000-asm.c: Regenerate. 535 * lm32-asm.c: Regenerate. 536 * m32c-asm.c: Regenerate. 537 * m32r-asm.c: Regenerate. 538 * mep-asm.c: Regenerate. 539 * mt-asm.c: Regenerate. 540 * openrisc-asm.c: Regenerate. 541 * xc16x-asm.c: Regenerate. 542 * xstormy16-asm.c: Regenerate. 543 5442010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr> 545 546 PR gas/11673 547 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later. 548 5492010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr> 550 551 PR binutils/11676 552 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e. 553 5542010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de> 555 556 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and 557 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2 558 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which 559 touch floating point regs and are enabled by COM, PPC or PPCCOM. 560 Treat sync as msync on e500. Treat eieio as mbar 1 on e500. 561 Treat lwsync as msync on e500. 562 5632010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 564 565 * arm-dis.c (thumb-opcodes): Add disassembly for movs. 566 5672010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 568 569 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon 570 constants is the same on 32-bit and 64-bit hosts. 571 5722010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com> 573 574 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as 575 .short directives so that they can be reassembled. 576 5772010-05-26 Catherine Moore <clm@codesourcery.com> 578 David Ung <davidu@mips.com> 579 580 * mips-opc.c: Change membership to I1 for instructions ssnop and 581 ehb. 582 5832010-05-26 H.J. Lu <hongjiu.lu@intel.com> 584 585 * i386-dis.c (sib): New. 586 (get_sib): Likewise. 587 (print_insn): Call get_sib. 588 OP_E_memory): Use sib. 589 5902010-05-26 Catherine Moore <clm@codesoourcery.com> 591 592 * mips-dis.c (mips_arch): Remove INSN_MIPS16. 593 * mips-opc.c (I16): Remove. 594 (mips_builtin_op): Reclassify jalx. 595 5962010-05-19 Alan Modra <amodra@gmail.com> 597 598 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde, 599 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx. 600 6012010-05-13 Alan Modra <amodra@gmail.com> 602 603 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding. 604 6052010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 606 607 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W 608 format. 609 (print_insn_thumb16): Add support for new %W format. 610 6112010-05-07 Tristan Gingold <gingold@adacore.com> 612 613 * Makefile.in: Regenerate with automake 1.11.1. 614 * aclocal.m4: Ditto. 615 6162010-05-05 Nick Clifton <nickc@redhat.com> 617 618 * po/es.po: Updated Spanish translation. 619 6202010-04-22 Nick Clifton <nickc@redhat.com> 621 622 * po/opcodes.pot: Updated by the Translation project. 623 * po/vi.po: Updated Vietnamese translation. 624 6252010-04-16 H.J. Lu <hongjiu.lu@intel.com> 626 627 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown 628 bits in opcode. 629 6302010-04-09 Nick Clifton <nickc@redhat.com> 631 632 * i386-dis.c (print_insn): Remove unused variable op. 633 (OP_sI): Remove unused variable mask. 634 6352010-04-07 Alan Modra <amodra@gmail.com> 636 637 * configure: Regenerate. 638 6392010-04-06 Peter Bergner <bergner@vnet.ibm.com> 640 641 * ppc-opc.c (RBOPT): New define. 642 ("dccci"): Enable for PPCA2. Make operands optional. 643 ("iccci"): Likewise. Do not deprecate for PPC476. 644 6452010-04-02 Masaki Muranaka <monaka@monami-software.com> 646 647 * cr16-opc.c (cr16_instruction): Fix typo in comment. 648 6492010-03-25 Joseph Myers <joseph@codesourcery.com> 650 651 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c. 652 * Makefile.in: Regenerate. 653 * configure.in (bfd_tic6x_arch): New. 654 * configure: Regenerate. 655 * disassemble.c (ARCH_tic6x): Define if ARCH_all. 656 (disassembler): Handle TI C6X. 657 * tic6x-dis.c: New. 658 6592010-03-24 Mike Frysinger <vapier@gentoo.org> 660 661 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2. 662 6632010-03-23 Joseph Myers <joseph@codesourcery.com> 664 665 * dis-buf.c (buffer_read_memory): Give error for reading just 666 before the start of memory. 667 6682010-03-22 Sebastian Pop <sebastian.pop@amd.com> 669 Quentin Neill <quentin.neill@amd.com> 670 671 * i386-dis.c (OP_LWP_I): Removed. 672 (reg_table): Do not use OP_LWP_I, use Iq. 673 (OP_LWPCB_E): Remove use of names16. 674 (OP_LWP_E): Same. 675 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns 676 should not set the Vex.length bit. 677 * i386-tbl.h: Regenerated. 678 6792010-02-25 Edmar Wienskoski <edmar@freescale.com> 680 681 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64". 682 6832010-02-24 Nick Clifton <nickc@redhat.com> 684 685 PR binutils/6773 686 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with 687 <prefix>asx. Replace <prefix>subaddx with <prefix>sax. 688 (thumb32_opcodes): Likewise. 689 6902010-02-15 Nick Clifton <nickc@redhat.com> 691 692 * po/vi.po: Updated Vietnamese translation. 693 6942010-02-12 Doug Evans <dje@sebabeach.org> 695 696 * lm32-opinst.c: Regenerate. 697 6982010-02-11 Doug Evans <dje@sebabeach.org> 699 700 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL. 701 (print_address): Delete CGEN_PRINT_ADDRESS. 702 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c, 703 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h, 704 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c, 705 * xc16x-dis.c, * xstormy16-dis.c: Regenerate. 706 707 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c, 708 * frv-desc.c, * frv-desc.h, * frv-opc.c, 709 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c, 710 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c, 711 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c, 712 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c, 713 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c, 714 * mep-desc.c, * mep-desc.h, * mep-opc.c, 715 * mt-desc.c, * mt-desc.h, * mt-opc.c, 716 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c, 717 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c, 718 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate. 719 7202010-02-11 H.J. Lu <hongjiu.lu@intel.com> 721 722 * i386-dis.c: Update copyright. 723 * i386-gen.c: Likewise. 724 * i386-opc.h: Likewise. 725 * i386-opc.tbl: Likewise. 726 7272010-02-10 Quentin Neill <quentin.neill@amd.com> 728 Sebastian Pop <sebastian.pop@amd.com> 729 730 * i386-dis.c (OP_EX_VexImmW): Reintroduced 731 function to handle 5th imm8 operand. 732 (PREFIX_VEX_3A48): Added. 733 (PREFIX_VEX_3A49): Added. 734 (VEX_W_3A48_P_2): Added. 735 (VEX_W_3A49_P_2): Added. 736 (prefix table): Added entries for PREFIX_VEX_3A48 737 and PREFIX_VEX_3A49. 738 (vex table): Added entries for VEX_W_3A48_P_2 and 739 and VEX_W_3A49_P_2. 740 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4 741 for Vec_Imm4 operands. 742 * i386-opc.h (enum): Added Vec_Imm4. 743 (i386_operand_type): Added vec_imm4. 744 * i386-opc.tbl: Add entries for vpermilp[ds]. 745 * i386-init.h: Regenerated. 746 * i386-tbl.h: Regenerated. 747 7482010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com> 749 750 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6" 751 and "pwr7". Move "a2" into alphabetical order. 752 7532010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 754 755 * ppc-dis.c (ppc_opts): Add titan entry. 756 * ppc-opc.c (TITAN, MULHW): Define. 757 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx). 758 7592010-02-03 Quentin Neill <quentin.neill@amd.com> 760 761 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS 762 to CPU_BDVER1_FLAGS 763 * i386-init.h: Regenerated. 764 7652010-02-03 Anthony Green <green@moxielogic.com> 766 767 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to 768 0x0f, and make 0x00 an illegal instruction. 769 7702010-01-29 Daniel Jacobowitz <dan@codesourcery.com> 771 772 * opcodes/arm-dis.c (struct arm_private_data): New. 773 (print_insn_coprocessor, print_insn_arm): Update to use struct 774 arm_private_data. 775 (is_mapping_symbol, get_map_sym_type): New functions. 776 (get_sym_code_type): Check the symbol's section. Do not check 777 mapping symbols. 778 (print_insn): Default to disassembling ARM mode code. Check 779 for mapping symbols separately from other symbols. Use 780 struct arm_private_data. 781 7822010-01-28 H.J. Lu <hongjiu.lu@intel.com> 783 784 * i386-dis.c (EXVexWdqScalar): New. 785 (vex_scalar_w_dq_mode): Likewise. 786 (prefix_table): Update entries for PREFIX_VEX_3899, 787 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F, 788 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD, 789 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB, 790 PREFIX_VEX_38BD and PREFIX_VEX_38BF. 791 (intel_operand_size): Handle vex_scalar_w_dq_mode. 792 (OP_EX): Likewise. 793 7942010-01-27 H.J. Lu <hongjiu.lu@intel.com> 795 796 * i386-dis.c (XMScalar): New. 797 (EXdScalar): Likewise. 798 (EXqScalar): Likewise. 799 (EXqScalarS): Likewise. 800 (VexScalar): Likewise. 801 (EXdVexScalarS): Likewise. 802 (EXqVexScalarS): Likewise. 803 (XMVexScalar): Likewise. 804 (scalar_mode): Likewise. 805 (d_scalar_mode): Likewise. 806 (d_scalar_swap_mode): Likewise. 807 (q_scalar_mode): Likewise. 808 (q_scalar_swap_mode): Likewise. 809 (vex_scalar_mode): Likewise. 810 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1, 811 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1, 812 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0, 813 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3, 814 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3, 815 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1, 816 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1, 817 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2, 818 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1, 819 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2. 820 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3, 821 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2, 822 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3, 823 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3, 824 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3, 825 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3, 826 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3, 827 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3, 828 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2. 829 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode, 830 q_scalar_mode, q_scalar_swap_mode. 831 (OP_XMM): Handle scalar_mode. 832 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode 833 and q_scalar_swap_mode. 834 (OP_VEX): Handle vex_scalar_mode. 835 8362010-01-24 H.J. Lu <hongjiu.lu@intel.com> 837 838 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }. 839 8402010-01-24 H.J. Lu <hongjiu.lu@intel.com> 841 842 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }. 843 8442010-01-24 H.J. Lu <hongjiu.lu@intel.com> 845 846 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }. 847 8482010-01-24 H.J. Lu <hongjiu.lu@intel.com> 849 850 * i386-dis.c (Bad_Opcode): New. 851 (bad_opcode): Likewise. 852 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }. 853 (dis386_twobyte): Likewise. 854 (reg_table): Likewise. 855 (prefix_table): Likewise. 856 (x86_64_table): Likewise. 857 (vex_len_table): Likewise. 858 (vex_w_table): Likewise. 859 (mod_table): Likewise. 860 (rm_table): Likewise. 861 (float_reg): Likewise. 862 (reg_table): Remove trailing "(bad)" entries. 863 (prefix_table): Likewise. 864 (x86_64_table): Likewise. 865 (vex_len_table): Likewise. 866 (vex_w_table): Likewise. 867 (mod_table): Likewise. 868 (rm_table): Likewise. 869 (get_valid_dis386): Handle bytemode 0. 870 8712010-01-23 H.J. Lu <hongjiu.lu@intel.com> 872 873 * i386-opc.h (VEXScalar): New. 874 875 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar 876 instructions. 877 * i386-tbl.h: Regenerated. 878 8792010-01-21 H.J. Lu <hongjiu.lu@intel.com> 880 881 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor. 882 883 * i386-opc.tbl: Add xsave64 and xrstor64. 884 * i386-tbl.h: Regenerated. 885 8862010-01-20 Nick Clifton <nickc@redhat.com> 887 888 PR 11170 889 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC 890 based post-indexed addressing. 891 8922010-01-15 Sebastian Pop <sebastian.pop@amd.com> 893 894 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns. 895 * i386-tbl.h: Regenerated. 896 8972010-01-14 H.J. Lu <hongjiu.lu@intel.com> 898 899 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in 900 comments. 901 9022010-01-14 H.J. Lu <hongjiu.lu@intel.com> 903 904 * i386-dis.c (names_mm): New. 905 (intel_names_mm): Likewise. 906 (att_names_mm): Likewise. 907 (names_xmm): Likewise. 908 (intel_names_xmm): Likewise. 909 (att_names_xmm): Likewise. 910 (names_ymm): Likewise. 911 (intel_names_ymm): Likewise. 912 (att_names_ymm): Likewise. 913 (print_insn): Set names_mm, names_xmm and names_ymm. 914 (OP_MMX): Use names_mm, names_xmm and names_ymm. 915 (OP_XMM): Likewise. 916 (OP_EM): Likewise. 917 (OP_EMC): Likewise. 918 (OP_MXC): Likewise. 919 (OP_EX): Likewise. 920 (XMM_Fixup): Likewise. 921 (OP_VEX): Likewise. 922 (OP_EX_VexReg): Likewise. 923 (OP_Vex_2src): Likewise. 924 (OP_Vex_2src_1): Likewise. 925 (OP_Vex_2src_2): Likewise. 926 (OP_REG_VexI4): Likewise. 927 9282010-01-13 H.J. Lu <hongjiu.lu@intel.com> 929 930 * i386-dis.c (print_insn): Update comments. 931 9322010-01-12 H.J. Lu <hongjiu.lu@intel.com> 933 934 * i386-dis.c (rex_original): Removed. 935 (ckprefix): Remove rex_original. 936 (print_insn): Update comments. 937 9382010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> 939 940 * Makefile.in: Regenerate. 941 * configure: Regenerate. 942 9432010-01-07 Doug Evans <dje@sebabeach.org> 944 945 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup. 946 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, 947 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, 948 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, 949 * xstormy16-ibld.c: Regenerate. 950 9512010-01-06 Quentin Neill <quentin.neill@amd.com> 952 953 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS. 954 * i386-init.h: Regenerated. 955 9562010-01-06 Daniel Gutson <dgutson@codesourcery.com> 957 958 * arm-dis.c (print_insn): Fixed search for next symbol and data 959 dumping condition, and the initial mapping symbol state. 960 9612010-01-05 Doug Evans <dje@sebabeach.org> 962 963 * cgen-ibld.in: #include "cgen/basic-modes.h". 964 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, 965 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, 966 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, 967 * xstormy16-ibld.c: Regenerate. 968 9692010-01-04 Nick Clifton <nickc@redhat.com> 970 971 PR 11123 972 * arm-dis.c (print_insn_coprocessor): Initialise value. 973 9742010-01-04 Edmar Wienskoski <edmar@freescale.com> 975 976 * ppc-dis.c (ppc_opts): Add entry for "e500mc64". 977 9782010-01-02 Doug Evans <dje@sebabeach.org> 979 980 * cgen-asm.in: Update copyright year. 981 * cgen-dis.in: Update copyright year. 982 * cgen-ibld.in: Update copyright year. 983 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c, 984 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c, 985 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h, 986 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c, 987 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c, 988 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c, 989 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c, 990 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h, 991 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h, 992 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c, 993 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c, 994 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c, 995 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h, 996 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c, 997 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c, 998 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c, 999 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c, 1000 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c, 1001 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c, 1002 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c, 1003 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate. 1004 1005For older changes see ChangeLog-2009 1006 1007Local Variables: 1008mode: change-log 1009left-margin: 8 1010fill-column: 74 1011version-control: never 1012End: 1013