1 /* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 3 2003, 2004, 2005, 2008 4 Free Software Foundation, Inc. 5 Contributed by Ralph Campbell and OSF 6 Commented and modified by Ian Lance Taylor, Cygnus Support 7 8 This file is part of GDB, GAS, and the GNU binutils. 9 10 GDB, GAS, and the GNU binutils are free software; you can redistribute 11 them and/or modify them under the terms of the GNU General Public 12 License as published by the Free Software Foundation; either version 13 1, or (at your option) any later version. 14 15 GDB, GAS, and the GNU binutils are distributed in the hope that they 16 will be useful, but WITHOUT ANY WARRANTY; without even the implied 17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 18 the GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this file; see the file COPYING. If not, write to the Free 22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 23 24 #ifndef _MIPS_H_ 25 #define _MIPS_H_ 26 27 /* These are bit masks and shift counts to use to access the various 28 fields of an instruction. To retrieve the X field of an 29 instruction, use the expression 30 (i >> OP_SH_X) & OP_MASK_X 31 To set the same field (to j), use 32 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 33 34 Make sure you use fields that are appropriate for the instruction, 35 of course. 36 37 The 'i' format uses OP, RS, RT and IMMEDIATE. 38 39 The 'j' format uses OP and TARGET. 40 41 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 42 43 The 'b' format uses OP, RS, RT and DELTA. 44 45 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 46 47 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 48 49 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 50 breakpoint instruction are not defined; Kane says the breakpoint 51 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 52 only use ten bits). An optional two-operand form of break/sdbbp 53 allows the lower ten bits to be set too, and MIPS32 and later 54 architectures allow 20 bits to be set with a signal operand 55 (using CODE20). 56 57 The syscall instruction uses CODE20. 58 59 The general coprocessor instructions use COPZ. */ 60 61 #define OP_MASK_OP 0x3f 62 #define OP_SH_OP 26 63 #define OP_MASK_RS 0x1f 64 #define OP_SH_RS 21 65 #define OP_MASK_FR 0x1f 66 #define OP_SH_FR 21 67 #define OP_MASK_FMT 0x1f 68 #define OP_SH_FMT 21 69 #define OP_MASK_BCC 0x7 70 #define OP_SH_BCC 18 71 #define OP_MASK_CODE 0x3ff 72 #define OP_SH_CODE 16 73 #define OP_MASK_CODE2 0x3ff 74 #define OP_SH_CODE2 6 75 #define OP_MASK_RT 0x1f 76 #define OP_SH_RT 16 77 #define OP_MASK_FT 0x1f 78 #define OP_SH_FT 16 79 #define OP_MASK_CACHE 0x1f 80 #define OP_SH_CACHE 16 81 #define OP_MASK_RD 0x1f 82 #define OP_SH_RD 11 83 #define OP_MASK_FS 0x1f 84 #define OP_SH_FS 11 85 #define OP_MASK_PREFX 0x1f 86 #define OP_SH_PREFX 11 87 #define OP_MASK_CCC 0x7 88 #define OP_SH_CCC 8 89 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 90 #define OP_SH_CODE20 6 91 #define OP_MASK_SHAMT 0x1f 92 #define OP_SH_SHAMT 6 93 #define OP_MASK_FD 0x1f 94 #define OP_SH_FD 6 95 #define OP_MASK_TARGET 0x3ffffff 96 #define OP_SH_TARGET 0 97 #define OP_MASK_COPZ 0x1ffffff 98 #define OP_SH_COPZ 0 99 #define OP_MASK_IMMEDIATE 0xffff 100 #define OP_SH_IMMEDIATE 0 101 #define OP_MASK_DELTA 0xffff 102 #define OP_SH_DELTA 0 103 #define OP_MASK_FUNCT 0x3f 104 #define OP_SH_FUNCT 0 105 #define OP_MASK_SPEC 0x3f 106 #define OP_SH_SPEC 0 107 #define OP_SH_LOCC 8 /* FP condition code. */ 108 #define OP_SH_HICC 18 /* FP condition code. */ 109 #define OP_MASK_CC 0x7 110 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 111 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 112 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 113 #define OP_MASK_COP1SPEC 0xf 114 #define OP_MASK_COP1SCLR 0x4 115 #define OP_MASK_COP1CMP 0x3 116 #define OP_SH_COP1CMP 4 117 #define OP_SH_FORMAT 21 /* FP short format field. */ 118 #define OP_MASK_FORMAT 0x7 119 #define OP_SH_TRUE 16 120 #define OP_MASK_TRUE 0x1 121 #define OP_SH_GE 17 122 #define OP_MASK_GE 0x01 123 #define OP_SH_UNSIGNED 16 124 #define OP_MASK_UNSIGNED 0x1 125 #define OP_SH_HINT 16 126 #define OP_MASK_HINT 0x1f 127 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 128 #define OP_MASK_MMI 0x3f 129 #define OP_SH_MMISUB 6 130 #define OP_MASK_MMISUB 0x1f 131 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 132 #define OP_SH_PERFREG 1 133 #define OP_SH_SEL 0 /* Coprocessor select field. */ 134 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 135 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 136 #define OP_MASK_CODE19 0x7ffff 137 #define OP_SH_ALN 21 138 #define OP_MASK_ALN 0x7 139 #define OP_SH_VSEL 21 140 #define OP_MASK_VSEL 0x1f 141 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 142 but 0x8-0xf don't select bytes. */ 143 #define OP_SH_VECBYTE 22 144 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 145 #define OP_SH_VECALIGN 21 146 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 147 #define OP_SH_INSMSB 11 148 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 149 #define OP_SH_EXTMSBD 11 150 151 /* MIPS DSP ASE */ 152 #define OP_SH_DSPACC 11 153 #define OP_MASK_DSPACC 0x3 154 #define OP_SH_DSPACC_S 21 155 #define OP_MASK_DSPACC_S 0x3 156 #define OP_SH_DSPSFT 20 157 #define OP_MASK_DSPSFT 0x3f 158 #define OP_SH_DSPSFT_7 19 159 #define OP_MASK_DSPSFT_7 0x7f 160 #define OP_SH_SA3 21 161 #define OP_MASK_SA3 0x7 162 #define OP_SH_SA4 21 163 #define OP_MASK_SA4 0xf 164 #define OP_SH_IMM8 16 165 #define OP_MASK_IMM8 0xff 166 #define OP_SH_IMM10 16 167 #define OP_MASK_IMM10 0x3ff 168 #define OP_SH_WRDSP 11 169 #define OP_MASK_WRDSP 0x3f 170 #define OP_SH_RDDSP 16 171 #define OP_MASK_RDDSP 0x3f 172 #define OP_SH_BP 11 173 #define OP_MASK_BP 0x3 174 175 /* MIPS MT ASE */ 176 #define OP_SH_MT_U 5 177 #define OP_MASK_MT_U 0x1 178 #define OP_SH_MT_H 4 179 #define OP_MASK_MT_H 0x1 180 #define OP_SH_MTACC_T 18 181 #define OP_MASK_MTACC_T 0x3 182 #define OP_SH_MTACC_D 13 183 #define OP_MASK_MTACC_D 0x3 184 185 #define OP_OP_COP0 0x10 186 #define OP_OP_COP1 0x11 187 #define OP_OP_COP2 0x12 188 #define OP_OP_COP3 0x13 189 #define OP_OP_LWC1 0x31 190 #define OP_OP_LWC2 0x32 191 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 192 #define OP_OP_LDC1 0x35 193 #define OP_OP_LDC2 0x36 194 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 195 #define OP_OP_SWC1 0x39 196 #define OP_OP_SWC2 0x3a 197 #define OP_OP_SWC3 0x3b 198 #define OP_OP_SDC1 0x3d 199 #define OP_OP_SDC2 0x3e 200 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 201 202 /* Values in the 'VSEL' field. */ 203 #define MDMX_FMTSEL_IMM_QH 0x1d 204 #define MDMX_FMTSEL_IMM_OB 0x1e 205 #define MDMX_FMTSEL_VEC_QH 0x15 206 #define MDMX_FMTSEL_VEC_OB 0x16 207 208 /* UDI */ 209 #define OP_SH_UDI1 6 210 #define OP_MASK_UDI1 0x1f 211 #define OP_SH_UDI2 6 212 #define OP_MASK_UDI2 0x3ff 213 #define OP_SH_UDI3 6 214 #define OP_MASK_UDI3 0x7fff 215 #define OP_SH_UDI4 6 216 #define OP_MASK_UDI4 0xfffff 217 218 /* Octeon */ 219 #define OP_SH_BBITIND 16 220 #define OP_MASK_BBITIND 0x1f 221 #define OP_SH_CINSPOS 6 222 #define OP_MASK_CINSPOS 0x1f 223 #define OP_SH_CINSLM1 11 224 #define OP_MASK_CINSLM1 0x1f 225 #define OP_SH_SEQI 6 226 #define OP_MASK_SEQI 0x3ff 227 228 /* This structure holds information for a particular instruction. */ 229 230 struct mips_opcode 231 { 232 /* The name of the instruction. */ 233 const char *name; 234 /* A string describing the arguments for this instruction. */ 235 const char *args; 236 /* The basic opcode for the instruction. When assembling, this 237 opcode is modified by the arguments to produce the actual opcode 238 that is used. If pinfo is INSN_MACRO, then this is 0. */ 239 unsigned long match; 240 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 241 relevant portions of the opcode when disassembling. If the 242 actual opcode anded with the match field equals the opcode field, 243 then we have found the correct instruction. If pinfo is 244 INSN_MACRO, then this field is the macro identifier. */ 245 unsigned long mask; 246 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 247 of bits describing the instruction, notably any relevant hazard 248 information. */ 249 unsigned long pinfo; 250 /* A collection of additional bits describing the instruction. */ 251 unsigned long pinfo2; 252 /* A collection of bits describing the instruction sets of which this 253 instruction or macro is a member. */ 254 unsigned long membership; 255 }; 256 257 /* These are the characters which may appear in the args field of an 258 instruction. They appear in the order in which the fields appear 259 when the instruction is used. Commas and parentheses in the args 260 string are ignored when assembling, and written into the output 261 when disassembling. 262 263 Each of these characters corresponds to a mask field defined above. 264 265 "<" 5 bit shift amount (OP_*_SHAMT) 266 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 267 "a" 26 bit target address (OP_*_TARGET) 268 "b" 5 bit base register (OP_*_RS) 269 "c" 10 bit breakpoint code (OP_*_CODE) 270 "d" 5 bit destination register specifier (OP_*_RD) 271 "h" 5 bit prefx hint (OP_*_PREFX) 272 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 273 "j" 16 bit signed immediate (OP_*_DELTA) 274 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 275 Also used for immediate operands in vr5400 vector insns. 276 "o" 16 bit signed offset (OP_*_DELTA) 277 "p" 16 bit PC relative branch target address (OP_*_DELTA) 278 "q" 10 bit extra breakpoint code (OP_*_CODE2) 279 "r" 5 bit same register used as both source and target (OP_*_RS) 280 "s" 5 bit source register specifier (OP_*_RS) 281 "t" 5 bit target register (OP_*_RT) 282 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 283 "v" 5 bit same register used as both source and destination (OP_*_RS) 284 "w" 5 bit same register used as both target and destination (OP_*_RT) 285 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 286 (used by clo and clz) 287 "C" 25 bit coprocessor function code (OP_*_COPZ) 288 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 289 "J" 19 bit wait function code (OP_*_CODE19) 290 "x" accept and ignore register name 291 "z" must be zero register 292 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 293 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 294 LSB (OP_*_SHAMT). 295 Enforces: 0 <= pos < 32. 296 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 297 Requires that "+A" or "+E" occur first to set position. 298 Enforces: 0 < (pos+size) <= 32. 299 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 300 Requires that "+A" or "+E" occur first to set position. 301 Enforces: 0 < (pos+size) <= 32. 302 (Also used by "dext" w/ different limits, but limits for 303 that are checked by the M_DEXT macro.) 304 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 305 Enforces: 32 <= pos < 64. 306 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 307 Requires that "+A" or "+E" occur first to set position. 308 Enforces: 32 < (pos+size) <= 64. 309 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 310 Requires that "+A" or "+E" occur first to set position. 311 Enforces: 32 < (pos+size) <= 64. 312 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 313 Requires that "+A" or "+E" occur first to set position. 314 Enforces: 32 < (pos+size) <= 64. 315 316 Floating point instructions: 317 "D" 5 bit destination register (OP_*_FD) 318 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 319 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 320 "S" 5 bit fs source 1 register (OP_*_FS) 321 "T" 5 bit ft source 2 register (OP_*_FT) 322 "R" 5 bit fr source 3 register (OP_*_FR) 323 "V" 5 bit same register used as floating source and destination (OP_*_FS) 324 "W" 5 bit same register used as floating target and destination (OP_*_FT) 325 326 Coprocessor instructions: 327 "E" 5 bit target register (OP_*_RT) 328 "G" 5 bit destination register (OP_*_RD) 329 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 330 "P" 5 bit performance-monitor register (OP_*_PERFREG) 331 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 332 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 333 see also "k" above 334 "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 335 for pretty-printing in disassembly only. 336 337 Macro instructions: 338 "A" General 32 bit expression 339 "I" 32 bit immediate (value placed in imm_expr). 340 "+I" 32 bit immediate (value placed in imm2_expr). 341 "F" 64 bit floating point constant in .rdata 342 "L" 64 bit floating point constant in .lit8 343 "f" 32 bit floating point constant 344 "l" 32 bit floating point constant in .lit4 345 346 MDMX instruction operands (note that while these use the FP register 347 fields, they accept both $fN and $vN names for the registers): 348 "O" MDMX alignment offset (OP_*_ALN) 349 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 350 "X" MDMX destination register (OP_*_FD) 351 "Y" MDMX source register (OP_*_FS) 352 "Z" MDMX source register (OP_*_FT) 353 354 DSP ASE usage: 355 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 356 "3" 3 bit unsigned immediate (OP_*_SA3) 357 "4" 4 bit unsigned immediate (OP_*_SA4) 358 "5" 8 bit unsigned immediate (OP_*_IMM8) 359 "6" 5 bit unsigned immediate (OP_*_RS) 360 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 361 "8" 6 bit unsigned immediate (OP_*_WRDSP) 362 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 363 "0" 6 bit signed immediate (OP_*_DSPSFT) 364 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 365 "'" 6 bit unsigned immediate (OP_*_RDDSP) 366 "@" 10 bit signed immediate (OP_*_IMM10) 367 368 MT ASE usage: 369 "!" 1 bit usermode flag (OP_*_MT_U) 370 "$" 1 bit load high flag (OP_*_MT_H) 371 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 372 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 373 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 374 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 375 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only 376 377 UDI immediates: 378 "+1" UDI immediate bits 6-10 379 "+2" UDI immediate bits 6-15 380 "+3" UDI immediate bits 6-20 381 "+4" UDI immediate bits 6-25 382 383 Octeon: 384 "+x" Bit index field of bbit. Enforces: 0 <= index < 32. 385 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, 386 otherwise skips to next candidate. 387 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. 388 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if 389 32 <= pos < 64, otherwise skips to next candidate. 390 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. 391 "+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32. 392 "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing 393 cint32/exts32. Enforces non-negative value and that 394 pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous 395 position field is "+p" or "+P". 396 397 Other: 398 "()" parens surrounding optional value 399 "," separates operands 400 "[]" brackets around index for vector-op scalar operand specifier (vr5400) 401 "+" Start of extension sequence. 402 403 Characters used so far, for quick reference when adding more: 404 "234567890" 405 "%[]<>(),+:'@!$*&" 406 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 407 "abcdefghijklopqrstuvwxz" 408 409 Extension character sequences used so far ("+" followed by the 410 following), for quick reference when adding more: 411 "1234" 412 "ABCDEFGHIPQSTX" 413 "pstx" 414 */ 415 416 /* These are the bits which may be set in the pinfo field of an 417 instructions, if it is not equal to INSN_MACRO. */ 418 419 /* Modifies the general purpose register in OP_*_RD. */ 420 #define INSN_WRITE_GPR_D 0x00000001 421 /* Modifies the general purpose register in OP_*_RT. */ 422 #define INSN_WRITE_GPR_T 0x00000002 423 /* Modifies general purpose register 31. */ 424 #define INSN_WRITE_GPR_31 0x00000004 425 /* Modifies the floating point register in OP_*_FD. */ 426 #define INSN_WRITE_FPR_D 0x00000008 427 /* Modifies the floating point register in OP_*_FS. */ 428 #define INSN_WRITE_FPR_S 0x00000010 429 /* Modifies the floating point register in OP_*_FT. */ 430 #define INSN_WRITE_FPR_T 0x00000020 431 /* Reads the general purpose register in OP_*_RS. */ 432 #define INSN_READ_GPR_S 0x00000040 433 /* Reads the general purpose register in OP_*_RT. */ 434 #define INSN_READ_GPR_T 0x00000080 435 /* Reads the floating point register in OP_*_FS. */ 436 #define INSN_READ_FPR_S 0x00000100 437 /* Reads the floating point register in OP_*_FT. */ 438 #define INSN_READ_FPR_T 0x00000200 439 /* Reads the floating point register in OP_*_FR. */ 440 #define INSN_READ_FPR_R 0x00000400 441 /* Modifies coprocessor condition code. */ 442 #define INSN_WRITE_COND_CODE 0x00000800 443 /* Reads coprocessor condition code. */ 444 #define INSN_READ_COND_CODE 0x00001000 445 /* TLB operation. */ 446 #define INSN_TLB 0x00002000 447 /* Reads coprocessor register other than floating point register. */ 448 #define INSN_COP 0x00004000 449 /* Instruction loads value from memory, requiring delay. */ 450 #define INSN_LOAD_MEMORY_DELAY 0x00008000 451 /* Instruction loads value from coprocessor, requiring delay. */ 452 #define INSN_LOAD_COPROC_DELAY 0x00010000 453 /* Instruction has unconditional branch delay slot. */ 454 #define INSN_UNCOND_BRANCH_DELAY 0x00020000 455 /* Instruction has conditional branch delay slot. */ 456 #define INSN_COND_BRANCH_DELAY 0x00040000 457 /* Conditional branch likely: if branch not taken, insn nullified. */ 458 #define INSN_COND_BRANCH_LIKELY 0x00080000 459 /* Moves to coprocessor register, requiring delay. */ 460 #define INSN_COPROC_MOVE_DELAY 0x00100000 461 /* Loads coprocessor register from memory, requiring delay. */ 462 #define INSN_COPROC_MEMORY_DELAY 0x00200000 463 /* Reads the HI register. */ 464 #define INSN_READ_HI 0x00400000 465 /* Reads the LO register. */ 466 #define INSN_READ_LO 0x00800000 467 /* Modifies the HI register. */ 468 #define INSN_WRITE_HI 0x01000000 469 /* Modifies the LO register. */ 470 #define INSN_WRITE_LO 0x02000000 471 /* Takes a trap (easier to keep out of delay slot). */ 472 #define INSN_TRAP 0x04000000 473 /* Instruction stores value into memory. */ 474 #define INSN_STORE_MEMORY 0x08000000 475 /* Instruction uses single precision floating point. */ 476 #define FP_S 0x10000000 477 /* Instruction uses double precision floating point. */ 478 #define FP_D 0x20000000 479 /* Instruction is part of the tx39's integer multiply family. */ 480 #define INSN_MULT 0x40000000 481 /* Instruction synchronize shared memory. */ 482 #define INSN_SYNC 0x80000000 483 /* Instruction is actually a macro. It should be ignored by the 484 disassembler, and requires special treatment by the assembler. */ 485 #define INSN_MACRO 0xffffffff 486 487 /* These are the bits which may be set in the pinfo2 field of an 488 instruction. */ 489 490 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 491 #define INSN2_ALIAS 0x00000001 492 /* Instruction reads MDMX accumulator. */ 493 #define INSN2_READ_MDMX_ACC 0x00000002 494 /* Instruction writes MDMX accumulator. */ 495 #define INSN2_WRITE_MDMX_ACC 0x00000004 496 /* Macro uses single-precision floating-point instructions. This should 497 only be set for macros. For instructions, FP_S in pinfo carries the 498 same information. */ 499 #define INSN2_M_FP_S 0x00000008 500 /* Macro uses double-precision floating-point instructions. This should 501 only be set for macros. For instructions, FP_D in pinfo carries the 502 same information. */ 503 #define INSN2_M_FP_D 0x00000010 504 505 /* Masks used to mark instructions to indicate which MIPS ISA level 506 they were introduced in. INSN_ISA_MASK masks an enumeration that 507 specifies the base ISA level(s). The remainder of a 32-bit 508 word constructed using these macros is a bitmask of the remaining 509 INSN_* values below. */ 510 511 #define INSN_ISA_MASK 0x0000000ful 512 513 /* We cannot start at zero due to ISA_UNKNOWN below. */ 514 #define INSN_ISA1 1 515 #define INSN_ISA2 2 516 #define INSN_ISA3 3 517 #define INSN_ISA4 4 518 #define INSN_ISA5 5 519 #define INSN_ISA32 6 520 #define INSN_ISA32R2 7 521 #define INSN_ISA64 8 522 #define INSN_ISA64R2 9 523 /* Below this point the INSN_* values correspond to combinations of ISAs. 524 They are only for use in the opcodes table to indicate membership of 525 a combination of ISAs that cannot be expressed using the usual inclusion 526 ordering on the above INSN_* values. */ 527 #define INSN_ISA3_32 10 528 #define INSN_ISA3_32R2 11 529 #define INSN_ISA4_32 12 530 #define INSN_ISA4_32R2 13 531 #define INSN_ISA5_32R2 14 532 533 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through 534 INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, 535 this table describes whether at least one of the ISAs described by X 536 is/are implemented by ISA Y. (Think of Y as the ISA level supported by 537 a particular core and X as the ISA level(s) at which a certain instruction 538 is defined.) The ISA(s) described by X is/are implemented by Y iff 539 (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 540 is non-zero. */ 541 static const unsigned int mips_isa_table[] = 542 { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; 543 544 /* Masks used for Chip specific instructions. */ 545 #define INSN_CHIP_MASK 0xc3ff0820 546 547 /* Cavium Networks Octeon instructions. */ 548 #define INSN_OCTEON 0x00000800 549 550 /* Masks used for MIPS-defined ASEs. */ 551 #define INSN_ASE_MASK 0x3c00f000 552 553 /* DSP ASE */ 554 #define INSN_DSP 0x00001000 555 #define INSN_DSP64 0x00002000 556 /* MIPS 16 ASE */ 557 #define INSN_MIPS16 0x00004000 558 /* MIPS-3D ASE */ 559 #define INSN_MIPS3D 0x00008000 560 561 /* MIPS R4650 instruction. */ 562 #define INSN_4650 0x00010000 563 /* LSI R4010 instruction. */ 564 #define INSN_4010 0x00020000 565 /* NEC VR4100 instruction. */ 566 #define INSN_4100 0x00040000 567 /* Toshiba R3900 instruction. */ 568 #define INSN_3900 0x00080000 569 /* MIPS R10000 instruction. */ 570 #define INSN_10000 0x00100000 571 /* Broadcom SB-1 instruction. */ 572 #define INSN_SB1 0x00200000 573 /* NEC VR4111/VR4181 instruction. */ 574 #define INSN_4111 0x00400000 575 /* NEC VR4120 instruction. */ 576 #define INSN_4120 0x00800000 577 /* NEC VR5400 instruction. */ 578 #define INSN_5400 0x01000000 579 /* NEC VR5500 instruction. */ 580 #define INSN_5500 0x02000000 581 582 /* MDMX ASE */ 583 #define INSN_MDMX 0x04000000 584 /* MT ASE */ 585 #define INSN_MT 0x08000000 586 /* SmartMIPS ASE */ 587 #define INSN_SMARTMIPS 0x10000000 588 /* DSP R2 ASE */ 589 #define INSN_DSPR2 0x20000000 590 /* ST Microelectronics Loongson 2E. */ 591 #define INSN_LOONGSON_2E 0x40000000 592 /* ST Microelectronics Loongson 2F. */ 593 #define INSN_LOONGSON_2F 0x80000000 594 /* RMI Xlr instruction */ 595 #define INSN_XLR 0x00000020 596 597 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 598 599 #define ISA_UNKNOWN 0 /* Gas internal use. */ 600 #define ISA_MIPS1 INSN_ISA1 601 #define ISA_MIPS2 INSN_ISA2 602 #define ISA_MIPS3 INSN_ISA3 603 #define ISA_MIPS4 INSN_ISA4 604 #define ISA_MIPS5 INSN_ISA5 605 606 #define ISA_MIPS32 INSN_ISA32 607 #define ISA_MIPS64 INSN_ISA64 608 609 #define ISA_MIPS32R2 INSN_ISA32R2 610 #define ISA_MIPS64R2 INSN_ISA64R2 611 612 613 /* CPU defines, use instead of hardcoding processor number. Keep this 614 in sync with bfd/archures.c in order for machine selection to work. */ 615 #define CPU_UNKNOWN 0 /* Gas internal use. */ 616 #define CPU_R3000 3000 617 #define CPU_R3900 3900 618 #define CPU_R4000 4000 619 #define CPU_R4010 4010 620 #define CPU_VR4100 4100 621 #define CPU_R4111 4111 622 #define CPU_VR4120 4120 623 #define CPU_R4300 4300 624 #define CPU_R4400 4400 625 #define CPU_R4600 4600 626 #define CPU_R4650 4650 627 #define CPU_R5000 5000 628 #define CPU_VR5400 5400 629 #define CPU_VR5500 5500 630 #define CPU_R6000 6000 631 #define CPU_RM7000 7000 632 #define CPU_R8000 8000 633 #define CPU_RM9000 9000 634 #define CPU_R10000 10000 635 #define CPU_R12000 12000 636 #define CPU_MIPS16 16 637 #define CPU_MIPS32 32 638 #define CPU_MIPS32R2 33 639 #define CPU_MIPS5 5 640 #define CPU_MIPS64 64 641 #define CPU_MIPS64R2 65 642 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 643 #define CPU_LOONGSON_2E 3001 644 #define CPU_LOONGSON_2F 3002 645 #define CPU_OCTEON 6501 646 #define CPU_XLR 887682 /* decimal 'XLR' */ 647 648 /* Test for membership in an ISA including chip specific ISAs. INSN 649 is pointer to an element of the opcode table; ISA is the specified 650 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 651 test, or zero if no CPU specific ISA test is desired. */ 652 653 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 654 (((isa & INSN_ISA_MASK) != 0 \ 655 && ((insn)->membership & INSN_ISA_MASK) != 0 \ 656 && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \ 657 (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \ 658 || ((isa & ~INSN_ISA_MASK) \ 659 & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \ 660 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ 661 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ 662 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ 663 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ 664 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ 665 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ 666 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ 667 && ((insn)->membership & INSN_10000) != 0) \ 668 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ 669 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ 670 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ 671 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ 672 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ 673 || (cpu == CPU_LOONGSON_2E \ 674 && ((insn)->membership & INSN_LOONGSON_2E) != 0) \ 675 || (cpu == CPU_LOONGSON_2F \ 676 && ((insn)->membership & INSN_LOONGSON_2F) != 0) \ 677 || (cpu == CPU_OCTEON \ 678 && ((insn)->membership & INSN_OCTEON) != 0) \ 679 || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ 680 || 0) /* Please keep this term for easier source merging. */ 681 682 /* This is a list of macro expanded instructions. 683 684 _I appended means immediate 685 _A appended means address 686 _AB appended means address with base register 687 _D appended means 64 bit floating point constant 688 _S appended means 32 bit floating point constant. */ 689 690 enum 691 { 692 M_ABS, 693 M_ADD_I, 694 M_ADDU_I, 695 M_AND_I, 696 M_BALIGN, 697 M_BEQ, 698 M_BEQ_I, 699 M_BEQL_I, 700 M_BGE, 701 M_BGEL, 702 M_BGE_I, 703 M_BGEL_I, 704 M_BGEU, 705 M_BGEUL, 706 M_BGEU_I, 707 M_BGEUL_I, 708 M_BGT, 709 M_BGTL, 710 M_BGT_I, 711 M_BGTL_I, 712 M_BGTU, 713 M_BGTUL, 714 M_BGTU_I, 715 M_BGTUL_I, 716 M_BLE, 717 M_BLEL, 718 M_BLE_I, 719 M_BLEL_I, 720 M_BLEU, 721 M_BLEUL, 722 M_BLEU_I, 723 M_BLEUL_I, 724 M_BLT, 725 M_BLTL, 726 M_BLT_I, 727 M_BLTL_I, 728 M_BLTU, 729 M_BLTUL, 730 M_BLTU_I, 731 M_BLTUL_I, 732 M_BNE, 733 M_BNE_I, 734 M_BNEL_I, 735 M_CACHE_AB, 736 M_DABS, 737 M_DADD_I, 738 M_DADDU_I, 739 M_DDIV_3, 740 M_DDIV_3I, 741 M_DDIVU_3, 742 M_DDIVU_3I, 743 M_DEXT, 744 M_DINS, 745 M_DIV_3, 746 M_DIV_3I, 747 M_DIVU_3, 748 M_DIVU_3I, 749 M_DLA_AB, 750 M_DLCA_AB, 751 M_DLI, 752 M_DMUL, 753 M_DMUL_I, 754 M_DMULO, 755 M_DMULO_I, 756 M_DMULOU, 757 M_DMULOU_I, 758 M_DREM_3, 759 M_DREM_3I, 760 M_DREMU_3, 761 M_DREMU_3I, 762 M_DSUB_I, 763 M_DSUBU_I, 764 M_DSUBU_I_2, 765 M_J_A, 766 M_JAL_1, 767 M_JAL_2, 768 M_JAL_A, 769 M_L_DOB, 770 M_L_DAB, 771 M_LA_AB, 772 M_LB_A, 773 M_LB_AB, 774 M_LBU_A, 775 M_LBU_AB, 776 M_LCA_AB, 777 M_LD_A, 778 M_LD_OB, 779 M_LD_AB, 780 M_LDC1_AB, 781 M_LDC2_AB, 782 M_LDC3_AB, 783 M_LDL_AB, 784 M_LDR_AB, 785 M_LH_A, 786 M_LH_AB, 787 M_LHU_A, 788 M_LHU_AB, 789 M_LI, 790 M_LI_D, 791 M_LI_DD, 792 M_LI_S, 793 M_LI_SS, 794 M_LL_AB, 795 M_LLD_AB, 796 M_LS_A, 797 M_LW_A, 798 M_LW_AB, 799 M_LWC0_A, 800 M_LWC0_AB, 801 M_LWC1_A, 802 M_LWC1_AB, 803 M_LWC2_A, 804 M_LWC2_AB, 805 M_LWC3_A, 806 M_LWC3_AB, 807 M_LWL_A, 808 M_LWL_AB, 809 M_LWR_A, 810 M_LWR_AB, 811 M_LWU_AB, 812 M_MSGSND, 813 M_MSGLD, 814 M_MSGLD_T, 815 M_MSGWAIT, 816 M_MSGWAIT_T, 817 M_MOVE, 818 M_MUL, 819 M_MUL_I, 820 M_MULO, 821 M_MULO_I, 822 M_MULOU, 823 M_MULOU_I, 824 M_NOR_I, 825 M_OR_I, 826 M_REM_3, 827 M_REM_3I, 828 M_REMU_3, 829 M_REMU_3I, 830 M_DROL, 831 M_ROL, 832 M_DROL_I, 833 M_ROL_I, 834 M_DROR, 835 M_ROR, 836 M_DROR_I, 837 M_ROR_I, 838 M_S_DA, 839 M_S_DOB, 840 M_S_DAB, 841 M_S_S, 842 M_SC_AB, 843 M_SCD_AB, 844 M_SD_A, 845 M_SD_OB, 846 M_SD_AB, 847 M_SDC1_AB, 848 M_SDC2_AB, 849 M_SDC3_AB, 850 M_SDL_AB, 851 M_SDR_AB, 852 M_SEQ, 853 M_SEQ_I, 854 M_SGE, 855 M_SGE_I, 856 M_SGEU, 857 M_SGEU_I, 858 M_SGT, 859 M_SGT_I, 860 M_SGTU, 861 M_SGTU_I, 862 M_SLE, 863 M_SLE_I, 864 M_SLEU, 865 M_SLEU_I, 866 M_SLT_I, 867 M_SLTU_I, 868 M_SNE, 869 M_SNE_I, 870 M_SB_A, 871 M_SB_AB, 872 M_SH_A, 873 M_SH_AB, 874 M_SW_A, 875 M_SW_AB, 876 M_SWC0_A, 877 M_SWC0_AB, 878 M_SWC1_A, 879 M_SWC1_AB, 880 M_SWC2_A, 881 M_SWC2_AB, 882 M_SWC3_A, 883 M_SWC3_AB, 884 M_SWL_A, 885 M_SWL_AB, 886 M_SWR_A, 887 M_SWR_AB, 888 M_SUB_I, 889 M_SUBU_I, 890 M_SUBU_I_2, 891 M_TEQ_I, 892 M_TGE_I, 893 M_TGEU_I, 894 M_TLT_I, 895 M_TLTU_I, 896 M_TNE_I, 897 M_TRUNCWD, 898 M_TRUNCWS, 899 M_ULD, 900 M_ULD_A, 901 M_ULH, 902 M_ULH_A, 903 M_ULHU, 904 M_ULHU_A, 905 M_ULW, 906 M_ULW_A, 907 M_USH, 908 M_USH_A, 909 M_USW, 910 M_USW_A, 911 M_USD, 912 M_USD_A, 913 M_XOR_I, 914 M_COP0, 915 M_COP1, 916 M_COP2, 917 M_COP3, 918 M_NUM_MACROS 919 }; 920 921 922 /* The order of overloaded instructions matters. Label arguments and 923 register arguments look the same. Instructions that can have either 924 for arguments must apear in the correct order in this table for the 925 assembler to pick the right one. In other words, entries with 926 immediate operands must apear after the same instruction with 927 registers. 928 929 Many instructions are short hand for other instructions (i.e., The 930 jal <register> instruction is short for jalr <register>). */ 931 932 extern const struct mips_opcode mips_builtin_opcodes[]; 933 extern const int bfd_mips_num_builtin_opcodes; 934 extern struct mips_opcode *mips_opcodes; 935 extern int bfd_mips_num_opcodes; 936 #define NUMOPCODES bfd_mips_num_opcodes 937 938 939 /* The rest of this file adds definitions for the mips16 TinyRISC 940 processor. */ 941 942 /* These are the bitmasks and shift counts used for the different 943 fields in the instruction formats. Other than OP, no masks are 944 provided for the fixed portions of an instruction, since they are 945 not needed. 946 947 The I format uses IMM11. 948 949 The RI format uses RX and IMM8. 950 951 The RR format uses RX, and RY. 952 953 The RRI format uses RX, RY, and IMM5. 954 955 The RRR format uses RX, RY, and RZ. 956 957 The RRI_A format uses RX, RY, and IMM4. 958 959 The SHIFT format uses RX, RY, and SHAMT. 960 961 The I8 format uses IMM8. 962 963 The I8_MOVR32 format uses RY and REGR32. 964 965 The IR_MOV32R format uses REG32R and MOV32Z. 966 967 The I64 format uses IMM8. 968 969 The RI64 format uses RY and IMM5. 970 */ 971 972 #define MIPS16OP_MASK_OP 0x1f 973 #define MIPS16OP_SH_OP 11 974 #define MIPS16OP_MASK_IMM11 0x7ff 975 #define MIPS16OP_SH_IMM11 0 976 #define MIPS16OP_MASK_RX 0x7 977 #define MIPS16OP_SH_RX 8 978 #define MIPS16OP_MASK_IMM8 0xff 979 #define MIPS16OP_SH_IMM8 0 980 #define MIPS16OP_MASK_RY 0x7 981 #define MIPS16OP_SH_RY 5 982 #define MIPS16OP_MASK_IMM5 0x1f 983 #define MIPS16OP_SH_IMM5 0 984 #define MIPS16OP_MASK_RZ 0x7 985 #define MIPS16OP_SH_RZ 2 986 #define MIPS16OP_MASK_IMM4 0xf 987 #define MIPS16OP_SH_IMM4 0 988 #define MIPS16OP_MASK_REGR32 0x1f 989 #define MIPS16OP_SH_REGR32 0 990 #define MIPS16OP_MASK_REG32R 0x1f 991 #define MIPS16OP_SH_REG32R 3 992 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 993 #define MIPS16OP_MASK_MOVE32Z 0x7 994 #define MIPS16OP_SH_MOVE32Z 0 995 #define MIPS16OP_MASK_IMM6 0x3f 996 #define MIPS16OP_SH_IMM6 5 997 998 /* These are the characters which may appears in the args field of a MIPS16 999 instruction. They appear in the order in which the fields appear when the 1000 instruction is used. Commas and parentheses in the args string are ignored 1001 when assembling, and written into the output when disassembling. 1002 1003 "y" 3 bit register (MIPS16OP_*_RY) 1004 "x" 3 bit register (MIPS16OP_*_RX) 1005 "z" 3 bit register (MIPS16OP_*_RZ) 1006 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 1007 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 1008 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 1009 "0" zero register ($0) 1010 "S" stack pointer ($sp or $29) 1011 "P" program counter 1012 "R" return address register ($ra or $31) 1013 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 1014 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 1015 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 1016 "a" 26 bit jump address 1017 "e" 11 bit extension value 1018 "l" register list for entry instruction 1019 "L" register list for exit instruction 1020 1021 The remaining codes may be extended. Except as otherwise noted, 1022 the full extended operand is a 16 bit signed value. 1023 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 1024 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 1025 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 1026 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 1027 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 1028 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 1029 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 1030 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 1031 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 1032 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 1033 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 1034 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 1035 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 1036 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 1037 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 1038 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 1039 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 1040 "q" 11 bit branch address (MIPS16OP_*_IMM11) 1041 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 1042 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 1043 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 1044 "m" 7 bit register list for save instruction (18 bit extended) 1045 "M" 7 bit register list for restore instruction (18 bit extended) 1046 */ 1047 1048 /* Save/restore encoding for the args field when all 4 registers are 1049 either saved as arguments or saved/restored as statics. */ 1050 #define MIPS16_ALL_ARGS 0xe 1051 #define MIPS16_ALL_STATICS 0xb 1052 1053 /* For the mips16, we use the same opcode table format and a few of 1054 the same flags. However, most of the flags are different. */ 1055 1056 /* Modifies the register in MIPS16OP_*_RX. */ 1057 #define MIPS16_INSN_WRITE_X 0x00000001 1058 /* Modifies the register in MIPS16OP_*_RY. */ 1059 #define MIPS16_INSN_WRITE_Y 0x00000002 1060 /* Modifies the register in MIPS16OP_*_RZ. */ 1061 #define MIPS16_INSN_WRITE_Z 0x00000004 1062 /* Modifies the T ($24) register. */ 1063 #define MIPS16_INSN_WRITE_T 0x00000008 1064 /* Modifies the SP ($29) register. */ 1065 #define MIPS16_INSN_WRITE_SP 0x00000010 1066 /* Modifies the RA ($31) register. */ 1067 #define MIPS16_INSN_WRITE_31 0x00000020 1068 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 1069 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 1070 /* Reads the register in MIPS16OP_*_RX. */ 1071 #define MIPS16_INSN_READ_X 0x00000080 1072 /* Reads the register in MIPS16OP_*_RY. */ 1073 #define MIPS16_INSN_READ_Y 0x00000100 1074 /* Reads the register in MIPS16OP_*_MOVE32Z. */ 1075 #define MIPS16_INSN_READ_Z 0x00000200 1076 /* Reads the T ($24) register. */ 1077 #define MIPS16_INSN_READ_T 0x00000400 1078 /* Reads the SP ($29) register. */ 1079 #define MIPS16_INSN_READ_SP 0x00000800 1080 /* Reads the RA ($31) register. */ 1081 #define MIPS16_INSN_READ_31 0x00001000 1082 /* Reads the program counter. */ 1083 #define MIPS16_INSN_READ_PC 0x00002000 1084 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ 1085 #define MIPS16_INSN_READ_GPR_X 0x00004000 1086 /* Is a branch insn. */ 1087 #define MIPS16_INSN_BRANCH 0x00010000 1088 1089 /* The following flags have the same value for the mips16 opcode 1090 table: 1091 INSN_UNCOND_BRANCH_DELAY 1092 INSN_COND_BRANCH_DELAY 1093 INSN_COND_BRANCH_LIKELY (never used) 1094 INSN_READ_HI 1095 INSN_READ_LO 1096 INSN_WRITE_HI 1097 INSN_WRITE_LO 1098 INSN_TRAP 1099 INSN_ISA3 1100 */ 1101 1102 extern const struct mips_opcode mips16_opcodes[]; 1103 extern const int bfd_mips16_num_opcodes; 1104 1105 #endif /* _MIPS_H_ */ 1106